From 2cb1511602db820f8fe77c6aadebd5583fe78bc7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 11:59:41 +0200 Subject: [PATCH 001/268] arch/nrf91: fix broken modem initialization fix broken modem initialization for nrf91 Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_os.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm/src/nrf91/nrf91_modem_os.c b/arch/arm/src/nrf91/nrf91_modem_os.c index 940befab047..cabb4ebe696 100644 --- a/arch/arm/src/nrf91/nrf91_modem_os.c +++ b/arch/arm/src/nrf91/nrf91_modem_os.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -266,7 +267,6 @@ int32_t nrf_modem_os_timedwait(uint32_t context, int32_t *timeout) { struct nrf91_modem_os_waiting_s *waiting = NULL; struct timespec ts_now; - struct timespec abstime; int32_t remaining = 0; int32_t diff = 0; int ret = -EAGAIN; @@ -307,12 +307,12 @@ int32_t nrf_modem_os_timedwait(uint32_t context, int32_t *timeout) } else { - /* Wait for event or timeout */ + /* Wait for event or timeout (relative timeout in milliseconds). + * Capture the return value so a posted event is reported as success + * instead of a timeout. + */ - abstime.tv_sec = *timeout / 1000; - abstime.tv_nsec = (*timeout % 1000) * 1000000; - - nxsem_timedwait(&waiting->sem, &abstime); + ret = nxsem_tickwait(&waiting->sem, MSEC2TICK(*timeout)); } /* Free a waiting slot */ @@ -477,12 +477,9 @@ int nrf_modem_os_sem_take(void *sem, int timeout) } else { - struct timespec abstime; + /* Relative timeout in milliseconds. */ - abstime.tv_sec = timeout / 1000; - abstime.tv_nsec = (timeout % 1000) * 1000000; - - ret = nxsem_timedwait(s, &abstime); + ret = nxsem_tickwait(s, MSEC2TICK(timeout)); } return ret; From af371bbaa5c3b670ae3fc211bfaab1c4b45b5b4a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 5 Jun 2026 11:59:59 +0200 Subject: [PATCH 002/268] arch/nrf91: add more ioctl calls for modem socket add support for these ioctl: - LTE_CMDID_RADIOON - LTE_CMDID_RADIOOFF - LTE_CMDID_ACTPDN Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_sock.c | 159 ++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) diff --git a/arch/arm/src/nrf91/nrf91_modem_sock.c b/arch/arm/src/nrf91/nrf91_modem_sock.c index e6d260e6642..c85557e32d2 100644 --- a/arch/arm/src/nrf91/nrf91_modem_sock.c +++ b/arch/arm/src/nrf91/nrf91_modem_sock.c @@ -474,6 +474,138 @@ static int nrf91_modem_getver(lte_version_t *version) return ret; } +/**************************************************************************** + * Name: nrf91_modem_actpdn + * + * Description: + * Activate the default packet data network: optionally (re)configure the + * APN, attach to the network (AT+CFUN=1), wait for registration and read + * the assigned IP address. + * + ****************************************************************************/ + +static int nrf91_modem_actpdn(FAR lte_apn_setting_t *apn, + FAR lte_pdn_t *pdn) +{ + FAR const char *pdptype = "IP"; + char resp[64]; + FAR char *p; + FAR char *q; + size_t n; + int stat = 0; + int tmp = 0; + int elapsed = 0; + int ret; + + switch (apn->ip_type) + { + case LTE_IPTYPE_V6: + pdptype = "IPV6"; + break; + case LTE_IPTYPE_V4V6: + pdptype = "IPV4V6"; + break; + default: + pdptype = "IP"; + break; + } + + /* (Re)configure the default PDN context when an APN is provided. Toggle + * the radio off first so the new context is used on (re)attach. + */ + + if (apn->apn != NULL && apn->apn[0] != '\0') + { + nrf_modem_at_printf("AT+CFUN=4"); + + ret = nrf_modem_at_printf("AT+CGDCONT=0,\"%s\",\"%s\"", + pdptype, apn->apn); + if (ret < 0) + { + nerr("AT+CGDCONT failed %d\n", ret); + return ret; + } + + if (apn->auth_type != LTE_APN_AUTHTYPE_NONE && + apn->user_name != NULL && apn->password != NULL) + { + ret = nrf_modem_at_printf("AT+CGAUTH=0,%u,\"%s\",\"%s\"", + (unsigned)apn->auth_type, + apn->user_name, apn->password); + if (ret < 0) + { + nerr("AT+CGAUTH failed %d\n", ret); + return ret; + } + } + } + + /* Attach to the network */ + + ret = nrf_modem_at_printf("AT+CFUN=1"); + if (ret < 0) + { + nerr("AT+CFUN=1 failed %d\n", ret); + return ret; + } + + /* Wait for network registration (1 = home, 5 = roaming) */ + + while (elapsed < 120) + { + ret = nrf_modem_at_scanf("AT+CEREG?", "+CEREG: %d,%d", &tmp, &stat); + if (ret >= 2 && (stat == 1 || stat == 5)) + { + break; + } + + nxsig_usleep(1000 * 1000); + elapsed++; + } + + if (stat != 1 && stat != 5) + { + nerr("LTE registration timed out, CEREG stat=%d\n", stat); + return -ETIMEDOUT; + } + + /* Fill the PDN info and read the assigned IP address from + * "+CGPADDR: 0,\"a.b.c.d\"". + */ + + memset(pdn, 0, sizeof(*pdn)); + pdn->session_id = 0; + pdn->active = LTE_PDN_ACTIVE; + pdn->apn_type = apn->apn_type; + pdn->ipaddr_num = 0; + + ret = nrf_modem_at_cmd(resp, sizeof(resp), "AT+CGPADDR=0"); + if (ret == 0) + { + p = strchr(resp, '"'); + if (p != NULL) + { + p++; + q = strchr(p, '"'); + if (q != NULL) + { + n = (size_t)(q - p); + if (n >= LTE_IPADDR_MAX_LEN) + { + n = LTE_IPADDR_MAX_LEN - 1; + } + + pdn->address[0].ip_type = apn->ip_type; + memcpy(pdn->address[0].address, p, n); + pdn->address[0].address[n] = '\0'; + pdn->ipaddr_num = 1; + } + } + } + + return OK; +} + /**************************************************************************** * Name: nrf91_ioctl_ltecmd ****************************************************************************/ @@ -500,6 +632,32 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) break; } + case LTE_CMDID_RADIOON: + { + /* The radio is enabled by AT+CFUN=1 at power-on / PDN + * activation, so there is nothing extra to do here. + */ + + ret = OK; + break; + } + + case LTE_CMDID_RADIOOFF: + { + ret = nrf_modem_at_printf("AT+CFUN=4"); + break; + } + + case LTE_CMDID_ACTPDN: + { + lte_apn_setting_t **apn = + (lte_apn_setting_t **)(ltecmd->inparam); + lte_pdn_t **pdn = + (lte_pdn_t **)(ltecmd->outparam + 1); + ret = nrf91_modem_actpdn(*apn, *pdn); + break; + } + case LTE_CMDID_GETVER: { lte_version_t **version = @@ -558,6 +716,7 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) } (*quality)->valid = true; + break; } /* TODO: commands from include/nuttx/wireless/lte/lte.h */ From 155805c2e633d062f13bc5c51e490a3518932b1c Mon Sep 17 00:00:00 2001 From: Martin Vajnar Date: Fri, 5 Jun 2026 14:37:46 +0200 Subject: [PATCH 003/268] video/fb: Trigger updatearea() if CONFIG_FB_UPDATE is defined When CONFIG_FB_UPDATE is defined the missing updatearea() trigger caused the splashscreen to not be displayed. Signed-off-by: Martin Vajnar --- drivers/video/fb.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/drivers/video/fb.c b/drivers/video/fb.c index 4aaf7374d55..0c182be74b3 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -1934,6 +1934,9 @@ int fb_register_device(int display, int plane, struct fb_panelinfo_s panelinfo; #ifdef CONFIG_VIDEO_FB_SPLASHSCREEN struct fb_planeinfo_s pinfo; +# ifdef CONFIG_FB_UPDATE + struct fb_area_s area; +# endif #endif struct fb_videoinfo_s vinfo; char devname[16]; @@ -2041,6 +2044,24 @@ int fb_register_device(int display, int plane, goto errout_with_paninfo; } +# ifdef CONFIG_FB_UPDATE + if (fb->vtable->updatearea == NULL) + { + goto errout_with_paninfo; + } + + area.x = 0; + area.y = 0; + area.w = vinfo.xres; + area.h = vinfo.yres; + + ret = fb->vtable->updatearea(fb->vtable, &area); + if (ret < 0) + { + goto errout_with_paninfo; + } +# endif + if (SPLASH_SLEEP != 0) { nxsched_sleep(SPLASH_SLEEP); @@ -2052,6 +2073,14 @@ int fb_register_device(int display, int plane, { goto errout_with_paninfo; } + +# ifdef CONFIG_FB_UPDATE + ret = fb->vtable->updatearea(fb->vtable, &area); + if (ret < 0) + { + goto errout_with_paninfo; + } +# endif # endif #endif From 80f133504a81af4ffedd17e638472b85e3ea08a8 Mon Sep 17 00:00:00 2001 From: hanzj Date: Fri, 5 Jun 2026 21:59:48 +0800 Subject: [PATCH 004/268] boards/sim/sim/sim/nsh: enable CONFIG_RTC so date command shows host time The default sim:nsh config has no RTC, causing NSH_DISABLE_DATE to be auto-enabled (default: DEFAULT_SMALL || !RTC). This means the date command is not compiled in, and the system time defaults to a hardcoded value instead of syncing with the host. Enable CONFIG_RTC, CONFIG_RTC_DRIVER, and CONFIG_RTC_ARCH in the sim:nsh defconfig so the date command is available and shows the correct host time out of the box. Signed-off-by: hanzj --- boards/sim/sim/sim/configs/nsh/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/boards/sim/sim/sim/configs/nsh/defconfig b/boards/sim/sim/sim/configs/nsh/defconfig index c44d9f32031..74e659cff02 100644 --- a/boards/sim/sim/sim/configs/nsh/defconfig +++ b/boards/sim/sim/sim/configs/nsh/defconfig @@ -60,6 +60,9 @@ CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_FILE=y CONFIG_PSEUDOFS_SOFTLINKS=y CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RTC=y +CONFIG_RTC_ARCH=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_EVENTS=y CONFIG_SCHED_HAVE_PARENT=y From 41381edb31c4e3846fb857b13011c562670385db Mon Sep 17 00:00:00 2001 From: Martin Vajnar Date: Sun, 7 Jun 2026 09:26:50 +0200 Subject: [PATCH 005/268] video/fb: Handle case of multiple displays where some do not require update It can happen that multiple display configuration is used in which some displays require explicit update while others do not. If the updatearea() is NULL, simply skip the update instead of erroring out. Signed-off-by: Martin Vajnar --- drivers/video/fb.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/video/fb.c b/drivers/video/fb.c index 0c182be74b3..461a13ce1bb 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -2047,18 +2047,20 @@ int fb_register_device(int display, int plane, # ifdef CONFIG_FB_UPDATE if (fb->vtable->updatearea == NULL) { - goto errout_with_paninfo; + gerr("ERROR: updatearea() == NULL\n"); } - - area.x = 0; - area.y = 0; - area.w = vinfo.xres; - area.h = vinfo.yres; - - ret = fb->vtable->updatearea(fb->vtable, &area); - if (ret < 0) + else { - goto errout_with_paninfo; + area.x = 0; + area.y = 0; + area.w = vinfo.xres; + area.h = vinfo.yres; + + ret = fb->vtable->updatearea(fb->vtable, &area); + if (ret < 0) + { + goto errout_with_paninfo; + } } # endif @@ -2075,10 +2077,13 @@ int fb_register_device(int display, int plane, } # ifdef CONFIG_FB_UPDATE - ret = fb->vtable->updatearea(fb->vtable, &area); - if (ret < 0) + if (fb->vtable->updatearea != NULL) { - goto errout_with_paninfo; + ret = fb->vtable->updatearea(fb->vtable, &area); + if (ret < 0) + { + goto errout_with_paninfo; + } } # endif # endif From 7922011b72f75ce79c2ce532b54c4d4141b387a0 Mon Sep 17 00:00:00 2001 From: hanzj Date: Sun, 7 Jun 2026 07:37:13 +0800 Subject: [PATCH 006/268] Documentation: document tcpdump command. Add documentation for the tcpdump system command, covering command-line options (-i, -w, -s), Kconfig configuration, usage examples, and notes on pcap output format compatibility. Signed-off-by: hanzj --- .../applications/system/tcpdump/index.rst | 81 +++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/Documentation/applications/system/tcpdump/index.rst b/Documentation/applications/system/tcpdump/index.rst index c83214a2e9a..e119fd71069 100644 --- a/Documentation/applications/system/tcpdump/index.rst +++ b/Documentation/applications/system/tcpdump/index.rst @@ -1,3 +1,84 @@ =========================== ``tcpdump`` tcpdump command =========================== + +Captures network packets from a specified interface and writes them to a file +in `pcap `__ format. The resulting capture file can +be analyzed with tools such as Wireshark or ``tcpdump`` on a host machine. + +Configuration +============= + +Enable the command with ``CONFIG_SYSTEM_TCPDUMP``. This option requires +``CONFIG_NET_PKT`` (raw packet socket support) and automatically selects +``CONFIG_SYSTEM_ARGTABLE3`` for command-line argument parsing. + +The following configuration options are available: + +``CONFIG_SYSTEM_TCPDUMP_PROGNAME`` + Program name for the ``tcpdump`` command. Default: ``tcpdump``. + +``CONFIG_SYSTEM_TCPDUMP_PRIORITY`` + Task priority. Default: ``100``. + +``CONFIG_SYSTEM_TCPDUMP_STACKSIZE`` + Stack size. Default: ``4096``. + +Usage +===== + +.. code-block:: console + + nsh> tcpdump -i -w [-s ] + +Options +======= + +``-i ``, ``--interface `` + Network interface to capture from (e.g. ``eth0``). Required. + +``-w `` + Path to the output pcap file. Required. + +``-s ``, ``--snapshot-length `` + Maximum number of bytes to capture per packet. Optional. + Default: ``262144``. + +Examples +======== + +Capture all packets on ``eth0`` and save to a file: + +.. code-block:: console + + nsh> tcpdump -i eth0 -w /tmp/capture.pcap + ^C + +Capture with a limited snapshot length: + +.. code-block:: console + + nsh> tcpdump -i eth0 -w /tmp/capture.pcap -s 1500 + ^C + +Copy the capture file to a host machine for analysis with Wireshark: + +.. code-block:: console + + nsh> cp /tmp/capture.pcap /mnt/capture.pcap + +Notes +===== + +- The output file uses the pcap format (version 2.4, nanosecond resolution) + which is compatible with Wireshark, ``tcpdump``, and other standard capture + analysis tools. +- The command captures on the specified interface until interrupted with + ``Ctrl-C`` (``SIGINT``). +- The link-layer type is detected automatically: ``LINKTYPE_ETHERNET`` (1) + for Ethernet interfaces, or ``LINKTYPE_RAW`` (101) for other interfaces + such as SLIP or tun. +- Packets are timestamped using ``CLOCK_REALTIME``. Ensure the system clock + is set correctly for meaningful timestamps in the capture file. +- The capture requires ``CONFIG_NET_PKT`` to be enabled for raw packet + socket support. From 9e9926317d15c6398d295a7b20b3059b7ac0574c Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sat, 6 Jun 2026 16:54:27 -0400 Subject: [PATCH 007/268] drivers/contactless/pn532: Fix potential overflow Fixes a potential overflow where more than 16 bytes are written to the cmd_buffer. Signed-off-by: Matteo Golin --- drivers/contactless/pn532.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/contactless/pn532.c b/drivers/contactless/pn532.c index bd93de40545..722ca843ea1 100644 --- a/drivers/contactless/pn532.c +++ b/drivers/contactless/pn532.c @@ -794,6 +794,7 @@ bool pn532_set_rf_config(struct pn532_dev_s * dev, pn532_frame_init(f, PN532_COMMAND_RFCONFIGURATION); f->data[1] = conf->cfg_item; + DEBUGASSERT(conf->data_size <= 16); memcpy(&f->data[2], conf->config, conf->data_size); f->len += conf->data_size + 1; pn532_frame_finish(f); From 9c10bbd04a165de47eff4c19de9f0a2e10993754 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Tue, 2 Jun 2026 09:18:13 +0300 Subject: [PATCH 008/268] drivers/mtd: Remove bad block management in FTL for devices not needing it Bad block management and the logical->physical mapping is only needed with raw NAND type memories, so we can compile that in conditionally, saving ~600 bytes of flash on a 32-bit arm when NAND is not used. Signed-off-by: Jukka Laitinen --- drivers/mtd/Kconfig | 10 ++++++++++ drivers/mtd/ftl.c | 48 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index b661bc44212..343693c8ffd 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -50,6 +50,15 @@ config FTL_READAHEAD default n depends on DRVR_READAHEAD +config FTL_BBM + bool "Enable bad block management in the FTL layer" + default y if MTD_NAND + ---help--- + Enable logical to physical erase-block mapping in the FTL layer for + MTD devices that expose bad blocks via the MTD isbad/markbad methods. + + This is needed for devices that require software bad block management. + config MTD_SECT512 bool "512B sector conversion" default n @@ -1442,6 +1451,7 @@ config MTD_GD5F bool "SPI-based GD5F nand FLASH" default n select SPI + select FTL_BBM if MTD_GD5F diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index 83c027e06a7..f175f4f5076 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -80,10 +80,12 @@ struct ftl_struct_s FAR uint8_t *eblock; /* One, in-memory erase block */ int oflags; - /* The nand block map between logic block and physical block */ +#ifdef CONFIG_FTL_BBM + /* The block map between logic block and physical block */ FAR off_t *lptable; off_t lpcount; +#endif }; /**************************************************************************** @@ -133,12 +135,14 @@ static const struct block_operations g_bops = * Private Functions ****************************************************************************/ +#ifdef CONFIG_FTL_BBM + /**************************************************************************** * Name: ftl_init_map * * Description: Allocate logical block and physical block mapping table - * space, and scan the entire nand flash device to establish - * the mapping relationship between logical block and physical + * space, and scan the entire MTD device to establish the + * mapping relationship between logical block and physical * good block. * ****************************************************************************/ @@ -207,6 +211,7 @@ static size_t ftl_get_cblock(FAR struct ftl_struct_s *dev, off_t start, return count; } +#endif /**************************************************************************** * Name: ftl_open @@ -273,11 +278,15 @@ static int ftl_close(FAR struct inode *inode) static ssize_t ftl_mtd_bread(FAR struct ftl_struct_s *dev, off_t startblock, size_t nblocks, FAR uint8_t *buffer) { +#ifdef CONFIG_FTL_BBM off_t mask = dev->blkper - 1; size_t nread = nblocks; +#endif ssize_t ret = OK; +#ifdef CONFIG_FTL_BBM if (dev->lptable == NULL) +#endif { ret = MTD_BREAD(dev->mtd, startblock, nblocks, buffer); if (ret != nblocks) @@ -289,6 +298,7 @@ static ssize_t ftl_mtd_bread(FAR struct ftl_struct_s *dev, off_t startblock, return ret; } +#ifdef CONFIG_FTL_BBM while (nblocks > 0) { off_t startphysicalblock; @@ -324,6 +334,7 @@ static ssize_t ftl_mtd_bread(FAR struct ftl_struct_s *dev, off_t startblock, } return nblocks != nread ? nread - nblocks : ret; +#endif } /**************************************************************************** @@ -339,10 +350,14 @@ static ssize_t ftl_mtd_bread(FAR struct ftl_struct_s *dev, off_t startblock, static ssize_t ftl_mtd_bwrite(FAR struct ftl_struct_s *dev, off_t startblock, FAR const uint8_t *buffer) { +#ifdef CONFIG_FTL_BBM off_t starteraseblock; +#endif ssize_t ret; +#ifdef CONFIG_FTL_BBM if (dev->lptable == NULL) +#endif { ret = MTD_BWRITE(dev->mtd, startblock, dev->blkper, buffer); if (ret != dev->blkper) @@ -354,6 +369,7 @@ static ssize_t ftl_mtd_bwrite(FAR struct ftl_struct_s *dev, off_t startblock, return ret; } +#ifdef CONFIG_FTL_BBM starteraseblock = startblock / dev->blkper; while (1) { @@ -372,6 +388,7 @@ static ssize_t ftl_mtd_bwrite(FAR struct ftl_struct_s *dev, off_t startblock, MTD_MARKBAD(dev->mtd, dev->lptable[starteraseblock]); ftl_update_map(dev, starteraseblock); } +#endif } /**************************************************************************** @@ -389,7 +406,9 @@ static ssize_t ftl_mtd_erase(FAR struct ftl_struct_s *dev, off_t startblock) { ssize_t ret; +#ifdef CONFIG_FTL_BBM if (dev->lptable == NULL) +#endif { ret = MTD_ERASE(dev->mtd, startblock, 1); if (ret < 0 && ret != -ENOSYS) @@ -402,6 +421,7 @@ static ssize_t ftl_mtd_erase(FAR struct ftl_struct_s *dev, off_t startblock) return OK; } +#ifdef CONFIG_FTL_BBM while (1) { if (startblock >= dev->lpcount) @@ -418,6 +438,7 @@ static ssize_t ftl_mtd_erase(FAR struct ftl_struct_s *dev, off_t startblock) MTD_MARKBAD(dev->mtd, dev->lptable[startblock]); ftl_update_map(dev, startblock); } +#endif } /**************************************************************************** @@ -517,7 +538,9 @@ static ssize_t ftl_flush_direct(FAR struct ftl_struct_s *dev, } } +#ifdef CONFIG_FTL_BBM if (dev->lptable == NULL) +#endif { ret = MTD_BWRITE(dev->mtd, startblock, count, buffer); if (ret != count) @@ -527,6 +550,7 @@ static ssize_t ftl_flush_direct(FAR struct ftl_struct_s *dev, return ret; } } +#ifdef CONFIG_FTL_BBM else { if (starteraseblock >= dev->lpcount) @@ -544,6 +568,7 @@ static ssize_t ftl_flush_direct(FAR struct ftl_struct_s *dev, continue; } } +#endif nblocks -= count; startblock += count; @@ -567,7 +592,11 @@ static ssize_t ftl_flush(FAR void *priv, FAR const uint8_t *buffer, int nbytes; int ret; +#ifdef CONFIG_FTL_BBM if (dev->mtd->erase == NULL && dev->lptable == NULL) +#else + if (dev->mtd->erase == NULL) +#endif { ret = MTD_BWRITE(dev->mtd, startblock, nblocks, buffer); if (ret != nblocks) @@ -922,6 +951,15 @@ int ftl_initialize_by_path(FAR const char *path, FAR struct mtd_dev_s *mtd, finfo("path=\"%s\"\n", path); +#ifndef CONFIG_FTL_BBM + /* It is likely a configuration error if the mtd driver implements + * the bad block management, but it is still disabled by the + * configuration. + */ + + DEBUGASSERT(mtd->isbad == NULL && mtd->markbad == NULL); +#endif + /* Allocate a FTL device structure */ dev = kmm_zalloc(sizeof(struct ftl_struct_s)); @@ -978,6 +1016,7 @@ int ftl_initialize_by_path(FAR const char *path, FAR struct mtd_dev_s *mtd, } #endif +#ifdef CONFIG_FTL_BBM if (MTD_ISBAD(dev->mtd, 0) != -ENOSYS) { ret = ftl_init_map(dev); @@ -986,6 +1025,7 @@ int ftl_initialize_by_path(FAR const char *path, FAR struct mtd_dev_s *mtd, goto out; } } +#endif /* Inode private data is a reference to the FTL device structure */ @@ -993,8 +1033,10 @@ int ftl_initialize_by_path(FAR const char *path, FAR struct mtd_dev_s *mtd, if (ret < 0) { ferr("ERROR: register_blockdriver failed: %d\n", -ret); +#ifdef CONFIG_FTL_BBM kmm_free(dev->lptable); out: +#endif #ifdef FTL_HAVE_RWBUFFER rwb_uninitialize(&dev->rwb); #endif From 14e434c3f0dab9105a9f4b5ce7528d1ccc9de140 Mon Sep 17 00:00:00 2001 From: leisiji <2265215145@qq.com> Date: Fri, 5 Jun 2026 12:06:11 +0800 Subject: [PATCH 009/268] mm/kasan: Fix compile options applied to wrong target in SPLIT build In SPLIT build mode, nuttx_add_kernel_library(mm SPLIT) creates two targets: mm (system library) and kmm (kernel library). The compile options were being applied to the mm target via target_compile_options(mm ...), but the kasan instrumentation is compiled as part of the kmm target. Change target_compile_options(mm ...) to target_compile_options(kmm ...) so that FLAGS (including -fno-builtin and NO_LTO) are correctly applied to the kernel target where kasan code is compiled. Signed-off-by: leisiji <2265215145@qq.com> --- mm/kasan/CMakeLists.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/mm/kasan/CMakeLists.txt b/mm/kasan/CMakeLists.txt index d33e1805fed..d802a55b1a4 100644 --- a/mm/kasan/CMakeLists.txt +++ b/mm/kasan/CMakeLists.txt @@ -34,4 +34,9 @@ if(CONFIG_MM_KASAN) endif() target_sources(mm PRIVATE ${SRCS}) -target_compile_options(mm PRIVATE ${FLAGS}) + +if(CONFIG_BUILD_FLAT) + target_compile_options(mm PRIVATE ${FLAGS}) +else() + target_compile_options(kmm PRIVATE ${FLAGS}) +endif() From ace40bfbfc44a74673c1d6e834369c0d218d4b0f Mon Sep 17 00:00:00 2001 From: leisiji <2265215145@qq.com> Date: Sat, 6 Jun 2026 10:10:47 +0800 Subject: [PATCH 010/268] build/fix: remove nonexistent target in cmake nuttx_apps_mksymtab is nonexistent in nuttx, which produce error when build with CONFIG_MODULES Signed-off-by: leisiji <2265215145@qq.com> --- cmake/nuttx_add_application.cmake | 1 - 1 file changed, 1 deletion(-) diff --git a/cmake/nuttx_add_application.cmake b/cmake/nuttx_add_application.cmake index db436aeba93..c0b147452a3 100644 --- a/cmake/nuttx_add_application.cmake +++ b/cmake/nuttx_add_application.cmake @@ -195,7 +195,6 @@ function(nuttx_add_application) # loadable build requires applying ELF flags to all applications if(CONFIG_MODULES) - add_dependencies(nuttx_apps_mksymtab ${TARGET}) target_compile_options( ${TARGET} PRIVATE From 8121b8866604cb4d0447718e4af23404bacfeb69 Mon Sep 17 00:00:00 2001 From: leisiji <2265215145@qq.com> Date: Sat, 6 Jun 2026 10:12:37 +0800 Subject: [PATCH 011/268] cmake/elf: Fix ELF entry point from __start to _start __start is the kernel boot entry for each chip, while _start (defined in crt0.c) is the correct C runtime entry point for ELF executables. Signed-off-by: leisiji <2265215145@qq.com> --- arch/arm/src/cmake/elf.cmake | 2 +- arch/arm64/src/cmake/elf.cmake | 2 +- arch/x86_64/src/cmake/elf.cmake | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/src/cmake/elf.cmake b/arch/arm/src/cmake/elf.cmake index 48735ec85f8..bd5a4bedef0 100644 --- a/arch/arm/src/cmake/elf.cmake +++ b/arch/arm/src/cmake/elf.cmake @@ -46,4 +46,4 @@ if(CONFIG_DEBUG_OPT_UNUSED_SECTIONS) endif() endif() -nuttx_elf_link_options(-e __start) +nuttx_elf_link_options(-e _start) diff --git a/arch/arm64/src/cmake/elf.cmake b/arch/arm64/src/cmake/elf.cmake index 2e54432f5dc..92e175ddfe0 100644 --- a/arch/arm64/src/cmake/elf.cmake +++ b/arch/arm64/src/cmake/elf.cmake @@ -32,4 +32,4 @@ nuttx_elf_link_options_ifdef(CONFIG_BUILD_KERNEL -Bstatic) nuttx_elf_link_options_ifdef(CONFIG_DEBUG_OPT_UNUSED_SECTIONS --gc-sections) -nuttx_elf_link_options(-e __start) +nuttx_elf_link_options(-e _start) diff --git a/arch/x86_64/src/cmake/elf.cmake b/arch/x86_64/src/cmake/elf.cmake index 302688f9e19..11b350ab2a7 100644 --- a/arch/x86_64/src/cmake/elf.cmake +++ b/arch/x86_64/src/cmake/elf.cmake @@ -30,4 +30,4 @@ nuttx_mod_link_options(-r) nuttx_elf_link_options_ifdef(CONFIG_DEBUG_OPT_UNUSED_SECTIONS --gc-sections) -nuttx_elf_link_options(-e __start) +nuttx_elf_link_options(-e _start) From 3c8621cb898f4d3bcbdb34bf64b632a16378c8ac Mon Sep 17 00:00:00 2001 From: hanzj Date: Mon, 8 Jun 2026 07:26:52 +0800 Subject: [PATCH 012/268] Documentation: document sensortest command Add documentation for the sensortest system tool which reads data from sensor drivers via the uORB topic interface. Signed-off-by: hanzj --- .../applications/system/sensortest/index.rst | 212 ++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 Documentation/applications/system/sensortest/index.rst diff --git a/Documentation/applications/system/sensortest/index.rst b/Documentation/applications/system/sensortest/index.rst new file mode 100644 index 00000000000..7bf5a930beb --- /dev/null +++ b/Documentation/applications/system/sensortest/index.rst @@ -0,0 +1,212 @@ +=============================== +``sensortest`` sensor test tool +=============================== + +Reads data from a sensor driver via the uORB topic interface and prints the +output to the console. Useful for verifying that a sensor driver is working +correctly and producing valid data. + +Configuration +============= + +Enable the command with ``CONFIG_SYSTEM_SENSORTEST``. This option requires +``CONFIG_SENSORS`` and ``CONFIG_ENABLE_ALL_SIGNALS``. + +The following configuration options are available: + +``CONFIG_SYSTEM_SENSORTEST_PROGNAME`` + Program name for the ``sensortest`` command. Default: ``sensortest``. + +``CONFIG_SYSTEM_SENSORTEST_PRIORITY`` + Task priority. Default: ``100``. + +``CONFIG_SYSTEM_SENSORTEST_STACKSIZE`` + Stack size. Default: ``DEFAULT_TASK_STACKSIZE``. + +Usage +===== + +.. code-block:: console + + nsh> sensortest [-i ] [-b ] [-n ] + +Options +======= + +``-i `` + Data output period in microseconds. Controls how often the sensor is + polled for new data. Optional. Default: ``1000000`` (1 second). + +``-b `` + Maximum report latency in microseconds. When set to a non-zero value, + the sensor may batch multiple readings and deliver them at once. + Optional. Default: ``0`` (no batching). + +``-n `` + Number of data samples to read before exiting. When set to ``0``, + the command runs continuously until interrupted. Optional. + Default: ``0`` (unlimited). + +``-h`` + Print help message and exit. + +Commands +======== + +```` + The sensor node name without the ``sensor_`` prefix and ``/dev/uorb/`` + path. For example, use ``accel`` to read from ``/dev/uorb/sensor_accel``. + +Supported Sensors +================= + +The following sensor types are supported: + +.. list-table:: + :header-rows: 1 + :widths: 25 25 50 + + * - Name + - Data Type + - Description + * - ``accel`` + - vec3 (x, y, z) + - Accelerometer + * - ``baro`` + - valf2 + - Barometer (pressure, temperature) + * - ``cap`` + - cap + - Capacitance + * - ``co2`` + - valf + - CO2 concentration + * - ``dust`` + - valf + - Dust particle concentration + * - ``ecg`` + - ecg + - Electrocardiogram + * - ``force`` + - force + - Force sensor + * - ``gnss`` + - gnss + - GNSS position + * - ``gnss_satellite`` + - gnss_satellite + - GNSS satellite info + * - ``gyro`` + - vec3 (x, y, z) + - Gyroscope + * - ``hall`` + - valb + - Hall effect sensor + * - ``hbeat`` + - valf + - Heartbeat + * - ``hcho`` + - valf + - Formaldehyde concentration + * - ``hrate`` + - valf + - Heart rate + * - ``humi`` + - valf + - Humidity + * - ``impd`` + - valf2 + - Impedance + * - ``ir`` + - valf + - Infrared + * - ``light`` + - valf + - Ambient light + * - ``mag`` + - vec3 (x, y, z) + - Magnetometer + * - ``noise`` + - valf + - Noise level + * - ``ots`` + - vali2 + - Optical tracking speed + * - ``ph`` + - valf + - pH value + * - ``pm10`` + - valf + - PM10 particulate matter + * - ``pm1p0`` + - valf + - PM1.0 particulate matter + * - ``pm25`` + - valf + - PM2.5 particulate matter + * - ``ppgd`` + - ppgd + - PPG (photoplethysmography) data + * - ``ppgq`` + - ppgq + - PPG quality + * - ``prox`` + - valf + - Proximity + * - ``rgb`` + - valf3 + - RGB color sensor + * - ``velocity`` + - velocity + - Velocity sensor + * - ``temp`` + - valf + - Temperature + * - ``tvoc`` + - valf + - Total volatile organic compounds + * - ``uv`` + - valf + - Ultraviolet + +Examples +======== + +Read accelerometer data at the default 1-second interval: + +.. code-block:: console + + nsh> sensortest accel + accel: timestamp:1234567890 x:0.12 y:-0.03 z:9.81, temperature:25.50 + accel: timestamp:1235567890 x:0.11 y:-0.04 z:9.80, temperature:25.51 + ^C + +Read gyroscope data at 100ms intervals, 10 samples: + +.. code-block:: console + + nsh> sensortest -i 100000 -n 10 gyro + gyro: timestamp:1234567890 x:0.01 y:0.02 z:0.00, temperature:26.00 + ... + +Read temperature sensor with batching enabled: + +.. code-block:: console + + nsh> sensortest -b 5000000 temp + temp: timestamp:1234567890 value:25.50 + ... + +Notes +===== + +- The command reads from ``/dev/uorb/sensor_`` using the uORB + subscriber interface. Ensure the corresponding sensor driver is + enabled and the uORB topic is published. +- The command runs continuously until interrupted with ``Ctrl-C`` + (``SIGINT``) unless a sample count is specified with ``-n``. +- The ``-b`` (latency) option controls batching behavior. When set to + a non-zero value, the sensor driver may buffer multiple readings and + deliver them together, reducing the number of wake-ups. +- The timestamp field in the output is provided by the sensor driver + and uses the system monotonic clock. From 59a66fa17d0c1ec36b4168438b89095c257762fb Mon Sep 17 00:00:00 2001 From: Shoji Tokunaga Date: Mon, 1 Jun 2026 15:32:15 +0900 Subject: [PATCH 013/268] tools: Enable Rust sim builds on Intel Macs Add support for building Rust apps on the NuttX simulator running on Intel (x86_64) macOS. - Add tools/x86_64-unknown-nuttx-macho.json, a Mach-O Rust target for the macOS sim. - Rust.defs: select the new x86_64 macho target for sim on macOS. - boards/sim/.../Make.defs: keep the default PIC/PIE-compatible code generation on macOS by not adding -fno-pic/-mcmodel=medium. - sethost.sh: enable CONFIG_HOST_X86_64 for non-arm64 hosts. Signed-off-by: Shoji Tokunaga --- boards/sim/sim/sim/scripts/Make.defs | 20 ++++++++++---- tools/Rust.defs | 2 ++ tools/aarch64-unknown-nuttx-macho.json | 1 + tools/sethost.sh | 3 +++ tools/x86_64-unknown-nuttx-macho.json | 36 ++++++++++++++++++++++++++ 5 files changed, 57 insertions(+), 5 deletions(-) create mode 100644 tools/x86_64-unknown-nuttx-macho.json diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index 2cc3d159d27..0b61eaebddd 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -149,11 +149,16 @@ ifeq ($(CONFIG_SIM_M32),y) ARCHCFLAGS += -m32 ARCHCXXFLAGS += -m32 else - ARCHCFLAGS += -fno-pic - ARCHCXXFLAGS += -fno-pic - ifeq ($(CONFIG_HOST_X86_64),y) - ARCHCFLAGS += -mcmodel=medium - ARCHCXXFLAGS += -mcmodel=medium + # On macOS, keep the default PIC/PIE-compatible code generation. + # Adding -fno-pic (which implies -mdynamic-no-pic on Apple clang) makes + # the final PIE link emit "PIE disabled. Absolute addressing ..." warnings. + ifneq ($(CONFIG_HOST_MACOS),y) + ARCHCFLAGS += -fno-pic + ARCHCXXFLAGS += -fno-pic + ifeq ($(CONFIG_HOST_X86_64),y) + ARCHCFLAGS += -mcmodel=medium + ARCHCXXFLAGS += -mcmodel=medium + endif endif endif @@ -327,6 +332,11 @@ ifeq ($(CONFIG_SIM_M32),y) SHMODULEFLAGS += -melf_i386 LDELFFLAGS += -melf_i386 +else ifeq ($(CONFIG_HOST_MACOS)$(CONFIG_HOST_X86_64),yy) + # Keep the default PIE link mode on macOS. + # -no_pie is deprecated for newer macOS deployment targets, and the + # PIC/PIE-compatible code generation above lets the PIE link succeed. + else ifeq ($(CONFIG_HOST_MACOS)$(CONFIG_HOST_ARM64),) # To compile 64-bit Sim, adding no-pie is necessary to prevent linking errors # but this may cause other issues on Ubuntu 20. diff --git a/tools/Rust.defs b/tools/Rust.defs index 50225761e63..ca87f901cfc 100644 --- a/tools/Rust.defs +++ b/tools/Rust.defs @@ -46,6 +46,8 @@ ifeq ($(CONFIG_ARCH_SIM),y) else ifeq ($(CONFIG_HOST_MACOS),y) ifeq ($(LLVM_ARCHTYPE),aarch64) RUSTFLAGS += --target $(TOPDIR)/tools/aarch64-unknown-nuttx-macho.json + else ifeq ($(LLVM_ARCHTYPE),x86_64) + RUSTFLAGS += --target $(TOPDIR)/tools/x86_64-unknown-nuttx-macho.json else $(error Unsupported Rust SIM target on macOS: LLVM_ARCHTYPE=$(LLVM_ARCHTYPE)) endif diff --git a/tools/aarch64-unknown-nuttx-macho.json b/tools/aarch64-unknown-nuttx-macho.json index 5410ffd9f21..8a2de4f90e7 100644 --- a/tools/aarch64-unknown-nuttx-macho.json +++ b/tools/aarch64-unknown-nuttx-macho.json @@ -23,6 +23,7 @@ }, "os": "nuttx", "panic-strategy": "abort", + "relocation-model": "pic", "split-debuginfo": "off", "stack-probes": { "kind": "inline" diff --git a/tools/sethost.sh b/tools/sethost.sh index 71fb33938b5..772c34b6688 100755 --- a/tools/sethost.sh +++ b/tools/sethost.sh @@ -191,6 +191,9 @@ if [ "X$host" == "Xlinux" -o "X$host" == "Xmacos" -o "X$host" == "Xbsd" ]; then if [ "X$cpu" == "Xarm64" ]; then echo " Select CONFIG_HOST_ARM64=y" kconfig-tweak --file $nuttx/.config --enable CONFIG_HOST_ARM64 + else + echo " Select CONFIG_HOST_X86_64=y" + kconfig-tweak --file $nuttx/.config --enable CONFIG_HOST_X86_64 fi fi diff --git a/tools/x86_64-unknown-nuttx-macho.json b/tools/x86_64-unknown-nuttx-macho.json new file mode 100644 index 00000000000..5e5fc7a206e --- /dev/null +++ b/tools/x86_64-unknown-nuttx-macho.json @@ -0,0 +1,36 @@ +{ + "arch": "x86_64", + "archive-format": "darwin", + "binary-format": "mach-o", + "cpu": "x86-64", + "crt-objects-fallback": "false", + "data-layout": "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128", + "debuginfo-kind": "dwarf", + "default-uwtable": true, + "disable-redzone": true, + "emit-debug-gdb-scripts": false, + "frame-pointer": "always", + "function-sections": false, + "linker-flavor": "gnu-lld", + "lld-flavor": "darwin", + "llvm-target": "x86_64-apple-macosx", + "max-atomic-width": 64, + "metadata": { + "description": "x86_64 Mach-O target for NuttX sim on macOS", + "host_tools": false, + "std": true, + "tier": 3 + }, + "os": "nuttx", + "panic-strategy": "abort", + "relocation-model": "pic", + "split-debuginfo": "off", + "stack-probes": { + "kind": "inline" + }, + "target-family": [ + "unix" + ], + "target-pointer-width": 64, + "vendor": "unknown" +} From fa7f85632c37cb843eaa0fd8d6d9b057580293e0 Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Tue, 19 May 2026 12:50:29 +0000 Subject: [PATCH 014/268] fs/vfs: enforce pseudoFS permissions on mutation operations Add pseudoFS permission enforcement for unlink(), mkdir(), and rename() VFS mutation operations. This change validates parent-directory permissions before modifying pseudoFS inode topology and returns -EACCES for unauthorized operations. The implementation preserves mountpoint filesystem behavior and fixes multiple inode lifetime/search-state issues in the rename path. Signed-off-by: Abhishek Mishra --- fs/inode/fs_inode.c | 193 ++++++++++++++++++++++++++++---------------- fs/inode/inode.h | 37 +++++---- fs/vfs/fs_mkdir.c | 13 +++ fs/vfs/fs_rename.c | 43 +++++++++- fs/vfs/fs_unlink.c | 8 ++ 5 files changed, 206 insertions(+), 88 deletions(-) diff --git a/fs/inode/fs_inode.c b/fs/inode/fs_inode.c index 32dee8ff432..2505fbc2e3e 100644 --- a/fs/inode/fs_inode.c +++ b/fs/inode/fs_inode.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -48,6 +49,70 @@ static rw_semaphore_t g_inode_lock = RWSEM_INITIALIZER; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: _inode_checkmode + * + * Description: + * Test effective credentials against 'inode' for 'amode' access. + * Kernel threads always pass. + * + * Returned Value: + * Zero (OK) or -EACCES. + * + ****************************************************************************/ + +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) +static int _inode_checkmode(FAR struct inode *inode, int amode) +{ + FAR struct tcb_s *rtcb; + mode_t perm; + uid_t uid; + gid_t gid; + + /* Kernel threads are always granted access */ + + rtcb = nxsched_self(); + if ((rtcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) + { + return OK; + } + + /* Use effective credentials */ + + DEBUGASSERT(rtcb->group != NULL); + uid = rtcb->group->tg_euid; + gid = rtcb->group->tg_egid; + + /* Select the applicable permission-bit triplet */ + + if (uid == inode->i_owner) + { + perm = (inode->i_mode >> 6) & 7; + } + else if (gid == inode->i_group) + { + perm = (inode->i_mode >> 3) & 7; + } + else + { + perm = inode->i_mode & 7; + } + + /* Every requested bit must be present in the selected triplet */ + + if ((amode & perm) != amode) + { + return -EACCES; + } + + return OK; +} +#endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -124,49 +189,45 @@ void inode_runlock(void) * Name: inode_checkperm * * Description: - * Validate that 'inode' can be opened with the access described by - * 'oflags'. Two sequential checks are performed: - * - * 1. Operation-support check (all inode types, unconditional): - * Verifies the driver exposes the read/write entry points required by - * 'oflags'. Returns -ENXIO when ops are NULL and -EACCES when the - * required entry point is absent. Pseudo-directory inodes - * (INODE_IS_PSEUDODIR) are exempted from this step. - * - * 2. UNIX permission check (pseudo-filesystem inodes only): - * Compares effective uid/gid against i_mode owner/group/other bits. - * Mountpoint inodes and kernel threads are unconditionally exempted. - * Requires CONFIG_PSEUDOFS_ATTRIBUTES and CONFIG_SCHED_USER_IDENTITY; - * when either option is disabled this step is a no-op. + * Validate open access to 'inode' for 'oflags'. Checks driver operation + * support, then pseudo-filesystem mode bits when enabled. Mountpoints + * are exempt from mode checks. * * Input Parameters: * inode - The inode to check * oflags - Open flags (O_RDONLY / O_WRONLY / O_RDWR) * * Returned Value: - * Zero (OK) on success. Negated errno on failure: - * -ENXIO ops pointer is NULL - * -EACCES required operation not supported, or permission denied + * Zero (OK) on success, or a negated errno on failure. * ****************************************************************************/ int inode_checkperm(FAR struct inode *inode, int oflags) { #if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - FAR struct tcb_s *rtcb; - mode_t perm; - uid_t uid; - gid_t gid; + int amode = 0; #endif FAR const struct file_operations *ops; - /* === Step 1: operation-support check === */ +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) + if ((oflags & O_RDOK) != 0) + { + amode |= R_OK; + } - /* Pseudo-directories carry no ops and are always accessible */ + if ((oflags & O_WROK) != 0) + { + amode |= W_OK; + } +#endif if (INODE_IS_PSEUDODIR(inode)) { +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) + return _inode_checkmode(inode, amode); +#else return OK; +#endif } ops = inode->u.i_ops; @@ -185,61 +246,51 @@ int inode_checkperm(FAR struct inode *inode, int oflags) #if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - /* === Step 2: UNIX permission check (pseudo-filesystem inodes only) === */ - - /* Mountpoints delegate permission enforcement to the underlying - * filesystem - */ - if (INODE_IS_MOUNTPT(inode)) { return OK; } - /* Kernel threads are always granted access */ - - rtcb = nxsched_self(); - if ((rtcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) - { - return OK; - } - - /* Use effective credentials */ - - DEBUGASSERT(rtcb->group != NULL); - uid = rtcb->group->tg_euid; - gid = rtcb->group->tg_egid; - - /* Select the applicable permission-bit triplet */ - - if (uid == inode->i_owner) - { - perm = (inode->i_mode >> 6) & 7; - } - else if (gid == inode->i_group) - { - perm = (inode->i_mode >> 3) & 7; - } - else - { - perm = inode->i_mode & 7; - } - - /* Bit 2 (value 4) = read permission */ - - if (((oflags & O_RDOK) != 0) && ((perm & 4) == 0)) - { - return -EACCES; - } - - /* Bit 1 (value 2) = write permission */ - - if (((oflags & O_WROK) != 0) && ((perm & 2) == 0)) - { - return -EACCES; - } + return _inode_checkmode(inode, amode); #endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ return OK; } + +/**************************************************************************** + * Name: inode_checkdirperm + * + * Description: + * Check parent directory 'dir' for 'amode' access on pseudo-filesystem + * inodes. NULL 'dir' (root) and mountpoints are exempt. + * + * Input Parameters: + * dir - Parent directory inode, or NULL for a root-level path + * amode - Access mode bitmask (R_OK / W_OK / X_OK) + * + * Returned Value: + * Zero (OK) on success, or -EACCES if permission is denied. + * + ****************************************************************************/ + +int inode_checkdirperm(FAR struct inode *dir, int amode) +{ +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) + + if (dir == NULL) + { + return OK; + } + + if (INODE_IS_MOUNTPT(dir)) + { + return OK; + } + + return _inode_checkmode(dir, amode); + +#else + return OK; +#endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ +} diff --git a/fs/inode/inode.h b/fs/inode/inode.h index 8eccad2d367..3735d9a566c 100644 --- a/fs/inode/inode.h +++ b/fs/inode/inode.h @@ -422,32 +422,39 @@ void inode_release(FAR struct inode *inode); * Name: inode_checkperm * * Description: - * Validate that 'inode' can be opened with the access described by - * 'oflags'. Two sequential checks are performed: - * - * 1. Operation-support check (all inode types): - * Ensures the driver exposes the read/write entry points required by - * 'oflags'. Pseudo-directory inodes are exempted. - * - * 2. UNIX permission check (pseudo-filesystem inodes only): - * Compares effective uid/gid against i_mode owner/group/other bits. - * Mountpoint inodes and kernel threads are unconditionally exempted. - * Active only when CONFIG_PSEUDOFS_ATTRIBUTES and - * CONFIG_SCHED_USER_IDENTITY are both enabled. + * Validate open access to 'inode' for 'oflags'. Checks driver operation + * support, then pseudo-filesystem mode bits when enabled. Mountpoints + * are exempt from mode checks. * * Input Parameters: * inode - The inode to check * oflags - Open flags (O_RDONLY / O_WRONLY / O_RDWR) * * Returned Value: - * Zero (OK) on success. Negated errno on failure: - * -ENXIO ops pointer is NULL - * -EACCES required operation not supported, or permission denied + * Zero (OK) on success, or a negated errno on failure. * ****************************************************************************/ int inode_checkperm(FAR struct inode *inode, int oflags); +/**************************************************************************** + * Name: inode_checkdirperm + * + * Description: + * Check parent directory 'dir' for 'amode' access on pseudo-filesystem + * inodes. NULL 'dir' (root) and mountpoints are exempt. + * + * Input Parameters: + * dir - Parent directory inode, or NULL for a root-level path + * amode - Access mode bitmask (R_OK / W_OK / X_OK) + * + * Returned Value: + * Zero (OK) on success, or -EACCES if permission is denied. + * + ****************************************************************************/ + +int inode_checkdirperm(FAR struct inode *dir, int amode); + /**************************************************************************** * Name: foreach_inode * diff --git a/fs/vfs/fs_mkdir.c b/fs/vfs/fs_mkdir.c index c9be09d1049..bfd66a25834 100644 --- a/fs/vfs/fs_mkdir.c +++ b/fs/vfs/fs_mkdir.c @@ -31,6 +31,7 @@ #include #include #include +#include #include @@ -136,6 +137,18 @@ int mkdir(const char *pathname, mode_t mode) else { + /* Verify write+search permission on the parent directory before + * adding a new name to the pseudo-filesystem tree. POSIX requires + * both W_OK and X_OK to create a directory entry. + */ + + ret = inode_checkdirperm(desc.parent, W_OK | X_OK); + if (ret < 0) + { + errcode = -ret; + goto errout_with_search; + } + /* Create an inode in the pseudo-filesystem at this path. * NOTE that the new inode will be created with a reference * count of zero. diff --git a/fs/vfs/fs_rename.c b/fs/vfs/fs_rename.c index 15442a0a18c..11ea28a3b3f 100644 --- a/fs/vfs/fs_rename.c +++ b/fs/vfs/fs_rename.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include @@ -66,21 +67,35 @@ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS static int pseudorename(FAR const char *oldpath, FAR struct inode *oldinode, + FAR struct inode *oldparent, FAR const char *newpath) { struct inode_search_s newdesc; + struct inode_search_s pardesc; FAR struct inode *newinode; + FAR struct inode *parnode; FAR char *subdir = NULL; #ifdef CONFIG_FS_NOTIFY bool isdir = INODE_IS_PSEUDODIR(oldinode); #endif int ret; + /* SETUP_SEARCH early so RELEASE_SEARCH at errout is safe. */ + + SETUP_SEARCH(&newdesc, newpath, true); + + /* Verify source parent write permission. */ + + ret = inode_checkdirperm(oldparent, W_OK); + if (ret < 0) + { + goto errout; + } + /* According to POSIX, any new inode at this path should be removed * first, provided that it is not a directory. */ - SETUP_SEARCH(&newdesc, newpath, true); ret = inode_find(&newdesc); if (ret >= 0) { @@ -156,6 +171,30 @@ static int pseudorename(FAR const char *oldpath, FAR struct inode *oldinode, inode_release(newinode); } + /* Re-resolve the final destination parent after path rewrite. */ + + SETUP_SEARCH(&pardesc, newpath, true); + inode_find(&pardesc); /* pardesc.parent valid even if node not found */ + parnode = pardesc.node; + + ret = inode_checkdirperm(pardesc.parent, W_OK); + + /* inode_find() holds a reference on parnode; RELEASE_SEARCH() only + * frees pardesc.buffer. + */ + + if (parnode != NULL) + { + inode_release(parnode); + } + + RELEASE_SEARCH(&pardesc); + + if (ret < 0) + { + goto errout; + } + /* Create a new, empty inode at the destination location. * NOTE that the new inode will be created with a reference count * of zero. @@ -505,7 +544,7 @@ int rename(FAR const char *oldpath, FAR const char *newpath) #endif /* CONFIG_DISABLE_MOUNTPOINT */ #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS { - ret = pseudorename(oldpath, oldinode, newpath); + ret = pseudorename(oldpath, oldinode, olddesc.parent, newpath); } #else { diff --git a/fs/vfs/fs_unlink.c b/fs/vfs/fs_unlink.c index 8726610a260..a8c70f66b86 100644 --- a/fs/vfs/fs_unlink.c +++ b/fs/vfs/fs_unlink.c @@ -121,6 +121,14 @@ int nx_unlink(FAR const char *pathname) goto errout_with_inode; } + /* Verify parent-directory write permission before unlink. */ + + ret = inode_checkdirperm(desc.parent, W_OK); + if (ret < 0) + { + goto errout_with_inode; + } + /* Notify the driver that it has been unlinked. If there are no * open references to the driver instance, then the driver should * release all resources because it is no longer accessible. From 065da307f53e494ba4da1bfb164bc8afe7e5a5f0 Mon Sep 17 00:00:00 2001 From: nicolasWDC Date: Mon, 8 Jun 2026 09:36:53 +0000 Subject: [PATCH 015/268] include/cxx/cmath: Define FLT_EVAL_METHOD from compiler builtin Some GCC-based external toolchains define **FLT_EVAL_METHOD** but do not leave the standard FLT_EVAL_METHOD macro visible when the NuttX cmath shim evaluates its guards. As a result, C math symbols such as log and pow are declared by NuttX math.h, but are not imported into namespace std by include/cxx/cmath. Define FLT_EVAL_METHOD locally from **FLT_EVAL_METHOD** when needed in the non-CONFIG_LIBM_TOOLCHAIN path. This fixes compilation of valid C++ code using std::log and std::pow with arm-none-eabi-g++. Signed-off-by: nicolasWDC --- include/cxx/cmath | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/cxx/cmath b/include/cxx/cmath index 719e625324f..a2fc0844295 100644 --- a/include/cxx/cmath +++ b/include/cxx/cmath @@ -41,6 +41,10 @@ # include +# if !defined(FLT_EVAL_METHOD) && defined(__FLT_EVAL_METHOD__) +# define FLT_EVAL_METHOD __FLT_EVAL_METHOD__ +# endif + #undef signbit #undef fpclassify #undef isfinite From 5844ff5abb82f59862822e391fe7a6f4a42fa2f1 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Fri, 5 Jun 2026 13:22:08 +0300 Subject: [PATCH 016/268] sched/misc/assert: Small flash-saving fixes - Use shared string for "stack pointer out of range" to avoid duplicate in flash - Re-use already calculated stack_used instead of calling up_check_tcbstack again Signed-off-by: Jukka Laitinen --- sched/misc/assert.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/sched/misc/assert.c b/sched/misc/assert.c index 128046ccc61..ab6c47bbd4c 100644 --- a/sched/misc/assert.c +++ b/sched/misc/assert.c @@ -168,6 +168,11 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg) #ifdef CONFIG_ARCH_STACKDUMP +static void sp_out_of_range(uintptr_t sp) +{ + _alert("ERROR: Stack pointer %" PRIxPTR " is not within the stack\n", sp); +} + /**************************************************************************** * Name: stack_dump ****************************************************************************/ @@ -285,8 +290,7 @@ static void dump_stacks(FAR struct tcb_s *rtcb, uintptr_t sp) else { force = true; - _alert("ERROR: Stack pointer %" PRIxPTR "is not within the stack\n", - sp); + sp_out_of_range(sp); } #if CONFIG_ARCH_INTERRUPTSTACK > 0 @@ -309,8 +313,7 @@ static void dump_stacks(FAR struct tcb_s *rtcb, uintptr_t sp) up_getusrsp((FAR void *)running_regs()) : 0; if (tcbstack_sp < tcbstack_base || tcbstack_sp >= tcbstack_top) { - _alert("ERROR: Stack pointer %" PRIxPTR " is not within the" - " stack\n", tcbstack_sp); + sp_out_of_range(tcbstack_sp); tcbstack_sp = 0; force = true; @@ -436,7 +439,7 @@ static void dump_task(FAR struct tcb_s *tcb, FAR void *arg) , tcb->stack_base_ptr , tcb->adj_stack_size #ifdef CONFIG_STACK_COLORATION - , up_check_tcbstack(tcb, tcb->adj_stack_size) + , stack_used , stack_filled / 10, stack_filled % 10 , (stack_filled >= 10 * 80 ? '!' : ' ') #endif From 40bbf67bd3aacc13a74c3a5bcee9fbb27d9117dd Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Thu, 4 Jun 2026 15:51:52 +0300 Subject: [PATCH 017/268] sched/misc/assert: Add CONFIG_SCHED_DUMP_TASKS and CONFIG_SCHED_DUMP_STACK Add more refined options for sched/misc/assert to control how verbose crash dumps are printed out: - SCHED_DUMP_TASKS - SCHED_DUMP_STACK These default to y unless DEFAULT_SMALL is defined. The options can be undefined to save flash space on a small system. Signed-off-by: Jukka Laitinen --- Kconfig | 22 ++++++++++++++++++++++ sched/misc/assert.c | 16 +++++++++------- 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/Kconfig b/Kconfig index def0bcf71a0..b7d2e6f49c6 100644 --- a/Kconfig +++ b/Kconfig @@ -733,6 +733,28 @@ config DEBUG_ALERT bool default n +config SCHED_DUMP_TASKS + bool "Include dumping the task info table in assert/crash output" + default !DEFAULT_SMALL + depends on DEBUG_ALERT + ---help--- + Selects whether the per-task table is printed as part of the + crash dump. + + Defaults to y unless DEFAULT_SMALL is selected. + +config SCHED_DUMP_STACK + bool "Include stack content in assert/crash output" + default !DEFAULT_SMALL + depends on DEBUG_ALERT && ARCH_STACKDUMP + ---help--- + When enabled, the crash dump prints the contents of each stack + (IRQ / kernel / user) as hex words. + + When disabled, only base and size are printed out for each stack. + + Defaults to y unless DEFAULT_SMALL is selected. + config DEBUG_FEATURES bool "Enable Debug Features" default n diff --git a/sched/misc/assert.c b/sched/misc/assert.c index ab6c47bbd4c..57db0448f1f 100644 --- a/sched/misc/assert.c +++ b/sched/misc/assert.c @@ -118,7 +118,7 @@ static spinlock_t g_assert_lock = SP_UNLOCKED; static uintptr_t g_last_regs[CONFIG_SMP_NCPUS][XCPTCONTEXT_REGS] aligned_data(XCPTCONTEXT_ALIGN); -#ifdef CONFIG_DEBUG_ALERT +#ifdef CONFIG_SCHED_DUMP_TASKS static FAR const char * const g_policy[4] = { "FIFO", "RR", "SPORADIC" @@ -173,6 +173,7 @@ static void sp_out_of_range(uintptr_t sp) _alert("ERROR: Stack pointer %" PRIxPTR " is not within the stack\n", sp); } +#ifdef CONFIG_SCHED_DUMP_STACK /**************************************************************************** * Name: stack_dump ****************************************************************************/ @@ -192,6 +193,7 @@ static void stack_dump(uintptr_t sp, uintptr_t stack_top) DUMP_PTR(ptr, 5), DUMP_PTR(ptr , 6), DUMP_PTR(ptr, 7)); } } +#endif /**************************************************************************** * Name: dump_stackinfo @@ -200,14 +202,14 @@ static void stack_dump(uintptr_t sp, uintptr_t stack_top) static void dump_stackinfo(FAR const char *tag, uintptr_t sp, uintptr_t base, size_t size, size_t used) { - uintptr_t top = base + size; - _alert("%s Stack:\n", tag); _alert(" base: %p\n", (FAR void *)base); _alert(" size: %08zu\n", size); +#ifdef CONFIG_SCHED_DUMP_STACK if (sp != 0) { + uintptr_t top = base + size; _alert(" sp: %p\n", (FAR void *)sp); /* Get more information */ @@ -237,6 +239,7 @@ static void dump_stackinfo(FAR const char *tag, uintptr_t sp, stack_dump(base, base + size); } +#endif } /**************************************************************************** @@ -346,10 +349,9 @@ static void dump_stacks(FAR struct tcb_s *rtcb, uintptr_t sp) ); } } - #endif -#ifdef CONFIG_DEBUG_ALERT +#ifdef CONFIG_SCHED_DUMP_TASKS /**************************************************************************** * Name: dump_task ****************************************************************************/ @@ -481,6 +483,7 @@ static void dump_fdlist(FAR struct tcb_s *tcb, FAR void *arg) static void dump_tasks(void) { +#ifdef CONFIG_SCHED_DUMP_TASKS #if CONFIG_ARCH_INTERRUPTSTACK > 0 int cpu; #endif @@ -551,9 +554,8 @@ static void dump_tasks(void) } #endif -#ifdef CONFIG_DEBUG_ALERT nxsched_foreach(dump_task, NULL); -#endif +#endif /* CONFIG_SCHED_DUMP_TASKS */ #ifdef CONFIG_SCHED_BACKTRACE nxsched_foreach(dump_backtrace, NULL); From f3e62b837bfa5abf12c0cff3f1c58e5f804c72e0 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Tue, 9 Jun 2026 10:13:19 +0300 Subject: [PATCH 018/268] Documentation: Add documentation of SCHED_DUMP_TASKS and SCHED_DUMP_STACK Add documentation for controlling the crash dump verbosity. Signed-off-by: Jukka Laitinen --- .../debugging/disabling_stackdumpdebug.rst | 36 ++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/Documentation/debugging/disabling_stackdumpdebug.rst b/Documentation/debugging/disabling_stackdumpdebug.rst index 7921480118c..0a2e7822bb1 100644 --- a/Documentation/debugging/disabling_stackdumpdebug.rst +++ b/Documentation/debugging/disabling_stackdumpdebug.rst @@ -12,4 +12,38 @@ the board configuration: .. code-block:: c - CONFIG_ARCH_STACKDUMP=n \ No newline at end of file + CONFIG_ARCH_STACKDUMP=n + +Reducing the Crash Dump Verbosity +================================= + +In addition to ``CONFIG_ARCH_STACKDUMP``, which controls whether the +architecture-specific stack dump is produced at all, two finer-grained +options are available to tune how verbose the assertion / crash output +from ``sched/misc/assert.c`` is. Disabling them is useful to reduce +flash usage on small targets and to keep the crash log short. + +Both options default to ``y`` unless ``CONFIG_DEFAULT_SMALL`` is +selected, in which case they default to ``n``. + +CONFIG_SCHED_DUMP_TASKS +----------------------- + +Controls whether the per-task information table (task list with PID, +priority, scheduling policy, stack usage, state, etc.) is printed as +part of the crash dump. + +.. code-block:: c + + CONFIG_SCHED_DUMP_TASKS=n /* Omit the task table from the crash dump */ + +CONFIG_SCHED_DUMP_STACK +----------------------- + +Controls whether the contents of each stack (IRQ / kernel / user) are +dumped as hex words. When disabled, only the base address and size of +each stack are printed; the stack memory itself is not dumped. + +.. code-block:: c + + CONFIG_SCHED_DUMP_STACK=n /* Omit the hex stack contents from the dump */ From 2c606a7b41f5ca8c9cf04ae0d4b22b1e8d7cdbcd Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 7 May 2025 11:32:53 +0200 Subject: [PATCH 019/268] !sensors/bme680: allow sensor configuration during registration BREAKING CHANGE: bme680_register() takes an additional "*config" argument. When config is NULL - driver behavior is the same as before. With this change bme680 can be configured during registration in board logic. This way we don't have to callibrate sensor from user-space but sensor is ready to use after registration. This change makes the registration the same as for bme688, which is a similar sensor. Signed-off-by: raiden00pl --- boards/xtensa/esp32/common/src/esp32_bme680.c | 2 +- drivers/sensors/bme680_uorb.c | 213 ++++++++++++------ include/nuttx/sensors/bme680.h | 3 +- 3 files changed, 148 insertions(+), 70 deletions(-) diff --git a/boards/xtensa/esp32/common/src/esp32_bme680.c b/boards/xtensa/esp32/common/src/esp32_bme680.c index d7472fdff2e..ab01783df2c 100644 --- a/boards/xtensa/esp32/common/src/esp32_bme680.c +++ b/boards/xtensa/esp32/common/src/esp32_bme680.c @@ -74,7 +74,7 @@ int board_bme680_initialize(int devno, int busno) * available controllers. */ - ret = bme680_register(devno, i2c); + ret = bme680_register(devno, i2c, NULL); if (ret < 0) { snerr("ERROR: Error registering BME680 in I2C%d\n", busno); diff --git a/drivers/sensors/bme680_uorb.c b/drivers/sensors/bme680_uorb.c index b4dece225ab..3b8c00ac11f 100644 --- a/drivers/sensors/bme680_uorb.c +++ b/drivers/sensors/bme680_uorb.c @@ -402,6 +402,7 @@ static int bme680_calibrate(FAR struct sensor_lowerhalf_s *lower, static int bme680_control(FAR struct sensor_lowerhalf_s *lower, FAR struct file *filep, int cmd, unsigned long arg); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -791,6 +792,10 @@ static int bme680_set_oversamp(FAR struct bme680_dev_s *priv) } #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS +/**************************************************************************** + * Name: bme680_push_press_data + ****************************************************************************/ + static int bme680_push_press_data(FAR struct bme680_dev_s *priv, FAR struct bme680_data_s *data) { @@ -815,6 +820,10 @@ static int bme680_push_press_data(FAR struct bme680_dev_s *priv, return OK; } #else +/**************************************************************************** + * Name: bme680_push_temp_data + ****************************************************************************/ + static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, FAR struct bme680_data_s *data) { @@ -839,6 +848,10 @@ static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, #endif /* !CONFIG_BME680_DISABLE_PRESS_MEAS */ #ifndef CONFIG_BME680_DISABLE_HUM_MEAS +/**************************************************************************** + * Name: bme680_push_hum_data + ****************************************************************************/ + static int bme680_push_hum_data(FAR struct bme680_dev_s *priv, FAR struct bme680_data_s *data) { @@ -863,6 +876,10 @@ static int bme680_push_hum_data(FAR struct bme680_dev_s *priv, #endif /* !CONFIG_BME680_DISABLE_HUM_MEAS */ #ifndef CONFIG_BME680_DISABLE_GAS_MEAS +/**************************************************************************** + * Name: bme680_push_gas_data + ****************************************************************************/ + static int bme680_push_gas_data(FAR struct bme680_dev_s *priv, FAR struct bme680_data_s *data) { @@ -965,6 +982,10 @@ static uint8_t calc_heater_dur(FAR const struct bme680_dev_s *priv) return gas_wait_val; } +/**************************************************************************** + * Name: bme680_set_gas_config + ****************************************************************************/ + static int bme680_set_gas_config(FAR struct bme680_dev_s *priv) { int ret; @@ -1081,6 +1102,77 @@ err_out: return ret; } +/**************************************************************************** + * Name: bme680_configure + ****************************************************************************/ + +static int bme680_configure(FAR struct bme680_dev_s *priv, + FAR struct bme680_config_s *config) +{ + int ret; + + /* Sanity checks */ + + if (!CHECK_OS_BOUNDS(config->temp_os)) + { + return -EINVAL; + } + +#ifndef CONFIG_BME680_DISABLE_PRESS_MEAS + if (!CHECK_OS_BOUNDS(config->press_os)) + { + return -EINVAL; + } +#endif + +#ifndef CONFIG_BME680_DISABLE_HUM_MEAS + if (!CHECK_OS_BOUNDS(config->hum_os)) + { + return -EINVAL; + } +#endif + +#ifdef CONFIG_BME680_ENABLE_IIR_FILTER + if (config->filter_coef < BME680_FILTER_COEF0 || + config->filter_coef > BME680_FILTER_COEF127) + { + return -EINVAL; + } +#endif + +#ifndef CONFIG_BME680_DISABLE_GAS_MEAS + if (config->target_temp < MIN_HOT_PLATE_TEMP || + config->target_temp > MAX_HOT_PLATE_TEMP) + { + return -EINVAL; + } + + if (config->nb_conv > 9) + { + return -EINVAL; + } +#endif + + /* Update config in priv */ + + memcpy(&priv->dev.config, config, sizeof(struct bme680_config_s)); + + ret = bme680_write_config(priv); + if (ret < 0) + { + snerr("Failed to calibrate sensor.\n"); + return ret; + } + + priv->dev.calibrated = true; + + return ret; +} + +/**************************************************************************** + * Name: bme680_comp_temp + ****************************************************************************/ + static float bme680_comp_temp(FAR struct bme680_dev_s *priv, uint32_t adc_temp) { @@ -1107,6 +1199,10 @@ static float bme680_comp_temp(FAR struct bme680_dev_s *priv, } #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS +/**************************************************************************** + * Name: bme680_comp_press + ****************************************************************************/ + static float bme680_comp_press(FAR struct bme680_dev_s *priv, uint32_t adc_press) { @@ -1144,6 +1240,10 @@ static float bme680_comp_press(FAR struct bme680_dev_s *priv, #endif /* !CONFIG_BME680_DISABLE_PRESS_MEAS */ #ifndef CONFIG_BME680_DISABLE_HUM_MEAS +/**************************************************************************** + * Name: bme680_comp_hum + ****************************************************************************/ + static float bme680_comp_hum(FAR struct bme680_dev_s *priv, uint16_t adc_hum) { @@ -1187,6 +1287,10 @@ static float bme680_comp_hum(FAR struct bme680_dev_s *priv, #endif /* !CONFIG_BME680_DISABLE_HUM_MEAS */ #ifndef CONFIG_BME680_DISABLE_GAS_MEAS +/**************************************************************************** + * Name: bme680_calc_gas_res + ****************************************************************************/ + static float bme680_calc_gas_res(FAR struct bme680_dev_s *priv, uint16_t adc_gas_res, uint8_t gas_range) { @@ -1209,7 +1313,7 @@ static float bme680_calc_gas_res(FAR struct bme680_dev_s *priv, * * Description: * Reads the raw data from the sensor and computes the compensated - * values, storing them in the data struct. + * values, storing them in the data struct. * ****************************************************************************/ @@ -1239,7 +1343,6 @@ static int bme680_read_measurements(FAR struct bme680_dev_s *priv, uint8_t data_regs[BME680_DATA_LEN]; ret = bme680_getregs(priv, BME680_DATA_ADDR, data_regs, BME680_DATA_LEN); - if (ret < 0) { snerr("Failed to read data registers.\n"); @@ -1285,7 +1388,6 @@ static int bme680_read_measurements(FAR struct bme680_dev_s *priv, /* Is measured gas valid? */ gas_valid = data_regs[14] & BME680_GASM_VALID_MSK; - if (!gas_valid) { sninfo("Invalid gas measurement.\n"); @@ -1293,7 +1395,6 @@ static int bme680_read_measurements(FAR struct bme680_dev_s *priv, } heat_stab = data_regs[14] & BME680_HEAT_STAB_MSK; - if (!heat_stab) { sninfo("The heater did not stabilize.\n"); @@ -1313,7 +1414,7 @@ static int bme680_read_measurements(FAR struct bme680_dev_s *priv, * * Description: * Compute the duration of a tphg cycle in us, taking into consideration - * the settings of the sensor. + * the settings of the sensor. * ****************************************************************************/ @@ -1362,6 +1463,10 @@ static uint16_t bme680_get_tphg_dur(FAR struct bme680_dev_s *priv) return duration; } +/**************************************************************************** + * Name: bme680_activate + ****************************************************************************/ + static int bme680_activate(FAR struct sensor_lowerhalf_s *lower, FAR struct file *filep, bool enable) { @@ -1405,7 +1510,6 @@ static int bme680_activate(FAR struct sensor_lowerhalf_s *lower, if (!priv->enabled && enable) { - dev->calibrated = false; priv->enabled = enable; /* Wake up the polling thread */ @@ -1420,6 +1524,10 @@ static int bme680_activate(FAR struct sensor_lowerhalf_s *lower, return OK; } +/**************************************************************************** + * Name: bme680_calibrate + ****************************************************************************/ + static int bme680_calibrate(FAR struct sensor_lowerhalf_s *lower, FAR struct file *filep, unsigned long arg) { @@ -1427,7 +1535,6 @@ static int bme680_calibrate(FAR struct sensor_lowerhalf_s *lower, FAR struct bme680_sensor_s *dev; FAR struct bme680_dev_s *priv; FAR struct bme680_config_s *calibval = (FAR struct bme680_config_s *)arg; - int ret; /* Get offset inside array of lowerhalfs */ @@ -1459,65 +1566,13 @@ static int bme680_calibrate(FAR struct sensor_lowerhalf_s *lower, priv = container_of(dev, FAR struct bme680_dev_s, dev); - /* Sanity checks */ - - if (!CHECK_OS_BOUNDS(calibval->temp_os)) - { - return -EINVAL; - } - -#ifndef CONFIG_BME680_DISABLE_PRESS_MEAS - if (!CHECK_OS_BOUNDS(calibval->press_os)) - { - return -EINVAL; - } -#endif - -#ifndef CONFIG_BME680_DISABLE_HUM_MEAS - if (!CHECK_OS_BOUNDS(calibval->hum_os)) - { - return -EINVAL; - } -#endif - -#ifdef CONFIG_BME680_ENABLE_IIR_FILTER - if (calibval->filter_coef < BME680_FILTER_COEF0 || - calibval->filter_coef > BME680_FILTER_COEF127) - { - return -EINVAL; - } -#endif - -#ifndef CONFIG_BME680_DISABLE_GAS_MEAS - if (calibval->target_temp < MIN_HOT_PLATE_TEMP || - calibval->target_temp > MAX_HOT_PLATE_TEMP) - { - return -EINVAL; - } - - if (calibval->nb_conv > 9) - { - return -EINVAL; - } -#endif - - /* Update config in priv */ - - memcpy(&priv->dev.config, calibval, sizeof(struct bme680_config_s)); - - ret = bme680_write_config(priv); - - if (ret < 0) - { - snerr("Failed to calibrate sensor.\n"); - return ret; - } - - priv->dev.calibrated = true; - - return ret; + return bme680_configure(priv, calibval); } +/**************************************************************************** + * Name: bme680_control + ****************************************************************************/ + static int bme680_control(FAR struct sensor_lowerhalf_s *lower, FAR struct file *filep, int cmd, unsigned long arg) @@ -1557,6 +1612,10 @@ static int bme680_control(FAR struct sensor_lowerhalf_s *lower, return OK; } +/**************************************************************************** + * Name: bme680_thread + ****************************************************************************/ + static int bme680_thread(int argc, char **argv) { FAR struct bme680_dev_s *priv = @@ -1623,15 +1682,20 @@ static int bme680_thread(int argc, char **argv) * * Description: * Register the BME680 character device - * @devno - The user-specified device number, starting from 0 - * @i2c - An instance of the I2C interface to use to communicate with + * + * Input Parameters: + * devno - The user-specified device number, starting from 0 + * i2c - An instance of the I2C interface to use to communicate with * BME680 + * config - optional sensor initial configuration * * Return value: * Zero (OK) on success; a negated errno value on failure + * ****************************************************************************/ -int bme680_register(int devno, FAR struct i2c_master_s *i2c) +int bme680_register(int devno, FAR struct i2c_master_s *i2c, + FAR struct bme680_config_s *config) { FAR struct sensor_lowerhalf_s *lower; FAR struct bme680_dev_s *priv; @@ -1668,13 +1732,26 @@ int bme680_register(int devno, FAR struct i2c_master_s *i2c) /* Get Calibration Data */ ret = bme680_get_calib_data(priv); - if (ret < 0) { snerr("Failed to read calib data from bme680:%d\n", ret); goto err_init; } + /* Sensor configuration */ + + priv->dev.calibrated = false; + + if (config) + { + ret = bme680_configure(priv, config); + if (ret < 0) + { + snerr("Failed to configure bme680:%d\n", ret); + goto err_init; + } + } + #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS /* Register the barometer driver */ diff --git a/include/nuttx/sensors/bme680.h b/include/nuttx/sensors/bme680.h index 30c16ccf0c8..1b2a0757c23 100644 --- a/include/nuttx/sensors/bme680.h +++ b/include/nuttx/sensors/bme680.h @@ -127,7 +127,8 @@ extern "C" * ****************************************************************************/ -int bme680_register(int devno, FAR struct i2c_master_s *i2c); +int bme680_register(int devno, FAR struct i2c_master_s *i2c, + FAR struct bme680_config_s *config); #undef EXTERN #ifdef __cplusplus From 165e7cb1ab7306bd09490a07b9bebce923026488 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 10:49:16 +0200 Subject: [PATCH 020/268] arch/arm/stm32f3/stm32f33xxx_pinmap.h: fix compilation fix compilation error Signed-off-by: raiden00pl --- arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h index 3d3be1182a6..629efe26b24 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h @@ -150,7 +150,7 @@ /* JTAG/SWD */ #define GPIO_JTDI_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15) -#define GPIO_JTDO_TRACES_WO_0GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) +#define GPIO_JTDO_TRACES_WO_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3) #define GPIO_NJTRST_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4) #define GPIO_SWCLK_JTCK_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14) #define GPIO_SWDIO_JTMS_0 (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13) From 0a9cb6538c8125b25864877eeca52c7fbc9a0a4d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 10:49:16 +0200 Subject: [PATCH 021/268] boards/arm/stm32f4/stm32f401rc-rs485: fix compilation fix compilation error Signed-off-by: raiden00pl --- boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c index a8a60d7a591..a31a7a7174a 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c @@ -66,8 +66,8 @@ static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = { - GPIO_ADC\1_IN\2_0, - GPIO_ADC\1_IN\2_0 + GPIO_ADC1_IN0_0, + GPIO_ADC1_IN4_0 }; /**************************************************************************** From 794f0c2ce93355bdf29341b89436218c6d94e77a Mon Sep 17 00:00:00 2001 From: nicolasWDC Date: Mon, 8 Jun 2026 20:07:31 +0000 Subject: [PATCH 022/268] include/cxx/ctime: Add localtime to std namespace. NuttX time.h declares localtime in the global namespace, but the C++ ctime shim does not import it into namespace std. As a result, valid C++ code using std::localtime fails to compile with the NuttX C++ headers, even though ::localtime is available. Add using ::localtime to include/cxx/ctime. Signed-off-by: nicolasWDC --- include/cxx/ctime | 1 + 1 file changed, 1 insertion(+) diff --git a/include/cxx/ctime b/include/cxx/ctime index 45b9aadcf64..fa9d2fc211e 100644 --- a/include/cxx/ctime +++ b/include/cxx/ctime @@ -46,6 +46,7 @@ namespace std using ::clock_settime; using ::clock_gettime; using ::mktime; + using ::localtime; using ::gmtime_r; using ::gmtime; using ::strftime; From 64b6bbb0c07c17f7238a5f8e67fadd9bd6c314fa Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Tue, 9 Jun 2026 13:50:33 +0300 Subject: [PATCH 023/268] sched/Kconfig: Fix ETC_ROMFS dependency When using FS_CROMFS for etc, user typically don't need FS_ROMFS, they are completely separate filesystems. But both ETC_ROMFS and ETC_CROMFS are needed, the first one selects that the ETC needs to be mounted from ROM based filesystem, and ETC_CROMFS just specifies that the backing filesystem is actually the CROMFS. Iow; make ETC_ROMFS depend on FS_ROMFS || FS_CROMFS, so that the user can drop FS_ROMFS when only FS_CROMFS is needed. Signed-off-by: Jukka Laitinen --- sched/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sched/Kconfig b/sched/Kconfig index a2c6fbff12f..9b4ed4c82c8 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -534,9 +534,9 @@ endif # INIT_FILE menuconfig ETC_ROMFS bool "Auto-mount etc baked-in ROMFS image" default n - depends on !DISABLE_MOUNTPOINT && FS_ROMFS + depends on !DISABLE_MOUNTPOINT && (FS_ROMFS || FS_CROMFS) ---help--- - Mount a ROMFS filesystem at /etc and provide a system init + Mount a ROMFS or a CROMFS filesystem at /etc and provide a system init script at /etc/init.d/rc.sysinit and a startup script at /etc/init.d/rcS. The default system init script mounts /tmp as TMPFS when FS_TMPFS is enabled, otherwise it can From 8021b5371e022a225825827ecbabe01703d32b3a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sat, 10 May 2025 08:36:18 +0200 Subject: [PATCH 024/268] sensors/bme680_uorb.c: always allow temperature topic registration Previously bme680 dont register temperature topic when pressure measurement was enabled. Temperature data is present in barometer data, but sometimes we need clear separation between these topics. The old behavior is still achievable by setting CONFIG_BME680_DISABLE_TEMP_MEAS=y Signed-off-by: raiden00pl --- drivers/sensors/Kconfig | 6 ++ drivers/sensors/bme680_uorb.c | 106 ++++++++++++++++++---------------- 2 files changed, 63 insertions(+), 49 deletions(-) diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index 4f6a42714d7..e09077d745d 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -617,6 +617,12 @@ config BME680_I2C_FREQUENCY int "BME680 I2C frequency" default 400000 +config BME680_DISABLE_TEMP_MEAS + bool "Disable Temperature Measurement" + default n + ---help--- + If enabled, the sensor will not measure temperature. + config BME680_DISABLE_PRESS_MEAS bool "Disable Pressure Measurement" default n diff --git a/drivers/sensors/bme680_uorb.c b/drivers/sensors/bme680_uorb.c index 3b8c00ac11f..11f04ea854a 100644 --- a/drivers/sensors/bme680_uorb.c +++ b/drivers/sensors/bme680_uorb.c @@ -61,7 +61,7 @@ /* Sub-sensor definitions */ -#ifdef CONFIG_BME680_DISABLE_PRESS_MEAS +#ifndef CONFIG_BME680_DISABLE_TEMP_MEAS # define BME680_TEMP_IDX (0) #else # define BME680_TEMP_IDX (-1) @@ -373,12 +373,14 @@ static int bme680_putreg8(FAR struct bme680_dev_s *priv, uint8_t regaddr, static int bme680_getregs(FAR struct bme680_dev_s *priv, uint8_t regaddr, uint8_t *rxbuffer, uint8_t length); +#ifndef CONFIG_BME680_DISABLE_TEMP_MEAS +static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, + FAR struct bme680_data_s *data); +#endif + #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS static int bme680_push_press_data(FAR struct bme680_dev_s *priv, FAR struct bme680_data_s *data); -#else -static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, - FAR struct bme680_data_s *data); #endif #ifndef CONFIG_BME680_DISABLE_HUM_MEAS @@ -409,18 +411,20 @@ static int bme680_control(FAR struct sensor_lowerhalf_s *lower, static const push_data_func deliver_data[BME680_SENSORS_COUNT] = { +#ifndef CONFIG_BME680_DISABLE_TEMP_MEAS + bme680_push_temp_data, +#endif + #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS - bme680_push_press_data -#else - bme680_push_temp_data + bme680_push_press_data, #endif #ifndef CONFIG_BME680_DISABLE_HUM_MEAS - , bme680_push_hum_data + bme680_push_hum_data, #endif #ifndef CONFIG_BME680_DISABLE_GAS_MEAS - , bme680_push_gas_data + bme680_push_gas_data, #endif }; @@ -791,6 +795,34 @@ static int bme680_set_oversamp(FAR struct bme680_dev_s *priv) return OK; } +#ifndef CONFIG_BME680_DISABLE_TEMP_MEAS +/**************************************************************************** + * Name: bme680_push_temp_data + ****************************************************************************/ + +static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, + FAR struct bme680_data_s *data) +{ + struct sensor_temp temp_data; + int ret; + + struct sensor_lowerhalf_s lower = priv->dev.lower[BME680_TEMP_IDX]; + + temp_data.timestamp = data->timestamp; + temp_data.temperature = data->temperature; + + ret = lower.push_event(lower.priv, &temp_data, sizeof(struct sensor_temp)); + + if (ret < 0) + { + snerr("Pushing temperature data failed\n"); + return ret; + } + + return OK; +} +#endif /* !CONFIG_BME680_DISABLE_TEMP_MEAS */ + #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS /**************************************************************************** * Name: bme680_push_press_data @@ -819,32 +851,6 @@ static int bme680_push_press_data(FAR struct bme680_dev_s *priv, return OK; } -#else -/**************************************************************************** - * Name: bme680_push_temp_data - ****************************************************************************/ - -static int bme680_push_temp_data(FAR struct bme680_dev_s *priv, - FAR struct bme680_data_s *data) -{ - struct sensor_temp temp_data; - int ret; - - struct sensor_lowerhalf_s lower = priv->dev.lower[BME680_TEMP_IDX]; - - temp_data.timestamp = data->timestamp; - temp_data.temperature = data->temperature; - - ret = lower.push_event(lower.priv, &temp_data, sizeof(struct sensor_temp)); - - if (ret < 0) - { - snerr("Pushing temperature data failed\n"); - return ret; - } - - return OK; -} #endif /* !CONFIG_BME680_DISABLE_PRESS_MEAS */ #ifndef CONFIG_BME680_DISABLE_HUM_MEAS @@ -1752,6 +1758,22 @@ int bme680_register(int devno, FAR struct i2c_master_s *i2c, } } +#ifndef CONFIG_BME680_DISABLE_TEMP_MEAS + /* Register the temperature driver */ + + lower = &priv->dev.lower[BME680_TEMP_IDX]; + lower->ops = &g_sensor_ops; + lower->type = SENSOR_TYPE_AMBIENT_TEMPERATURE; + + ret = sensor_register(lower, devno); + if (ret < 0) + { + snerr("ERROR: Failed to register temperature driver (err = %d)\n", + ret); + goto err_init; + } +#endif + #ifndef CONFIG_BME680_DISABLE_PRESS_MEAS /* Register the barometer driver */ @@ -1766,20 +1788,6 @@ int bme680_register(int devno, FAR struct i2c_master_s *i2c, ret); goto err_init; } -#else - /* Register the temperature driver */ - - lower = &priv->dev.lower[BME680_TEMP_IDX]; - lower->ops = &g_sensor_ops; - lower->type = SENSOR_TYPE_AMBIENT_TEMPERATURE; - - ret = sensor_register(lower, devno); - if (ret < 0) - { - snerr("ERROR: Failed to register temperature driver (err = %d)\n", - ret); - goto err_init; - } #endif #ifndef CONFIG_BME680_DISABLE_HUM_MEAS From 46cc145645fbbfa75c6a9a9c7bbc306b580b5082 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 8 Mar 2024 14:13:11 +0100 Subject: [PATCH 025/268] thingy91: initial sensors support initial sensors support for thingy91 Signed-off-by: raiden00pl --- .../arm/nrf91/boards/thingy91/index.rst | 18 +- .../arm/nrf91/common/include/nrf91_adxl362.h | 40 ++++ .../arm/nrf91/common/include/nrf91_adxl372.h | 40 ++++ .../nrf91/common/include/nrf91_bh1749nuc.h | 40 ++++ .../arm/nrf91/common/include/nrf91_bme680.h | 40 ++++ boards/arm/nrf91/common/src/CMakeLists.txt | 16 ++ boards/arm/nrf91/common/src/Make.defs | 16 ++ boards/arm/nrf91/common/src/nrf91_adxl362.c | 68 ++++++ boards/arm/nrf91/common/src/nrf91_adxl372.c | 68 ++++++ boards/arm/nrf91/common/src/nrf91_bh1749nuc.c | 80 +++++++ boards/arm/nrf91/common/src/nrf91_bme680.c | 89 ++++++++ .../thingy91/configs/thingy91_rtt/defconfig | 67 ++++++ boards/arm/nrf91/thingy91/src/CMakeLists.txt | 10 +- boards/arm/nrf91/thingy91/src/Make.defs | 10 +- boards/arm/nrf91/thingy91/src/nrf91_boot.c | 6 + boards/arm/nrf91/thingy91/src/nrf91_bringup.c | 14 ++ boards/arm/nrf91/thingy91/src/nrf91_i2c.c | 118 ++++++++++ boards/arm/nrf91/thingy91/src/nrf91_sensors.c | 130 +++++++++++ boards/arm/nrf91/thingy91/src/nrf91_spi.c | 208 ++++++++++++++++++ boards/arm/nrf91/thingy91/src/thingy91.h | 55 ++++- 20 files changed, 1121 insertions(+), 12 deletions(-) create mode 100644 boards/arm/nrf91/common/include/nrf91_adxl362.h create mode 100644 boards/arm/nrf91/common/include/nrf91_adxl372.h create mode 100644 boards/arm/nrf91/common/include/nrf91_bh1749nuc.h create mode 100644 boards/arm/nrf91/common/include/nrf91_bme680.h create mode 100644 boards/arm/nrf91/common/src/nrf91_adxl362.c create mode 100644 boards/arm/nrf91/common/src/nrf91_adxl372.c create mode 100644 boards/arm/nrf91/common/src/nrf91_bh1749nuc.c create mode 100644 boards/arm/nrf91/common/src/nrf91_bme680.c create mode 100644 boards/arm/nrf91/thingy91/configs/thingy91_rtt/defconfig create mode 100644 boards/arm/nrf91/thingy91/src/nrf91_i2c.c create mode 100644 boards/arm/nrf91/thingy91/src/nrf91_sensors.c create mode 100644 boards/arm/nrf91/thingy91/src/nrf91_spi.c diff --git a/Documentation/platforms/arm/nrf91/boards/thingy91/index.rst b/Documentation/platforms/arm/nrf91/boards/thingy91/index.rst index 7e6c1e26312..2af89956ef3 100644 --- a/Documentation/platforms/arm/nrf91/boards/thingy91/index.rst +++ b/Documentation/platforms/arm/nrf91/boards/thingy91/index.rst @@ -19,14 +19,14 @@ GPS No Buttons Yes LEDs No COEX No -PMIC No +PMIC (ADP5360) No I2C 0x46 Battery monitoring No Buzzer No -EEPROM (24CW160) No -Low power accelerometer (ADXL362) No -Hi G accelerometer (ADXL372) No -Air quality sensor (HBME680) No -Color sensor (BH1749NUC) No +EEPROM (24CW160) No I2C 0x50 +Low power accelerometer (ADXL362) No SPI +Hi G accelerometer (ADXL372) No SPI +Air quality sensor (BME680) No I2C 0x76 +Color sensor (BH1749NUC) No I2C 0x38 ================================== ======= ============= Serial Console @@ -39,7 +39,11 @@ Serial Console Configurations ============== -TODO +thingy91_rtt +------------ + +Configuration with a console over RTT, enabling available peripherals +on the board (WIP). Flash & Debug ============= diff --git a/boards/arm/nrf91/common/include/nrf91_adxl362.h b/boards/arm/nrf91/common/include/nrf91_adxl362.h new file mode 100644 index 00000000000..1d177bd3083 --- /dev/null +++ b/boards/arm/nrf91/common/include/nrf91_adxl362.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/arm/nrf91/common/include/nrf91_adxl362.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL362_H +#define __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL362_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_adxl362_init + ****************************************************************************/ + +int nrf91_adxl362_init(int devno, int busno); + +#endif /* __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL362_H */ diff --git a/boards/arm/nrf91/common/include/nrf91_adxl372.h b/boards/arm/nrf91/common/include/nrf91_adxl372.h new file mode 100644 index 00000000000..8663494a5c7 --- /dev/null +++ b/boards/arm/nrf91/common/include/nrf91_adxl372.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/arm/nrf91/common/include/nrf91_adxl372.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL372_H +#define __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL372_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_adxl372_init + ****************************************************************************/ + +int nrf91_adxl372_init(int devno, int busno); + +#endif /* __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_ADXL372_H */ diff --git a/boards/arm/nrf91/common/include/nrf91_bh1749nuc.h b/boards/arm/nrf91/common/include/nrf91_bh1749nuc.h new file mode 100644 index 00000000000..52045ef8330 --- /dev/null +++ b/boards/arm/nrf91/common/include/nrf91_bh1749nuc.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/arm/nrf91/common/include/nrf91_bh1749nuc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BH1749NUC_H +#define __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BH1749NUC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_bh1749nuc_init + ****************************************************************************/ + +int nrf91_bh1749nuc_init(int devno, int busno, uint8_t addr); + +#endif /* __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BH1749NUC_H */ diff --git a/boards/arm/nrf91/common/include/nrf91_bme680.h b/boards/arm/nrf91/common/include/nrf91_bme680.h new file mode 100644 index 00000000000..714595ccf90 --- /dev/null +++ b/boards/arm/nrf91/common/include/nrf91_bme680.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/arm/nrf91/common/include/nrf91_bme680.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BME680_H +#define __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BME680_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_bme680_init + ****************************************************************************/ + +int nrf91_bme680_init(int devno, int busno); + +#endif /* __BOARDS_ARM_NRF91_COMMON_INCLUDE_NRF91_BME680_H */ diff --git a/boards/arm/nrf91/common/src/CMakeLists.txt b/boards/arm/nrf91/common/src/CMakeLists.txt index d800cd1bb0a..3296b72afa4 100644 --- a/boards/arm/nrf91/common/src/CMakeLists.txt +++ b/boards/arm/nrf91/common/src/CMakeLists.txt @@ -38,6 +38,22 @@ if(CONFIG_ARCH_BOARD_COMMON) list(APPEND SRCS nrf91_reset.c) endif() + if(CONFIG_SENSORS_BH1749NUC) + list(APPEND SRCS nrf91_bh1749nuc.c) + endif() + + if(CONFIG_SENSORS_BME680) + list(APPEND SRCS nrf91_bme680.c) + endif() + + if(CONFIG_SENSORS_ADXL372) + list(APPEND SRCS nrf91_adxl372.c) + endif() + + if(CONFIG_SENSORS_ADXL362) + list(APPEND SRCS nrf91_adxl362.c) + endif() + target_sources(board PRIVATE ${SRCS}) endif() diff --git a/boards/arm/nrf91/common/src/Make.defs b/boards/arm/nrf91/common/src/Make.defs index 290b73bfa3b..279e7a40728 100644 --- a/boards/arm/nrf91/common/src/Make.defs +++ b/boards/arm/nrf91/common/src/Make.defs @@ -38,6 +38,22 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += nrf91_reset.c endif +ifeq ($(CONFIG_SENSORS_BH1749NUC),y) + CSRCS += nrf91_bh1749nuc.c +endif + +ifeq ($(CONFIG_SENSORS_BME680),y) + CSRCS += nrf91_bme680.c +endif + +ifeq ($(CONFIG_SENSORS_ADXL372),y) + CSRCS += nrf91_adxl372.c +endif + +ifeq ($(CONFIG_SENSORS_ADXL362),y) + CSRCS += nrf91_adxl362.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/nrf91/common/src/nrf91_adxl362.c b/boards/arm/nrf91/common/src/nrf91_adxl362.c new file mode 100644 index 00000000000..9c5e33c5bc6 --- /dev/null +++ b/boards/arm/nrf91/common/src/nrf91_adxl362.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/nrf91/common/src/nrf91_adxl362.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nrf91_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_adxl362_init + ****************************************************************************/ + +int nrf91_adxl362_init(int devno, int busno) +{ + struct spi_dev_s *spi; + int ret; + + sninfo("Initializing ADXL362!\n"); + + /* Initialize SPI */ + + spi = nrf91_spibus_initialize(busno); + if (!spi) + { + return -ENODEV; + } + + /* Then register the barometer sensor */ + + ret = adxl362_register(devno, spi); + if (ret < 0) + { + snerr("ERROR: Error registering ADXL362\n"); + } + + return ret; +} diff --git a/boards/arm/nrf91/common/src/nrf91_adxl372.c b/boards/arm/nrf91/common/src/nrf91_adxl372.c new file mode 100644 index 00000000000..52c342435f7 --- /dev/null +++ b/boards/arm/nrf91/common/src/nrf91_adxl372.c @@ -0,0 +1,68 @@ +/**************************************************************************** + * boards/arm/nrf91/common/src/nrf91_adxl372.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nrf91_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_adxl372_init + ****************************************************************************/ + +int nrf91_adxl372_init(int devno, int busno) +{ + struct spi_dev_s *spi; + int ret; + + sninfo("Initializing ADXL372!\n"); + + /* Initialize SPI */ + + spi = nrf91_spibus_initialize(busno); + if (!spi) + { + return -ENODEV; + } + + /* Then register the barometer sensor */ + + ret = adxl372_register_uorb(devno, spi); + if (ret < 0) + { + snerr("ERROR: Error registering ADXL372\n"); + } + + return ret; +} diff --git a/boards/arm/nrf91/common/src/nrf91_bh1749nuc.c b/boards/arm/nrf91/common/src/nrf91_bh1749nuc.c new file mode 100644 index 00000000000..d8c7006bc7d --- /dev/null +++ b/boards/arm/nrf91/common/src/nrf91_bh1749nuc.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/nrf91/common/src/nrf91_bh1749nuc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nrf91_i2c.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_SENSORS_BH1749NUC_UORB +# error BH1749NUC UORB is only supported +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_bh1749nuc_init + ****************************************************************************/ + +int nrf91_bh1749nuc_init(int devno, int busno, uint8_t addr) +{ + struct bh1749nuc_config_s config; + struct i2c_master_s *i2c; + int ret; + + sninfo("Initializing BH1749NUC!\n"); + + /* Initialize I2C */ + + i2c = nrf91_i2cbus_initialize(busno); + if (!i2c) + { + return -ENODEV; + } + + /* Then register the barometer sensor */ + + config.i2c = i2c; + config.addr = addr; + + ret = bh1749nuc_register_uorb(devno, &config); + if (ret < 0) + { + snerr("ERROR: Error registering BH1749NUC\n"); + } + + return ret; +} diff --git a/boards/arm/nrf91/common/src/nrf91_bme680.c b/boards/arm/nrf91/common/src/nrf91_bme680.c new file mode 100644 index 00000000000..5b0417589d0 --- /dev/null +++ b/boards/arm/nrf91/common/src/nrf91_bme680.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/nrf91/common/src/nrf91_bme680.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "nrf91_i2c.h" + +/**************************************************************************** + * Private data + ****************************************************************************/ + +/* Default measurement configuration. Without a configuration the driver + * never leaves the "not calibrated" state and no measurements are taken. + * Oversampling follows the Bosch "indoor navigation" recommendation; the + * gas heater profile targets 320 C for 150 ms. + */ + +struct bme680_config_s g_bme680_config = +{ + .temp_os = BME680_OS_8X, + .press_os = BME680_OS_4X, + .hum_os = BME680_OS_2X, + .target_temp = 320, + .heater_duration = 150, + .nb_conv = 0, + .amb_temp = 25, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_bme680_init + ****************************************************************************/ + +int nrf91_bme680_init(int devno, int busno) +{ + struct i2c_master_s *i2c; + int ret; + + sninfo("Initializing BME680!\n"); + + /* Initialize I2C */ + + i2c = nrf91_i2cbus_initialize(busno); + if (!i2c) + { + return -ENODEV; + } + + /* Then register the barometer sensor */ + + ret = bme680_register(devno, i2c, &g_bme680_config); + if (ret < 0) + { + snerr("ERROR: Error registering BME680\n"); + } + + return ret; +} diff --git a/boards/arm/nrf91/thingy91/configs/thingy91_rtt/defconfig b/boards/arm/nrf91/thingy91/configs/thingy91_rtt/defconfig new file mode 100644 index 00000000000..5476f2c9f4e --- /dev/null +++ b/boards/arm/nrf91/thingy91/configs/thingy91_rtt/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="thingy91" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_THINGY91=y +CONFIG_ARCH_CHIP="nrf91" +CONFIG_ARCH_CHIP_NRF9160=y +CONFIG_ARCH_CHIP_NRF91=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH_TRUSTZONE_SECURE=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SENSORS=y +CONFIG_DEBUG_SENSORS_ERROR=y +CONFIG_DEBUG_SENSORS_INFO=y +CONFIG_DEBUG_SENSORS_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_UORB=y +CONFIG_EXPERIMENTAL=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NDEBUG=y +CONFIG_NRF91_SPI1_MASTER=y +CONFIG_NRF91_SPI_MASTER_INTERRUPTS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_ADXL372=y +CONFIG_SENSORS_ADXL372_UORB=y +CONFIG_SERIAL_RTT0=y +CONFIG_STACK_CANARIES=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=3 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_RTT=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UORB=y +CONFIG_UORB_ALERT=y +CONFIG_UORB_ERROR=y +CONFIG_UORB_INFO=y +CONFIG_UORB_LISTENER=y +CONFIG_UORB_WARN=y +CONFIG_USENSOR=y diff --git a/boards/arm/nrf91/thingy91/src/CMakeLists.txt b/boards/arm/nrf91/thingy91/src/CMakeLists.txt index 991764c8e78..b3ec909aaf5 100644 --- a/boards/arm/nrf91/thingy91/src/CMakeLists.txt +++ b/boards/arm/nrf91/thingy91/src/CMakeLists.txt @@ -20,12 +20,20 @@ # # ############################################################################## -set(SRCS nrf91_boot.c nrf91_bringup.c) +set(SRCS nrf91_boot.c nrf91_bringup.c nrf91_sensors.c) if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS nrf91_buttons.c) endif() +if(CONFIG_NRF91_SPI_MASTER) + list(APPEND SRCS nrf91_spi.c) +endif() + +if(CONFIG_I2C) + list(APPEND SRCS nrf91_i2c.c) +endif() + if(CONFIG_NRF91_MODEM) list(APPEND SRCS nrf91_modem.c) endif() diff --git a/boards/arm/nrf91/thingy91/src/Make.defs b/boards/arm/nrf91/thingy91/src/Make.defs index 599f6f5a9b8..d68245956ef 100644 --- a/boards/arm/nrf91/thingy91/src/Make.defs +++ b/boards/arm/nrf91/thingy91/src/Make.defs @@ -22,7 +22,7 @@ include $(TOPDIR)/Make.defs -CSRCS = nrf91_boot.c nrf91_bringup.c +CSRCS = nrf91_boot.c nrf91_bringup.c nrf91_sensors.c ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += nrf91_buttons.c @@ -32,6 +32,14 @@ ifeq ($(CONFIG_NRF91_MODEM),y) CSRCS += nrf91_modem.c endif +ifeq ($(CONFIG_NRF91_SPI_MASTER),y) +CSRCS += nrf91_spi.c +endif + +ifeq ($(CONFIG_I2C),y) +CSRCS += nrf91_i2c.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/nrf91/thingy91/src/nrf91_boot.c b/boards/arm/nrf91/thingy91/src/nrf91_boot.c index 0450484bb95..a5e2cdcf4f3 100644 --- a/boards/arm/nrf91/thingy91/src/nrf91_boot.c +++ b/boards/arm/nrf91/thingy91/src/nrf91_boot.c @@ -56,6 +56,12 @@ void nrf91_board_initialize(void) #ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif + +#ifdef CONFIG_NRF91_SPI_MASTER + /* Configure SPI chip selects */ + + nrf91_spidev_initialize(); +#endif } /**************************************************************************** diff --git a/boards/arm/nrf91/thingy91/src/nrf91_bringup.c b/boards/arm/nrf91/thingy91/src/nrf91_bringup.c index 9c80e57eb44..4d52425598d 100644 --- a/boards/arm/nrf91/thingy91/src/nrf91_bringup.c +++ b/boards/arm/nrf91/thingy91/src/nrf91_bringup.c @@ -87,6 +87,10 @@ int nrf91_bringup(void) { int ret; +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + nrf91_i2ctool(); +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -120,6 +124,16 @@ int nrf91_bringup(void) } #endif + /* Initialzie on-board sensors */ + + ret = nrf91_sensors_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize sensors: %d\n", + ret); + } + #ifdef CONFIG_NRF91_MODEM /* Initialize modem */ diff --git a/boards/arm/nrf91/thingy91/src/nrf91_i2c.c b/boards/arm/nrf91/thingy91/src/nrf91_i2c.c new file mode 100644 index 00000000000..d76554d1318 --- /dev/null +++ b/boards/arm/nrf91/thingy91/src/nrf91_i2c.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/nrf91/thingy91/src/nrf91_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#ifdef CONFIG_I2C +# include "nrf91_i2c.h" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef CONFIG_SYSTEM_I2CTOOL +int nrf91_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret = OK; + + i2c = nrf91_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + nrf91_i2cbus_uninitialize(i2c); + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: nrf91_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef CONFIG_SYSTEM_I2CTOOL +int nrf91_i2ctool(void) +{ + int ret = OK; + +#ifdef CONFIG_NRF91_I2C0_MASTER + ret = nrf91_i2c_register(0); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_NRF91_I2C1_MASTER + ret = nrf91_i2c_register(1); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_NRF91_I2C2_MASTER + ret = nrf91_i2c_register(2); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_NRF91_I2C3_MASTER + ret = nrf91_i2c_register(3); + if (ret != OK) + { + return ret; + } +#endif + + return ret; +} +#endif diff --git a/boards/arm/nrf91/thingy91/src/nrf91_sensors.c b/boards/arm/nrf91/thingy91/src/nrf91_sensors.c new file mode 100644 index 00000000000..880c3bb61d7 --- /dev/null +++ b/boards/arm/nrf91/thingy91/src/nrf91_sensors.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/nrf91/thingy91/src/nrf91_sensors.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_SENSORS_BH1749NUC +# include "nrf91_bh1749nuc.h" +#endif + +#ifdef CONFIG_SENSORS_BME680 +# include "nrf91_bme680.h" +#endif + +#ifdef CONFIG_SENSORS_ADXL362 +# include "nrf91_adxl362.h" +#endif + +#ifdef CONFIG_SENSORS_ADXL372 +# include "nrf91_adxl372.h" +#endif + +#include "thingy91.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BH1749NUC_I2C_ADDR 0x38 +#define BH1749NUC_I2C_BUS 2 + +#define BME680_I2C_BUS 2 + +#define ADXL372_SPI_BUS 1 +#define ADXL362_SPI_BUS 1 + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_sensors_init + * + * Description: + * Initialzie on-board sensors + * + ****************************************************************************/ + +int nrf91_sensors_init(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_SENSORS_BH1749NUC + nrf91_gpio_config(GPIO_BH1749_INT); + + /* Initialize BH1749NUC */ + + ret = nrf91_bh1749nuc_init(0, BH1749NUC_I2C_BUS, BH1749NUC_I2C_ADDR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nrf91_bh1749nuc_init failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BME680 + /* Initialize BME680 */ + + ret = nrf91_bme680_init(0, BME680_I2C_BUS); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nrf91_bme680_init failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_ADXL372 + nrf91_gpio_config(GPIO_ADXL372_INT1); + + /* Initialize ADXL372 */ + + ret = nrf91_adxl372_init(ADXL372_SPI_DEVNO, ADXL372_SPI_BUS); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nrf91_adxl372_init failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_ADXL362 + nrf91_gpio_config(GPIO_ADXL362_INT1); + + /* Initialize ADXL362 */ + + ret = nrf91_adxl362_init(ADXL362_SPI_DEVNO, ADXL362_SPI_BUS); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nrf91_adxl362_init failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/nrf91/thingy91/src/nrf91_spi.c b/boards/arm/nrf91/thingy91/src/nrf91_spi.c new file mode 100644 index 00000000000..420b19d6ec9 --- /dev/null +++ b/boards/arm/nrf91/thingy91/src/nrf91_spi.c @@ -0,0 +1,208 @@ +/**************************************************************************** + * boards/arm/nrf91/thingy91/src/nrf91_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "nrf91_gpio.h" +#include "nrf91_spi.h" + +#include "thingy91.h" +#include + +#ifdef CONFIG_NRF91_SPI_MASTER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void nrf91_spidev_initialize(void) +{ +#ifdef CONFIG_NRF91_SPI1_MASTER + nrf91_gpio_config(GPIO_ADXL372_CS); + nrf91_gpio_write(GPIO_ADXL372_CS, true); + + nrf91_gpio_config(GPIO_ADXL362_CS); + nrf91_gpio_write(GPIO_ADXL362_CS, true); +#endif +} + +/**************************************************************************** + * Name: nrf91_spi0/1/2/3/select and nrf91_spi0/1/2/3/status + * + * Description: + * The external functions, nrf91_spi0/1/2/3select and + * nrf91_spi0/1/2/3status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including nrf91_spibus_initialize()) are provided + * by common NRF91 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in nrf91_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide nrf91_spi0/1/2/3select() and nrf91_spi0/1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to nrf91_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by nrf91_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_NRF91_SPI0_MASTER +void nrf91_spi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t nrf91_spi0status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_NRF91_SPI1_MASTER +void nrf91_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", (unsigned long)devid, + selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_SENSORS_ADXL372 + case SPIDEV_ACCELEROMETER(ADXL372_SPI_DEVNO): + { + spiinfo("ADXL372 device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + nrf91_gpio_write(GPIO_ADXL372_CS, !selected); + break; + } +#endif + +#ifdef CONFIG_SENSORS_ADXL362 + case SPIDEV_ACCELEROMETER(ADXL362_SPI_DEVNO): + { + spiinfo("ADXL372 device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + nrf91_gpio_write(GPIO_ADXL362_CS, !selected); + break; + } +#endif + + default: + { + break; + } + } +} + +uint8_t nrf91_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_SENSORS_ADXL372 + case SPIDEV_ACCELEROMETER(ADXL372_SPI_DEVNO): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + +#ifdef CONFIG_SENSORS_ADXL362 + case SPIDEV_ACCELEROMETER(ADXL362_SPI_DEVNO): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif + +#ifdef CONFIG_nrf91_SPI2_MASTER +void nrf91_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t nrf91_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_NRF91_SPI3_MASTER +void nrf91_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t nrf91_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_NRF91_SPI_MASTER */ diff --git a/boards/arm/nrf91/thingy91/src/thingy91.h b/boards/arm/nrf91/thingy91/src/thingy91.h index 381e90736c2..26cef5ca962 100644 --- a/boards/arm/nrf91/thingy91/src/thingy91.h +++ b/boards/arm/nrf91/thingy91/src/thingy91.h @@ -67,12 +67,13 @@ /* Supported devices ********************************************************/ /* ADXL372 - * INT1 - P0.09 - * CS - P0.08 + * INT1 - P0.06 + * CS - P0.07 */ #define GPIO_ADXL372_INT1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(6)) #define GPIO_ADXL372_CS (GPIO_OUTPUT | GPIO_PORT0 | GPIO_PIN(7)) +#define ADXL372_SPI_DEVNO 0 /* ADXL362 * INT1 - P0.09 @@ -81,8 +82,9 @@ #define GPIO_ADXL362_INT1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(9)) #define GPIO_ADXL362_CS (GPIO_OUTPUT | GPIO_PORT0 | GPIO_PIN(8)) +#define ADXL362_SPI_DEVNO 1 -/* BH1749 +/* BH1749NUC * INT - P0.27 */ @@ -121,5 +123,52 @@ int nrf91_bringup(void); +/**************************************************************************** + * Name: nrf91_sensors_init + * + * Description: + * Initialzie on-board sensors + * + ****************************************************************************/ + +int nrf91_sensors_init(void); + +/**************************************************************************** + * Name: nrf91_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C +int nrf91_i2c_register(int bus); +#endif + +/**************************************************************************** + * Name: nrf91_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef CONFIG_SYSTEM_I2CTOOL +int nrf91_i2ctool(void); +#endif + +/**************************************************************************** + * Name: nrf91_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the + * thingy91 board. + * + ****************************************************************************/ + +#ifdef CONFIG_NRF91_SPI_MASTER +void nrf91_spidev_initialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_ARM_NRF91_THINGY91_SRC_THINGY91_H */ From 84f891b8484d647e3785f3bbd40b8a2ee2f91f49 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 10 Jun 2026 09:32:12 +0200 Subject: [PATCH 026/268] drivers/sensors/adxl372_uorb.c: fix compilation error drivers/sensors/adxl372_uorb.c: fix compilation error Signed-off-by: raiden00pl --- drivers/sensors/adxl372_uorb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/sensors/adxl372_uorb.c b/drivers/sensors/adxl372_uorb.c index 168c3e21d01..d9267755f1c 100644 --- a/drivers/sensors/adxl372_uorb.c +++ b/drivers/sensors/adxl372_uorb.c @@ -111,7 +111,7 @@ static const struct sensor_ops_s g_adxl372_accel_ops = NULL, /* selftest */ NULL, /* set_calibvalue */ NULL, /* calibrate */ - NULL /* get_info */ + NULL, /* get_info */ NULL, /* set_nonwakeup */ NULL /* control */ }; From 46d2306bf815418ca4a23e78c4512b1e1673d112 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 12:11:57 +0200 Subject: [PATCH 027/268] !arch/stm32: rename STM32F7/H7 QUADSPI Kconfig symbol to QSPI BREAKING CHANGE: CONFIG_STM32F7_QUADSPI and CONFIG_STM32H7_QUADSPI are renamed to CONFIG_STM32F7_QSPI and CONFIG_STM32H7_QSPI. Out-of-tree F7/H7 board configurations must update the symbol name. Standardize the F7/H7 QSPI enable symbol on the QSPI name (the QUADSPI and QSPI peripherals are the same IP block). Only the Kconfig enable symbol and its CONFIG_ references are renamed; the QUADSPI hardware register/pin/DMA macros are unchanged. Signed-off-by: raiden00pl --- arch/arm/src/stm32f7/CMakeLists.txt | 2 +- arch/arm/src/stm32f7/Kconfig | 4 ++-- arch/arm/src/stm32f7/Make.defs | 2 +- arch/arm/src/stm32f7/stm32_qspi.c | 2 +- arch/arm/src/stm32f7/stm32_qspi.h | 2 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 2 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 2 +- arch/arm/src/stm32h7/CMakeLists.txt | 2 +- arch/arm/src/stm32h7/Kconfig | 4 ++-- arch/arm/src/stm32h7/Make.defs | 2 +- arch/arm/src/stm32h7/stm32_qspi.c | 2 +- arch/arm/src/stm32h7/stm32_qspi.h | 2 +- boards/arm/stm32f7/stm32f746g-disco/Kconfig | 2 +- .../stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig | 2 +- boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig | 2 +- .../stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig | 2 +- .../arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig | 2 +- boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c | 4 ++-- .../arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig | 2 +- boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig | 2 +- 21 files changed, 24 insertions(+), 24 deletions(-) diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index 89cca465803..fbf052e2458 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -128,7 +128,7 @@ if(CONFIG_STM32F7_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F7_QUADSPI) +if(CONFIG_STM32F7_QSPI) list(APPEND SRCS stm32_qspi.c) endif() diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index ec6c5361ede..825e55ef277 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1469,7 +1469,7 @@ config STM32F7_OTGFSHS default n select USBHOST_HAVE_ASYNCH if USBHOST -config STM32F7_QUADSPI +config STM32F7_QSPI bool "QuadSPI" default n @@ -2185,7 +2185,7 @@ config STM32F7_EXTERNAL_RAM In addition to internal SDRAM, external RAM may be available through the FMC. menu "QuadSPI Configuration" - depends on STM32F7_QUADSPI + depends on STM32F7_QSPI config STM32F7_QSPI_FLASH_SIZE int "Size of attached serial flash, bytes" diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 04f0514666b..4c9fe1c7319 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -130,7 +130,7 @@ ifeq ($(CONFIG_STM32F7_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F7_QUADSPI),y) +ifeq ($(CONFIG_STM32F7_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index a9e46655548..c9f30d3155a 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index 018bf0c1173..ae919405ef5 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 19d3e90346b..625c5917073 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -309,7 +309,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index fac08c11467..a0f80c1a031 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -311,7 +311,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index ff026b7f8e7..a497d7ccb85 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -319,7 +319,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index eb5a4218c22..e1636a3fb8d 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -109,7 +109,7 @@ if(CONFIG_STM32H7_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32H7_QUADSPI) +if(CONFIG_STM32H7_QSPI) list(APPEND SRCS stm32_qspi.c) endif() diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 4f1c6eaaa17..bc7c0670d88 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -954,7 +954,7 @@ config STM32H7_OTG_USBREGEN bool "Enable USB voltage regulator" default n -config STM32H7_QUADSPI +config STM32H7_QSPI bool "QuadSPI" default n @@ -2221,7 +2221,7 @@ endif # STM32H7_RTC_LSECLOCK endmenu # RTC Configuration menu "QuadSPI Configuration" - depends on STM32H7_QUADSPI + depends on STM32H7_QSPI config STM32H7_QSPI_FLASH_SIZE int "Size of attached serial flash, bytes" diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 73f9b13979a..005c695adc8 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -111,7 +111,7 @@ ifeq ($(CONFIG_STM32H7_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32H7_QUADSPI),y) +ifeq ($(CONFIG_STM32H7_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index bb985448e65..c346fa55125 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32H7_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 93f03807023..36724b2538e 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_QUADSPI +#ifdef CONFIG_STM32H7_QSPI /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index 40785710b6d..f43ffe7e876 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32F7_QUADSPI + select STM32F7_QSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 0361ac3973f..23b69992c3e 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -65,8 +65,8 @@ CONFIG_START_DAY=14 CONFIG_STM32F7_DMA1=y CONFIG_STM32F7_DMA2=y CONFIG_STM32F7_OTGFS=y +CONFIG_STM32F7_QSPI=y CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y CONFIG_STM32F7_SDMMC2=y CONFIG_STM32F7_SDMMC_DMA=y CONFIG_STM32F7_USART1=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index 2a5630c8763..bd8641a4643 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -93,8 +93,8 @@ CONFIG_STM32F7_I2S2=y CONFIG_STM32F7_I2S2_MCK=y CONFIG_STM32F7_I2S2_TX=y CONFIG_STM32F7_OTGFS=y +CONFIG_STM32F7_QSPI=y CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_QUADSPI=y CONFIG_STM32F7_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index e4d37559d9d..9df11e1e0fc 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -66,7 +66,7 @@ CONFIG_SPI=y CONFIG_START_DAY=14 CONFIG_STM32F7_I2C1=y CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y +CONFIG_STM32F7_QSPI=y CONFIG_STM32F7_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 6fb257d819b..1b453b93181 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -55,7 +55,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QUADSPI=y +CONFIG_STM32F7_QSPI=y CONFIG_STM32F7_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index fbf4f961fc5..5966f0315b8 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32F7_QUADSPI +#ifdef CONFIG_STM32F7_QSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index ef1fdd8f3fa..d0502ff974d 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -58,8 +58,8 @@ CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_QSPI=y CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y CONFIG_STM32H7_RTC=y CONFIG_STM32H7_USART1=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index c04492147c9..25020b5ef45 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -52,8 +52,8 @@ CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_QSPI=y CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_QUADSPI=y CONFIG_STM32H7_RTC=y CONFIG_STM32H7_USART1=y CONFIG_SYSTEM_NSH=y From 46967df94fea03b52233dff0e10108d20abd59e9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 08:59:37 +0200 Subject: [PATCH 028/268] !arm/stm32: split legacy STM32 family selectors BREAKING CHANGE: Convert the legacy STM32 F1/F2/F3/F4/G4/L1 port to the concrete family selectors while keeping the shared STM32 selector hidden. Legacy STM32 family selector Kconfig symbols were split by concrete STM32 sub-family. Out-of-tree defconfigs and code must update CONFIG_ARCH_CHIP_* selections to the new family-specific selectors. Signed-off-by: raiden00pl --- .../arm/stm32f1/boards/fire-stm32v2/index.rst | 2 +- arch/arm/Kconfig | 105 +++++++++++++++++- arch/arm/src/stm32/Kconfig | 2 +- .../arm/stm32/axoloti/configs/nsh/defconfig | 1 + .../stm32/b-g431b-esc1/configs/can/defconfig | 1 + .../b-g431b-esc1/configs/cansock/defconfig | 1 + .../b-g431b-esc1/configs/foc_b16/defconfig | 1 + .../b-g431b-esc1/configs/foc_f32/defconfig | 1 + .../stm32/b-g431b-esc1/configs/nsh/defconfig | 1 + .../b-g474e-dpow1/configs/buckboost/defconfig | 1 + .../stm32/b-g474e-dpow1/configs/nsh/defconfig | 1 + .../b-g474e-dpow1/configs/ostest/defconfig | 1 + .../clicker2-stm32/configs/knsh/defconfig | 1 + .../configs/mrf24j40-6lowpan/defconfig | 1 + .../configs/mrf24j40-mac/defconfig | 1 + .../configs/mrf24j40-starhub/defconfig | 1 + .../configs/mrf24j40-starpoint/defconfig | 1 + .../clicker2-stm32/configs/nsh/defconfig | 1 + .../clicker2-stm32/configs/usbnsh/defconfig | 1 + .../configs/xbee-6lowpan/defconfig | 1 + .../arm/stm32/cloudctrl/configs/nsh/defconfig | 1 + .../arm/stm32/emw3162/configs/nsh/defconfig | 1 + .../arm/stm32/emw3162/configs/wlan/defconfig | 1 + .../et-stm32-stamp/configs/nsh/defconfig | 1 + .../stm32/fire-stm32v2/configs/nsh/defconfig | 1 + .../stm32/hymini-stm32v/configs/nsh/defconfig | 1 + .../hymini-stm32v/configs/nsh2/defconfig | 1 + .../hymini-stm32v/configs/usbmsc/defconfig | 1 + .../hymini-stm32v/configs/usbnsh/defconfig | 1 + .../hymini-stm32v/configs/usbserial/defconfig | 1 + boards/arm/stm32/maple/configs/nsh/defconfig | 1 + boards/arm/stm32/maple/configs/nx/defconfig | 1 + .../arm/stm32/maple/configs/usbnsh/defconfig | 1 + .../mikroe-stm32f4/configs/fulldemo/defconfig | 1 + .../mikroe-stm32f4/configs/kostest/defconfig | 1 + .../mikroe-stm32f4/configs/nsh/defconfig | 1 + .../stm32/mikroe-stm32f4/configs/nx/defconfig | 1 + .../mikroe-stm32f4/configs/nxlines/defconfig | 1 + .../mikroe-stm32f4/configs/nxtext/defconfig | 1 + .../mikroe-stm32f4/configs/usbnsh/defconfig | 1 + .../stm32/nucleo-f103rb/configs/adc/defconfig | 1 + .../configs/ihm07m1_b16/defconfig | 1 + .../stm32/nucleo-f103rb/configs/nsh/defconfig | 1 + .../stm32/nucleo-f103rb/configs/pwm/defconfig | 1 + .../nucleo-f103rb/configs/qenco/defconfig | 1 + .../stm32/nucleo-f207zg/configs/adc/defconfig | 1 + .../stm32/nucleo-f207zg/configs/nsh/defconfig | 1 + .../stm32/nucleo-f207zg/configs/pwm/defconfig | 1 + .../stm32/nucleo-f302r8/configs/can/defconfig | 1 + .../nucleo-f302r8/configs/cansock/defconfig | 1 + .../nucleo-f302r8/configs/highpri/defconfig | 1 + .../configs/ihm07m1_b16/defconfig | 1 + .../configs/ihm07m1_f32/defconfig | 1 + .../stm32/nucleo-f302r8/configs/nsh/defconfig | 1 + .../nucleo-f302r8/configs/qenco/defconfig | 1 + .../stm32/nucleo-f303re/configs/adc/defconfig | 1 + .../stm32/nucleo-f303re/configs/can/defconfig | 1 + .../nucleo-f303re/configs/hello/defconfig | 1 + .../stm32/nucleo-f303re/configs/nsh/defconfig | 1 + .../nucleo-f303re/configs/nxlines/defconfig | 1 + .../stm32/nucleo-f303re/configs/pwm/defconfig | 1 + .../nucleo-f303re/configs/serialrx/defconfig | 1 + .../stm32/nucleo-f303ze/configs/adc/defconfig | 1 + .../stm32/nucleo-f303ze/configs/nsh/defconfig | 1 + .../configs/nxlines_oled/defconfig | 1 + .../stm32/nucleo-f334r8/configs/adc/defconfig | 1 + .../nucleo-f334r8/configs/highpri/defconfig | 1 + .../stm32/nucleo-f334r8/configs/nsh/defconfig | 1 + .../nucleo-f334r8/configs/spwm1/defconfig | 1 + .../nucleo-f334r8/configs/spwm2/defconfig | 1 + .../stm32/nucleo-f401re/configs/fb/defconfig | 1 + .../stm32/nucleo-f401re/configs/nsh/defconfig | 1 + .../stm32/nucleo-f410rb/configs/nsh/defconfig | 1 + .../configs/mcp2515-extid/defconfig | 1 + .../stm32/nucleo-f411re/configs/nsh/defconfig | 1 + .../nucleo-f412zg/configs/coremark/defconfig | 1 + .../stm32/nucleo-f412zg/configs/nsh/defconfig | 1 + .../nucleo-f412zg/configs/ostest/defconfig | 1 + .../nucleo-f429zi/configs/netnsh/defconfig | 1 + .../stm32/nucleo-f429zi/configs/nsh/defconfig | 1 + .../nucleo-f429zi/configs/trace/defconfig | 1 + .../stm32/nucleo-f446re/configs/adc/defconfig | 1 + .../stm32/nucleo-f446re/configs/can/defconfig | 1 + .../nucleo-f446re/configs/cansock/defconfig | 1 + .../stm32/nucleo-f446re/configs/dac/defconfig | 1 + .../nucleo-f446re/configs/gpio/defconfig | 1 + .../configs/ihm08m1_b16/defconfig | 1 + .../configs/ihm08m1_f32/defconfig | 1 + .../nucleo-f446re/configs/jumbo/defconfig | 1 + .../stm32/nucleo-f446re/configs/lcd/defconfig | 1 + .../stm32/nucleo-f446re/configs/nsh/defconfig | 1 + .../stm32/nucleo-f446re/configs/pwm/defconfig | 1 + .../nucleo-f446re/configs/qenco/defconfig | 1 + .../configs/systemview/defconfig | 1 + .../nucleo-g431kb/configs/comp/defconfig | 1 + .../stm32/nucleo-g431kb/configs/nsh/defconfig | 1 + .../stm32/nucleo-g431kb/configs/pwm/defconfig | 1 + .../stm32/nucleo-g431rb/configs/adc/defconfig | 1 + .../stm32/nucleo-g431rb/configs/can/defconfig | 1 + .../nucleo-g431rb/configs/cansock/defconfig | 1 + .../nucleo-g431rb/configs/cordic/defconfig | 1 + .../configs/ihm16m1_b16/defconfig | 1 + .../configs/ihm16m1_f32/defconfig | 1 + .../stm32/nucleo-g431rb/configs/nsh/defconfig | 1 + .../stm32/nucleo-g431rb/configs/pwm/defconfig | 1 + .../nucleo-g431rb/configs/qenco/defconfig | 1 + .../nucleo-g474re/configs/lpuartnsh/defconfig | 1 + .../stm32/nucleo-g474re/configs/nsh/defconfig | 1 + .../nucleo-g474re/configs/usbserial/defconfig | 1 + .../stm32/nucleo-l152re/configs/lcd/defconfig | 1 + .../stm32/nucleo-l152re/configs/nsh/defconfig | 1 + .../arm/stm32/odrive36/configs/nsh/defconfig | 1 + .../stm32/odrive36/configs/usbnsh/defconfig | 1 + .../configs/bmp180/defconfig | 1 + .../olimex-stm32-e407/configs/dac/defconfig | 1 + .../configs/discover/defconfig | 1 + .../configs/ina219/defconfig | 1 + .../configs/mrf24j40-6lowpan/defconfig | 1 + .../configs/mrf24j40-mac/defconfig | 1 + .../configs/netnsh/defconfig | 1 + .../olimex-stm32-e407/configs/nsh/defconfig | 1 + .../configs/telnetd/defconfig | 1 + .../olimex-stm32-e407/configs/timer/defconfig | 1 + .../configs/usbnsh/defconfig | 1 + .../configs/webserver/defconfig | 1 + .../configs/usbnsh/defconfig | 1 + .../olimex-stm32-h407/configs/nsh/defconfig | 1 + .../configs/nsh_uext/defconfig | 1 + .../olimex-stm32-p107/configs/nsh/defconfig | 1 + .../olimex-stm32-p207/configs/nsh/defconfig | 1 + .../olimex-stm32-p407/configs/audio/defconfig | 1 + .../olimex-stm32-p407/configs/dhtxx/defconfig | 1 + .../configs/hidkbd/defconfig | 1 + .../olimex-stm32-p407/configs/kelf/defconfig | 1 + .../configs/kmodule/defconfig | 1 + .../olimex-stm32-p407/configs/knsh/defconfig | 1 + .../configs/module/defconfig | 1 + .../olimex-stm32-p407/configs/mqttc/defconfig | 1 + .../olimex-stm32-p407/configs/nsh/defconfig | 1 + .../configs/zmodem/defconfig | 1 + .../olimexino-stm32/configs/can/defconfig | 1 + .../configs/composite/defconfig | 1 + .../olimexino-stm32/configs/nsh/defconfig | 1 + .../configs/smallnsh/defconfig | 1 + .../olimexino-stm32/configs/tiny/defconfig | 1 + .../arm/stm32/omnibusf4/configs/nsh/defconfig | 1 + boards/arm/stm32/photon/configs/adb/defconfig | 1 + boards/arm/stm32/photon/configs/nsh/defconfig | 1 + .../arm/stm32/photon/configs/rgbled/defconfig | 1 + .../arm/stm32/photon/configs/usbnsh/defconfig | 1 + .../stm32/photon/configs/wlan-perf/defconfig | 1 + .../arm/stm32/photon/configs/wlan/defconfig | 1 + .../arm/stm32/shenzhou/configs/nsh/defconfig | 1 + .../arm/stm32/shenzhou/configs/nxwm/defconfig | 1 + .../stm32/shenzhou/configs/thttpd/defconfig | 1 + .../stm3210e-eval/configs/composite/defconfig | 1 + .../stm32/stm3210e-eval/configs/nsh/defconfig | 1 + .../stm3210e-eval/configs/nsh2/defconfig | 1 + .../stm32/stm3210e-eval/configs/nx/defconfig | 1 + .../stm3210e-eval/configs/nxterm/defconfig | 1 + .../stm32/stm3210e-eval/configs/pm/defconfig | 1 + .../stm3210e-eval/configs/usbmsc/defconfig | 1 + .../stm3210e-eval/configs/usbserial/defconfig | 1 + .../stm3220g-eval/configs/dhcpd/defconfig | 1 + .../stm3220g-eval/configs/nettest/defconfig | 1 + .../stm32/stm3220g-eval/configs/nsh/defconfig | 1 + .../stm3220g-eval/configs/nsh2/defconfig | 1 + .../stm3220g-eval/configs/nxwm/defconfig | 1 + .../stm3220g-eval/configs/telnetd/defconfig | 1 + .../stm3240g-eval/configs/dhcpd/defconfig | 1 + .../stm3240g-eval/configs/discover/defconfig | 1 + .../stm32/stm3240g-eval/configs/fb/defconfig | 1 + .../stm3240g-eval/configs/knxwm/defconfig | 1 + .../stm3240g-eval/configs/nettest/defconfig | 1 + .../stm32/stm3240g-eval/configs/nsh/defconfig | 1 + .../stm3240g-eval/configs/nsh2/defconfig | 1 + .../stm3240g-eval/configs/nxterm/defconfig | 1 + .../stm3240g-eval/configs/nxwm/defconfig | 1 + .../stm3240g-eval/configs/telnetd/defconfig | 1 + .../stm3240g-eval/configs/webserver/defconfig | 1 + .../stm3240g-eval/configs/xmlrpc/defconfig | 1 + .../stm32/stm32_tiny/configs/nsh/defconfig | 1 + .../stm32/stm32_tiny/configs/usbnsh/defconfig | 1 + .../stm32butterfly2/configs/nsh/defconfig | 1 + .../stm32butterfly2/configs/nshnet/defconfig | 1 + .../configs/nshusbdev/defconfig | 1 + .../configs/nshusbhost/defconfig | 1 + .../stm32f103-minimum/configs/adb/defconfig | 1 + .../configs/apds9960/defconfig | 1 + .../configs/audio_tone/defconfig | 1 + .../configs/buttons/defconfig | 1 + .../stm32f103-minimum/configs/can/defconfig | 1 + .../stm32f103-minimum/configs/hello/defconfig | 1 + .../configs/jlx12864g/defconfig | 1 + .../configs/lcd1602/defconfig | 1 + .../configs/mcp2515/defconfig | 1 + .../stm32f103-minimum/configs/nrf24/defconfig | 1 + .../stm32f103-minimum/configs/nsh/defconfig | 1 + .../stm32f103-minimum/configs/pwm/defconfig | 1 + .../configs/rfid-rc522/defconfig | 1 + .../configs/rgbled/defconfig | 1 + .../configs/sensors/defconfig | 1 + .../configs/ssd1306/defconfig | 1 + .../configs/usbnsh/defconfig | 1 + .../configs/userled/defconfig | 1 + .../configs/veml6070/defconfig | 1 + .../configs/buckboost/defconfig | 1 + .../stm32f334-disco/configs/nsh/defconfig | 1 + .../configs/powerled/defconfig | 1 + .../stm32f3discovery/configs/nsh/defconfig | 1 + .../stm32f3discovery/configs/usbnsh/defconfig | 1 + .../stm32f401rc-rs485/configs/adc/defconfig | 1 + .../configs/bmp280/defconfig | 1 + .../stm32f401rc-rs485/configs/dac/defconfig | 1 + .../configs/hcsr04/defconfig | 1 + .../configs/lcd1602/defconfig | 1 + .../stm32f401rc-rs485/configs/lm75/defconfig | 1 + .../configs/max7219/defconfig | 1 + .../configs/mfrc522/defconfig | 1 + .../configs/modbus_master/defconfig | 1 + .../configs/modbus_slave/defconfig | 1 + .../stm32f401rc-rs485/configs/nsh/defconfig | 1 + .../configs/qencoder/defconfig | 1 + .../stm32f401rc-rs485/configs/rndis/defconfig | 1 + .../configs/sdcard/defconfig | 1 + .../configs/ssd1309/defconfig | 1 + .../configs/telnetd/defconfig | 1 + .../configs/usbmsc/defconfig | 1 + .../configs/usbnsh/defconfig | 1 + .../configs/ws2812/defconfig | 1 + .../configs/composite/defconfig | 1 + .../stm32f411-minimum/configs/nsh/defconfig | 1 + .../stm32f411-minimum/configs/pwm/defconfig | 1 + .../configs/rgbled/defconfig | 1 + .../configs/spifsnsh/defconfig | 1 + .../configs/usbmsc/defconfig | 1 + .../stm32f411e-disco/configs/nsh/defconfig | 1 + .../stm32f429i-disco/configs/adc/defconfig | 1 + .../configs/bootlogo/defconfig | 1 + .../configs/extflash/defconfig | 1 + .../stm32f429i-disco/configs/fb/defconfig | 1 + .../configs/gdbstub/defconfig | 1 + .../configs/highpri/defconfig | 1 + .../stm32f429i-disco/configs/lcd/defconfig | 1 + .../stm32f429i-disco/configs/lvgl/defconfig | 1 + .../stm32f429i-disco/configs/nsh/defconfig | 1 + .../configs/nxhello/defconfig | 1 + .../stm32f429i-disco/configs/nxwm/defconfig | 1 + .../configs/ofloader/defconfig | 1 + .../stm32f429i-disco/configs/stack/defconfig | 1 + .../configs/systemview/defconfig | 1 + .../stm32f429i-disco/configs/usbmsc/defconfig | 1 + .../stm32f429i-disco/configs/usbnsh/defconfig | 1 + .../stm32f4discovery/configs/adb/defconfig | 1 + .../stm32f4discovery/configs/audio/defconfig | 1 + .../configs/brickmatch/defconfig | 1 + .../stm32f4discovery/configs/canard/defconfig | 1 + .../configs/composite/defconfig | 1 + .../configs/cxx-oot-build/defconfig | 1 + .../configs/cxxtest/defconfig | 1 + .../stm32f4discovery/configs/elf/defconfig | 1 + .../configs/ether_w5500/defconfig | 1 + .../stm32f4discovery/configs/ipv6/defconfig | 1 + .../configs/kostest/defconfig | 1 + .../configs/lcd1602/defconfig | 1 + .../stm32f4discovery/configs/lwl/defconfig | 1 + .../configs/max31855/defconfig | 1 + .../configs/max7219/defconfig | 1 + .../configs/mmcsdspi/defconfig | 1 + .../configs/modbus_slave/defconfig | 1 + .../stm32f4discovery/configs/module/defconfig | 1 + .../configs/mpr121_keypad/defconfig | 1 + .../stm32f4discovery/configs/mt6816/defconfig | 1 + .../stm32f4discovery/configs/netnsh/defconfig | 1 + .../stm32f4discovery/configs/nsh/defconfig | 1 + .../configs/nxlines/defconfig | 1 + .../configs/nxscope_cdcacm/defconfig | 1 + .../stm32f4discovery/configs/pm/defconfig | 1 + .../configs/posix_spawn/defconfig | 1 + .../configs/pseudoterm/defconfig | 1 + .../stm32f4discovery/configs/rgbled/defconfig | 1 + .../stm32f4discovery/configs/rndis/defconfig | 1 + .../configs/sbutton/defconfig | 1 + .../configs/sporadic/defconfig | 1 + .../stm32f4discovery/configs/st7567/defconfig | 1 + .../stm32f4discovery/configs/st7789/defconfig | 1 + .../configs/testlibcxx/defconfig | 1 + .../stm32f4discovery/configs/usbmsc/defconfig | 1 + .../stm32f4discovery/configs/usbnsh/defconfig | 1 + .../stm32f4discovery/configs/wifi/defconfig | 1 + .../configs/xen1210/defconfig | 1 + .../stm32ldiscovery/configs/chrono/defconfig | 1 + .../stm32ldiscovery/configs/nsh/defconfig | 1 + .../stm32vldiscovery/configs/nsh/defconfig | 1 + .../configs/ft80x/defconfig | 1 + .../configs/highpri/defconfig | 1 + .../configs/netnsh/defconfig | 1 + .../viewtool-stm32f107/configs/nsh/defconfig | 1 + .../configs/tcpblaster/defconfig | 1 + 299 files changed, 397 insertions(+), 8 deletions(-) diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index e82450a5e2f..19ce66c3fb0 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -324,7 +324,7 @@ M3 Wildfire-specific Configuration Options CONFIG_ARCH_CHIP_name - For use in C code to identify the exact chip: - CONFIG_ARCH_CHIP_STM32 + CONFIG_ARCH_CHIP_STM32F1 CONFIG_ARCH_CHIP_STM32F103VE CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cdf4df2bb13..4eb585a6d76 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -55,7 +55,7 @@ endchoice # ARM Toolchain Selection choice prompt "ARM MCU selection" - default ARCH_CHIP_STM32 + default ARCH_CHIP_STM32F1 config ARCH_CHIP_A1X bool "Allwinner A1X" @@ -489,8 +489,9 @@ config ARCH_CHIP_SIMPLELINK ---help--- TI SimpleLink CCxxx architectures (ARM Cortex-M3 or M4) -config ARCH_CHIP_STM32 - bool "STMicro STM32 F1/F2/F3/F4/G4/L1" +config ARCH_CHIP_STM32F1 + bool "STMicro STM32 F1" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD select ARCH_HAVE_I2CRESET @@ -503,7 +504,92 @@ config ARCH_CHIP_STM32 select ARMV7M_HAVE_STACKCHECK select ARCH_HAVE_ADJTIME ---help--- - STMicro STM32 architectures (ARM Cortex-M3/4). + STMicro STM32F1 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F2 + bool "STMicro STM32 F2" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F2 architectures (ARM Cortex-M3). + +config ARCH_CHIP_STM32F3 + bool "STMicro STM32 F3" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F3 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32F4 + bool "STMicro STM32 F4" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32F4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32G4 + bool "STMicro STM32 G4" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32G4 architectures (ARM Cortex-M4). + +config ARCH_CHIP_STM32L1 + bool "STMicro STM32 L1" + select ARCH_CHIP_STM32 + select ARCH_HAVE_MPU + select ARCH_HAVE_FETCHADD + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_PROGMEM + select ARCH_HAVE_SPI_BITORDER + select ARCH_HAVE_TICKLESS + select ARCH_HAVE_TIMEKEEPING + select ARM_HAVE_MPU_UNIFIED + select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_ADJTIME + ---help--- + STMicro STM32L1 architectures (ARM Cortex-M3). config ARCH_CHIP_STM32F0 bool "STMicro STM32 F0" @@ -812,6 +898,13 @@ config ARCH_CHIP_ARM_CUSTOM endchoice # ARM MCU selection +config ARCH_CHIP_STM32 + bool + default n + ---help--- + Common STM32 architecture selector. This is selected by the concrete + STM32 family options and gates shared STM32 Kconfig options. + config ARCH_ARM7TDMI bool default n @@ -1211,7 +1304,7 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32 + default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 @@ -1713,7 +1806,7 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32 +if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 source "arch/arm/src/stm32/Kconfig" endif if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f6d7ff5b37e..f9666d1c84e 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -8,7 +8,7 @@ comment "STM32 Configuration Options" choice prompt "STM32 Chip Selection" default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32 + depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 config ARCH_CHIP_STM32L151C6 bool "STM32L151C6" diff --git a/boards/arm/stm32/axoloti/configs/nsh/defconfig b/boards/arm/stm32/axoloti/configs/nsh/defconfig index 1d43644ebd1..13126e94b97 100644 --- a/boards/arm/stm32/axoloti/configs/nsh/defconfig +++ b/boards/arm/stm32/axoloti/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F427I=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_INIT_ENTRYPOINT="nsh_main" diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig index 43dc0f4143a..17b32fcb9bb 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig index ba24fe7e2fe..373cdc11f37 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig index a8d73452d00..a539b4674fc 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig index 2dd0555c613..83afe8d9abe 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig index 7008df08655..e90af74b545 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig index fadfe62a852..fbccc190546 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig index 067ed861738..4a06eef534f 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig index 70a00af2020..f0062bba6a8 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig +++ b/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig index b44ea5be1a4..8bc472bb1a3 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig index 67b83406eb1..7a9d38c2dc5 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig index bb355e1aeb4..045007e9967 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig index 1d2e6c692f5..c468cfa3458 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig index d49e01b2da3..18104f2c327 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig index 8d0945efcca..fe869ff395f 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig index 48aee341fff..1b1542c9e7d 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig index 4f4c219be01..a453402fc63 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ b/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig index be4882c81d0..d27766792b5 100644 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ b/boards/arm/stm32/cloudctrl/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_CLOUDCTRL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32/emw3162/configs/nsh/defconfig index 9688757eaf2..fc40697134b 100644 --- a/boards/arm/stm32/emw3162/configs/nsh/defconfig +++ b/boards/arm/stm32/emw3162/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_EMW3162=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32/emw3162/configs/wlan/defconfig index ceeedd6a6b5..ccfcd0a4584 100644 --- a/boards/arm/stm32/emw3162/configs/wlan/defconfig +++ b/boards/arm/stm32/emw3162/configs/wlan/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_EMW3162=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig index 4c71777c0f8..e1777e13148 100644 --- a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig +++ b/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_ET_STM32_STAMP=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig index 334352f9853..bdd40431cd1 100644 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ b/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_FIRE_STM32=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig index 46a47095c31..b904fc0c04c 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_DISABLE=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig index 07770b9836b..af5c99a60ef 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig index 429596080a6..93e1fda2fb6 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig index 73800aa8adf..d4abd686cc2 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_DISABLE=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig index 7f6da595e2a..e83a76ba4d6 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ b/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32/maple/configs/nsh/defconfig index 7c9ac9e17fb..8560b225c2a 100644 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ b/boards/arm/stm32/maple/configs/nsh/defconfig @@ -26,6 +26,7 @@ CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32/maple/configs/nx/defconfig index 9ffbeb782a2..b0fe6deb135 100644 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ b/boards/arm/stm32/maple/configs/nx/defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32/maple/configs/usbnsh/defconfig index 5dac2d20570..e25aa718adb 100644 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ b/boards/arm/stm32/maple/configs/usbnsh/defconfig @@ -27,6 +27,7 @@ CONFIG_ARCH_BOARD_MAPLE=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig index 7413ebbd7f9..4608142f8d4 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y CONFIG_AUDIO_FORMAT_MIDI=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig index e89262a68b9..e8099c11539 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig index 78dfe980601..c8abdaa5642 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig index c8b0ef583d7..f8e4317f850 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig index 9245c04e424..7ebdd06692a 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig index 7959ef46086..cff66efd83a 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig index c011fdde8bb..3d2e73deec4 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig index 46570b4a608..c42749dde06 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig index e8185cb7802..c9db38b3727 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig index 2be574f9f86..3e2df5a41ac 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig index 1fd7b4dd5e8..5be68b08744 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig index df060b58063..dfcbc2403c6 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig index 2615e630e80..019a6cec7cb 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig index 855e4c155bb..0bba482d3d2 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig index 03abe05bec9..785cc7e2c1b 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig index def904eba3d..d9e63f0503d 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig index 701e71056cc..a7d8a70986e 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_INITTHREAD_STACKSIZE=1024 diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig index 386f0a3d399..591de57c991 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig index 39910fedf69..3c84735698b 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig index c3c5fc1ce34..4a8b23fe7b9 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig index a1df51d77ca..0e3692e647d 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig index 1197a24f5e6..a63d93c717a 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig @@ -65,6 +65,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQPRIO=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig index ea4831dc3fd..40f25f3adf6 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig index 4c85a315731..7132acae45a 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/can/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig index a51fa54aaa0..ca034f8f9bd 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_DEBUG_SYMBOLS=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig index 95b091e30b4..2c491319b47 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_DEBUG_SYMBOLS=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig index 8bacca4eb3f..75d56847146 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_CAN=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig index 7c449ee522c..2b12f647fd7 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig index 16397524983..1f48a0590ec 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ b/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig index b90be268b18..2d1aa57d9d7 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig index 7081c146db7..876b7df5a5e 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig index 3c09c2da600..8e5491d82fe 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig index 33656febfca..8408fa611bf 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig index 1866cd70f3c..fd85cdf0d5d 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig index 2bb393ba170..38e98f8d2c5 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig index 37daa3d7509..eabb1afa344 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig index d238c8b4564..abe476df3aa 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ b/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig index 88504078e4d..9ac5b0e47cc 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig +++ b/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig index 8bf7d35ad49..9ad92364dd4 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig index 58fb8efa0e5..d34fcf48937 100644 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F410RB=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig index 78f646b76fe..94fb4e9344c 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig +++ b/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig index ecb6ba9c1d2..4711d3f0d23 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411RE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig index 6dd586b0050..bc43703857b 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig index fc06830d00b..1f346ea02df 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig index 5c9c9c9657c..223b220ecac 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig +++ b/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_SIZET_LONG=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig index 8af3bb56e5f..13de7189e38 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig index d13b9d0031e..6b6330f2792 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig index a82d50d95dd..691ca8e05ed 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig +++ b/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig index 20fde7d94c8..fef22a76f57 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig index f699366f92d..eb95a0857ea 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/can/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig index 1ed153216c6..93cd1a3a7a6 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig index 8b4215f22ec..94e7c7aa642 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig index 7436007b483..bc1d3de1e86 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig index 2c152f31e76..a4f0be9b9bc 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig index 5b3e84da6ad..cfba3f468ea 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig index e553a334ca1..37087dd5ce9 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig index 2c85afecb9f..113b92fc963 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig index 1dd5ff9cb17..f37e6a0b9a4 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig index 64d5b681a44..49a67a4fa1c 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig index d0da232ae1b..e2a2f748c60 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQPRIO=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig index 01ea37491e5..1fdaa7ce509 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig +++ b/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig index 5631b4f1a60..19ef6fb3b3a 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig index 2470af3cfac..71d86817a14 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig index b8e9c1184c3..03c3f4463e2 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_NUCLEO_G431KB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig index 143878d3afd..c275012af8b 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig index 4796db68b7d..164ca565954 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig index dbca1ec3f65..6986192ece8 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig index 105f0e801d7..a70cdc98d43 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig index 198ec5e9645..de716f64e0e 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig index 54b46c61d05..0565f5b91df 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=1024 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARMV7M_LIBM=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig index b28e171393d..d86c4e134ce 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig index 8f56b95cda3..63712349344 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig index a3b86c5b5b5..8c11d4f8a59 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig index bbfd0aa9b52..380f216200a 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig index 0850c88d054..fbcf8585258 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig index e93dcf5ab62..3dc81656600 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig +++ b/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y +CONFIG_ARCH_CHIP_STM32G4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig index 5695f7ee012..bbbb2ac2407 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_NUCLEO_L152RE=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig index 4232102fb61..19e97ac9e09 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ b/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_NUCLEO_L152RE=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/odrive36/configs/nsh/defconfig b/boards/arm/stm32/odrive36/configs/nsh/defconfig index 2f27a769673..bd3b6e49f09 100644 --- a/boards/arm/stm32/odrive36/configs/nsh/defconfig +++ b/boards/arm/stm32/odrive36/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_ODRIVE36=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=15272 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig index c0b74daa753..d216eecfd45 100644 --- a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig +++ b/boards/arm/stm32/odrive36/configs/usbnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_ODRIVE36=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=15272 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig index d5df1ff53ba..1aa6e086128 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig index 19fe3319452..a4ec3de1aec 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig index a83bf4730a9..ecab558ba8a 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig index e406cc5fb02..524514c10a5 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig index c0f90c97411..82866611578 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig index a9221bfba48..ce4bcf2897c 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig index 2e75fb27370..afcfaffe6bf 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig index 571f8a9adb7..221b5529d60 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig index 6a11a0f3b39..3c53e107b14 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig index 98aa59ace4c..f8bfe6f3aba 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig index 93de5493566..219c9d105fa 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig index f01bcc9c11c..ef871f1e02f 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ b/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig index 302f0bd148f..56300440f6b 100644 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig index b2e63d079be..37c7caa077f 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig index 2095476d0ef..ffecc92a539 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ b/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig index 0e6f00bff3b..3c3be28514f 100644 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig index 4e50e59cce3..d8e2974ccfc 100644 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZE=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig index 1d4015c4802..01fefc9cf1e 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig index 1ec9ec6df1f..47c8e24b497 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig index ed45a26523b..f835cb6764b 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig index bb4a056ff46..e70543e3326 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_BINFMT_CONSTRUCTORS=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig index cde47ac79db..39ae6fde6a8 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig index 7be5a978eda..1d27f2abdbf 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig index 7157051491c..fbcc984f58e 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig index 76e96ce5920..15d2916f721 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig index bb3cbd8e780..120b8f3bb36 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig index 7c2ccb8cb1f..4843b097e6a 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ b/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig index d02669c5502..5cda9c9dfaf 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/can/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig index ce360b21b94..17a4b63f45e 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig @@ -35,6 +35,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig index 7fac8d7932b..14b1c6b45e4 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig @@ -35,6 +35,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig index 9e47e5a1c4a..1a32249955a 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig index 34a814085c5..6c7249cf180 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ b/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_INTERRUPTSTACK=340 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig index 3c35b9f82b2..a092cd5ce1e 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32/omnibusf4/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_OMNIBUSF4=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_IOCTL=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig index 1cd0b1d4e0f..51b74bca0df 100644 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ b/boards/arm/stm32/photon/configs/adb/defconfig @@ -21,6 +21,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32/photon/configs/nsh/defconfig index e0e25c7c346..4401baf4dfd 100644 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ b/boards/arm/stm32/photon/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32/photon/configs/rgbled/defconfig index d1096c8a84d..c8935b1083d 100644 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ b/boards/arm/stm32/photon/configs/rgbled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32/photon/configs/usbnsh/defconfig index 860b3301702..80a40d20e62 100644 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ b/boards/arm/stm32/photon/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/photon/configs/wlan-perf/defconfig b/boards/arm/stm32/photon/configs/wlan-perf/defconfig index d6a02110e3b..ccd836bce23 100644 --- a/boards/arm/stm32/photon/configs/wlan-perf/defconfig +++ b/boards/arm/stm32/photon/configs/wlan-perf/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32/photon/configs/wlan/defconfig index c2cf5294c3b..97ef2d948dd 100644 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ b/boards/arm/stm32/photon/configs/wlan/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_PHOTON=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32/shenzhou/configs/nsh/defconfig index 3cad521d666..b2165bef2b2 100644 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig index 815572c9038..66414f65561 100644 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ b/boards/arm/stm32/shenzhou/configs/nxwm/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_ETH0_PHY_DM9161=y diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig index 7a6bad14a95..4316fa865f2 100644 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ b/boards/arm/stm32/shenzhou/configs/thttpd/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_SHENZHOU=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig index 82259cb8156..4d34cbf1d2f 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig index 315e9136cf1..47fd55dd162 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig index 0f9b059c5d2..e4725eae5e5 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig @@ -24,6 +24,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig index f221932c7c7..6b36c1764c1 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_CONSOLE_SYSLOG=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig index 395633cb5f0..b0bb9f6722e 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig index 4fd1d15afc4..b463e9b6cb4 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_IDLE_CUSTOM=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig index 976438a2393..cf8067e033f 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig index 205b97bbc4e..2e238975a91 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ b/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT_OABI=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig index 4765c757824..99c464911f8 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_DISABLE_ENVIRON=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig index ad6101db818..1d654ac87eb 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_CONSOLE_SYSLOG=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig index 45e7aca47f1..fc5b0a1d607 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig index 25cbc3ad5eb..5c70dff6840 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig index 4756ef1512f..560ebc95176 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_ETH0_PHY_DP83848C=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig index 7ca6a50bbac..6ff3b7d474f 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_STM3220G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y +CONFIG_ARCH_CHIP_STM32F2=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=10926 CONFIG_CONSOLE_SYSLOG=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig index 1e1d4bae5c1..34b5600ff35 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_DISABLE_ENVIRON=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig index fa73ac6e959..c44d9a0e2bd 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_DISCOVER_DESCR="STM3240G-EVAL" diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig index 7db5d2ec714..5dc598e063b 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig index dc2de40c871..203da50b7bb 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig index cecabe2f65f..01e8df44d21 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_CONSOLE_SYSLOG=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig index e445c306c4d..b10f9d1ad78 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig index 007647eefa5..1020cc7ac97 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig index cdf394741be..d1fbb36a5eb 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig index 550058e72ce..50139a990d9 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_FAT_LCNAMES=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig index b34caaabfe6..f97d570a56f 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_CONSOLE_SYSLOG=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig index b50bf38bc91..ac283d015d3 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_EXAMPLES_NETTEST=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig index ca17c0e962f..23c950db80b 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ b/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_STM3240G_EVAL=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_ETH0_PHY_DP83848C=y diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig index 221484c5f59..d8ef1dff900 100644 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32_TINY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig index 39ded7939a6..3ff9fd0c32e 100644 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig @@ -24,6 +24,7 @@ CONFIG_ARCH_BOARD_STM32_TINY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig index 79655e199f1..893268b7731 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig index 762efdfdce2..346a366f30e 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig index 294531d34d6..31c7bc88829 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig index 79655e199f1..893268b7731 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ b/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig index 493f2fdb003..d907586a307 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig @@ -35,6 +35,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig index 2789b752ecf..6104e46be6d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig index 6c6800df69d..b8535b6a90f 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y CONFIG_AUDIO_TONE=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig index 11c015562a8..cd55e62de45 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig @@ -24,6 +24,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig index 8d76332f3de..10d91ed5c67 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig @@ -36,6 +36,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig index 029d1efc944..ac563e19f7b 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_DEFAULT_SMALL=y CONFIG_DISABLE_MOUNTPOINT=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig index 5eea66e1f1b..03814d1bd53 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig index b91f9cca66b..29472d4f0ac 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig index 9f2e614adb3..3a16a7bc3ed 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig index ac06a6bc606..fe3f09845e6 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig index 3c704737ee2..93f668740d1 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig @@ -36,6 +36,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig index 8d0dda31037..d8c11ad84e0 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig index 9b30668c97e..dfff987949b 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig index cba32112192..047341ed0b4 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig @@ -22,6 +22,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig index 589d6e8d4dd..3fd2d3dbf38 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig @@ -21,6 +21,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_BOARDCTL=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig index 8ab229454da..66f457ffcf6 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig @@ -36,6 +36,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig index a633b578537..c88a05558e1 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig @@ -24,6 +24,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=5483 diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig index 931b29c9ded..3977f0bef72 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig index 3f439883df6..9fa8c828abe 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig @@ -23,6 +23,7 @@ CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig index 8c31ee1302b..2f7c28b1b2a 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig index db3bc11cbbb..e7c49036087 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig index 10a5ed5968f..b08e14d40ba 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig @@ -30,6 +30,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_TOOLCHAIN_BUILDROOT=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig index 1973cf7321a..b05c264572a 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=6522 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig index 5d388639fb4..11e8b675785 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303VC=y +CONFIG_ARCH_CHIP_STM32F3=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=6522 diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig index 2c10476201e..6e22dc02126 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig index ee0e197c265..178a756ab5d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig index 4487a2834aa..9c1468d40d2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig index 87491419a25..df1e41dab3d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig index 68f78a2565b..dcb15b1eb51 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig index b431f061e80..9fa82205b31 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig index 100a1658edf..e911ed96554 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig index d24b43acad1..2359bdf62c1 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig index 2e5ad3de7e2..311c24b5ce4 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig index 199a6fe8f23..62e05716167 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig index 4effd9f2056..934fe5937d5 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig index 041d1063cf9..0b08c8a1637 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig index e6a0c65cdab..60be3f8d8ef 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig index bdd8cbb1b33..17e9bcd416a 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig index 0ebbf98d62c..3e49da0d35e 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig index 38212b7cf51..17abb4b5997 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig index 8810cd175f3..f1b9b35d2cd 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig index 8394c946d47..4604117e6a1 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig index 7f4abba8eac..0b46c33727a 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig index 3b481dfd674..fd0ea5aa335 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig index 371cea88bf7..d9e14188dee 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig index 3f60dea5481..eea54a81ee2 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig index c5ebec8a82b..df31e577207 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig index bc6985a1d4c..6534f827cf1 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig index 1d49a8275be..a4b9ef9cb77 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig index 3a2397b01be..dae6672714d 100644 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BOARD_STM32F411E_DISCO=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411VE=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=8499 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig index 2e4718deb92..40e510989cc 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig index d9f7431a024..82c861c4e6d 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig index 61264520860..2e3dce2e53e 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig index f4449b5807f..ff349a213b4 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig index a2ae14866f2..4982ec9e495 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=4096 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig index d8fe5c1b7d9..207032d4861 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig index 55ff0bb5b9f..cc548e45b17 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig index d4b2f40ad71..34f00994c65 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig index 1b17784c3aa..1ab0fba0f4f 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig index fc3c836a064..89ff4b37859 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig index 819fa8d7df8..c3300bb7d34 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig index e0d8d16cb0f..15ff2c9db50 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig index 03a81bfa4c3..c3dc124c4a5 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INSTRUMENT_ALL=y CONFIG_ARCH_INTERRUPTSTACK=4096 CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig index 2500bae8c27..10a6be5de4a 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig index 03447b3fac8..9e9a7617949 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig index 7246fb6ffad..53447258b17 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig index 70765999bf7..3b05080d90f 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig index 7a58739b221..623d3a1e1bb 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_AUDIO=y CONFIG_AUDIO_CS43L22=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig index bb8d3b33270..ecd9f77382d 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig index 553cc77d002..869c48008b0 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig index 8485892f11c..dbe02211a04 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig index 6dd62ac3583..d6797cbdc44 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig index 9784e9650a4..225ef545f47 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_DISABLE_MOUNTPOINT=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig index d67f3e5aa69..e56e68e8342 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_CONSTRUCTORS=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig index 41f42ad54d1..a4a5c25d0e0 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig index 910ab3e1436..6858d9793fa 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig index cc106c43eb4..2a280821536 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARM_MPU=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig index da7f85f99a7..a77136217c5 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig index 562e7ffef0e..9e891cdedc8 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig index 05486e4a8f7..9781ef94b88 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig index 9be5d50f0b3..9535be0eca2 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig @@ -47,6 +47,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig index 7c3b724bbed..954b7b3a225 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig index 7e4857ec739..43ba01f9c0e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig index 3b84fd63e69..df1afdd0b43 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/module/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig index c6b607db287..21b36c9bdd4 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig index 609bf1e8f07..0245779431b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig index acf1c69a886..ec06dd1c797 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig index 27dc6222beb..88ce0cf4f4c 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig index 8ecab5062eb..3802741e950 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_EXAMPLES_NXLINES=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig index efc7a7cfe45..97640d9aed1 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL=y CONFIG_BOARDCTL_MKRD=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig index 4f196c9c570..2213a49a0f5 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_IDLE_CUSTOM=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig index 9f49ec41573..7300c051e05 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BINFMT_CONSTRUCTORS=y CONFIG_BOARDCTL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig index 2deb457fa77..86c0b568849 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig index 48ded7700ac..54b58a3d240 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig index fde92641665..78c093599ac 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig index 2dbb1e6193a..f97fa10aa37 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig index 3af85b79a13..9162788372a 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig index e3166d9e8a1..5da6dfcacc8 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig index 9d846ecf6a4..d1a66e7735a 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig index fd17d315831..98bd5b03d4a 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig index 0bc84e9ee02..b5881e0ef33 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig index dce3e3d343b..76611a126a3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_USBDEVCTRL=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig index 9867fcf30a5..dec3fc4699e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig index e0237c63e67..13fc63197cb 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y +CONFIG_ARCH_CHIP_STM32F4=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig index 0167eac8ad0..9022ce804f8 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig @@ -19,6 +19,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_IRQBUTTONS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig index f6f307ffc1e..0ed417736d6 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y +CONFIG_ARCH_CHIP_STM32L1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2796 CONFIG_DEFAULT_SMALL=y diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig index 58ac9e12dae..388c171d65c 100644 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F100RB=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=2398 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig index f952c3ca348..a12fed7ddbf 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig index 817e9d62fd4..1c9bac124dc 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_HIPRI_INTERRUPT=y CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig index 083ecf7359a..186f2553905 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig index b68528e2301..6a9adabea7b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig index 1e3c72298e8..30468070067 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ b/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_CHIP="stm32" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y +CONFIG_ARCH_CHIP_STM32F1=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARD_LOOPSPERMSEC=5483 CONFIG_BUILTIN=y From d0665a8cffab25e741cefb8769dde1f36a502192 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 09:42:40 +0800 Subject: [PATCH 029/268] Documentation/applications/system/ip6tables: add ip6tables man page Add comprehensive documentation for the ip6tables command including all supported commands, options, and IPv6-specific usage examples. Signed-off-by: hanzhijian --- .../applications/system/ip6tables/index.rst | 160 ++++++++++++++++++ 1 file changed, 160 insertions(+) create mode 100644 Documentation/applications/system/ip6tables/index.rst diff --git a/Documentation/applications/system/ip6tables/index.rst b/Documentation/applications/system/ip6tables/index.rst new file mode 100644 index 00000000000..563a133d0e9 --- /dev/null +++ b/Documentation/applications/system/ip6tables/index.rst @@ -0,0 +1,160 @@ +============================== +``ip6tables`` IPv6 firewall +============================== + +The ``ip6tables`` command is used to set up, maintain, and inspect the +tables of IPv6 packet filter rules in the NuttX kernel. + +Configuration +============= + +- :kconfig:option:`CONFIG_SYSTEM_IP6TABLES` +- :kconfig:option:`CONFIG_NET_IPTABLES` +- :kconfig:option:`CONFIG_NET_IPv6` + +The following additional options are available: + +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_PRIORITY` - Task priority + (default: 100) +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_STACKSIZE` - Stack size + (default: ``DEFAULT_TASK_STACKSIZE``) + +Usage +===== + +.. code-block:: text + + ip6tables -t table -[AD] chain rule-specification + ip6tables -t table -I chain [rulenum] rule-specification + ip6tables -t table -D chain rulenum + ip6tables -t table -P chain target + ip6tables -t table -[FL] [chain] + +Commands +======== + +``-A, --append chain`` + Append one or more rules to the end of the selected chain. + +``-D, --delete chain [rulenum]`` + Delete one or more rules from the selected chain. If ``rulenum`` is + specified, delete the rule at that position. + +``-I, --insert chain [rulenum]`` + Insert one or more rules at the given position in the selected chain. + If ``rulenum`` is not specified, the rule is inserted at position 1. + +``-L, --list [chain]`` + List all rules in the selected chain. If no chain is specified, all + chains in the table are listed. + +``-F, --flush [chain]`` + Delete all rules in the selected chain. If no chain is specified, all + chains in the table are flushed. + +``-P, --policy chain target`` + Set the policy for the built-in chain to the specified target. The + target must be ``ACCEPT`` or ``DROP``. + +Options +======= + +``-t, --table table`` + Specify the table to manipulate. The default table is ``filter``. + + Only the ``filter`` table is currently supported (requires + :kconfig:option:`CONFIG_NET_IPFILTER`). + +``-j, --jump target`` + Specify the target of the rule; i.e., what to do if the packet + matches it. The target can be ``ACCEPT``, ``DROP``, or a custom + target name. + +``[!] -s, --source address[/mask]`` + Source specification. ``address`` can be a network name, hostname, + network IPv6 address (with ``/mask``), or plain IPv6 address. The + mask is specified as a prefix length (e.g., ``/64``). The ``!`` + argument inverts the match. + +``[!] -d, --destination address[/mask]`` + Destination specification. Same format as ``--source``. + +``[!] -p, --protocol protocol`` + Protocol of the rule or of the packet to check. The specified + protocol can be one of ``tcp``, ``udp``, ``icmp6``, ``icmpv6``, + ``ipv6-icmp``, ``esp``, or ``all``, or a numeric protocol number. + The ``!`` argument inverts the match. + +``[!] -i, --in-interface dev`` + Name of an interface via which a packet was received. The ``!`` + argument inverts the match. + +``[!] -o, --out-interface dev`` + Name of an interface via which a packet is going to be sent. The + ``!`` argument inverts the match. + +``[!] --sport, --source-port port[:port]`` + Source port specification. Can be a single port or a port range + (e.g., ``1024:65535``). Only valid with ``-p tcp`` or ``-p udp``. + The ``!`` argument inverts the match. + +``[!] --dport, --destination-port port[:port]`` + Destination port specification. Same format as ``--source-port``. + +``[!] --icmpv6-type type`` + ICMPv6 type specification. Can be a numeric type (0-255). Only + valid with ``-p icmp6`` (or ``-p icmpv6``, ``-p ipv6-icmp``). The + ``!`` argument inverts the match. + +``!`` + Inverts the following match criterion. + +Examples +======== + +List all rules in the filter table: + +.. code-block:: text + + nsh> ip6tables -L + +Append a rule to allow TCP traffic on port 22: + +.. code-block:: text + + nsh> ip6tables -A INPUT -p tcp --dport 22 -j ACCEPT + +Insert a rule at position 1 to drop UDP traffic from a specific source: + +.. code-block:: text + + nsh> ip6tables -I INPUT 1 -s fc00::1 -p udp -j DROP + +Delete a specific rule by rule number: + +.. code-block:: text + + nsh> ip6tables -D INPUT 1 + +Set the default policy for the INPUT chain to DROP: + +.. code-block:: text + + nsh> ip6tables -P INPUT DROP + +Flush all rules in the INPUT chain: + +.. code-block:: text + + nsh> ip6tables -F INPUT + +Use negation to match all protocols except TCP: + +.. code-block:: text + + nsh> ip6tables -A INPUT ! -p tcp -j ACCEPT + +See Also +======== + +- :doc:`../iptables/index` From a0c9463f015246f750c149575327d9b73d399f32 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 10:02:48 +0800 Subject: [PATCH 030/268] fix: replace :kconfig:option: with plain backticks for Sphinx compatibility --- .../applications/system/ip6tables/index.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/Documentation/applications/system/ip6tables/index.rst b/Documentation/applications/system/ip6tables/index.rst index 563a133d0e9..a73409bb2e7 100644 --- a/Documentation/applications/system/ip6tables/index.rst +++ b/Documentation/applications/system/ip6tables/index.rst @@ -8,15 +8,15 @@ tables of IPv6 packet filter rules in the NuttX kernel. Configuration ============= -- :kconfig:option:`CONFIG_SYSTEM_IP6TABLES` -- :kconfig:option:`CONFIG_NET_IPTABLES` -- :kconfig:option:`CONFIG_NET_IPv6` +- ``CONFIG_SYSTEM_IP6TABLES`` +- ``CONFIG_NET_IPTABLES`` +- ``CONFIG_NET_IPv6`` The following additional options are available: -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_PRIORITY` - Task priority +- ``CONFIG_SYSTEM_IPTABLES_PRIORITY`` - Task priority (default: 100) -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_STACKSIZE` - Stack size +- ``CONFIG_SYSTEM_IPTABLES_STACKSIZE`` - Stack size (default: ``DEFAULT_TASK_STACKSIZE``) Usage @@ -63,7 +63,7 @@ Options Specify the table to manipulate. The default table is ``filter``. Only the ``filter`` table is currently supported (requires - :kconfig:option:`CONFIG_NET_IPFILTER`). + ``CONFIG_NET_IPFILTER``). ``-j, --jump target`` Specify the target of the rule; i.e., what to do if the packet @@ -157,4 +157,4 @@ Use negation to match all protocols except TCP: See Also ======== -- :doc:`../iptables/index` +- :doc:`../iptables/index`` From 21157586bc5f18ab7089a5dd14fc43a6552b38b3 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 11:43:34 +0800 Subject: [PATCH 031/268] fix: remove extra backtick in See Also doc reference --- Documentation/applications/system/ip6tables/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/applications/system/ip6tables/index.rst b/Documentation/applications/system/ip6tables/index.rst index a73409bb2e7..cb928751ea8 100644 --- a/Documentation/applications/system/ip6tables/index.rst +++ b/Documentation/applications/system/ip6tables/index.rst @@ -157,4 +157,4 @@ Use negation to match all protocols except TCP: See Also ======== -- :doc:`../iptables/index`` +- :doc:`../iptables/index` From ffd09067e4d9f2d672dc189acaa53729a96a1459 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 09:38:06 +0800 Subject: [PATCH 032/268] Documentation/applications/system/iptables: add iptables man page Add comprehensive documentation for the iptables command including all supported commands, options, and usage examples. Signed-off-by: hanzhijian --- .../applications/system/iptables/index.rst | 175 +++++++++++++++++- 1 file changed, 172 insertions(+), 3 deletions(-) diff --git a/Documentation/applications/system/iptables/index.rst b/Documentation/applications/system/iptables/index.rst index 248bde72274..d9510a93968 100644 --- a/Documentation/applications/system/iptables/index.rst +++ b/Documentation/applications/system/iptables/index.rst @@ -1,3 +1,172 @@ -=============================== -``iptables`` "iptables" command -=============================== +============================= +``iptables`` IPv4 firewall +============================= + +The ``iptables`` command is used to set up, maintain, and inspect the +tables of IPv4 packet filter rules in the NuttX kernel. + +Configuration +============= + +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES` +- :kconfig:option:`CONFIG_NET_IPTABLES` +- :kconfig:option:`CONFIG_NET_IPv4` + +The following additional options are available: + +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_PRIORITY` - Task priority + (default: 100) +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_STACKSIZE` - Stack size + (default: ``DEFAULT_TASK_STACKSIZE``) +- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_LOCK_FILE_PATH` - Lock file + path to prevent concurrent overwrite (default: ``/tmp/iptables.lock``) + +Usage +===== + +.. code-block:: text + + iptables -t table -[AD] chain rule-specification + iptables -t table -I chain [rulenum] rule-specification + iptables -t table -D chain rulenum + iptables -t table -P chain target + iptables -t table -[FL] [chain] + +Commands +======== + +``-A, --append chain`` + Append one or more rules to the end of the selected chain. + +``-D, --delete chain [rulenum]`` + Delete one or more rules from the selected chain. If ``rulenum`` is + specified, delete the rule at that position. + +``-I, --insert chain [rulenum]`` + Insert one or more rules at the given position in the selected chain. + If ``rulenum`` is not specified, the rule is inserted at position 1. + +``-L, --list [chain]`` + List all rules in the selected chain. If no chain is specified, all + chains in the table are listed. + +``-F, --flush [chain]`` + Delete all rules in the selected chain. If no chain is specified, all + chains in the table are flushed. + +``-P, --policy chain target`` + Set the policy for the built-in chain to the specified target. The + target must be ``ACCEPT`` or ``DROP``. + +Options +======= + +``-t, --table table`` + Specify the table to manipulate. The default table is ``filter``. + + The following tables are available: + + - ``filter``: The default table for packet filtering (requires + :kconfig:option:`CONFIG_NET_IPFILTER`). + - ``nat``: Used for Network Address Translation (requires + :kconfig:option:`CONFIG_NET_NAT`). Only supports the + ``MASQUERADE`` target with ``-o`` option. + +``-j, --jump target`` + Specify the target of the rule; i.e., what to do if the packet + matches it. The target can be ``ACCEPT``, ``DROP``, or a custom + target name. + +``[!] -s, --source address[/mask]`` + Source specification. ``address`` can be a network name, hostname, + network IP address (with ``/mask``), or plain IP address. The mask + can be a network prefix length (e.g., ``/24``) or a plain mask + (e.g., ``255.255.255.0``). The ``!`` argument inverts the match. + +``[!] -d, --destination address[/mask]`` + Destination specification. Same format as ``--source``. + +``[!] -p, --protocol protocol`` + Protocol of the rule or of the packet to check. The specified + protocol can be one of ``tcp``, ``udp``, ``icmp``, ``esp``, or + ``all``, or a numeric protocol number. The ``!`` argument inverts + the match. + +``[!] -i, --in-interface dev`` + Name of an interface via which a packet was received. The ``!`` + argument inverts the match. + +``[!] -o, --out-interface dev`` + Name of an interface via which a packet is going to be sent. The + ``!`` argument inverts the match. + +``[!] --sport, --source-port port[:port]`` + Source port specification. Can be a single port or a port range + (e.g., ``1024:65535``). Only valid with ``-p tcp`` or ``-p udp``. + The ``!`` argument inverts the match. + +``[!] --dport, --destination-port port[:port]`` + Destination port specification. Same format as ``--source-port``. + +``[!] --icmp-type type`` + ICMP type specification. Can be a numeric type (0-255). Only valid + with ``-p icmp``. The ``!`` argument inverts the match. + +``!`` + Inverts the following match criterion. + +Examples +======== + +List all rules in the filter table: + +.. code-block:: text + + nsh> iptables -L + +Append a rule to allow TCP traffic on port 80: + +.. code-block:: text + + nsh> iptables -A INPUT -p tcp --dport 80 -j ACCEPT + +Insert a rule at position 1 to drop UDP traffic from a specific source: + +.. code-block:: text + + nsh> iptables -I INPUT 1 -s 192.168.1.100 -p udp -j DROP + +Delete a specific rule by rule number: + +.. code-block:: text + + nsh> iptables -D INPUT 1 + +Set the default policy for the INPUT chain to DROP: + +.. code-block:: text + + nsh> iptables -P INPUT DROP + +Flush all rules in the INPUT chain: + +.. code-block:: text + + nsh> iptables -F INPUT + +Use NAT with MASQUERADE on an output interface: + +.. code-block:: text + + nsh> iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE + +Use negation to match all protocols except TCP: + +.. code-block:: text + + nsh> iptables -A INPUT ! -p tcp -j ACCEPT + +See Also +======== + +- :doc:`../ip6tables/index` From 77060179dd0de76c7042bf2d9f8e5130744f5c96 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 10:03:14 +0800 Subject: [PATCH 033/268] fix: replace :kconfig:option: with plain backticks for Sphinx compatibility --- .../applications/system/iptables/index.rst | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/applications/system/iptables/index.rst b/Documentation/applications/system/iptables/index.rst index d9510a93968..002b4805b7f 100644 --- a/Documentation/applications/system/iptables/index.rst +++ b/Documentation/applications/system/iptables/index.rst @@ -8,17 +8,17 @@ tables of IPv4 packet filter rules in the NuttX kernel. Configuration ============= -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES` -- :kconfig:option:`CONFIG_NET_IPTABLES` -- :kconfig:option:`CONFIG_NET_IPv4` +- ``CONFIG_SYSTEM_IPTABLES`` +- ``CONFIG_NET_IPTABLES`` +- ``CONFIG_NET_IPv4`` The following additional options are available: -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_PRIORITY` - Task priority +- ``CONFIG_SYSTEM_IPTABLES_PRIORITY`` - Task priority (default: 100) -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_STACKSIZE` - Stack size +- ``CONFIG_SYSTEM_IPTABLES_STACKSIZE`` - Stack size (default: ``DEFAULT_TASK_STACKSIZE``) -- :kconfig:option:`CONFIG_SYSTEM_IPTABLES_LOCK_FILE_PATH` - Lock file +- ``CONFIG_SYSTEM_IPTABLES_LOCK_FILE_PATH`` - Lock file path to prevent concurrent overwrite (default: ``/tmp/iptables.lock``) Usage @@ -67,9 +67,9 @@ Options The following tables are available: - ``filter``: The default table for packet filtering (requires - :kconfig:option:`CONFIG_NET_IPFILTER`). + ``CONFIG_NET_IPFILTER``). - ``nat``: Used for Network Address Translation (requires - :kconfig:option:`CONFIG_NET_NAT`). Only supports the + ``CONFIG_NET_NAT``). Only supports the ``MASQUERADE`` target with ``-o`` option. ``-j, --jump target`` From cdf500960f1520a1061c4929b0c850d1bd9c67bb Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 10:20:38 +0800 Subject: [PATCH 034/268] fix: remove cross-reference to ip6tables doc not yet in tree --- Documentation/applications/system/iptables/index.rst | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Documentation/applications/system/iptables/index.rst b/Documentation/applications/system/iptables/index.rst index 002b4805b7f..7f92715340d 100644 --- a/Documentation/applications/system/iptables/index.rst +++ b/Documentation/applications/system/iptables/index.rst @@ -166,7 +166,3 @@ Use negation to match all protocols except TCP: nsh> iptables -A INPUT ! -p tcp -j ACCEPT -See Also -======== - -- :doc:`../ip6tables/index` From 5de32920f7375906c5b1546dc2cde219ff7874f8 Mon Sep 17 00:00:00 2001 From: yushuailong Date: Wed, 10 Jun 2026 19:21:07 +0800 Subject: [PATCH 035/268] drivers/timers: Fix non-atomic clock read in up_timer_gettime. up_timer_gettime() computed tv_sec and tv_nsec from two separate calls to current_usec(), which returns a free-running microsecond counter. The counter advances between the two calls, so a read that straddles a second boundary yields an inconsistent (possibly backwards) timespec. Read current_usec() once into a local variable and derive both fields from that single snapshot. Signed-off-by: yushuailong --- drivers/timers/arch_timer.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/timers/arch_timer.c b/drivers/timers/arch_timer.c index c3cf4f83d06..c0cb09fd9d6 100644 --- a/drivers/timers/arch_timer.c +++ b/drivers/timers/arch_timer.c @@ -289,11 +289,14 @@ int weak_function up_timer_gettick(FAR clock_t *ticks) int weak_function up_timer_gettime(struct timespec *ts) { int ret = -EAGAIN; + uint64_t usec; if (g_timer.lower != NULL) { - ts->tv_sec = current_usec() / USEC_PER_SEC; - ts->tv_nsec = (current_usec() % USEC_PER_SEC) * NSEC_PER_USEC; + usec = current_usec(); + + ts->tv_sec = usec / USEC_PER_SEC; + ts->tv_nsec = (usec % USEC_PER_SEC) * NSEC_PER_USEC; ret = OK; } From c11029848e85e13fb186399d9495002c717cad04 Mon Sep 17 00:00:00 2001 From: yushuailong Date: Wed, 10 Jun 2026 19:21:15 +0800 Subject: [PATCH 036/268] arch/xtensa/espressif: Fix non-atomic clock read in esp_rtc_rdalarm. esp_rtc_rdalarm() computed tv_sec and tv_nsec from two separate evaluations of esp_hr_timer_time_us() + offset + deadline. The high-resolution timer advances between the two calls, so a read that straddles a second boundary yields an inconsistent timespec. Compute the microsecond value once into a local variable and derive both fields from that single snapshot. Signed-off-by: yushuailong --- arch/xtensa/src/common/espressif/esp_rtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/xtensa/src/common/espressif/esp_rtc.c b/arch/xtensa/src/common/espressif/esp_rtc.c index 2d08b1d056e..bb4e200b54e 100644 --- a/arch/xtensa/src/common/espressif/esp_rtc.c +++ b/arch/xtensa/src/common/espressif/esp_rtc.c @@ -611,6 +611,7 @@ static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, struct timespec ts; struct alm_cbinfo_s *cbinfo; irqstate_t flags; + uint64_t time_us; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarminfo != NULL); @@ -624,10 +625,11 @@ static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, cbinfo = &priv->alarmcb[alarminfo->id]; - ts.tv_sec = (esp_hr_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - ts.tv_nsec = ((esp_hr_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + time_us = esp_hr_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us; + + ts.tv_sec = time_us / USEC_PER_SEC; + ts.tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; localtime_r(&ts.tv_sec, (struct tm *)alarminfo->time); From 1d08a9d019d89f3575e92754227041a159a73c81 Mon Sep 17 00:00:00 2001 From: yushuailong Date: Wed, 10 Jun 2026 19:21:24 +0800 Subject: [PATCH 037/268] arch/risc-v/espressif: Fix non-atomic clock read in esp_rtc_rdalarm. esp_rtc_rdalarm() computed tv_sec and tv_nsec from two separate evaluations of esp_hr_timer_time_us() + offset + deadline. The high-resolution timer advances between the two calls, so a read that straddles a second boundary yields an inconsistent timespec. Compute the microsecond value once into a local variable and derive both fields from that single snapshot. Signed-off-by: yushuailong --- arch/risc-v/src/common/espressif/esp_rtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/common/espressif/esp_rtc.c b/arch/risc-v/src/common/espressif/esp_rtc.c index ed76d633527..16c10abe401 100644 --- a/arch/risc-v/src/common/espressif/esp_rtc.c +++ b/arch/risc-v/src/common/espressif/esp_rtc.c @@ -612,6 +612,7 @@ static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, struct timespec ts; struct alm_cbinfo_s *cbinfo; irqstate_t flags; + uint64_t time_us; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarminfo != NULL); @@ -625,10 +626,11 @@ static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, cbinfo = &priv->alarmcb[alarminfo->id]; - ts.tv_sec = (esp_hr_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - ts.tv_nsec = ((esp_hr_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + time_us = esp_hr_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us; + + ts.tv_sec = time_us / USEC_PER_SEC; + ts.tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; localtime_r(&ts.tv_sec, (struct tm *)alarminfo->time); From 1a3185beebf43093ffcc7d4e2caae57ebc2eef44 Mon Sep 17 00:00:00 2001 From: yushuailong Date: Wed, 10 Jun 2026 19:21:30 +0800 Subject: [PATCH 038/268] arch/risc-v/esp32c3-legacy: Fix non-atomic clock read in up_rtc_rdalarm. up_rtc_rdalarm() computed tv_sec and tv_nsec from two separate evaluations of rt_timer_time_us() + offset + deadline. The RT timer advances between the two calls, so a read that straddles a second boundary yields an inconsistent timespec. Compute the microsecond value once into a local variable and derive both fields from that single snapshot. Signed-off-by: yushuailong --- arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c index 0db475b59c5..dc71fa86b32 100644 --- a/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c @@ -3383,6 +3383,7 @@ int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) { irqstate_t flags; struct alm_cbinfo_s *cbinfo; + uint64_t time_us; DEBUGASSERT(tp != NULL); DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); @@ -3393,10 +3394,11 @@ int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) cbinfo = &g_alarmcb[alarmid]; - tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + time_us = rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us; + + tp->tv_sec = time_us / USEC_PER_SEC; + tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; spin_unlock_irqrestore(&g_rtc_lock, flags); From 726dd10bcd092dd6e1fbc8e6a9b1b83734ced5a4 Mon Sep 17 00:00:00 2001 From: Michal Lenc Date: Thu, 4 Jun 2026 13:20:44 +0200 Subject: [PATCH 039/268] fs/vfs/fs_lock.c: fix flock behavior for more threads and fds We need to use gettid instead of getpid, otherwise flocks applied from different threads are considered as single thread lock and are ignored (or updated). Also fix the behavior if process opens the file multiple times Linux/BSD manual states multiple file descriptors opened by a single process shall be treated independently. Therefore we also need to compare struct file pointer to determine whether the lock applies to the same descriptor or not. Signed-off-by: Michal Lenc --- fs/vfs/fs_lock.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/fs/vfs/fs_lock.c b/fs/vfs/fs_lock.c index 535b35ec39f..54c9eebcc75 100644 --- a/fs/vfs/fs_lock.c +++ b/fs/vfs/fs_lock.c @@ -260,18 +260,20 @@ static void file_lock_delete_bucket(FAR struct file_lock_bucket_s *bucket, ****************************************************************************/ static bool file_lock_is_conflict(FAR struct flock *request, - FAR struct flock *internal) + FAR struct file *request_filep, + FAR struct file_lock_s *internal) { /* If the request is not exactly to the left or right of the internal, * then there is an overlap. */ - if (request->l_start <= internal->l_end && request->l_end >= - internal->l_start) + if (request->l_start <= internal->fl_lock.l_end && request->l_end >= + internal->fl_lock.l_start) { - if (request->l_type == F_WRLCK || internal->l_type == F_WRLCK) + if (request->l_type == F_WRLCK || internal->fl_lock.l_type == F_WRLCK) { - return request->l_pid != internal->l_pid; + return request->l_pid != internal->fl_lock.l_pid || + request_filep != internal->fl_file; } } @@ -371,8 +373,8 @@ static int file_lock_modify(FAR struct file *filep, { if (request->l_pid != file_lock->fl_lock.l_pid) { - /* Only file locks with the same pid need to be processed, so the - * lookup is skipped. + /* Only file locks with the same thread id need to be + * processed, so the lookup is skipped. */ if (find) @@ -598,7 +600,7 @@ int file_getlk(FAR struct file *filep, FAR struct flock *flock) list_for_every_entry(&bucket->list, file_lock, struct file_lock_s, fl_node) { - if (file_lock_is_conflict(flock, &file_lock->fl_lock)) + if (file_lock_is_conflict(flock, filep, file_lock)) { memcpy(flock, &file_lock->fl_lock, sizeof(*flock)); goto out; @@ -677,7 +679,7 @@ int file_setlk(FAR struct file *filep, FAR struct flock *flock, goto out_free; } - request.l_pid = getpid(); + request.l_pid = gettid(); nxmutex_lock(&g_protect_lock); @@ -709,7 +711,7 @@ retry: list_for_every_entry(&bucket->list, file_lock, struct file_lock_s, fl_node) { - if (file_lock_is_conflict(&request, &file_lock->fl_lock)) + if (file_lock_is_conflict(&request, filep, file_lock)) { if (nonblock) { From e1a9b953e259c5498eda2794971f11ae724848e1 Mon Sep 17 00:00:00 2001 From: Michal Lenc Date: Wed, 10 Jun 2026 16:05:02 +0200 Subject: [PATCH 040/268] fs/vfs/fs_lock.c: support flock for SHM driver We can apply file lock on SHM inode as well. Ensure file_lock_get_path function passes and doesn't return EBADF errno. Signed-off-by: Michal Lenc --- fs/vfs/fs_lock.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/fs/vfs/fs_lock.c b/fs/vfs/fs_lock.c index 54c9eebcc75..135232da452 100644 --- a/fs/vfs/fs_lock.c +++ b/fs/vfs/fs_lock.c @@ -102,10 +102,13 @@ static int file_lock_get_path(FAR struct file *filep, FAR char *path) FAR struct tcb_s *tcb = this_task(); bool is_allowed_type; - /* We only apply file lock on mountpt and driver (f_inode won't be NULL). */ + /* We only apply file lock on mountpt, driver or shm + * (f_inode won't be NULL). + */ is_allowed_type = INODE_IS_MOUNTPT(filep->f_inode) || - INODE_IS_DRIVER(filep->f_inode); + INODE_IS_DRIVER(filep->f_inode) || + INODE_IS_SHM(filep->f_inode); if (!is_allowed_type || tcb->flags & TCB_FLAG_SIGNAL_ACTION) { From 0574de1801b2845598f76d67b417f6fcbff54f39 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 10 Jun 2026 08:41:51 +0200 Subject: [PATCH 041/268] arch/arm/src/stm32f7: remove duplicated stm32_exti_alarm.c source stm32_exti_alarm.c was added twice in Make.defs and CMakeLists.txt. Drop the duplicate block Signed-off-by: raiden00pl --- arch/arm/src/stm32f7/CMakeLists.txt | 6 ------ arch/arm/src/stm32f7/Make.defs | 6 ------ 2 files changed, 12 deletions(-) diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index fbf052e2458..e7e7126cd17 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -132,12 +132,6 @@ if(CONFIG_STM32F7_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32F7_RTC) - if(CONFIG_RTC_ALARM) - list(APPEND SRCS stm32_exti_alarm.c) - endif() -endif() - if(CONFIG_STM32F7_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 4c9fe1c7319..01e8d8c4408 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -134,12 +134,6 @@ ifeq ($(CONFIG_STM32F7_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) -ifeq ($(CONFIG_RTC_ALARM),y) -CHIP_CSRCS += stm32_exti_alarm.c -endif -endif - ifeq ($(CONFIG_STM32F7_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif From d7f168061b27e61eccefec7aa35d10ac2a52b8d1 Mon Sep 17 00:00:00 2001 From: lccosy <1191294205@qq.com> Date: Thu, 11 Jun 2026 00:02:55 +0800 Subject: [PATCH 042/268] arch/arm/gd32f4: fix missing CTL selector bits in up_disableusartint. up_disableusartint() saves USART interrupt state from hardware CTL0-CTL3 registers but omits the CTL selector bits (bits 24-27) in the encoded ie value. When up_restoreusartint() later restores interrupts, it uses ie >> 24 to determine which CTL register to write. Without selector bits this evaluates to 0, so no CTL register is updated and all interrupt enables (including RBNEIE) are permanently lost. This causes RX interrupts to never fire after any call to up_putc() (e.g. via syslog), making the serial console unable to receive input. Fix by adding the corresponding CTL selector bit (USART_CFG_CTLx_INT << USART_CFG_SHIFT) whenever a CTL register has active interrupt bits. Signed-off-by: lccosy <1191294205@qq.com> --- arch/arm/src/gd32f4/gd32f4xx_serial.c | 30 +++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 7291a9dceec..5ced798a320 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -1142,25 +1142,47 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) { uint32_t ctl; + ctl_ie = 0; + /* Save interrupt in CTL0 register */ ctl = up_serialin(priv, GD32_USART_CTL0_OFFSET); - ctl_ie = ((ctl & USART_CTL0_USED_INTS) >> USART_CFG_CTL0_INT_SHIFT); + if (ctl & USART_CTL0_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL0_USED_INTS) >> + USART_CFG_CTL0_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL0_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL1 register */ ctl = up_serialin(priv, GD32_USART_CTL1_OFFSET); - ctl_ie |= ((ctl & USART_CTL1_USED_INTS) >> USART_CFG_CTL1_INT_SHIFT); + if (ctl & USART_CTL1_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL1_USED_INTS) >> + USART_CFG_CTL1_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL1_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL2 register */ ctl = up_serialin(priv, GD32_USART_CTL2_OFFSET); - ctl_ie |= ((ctl & USART_CTL2_USED_INTS) << USART_CFG_CTL2_INT_SHIFT); + if (ctl & USART_CTL2_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL2_USED_INTS) << + USART_CFG_CTL2_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL2_INT << USART_CFG_SHIFT); + } /* Save interrupt in CTL3 register */ ctl = up_serialin(priv, GD32_USART_CTL3_OFFSET); - ctl_ie |= ((ctl & USART_CTL3_USED_INTS) << USART_CFG_CTL3_INT_SHIFT); + if (ctl & USART_CTL3_USED_INTS) + { + ctl_ie |= ((ctl & USART_CTL3_USED_INTS) << + USART_CFG_CTL3_INT_SHIFT); + ctl_ie |= (USART_CFG_CTL3_INT << USART_CFG_SHIFT); + } *ie = ctl_ie; } From ce01327a458c39803f791de6d37866c75c2f327d Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Sat, 6 Jun 2026 16:47:24 +0000 Subject: [PATCH 043/268] fs/vfs: inherit ownership in pseudofile_create Initialize i_owner and i_group from the creating task's effective uid/gid when a pseudo-file is created via O_CREAT. This aligns pseudo-file ownership with the creator's effective credentials instead of leaving new files root-owned by default. Signed-off-by: Abhishek Mishra --- fs/vfs/fs_pseudofile.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/fs/vfs/fs_pseudofile.c b/fs/vfs/fs_pseudofile.c index 7b091bce740..e5376cfe97e 100644 --- a/fs/vfs/fs_pseudofile.c +++ b/fs/vfs/fs_pseudofile.c @@ -468,6 +468,10 @@ int pseudofile_create(FAR struct inode **node, FAR const char *path, mode_t mode) { FAR struct fs_pseudofile_s *pf; +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && \ + defined(CONFIG_SCHED_USER_IDENTITY) + FAR struct tcb_s *rtcb; +#endif int ret; if (node == NULL || path == NULL) @@ -493,6 +497,18 @@ int pseudofile_create(FAR struct inode **node, FAR const char *path, (*node)->i_flags = 1; (*node)->u.i_ops = &g_pseudofile_ops; (*node)->i_private = pf; + +#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && \ + defined(CONFIG_SCHED_USER_IDENTITY) + + rtcb = nxsched_self(); + if (rtcb != NULL && rtcb->group != NULL) + { + (*node)->i_owner = rtcb->group->tg_euid; + (*node)->i_group = rtcb->group->tg_egid; + } +#endif + atomic_fetch_add(&(*node)->i_crefs, 1); inode_unlock(); From bb025be12db86bad3e1a7b931926bf646e2ed5e5 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 11 Jun 2026 09:19:39 +0200 Subject: [PATCH 044/268] arch/nrf91: add PWM support add PWM support for nrf91 Signed-off-by: raiden00pl --- arch/arm/src/nrf91/Kconfig | 39 ++ arch/arm/src/nrf91/hardware/nrf91_pwm.h | 180 ++++++ arch/arm/src/nrf91/nrf91_pwm.c | 706 ++++++++++++++++++++++++ arch/arm/src/nrf91/nrf91_pwm.h | 133 +++++ 4 files changed, 1058 insertions(+) create mode 100644 arch/arm/src/nrf91/hardware/nrf91_pwm.h create mode 100644 arch/arm/src/nrf91/nrf91_pwm.c create mode 100644 arch/arm/src/nrf91/nrf91_pwm.h diff --git a/arch/arm/src/nrf91/Kconfig b/arch/arm/src/nrf91/Kconfig index 57048b5fb8c..120688899fd 100644 --- a/arch/arm/src/nrf91/Kconfig +++ b/arch/arm/src/nrf91/Kconfig @@ -203,6 +203,11 @@ config NRF91_PWM2 select NRF91_PWM default n +config NRF91_PWM3 + bool "PWM3" + select NRF91_PWM + default n + config NRF91_SAADC bool "SAADC" default n @@ -568,6 +573,34 @@ config NRF91_PWM2_CH3 endif # NRF91_PWM2 +if NRF91_PWM3 + +config NRF91_PWM3_CH0 + bool "PWM3 Channel 0 Output" + default n + ---help--- + Enables channel 0 output. + +config NRF91_PWM3_CH1 + bool "PWM3 Channel 1 Output" + default n + ---help--- + Enables channel 1 output. + +config NRF91_PWM3_CH2 + bool "PWM3 Channel 2 Output" + default n + ---help--- + Enables channel 2 output. + +config NRF91_PWM3_CH3 + bool "PWM3 Channel 3 Output" + default n + ---help--- + Enables channel 3 output. + +endif # NRF91_PWM3 + endif # !NRF91_PWM_MULTICHAN if !NRF91_PWM_MULTICHAN @@ -590,6 +623,12 @@ config NRF91_PWM2_CHANNEL default 0 range 0 3 +config NRF91_PWM3_CHANNEL + int "PWM3 Output Channel" + depends on NRF91_PWM3 + default 0 + range 0 3 + endif # !NRF91_PWM_MULTICHAN endif # NRF91_PWM diff --git a/arch/arm/src/nrf91/hardware/nrf91_pwm.h b/arch/arm/src/nrf91/hardware/nrf91_pwm.h new file mode 100644 index 00000000000..95249fc1a1c --- /dev/null +++ b/arch/arm/src/nrf91/hardware/nrf91_pwm.h @@ -0,0 +1,180 @@ +/**************************************************************************** + * arch/arm/src/nrf91/hardware/nrf91_pwm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_PWM_H +#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/nrf91_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Register offsets *********************************************************/ + +#define NRF91_PWM_TASKS_STOP_OFFSET 0x0004 /* Stop PWM */ +#define NRF91_PWM_TASKS_SEQSTART0_OFFSET 0x0008 /* Sequence 0 start */ +#define NRF91_PWM_TASKS_SEQSTART1_OFFSET 0x000c /* Sequence 1 start */ +#define NRF91_PWM_TASKS_NEXTSTEP_OFFSET 0x0010 /* Steps by one value in the current sequence */ + /* TODO: 0x084-0x090 */ +#define NRF91_PWM_EVENTS_STOPPED_OFFSET 0x0104 /* STOP event */ +#define NRF91_PWM_EVENTS_SEQSTARTED0_OFFSET 0x0108 /* Sequence 0 started event */ +#define NRF91_PWM_EVENTS_SEQSTARTED1_OFFSET 0x010c /* Sequence 1 started event */ +#define NRF91_PWM_EVENTS_SEQEND0_OFFSET 0x0110 /* Sequence 0 end event */ +#define NRF91_PWM_EVENTS_SEQEND1_OFFSET 0x0114 /* Sequence 1 end event */ +#define NRF91_PWM_EVENTS_PWMPERIODEN_OFFSET 0x0118 /* PWM period end event */ +#define NRF91_PWM_EVENTS_LOOPSDONE_OFFSET 0x011c /* Loop done event */ + /* TODO: 0x184-0x19c */ +#define NRF91_PWM_SHORTS_OFFSET 0x0200 /* Shourtcut register */ +#define NRF91_PWM_INTEN_OFFSET 0x0300 /* Enable or disable interrupt */ +#define NRF91_PWM_INTENSET_OFFSET 0x0304 /* Enable interrupt */ +#define NRF91_PWM_INTENCLR_OFFSET 0x0308 /* Disable interrupt */ +#define NRF91_PWM_ENABLE_OFFSET 0x0500 /* PWM enable */ +#define NRF91_PWM_MODE_OFFSET 0x0504 /* Wave counter mode */ +#define NRF91_PWM_COUNTERTOP_OFFSET 0x0508 /* Counter max value */ +#define NRF91_PWM_PRESCALER_OFFSET 0x050c /* Prescaler configuration */ +#define NRF91_PWM_DECODER_OFFSET 0x0510 /* Configuration of the decoder */ +#define NRF91_PWM_LOOP_OFFSET 0x0514 /* Amount of playback of a loop */ +#define NRF91_PWM_SEQ0PTR_OFFSET 0x0520 /* Sequence 0 beginning address */ +#define NRF91_PWM_SEQ0CNT_OFFSET 0x0524 /* Sequence 0 length */ +#define NRF91_PWM_SEQ0REFRESH_OFFSET 0x0528 /* Sequence 0 additional periods */ +#define NRF91_PWM_SEQ0ENDDELAY_OFFSET 0x052c /* Time added after sequence 0 */ +#define NRF91_PWM_SEQ1PTR_OFFSET 0x0540 /* Sequence 1 beginning address */ +#define NRF91_PWM_SEQ1CNT_OFFSET 0x0544 /* Sequence 1 length */ +#define NRF91_PWM_SEQ1REFRESH_OFFSET 0x0548 /* Sequence 0 additional periods */ +#define NRF91_PWM_SEQ1ENDDELAY_OFFSET 0x054c /* Time added after sequence 1 */ +#define NRF91_PWM_PSEL0_OFFSET 0x0560 /* Output pin select for PWM chan 0 */ +#define NRF91_PWM_PSEL1_OFFSET 0x0564 /* Output pin select for PWM chan 1 */ +#define NRF91_PWM_PSEL2_OFFSET 0x0568 /* Output pin select for PWM chan 2 */ +#define NRF91_PWM_PSEL3_OFFSET 0x056c /* Output pin select for PWM chan 3 */ + +/* Register Bitfield Definitions ********************************************/ + +/* TASKS_STOP Register */ + +#define PWM_TASKS_STOP (1 << 0) /* Bit 0: Stop PWM */ + +/* TASKS_SEQSTART[n] Register */ + +#define PWM_TASKS_SEQSTART (1 << 0) /* Bit 0: Start sequence */ + +/* TASKS_NEXTSTEP Register */ + +#define PWM_TASKS_NEXTSTEP (1 << 0) /* Bit 0: Next step */ + +/* SHORTS Register */ + +#define PWM_SHORTS_SEQEND0_STOP (1 << 0) /* Bit 0: Shortcut between event SEQEND[0] and task STOP */ +#define PWM_SHORTS_SEQEND1_STOP (1 << 1) /* Bit 1: Shortcut between event SEQEND[1] and task STOP */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART0 (1 << 2) /* Bit 2: Shortcut between event LOOPSDONE and task SEQSTART[0] */ +#define PWM_SHORTS_LOOPSDONE_SEQSTART1 (1 << 3) /* Bit 3: Shortcut between event LOOPSDONE and task SEQSTART[1] */ +#define PWM_SHORTS_LOOPSDONE_STOP (1 << 4) /* Bit 4: Shortcut between event LOOPSDONE and task STOP */ + +/* INTEN/INTENSET/INTENCLR Register */ + +#define PWM_INT_STOPPED (1 << 0) /* Bit 0: Interrupt for event STOPPED */ +#define PWM_INT_SEQSTARTED0 (1 << 1) /* Bit 1: Interrupt for event SEQSTARTED0 */ +#define PWM_INT_SEQSTARTED1 (1 << 2) /* Bit 2: Interrupt for event SEQSTARTED2 */ +#define PWM_INT_SEQEND0 (1 << 3) /* Bit 3: Interrupt for event SEQEND0 */ +#define PWM_INT_SEQEND1 (1 << 4) /* Bit 4: Interrupt for event SEQEND1 */ +#define PWM_INT_PWMPERIODEND (1 << 5) /* Bit 5: Interrupt for event PWMPERIODEND */ +#define PWM_INT_LOOPSDONE (1 << 6) /* Bit 6: Interrupt for event LOOPSDONE */ + +/* ENABLE Register */ + +#define PWM_ENABLE_ENABLE (1 << 0) /* Bit 0: Enable PWM module */ +#define PWM_ENABLE_DISABLE (0 << 0) /* Bit 0: Disable PWM module */ + +/* MODE Register */ + +#define PWM_MODE_UP (0 << 0) /* Bit 0: Up counter, edge-aligned PWM */ +#define PWM_MODE_UPDOWN (1 << 0) /* Bit 0: Up and down counter, center-aligned PWM */ + +/* COUNTERTOP Register */ + +#define PWM_COUNTERTOP_MASK (0x7fff) + +/* PRESCALER Register */ + +#define PWM_PRESCALER_SHIFT (0) +#define PWM_PRESCALER_MASK (7 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_16MHZ (0 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_8MHZ (1 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_4MHZ (2 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_2MHZ (3 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_1MHZ (4 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_500KHZ (5 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_250KHZ (6 << PWM_PRESCALER_SHIFT) +# define PWM_PRESCALER_125KHZ (7 << PWM_PRESCALER_SHIFT) + +/* DECODER Register */ + +#define PWM_DECODER_LOAD_SHIFT (0) /* Bits 0-1: How a sequence is read from RAM */ +#define PWM_DECODER_LOAD_MASK (3 << PWM_DECODER_LOAD_SHIFT) +# define PWM_DECODER_LOAD_COMMON (0 << PWM_DECODER_LOAD_SHIFT) +# define PWM_DECODER_LOAD_GROUPED (1 << PWM_DECODER_LOAD_SHIFT) +# define PWM_DECODER_LOAD_INDIVIDUAL (2 << PWM_DECODER_LOAD_SHIFT) +# define PWM_DECODER_LOAD_WAVEFORM (3 << PWM_DECODER_LOAD_SHIFT) + +#define PWM_DECODER_MODE_REFRESH (8 << 0) /* Bit 8: */ +#define PWM_DECODER_MODE_NEXTSTEP (8 << 1) /* Bit 8: */ + +/* LOOP Register */ + +#define PWM_LOOP_MASK (0xffff) + +/* SEQ[n]CNT Register */ + +#define PWM_SEQCNT_MASK (0x7fff) + +/* SEQ[n]REFRESH Register */ + +#define PWM_SEQREFRESH_MASK (0xffffff) + +/* SEQ[n]ENDDELAY Register */ + +#define PWM_SEQENDDELAY_MASK (0xffffff) + +/* PSEL[x] Register */ + +#define PWM_PSEL_PIN_SHIFT (0) /* Bits 0-4: OUT pin number */ +#define PWM_PSEL_PIN_MASK (0x1f << PWM_PSELSDA_PIN_SHIFT) +#define PWM_PSEL_PORT_SHIFT (5) /* Bit 5: PUT port number */ +#define PWM_PSEL_PORT_MASK (0x1 << PWM_PSELSDA_PORT_SHIFT) +#define PWM_PSEL_CONNECTED (1 << 31) /* Bit 31: Connection */ +#define PWM_PSEL_RESET (0xffffffff) + +/* Decoder data */ + +#define PWM_DECODER_COMPARE_SHIFT (0) +#define PWM_DECODER_COMPARE_MASK (0x7fff) +#define PWM_DECODER_POL_RISING (0 << 15) +#define PWM_DECODER_POL_FALLING (1 << 15) + +#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_PWM_H */ diff --git a/arch/arm/src/nrf91/nrf91_pwm.c b/arch/arm/src/nrf91/nrf91_pwm.c new file mode 100644 index 00000000000..964ac96ef51 --- /dev/null +++ b/arch/arm/src/nrf91/nrf91_pwm.c @@ -0,0 +1,706 @@ +/**************************************************************************** + * arch/arm/src/nrf91/nrf91_pwm.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "nrf91_gpio.h" +#include "nrf91_pwm.h" + +#include "hardware/nrf91_pwm.h" +#include "hardware/nrf91_utils.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default PWM polarity */ + +#define PWM_POLARITY_DEFAULT (PWM_DECODER_POL_FALLING) + +/* Sequence 0 length */ + +#define PWM_SEQ0_LEN (4) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct nrf91_pwm_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + uint32_t base; /* Base address of PWM register */ + uint32_t frequency; /* Current frequency setting */ + uint32_t cntrtop; /* Counter top */ + uint32_t ch0_pin; /* Channel 1 pin */ + uint32_t ch1_pin; /* Channel 2 pin */ + uint32_t ch2_pin; /* Channel 3 pin */ + uint32_t ch3_pin; /* Channel 4 pin */ + + /* Sequence 0 */ + + uint16_t seq0[PWM_SEQ0_LEN]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* PWM Register access */ + +static inline void nrf91_pwm_putreg(struct nrf91_pwm_s *priv, + uint32_t offset, + uint32_t value); +static inline uint32_t nrf91_pwm_getreg(struct nrf91_pwm_s *priv, + uint32_t offset); + +/* PWM helpers */ + +static int nrf91_pwm_configure(struct nrf91_pwm_s *priv); +static int nrf91_pwm_duty(struct nrf91_pwm_s *priv, uint8_t chan, + ub16_t duty); +static int nrf91_pwm_freq(struct nrf91_pwm_s *priv, uint32_t freq); + +/* PWM driver methods */ + +static int nrf91_pwm_setup(struct pwm_lowerhalf_s *dev); +static int nrf91_pwm_shutdown(struct pwm_lowerhalf_s *dev); +static int nrf91_pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); +static int nrf91_pwm_stop(struct pwm_lowerhalf_s *dev); +static int nrf91_pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver. + */ + +static const struct pwm_ops_s g_nrf91_pwmops = +{ + .setup = nrf91_pwm_setup, + .shutdown = nrf91_pwm_shutdown, + .start = nrf91_pwm_start, + .stop = nrf91_pwm_stop, + .ioctl = nrf91_pwm_ioctl, +}; + +#ifdef CONFIG_NRF91_PWM0 +/* PWM 0 */ + +struct nrf91_pwm_s g_nrf91_pwm0 = +{ + .ops = &g_nrf91_pwmops, + .base = NRF91_PWM0_BASE, +#ifdef CONFIG_NRF91_PWM0_CH0 + .ch0_pin = NRF91_PWM0_CH0_PIN, +#endif +#ifdef CONFIG_NRF91_PWM0_CH1 + .ch1_pin = NRF91_PWM0_CH1_PIN, +#endif +#ifdef CONFIG_NRF91_PWM0_CH2 + .ch2_pin = NRF91_PWM0_CH2_PIN, +#endif +#ifdef CONFIG_NRF91_PWM0_CH3 + .ch3_pin = NRF91_PWM0_CH3_PIN, +#endif +}; +#endif + +#ifdef CONFIG_NRF91_PWM1 +/* PWM 1 */ + +struct nrf91_pwm_s g_nrf91_pwm1 = +{ + .ops = &g_nrf91_pwmops, + .base = NRF91_PWM1_BASE, +#ifdef CONFIG_NRF91_PWM1_CH0 + .ch0_pin = NRF91_PWM1_CH0_PIN, +#endif +#ifdef CONFIG_NRF91_PWM1_CH1 + .ch1_pin = NRF91_PWM1_CH1_PIN, +#endif +#ifdef CONFIG_NRF91_PWM1_CH2 + .ch2_pin = NRF91_PWM1_CH2_PIN, +#endif +#ifdef CONFIG_NRF91_PWM1_CH3 + .ch3_pin = NRF91_PWM1_CH3_PIN, +#endif +}; +#endif + +#ifdef CONFIG_NRF91_PWM2 +/* PWM 2 */ + +struct nrf91_pwm_s g_nrf91_pwm2 = +{ + .ops = &g_nrf91_pwmops, + .base = NRF91_PWM2_BASE, +#ifdef CONFIG_NRF91_PWM2_CH0 + .ch0_pin = NRF91_PWM2_CH0_PIN, +#endif +#ifdef CONFIG_NRF91_PWM2_CH1 + .ch1_pin = NRF91_PWM2_CH1_PIN, +#endif +#ifdef CONFIG_NRF91_PWM2_CH2 + .ch2_pin = NRF91_PWM2_CH2_PIN, +#endif +#ifdef CONFIG_NRF91_PWM2_CH3 + .ch3_pin = NRF91_PWM2_CH3_PIN, +#endif +}; +#endif + +#ifdef CONFIG_NRF91_PWM3 +/* PWM 2 */ + +struct nrf91_pwm_s g_nrf91_pwm3 = +{ + .ops = &g_nrf91_pwmops, + .base = NRF91_PWM3_BASE, +#ifdef CONFIG_NRF91_PWM3_CH0 + .ch0_pin = NRF91_PWM3_CH0_PIN, +#endif +#ifdef CONFIG_NRF91_PWM3_CH1 + .ch1_pin = NRF91_PWM3_CH1_PIN, +#endif +#ifdef CONFIG_NRF91_PWM3_CH2 + .ch2_pin = NRF91_PWM3_CH2_PIN, +#endif +#ifdef CONFIG_NRF91_PWM3_CH3 + .ch3_pin = NRF91_PWM3_CH3_PIN, +#endif +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_pwm_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void nrf91_pwm_putreg(struct nrf91_pwm_s *priv, + uint32_t offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: nrf91_pwm_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t nrf91_pwm_getreg(struct nrf91_pwm_s *priv, + uint32_t offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: nrf91_pwm_configure + * + * Description: + * Configure PWM + * + ****************************************************************************/ + +static int nrf91_pwm_configure(struct nrf91_pwm_s *priv) +{ + uint32_t regval = 0; + int ret = OK; + + DEBUGASSERT(priv); + + /* Configure PWM mode */ + + nrf91_pwm_putreg(priv, NRF91_PWM_MODE_OFFSET, PWM_MODE_UP); + + /* Configure decoder */ + + regval = PWM_DECODER_LOAD_INDIVIDUAL | PWM_DECODER_MODE_REFRESH; + nrf91_pwm_putreg(priv, NRF91_PWM_DECODER_OFFSET, regval); + + /* Configure sequence 0 */ + + regval = (uint32_t)priv->seq0; + DEBUGASSERT(nrf91_easydma_valid(regval)); + nrf91_pwm_putreg(priv, NRF91_PWM_SEQ0PTR_OFFSET, regval); + + regval = PWM_SEQ0_LEN; + nrf91_pwm_putreg(priv, NRF91_PWM_SEQ0CNT_OFFSET, regval); + + regval = 0; + nrf91_pwm_putreg(priv, NRF91_PWM_SEQ0REFRESH_OFFSET, regval); + + return ret; +} + +/**************************************************************************** + * Name: nrf91_pwm_duty + * + * Description: + * Configure PWM duty + * + ****************************************************************************/ + +static int nrf91_pwm_duty(struct nrf91_pwm_s *priv, uint8_t chan, + ub16_t duty) +{ + uint16_t compare = 0; + + DEBUGASSERT(priv); + + pwminfo("PWM channel: %d duty: %" PRId32 "\n", chan, duty); + + /* Get compare + * + * duty cycle = compare / reload (fractional value) + */ + + compare = b16toi(duty * priv->cntrtop + b16HALF); + + /* Configure channel sequence */ + + priv->seq0[chan] = PWM_POLARITY_DEFAULT | compare; + + pwminfo("seq0[%d]: %d %d\n", chan, compare, priv->seq0[chan]); + + return OK; +} + +/**************************************************************************** + * Name: nrf91_pwm_freq + * + * Description: + * Configure PWM frequency + * + ****************************************************************************/ + +static int nrf91_pwm_freq(struct nrf91_pwm_s *priv, uint32_t freq) +{ + uint32_t regval = 0; + uint32_t pwm_clk = 0; + uint32_t top = 0; + uint32_t prescaler = 0; + uint64_t tmp = 0; + int ret = OK; + + DEBUGASSERT(priv); + + /* Get best prescaler */ + + tmp = PWM_COUNTERTOP_MASK * freq; + + if (tmp >= 16000000) + { + pwm_clk = 16000000; + prescaler = PWM_PRESCALER_16MHZ; + } + else if (tmp >= 8000000) + { + pwm_clk = 8000000; + prescaler = PWM_PRESCALER_8MHZ; + } + else if (tmp >= 4000000) + { + pwm_clk = 4000000; + prescaler = PWM_PRESCALER_4MHZ; + } + else if (tmp >= 2000000) + { + pwm_clk = 2000000; + prescaler = PWM_PRESCALER_2MHZ; + } + else if (tmp >= 1000000) + { + pwm_clk = 1000000; + prescaler = PWM_PRESCALER_1MHZ; + } + else if (tmp >= 500000) + { + pwm_clk = 500000; + prescaler = PWM_PRESCALER_500KHZ; + } + else if (tmp >= 250000) + { + pwm_clk = 250000; + prescaler = PWM_PRESCALER_250KHZ; + } + else + { + pwm_clk = 125000; + prescaler = PWM_PRESCALER_125KHZ; + } + + /* Configure prescaler */ + + nrf91_pwm_putreg(priv, NRF91_PWM_PRESCALER_OFFSET, prescaler); + + /* Get counter max */ + + top = pwm_clk / freq; + if (top < 2) + { + top = 1; + } + else if (top > PWM_COUNTERTOP_MASK) + { + top = PWM_COUNTERTOP_MASK; + } + else + { + top = top - 1; + } + + /* Configure counter max */ + + regval = top; + nrf91_pwm_putreg(priv, NRF91_PWM_COUNTERTOP_OFFSET, regval); + + priv->cntrtop = top; + + pwminfo("PWM frequency: %" PRId32 " pwm_clk: %" PRId32 + " pwm_prescaler: %" PRId32 " top: %" PRId32 "\n", + freq, pwm_clk, prescaler, top); + + return ret; +} + +/**************************************************************************** + * Name: nrf91_pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + ****************************************************************************/ + +static int nrf91_pwm_setup(struct pwm_lowerhalf_s *dev) +{ + struct nrf91_pwm_s *priv = (struct nrf91_pwm_s *)dev; + int ret = OK; + uint32_t regval = 0; + uint32_t pin = 0; + uint32_t port = 0; + + DEBUGASSERT(dev); + + /* Configure channels */ + + if (priv->ch0_pin != 0) + { + nrf91_gpio_config(priv->ch0_pin); + + pin = GPIO_PIN_DECODE(priv->ch0_pin); + port = GPIO_PORT_DECODE(priv->ch0_pin); + + regval = (port << PWM_PSEL_PORT_SHIFT); + regval |= (pin << PWM_PSEL_PIN_SHIFT); + + nrf91_pwm_putreg(priv, NRF91_PWM_PSEL0_OFFSET, regval); + } + + if (priv->ch1_pin != 0) + { + nrf91_gpio_config(priv->ch1_pin); + + pin = GPIO_PIN_DECODE(priv->ch1_pin); + port = GPIO_PORT_DECODE(priv->ch1_pin); + + regval = (port << PWM_PSEL_PORT_SHIFT); + regval |= (pin << PWM_PSEL_PIN_SHIFT); + + nrf91_pwm_putreg(priv, NRF91_PWM_PSEL1_OFFSET, regval); + } + + if (priv->ch2_pin != 0) + { + nrf91_gpio_config(priv->ch2_pin); + + pin = GPIO_PIN_DECODE(priv->ch2_pin); + port = GPIO_PORT_DECODE(priv->ch2_pin); + + regval = (port << PWM_PSEL_PORT_SHIFT); + regval |= (pin << PWM_PSEL_PIN_SHIFT); + + nrf91_pwm_putreg(priv, NRF91_PWM_PSEL2_OFFSET, regval); + } + + if (priv->ch3_pin != 0) + { + nrf91_gpio_config(priv->ch3_pin); + + pin = GPIO_PIN_DECODE(priv->ch3_pin); + port = GPIO_PORT_DECODE(priv->ch3_pin); + + regval = (port << PWM_PSEL_PORT_SHIFT); + regval |= (pin << PWM_PSEL_PIN_SHIFT); + + nrf91_pwm_putreg(priv, NRF91_PWM_PSEL3_OFFSET, regval); + } + + /* Configure PWM */ + + ret = nrf91_pwm_configure(priv); + if (ret < 0) + { + pwmerr("ERROR: nrf91_pwm_configure failed %d\n", ret); + goto errout; + } + + /* Enable PWM */ + + nrf91_pwm_putreg(priv, NRF91_PWM_ENABLE_OFFSET, 1); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf91_pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + ****************************************************************************/ + +static int nrf91_pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + struct nrf91_pwm_s *priv = (struct nrf91_pwm_s *)dev; + int ret = OK; + + DEBUGASSERT(dev); + + /* Disable PWM */ + + nrf91_pwm_putreg(priv, NRF91_PWM_ENABLE_OFFSET, 0); + + return ret; +} + +/**************************************************************************** + * Name: nrf91_pwm_start + * + * Description: + * (Re-)initialize the PWM and start the pulsed output + * + ****************************************************************************/ + +static int nrf91_pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct nrf91_pwm_s *priv = (struct nrf91_pwm_s *)dev; + int ret = OK; + int i = 0; + + DEBUGASSERT(dev); + + /* If frequency has not changed we just update duty */ + + if (info->frequency != priv->frequency) + { + /* Update frequency */ + + ret = nrf91_pwm_freq(priv, info->frequency); + + if (ret == OK) + { + priv->frequency = info->frequency; + } + } + + for (i = 0; ret == OK && i < CONFIG_PWM_NCHANNELS; i++) + { + /* Break the loop if all following channels are not configured */ + + if (info->channels[i].channel == -1) + { + break; + } + + /* Set output if channel configured */ + + if (info->channels[i].channel != 0) + { + ret = nrf91_pwm_duty(priv, + (info->channels[i].channel - 1), + info->channels[i].duty); + } + } + + /* Start sequence 0 */ + + nrf91_pwm_putreg(priv, NRF91_PWM_TASKS_SEQSTART0_OFFSET, 1); + + /* Wait for sequence started */ + + while (nrf91_pwm_getreg(priv, NRF91_PWM_EVENTS_SEQSTARTED0_OFFSET) != 1); + + return ret; +} + +/**************************************************************************** + * Name: nrf91_pwm_stop + * + * Description: + * Stop the PWM + * + ****************************************************************************/ + +static int nrf91_pwm_stop(struct pwm_lowerhalf_s *dev) +{ + struct nrf91_pwm_s *priv = (struct nrf91_pwm_s *)dev; + + DEBUGASSERT(dev); + + /* Stop PWM */ + + nrf91_pwm_putreg(priv, NRF91_PWM_TASKS_STOP_OFFSET, 1); + + /* Wait for PWM stopped */ + + while (nrf91_pwm_getreg(priv, NRF91_PWM_EVENTS_STOPPED_OFFSET) != 1); + + return OK; +} + +/**************************************************************************** + * Name: nrf91_pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + ****************************************************************************/ + +static int nrf91_pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg) +{ + struct nrf91_pwm_s *priv = (struct nrf91_pwm_s *)dev; + + DEBUGASSERT(dev); + + /* There are no platform-specific ioctl commands */ + + UNUSED(priv); + + return -ENOTTY; +} + +/**************************************************************************** + * Public Function + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * pwm - A number identifying the pwm instance. + * + * Returned Value: + * On success, a pointer to the NRF91 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *nrf91_pwminitialize(int pwm) +{ + struct nrf91_pwm_s *lower = NULL; + + pwminfo("Initialize PWM%u\n", pwm); + + switch (pwm) + { +#ifdef CONFIG_NRF91_PWM0 + case 0: + { + lower = &g_nrf91_pwm0; + break; + } +#endif + +#ifdef CONFIG_NRF91_PWM1 + case 1: + { + lower = &g_nrf91_pwm1; + break; + } +#endif + +#ifdef CONFIG_NRF91_PWM2 + case 2: + { + lower = &g_nrf91_pwm2; + break; + } +#endif + +#ifdef CONFIG_NRF91_PWM3 + case 3: + { + lower = &g_nrf91_pwm3; + break; + } +#endif + + default: + { + pwmerr("ERROR: No such PWM device %d\n", pwm); + lower = NULL; + goto errout; + } + } + +errout: + return (struct pwm_lowerhalf_s *)lower; +} diff --git a/arch/arm/src/nrf91/nrf91_pwm.h b/arch/arm/src/nrf91/nrf91_pwm.h new file mode 100644 index 00000000000..19e72781876 --- /dev/null +++ b/arch/arm/src/nrf91/nrf91_pwm.h @@ -0,0 +1,133 @@ +/**************************************************************************** + * arch/arm/src/nrf91/nrf91_pwm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF91_NRF91_PWM_H +#define __ARCH_ARM_SRC_NRF91_NRF91_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Enable the specified PWM channel if multichannel PWM is disabled */ + +#ifndef CONFIG_NRF91_PWM_MULTICHAN + +# ifdef CONFIG_NRF91_PWM0 +# if !defined(CONFIG_NRF91_PWM0_CHANNEL) +# error "CONFIG_NRF91_PWM0_CHANNEL must be provided" +# elif CONFIG_NRF91_PWM0_CHANNEL == 0 +# define CONFIG_NRF91_PWM0_CH0 1 +# elif CONFIG_NRF91_PWM0_CHANNEL == 1 +# define CONFIG_NRF91_PWM0_CH1 1 +# elif CONFIG_NRF91_PWM0_CHANNEL == 2 +# define CONFIG_NRF91_PWM0_CH2 1 +# elif CONFIG_NRF91_PWM0_CHANNEL == 3 +# define CONFIG_NRF91_PWM0_CH3 1 +# else +# error "Unsupported value of CONFIG_NRF91_PWM0_CHANNEL" +# endif +# endif + +# ifdef CONFIG_NRF91_PWM1 +# if !defined(CONFIG_NRF91_PWM1_CHANNEL) +# error "CONFIG_NRF91_PWM1_CHANNEL must be provided" +# elif CONFIG_NRF91_PWM1_CHANNEL == 0 +# define CONFIG_NRF91_PWM1_CH0 1 +# elif CONFIG_NRF91_PWM1_CHANNEL == 1 +# define CONFIG_NRF91_PWM1_CH1 1 +# elif CONFIG_NRF91_PWM1_CHANNEL == 2 +# define CONFIG_NRF91_PWM1_CH2 1 +# elif CONFIG_NRF91_PWM1_CHANNEL == 3 +# define CONFIG_NRF91_PWM1_CH3 1 +# else +# error "Unsupported value of CONFIG_NRF91_PWM1_CHANNEL" +# endif +# endif + +# ifdef CONFIG_NRF91_PWM2 +# if !defined(CONFIG_NRF91_PWM2_CHANNEL) +# error "CONFIG_NRF91_PWM2_CHANNEL must be provided" +# elif CONFIG_NRF91_PWM2_CHANNEL == 0 +# define CONFIG_NRF91_PWM2_CH0 1 +# elif CONFIG_NRF91_PWM2_CHANNEL == 1 +# define CONFIG_NRF91_PWM2_CH1 1 +# elif CONFIG_NRF91_PWM2_CHANNEL == 2 +# define CONFIG_NRF91_PWM2_CH2 1 +# elif CONFIG_NRF91_PWM2_CHANNEL == 3 +# define CONFIG_NRF91_PWM2_CH3 1 +# else +# error "Unsupported value of CONFIG_NRF91_PWM2_CHANNEL" +# endif +# endif + +# ifdef CONFIG_NRF91_PWM3 +# if !defined(CONFIG_NRF91_PWM3_CHANNEL) +# error "CONFIG_NRF91_PWM3_CHANNEL must be provided" +# elif CONFIG_NRF91_PWM3_CHANNEL == 0 +# define CONFIG_NRF91_PWM3_CH0 1 +# elif CONFIG_NRF91_PWM3_CHANNEL == 1 +# define CONFIG_NRF91_PWM3_CH1 1 +# elif CONFIG_NRF91_PWM3_CHANNEL == 2 +# define CONFIG_NRF91_PWM3_CH2 1 +# elif CONFIG_NRF91_PWM3_CHANNEL == 3 +# define CONFIG_NRF91_PWM3_CH3 1 +# else +# error "Unsupported value of CONFIG_NRF91_PWM3_CHANNEL" +# endif +# endif + +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_pwminitialize + * + * Description: + * Initialize one timer for use with the upper_level PWM driver. + * + * Input Parameters: + * pwm - A number identifying the pwm instance. + * + * Returned Value: + * On success, a pointer to the NRF91 lower half PWM driver is returned. + * NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *nrf91_pwminitialize(int pwm); + +#endif /* __ARCH_ARM_SRC_NRF91_NRF91_PWM_H */ From f442c6b05efb6e5fc78f2e4721b1655f11b4d8db Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Thu, 11 Jun 2026 16:29:16 +0300 Subject: [PATCH 045/268] libs/libc/pthread/pthread_mutex: Fix robust mutex initialization This fixes an issue where ostest robust mutex test gets stuck. In CONFIG_PTHREAD_MUTEX_ROBUST mode, every NORMAL mutex is robust by definition, so the robust flag must be set to allow the mutex to be tracked in the holder's mutex list. Otherwise, pthread_mutex_add() will not record the mutex and pthread_mutex_inconsistent() will not be able to mark it as inconsistent or wake waiters when the holder thread terminates. Signed-off-by: Jukka Laitinen --- libs/libc/pthread/pthread_mutex_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libs/libc/pthread/pthread_mutex_init.c b/libs/libc/pthread/pthread_mutex_init.c index e9ca24b0347..9c6529ce87a 100644 --- a/libs/libc/pthread/pthread_mutex_init.c +++ b/libs/libc/pthread/pthread_mutex_init.c @@ -86,7 +86,7 @@ int pthread_mutex_init(FAR pthread_mutex_t *mutex, mutex->flags = attr && attr->robust == PTHREAD_MUTEX_ROBUST ? _PTHREAD_MFLAGS_ROBUST : 0; # else - mutex->flags = 0; + mutex->flags = _PTHREAD_MFLAGS_ROBUST; # endif #endif From 14661fdba07b4389e8ed7ae2539609da9841756a Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Wed, 10 Jun 2026 08:03:35 +0000 Subject: [PATCH 046/268] sched/group: implement POSIX saved-set-UID/GID semantics Adds tg_suid and tg_sgid fields to task_group_s to complete the POSIX three-field identity model (real, effective, saved-set). Updates group_inherit_identity() to propagate the new fields from parent to child task group on task creation. Fixes setuid(), setgid(), seteuid(), and setegid() to implement correct POSIX privilege transition logic: - Root (euid==0): may set any value; all three IDs updated by setuid/setgid - Non-root: may only set effective ID to real or saved value; else EPERM Signed-off-by: Abhishek Mishra --- include/nuttx/sched.h | 2 ++ sched/group/group_create.c | 6 ++++-- sched/group/group_setegid.c | 17 ++++++++++++++--- sched/group/group_seteuid.c | 17 ++++++++++++++--- sched/group/group_setgid.c | 24 +++++++++++++++++++++--- sched/group/group_setuid.c | 24 +++++++++++++++++++++--- 6 files changed, 76 insertions(+), 14 deletions(-) diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 61e9c461108..ca3781995bd 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -462,6 +462,8 @@ struct task_group_s gid_t tg_gid; /* User group identity */ uid_t tg_euid; /* Effective user identity */ gid_t tg_egid; /* Effective user group identity */ + uid_t tg_suid; /* Saved set-user identity */ + gid_t tg_sgid; /* Saved set-group identity */ #endif /* Group membership *******************************************************/ diff --git a/sched/group/group_create.c b/sched/group/group_create.c index 473f6df0acf..677d818b37c 100644 --- a/sched/group/group_create.c +++ b/sched/group/group_create.c @@ -78,10 +78,12 @@ static inline void group_inherit_identity(FAR struct task_group_s *group) /* Inherit the user identity from the parent task group. */ DEBUGASSERT(group != NULL); - group->tg_uid = rgroup->tg_uid; - group->tg_gid = rgroup->tg_gid; + group->tg_uid = rgroup->tg_uid; + group->tg_gid = rgroup->tg_gid; group->tg_euid = rgroup->tg_euid; group->tg_egid = rgroup->tg_egid; + group->tg_suid = rgroup->tg_suid; + group->tg_sgid = rgroup->tg_sgid; } #else # define group_inherit_identity(group) diff --git a/sched/group/group_setegid.c b/sched/group/group_setegid.c index ac5dee2d7f9..733f11f84dc 100644 --- a/sched/group/group_setegid.c +++ b/sched/group/group_setegid.c @@ -78,9 +78,20 @@ int setegid(gid_t gid) rtcb = this_task(); rgroup = rtcb->group; - /* Set the task group's group identity. */ - DEBUGASSERT(rgroup != NULL); - rgroup->tg_egid = gid; + + if (rgroup->tg_egid == 0 || + gid == rgroup->tg_gid || gid == rgroup->tg_sgid) + { + /* Root may set any value; non-root may only set to real or saved. */ + + rgroup->tg_egid = gid; + } + else + { + set_errno(EPERM); + return ERROR; + } + return OK; } diff --git a/sched/group/group_seteuid.c b/sched/group/group_seteuid.c index b306f9a58b2..758a6355365 100644 --- a/sched/group/group_seteuid.c +++ b/sched/group/group_seteuid.c @@ -80,9 +80,20 @@ int seteuid(uid_t uid) rtcb = this_task(); rgroup = rtcb->group; - /* Set the task group's group identity. */ - DEBUGASSERT(rgroup != NULL); - rgroup->tg_euid = uid; + + if (rgroup->tg_euid == 0 || + uid == rgroup->tg_uid || uid == rgroup->tg_suid) + { + /* Root may set any value; non-root may only set to real or saved. */ + + rgroup->tg_euid = uid; + } + else + { + set_errno(EPERM); + return ERROR; + } + return OK; } diff --git a/sched/group/group_setgid.c b/sched/group/group_setgid.c index 2fc0b423148..72131e5ee5f 100644 --- a/sched/group/group_setgid.c +++ b/sched/group/group_setgid.c @@ -79,9 +79,27 @@ int setgid(gid_t gid) rtcb = this_task(); rgroup = rtcb->group; - /* Set the task group's group identity. */ - DEBUGASSERT(rgroup != NULL); - rgroup->tg_gid = gid; + + if (rgroup->tg_egid == 0) + { + /* Root: set real, effective, and saved set-group-ID. */ + + rgroup->tg_gid = gid; + rgroup->tg_egid = gid; + rgroup->tg_sgid = gid; + } + else if (gid == rgroup->tg_gid || gid == rgroup->tg_sgid) + { + /* Non-root: may only set effective GID to real or saved value. */ + + rgroup->tg_egid = gid; + } + else + { + set_errno(EPERM); + return ERROR; + } + return OK; } diff --git a/sched/group/group_setuid.c b/sched/group/group_setuid.c index 46cf4f8b16f..16073ed5313 100644 --- a/sched/group/group_setuid.c +++ b/sched/group/group_setuid.c @@ -80,9 +80,27 @@ int setuid(uid_t uid) rtcb = this_task(); rgroup = rtcb->group; - /* Set the task group's group identity. */ - DEBUGASSERT(rgroup != NULL); - rgroup->tg_uid = uid; + + if (rgroup->tg_euid == 0) + { + /* Root: set real, effective, and saved set-user-ID. */ + + rgroup->tg_uid = uid; + rgroup->tg_euid = uid; + rgroup->tg_suid = uid; + } + else if (uid == rgroup->tg_uid || uid == rgroup->tg_suid) + { + /* Non-root: may only set effective UID to real or saved value. */ + + rgroup->tg_euid = uid; + } + else + { + set_errno(EPERM); + return ERROR; + } + return OK; } From d487c46a292d96bee1bb59b229c84714865bd40c Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Thu, 11 Jun 2026 19:48:15 +0000 Subject: [PATCH 047/268] Documentation/sched: Add POSIX user identity transition docs Adds comprehensive documentation for the POSIX three-tier user identity model (real, effective, saved-set IDs) enabled by CONFIG_SCHED_USER_IDENTITY. * Updates sched/Kconfig with detailed help text explaining the config. * Adds user_identity.rst to formally document credential inheritance and the privilege transition rules for setuid(), seteuid(), setgid(), and setegid(). * Updates tasks_vs_threads.rst to list credentials as a shared task group resource. Signed-off-by: Abhishek Mishra --- Documentation/implementation/index.rst | 1 + .../implementation/tasks_vs_threads.rst | 2 + .../implementation/user_identity.rst | 71 +++++++++++++++++++ include/nuttx/sched.h | 8 +-- sched/Kconfig | 19 +++-- 5 files changed, 91 insertions(+), 10 deletions(-) create mode 100644 Documentation/implementation/user_identity.rst diff --git a/Documentation/implementation/index.rst b/Documentation/implementation/index.rst index b05cffad841..bcb87e9eff3 100644 --- a/Documentation/implementation/index.rst +++ b/Documentation/implementation/index.rst @@ -38,4 +38,5 @@ Implementation Details tasks_vs_threads.rst tickless_os.rst tls.rst + user_identity.rst usb.rst diff --git a/Documentation/implementation/tasks_vs_threads.rst b/Documentation/implementation/tasks_vs_threads.rst index 4bd14efb6f4..71bd38f989c 100644 --- a/Documentation/implementation/tasks_vs_threads.rst +++ b/Documentation/implementation/tasks_vs_threads.rst @@ -69,6 +69,8 @@ reside within the task group structure struct ``task_group_s``: * Opened message queues. * ``pthread`` keys. * Support data for ``atexit()``, ``on_exit()``, and/or ``waitpid()``. +* User and group identity when ``CONFIG_SCHED_USER_IDENTITY`` is enabled + (see :ref:`user-identity`). The exception is the PIC address space used with NXFLAT. It currently has its own data structure (struct ``dspace_s``, diff --git a/Documentation/implementation/user_identity.rst b/Documentation/implementation/user_identity.rst new file mode 100644 index 00000000000..ab7ecdaa6ca --- /dev/null +++ b/Documentation/implementation/user_identity.rst @@ -0,0 +1,71 @@ +.. _user-identity: + +======================= +User and Group Identity +======================= + +When ``CONFIG_SCHED_USER_IDENTITY`` is enabled, each task group maintains POSIX +process credentials. All threads within a task group share the same credentials +(see :ref:`tasks-vs-threads`). + +Credentials +=========== + +The full POSIX three-field credential model is stored in ``struct task_group_s`` +(``include/nuttx/sched.h``): + +* ``tg_uid`` / ``tg_gid`` — real user and group IDs. +* ``tg_euid`` / ``tg_egid`` — effective IDs used for permission checks. +* ``tg_suid`` / ``tg_sgid`` — saved set-IDs that allow a non-root process to + restore a previously held effective ID. + +All six fields are zero-initialized at task creation, so the initial task runs +as root (UID/GID 0) unless explicitly changed. + +Inheritance +=========== + +When a new task is created, ``group_inherit_identity()`` in +``sched/group/group_create.c`` copies all six credential fields from the parent +task group to the child task group. + +Privilege Transitions +===================== + +``setuid()`` and ``setgid()`` +----------------------------- + +When the effective ID is zero (root): + +* ``setuid(uid)`` sets ``tg_uid``, ``tg_euid``, and ``tg_suid`` to ``uid``. +* ``setgid(gid)`` sets ``tg_gid``, ``tg_egid``, and ``tg_sgid`` to ``gid``. + +When the effective ID is non-zero: + +* The caller may only set the effective ID to the current real or saved value. +* Any other value causes the function to return ``-1`` with ``errno`` set to + ``EPERM``. + +``seteuid()`` and ``setegid()`` +------------------------------- + +When the effective ID is zero, any value may be assigned as the new effective +ID. + +When the effective ID is non-zero, the requested value must equal the real or +the saved ID. Otherwise the function returns ``-1`` with ``errno`` set to +``EPERM``. + +This implements the standard POSIX pattern of temporarily dropping privileges +with ``seteuid()`` or ``setegid()`` and later restoring them to the saved value. + +Configuration +============= + +``CONFIG_SCHED_USER_IDENTITY`` + Enables per-task-group credential tracking. Without this option, stub + root-only versions of all credential interfaces are provided. + +``CONFIG_FS_PERMISSION`` + Enables filesystem ownership and permission enforcement. Requires + ``CONFIG_SCHED_USER_IDENTITY``. diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index ca3781995bd..9f40db43828 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -455,13 +455,13 @@ struct task_group_s pid_t tg_ppid; /* This is the ID of the parent thread */ uint8_t tg_flags; /* See GROUP_FLAG_* definitions */ - /* User identity **********************************************************/ + /* User identity (POSIX real, effective, and saved-set IDs) ***************/ #ifdef CONFIG_SCHED_USER_IDENTITY - uid_t tg_uid; /* User identity */ - gid_t tg_gid; /* User group identity */ + uid_t tg_uid; /* Real user identity */ + gid_t tg_gid; /* Real group identity */ uid_t tg_euid; /* Effective user identity */ - gid_t tg_egid; /* Effective user group identity */ + gid_t tg_egid; /* Effective group identity */ uid_t tg_suid; /* Saved set-user identity */ gid_t tg_sgid; /* Saved set-group identity */ #endif diff --git a/sched/Kconfig b/sched/Kconfig index 9b4ed4c82c8..3b5808a4417 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -789,12 +789,19 @@ config SCHED_USER_IDENTITY bool "Support per-task User Identity" default n ---help--- - This selection enables functionality of getuid(), setuid(), getgid(), - setgid(). If this option is not selected, then stub, root-only - versions of these interfaces are available. When selected, these - interfaces will associate a UID and/or GID with each task group. - Those can then be managed using the interfaces. Child tasks will - inherit the UID and GID of its parent. + Enable per-task-group POSIX user and group credentials. + + When selected, each task group tracks real, effective, and saved-set + UID/GID values and provides getuid(), getgid(), geteuid(), + getegid(), setuid(), setgid(), seteuid(), and setegid(). + + Child tasks inherit all credential fields from the parent task + group. setuid()/setgid() update real, effective, and saved-set + IDs when called with effective privileges; seteuid()/setegid() + implement the standard POSIX privilege transition rules. + + If this option is not selected, stub root-only versions of these + interfaces are available instead. config SCHED_THREAD_LOCAL bool "Support __thread/thread_local keyword" From 4982f5016e7cb56a1456945a70f7f7844c5b7e1a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 048/268] !arch/stm32f7: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32F7 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32f7/chip.h | 142 +++++++++--------- arch/arm/src/stm32f7/hardware/stm32_qspi.h | 4 +- arch/arm/src/stm32f7/hardware/stm32_sai.h | 98 ++++++------ .../src/stm32f7/hardware/stm32f72xx73xx_adc.h | 6 +- .../stm32f7/hardware/stm32f72xx73xx_gpio.h | 22 +-- .../src/stm32f7/hardware/stm32f72xx73xx_spi.h | 12 +- .../src/stm32f7/hardware/stm32f72xx73xx_tim.h | 28 ++-- .../stm32f7/hardware/stm32f72xx73xx_uart.h | 16 +- .../stm32f7/hardware/stm32f74xx75xx_gpio.h | 22 +-- .../src/stm32f7/hardware/stm32f74xx75xx_tim.h | 28 ++-- .../src/stm32f7/hardware/stm32f74xx77xx_adc.h | 6 +- .../src/stm32f7/hardware/stm32f74xx77xx_i2c.h | 8 +- .../src/stm32f7/hardware/stm32f74xx77xx_spi.h | 12 +- .../stm32f7/hardware/stm32f74xx77xx_uart.h | 16 +- .../stm32f7/hardware/stm32f76xx77xx_gpio.h | 22 +-- .../src/stm32f7/hardware/stm32f76xx77xx_tim.h | 28 ++-- arch/arm/src/stm32f7/stm32_allocateheap.c | 4 +- arch/arm/src/stm32f7/stm32_bbsram.c | 6 +- arch/arm/src/stm32f7/stm32_bbsram.h | 8 +- arch/arm/src/stm32f7/stm32_can.h | 2 +- arch/arm/src/stm32f7/stm32_can_sock.c | 2 +- arch/arm/src/stm32f7/stm32_config.h | 30 ++-- arch/arm/src/stm32f7/stm32_dma.c | 10 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 28 ++-- arch/arm/src/stm32f7/stm32_ethernet.c | 26 ++-- arch/arm/src/stm32f7/stm32_ethernet.h | 6 +- arch/arm/src/stm32f7/stm32_foc.c | 24 +-- arch/arm/src/stm32f7/stm32_gpio.c | 30 ++-- arch/arm/src/stm32f7/stm32_gpio.h | 2 +- arch/arm/src/stm32f7/stm32_i2s.c | 18 +-- arch/arm/src/stm32f7/stm32_sai.c | 90 +++++------ arch/arm/src/stm32f7/stm32_serial.c | 6 +- arch/arm/src/stm32f7/stm32_uart.h | 16 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 22 +-- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 22 +-- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 22 +-- boards/arm/stm32f7/common/src/stm32_spitest.c | 6 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_adc.c | 6 +- .../stm32f7/nucleo-f722ze/src/stm32_bbsram.c | 6 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_adc.c | 6 +- .../stm32f7/nucleo-f746zg/src/stm32_bbsram.c | 6 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_adc.c | 6 +- .../stm32f7/nucleo-f767zi/src/stm32_bbsram.c | 6 +- .../stm32f7/stm32f746g-disco/include/board.h | 4 +- .../stm32f746g-disco/src/stm32_extmem.c | 2 +- .../stm32f769i-disco/src/stm32_extmem.c | 2 +- .../stm32f777zit6-meadow/include/board.h | 4 +- .../stm32f777zit6-meadow/src/stm32_extmem.c | 2 +- 48 files changed, 450 insertions(+), 450 deletions(-) diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 5b2eb34fc1f..99047dd9757 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -265,43 +265,43 @@ /* Size SRAM */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ -# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */ # else -# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif #else # error STM32 F7 chip Family not identified @@ -310,33 +310,33 @@ /* Common to all Advanced (vs Foundation) Family members */ #if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) -# define STM32F7_NSPDIFRX 0 /* Not supported */ -# define STM32F7_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32F7_NI2C 3 /* I2C1-3 */ +# define STM32_NSPDIFRX 0 /* Not supported */ +# define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NI2C 3 /* I2C1-3 */ #else -# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ -# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ -# define STM32F7_NI2C 4 /* I2C1-4 */ +# define STM32_NSPDIFRX 4 /* 4 SPDIFRX inputs */ +# define STM32_NGPIO 11 /* 11 GPIO ports, GPIOA-K */ +# define STM32_NI2C 4 /* I2C1-4 */ #endif /* Common to all Family members */ -# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */ -# define STM32F7_NUSART 4 /* USART1-3 and 6 */ -# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ -# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ -# define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NDMA 2 /* DMA1-2 */ -# define STM32F7_NADC 3 /* 12-bit ADC1-3, number of channels vary */ -# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32F7_NCRC 1 /* CRC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NUART 4 /* UART 4-5 and 7-8 */ +# define STM32_NUSART 4 /* USART1-3 and 6 */ +# define STM32_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBOTGHS 1 /* USB OTG HS */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NADC 3 /* 12-bit ADC1-3, number of channels vary */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ /* TBD FPU Configuration */ @@ -351,82 +351,82 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32F7_HAVE_FMC) -# define STM32F7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32F7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif #if defined(CONFIG_STM32F7_HAVE_ETHRNET) -# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32F7_HAVE_RNG) -# define STM32F7_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ #else -# define STM32F7_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif #if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) -# define STM32F7_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ +# define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI5) -# define STM32F7_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ +# define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ #elif defined(CONFIG_STM32F7_HAVE_SPI4) -# define STM32F7_NSPI 4 /* SPI1-4 V series */ +# define STM32_NSPI 4 /* SPI1-4 V series */ #else -# define STM32F7_NSPI 3 /* SPI1-3 R series */ +# define STM32_NSPI 3 /* SPI1-3 R series */ #endif #if defined(CONFIG_STM32F7_HAVE_SDMMC2) -# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */ +# define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else -# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */ +# define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif #if defined(CONFIG_STM32F7_HAVE_CAN3) -# define STM32F7_NCAN 3 /* CAN1-3 */ +# define STM32_NCAN 3 /* CAN1-3 */ #elif defined(CONFIG_STM32F7_HAVE_CAN2) -# define STM32F7_NCAN 2 /* CAN1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32F7_NCAN 1 /* CAN1 only */ +# define STM32_NCAN 1 /* CAN1 only */ #endif #if defined(CONFIG_STM32F7_HAVE_DCMI) -# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else -# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */ +# define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif #if defined(CONFIG_STM32F7_HAVE_DSIHOST) -# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */ +# define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else -# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */ +# define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif #if defined (CONFIG_STM32F7_HAVE_LTDC) -# define STM32F7_NLCDTFT 1 /* One LCD-TFT */ +# define STM32_NLCDTFT 1 /* One LCD-TFT */ #else -# define STM32F7_NLCDTFT 0 /* No LCD-TFT */ +# define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif #if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ -# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else -# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ +# define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif #if defined(CONFIG_STM32F7_HAVE_JPEG) -#define STM32F7_NJPEG 1 /* One JPEG Converter */ +#define STM32_NJPEG 1 /* One JPEG Converter */ #else -#define STM32F7_NJPEG 0 /* No JPEG Converter */ +#define STM32_NJPEG 0 /* No JPEG Converter */ #endif #if defined(CONFIG_STM32F7_HAVE_CRYP) -#define STM32F7_NCRYP 1 /* One CRYP engine */ +#define STM32_NCRYP 1 /* One CRYP engine */ #else -#define STM32F7_NCRYP 0 /* No CRYP engine */ +#define STM32_NCRYP 0 /* No CRYP engine */ #endif #if defined(CONFIG_STM32F7_HAVE_HASH) -#define STM32F7_NHASH 1 /* One HASH engine */ +#define STM32_NHASH 1 /* One HASH engine */ #else -#define STM32F7_NHASH 0 /* No HASH engine */ +#define STM32_NHASH 0 /* No HASH engine */ #endif #if defined(CONFIG_STM32F7_HAVE_DFSDM) -#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */ +#define STM32_NDFSDM 4 /* One set of 4 Digital filters */ #else -#define STM32F7_NDFSDM 0 /* No Digital filters */ +#define STM32_NDFSDM 0 /* No Digital filters */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_qspi.h b/arch/arm/src/stm32f7/hardware/stm32_qspi.h index 31cf04e8534..b857ca463b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32F7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32F7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32_sai.h b/arch/arm/src/stm32f7/hardware/stm32_sai.h index c71d7adc87f..b9378498902 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sai.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32F7_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32F7_SAI_A_OFFSET 0x0004 -#define STM32F7_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32F7_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32F7_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32F7_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32F7_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32F7_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32F7_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32F7_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32F7_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32F7_SAI1_GCR (STM32_SAI1_BASE+STM32F7_SAI_GCR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI1_BASE+STM32_SAI_GCR_OFFSET) -#define STM32F7_SAI1_A_BASE (STM32_SAI1_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI1_B_BASE (STM32_SAI1_BASE+STM32F7_SAI_B_OFFSET) +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) -#define STM32F7_SAI1_ACR1 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_ACR2 (STM32F7_SAI1_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_AFRCR (STM32F7_SAI1_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_ASLOTR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_AIM (STM32F7_SAI1_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_ASR (STM32F7_SAI1_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_ACLRFR (STM32F7_SAI1_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_ADR (STM32F7_SAI1_A_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_DR_OFFSET) -#define STM32F7_SAI1_BCR1 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI1_BCR2 (STM32F7_SAI1_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI1_BFRCR (STM32F7_SAI1_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI1_BSLOTR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI1_BIM (STM32F7_SAI1_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI1_BSR (STM32F7_SAI1_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI1_BCLRFR (STM32F7_SAI1_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI1_BDR (STM32F7_SAI1_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_DR_OFFSET) -#define STM32F7_SAI2_GCR (STM32_SAI2_BASE+STM32F7_SAI_GCR_OFFSET) +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) -#define STM32F7_SAI2_A_BASE (STM32_SAI2_BASE+STM32F7_SAI_A_OFFSET) -#define STM32F7_SAI2_B_BASE (STM32_SAI2_BASE+STM32F7_SAI_B_OFFSET) +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) -#define STM32F7_SAI2_ACR1 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_ACR2 (STM32F7_SAI2_A_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_AFRCR (STM32F7_SAI2_A_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_ASLOTR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_AIM (STM32F7_SAI2_A_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_ASR (STM32F7_SAI2_A_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_ACLRFR (STM32F7_SAI2_A_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_ADR (STM32F7_SAI2_A_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_DR_OFFSET) -#define STM32F7_SAI2_BCR1 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR1_OFFSET) -#define STM32F7_SAI2_BCR2 (STM32F7_SAI2_B_BASE+STM32F7_SAI_CR2_OFFSET) -#define STM32F7_SAI2_BFRCR (STM32F7_SAI2_B_BASE+STM32F7_SAI_FRCR_OFFSET) -#define STM32F7_SAI2_BSLOTR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SLOTR_OFFSET) -#define STM32F7_SAI2_BIM (STM32F7_SAI2_B_BASE+STM32F7_SAI_IM_OFFSET) -#define STM32F7_SAI2_BSR (STM32F7_SAI2_B_BASE+STM32F7_SAI_SR_OFFSET) -#define STM32F7_SAI2_BCLRFR (STM32F7_SAI2_B_BASE+STM32F7_SAI_CLRFR_OFFSET) -#define STM32F7_SAI2_BDR (STM32F7_SAI2_B_BASE+STM32F7_SAI_DR_OFFSET) +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_CR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_CR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_FRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_SLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_IM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_SR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_CLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h index e02cfef5ecf..0c529af4b75 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index 07752be9bf5..bdb8128244c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h index cbcba08dbf4..00fe52c6f7c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_spi.h @@ -54,7 +54,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -64,7 +64,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -76,7 +76,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -88,7 +88,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -100,7 +100,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -112,7 +112,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h index d9d897fe1e3..5a3e8dbb1d4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 6473f22947b..5c73674d3d0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -66,7 +66,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -81,7 +81,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -96,7 +96,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -111,7 +111,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -126,7 +126,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -141,7 +141,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -156,7 +156,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index 7d40fb94d08..eee436dc44f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h index 44bea326903..f3144d3568d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_tim.h @@ -97,7 +97,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -123,7 +123,7 @@ # define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -153,7 +153,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -175,7 +175,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -196,7 +196,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -217,7 +217,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -244,7 +244,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -259,7 +259,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -272,7 +272,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -286,7 +286,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -301,7 +301,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -314,7 +314,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -329,7 +329,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -340,7 +340,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h index 4d6e8e39878..8f2ede7053f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_adc.h @@ -64,7 +64,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NADC > 0 +#if STM32_NADC > 0 # define STM32_ADC1_SR (STM32_ADC1_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC1_CR1 (STM32_ADC1_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC1_CR2 (STM32_ADC1_BASE+STM32_ADC_CR2_OFFSET) @@ -87,7 +87,7 @@ # define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 1 +#if STM32_NADC > 1 # define STM32_ADC2_SR (STM32_ADC2_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC2_CR1 (STM32_ADC2_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC2_CR2 (STM32_ADC2_BASE+STM32_ADC_CR2_OFFSET) @@ -110,7 +110,7 @@ # define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) #endif -#if STM32F7_NADC > 2 +#if STM32_NADC > 2 # define STM32_ADC3_SR (STM32_ADC3_BASE+STM32_ADC_SR_OFFSET) # define STM32_ADC3_CR1 (STM32_ADC3_BASE+STM32_ADC_CR1_OFFSET) # define STM32_ADC3_CR2 (STM32_ADC3_BASE+STM32_ADC_CR2_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h index 0194d61ee74..a6417e0d4a8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32F7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index dd0d8963188..946408d1916 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) @@ -68,7 +68,7 @@ # define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32F7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) @@ -80,7 +80,7 @@ # define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) @@ -92,7 +92,7 @@ # define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET) @@ -104,7 +104,7 @@ # define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET) @@ -116,7 +116,7 @@ # define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET) #endif -#if STM32F7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index 6dfbba5177a..c996cd30768 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART6_TDR (STM32_USART6_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32F7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index dc769114062..370b090abd1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -51,7 +51,7 @@ /* Register Addresses *******************************************************/ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -64,7 +64,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -77,7 +77,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -90,7 +90,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -103,7 +103,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -116,7 +116,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -129,7 +129,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -142,7 +142,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -155,7 +155,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -168,7 +168,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h index fc2fa7bec81..b2586544aa4 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_tim.h @@ -99,7 +99,7 @@ /* Advanced Timers - TIM1 and TIM8 */ -#if STM32F7_NATIM > 0 +#if STM32_NATIM > 0 # define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) @@ -127,7 +127,7 @@ # define STM32_TIM1_AF2 (STM32_TIM1_BASE+STM32_ATIM_AF2_OFFSET) #endif -#if STM32F7_NATIM > 1 +#if STM32_NATIM > 1 # define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) # define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) # define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) @@ -159,7 +159,7 @@ * All timers are 16-bit except for TIM2 and 5 are 32-bit */ -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 0 +#if (STM32_NGTIM16+STM32_NGTIM32) > 0 # define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) @@ -181,7 +181,7 @@ # define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 1 +#if (STM32_NGTIM16+STM32_NGTIM32) > 1 # define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) @@ -202,7 +202,7 @@ # define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 2 +#if (STM32_NGTIM16+STM32_NGTIM32) > 2 # define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) @@ -223,7 +223,7 @@ # define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) #endif -#if (STM32F7_NGTIM16+STM32F7_NGTIM32) > 3 +#if (STM32_NGTIM16+STM32_NGTIM32) > 3 # define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) @@ -250,7 +250,7 @@ * (2) TIM9 and TIM12 differ from the others. */ -#if STM32F7_NGTIMNDMA > 0 +#if STM32_NGTIMNDMA > 0 # define STM32_TIM9_CR1 (STM32_TIM9_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM9_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM9_DIER (STM32_TIM9_BASE+STM32_GTIM_DIER_OFFSET) @@ -265,7 +265,7 @@ # define STM32_TIM9_CCR2 (STM32_TIM9_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 1 +#if STM32_NGTIMNDMA > 1 # define STM32_TIM10_CR1 (STM32_TIM10_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM10_DIER (STM32_TIM10_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM10_SR (STM32_TIM10_BASE+STM32_GTIM_SR_OFFSET) @@ -278,7 +278,7 @@ # define STM32_TIM10_CCR1 (STM32_TIM10_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 2 +#if STM32_NGTIMNDMA > 2 # define STM32_TIM11_CR1 (STM32_TIM11_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM11_DIER (STM32_TIM11_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM11_SR (STM32_TIM11_BASE+STM32_GTIM_SR_OFFSET) @@ -292,7 +292,7 @@ # define STM32_TIM11_OR (STM32_TIM11_BASE+STM32_GTIM_OR_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 3 +#if STM32_NGTIMNDMA > 3 # define STM32_TIM12_CR1 (STM32_TIM12_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM12_CR2 (STM32_TIM9_BASE+STM32_GTIM_CR2_OFFSET) # define STM32_TIM12_DIER (STM32_TIM12_BASE+STM32_GTIM_DIER_OFFSET) @@ -307,7 +307,7 @@ # define STM32_TIM12_CCR2 (STM32_TIM12_BASE+STM32_GTIM_CCR2_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 4 +#if STM32_NGTIMNDMA > 4 # define STM32_TIM13_CR1 (STM32_TIM13_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM13_DIER (STM32_TIM13_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM13_SR (STM32_TIM13_BASE+STM32_GTIM_SR_OFFSET) @@ -320,7 +320,7 @@ # define STM32_TIM13_CCR1 (STM32_TIM13_BASE+STM32_GTIM_CCR1_OFFSET) #endif -#if STM32F7_NGTIMNDMA > 5 +#if STM32_NGTIMNDMA > 5 # define STM32_TIM14_CR1 (STM32_TIM14_BASE+STM32_GTIM_CR1_OFFSET) # define STM32_TIM14_DIER (STM32_TIM14_BASE+STM32_GTIM_DIER_OFFSET) # define STM32_TIM14_SR (STM32_TIM14_BASE+STM32_GTIM_SR_OFFSET) @@ -335,7 +335,7 @@ /* Basic Timers - TIM6 and TIM7 */ -#if STM32F7_NBTIM > 0 +#if STM32_NBTIM > 0 # define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) @@ -346,7 +346,7 @@ # define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) #endif -#if STM32F7_NBTIM > 1 +#if STM32_NBTIM > 1 # define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) # define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) # define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 0991bcece13..47ac51b14ed 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -79,10 +79,10 @@ /* Set the start and end of SRAM1 and SRAM2 */ #define SRAM1_START STM32_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32F7_SRAM1_SIZE) +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* The STM32 F7 has DTCM memory */ diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index 36d92cc7de3..bdf2060127c 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -130,7 +130,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32F7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -544,7 +544,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -627,7 +627,7 @@ static int stm32_bbsram_unlink(struct inode *inode) static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) { int i; - int avail = STM32F7_BBSRAM_SIZE; + int avail = STM32_BBSRAM_SIZE; int alloc; int size; int ret = -EFBIG; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 4d080578c4e..0eff55b26e1 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) -# define STM32F7_BBSRAM_SIZE 4096 +# define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif @@ -55,11 +55,11 @@ # define CONFIG_STM32F7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -129,7 +129,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: - * fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index 05dbe1e10c6..b9377f43389 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -151,4 +151,4 @@ int stm32_cansockinitialize(int port); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32F7_CAN_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index c421e4c0e5e..e4e8f68da1d 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -729,7 +729,7 @@ static void stm32can_errint(struct stm32_can_s *priv, bool enable) } else { - regval &= ~STM32F7_CAN_ERRINT; + regval &= ~STM32_CAN_ERRINT; } stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index 9bec9e58704..c5a0cee3b6d 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -46,19 +46,19 @@ # undef CONFIG_STM32F7_GPIOE_IRQ #endif -#if STM32F7_NPORTS < 1 +#if STM32_NPORTS < 1 # undef CONFIG_STM32F7_GPIOA_IRQ #endif -#if STM32F7_NPORTS < 2 +#if STM32_NPORTS < 2 # undef CONFIG_STM32F7_GPIOB_IRQ #endif -#if STM32F7_NPORTS < 3 +#if STM32_NPORTS < 3 # undef CONFIG_STM32F7_GPIOC_IRQ #endif -#if STM32F7_NPORTS < 4 +#if STM32_NPORTS < 4 # undef CONFIG_STM32F7_GPIOD_IRQ #endif -#if STM32F7_NPORTS < 5 +#if STM32_NPORTS < 5 # undef CONFIG_STM32F7_GPIOE_IRQ #endif @@ -66,25 +66,25 @@ /* Don't enable UARTs not supported by the chip. */ -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART0 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 2 +#elif STM32_NUART < 2 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 3 +#elif STM32_NUART < 3 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 4 +#elif STM32_NUART < 4 # undef CONFIG_STM32F7_UART3 # undef CONFIG_STM32F7_UART4 -#elif STM32F7_NUART < 5 +#elif STM32_NUART < 5 # undef CONFIG_STM32F7_UART4 #endif @@ -115,14 +115,14 @@ /* Don't enable USARTs not supported by the chip. */ -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART0 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 2 +#elif STM32_NUSART < 2 # undef CONFIG_STM32F7_USART1 # undef CONFIG_STM32F7_USART2 -#elif STM32F7_NUSART < 3 +#elif STM32_NUSART < 3 # undef CONFIG_STM32F7_USART2 #endif @@ -158,8 +158,8 @@ /* Is there a serial console? There should be no more than one defined. * It could be on any: - * UARTn, n=1..STM32F7_NUART, or - * USARTn, n=1..STM32F7_NUSART + * UARTn, n=1..STM32_NUART, or + * USARTn, n=1..STM32_NUSART */ #undef HAVE_SERIAL_CONSOLE diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 72e2d1f52d3..4b1df56c919 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -55,7 +55,7 @@ ****************************************************************************/ #define DMA1_NSTREAMS 8 -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NSTREAMS 8 # define DMA_NSTREAMS (DMA1_NSTREAMS+DMA2_NSTREAMS) #else @@ -148,7 +148,7 @@ static struct stm32_dma_s g_dma[DMA_NSTREAMS] = .sem = SEM_INITIALIZER(1), .base = STM32_DMA1_BASE + STM32_DMA_OFFSET(7), }, -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 { .stream = 0, .irq = STM32_IRQ_DMA2S0, @@ -268,13 +268,13 @@ static inline struct stm32_dma_s *stm32_dmastream(unsigned int stream, { int index; - DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32F7_NDMA); + DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA); /* Convert the controller + stream based on the fact that there are * 8 streams per controller. */ -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 index = controller << 3 | stream; #else index = stream; @@ -376,7 +376,7 @@ static int stm32_dmainterrupt(int irq, void *context, void *arg) controller = DMA1; } else -#if STM32F7_NDMA > 1 +#if STM32_NDMA > 1 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index bf70e68ec45..45820a0adca 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -54,31 +54,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32F7_NGPIO] = +static const char g_portchar[STM32_NGPIO] = { -#if STM32F7_NGPIO > 11 +#if STM32_NGPIO > 11 # error "Additional support required for this number of GPIOs" -#elif STM32F7_NGPIO > 10 +#elif STM32_NGPIO > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32F7_NGPIO > 9 +#elif STM32_NGPIO > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32F7_NGPIO > 8 +#elif STM32_NGPIO > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32F7_NGPIO > 7 +#elif STM32_NGPIO > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32F7_NGPIO > 6 +#elif STM32_NGPIO > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32F7_NGPIO > 5 +#elif STM32_NGPIO > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32F7_NGPIO > 4 +#elif STM32_NGPIO > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32F7_NGPIO > 3 +#elif STM32_NGPIO > 3 'A', 'B', 'C', 'D' -#elif STM32F7_NGPIO > 2 +#elif STM32_NGPIO > 2 'A', 'B', 'C' -#elif STM32F7_NGPIO > 1 +#elif STM32_NGPIO > 1 'A', 'B' -#elif STM32F7_NGPIO > 0 +#elif STM32_NGPIO > 0 'A' #else # error "Bad number of GPIOs" @@ -112,7 +112,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32F7_NGPIO); + DEBUGASSERT(port < STM32_NGPIO); gpioinfo("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 22c185ac8f8..668418a15ca 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -65,12 +65,12 @@ #include -/* STM32F7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32F7_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -78,7 +78,7 @@ /* Configuration ************************************************************/ -#if STM32F7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -243,14 +243,14 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32F7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -659,7 +659,7 @@ static uint8_t g_txbuffer[TXBUFFER_ALLOC] /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32F7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3899,7 +3899,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 || defined(CONFIG_NETDEV_LATEINIT) static inline #endif int stm32_ethinitialize(int intf) @@ -3912,7 +3912,7 @@ int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32F7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -3973,7 +3973,7 @@ int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32F7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -3988,11 +3988,11 @@ int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32F7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32F7_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index 26d0e98ab89..b33dd2a646d 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32F7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32F7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32F7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index cddddee17d6..aeaea51aa19 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -376,9 +376,9 @@ /* ADC1 + ADC2 + ADC3 interrupt */ -#define STM32F7_IRQ_ADC1_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC2_FOC STM32_IRQ_ADC -#define STM32F7_IRQ_ADC3_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC1_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC2_FOC STM32_IRQ_ADC +#define STM32_IRQ_ADC3_FOC STM32_IRQ_ADC /* ADC common ***************************************************************/ @@ -392,38 +392,38 @@ #ifdef CONFIG_STM32F7_FOC_FOC0 # ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 -# define FOC0_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif #ifdef CONFIG_STM32F7_FOC_FOC1 # ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC1_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC2_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC3_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif # ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 -# define FOC1_ADC_IRQ STM32F7_IRQ_ADC4_FOC +# define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif #endif @@ -772,7 +772,7 @@ void stm32_foc_sync_all(void) /* Store EGR register address */ - egr_reg[i] = foc_dev->pwm_base + STM32F7_GTIM_EGR_OFFSET; + egr_reg[i] = foc_dev->pwm_base + STM32_GTIM_EGR_OFFSET; } /* Write all registers at once */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 0033faf47da..27455106e85 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -60,39 +60,39 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32F7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 STM32_GPIOF_BASE, #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 STM32_GPIOG_BASE, #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -134,7 +134,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32F7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -409,7 +409,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -449,7 +449,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32F7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32f7/stm32_gpio.h b/arch/arm/src/stm32f7/stm32_gpio.h index 00fee28b71a..97fcbc8dfaf 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.h +++ b/arch/arm/src/stm32f7/stm32_gpio.h @@ -240,7 +240,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index f6f6d0c0272..53b8e44da21 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -232,9 +232,9 @@ #endif #if CONFIG_STM32F7_I2S1_DATALEN == 8 -# define STM32F7_I2S1_DATAMASK 0 +# define STM32_I2S1_DATAMASK 0 #elif CONFIG_STM32F7_I2S1_DATALEN == 16 -# define STM32F7_I2S1_DATAMASK 1 +# define STM32_I2S1_DATAMASK 1 #elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S1_DATALEN #else @@ -242,9 +242,9 @@ #endif #if CONFIG_STM32F7_I2S2_DATALEN == 8 -# define STM32F7_I2S2_DATAMASK 0 +# define STM32_I2S2_DATAMASK 0 #elif CONFIG_STM32F7_I2S2_DATALEN == 16 -# define STM32F7_I2S2_DATAMASK 1 +# define STM32_I2S2_DATAMASK 1 #elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S2_DATALEN #else @@ -252,9 +252,9 @@ #endif #if CONFIG_STM32F7_I2S3_DATALEN == 8 -# define STM32F7_I2S3_DATAMASK 0 +# define STM32_I2S3_DATAMASK 0 #elif CONFIG_STM32F7_I2S3_DATALEN == 16 -# define STM32F7_I2S3_DATAMASK 1 +# define STM32_I2S3_DATAMASK 1 #elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 # error Invalid value for CONFIG_STM32F7_I2S3_DATALEN #else @@ -2486,7 +2486,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S1 */ @@ -2551,7 +2551,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S2_DATAMASK; + priv->align = STM32_I2S2_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S2 */ @@ -2616,7 +2616,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; #ifdef CONFIG_DEBUG - priv->align = STM32F7_I2S3_DATAMASK; + priv->align = STM32_I2S3_DATAMASK; #endif } #endif /* CONFIG_STM32F7_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 3883278b6f3..c05e18fc7fe 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -107,14 +107,14 @@ #endif #ifdef CONFIG_STM32F7_SAI1 -#ifndef STM32F7_SAI1_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI1_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif #ifdef CONFIG_STM32F7_SAI2 -#ifndef STM32F7_SAI2_FREQUENCY -# error "Please define STM32F7_SAI1_FREQUENCY in board.h" +#ifndef STM32_SAI2_FREQUENCY +# error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif @@ -278,9 +278,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -299,9 +299,9 @@ static struct stm32f7_sai_s g_sai1a_priv = static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -322,9 +322,9 @@ static struct stm32f7_sai_s g_sai1b_priv = static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -343,9 +343,9 @@ static struct stm32f7_sai_s g_sai2a_priv = static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32F7_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32F7_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else @@ -479,30 +479,30 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #if 0 i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_CR1_OFFSET), - sai_getreg(priv, STM32F7_SAI_CR2_OFFSET), - sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32F7_SAI_IM_OFFSET), - sai_getreg(priv, STM32F7_SAI_SR_OFFSET), - sai_getreg(priv, STM32F7_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); #else /* GCR */ #ifdef CONFIG_STM32F7_SAI1 - uint32_t gcr = getreg32(STM32F7_SAI1_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI1_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI1_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else - uint32_t gcr = getreg32(STM32F7_SAI2_GCR); - i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI2_GCR, gcr); + uint32_t gcr = getreg32(STM32_SAI2_GCR); + i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI2_GCR, gcr); #endif /* CR1 */ - uint32_t cr1 = sai_getreg(priv, STM32F7_SAI_CR1_OFFSET); - i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32F7_SAI_CR1_OFFSET, cr1); + uint32_t cr1 = sai_getreg(priv, STM32_SAI_CR1_OFFSET); + i2sinfo("CR1: *%08" PRIx32 " = %08x\n", STM32_SAI_CR1_OFFSET, cr1); uint32_t mode = (cr1 & SAI_CR1_MODE_MASK) >> SAI_CR1_MODE_SHIFT; const char *mode_string[] = @@ -584,8 +584,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* CR2 */ - uint32_t cr2 = sai_getreg(priv, STM32F7_SAI_CR2_OFFSET); - i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32F7_SAI_CR2_OFFSET, cr2); + uint32_t cr2 = sai_getreg(priv, STM32_SAI_CR2_OFFSET); + i2sinfo("CR2: *%08x = %08" PRIx32 "\n", STM32_SAI_CR2_OFFSET, cr2); uint32_t fth = (cr2 & SAI_CR2_FTH_MASK) >> SAI_CR2_FTH_SHIFT; const char *fth_string[] = { "FIFO empty", @@ -638,8 +638,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* FRCR */ - uint32_t frcr = sai_getreg(priv, STM32F7_SAI_FRCR_OFFSET); - i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_FRCR_OFFSET, frcr); + uint32_t frcr = sai_getreg(priv, STM32_SAI_FRCR_OFFSET); + i2sinfo("FRCR: *%08x = %08" PRIx32 "\n", STM32_SAI_FRCR_OFFSET, frcr); uint32_t frl = (frcr & SAI_FRCR_FRL_MASK) >> SAI_FRCR_FRL_SHIFT; i2sinfo("\t\tFRCR: FRL[7:0] = %d\n", frl); @@ -662,8 +662,8 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) /* SLOTR */ - uint32_t slotr = sai_getreg(priv, STM32F7_SAI_SLOTR_OFFSET); - i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32F7_SAI_SLOTR_OFFSET, slotr); + uint32_t slotr = sai_getreg(priv, STM32_SAI_SLOTR_OFFSET); + i2sinfo("SLOTR: *%08x = %08" PRIx32 "\n", STM32_SAI_SLOTR_OFFSET, slotr); uint32_t fboff = (slotr & SAI_SLOTR_FBOFF_MASK) >> SAI_SLOTR_FBOFF_SHIFT; i2sinfo("\t\tSLOTR: FBOFF[4:0] = %d\n", fboff); @@ -731,7 +731,7 @@ static void sai_mckdivider(struct stm32f7_sai_s *priv) mckdiv += 1; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -878,7 +878,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32_dmasetup(priv->dma, priv->base + STM32F7_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -891,7 +891,7 @@ static int sai_dma_setup(struct stm32f7_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -1169,9 +1169,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -1244,7 +1244,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1344,7 +1344,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1528,28 +1528,28 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_OUTDRIV); - sai_modifyreg(priv, STM32F7_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32F7_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32F7_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); - sai_modifyreg(priv, STM32F7_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); sai_dump_regs(priv, "After initialization"); } diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index dd5a10c0ee0..c04b5eca680 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -64,7 +64,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32F7_NUSART + STM32F7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1790,7 +1790,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3565,7 +3565,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32F7_NUSART + STM32F7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index 447a020e51f..d65dbe36b2f 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32F7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32F7_UART8 #endif -#if STM32F7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32F7_UART7 #endif -#if STM32F7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32F7_UART5 #endif -#if STM32F7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32F7_UART4 #endif -#if STM32F7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32F7_USART6 #endif -#if STM32F7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32F7_USART3 #endif -#if STM32F7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32F7_USART2 #endif -#if STM32F7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART1 #endif diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 625c5917073..2633267d255 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -132,36 +132,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index a0f80c1a031..f2a51b9e306 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -134,36 +134,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index a497d7ccb85..d59a5729de6 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -142,36 +142,36 @@ static inline void rcc_enableahb1(void) /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32F7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB1ENR_GPIOAEN -#if STM32F7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB1ENR_GPIOBEN #endif -#if STM32F7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB1ENR_GPIOCEN #endif -#if STM32F7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB1ENR_GPIODEN #endif -#if STM32F7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB1ENR_GPIOEEN #endif -#if STM32F7_NGPIO > 5 +#if STM32_NGPIO > 5 | RCC_AHB1ENR_GPIOFEN #endif -#if STM32F7_NGPIO > 6 +#if STM32_NGPIO > 6 | RCC_AHB1ENR_GPIOGEN #endif -#if STM32F7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB1ENR_GPIOHEN #endif -#if STM32F7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB1ENR_GPIOIEN #endif -#if STM32F7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB1ENR_GPIOJEN #endif -#if STM32F7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB1ENR_GPIOKEN #endif ); diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index f82b9b8fe64..51bf2d63ca6 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -127,7 +127,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI1 to STM32F7_SPI1_FREQ and mode */ + /* Default SPI1 to STM32_SPI1_FREQ and mode */ SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); @@ -145,7 +145,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI2 to STM32F7_SPI2_FREQ and mode */ + /* Default SPI2 to STM32_SPI2_FREQ and mode */ SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); @@ -163,7 +163,7 @@ int stm32_spidev_bus_test(void) return -ENODEV; } - /* Default SPI3 to STM32F7_SPI3_FREQ and mode */ + /* Default SPI3 to STM32_SPI3_FREQ and mode */ SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 11dab91d01c..96deea3ee98 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index b9a578268f7..04b76397fdf 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 76e270d40d3..7f79bebc84d 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index e575a7f653d..7834ac832df 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index d8c2ca1239b..bf7d56c0c6b 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32F7_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32F7_ADC3 #endif -#if STM32F7_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32F7_ADC2 #endif -#if STM32F7_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32F7_ADC1 #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index d1c7ab99d2d..31431f9d53d 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -76,7 +76,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F7_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index b3904989749..0cd3f2c5624 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -152,8 +152,8 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 774f9204fb6..666181b3eb8 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -61,7 +61,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 7 +#if STM32_NGPIO < 7 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index 26ee7b72fd3..f0c45df93e3 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 8 +#if STM32_NGPIO < 8 # error "Required GPIO ports not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9f5fb71fe13..2b1cfc1a9f9 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -158,8 +158,8 @@ * 25000000 / 25 * 384 / 2 / 8 */ -#define STM32F7_SAI1_FREQUENCY (49142857) -#define STM32F7_SAI2_FREQUENCY (49142857) +#define STM32_SAI1_FREQUENCY (49142857) +#define STM32_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index a73495f2e0c..25d4604116b 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -47,7 +47,7 @@ # warning "FMC is not enabled" #endif -#if STM32F7_NGPIO < 6 +#if STM32_NGPIO < 6 # error "Required GPIO ports not enabled" #endif From 2ec8e5aa43e60bd4f8932c52f0eb053f2b40274f Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 049/268] !arch/stm32h5: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32H5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32h5/chip.h | 82 ++-- arch/arm/src/stm32h5/hardware/stm32_qspi.h | 4 +- .../src/stm32h5/hardware/stm32h5xxx_gpio.h | 18 +- .../arm/src/stm32h5/hardware/stm32h5xxx_i2c.h | 8 +- .../arm/src/stm32h5/hardware/stm32h5xxx_spi.h | 12 +- .../src/stm32h5/hardware/stm32h5xxx_uart.h | 26 +- arch/arm/src/stm32h5/stm32_ethernet.c | 26 +- arch/arm/src/stm32h5/stm32_ethernet.h | 6 +- arch/arm/src/stm32h5/stm32_fdcan.c | 8 +- arch/arm/src/stm32h5/stm32_gpio.c | 24 +- arch/arm/src/stm32h5/stm32_gpio.h | 2 +- arch/arm/src/stm32h5/stm32_icache.c | 4 +- arch/arm/src/stm32h5/stm32_lowputc.c | 426 +++++++++--------- arch/arm/src/stm32h5/stm32_rcc.c | 12 +- arch/arm/src/stm32h5/stm32_serial.c | 10 +- arch/arm/src/stm32h5/stm32_start.c | 4 +- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 148 +++--- arch/arm/src/stm32h5/stm32h563xx_flash.c | 2 +- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 54 +-- .../arm/stm32h5/nucleo-h563zi/include/board.h | 12 +- 20 files changed, 444 insertions(+), 444 deletions(-) diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index 3db5fd6905a..88906a435a0 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -34,65 +34,65 @@ ****************************************************************************/ #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ #elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ #else # error "Unsupported STM32H5 chip" #endif -#define STM32H5_NFSMC (1) /* Have FSMC memory controller */ -#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ -#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ -#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ -#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ -#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */ -#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ -#define STM32H5_NRNG (1) /* Random number generator (RNG) */ +#define STM32_NFSMC (1) /* Have FSMC memory controller */ +#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */ +#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */ +#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */ +#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */ +#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */ +#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ +#define STM32_NRNG (1) /* Random number generator (RNG) */ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */ -# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */ +# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ +# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NUART (2) /* UART 4-5 */ -# define STM32H5_NUSART (4) /* USART 1-3, 6*/ +# define STM32_NUART (2) /* UART 4-5 */ +# define STM32_NUSART (4) /* USART 1-3, 6*/ #endif -#define STM32H5_NLPUART (1) /* LPUART 1 */ -#define STM32H5_QSPI (0) /* No QuadSPI1 */ -#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/ +#define STM32_NLPUART (1) /* LPUART 1 */ +#define STM32_QSPI (0) /* No QuadSPI1 */ +#define STM32_OCTOSPI (1) /* OCTOSPI1*/ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSPI (6) /* SPI1-SPI6 */ -# define STM32H5_NI2C (4) /* I2C1-4 */ +# define STM32_NSPI (6) /* SPI1-SPI6 */ +# define STM32_NI2C (4) /* I2C1-4 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSPI (3) /* SPI1-SPI3 */ -# define STM32H5_NI2C (3) /* I2C1-3 */ +# define STM32_NSPI (3) /* SPI1-SPI3 */ +# define STM32_NI2C (3) /* I2C1-3 */ #endif -#define STM32H5_NSWPMI (0) /* No SWPMI1 */ -#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */ -#define STM32H5_NUSBFS (1) /* No USB FS */ -#define STM32H5_NCAN (2) /* CAN1 */ -#define STM32H5_NSAI (2) /* SAI1-2 */ +#define STM32_NSWPMI (0) /* No SWPMI1 */ +#define STM32_NUSBOTGFS (0) /* USB OTG FS */ +#define STM32_NUSBFS (1) /* No USB FS */ +#define STM32_NCAN (2) /* CAN1 */ +#define STM32_NSAI (2) /* SAI1-2 */ #if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) -# define STM32H5_NSDMMC (2) /* SDMMC interface */ +# define STM32_NSDMMC (2) /* SDMMC interface */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) -# define STM32H5_NSDMMC (1) /* SDMMC interface */ +# define STM32_NSDMMC (1) /* SDMMC interface */ #endif -#define STM32H5_NDMA (2) /* DMA1-2 */ -#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ -#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */ -#define STM32H5_NDAC (1) /* 12-bit DAC1 */ -#define STM32H5_NCRC (1) /* CRC */ -#define STM32H5_NCOMP (0) /* Comparators */ -#define STM32H5_NOPAMP (0) /* Operational Amplifiers */ +#define STM32_NDMA (2) /* DMA1-2 */ +#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */ +#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */ +#define STM32_NDAC (1) /* 12-bit DAC1 */ +#define STM32_NCRC (1) /* CRC */ +#define STM32_NCOMP (0) /* Comparators */ +#define STM32_NOPAMP (0) /* Operational Amplifiers */ /* NVIC priority levels *****************************************************/ @@ -104,9 +104,9 @@ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ #if defined(CONFIG_STM32H5_HAVE_ETHERNET) -# define STM32H5_NETHERNET 1 /* Ethernet MAC */ +# define STM32_NETHERNET 1 /* Ethernet MAC */ #else -# define STM32H5_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ #endif #endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32_qspi.h b/arch/arm/src/stm32h5/hardware/stm32_qspi.h index bda49dd568b..e4ea385ead6 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h5/hardware/stm32_qspi.h @@ -36,8 +36,8 @@ /* General Characteristics **************************************************/ -#define STM32H5_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H5_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h index 915d6b4d4b0..9718063e461 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h @@ -53,7 +53,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -69,7 +69,7 @@ # define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -85,7 +85,7 @@ # define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -101,7 +101,7 @@ # define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -117,7 +117,7 @@ # define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 # define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -149,7 +149,7 @@ # define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 # define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -165,7 +165,7 @@ # define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -181,7 +181,7 @@ # define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32H5_NPORTS > 8 +#if STM32_NPORTS > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h index eb36e1b58c5..5b3adf5963e 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H5_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index 1ef4fae5845..d81ead3491d 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -60,7 +60,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -77,7 +77,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -94,7 +94,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -111,7 +111,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -128,7 +128,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -145,7 +145,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H5_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h index 74d23099c03..3e9cf171976 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h @@ -52,7 +52,7 @@ /* Register Addresses *******************************************************/ -#if STM32H5_NLPUART > 0 +#if STM32_NLPUART > 0 # define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) @@ -67,7 +67,7 @@ # define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -82,7 +82,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -97,7 +97,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -112,7 +112,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 4 +#if STM32_NUSART > 4 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -127,7 +127,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 5 +#if STM32_NUSART > 5 # define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET) @@ -142,7 +142,7 @@ # define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUSART > 6 +#if STM32_NUSART > 6 # define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET) @@ -157,7 +157,7 @@ # define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -172,7 +172,7 @@ # define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -187,7 +187,7 @@ # define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -202,7 +202,7 @@ # define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) @@ -217,7 +217,7 @@ # define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 4 +#if STM32_NUART > 4 # define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET) @@ -232,7 +232,7 @@ # define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H5_NUART > 5 +#if STM32_NUART > 5 # define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 4dbcee14fb6..27a40cc3ec5 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -66,12 +66,12 @@ #include -/* STM32H5_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if * any STM32H5 Ethernet support is enabled in the configuration. */ -#if STM32H5_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ /* Configuration ************************************************************/ -#if STM32H5_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -227,14 +227,14 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H5_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H5_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -653,7 +653,7 @@ aligned_data(ARMV8M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -4181,7 +4181,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H5_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4268,7 +4268,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H5_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4283,11 +4283,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H5_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H5_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.h b/arch/arm/src/stm32h5/stm32_ethernet.h index 66107aa0181..d337248893c 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/stm32_ethernet.h @@ -29,7 +29,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H5_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -65,7 +65,7 @@ extern "C" * ****************************************************************************/ -#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -100,5 +100,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H5_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 622c809eafa..889a3af8149 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -328,10 +328,10 @@ # undef CONFIG_STM32H5_FDCAN_REGDEBUG #endif -#undef STM32H5_FDCAN_LOOPBACK +#undef STM32_FDCAN_LOOPBACK #if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \ defined(CONFIG_STM32H5_FDCAN2_LOOPBACK) -# define STM32H5_FDCAN_LOOPBACK 1 +# define STM32_FDCAN_LOOPBACK 1 #endif /**************************************************************************** @@ -403,7 +403,7 @@ struct stm32_config_s uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */ uint8_t txeventesize; /* TXevent element size (words) */ uint8_t txbufferesize; /* TX buffer element size (words) */ -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK bool loopback; /* True: Loopback mode */ #endif @@ -3282,7 +3282,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) #endif fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval); -#ifdef STM32H5_FDCAN_LOOPBACK +#ifdef STM32_FDCAN_LOOPBACK /* Is loopback mode selected for this peripheral? */ if (config->loopback) diff --git a/arch/arm/src/stm32h5/stm32_gpio.c b/arch/arm/src/stm32h5/stm32_gpio.c index 7664d245c9e..334a5faf38a 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.c +++ b/arch/arm/src/stm32h5/stm32_gpio.c @@ -52,30 +52,30 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 STM32_GPIOA_BASE, #endif -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 STM32_GPIOB_BASE, #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 STM32_GPIOC_BASE, #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 STM32_GPIOD_BASE, #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 STM32_GPIOE_BASE, #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 STM32_GPIOF_BASE, #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 STM32_GPIOG_BASE, #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 STM32_GPIOH_BASE, #endif }; @@ -139,7 +139,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -350,7 +350,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -390,7 +390,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h index 9b3552cedc8..ab323a048ab 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ b/arch/arm/src/stm32h5/stm32_gpio.h @@ -242,7 +242,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h5/stm32_icache.c b/arch/arm/src/stm32h5/stm32_icache.c index 8cd9c0483ee..8566734a1ae 100644 --- a/arch/arm/src/stm32h5/stm32_icache.c +++ b/arch/arm/src/stm32h5/stm32_icache.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H5_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ +#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ defined(CONFIG_STM32H5_ICACHE_ERR_INT)) /**************************************************************************** @@ -266,7 +266,7 @@ void stm32_icache_initialize(void) stm32_icache_setup_region(region3); #endif -#if STM32H5_ICACHE_INTERRUPT +#if STM32_ICACHE_INTERRUPT /* Attach ISR */ int ret; diff --git a/arch/arm/src/stm32h5/stm32_lowputc.c b/arch/arm/src/stm32h5/stm32_lowputc.c index 7de76e7300c..16a0a613166 100644 --- a/arch/arm/src/stm32h5/stm32_lowputc.c +++ b/arch/arm/src/stm32h5/stm32_lowputc.c @@ -46,260 +46,260 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_LPUART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB3ENR -# define STM32H5_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32H5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB3ENR +# define STM32_CONSOLE_APBEN RCC_APB3ENR_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART1_BASE -# define STM32H5_APBCLOCK STM32_PCLK2_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB2ENR -# define STM32H5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART1_TX -# define STM32H5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART2_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART2EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART2_TX -# define STM32H5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART3_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART3EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART3_TX -# define STM32H5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART4_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART4EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART4_TX -# define STM32H5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART5_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART5EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART5_TX -# define STM32H5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART6_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART6_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART6EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART6_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART6_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART6_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART6_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART6_TX -# define STM32H5_CONSOLE_RX GPIO_USART6_RX +# define STM32_CONSOLE_BASE STM32_USART6_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART6EN +# define STM32_CONSOLE_BAUD CONFIG_USART6_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART6_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART6_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART6_2STOP +# define STM32_CONSOLE_TX GPIO_USART6_TX +# define STM32_CONSOLE_RX GPIO_USART6_RX # ifdef CONFIG_USART6_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR # if (CONFIG_USART6_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART7_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART7_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART7EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART7_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART7_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART7_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART7_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART7_TX -# define STM32H5_CONSOLE_RX GPIO_UART7_RX +# define STM32_CONSOLE_BASE STM32_UART7_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART7EN +# define STM32_CONSOLE_BAUD CONFIG_UART7_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART7_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART7_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART7_2STOP +# define STM32_CONSOLE_TX GPIO_UART7_TX +# define STM32_CONSOLE_RX GPIO_UART7_RX # ifdef CONFIG_UART7_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART7_RS485_DIR # if (CONFIG_UART7_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART8_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART8_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART8EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART8_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART8_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART8_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART8_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART8_TX -# define STM32H5_CONSOLE_RX GPIO_UART8_RX +# define STM32_CONSOLE_BASE STM32_UART8_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART8EN +# define STM32_CONSOLE_BAUD CONFIG_UART8_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART8_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART8_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART8_2STOP +# define STM32_CONSOLE_TX GPIO_UART8_TX +# define STM32_CONSOLE_RX GPIO_UART8_RX # ifdef CONFIG_UART8_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART8_RS485_DIR # if (CONFIG_UART8_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART9_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART9_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART9EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART9_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART9_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART9_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART9_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART9_TX -# define STM32H5_CONSOLE_RX GPIO_UART9_RX +# define STM32_CONSOLE_BASE STM32_UART9_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART9EN +# define STM32_CONSOLE_BAUD CONFIG_UART9_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART9_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART9_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART9_2STOP +# define STM32_CONSOLE_TX GPIO_UART9_TX +# define STM32_CONSOLE_RX GPIO_UART9_RX # ifdef CONFIG_UART9_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART9_RS485_DIR # if (CONFIG_UART9_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART10_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART10_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART10EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART10_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART10_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART10_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART10_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART10_TX -# define STM32H5_CONSOLE_RX GPIO_USART10_RX +# define STM32_CONSOLE_BASE STM32_USART10_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART10EN +# define STM32_CONSOLE_BAUD CONFIG_USART10_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART10_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART10_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART10_2STOP +# define STM32_CONSOLE_TX GPIO_USART10_TX +# define STM32_CONSOLE_RX GPIO_USART10_RX # ifdef CONFIG_USART10_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART10_RS485_DIR # if (CONFIG_USART10_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART11_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_USART11_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_USART11EN -# define STM32H5_CONSOLE_BAUD CONFIG_USART11_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_USART11_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_USART11_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_USART11_2STOP -# define STM32H5_CONSOLE_TX GPIO_USART11_TX -# define STM32H5_CONSOLE_RX GPIO_USART11_RX +# define STM32_CONSOLE_BASE STM32_USART11_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_USART11EN +# define STM32_CONSOLE_BAUD CONFIG_USART11_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART11_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART11_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART11_2STOP +# define STM32_CONSOLE_TX GPIO_USART11_TX +# define STM32_CONSOLE_RX GPIO_USART11_RX # ifdef CONFIG_USART11_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART11_RS485_DIR # if (CONFIG_USART11_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART12_SERIAL_CONSOLE) -# define STM32H5_CONSOLE_BASE STM32_UART12_BASE -# define STM32H5_APBCLOCK STM32_PCLK1_FREQUENCY -# define STM32H5_CONSOLE_APBREG STM32_RCC_APB1LENR -# define STM32H5_CONSOLE_APBEN RCC_APB1LENR_UART12EN -# define STM32H5_CONSOLE_BAUD CONFIG_UART12_BAUD -# define STM32H5_CONSOLE_BITS CONFIG_UART12_BITS -# define STM32H5_CONSOLE_PARITY CONFIG_UART12_PARITY -# define STM32H5_CONSOLE_2STOP CONFIG_UART12_2STOP -# define STM32H5_CONSOLE_TX GPIO_UART12_TX -# define STM32H5_CONSOLE_RX GPIO_UART12_RX +# define STM32_CONSOLE_BASE STM32_UART12_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1LENR +# define STM32_CONSOLE_APBEN RCC_APB1LENR_UART12EN +# define STM32_CONSOLE_BAUD CONFIG_UART12_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART12_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART12_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART12_2STOP +# define STM32_CONSOLE_TX GPIO_UART12_TX +# define STM32_CONSOLE_RX GPIO_UART12_RX # ifdef CONFIG_UART12_RS485 -# define STM32H5_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART12_RS485_DIR # if (CONFIG_UART12_RS485_DIR_POLARITY == 0) -# define STM32H5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32H5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32H5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32H5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -307,15 +307,15 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32H5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32H5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 # endif -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE # define USART_CR1_CLRBITS \ (USART_CR1_UE | USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \ USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M0 | USART_CR1_M1 | \ @@ -333,7 +333,7 @@ /* CR2 settings */ -# if STM32H5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -362,7 +362,7 @@ # undef USE_OVER8 /* Calculate USART BAUD rate divider */ -# if STM32H5_CONSOLE_BASE == STM32_LPUART1_BASE +# if STM32_CONSOLE_BASE == STM32_LPUART1_BASE /* BRR = (256 * (APBCLOCK / Prescaler)) / (Baud rate) * With Prescaler == 16, BRR = (16 * APBCLOCK / (Baud rate) @@ -388,19 +388,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32H5_USARTDIV8 \ - (((STM32H5_APBCLOCK << 1) + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) -# define STM32H5_USARTDIV16 \ - ((STM32H5_APBCLOCK + (STM32H5_CONSOLE_BAUD >> 1)) / STM32H5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32H5_USARTDIV8 > 2000 -# define STM32H5_BRR_VALUE STM32H5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32H5_BRR_VALUE \ - ((STM32H5_USARTDIV8 & 0xfff0) | ((STM32H5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif #endif /* HAVE_CONSOLE */ @@ -442,22 +442,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32H5_CONSOLE_BASE + STM32_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32H5_CONSOLE_RS485_DIR - while ((getreg32(STM32H5_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -483,7 +483,7 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB clock */ - modifyreg32(STM32H5_CONSOLE_APBREG, 0, STM32H5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -492,17 +492,17 @@ void stm32_lowsetup(void) * stm32_rcc.c */ -#ifdef STM32H5_CONSOLE_TX - stm32_configgpio(STM32H5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32H5_CONSOLE_RX - stm32_configgpio(STM32H5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32H5_CONSOLE_RS485_DIR - stm32_configgpio(STM32H5_CONSOLE_RS485_DIR); - stm32_gpiowrite(STM32H5_CONSOLE_RS485_DIR, - !STM32H5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -510,42 +510,42 @@ void stm32_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32H5_BRR_VALUE, - STM32H5_CONSOLE_BASE + STM32_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32H5_CONSOLE_BASE + STM32_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.c b/arch/arm/src/stm32h5/stm32_rcc.c index e54cd1f2ce2..0b4dc0fad41 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.c +++ b/arch/arm/src/stm32h5/stm32_rcc.c @@ -111,14 +111,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32h5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32H5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32H5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -136,14 +136,14 @@ static inline void rcc_resetbkp(void) /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32H5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32H5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index 4d2e94ad577..d0a3152b478 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -1429,7 +1429,7 @@ static struct stm32_serial_s g_uart12priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -2012,7 +2012,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -3930,7 +3930,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -4000,7 +4000,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -4069,7 +4069,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index 812f82951ed..ec63b6dac10 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -83,10 +83,10 @@ */ #define SRAM2_START STM32_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define SRAM3_START STM32_SRAM3_BASE -#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE) +#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 46fb168b718..11d20e68e67 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -84,28 +84,28 @@ /* Hardware definitions */ -#define STM32H5_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS -#define STM32H5_EP0_MAX_PACKET_SIZE 64 -#define STM32H5_RETRY_COUNT 3 /* Control transfer retries */ +#define STM32_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS +#define STM32_EP0_MAX_PACKET_SIZE 64 +#define STM32_RETRY_COUNT 3 /* Control transfer retries */ /* PMA Buffer allocation (fixed-size bitmap allocator) */ -#define STM32H5_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ -#define STM32H5_PMA_NBUFFERS 30 /* Total allocatable buffers */ -#define STM32H5_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ -#define STM32H5_PMA_BUFFER_BIT(bn) (1U << (bn)) -#define STM32H5_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32H5_PMA_BUFFER_SIZE)) -#define STM32H5_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ +#define STM32_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */ +#define STM32_PMA_NBUFFERS 30 /* Total allocatable buffers */ +#define STM32_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */ +#define STM32_PMA_BUFFER_BIT(bn) (1U << (bn)) +#define STM32_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32_PMA_BUFFER_SIZE)) +#define STM32_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */ /* Delays */ -#define STM32H5_DATANAK_DELAY SEC2TICK(5) -#define STM32H5_RESET_DELAY 100 /* ms */ +#define STM32_DATANAK_DELAY SEC2TICK(5) +#define STM32_RESET_DELAY 100 /* ms */ /* USB DRD base addresses */ -#define STM32H5_USBDRD_BASE STM32_USB_FS_BASE -#define STM32H5_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE +#define STM32_USBDRD_BASE STM32_USB_FS_BASE +#define STM32_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE /* Register access helpers */ @@ -115,7 +115,7 @@ /* Channel register access */ -#define STM32H5_USB_CHEP(n) (STM32H5_USBDRD_BASE + ((n) << 2)) +#define STM32_USB_CHEP(n) (STM32_USBDRD_BASE + ((n) << 2)) /* Host channel data PID values */ @@ -227,7 +227,7 @@ struct stm32_usbhost_s /* Host channels */ - struct stm32_chan_s chan[STM32H5_NHOST_CHANNELS]; + struct stm32_chan_s chan[STM32_NHOST_CHANNELS]; /* PMA allocation */ @@ -416,7 +416,7 @@ static void stm32_pma_write(const uint8_t *buffer, uint16_t pmaaddr, uint32_t count; uint32_t remaining; - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; /* Number of 32-bit words */ remaining = nbytes & 0x03; /* Remaining bytes */ @@ -466,7 +466,7 @@ static void stm32_pma_read(uint8_t *buffer, uint16_t pmaaddr, UP_DSB(); - pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr); + pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr); count = nbytes >> 2; remaining = nbytes & 0x03; @@ -508,9 +508,9 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) flags = enter_critical_section(); - for (bufndx = 0; bufndx < STM32H5_PMA_NBUFFERS; bufndx++) + for (bufndx = 0; bufndx < STM32_PMA_NBUFFERS; bufndx++) { - uint32_t bit = STM32H5_PMA_BUFFER_BIT(bufndx); + uint32_t bit = STM32_PMA_BUFFER_BIT(bufndx); if ((priv->pma_bufavail & bit) != 0) { priv->pma_bufavail &= ~bit; /* Mark allocated */ @@ -524,12 +524,12 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv) if (bufno >= 0) { uinfo("PMA buffer allocated: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } else { uerr("ERROR: PMA buffer allocation failed, all %d buffers in use\n", - STM32H5_PMA_NBUFFERS); + STM32_PMA_NBUFFERS); } return bufno; @@ -548,14 +548,14 @@ static void stm32_pma_free_buffer(struct stm32_usbhost_s *priv, { irqstate_t flags; - DEBUGASSERT(bufno < STM32H5_PMA_NBUFFERS); + DEBUGASSERT(bufno < STM32_PMA_NBUFFERS); flags = enter_critical_section(); - priv->pma_bufavail |= STM32H5_PMA_BUFFER_BIT(bufno); /* Mark available */ + priv->pma_bufavail |= STM32_PMA_BUFFER_BIT(bufno); /* Mark available */ leave_critical_section(flags); uinfo("PMA buffer freed: bufno=%d addr=0x%04x\n", - bufno, STM32H5_PMA_BUFNO2ADDR(bufno)); + bufno, STM32_PMA_BUFNO2ADDR(bufno)); } /**************************************************************************** @@ -570,7 +570,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (!priv->chan[chidx].inuse) { @@ -582,7 +582,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv) priv->chan[chidx].inuse = true; priv->chan[chidx].pmabufno = (uint8_t)bufno; - priv->chan[chidx].pmaaddr = STM32H5_PMA_BUFNO2ADDR(bufno); + priv->chan[chidx].pmaaddr = STM32_PMA_BUFNO2ADDR(bufno); uinfo("Channel allocated: chidx=%d\n", chidx); return chidx; } @@ -604,18 +604,18 @@ static inline void stm32_chan_free(struct stm32_usbhost_s *priv, { struct stm32_chan_s *chan; - DEBUGASSERT((unsigned)chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; /* Free PMA buffer if allocated */ - if (chan->pmabufno != STM32H5_PMA_BUFFER_NONE) + if (chan->pmabufno != STM32_PMA_BUFFER_NONE) { stm32_set_chep_rx_status(priv, chidx, USB_CHEP_RX_STRX_DIS); stm32_set_chep_tx_status(priv, chidx, USB_CHEP_TX_STTX_DIS); stm32_pma_free_buffer(priv, chan->pmabufno); - chan->pmabufno = STM32H5_PMA_BUFFER_NONE; + chan->pmabufno = STM32_PMA_BUFFER_NONE; chan->pmaaddr = 0; uinfo("Channel freed: chidx=%d\n", chidx); } @@ -639,7 +639,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_TX_DTOGMASK; if (status & USB_CHEP_TX_DTOG1) { @@ -651,7 +651,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_TX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -671,7 +671,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, /* Status changes work by toggling the DTOG bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx)) + regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx)) & USB_CHEP_RX_DTOGMASK; if (status & USB_CHEP_RX_DTOG1) { @@ -683,7 +683,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv, regval ^= USB_CHEP_RX_DTOG2; } - stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx), + stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -701,7 +701,7 @@ static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) /* Free all host channels */ - for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { if (priv->chan[chidx].inuse) { @@ -748,7 +748,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Read current register value and mask toggleable bits */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CH_T_MASK; + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CH_T_MASK; /* Set endpoint type */ @@ -772,7 +772,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv, /* Write the channel register with VT bits preserved */ - stm32_putreg(STM32H5_USB_CHEP(chidx), + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -944,7 +944,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -956,7 +956,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, chan->eptype = USB_EP_ATTR_XFER_CONTROL; chan->funcaddr = funcaddr; chan->speed = speed; - chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE; + chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1092,7 +1092,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval |= (nblocks << USB_PMA_RXBD_NUM_BLOCK_SHIFT); } - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); *pbd = bdval; @@ -1104,7 +1104,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, /* Clear data toggle if starting new transfer */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_RX) != 0) { if (!chan->indata1) @@ -1113,7 +1113,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1124,7 +1124,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1146,7 +1146,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, bdval = chan->pmaaddr; /* chan->pmaaddr is already 4 byte aligned */ bdval |= ((uint32_t)len << USB_PMA_TXBD_COUNT_SHIFT); - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_TXBD_OFFSET(chidx)); *pbd = bdval; @@ -1154,8 +1154,8 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, if (chan->pid == HC_PID_SETUP) { - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; - stm32_putreg(STM32H5_USB_CHEP(chidx), + regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CHEP_REG_MASK; + stm32_putreg(STM32_USB_CHEP(chidx), regval | USB_CHEP_SETUP | USB_CHEP_VTRX | USB_CHEP_VTTX); } @@ -1164,7 +1164,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, * hardware auto-toggles after successful transmit) */ - regval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + regval = stm32_getreg(STM32_USB_CHEP(chidx)); if ((regval & USB_CHEP_DTOG_TX) != 0) { if (!chan->outdata1) @@ -1173,7 +1173,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } else @@ -1184,7 +1184,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv, regval = (regval & USB_CHEP_REG_MASK) | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX; - stm32_putreg(STM32H5_USB_CHEP(chidx), regval); + stm32_putreg(STM32_USB_CHEP(chidx), regval); } } @@ -1460,13 +1460,13 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t rx_status = chepval & USB_CHEP_RX_STRX_MASK; bool wakeup = false; if ((chepval & USB_CHEP_ERRRX) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uerr("ERRRX chidx=%d chepval=0x%08x rx_status=%d nak=%d\n", chidx, (unsigned int)chepval, (int)((chepval & USB_CHEP_RX_STRX_MASK) >> @@ -1479,7 +1479,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK) & ~USB_CHEP_ERRRX) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1500,7 +1500,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) uint16_t count; bool transfer_complete; - pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + + pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + USB_PMA_RXBD_OFFSET(chidx)); count = (*pbd >> USB_PMA_RXBD_COUNT_SHIFT) & 0x3ff; @@ -1546,10 +1546,10 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); /* More data expected - reactivate channel for next packet */ @@ -1598,9 +1598,9 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) * (toggle bit, write 1 keeps, write 0 clears) */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -1620,7 +1620,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx) static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) { struct stm32_chan_s *chan = &priv->chan[chidx]; - uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx)); uint32_t tx_status = chepval & USB_CHEP_TX_STTX_MASK; bool wakeup = false; @@ -1630,10 +1630,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) * write 1 to VTRX/VTTX to preserve */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_ERRTX) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); chan->result = EIO; chan->chreason = CHREASON_TXERR; @@ -1699,10 +1699,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) if ((chepval & USB_CHEP_NAK) != 0) { - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_NAK) | USB_CHEP_VTRX | USB_CHEP_VTTX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); } if (!chan->waiter && !chan->callback) @@ -1728,9 +1728,9 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx) /* Clear VTTX by writing 0 to it */ - chepval = stm32_getreg(STM32H5_USB_CHEP(chidx)); + chepval = stm32_getreg(STM32_USB_CHEP(chidx)); chepval = (chepval & (0xffffff7f & USB_CHEP_REG_MASK)) | USB_CHEP_VTRX; - stm32_putreg(STM32H5_USB_CHEP(chidx), chepval); + stm32_putreg(STM32_USB_CHEP(chidx), chepval); if (wakeup) { @@ -2132,11 +2132,11 @@ static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /* A single channel is represent by an index in the range of 0 to - * STM32H5_NHOST_CHANNELS. Otherwise, the ep must be a pointer to + * STM32_NHOST_CHANNELS. Otherwise, the ep must be a pointer to * an allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32H5_NHOST_CHANNELS) + if ((uintptr_t)ep < STM32_NHOST_CHANNELS) { /* Halt the channel and mark the channel available */ @@ -2275,7 +2275,7 @@ static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2351,7 +2351,7 @@ static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, return ret; } - for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send SETUP */ @@ -2409,7 +2409,7 @@ static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, ssize_t nbytes; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2461,7 +2461,7 @@ static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, struct stm32_chan_s *chan; int ret; - DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS); ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -2499,7 +2499,7 @@ static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) struct stm32_chan_s *chan; irqstate_t flags; - DEBUGASSERT(priv && chidx < STM32H5_NHOST_CHANNELS); + DEBUGASSERT(priv && chidx < STM32_NHOST_CHANNELS); chan = &priv->chan[chidx]; @@ -2595,7 +2595,7 @@ static void stm32_portreset(struct stm32_usbhost_s *priv) /* Wait for reset */ - nxsched_usleep(STM32H5_RESET_DELAY * 1000); + nxsched_usleep(STM32_RESET_DELAY * 1000); /* Release reset */ @@ -2722,15 +2722,15 @@ static void stm32_sw_initialize(struct stm32_usbhost_s *priv) /* Initialize PMA allocation - all buffers available */ - priv->pma_bufavail = STM32H5_PMA_BUFFER_ALLSET; + priv->pma_bufavail = STM32_PMA_BUFFER_ALLSET; /* Initialize channels */ - for (i = 0; i < STM32H5_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { priv->chan[i].chidx = i; priv->chan[i].inuse = false; - priv->chan[i].pmabufno = STM32H5_PMA_BUFFER_NONE; + priv->chan[i].pmabufno = STM32_PMA_BUFFER_NONE; nxsem_init(&priv->chan[i].waitsem, 0, 0); } } diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 3b2aebdcaff..199cc59b9d9 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -96,7 +96,7 @@ #elif defined(CONFIG_STM32H5_FLASH_CONFIG_B) # define H5_FLASH_BANK_NBLOCKS 8 #else -# warning "No valid STM32H5_FLASH_CONFIG_x defined." +# warning "No valid STM32_FLASH_CONFIG_x defined." #endif #define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS) diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 62f94162fbb..87b12f55e92 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -58,19 +58,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48) -# if defined(STM32H5_CLKUSB_SEL) -# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if defined(STM32_CLKUSB_SEL) +# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif -# if defined(STM32H5_CLKRNG_SEL) -# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) -# define STM32H5_USE_HSI48 1 +# if defined(STM32_CLKRNG_SEL) +# if (STM32_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK) +# define STM32_USE_HSI48 1 # endif # endif #endif @@ -203,30 +203,30 @@ static inline void rcc_enableahb2(void) /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32H5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32H5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32H5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32H5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32H5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32H5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32H5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32H5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOIEN #endif @@ -419,8 +419,8 @@ static inline void rcc_enableapb1l(void) regval |= RCC_APB1LENR_I3C1EN; #endif -#ifdef STM32H5_USE_HSI48 - if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Bit 24: CRS clock enable */ @@ -842,10 +842,10 @@ void stm32_rcc_enableperipherals(void) rcc_enableapb2(); rcc_enableapb3(); -#ifdef STM32H5_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32H5_HSI48_SYNCSRC); + stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -1097,14 +1097,14 @@ void stm32_stdclockconfig(void) } #if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ - defined(STM32H5_USE_LSCO_LSI) + defined(STM32_USE_LSCO_LSI) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(STM32_USE_LSE) || defined(STM32H5_USE_LSCO_LSE) +#if defined(STM32_USE_LSE) || defined(STM32_USE_LSCO_LSE) /* Low speed external clock source LSE */ stm32_rcc_enablelse(); @@ -1203,19 +1203,19 @@ void stm32_stdclockconfig(void) /* Configure USB source clock */ -#if defined(STM32H5_CLKUSB_SEL) +#if defined(STM32_CLKUSB_SEL) regval = getreg32(STM32_RCC_CCIPR4); regval &= ~RCC_CCIPR4_USBSEL_MASK; - regval |= STM32H5_CLKUSB_SEL; + regval |= STM32_CLKUSB_SEL; putreg32(regval, STM32_RCC_CCIPR4); #endif /* Configure RNG source clock */ -#if defined(STM32H5_CLKRNG_SEL) +#if defined(STM32_CLKRNG_SEL) regval = getreg32(STM32_RCC_CCIPR5); regval &= ~RCC_CCIPR5_RNGSEL_MASK; - regval |= STM32H5_CLKRNG_SEL; + regval |= STM32_CLKRNG_SEL; putreg32(regval, STM32_RCC_CCIPR5); #endif } diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index 11ff18fb037..d68741a2620 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -132,7 +132,7 @@ #define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FRQ / 10) /* 48 MHz */ /* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */ -#define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK +#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK #endif /* CONFIG_STM32H5_USBFS_HOST */ @@ -186,18 +186,18 @@ /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) -# define STM32H5_USE_CLK48 1 +# define STM32_USE_CLK48 1 #endif #if defined(CONFIG_STM32H5_USBFS) -# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK -# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB +# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK +# define STM32_HSI48_SYNCSRC SYNCSRC_USB #else -# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif #if defined(CONFIG_STM32H5_RNG) -# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK +# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK #endif /* Enable LSE (for the RTC) */ From 8397881df4a1a662f36149682893170627353414 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 050/268] !arch/stm32h7: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32H7 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32h7/chip.h | 192 +++++++++--------- arch/arm/src/stm32h7/hardware/stm32_qspi.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_gpio.h | 22 +- .../src/stm32h7/hardware/stm32h7x3xx_i2c.h | 8 +- .../src/stm32h7/hardware/stm32h7x3xx_spi.h | 12 +- .../src/stm32h7/hardware/stm32h7x3xx_uart.h | 16 +- arch/arm/src/stm32h7/stm32_allocateheap.c | 12 +- arch/arm/src/stm32h7/stm32_bbsram.c | 10 +- arch/arm/src/stm32h7/stm32_bbsram.h | 8 +- .../arm/src/stm32h7/stm32_capture_lowerhalf.c | 62 +++--- arch/arm/src/stm32h7/stm32_ethernet.c | 106 +++++----- arch/arm/src/stm32h7/stm32_ethernet.h | 6 +- arch/arm/src/stm32h7/stm32_gpio.c | 30 +-- arch/arm/src/stm32h7/stm32_gpio.h | 24 +-- arch/arm/src/stm32h7/stm32_mpuinit.c | 2 +- arch/arm/src/stm32h7/stm32_otg.h | 2 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 4 +- arch/arm/src/stm32h7/stm32_serial.c | 6 +- arch/arm/src/stm32h7/stm32_uart.h | 16 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 22 +- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 22 +- 21 files changed, 293 insertions(+), 293 deletions(-) diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index b97a8659e6c..2aa62e17e93 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -95,154 +95,154 @@ /* Memory */ # ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX -# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7B3XX) /* Memory */ -# define STM32H7_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (64*1024) /* 64Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (128*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ # if defined(CONFIG_STM32H7_IO_CONFIG_A) -# define STM32H7_NGPIO (10) /* GPIOA-GPIOJ */ +# define STM32_NGPIO (10) /* GPIOA-GPIOJ */ # elif defined(CONFIG_STM32H7_IO_CONFIG_B) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_I) -# define STM32H7_NGPIO (9) /* GPIOA-GPIOI */ +# define STM32_NGPIO (9) /* GPIOA-GPIOI */ # elif defined(CONFIG_STM32H7_IO_CONFIG_L) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_V) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH, missing GPIOF-GPIOG */ # elif defined(CONFIG_STM32H7_IO_CONFIG_X) -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ # elif defined(CONFIG_STM32H7_IO_CONFIG_Z) -# define STM32H7_NGPIO (8) /* GPIOA-GPIOH */ +# define STM32_NGPIO (8) /* GPIOA-GPIOH */ # else # error CONFIG_STM32H7_IO_CONFIG_x Not Set # endif -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #elif defined(CONFIG_STM32H7_STM32H7X7XX) /* Memory */ -# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ -# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ -# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ +# define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ +# define STM32_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ +# define STM32_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ +# define STM32_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ +# define STM32_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) -# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # else -# define STM32H7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ +# define STM32_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */ # endif # if defined(CONFIG_ARMV7M_HAVE_ITCM) -# define STM32H7_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (64*1024) /* 64b ITCM SRAM on TCM interface */ # else -# define STM32H7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ +# define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif /* Peripherals */ -# define STM32H7_NGPIO (11) /* GPIOA-GPIOK */ -# define STM32H7_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ -# define STM32H7_NADC (3) /* (3) ADC1-3*/ -# define STM32H7_NDAC (2) /* (2) DAC1-2*/ -# define STM32H7_NCMP (2) /* (2) ultra-low power comparators */ -# define STM32H7_NPGA (2) /* (2) Operational amplifiers: OPAMP */ -# define STM32H7_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ -# define STM32H7_NUSART (4) /* (4) USART1-3, 6 */ -# define STM32H7_NSPI (6) /* (6) SPI1-6 */ -# define STM32H7_NI2S (3) /* (3) I2S1-3 */ -# define STM32H7_NUART (4) /* (4) UART4-5, 7-8 */ -# define STM32H7_NI2C (4) /* (4) I2C1-4 */ -# define STM32H7_NSAI (4) /* (4) SAI1-4*/ -# define STM32H7_NCAN (2) /* (2) CAN1-2 */ -# define STM32H7_NSDIO (2) /* (2) SDIO */ +# define STM32_NGPIO (11) /* GPIOA-GPIOK */ +# define STM32_NDMA (4) /* (4) DMA1, DMA2, BDMA and MDMA */ +# define STM32_NADC (3) /* (3) ADC1-3*/ +# define STM32_NDAC (2) /* (2) DAC1-2*/ +# define STM32_NCMP (2) /* (2) ultra-low power comparators */ +# define STM32_NPGA (2) /* (2) Operational amplifiers: OPAMP */ +# define STM32_NDFSDM (1) /* (1) digital filters for sigma delta modulator */ +# define STM32_NUSART (4) /* (4) USART1-3, 6 */ +# define STM32_NSPI (6) /* (6) SPI1-6 */ +# define STM32_NI2S (3) /* (3) I2S1-3 */ +# define STM32_NUART (4) /* (4) UART4-5, 7-8 */ +# define STM32_NI2C (4) /* (4) I2C1-4 */ +# define STM32_NSAI (4) /* (4) SAI1-4*/ +# define STM32_NCAN (2) /* (2) CAN1-2 */ +# define STM32_NSDIO (2) /* (2) SDIO */ #else # error STM32 H7 chip Family not identified #endif @@ -260,15 +260,15 @@ /* Diversification based on Family and package */ #if defined(CONFIG_STM32H7_HAVE_ETHERNET) -# define STM32H7_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else -# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */ +# define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif #if defined(CONFIG_STM32H7_HAVE_FMC) -# define STM32H7_NFMC 1 /* Have FMC memory controller */ +# define STM32_NFMC 1 /* Have FMC memory controller */ #else -# define STM32H7_NFMC 0 /* No FMC memory controller */ +# define STM32_NFMC 0 /* No FMC memory controller */ #endif /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32_qspi.h b/arch/arm/src/stm32h7/hardware/stm32_qspi.h index dcc4e882cdf..a66957eac89 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_qspi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_qspi.h @@ -38,8 +38,8 @@ /* General Characteristics **************************************************/ -#define STM32H7_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32H7_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index e052e88da45..c38ff4666e2 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -55,7 +55,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -68,7 +68,7 @@ # define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -81,7 +81,7 @@ # define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -94,7 +94,7 @@ # define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -107,7 +107,7 @@ # define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -146,7 +146,7 @@ # define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -159,7 +159,7 @@ # define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -172,7 +172,7 @@ # define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define STM32_GPIOJ_MODER (STM32_GPIOJ_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOJ_OTYPER (STM32_GPIOJ_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOJ_OSPEED (STM32_GPIOJ_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -185,7 +185,7 @@ # define STM32_GPIOJ_AFRH (STM32_GPIOJ_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define STM32_GPIOK_MODER (STM32_GPIOK_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOK_OTYPER (STM32_GPIOK_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOK_OSPEED (STM32_GPIOK_BASE+STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h index bd2e3590407..944b1f0ef2c 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_i2c.h @@ -43,7 +43,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NI2C > 0 +#if STM32_NI2C > 0 # define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) @@ -57,7 +57,7 @@ # define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 1 +#if STM32_NI2C > 1 # define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) @@ -71,7 +71,7 @@ # define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 2 +#if STM32_NI2C > 2 # define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) @@ -85,7 +85,7 @@ # define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32H7_NI2C > 3 +#if STM32_NI2C > 3 # define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) # define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) # define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index 2e00669d7d4..fa7c71d92bf 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -62,7 +62,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NSPI > 0 +#if STM32_NSPI > 0 # define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET) @@ -79,7 +79,7 @@ # define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 1 +#if STM32_NSPI > 1 # define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET) @@ -96,7 +96,7 @@ # define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 2 +#if STM32_NSPI > 2 # define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET) @@ -113,7 +113,7 @@ # define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 3 +#if STM32_NSPI > 3 # define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET) @@ -130,7 +130,7 @@ # define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 4 +#if STM32_NSPI > 4 # define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET) @@ -147,7 +147,7 @@ # define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET) #endif -#if STM32H7_NSPI > 5 +#if STM32_NSPI > 5 # define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET) # define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET) # define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET) diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index e5785ef1c16..7bab6c142c4 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -58,7 +58,7 @@ /* Register Addresses *******************************************************/ -#if STM32H7_NUSART > 0 +#if STM32_NUSART > 0 # define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) @@ -74,7 +74,7 @@ # define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 1 +#if STM32_NUSART > 1 # define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) @@ -90,7 +90,7 @@ # define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 2 +#if STM32_NUSART > 2 # define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) @@ -106,7 +106,7 @@ # define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUSART > 3 +#if STM32_NUSART > 3 # define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET) # define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET) # define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET) @@ -122,7 +122,7 @@ # define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32H7_NUART > 0 +#if STM32_NUART > 0 # define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) @@ -137,7 +137,7 @@ # define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 1 +#if STM32_NUART > 1 # define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) @@ -152,7 +152,7 @@ # define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 2 +#if STM32_NUART > 2 # define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET) @@ -167,7 +167,7 @@ # define STM32_UART7_TDR (STM32_UART7_BASE + STM32_USART_TDR_OFFSET) #endif -#if STM32H7_NUART > 3 +#if STM32_NUART > 3 # define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET) # define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET) # define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET) diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index cec7d503b3b..3b64acba794 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -111,10 +111,10 @@ /* Set the start and end of the SRAMs */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ defined(CONFIG_STM32H7_CORTEXM4_ENABLED) @@ -122,7 +122,7 @@ /* Configuration for M7 core when M4 core support enabled */ # define SRAM_START STM32_AXISRAM_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM_SIZE) /* Exclude SRAM123 */ @@ -134,8 +134,8 @@ /* Configuration for M4 core support enabled */ # define SRAM_START STM32_SRAM123_BASE -# define SRAM_END (SRAM_START + STM32H7_SRAM123_SIZE - \ - STM32H7_SRAM3_SIZE) +# define SRAM_END (SRAM_START + STM32_SRAM123_SIZE - \ + STM32_SRAM3_SIZE) #endif #undef HAVE_SRAM4 @@ -143,7 +143,7 @@ # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) -# define SRAM4_END ((uint32_t)(SRAM4_START + STM32H7_SRAM4_SIZE)) +# define SRAM4_END ((uint32_t)(SRAM4_START + STM32_SRAM4_SIZE)) # define SRAM4_HEAP_START ((uint32_t)_sram4_heap_start) #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index a4666960d31..8f27740c1aa 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -151,7 +151,7 @@ static int stm32_bbsram_unlink(struct inode *inode); ****************************************************************************/ #if defined(CONFIG_BBSRAM_DEBUG) -static uint8_t debug[STM32H7_BBSRAM_SIZE]; +static uint8_t debug[STM32_BBSRAM_SIZE]; #endif static const struct file_operations g_stm32_bbsram_fops = @@ -591,7 +591,7 @@ static int stm32_bbsram_ioctl(struct file *filep, int cmd, DEBUGASSERT(inode->i_private); bbr = inode->i_private; - if (cmd == STM32H7_BBSRAM_GETDESC_IOCTL) + if (cmd == STM32_BBSRAM_GETDESC_IOCTL) { struct bbsramd_s *bbrr = (struct bbsramd_s *)((uintptr_t)arg); @@ -688,7 +688,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) * after reset due to the ECC behavior. */ - avail = STM32H7_BBSRAM_SIZE; + avail = STM32_BBSRAM_SIZE; for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); i++) @@ -793,9 +793,9 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) */ # if defined(CONFIG_BUILD_PROTECTED) - mpu_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); # else - mpu_user_peripheral(STM32_BBSRAM_BASE, STM32H7_BBSRAM_SIZE); + mpu_user_peripheral(STM32_BBSRAM_BASE, STM32_BBSRAM_SIZE); mpu_control(true, true, true); # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index c9d41f73cc2..08421e22571 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -46,17 +46,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32H7_BBSRAM_SIZE 4096 +#define STM32_BBSRAM_SIZE 4096 #if !defined(CONFIG_STM32H7_BBSRAM_FILES) # define CONFIG_STM32H7_BBSRAM_FILES 4 #endif -/* REVISIT: What guarantees that STM32H7_BBSRAM_GETDESC_IOCTL has a unique +/* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique * value among all over _DIOC() values? */ -#define STM32H7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ +#define STM32_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ /**************************************************************************** * Public Types @@ -126,7 +126,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * Saves the panic context in a previously allocated BBSRAM file * * Parameters: -* fileno - the value returned by the ioctl STM32H7_BBSRAM_GETDESC_IOCTL +* fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL * context - Pointer to a any array of bytes to save * length - The length of the data pointed to byt context * diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index 6bdf846cfb0..c1a1e71517d 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -47,35 +47,35 @@ /* 32-Bit Timers ************************************************************/ -#define STM32H7_TIM2_RES 32 -#define STM32H7_TIM5_RES 32 +#define STM32_TIM2_RES 32 +#define STM32_TIM5_RES 32 /* 16-Bit Timers ************************************************************/ /* Advanced-Control Timers */ -#define STM32H7_TIM1_RES 16 -#define STM32H7_TIM8_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM8_RES 16 /* General-Purpose Timers */ -#define STM32H7_TIM3_RES 16 -#define STM32H7_TIM4_RES 16 -#define STM32H7_TIM12_RES 16 -#define STM32H7_TIM13_RES 16 -#define STM32H7_TIM14_RES 16 -#define STM32H7_TIM15_RES 16 -#define STM32H7_TIM16_RES 16 -#define STM32H7_TIM17_RES 16 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM12_RES 16 +#define STM32_TIM13_RES 16 +#define STM32_TIM14_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /* Basic Timers */ -#define STM32H7_TIM6_RES 16 -#define STM32H7_TIM7_RES 16 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 /* Low-Power Timers */ -#define STM32H7_LPTIM1_RES 16 -#define STM32H7_LPTIM2_RES 16 -#define STM32H7_LPTIM3_RES 16 -#define STM32H7_LPTIM4_RES 16 -#define STM32H7_LPTIM5_RES 16 +#define STM32_LPTIM1_RES 16 +#define STM32_LPTIM2_RES 16 +#define STM32_LPTIM3_RES 16 +#define STM32_LPTIM4_RES 16 +#define STM32_LPTIM5_RES 16 /**************************************************************************** * Private Types @@ -129,7 +129,7 @@ static const struct cap_ops_s g_cap_ops = static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM1_RES, + .resolution = STM32_TIM1_RES, .channel = CONFIG_STM32H7_TIM1_CHANNEL, .clock = CONFIG_STM32H7_TIM1_CLOCK, }; @@ -139,7 +139,7 @@ static struct stm32_lowerhalf_s g_cap1_lowerhalf = static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM2_RES, + .resolution = STM32_TIM2_RES, .channel = CONFIG_STM32H7_TIM2_CHANNEL, .clock = CONFIG_STM32H7_TIM2_CLOCK, }; @@ -149,7 +149,7 @@ static struct stm32_lowerhalf_s g_cap2_lowerhalf = static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM3_RES, + .resolution = STM32_TIM3_RES, .channel = CONFIG_STM32H7_TIM3_CHANNEL, .clock = CONFIG_STM32H7_TIM3_CLOCK, }; @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_cap3_lowerhalf = static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM4_RES, + .resolution = STM32_TIM4_RES, .channel = CONFIG_STM32H7_TIM4_CHANNEL, .clock = CONFIG_STM32H7_TIM4_CLOCK, }; @@ -169,7 +169,7 @@ static struct stm32_lowerhalf_s g_cap4_lowerhalf = static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM5_RES, + .resolution = STM32_TIM5_RES, .channel = CONFIG_STM32H7_TIM5_CHANNEL, .clock = CONFIG_STM32H7_TIM5_CLOCK, }; @@ -179,7 +179,7 @@ static struct stm32_lowerhalf_s g_cap5_lowerhalf = static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM8_RES, + .resolution = STM32_TIM8_RES, .channel = CONFIG_STM32H7_TIM8_CHANNEL, .clock = CONFIG_STM32H7_TIM8_CLOCK, }; @@ -189,7 +189,7 @@ static struct stm32_lowerhalf_s g_cap8_lowerhalf = static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM12_RES, + .resolution = STM32_TIM12_RES, .channel = CONFIG_STM32H7_TIM12_CHANNEL, .clock = CONFIG_STM32H7_TIM12_CLOCK, }; @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_cap12_lowerhalf = static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM13_RES, + .resolution = STM32_TIM13_RES, .channel = CONFIG_STM32H7_TIM13_CHANNEL, .clock = CONFIG_STM32H7_TIM13_CLOCK, }; @@ -209,7 +209,7 @@ static struct stm32_lowerhalf_s g_cap13_lowerhalf = static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM14_RES, + .resolution = STM32_TIM14_RES, .channel = CONFIG_STM32H7_TIM14_CHANNEL, .clock = CONFIG_STM32H7_TIM14_CLOCK, }; @@ -219,7 +219,7 @@ static struct stm32_lowerhalf_s g_cap14_lowerhalf = static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM15_RES, + .resolution = STM32_TIM15_RES, .channel = CONFIG_STM32H7_TIM15_CHANNEL, .clock = CONFIG_STM32H7_TIM15_CLOCK, }; @@ -229,7 +229,7 @@ static struct stm32_lowerhalf_s g_cap15_lowerhalf = static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM16_RES, + .resolution = STM32_TIM16_RES, .channel = CONFIG_STM32H7_TIM16_CHANNEL, .clock = CONFIG_STM32H7_TIM16_CLOCK, }; @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_cap16_lowerhalf = static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, - .resolution = STM32H7_TIM17_RES, + .resolution = STM32_TIM17_RES, .channel = CONFIG_STM32H7_TIM17_CHANNEL, .clock = CONFIG_STM32H7_TIM17_CLOCK, }; diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 2787c840596..9cd6b485b88 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -68,12 +68,12 @@ #include -/* STM32H7_NETHERNET determines the number of physical interfaces that can +/* STM32_NETHERNET determines the number of physical interfaces that can * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32H7_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -81,7 +81,7 @@ /* Configuration ************************************************************/ -#if STM32H7_NETHERNET > 1 +#if STM32_NETHERNET > 1 # error "Logic to support multiple Ethernet interfaces is incomplete" #endif @@ -105,59 +105,59 @@ #endif #if defined(CONFIG_ETH0_PHY_AM79C874) -# define STM32H7_PHYID1 MII_PHYID1_AM79C874 -# define STM32H7_PHYID2 MII_PHYID2_AM79C874 +# define STM32_PHYID1 MII_PHYID1_AM79C874 +# define STM32_PHYID2 MII_PHYID2_AM79C874 #elif defined(CONFIG_ETH0_PHY_AR8031) -# define STM32H7_PHYID1 MII_PHYID1_AR8031 -# define STM32H7_PHYID2 MII_PHYID2_AR8031 +# define STM32_PHYID1 MII_PHYID1_AR8031 +# define STM32_PHYID2 MII_PHYID2_AR8031 #elif defined(CONFIG_ETH0_PHY_KS8721) -# define STM32H7_PHYID1 MII_PHYID1_KS8721 -# define STM32H7_PHYID2 MII_PHYID2_KS8721 +# define STM32_PHYID1 MII_PHYID1_KS8721 +# define STM32_PHYID2 MII_PHYID2_KS8721 #elif defined(CONFIG_ETH0_PHY_KSZ8041) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8041 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8041 +# define STM32_PHYID1 MII_PHYID1_KSZ8041 +# define STM32_PHYID2 MII_PHYID2_KSZ8041 #elif defined(CONFIG_ETH0_PHY_KSZ8051) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8051 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8051 +# define STM32_PHYID1 MII_PHYID1_KSZ8051 +# define STM32_PHYID2 MII_PHYID2_KSZ8051 #elif defined(CONFIG_ETH0_PHY_KSZ8061) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8061 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8061 +# define STM32_PHYID1 MII_PHYID1_KSZ8061 +# define STM32_PHYID2 MII_PHYID2_KSZ8061 #elif defined(CONFIG_ETH0_PHY_KSZ8081) -# define STM32H7_PHYID1 MII_PHYID1_KSZ8081 -# define STM32H7_PHYID2 MII_PHYID2_KSZ8081 +# define STM32_PHYID1 MII_PHYID1_KSZ8081 +# define STM32_PHYID2 MII_PHYID2_KSZ8081 #elif defined(CONFIG_ETH0_PHY_DP83848C) -# define STM32H7_PHYID1 MII_PHYID1_DP83848C -# define STM32H7_PHYID2 MII_PHYID2_DP83848C +# define STM32_PHYID1 MII_PHYID1_DP83848C +# define STM32_PHYID2 MII_PHYID2_DP83848C #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define STM32H7_PHYID1 MII_PHYID1_DP83825I -# define STM32H7_PHYID2 MII_PHYID2_DP83825I +# define STM32_PHYID1 MII_PHYID1_DP83825I +# define STM32_PHYID2 MII_PHYID2_DP83825I #elif defined(CONFIG_ETH0_PHY_TJA1100) -# define STM32H7_PHYID1 MII_PHYID1_TJA1100 -# define STM32H7_PHYID2 MII_PHYID2_TJA1100 +# define STM32_PHYID1 MII_PHYID1_TJA1100 +# define STM32_PHYID2 MII_PHYID2_TJA1100 #elif defined(CONFIG_ETH0_PHY_TJA1101) -# define STM32H7_PHYID1 MII_PHYID1_TJA1101 -# define STM32H7_PHYID2 MII_PHYID2_TJA1101 +# define STM32_PHYID1 MII_PHYID1_TJA1101 +# define STM32_PHYID2 MII_PHYID2_TJA1101 #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define STM32H7_PHYID1 MII_PHYID1_TJA1103 -# define STM32H7_PHYID2 MII_PHYID2_TJA1103 +# define STM32_PHYID1 MII_PHYID1_TJA1103 +# define STM32_PHYID2 MII_PHYID2_TJA1103 #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define STM32H7_PHYID1 MII_PHYID1_LAN8720 -# define STM32H7_PHYID2 MII_PHYID2_LAN8720 +# define STM32_PHYID1 MII_PHYID1_LAN8720 +# define STM32_PHYID2 MII_PHYID2_LAN8720 #elif defined(CONFIG_ETH0_PHY_LAN8740) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740 -# define STM32H7_PHYID2 MII_PHYID2_LAN8740 +# define STM32_PHYID1 MII_PHYID1_LAN8740 +# define STM32_PHYID2 MII_PHYID2_LAN8740 #elif defined(CONFIG_ETH0_PHY_LAN8740A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8740A -# define STM32H7_PHYID2 MII_PHYID2_LAN8740A +# define STM32_PHYID1 MII_PHYID1_LAN8740A +# define STM32_PHYID2 MII_PHYID2_LAN8740A #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define STM32H7_PHYID1 MII_PHYID1_LAN8742A -# define STM32H7_PHYID2 MII_PHYID2_LAN8742A +# define STM32_PHYID1 MII_PHYID1_LAN8742A +# define STM32_PHYID2 MII_PHYID2_LAN8742A #elif defined(CONFIG_ETH0_PHY_DM9161) -# define STM32H7_PHYID1 MII_PHYID1_DM9161 -# define STM32H7_PHYID2 MII_PHYID2_DM9161 +# define STM32_PHYID1 MII_PHYID1_DM9161 +# define STM32_PHYID2 MII_PHYID2_DM9161 #elif defined(CONFIG_ETH0_PHY_YT8512) -# define STM32H7_PHYID1 MII_PHYID1_YT8512 -# define STM32H7_PHYID2 MII_PHYID2_YT8512 +# define STM32_PHYID1 MII_PHYID1_YT8512 +# define STM32_PHYID2 MII_PHYID2_YT8512 #else # warning "No PHY specified!" #endif @@ -289,14 +289,14 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32H7_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) #define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) -#define RXBUFFER_ALLOC (STM32H7_NETHERNET * RXBUFFER_SIZE) +#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) -#define TXBUFFER_ALLOC (STM32H7_NETHERNET * TXBUFFER_SIZE) +#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE) /* Extremely detailed register debug that you would normally never want * enabled. @@ -723,7 +723,7 @@ aligned_data(ARMV7M_DCACHE_LINESIZE); /* These are the pre-allocated Ethernet device structures */ -static struct stm32_ethmac_s g_stm32ethmac[STM32H7_NETHERNET]; +static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /**************************************************************************** * Private Function Prototypes @@ -3279,10 +3279,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if (phyval != STM32H7_PHYID1) + if (phyval != STM32_PHYID1) { nerr("ERROR: Incorrect PHYID1: %u expected: %u\n", - phyval, STM32H7_PHYID1); + phyval, STM32_PHYID1); return -ENXIO; } @@ -3297,10 +3297,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) return ret; } - if ((phyval & 0xfff0) != (STM32H7_PHYID2 & 0xfff0)) + if ((phyval & 0xfff0) != (STM32_PHYID2 & 0xfff0)) { nerr("ERROR: Incorrect PHYID2: %u expected: %u\n", - phyval, STM32H7_PHYID2); + phyval, STM32_PHYID2); return -ENXIO; } @@ -4120,7 +4120,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf) #else static inline int stm32_ethinitialize(int intf) @@ -4135,7 +4135,7 @@ static inline int stm32_ethinitialize(int intf) /* Get the interface structure associated with this interface number. */ - DEBUGASSERT(intf < STM32H7_NETHERNET); + DEBUGASSERT(intf < STM32_NETHERNET); priv = &g_stm32ethmac[intf]; /* Initialize the driver structure */ @@ -4216,7 +4216,7 @@ static inline int stm32_ethinitialize(int intf) * * Description: * This is the "standard" network initialization logic called from the - * low-level initialization logic in arm_initialize.c. If STM32H7_NETHERNET + * low-level initialization logic in arm_initialize.c. If STM32_NETHERNET * greater than one, then board specific logic will have to supply a * version of arm_netinitialize() that calls stm32_ethinitialize() with * the appropriate interface number. @@ -4231,11 +4231,11 @@ static inline int stm32_ethinitialize(int intf) * ****************************************************************************/ -#if STM32H7_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { stm32_ethinitialize(0); } #endif -#endif /* STM32H7_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 6f7026bacac..8faf17694ca 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -31,7 +31,7 @@ #include "hardware/stm32_ethernet.h" -#if STM32H7_NETHERNET > 0 +#if STM32_NETHERNET > 0 #ifndef __ASSEMBLY__ /**************************************************************************** @@ -67,7 +67,7 @@ extern "C" * ****************************************************************************/ -#if STM32H7_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) +#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT) int stm32_ethinitialize(int intf); #endif @@ -102,5 +102,5 @@ int stm32_phy_boardinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* STM32H7_NETHERNET > 0 */ +#endif /* STM32_NETHERNET > 0 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8f59ef8b8a8..8723b1d4b5f 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -62,47 +62,47 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32H7_NGPIO] = +const uint32_t g_gpiobase[STM32_NGPIO] = { -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 STM32_GPIOA_BASE, #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 STM32_GPIOB_BASE, #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 STM32_GPIOC_BASE, #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 STM32_GPIOD_BASE, #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 STM32_GPIOE_BASE, #endif -#if STM32H7_NGPIO > 5 +#if STM32_NGPIO > 5 # if defined(CONFIG_STM32H7_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 6 +#if STM32_NGPIO > 6 # if defined(CONFIG_STM32H7_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, # endif #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 STM32_GPIOH_BASE, #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 STM32_GPIOI_BASE, #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 STM32_GPIOJ_BASE, #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 STM32_GPIOK_BASE, #endif }; @@ -163,7 +163,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32H7_NGPIO) + if (port >= STM32_NGPIO) { return -EINVAL; } @@ -443,7 +443,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ @@ -485,7 +485,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32H7_NGPIO) + if (port < STM32_NGPIO) { /* Get the port base address */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index 02a644c3290..ab46e15a402 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -184,37 +184,37 @@ #define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */ #define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT) -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ #endif -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 # define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */ #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 # define GPIO_PORTI (8 << GPIO_PORT_SHIFT) /* GPIOI */ #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 # define GPIO_PORTJ (9 << GPIO_PORT_SHIFT) /* GPIOJ */ #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 # define GPIO_PORTK (10 << GPIO_PORT_SHIFT) /* GPIOK */ #endif @@ -262,7 +262,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32H7_NGPIO]; +EXTERN const uint32_t g_gpiobase[STM32_NGPIO]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 91d78295bb8..625e7eb2a5f 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -46,7 +46,7 @@ #ifdef CONFIG_RPTUN # ifdef CONFIG_STM32H7_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE -# define STM32_SHMEM_SIZE STM32H7_SRAM3_SIZE +# define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else # error missing shmem MPU configuration # endif diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 131be78c428..43208d091f9 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -42,7 +42,7 @@ #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ !defined(CONFIG_STM32H7_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ - enabled. Enable STM32H7_HSI48 + enabled. Enable STM32_HSI48 #endif #if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 414e6c5dbdd..cfddcb3be49 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -135,9 +135,9 @@ # warning "Large Non-DMA transfer may result in RX overrun failures" #elif defined(CONFIG_STM32H7_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE -# define SRAM123_END (SRAM123_START + STM32H7_SRAM123_SIZE) +# define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE -# define SRAM4_END (SRAM4_START + STM32H7_SRAM4_SIZE) +# define SRAM4_END (SRAM4_START + STM32_SRAM4_SIZE) #endif #if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 7860667a245..e7442fe452c 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -65,7 +65,7 @@ /* Total number of possible serial devices */ -#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART) +#define STM32_NSERIAL (STM32_NUSART + STM32_NUART) /* DMA configuration */ @@ -1952,7 +1952,7 @@ static void up_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; @@ -3761,7 +3761,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32H7_NUSART + STM32H7_NUART; n++) + for (n = 0; n < STM32_NUSART + STM32_NUART; n++) { struct up_dev_s *priv = g_uart_devs[n]; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index 92234cb4c45..ea171109805 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -40,29 +40,29 @@ * device. */ -#if STM32H7_NUART < 4 +#if STM32_NUART < 4 # undef CONFIG_STM32H7_UART8 #endif -#if STM32H7_NUART < 3 +#if STM32_NUART < 3 # undef CONFIG_STM32H7_UART7 #endif -#if STM32H7_NUART < 2 +#if STM32_NUART < 2 # undef CONFIG_STM32H7_UART5 #endif -#if STM32H7_NUART < 1 +#if STM32_NUART < 1 # undef CONFIG_STM32H7_UART4 #endif -#if STM32H7_NUSART < 4 +#if STM32_NUSART < 4 # undef CONFIG_STM32H7_USART6 #endif -#if STM32H7_NUSART < 3 +#if STM32_NUSART < 3 # undef CONFIG_STM32H7_USART3 #endif -#if STM32H7_NUSART < 2 +#if STM32_NUSART < 2 # undef CONFIG_STM32H7_USART2 #endif -#if STM32H7_NUSART < 1 +#if STM32_NUSART < 1 # undef CONFIG_STM32H7_USART1 #endif diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index a1ce272975b..5fb2cae9f94 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -408,36 +408,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 2a032086236..481183e8ea5 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -383,36 +383,36 @@ static inline void rcc_enableahb4(void) /* Enable GPIO, GPIOB, ... GPIOK */ -#if STM32H7_NGPIO > 0 +#if STM32_NGPIO > 0 regval |= (RCC_AHB4ENR_GPIOAEN -#if STM32H7_NGPIO > 1 +#if STM32_NGPIO > 1 | RCC_AHB4ENR_GPIOBEN #endif -#if STM32H7_NGPIO > 2 +#if STM32_NGPIO > 2 | RCC_AHB4ENR_GPIOCEN #endif -#if STM32H7_NGPIO > 3 +#if STM32_NGPIO > 3 | RCC_AHB4ENR_GPIODEN #endif -#if STM32H7_NGPIO > 4 +#if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif -#if STM32H7_NGPIO > 7 +#if STM32_NGPIO > 7 | RCC_AHB4ENR_GPIOHEN #endif -#if STM32H7_NGPIO > 8 +#if STM32_NGPIO > 8 | RCC_AHB4ENR_GPIOIEN #endif -#if STM32H7_NGPIO > 9 +#if STM32_NGPIO > 9 | RCC_AHB4ENR_GPIOJEN #endif -#if STM32H7_NGPIO > 10 +#if STM32_NGPIO > 10 | RCC_AHB4ENR_GPIOKEN #endif ); From feb24082bd9e86af21265ef5fbddb93bdd77a51d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 051/268] !arch/stm32l4: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32L4 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32l4/chip.h | 416 ++++---- arch/arm/include/stm32l4/irq.h | 30 +- arch/arm/include/stm32l4/stm32l4x3xx_irq.h | 170 +-- arch/arm/include/stm32l4/stm32l4x5xx_irq.h | 178 ++-- arch/arm/include/stm32l4/stm32l4x6xx_irq.h | 198 ++-- arch/arm/include/stm32l4/stm32l4xrxx_irq.h | 198 ++-- arch/arm/src/stm32l4/chip.h | 2 +- arch/arm/src/stm32l4/hardware/stm32l4_adc.h | 240 ++--- arch/arm/src/stm32l4/hardware/stm32l4_can.h | 174 ++-- arch/arm/src/stm32l4/hardware/stm32l4_comp.h | 16 +- arch/arm/src/stm32l4/hardware/stm32l4_crs.h | 16 +- arch/arm/src/stm32l4/hardware/stm32l4_dac.h | 80 +- arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h | 182 ++-- arch/arm/src/stm32l4/hardware/stm32l4_exti.h | 116 +-- arch/arm/src/stm32l4/hardware/stm32l4_flash.h | 96 +- arch/arm/src/stm32l4/hardware/stm32l4_gpio.h | 258 ++--- arch/arm/src/stm32l4/hardware/stm32l4_i2c.h | 118 +-- arch/arm/src/stm32l4/hardware/stm32l4_lptim.h | 48 +- .../src/stm32l4/hardware/stm32l4_memorymap.h | 264 ++--- arch/arm/src/stm32l4/hardware/stm32l4_pwr.h | 104 +- arch/arm/src/stm32l4/hardware/stm32l4_qspi.h | 56 +- arch/arm/src/stm32l4/hardware/stm32l4_rng.h | 12 +- arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h | 210 ++-- arch/arm/src/stm32l4/hardware/stm32l4_sai.h | 98 +- arch/arm/src/stm32l4/hardware/stm32l4_spi.h | 64 +- arch/arm/src/stm32l4/hardware/stm32l4_tim.h | 492 ++++----- arch/arm/src/stm32l4/hardware/stm32l4_uart.h | 142 +-- .../arm/src/stm32l4/hardware/stm32l4_usbdev.h | 92 +- arch/arm/src/stm32l4/hardware/stm32l4_wdg.h | 32 +- .../src/stm32l4/hardware/stm32l4x3xx_dma.h | 432 ++++---- .../stm32l4/hardware/stm32l4x3xx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4x3xx_rcc.h | 128 +-- .../src/stm32l4/hardware/stm32l4x3xx_syscfg.h | 44 +- .../src/stm32l4/hardware/stm32l4x5xx_dma.h | 476 ++++----- .../stm32l4/hardware/stm32l4x5xx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4x5xx_otgfs.h | 240 ++--- .../src/stm32l4/hardware/stm32l4x5xx_rcc.h | 120 +-- .../src/stm32l4/hardware/stm32l4x5xx_syscfg.h | 44 +- .../src/stm32l4/hardware/stm32l4x6xx_dma.h | 494 ++++----- .../stm32l4/hardware/stm32l4x6xx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4x6xx_otgfs.h | 238 ++--- .../src/stm32l4/hardware/stm32l4x6xx_rcc.h | 128 +-- .../src/stm32l4/hardware/stm32l4x6xx_syscfg.h | 48 +- .../src/stm32l4/hardware/stm32l4xrxx_dma.h | 228 ++-- .../src/stm32l4/hardware/stm32l4xrxx_dmamux.h | 103 +- .../stm32l4/hardware/stm32l4xrxx_firewall.h | 28 +- .../src/stm32l4/hardware/stm32l4xrxx_rcc.h | 128 +-- .../src/stm32l4/hardware/stm32l4xrxx_syscfg.h | 48 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 98 +- arch/arm/src/stm32l4/stm32l4_adc.c | 238 ++--- arch/arm/src/stm32l4/stm32l4_adc.h | 90 +- arch/arm/src/stm32l4/stm32l4_allocateheap.c | 14 +- arch/arm/src/stm32l4/stm32l4_can.c | 230 ++-- arch/arm/src/stm32l4/stm32l4_can.h | 2 +- arch/arm/src/stm32l4/stm32l4_comp.c | 82 +- arch/arm/src/stm32l4/stm32l4_comp.h | 74 +- arch/arm/src/stm32l4/stm32l4_dac.c | 102 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 156 +-- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 28 +- arch/arm/src/stm32l4/stm32l4_dfumode.c | 62 +- arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 52 +- arch/arm/src/stm32l4/stm32l4_exti_alarm.c | 16 +- arch/arm/src/stm32l4/stm32l4_exti_comp.c | 24 +- arch/arm/src/stm32l4/stm32l4_exti_gpio.c | 30 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.c | 16 +- arch/arm/src/stm32l4/stm32l4_exti_wakeup.c | 16 +- arch/arm/src/stm32l4/stm32l4_firewall.c | 24 +- arch/arm/src/stm32l4/stm32l4_flash.c | 90 +- arch/arm/src/stm32l4/stm32l4_freerun.c | 28 +- arch/arm/src/stm32l4/stm32l4_gpio.c | 74 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 2 +- arch/arm/src/stm32l4/stm32l4_hsi48.c | 26 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 116 +-- arch/arm/src/stm32l4/stm32l4_irq.c | 50 +- arch/arm/src/stm32l4/stm32l4_iwdg.c | 20 +- arch/arm/src/stm32l4/stm32l4_lowputc.c | 240 ++--- arch/arm/src/stm32l4/stm32l4_lptim.c | 128 +-- arch/arm/src/stm32l4/stm32l4_lptim.h | 58 +- arch/arm/src/stm32l4/stm32l4_lse.c | 8 +- arch/arm/src/stm32l4/stm32l4_lsi.c | 6 +- arch/arm/src/stm32l4/stm32l4_oneshot.c | 28 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 2 +- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 982 +++++++++--------- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 326 +++--- arch/arm/src/stm32l4/stm32l4_pmlpr.c | 14 +- arch/arm/src/stm32l4/stm32l4_pmstandby.c | 6 +- arch/arm/src/stm32l4/stm32l4_pmstop.c | 8 +- arch/arm/src/stm32l4/stm32l4_pulsecount.c | 134 +-- arch/arm/src/stm32l4/stm32l4_pwm.c | 440 ++++---- arch/arm/src/stm32l4/stm32l4_pwm.h | 72 +- arch/arm/src/stm32l4/stm32l4_pwr.c | 48 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 222 ++-- arch/arm/src/stm32l4/stm32l4_qspi.c | 240 ++--- arch/arm/src/stm32l4/stm32l4_rcc.c | 16 +- arch/arm/src/stm32l4/stm32l4_rcc.h | 4 +- arch/arm/src/stm32l4/stm32l4_rng.c | 28 +- arch/arm/src/stm32l4/stm32l4_rtc.c | 196 ++-- arch/arm/src/stm32l4/stm32l4_rtc.h | 6 +- arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 4 +- arch/arm/src/stm32l4/stm32l4_sai.c | 54 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 4 +- arch/arm/src/stm32l4/stm32l4_serial.c | 194 ++-- arch/arm/src/stm32l4/stm32l4_spi.c | 80 +- arch/arm/src/stm32l4/stm32l4_start.c | 4 +- arch/arm/src/stm32l4/stm32l4_tim.c | 402 +++---- arch/arm/src/stm32l4/stm32l4_tim.h | 86 +- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 82 +- arch/arm/src/stm32l4/stm32l4_timerisr.c | 8 +- arch/arm/src/stm32l4/stm32l4_uid.c | 6 +- arch/arm/src/stm32l4/stm32l4_usbdev.c | 644 ++++++------ arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 232 ++--- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 216 ++-- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 154 +-- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 262 ++--- arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 180 ++-- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 240 ++--- .../include/b-l475e-iot01a_clock.h | 302 +++--- .../arm/stm32l4/nucleo-l432kc/include/board.h | 2 +- .../nucleo-l432kc/include/nucleo-l432kc.h | 280 ++--- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 18 +- .../nucleo-l452re/include/nucleo-l452re.h | 296 +++--- .../stm32l4/nucleo-l452re/src/nucleo-l452re.h | 6 +- .../nucleo-l476rg/include/nucleo-l476rg.h | 306 +++--- .../arm/stm32l4/nucleo-l496zg/include/board.h | 300 +++--- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 6 +- .../stm32l4/steval-stlcs01v1/include/board.h | 136 +-- .../include/stm32l476-mdk-clocking.h | 190 ++-- .../stm32l476-mdk/src/stm32_clockconfig.c | 78 +- .../include/stm32l476vg-disco-clocking.h | 268 ++--- .../stm32l476vg-disco/src/stm32_clockconfig.c | 78 +- .../include/stm32l4r9ai-disco-clocking.h | 286 ++--- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 78 +- 132 files changed, 8786 insertions(+), 8781 deletions(-) diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index febd84d6fac..79b07b9e1c9 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -66,260 +66,260 @@ */ #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -# define STM32L4_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \ defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ #elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ -# define STM32L4_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L4 chip" #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 0 /* No QuadSPI1 */ -# define STM32L4_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 0 /* No SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ -# define STM32L4_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4XR */ #if defined(CONFIG_STM32L4_STM32L4X5) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 3 /* I2C1-3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4X5 */ #if defined(CONFIG_STM32L4_STM32L4X6) -# define STM32L4_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L4_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L4_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 2 /* UART 4-5 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NI2C 4 /* I2C1-4 */ +# define STM32_NI2C 4 /* I2C1-4 */ #else -# define STM32L4_NI2C 3 /* I2C1-3 */ +# define STM32_NI2C 3 /* I2C1-3 */ #endif -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L4_NUSBFS 0 /* No USB FS */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NCAN 2 /* CAN1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ #else -# define STM32L4_NCAN 1 /* CAN1 */ +# define STM32_NCAN 1 /* CAN1 */ #endif -# define STM32L4_NSAI 2 /* SAI1-2 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ #if defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ +# define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ #else -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ #endif -# define STM32L4_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NADC 3 /* 12-bit ADC1-3, up to 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L4X6 */ #if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ defined(CONFIG_STM32L4_STM32L462XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 1 /* UART 4 */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-3 */ -# define STM32L4_NI2C 4 /* I2C1-4 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 3 /* 16-bit general timers TIM3, TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 1 /* UART 4 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ #if defined(CONFIG_STM32L4_STM32L451XX) -# define STM32L4_NUSBFS 0 /* No USB FS */ +# define STM32_NUSBFS 0 /* No USB FS */ #else -# define STM32L4_NUSBFS 1 /* USB FS */ +# define STM32_NUSBFS 1 /* USB FS */ #endif -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ #if defined(CONFIG_STM32L4_HAVE_SDMMC1) -# define STM32L4_NSDMMC 1 /* SDMMC interface */ +# define STM32_NSDMMC 1 /* SDMMC interface */ #else -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ #endif -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ -# define STM32L4_NDAC 1 /* 12-bit DAC1 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 16 channels (10 in CE,CV) */ +# define STM32_NDAC 1 /* 12-bit DAC1 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L451XX */ #if defined(CONFIG_STM32L4_STM32L432XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 2 /* USART 1-2 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 2 /* SPI1, SPI3 */ -# define STM32L4_NI2C 2 /* I2C1, I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 2 /* SPI1, SPI3 */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L432XX */ #if defined(CONFIG_STM32L4_STM32L433XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 1 /* SWPMI1 */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 1 /* CAN1 */ -# define STM32L4_NSAI 1 /* SAI1 */ -# define STM32L4_NSDMMC 1 /* SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 1 /* 12-bit ADC1, 10 channels */ -# define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 1 /* SWPMI1 */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 1 /* SAI1 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, 10 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L433XX */ #if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) -# define STM32L4_NFSMC 0 /* No FSMC memory controller */ -# define STM32L4_NATIM 1 /* One advanced timer TIM1 */ -# define STM32L4_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32L4_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ -# define STM32L4_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32L4_NBTIM 1 /* One basic timer, TIM6 */ -# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L4_NRNG 1 /* Random number generator (RNG) */ -# define STM32L4_NUART 0 /* No UART */ -# define STM32L4_NUSART 3 /* USART 1-3 */ -# define STM32L4_NLPUART 1 /* LPUART 1 */ -# define STM32L4_QSPI 1 /* QuadSPI1 */ -# define STM32L4_NSPI 3 /* SPI1-SPI3 */ -# define STM32L4_NI2C 3 /* I2C1-I2C3 */ -# define STM32L4_NSWPMI 0 /* No SWPMI */ -# define STM32L4_NUSBOTGFS 0 /* No USB OTG FS */ -# define STM32L4_NUSBFS 1 /* USB FS */ -# define STM32L4_NCAN 0 /* No CAN */ -# define STM32L4_NSAI 0 /* No SAI */ -# define STM32L4_NSDMMC 0 /* No SDMMC interface */ -# define STM32L4_NDMA 2 /* DMA1-2 */ -# define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 2 /* 12-bit ADC1-2, 10 channels */ -# define STM32L4_NDAC 0 /* No DAC */ -# define STM32L4_NCRC 1 /* CRC */ -# define STM32L4_NCOMP 2 /* Comparators */ -# define STM32L4_NOPAMP 1 /* Operational Amplifiers */ +# define STM32_NFSMC 0 /* No FSMC memory controller */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM15-16 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 1 /* One basic timer, TIM6 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 0 /* No UART */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 1 /* QuadSPI1 */ +# define STM32_NSPI 3 /* SPI1-SPI3 */ +# define STM32_NI2C 3 /* I2C1-I2C3 */ +# define STM32_NSWPMI 0 /* No SWPMI */ +# define STM32_NUSBOTGFS 0 /* No USB OTG FS */ +# define STM32_NUSBFS 1 /* USB FS */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSAI 0 /* No SAI */ +# define STM32_NSDMMC 0 /* No SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 2 /* 12-bit ADC1-2, 10 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 1 /* Operational Amplifiers */ #endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index a17c1567157..528204f8969 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L4_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L4_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L4_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L4_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L4_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L4_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L4_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L4_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 1b3b5b27945..2d6e4d570f2 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -52,99 +52,99 @@ * */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ - /* Reserved 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ - /* Reserved 42-48 */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ - /* Reserved 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ - /* Reserved 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ - /* Reserved 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ - /* Reserved 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ + /* Reserved 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ + /* Reserved 42-48 */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ + /* Reserved 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ + /* Reserved 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ + /* Reserved 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ + /* Reserved 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 82) /* 82: CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ #if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_IRQ_NEXTINTS 85 +# define STM32_IRQ_NEXTINTS 85 #else # error "Unsupported STM32L4 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h index 3c0c8f49842..e21faaae230 100644 --- a/arch/arm/include/stm32l4/stm32l4x5xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x5xx_irq.h @@ -48,99 +48,99 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */ -#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST + 78) /* 78: Reserved */ +#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST + 79) /* 79: Reserved */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_NEXTINTS 82 +#define STM32_IRQ_NEXTINTS 82 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h index 039cc81d92a..7e937ff34c7 100644 --- a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h @@ -48,117 +48,117 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ -#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ +#define STM32_IRQ_ADC3 (STM32_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_SWPMI1 (STM32_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_LCD (STM32_IRQ_FIRST + 78) /* 78: LCD global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ /* STM32L496xx/4A6xx only: */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ -#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ -#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ -#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ -#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ +#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */ +#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */ +#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */ +#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ #if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) -# define STM32L4_IRQ_NEXTINTS 82 +# define STM32_IRQ_NEXTINTS 82 #elif defined(CONFIG_STM32L4_STM32L496XX) -# define STM32L4_IRQ_NEXTINTS 91 +# define STM32_IRQ_NEXTINTS 91 #else # error "Unsupported STM32L4 chip" #endif /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h index 803bf8dc012..ec9f7db1f95 100644 --- a/arch/arm/include/stm32l4/stm32l4xrxx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4xrxx_irq.h @@ -48,109 +48,109 @@ * External interrupts (vectors >= 16) */ -#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ -#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ -#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ -#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ -#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ -#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ -#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ -#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ -#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ -#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ -#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ -#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ -#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ -#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ -#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ -#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ -#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ -#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ -#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ -#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ -#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ -#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ -#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ -#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ -#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ -#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ - /* Reserved 47: ADC3 global interrupt */ -#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ -#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ -#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ -#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ -#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ -#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ -#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ -#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ -#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ -#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ -#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ -#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ -#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ -#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ -#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ -#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ -#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ -#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ -#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ -#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ -#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ -#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ -#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ -#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ -#define STM32L4_IRQ_OCTOSPI1 (STM32L4_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ -#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ -#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ -#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ -#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ -#define STM32L4_IRQ_OCTOSPI2 (STM32L4_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ -#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */ -#define STM32L4_IRQ_DSIHSOT (STM32L4_IRQ_FIRST + 78) /* 78: DSI global interrupt */ -#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ -#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */ -#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */ -#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ -#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ -#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ - /* Reserved 86-89: CAN2 */ -#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ -#define STM32L4_IRQ_LCD_TFT (STM32L4_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ -#define STM32L4_IRQ_LCD_TFT_ER (STM32L4_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ -#define STM32L4_IRQ_GFXMMU (STM32L4_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ -#define STM32L4_IRQ_DMAMUX1_OVR (STM32L4_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */ +#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */ +#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */ +#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */ +#define STM32_IRQ_DFSDM3 (STM32_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */ +#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */ +#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */ +#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */ +#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */ + /* Reserved 47: ADC3 global interrupt */ +#define STM32_IRQ_FSMC (STM32_IRQ_FIRST + 48) /* 48: FSMC global interrupt */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DFSDM0 (STM32_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */ +#define STM32_IRQ_DFSDM1 (STM32_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/ +#define STM32_IRQ_DFSDM2 (STM32_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */ +#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 71) /* 71: OCTOSPI1 global interrupt */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */ +#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 77) /* 77: TSC global interrupt */ +#define STM32_IRQ_DSIHSOT (STM32_IRQ_FIRST + 78) /* 78: DSI global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */ +#define STM32_IRQ_HASH_CRS (STM32_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */ +#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ +#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ +#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 85) /* 85: DCMI global interrupt */ + /* Reserved 86-89: CAN2 */ +#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ +#define STM32_IRQ_LCD_TFT (STM32_IRQ_FIRST + 91) /* 91: LTDC global interrupt */ +#define STM32_IRQ_LCD_TFT_ER (STM32_IRQ_FIRST + 92) /* 92: LTDC global error interrupt */ +#define STM32_IRQ_GFXMMU (STM32_IRQ_FIRST + 93) /* 93: GFXMMU global error interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 94) /* 94: DMAMUX overrun interrupt */ -#define STM32L4_IRQ_NEXTINTS 95 +#define STM32_IRQ_NEXTINTS 95 /* EXTI interrupts (Do not use IRQ numbers) */ -#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h index fb3a0d22027..b1b27fca0dc 100644 --- a/arch/arm/src/stm32l4/chip.h +++ b/arch/arm/src/stm32l4/chip.h @@ -49,7 +49,7 @@ * arch/stm32l4/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32L4 */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index c78b9f598df..f030bc56d98 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -41,136 +41,136 @@ * offset 0x0100 for slave. */ -#define STM32L4_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ -#define STM32L4_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ -#define STM32L4_ADC_CR_OFFSET 0x0008 /* ADC control register */ -#define STM32L4_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ -#define STM32L4_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ -#define STM32L4_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ -#define STM32L4_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ -#define STM32L4_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ -#define STM32L4_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ -#define STM32L4_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ -#define STM32L4_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ -#define STM32L4_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ -#define STM32L4_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ -#define STM32L4_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ -#define STM32L4_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ -#define STM32L4_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ -#define STM32L4_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ -#define STM32L4_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ -#define STM32L4_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ -#define STM32L4_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ -#define STM32L4_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ -#define STM32L4_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ -#define STM32L4_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ -#define STM32L4_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ -#define STM32L4_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ -#define STM32L4_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ -#define STM32L4_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ -#define STM32L4_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ +#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */ +#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */ +#define STM32_ADC_CR_OFFSET 0x0008 /* ADC control register */ +#define STM32_ADC_CFGR_OFFSET 0x000c /* ADC configuration register */ +#define STM32_ADC_CFGR2_OFFSET 0x0010 /* ADC configuration register 2 */ +#define STM32_ADC_SMPR1_OFFSET 0x0014 /* ADC sample time register 1 */ +#define STM32_ADC_SMPR2_OFFSET 0x0018 /* ADC sample time register 2 */ +#define STM32_ADC_TR1_OFFSET 0x0020 /* ADC watchdog threshold register 1 */ +#define STM32_ADC_TR2_OFFSET 0x0024 /* ADC watchdog threshold register 2 */ +#define STM32_ADC_TR3_OFFSET 0x0028 /* ADC watchdog threshold register 3 */ +#define STM32_ADC_SQR1_OFFSET 0x0030 /* ADC regular sequence register 1 */ +#define STM32_ADC_SQR2_OFFSET 0x0034 /* ADC regular sequence register 2 */ +#define STM32_ADC_SQR3_OFFSET 0x0038 /* ADC regular sequence register 3 */ +#define STM32_ADC_SQR4_OFFSET 0x003c /* ADC regular sequence register 4 */ +#define STM32_ADC_DR_OFFSET 0x0040 /* ADC regular data register */ +#define STM32_ADC_JSQR_OFFSET 0x004c /* ADC injected sequence register */ +#define STM32_ADC_OFR1_OFFSET 0x0060 /* ADC offset register 1 */ +#define STM32_ADC_OFR2_OFFSET 0x0064 /* ADC offset register 2 */ +#define STM32_ADC_OFR3_OFFSET 0x0068 /* ADC offset register 3 */ +#define STM32_ADC_OFR4_OFFSET 0x006c /* ADC offset register 4 */ +#define STM32_ADC_JDR1_OFFSET 0x0080 /* ADC injected data register 1 */ +#define STM32_ADC_JDR2_OFFSET 0x0084 /* ADC injected data register 2 */ +#define STM32_ADC_JDR3_OFFSET 0x0088 /* ADC injected data register 3 */ +#define STM32_ADC_JDR4_OFFSET 0x008c /* ADC injected data register 4 */ +#define STM32_ADC_AWD2CR_OFFSET 0x00a0 /* ADC analog watchdog 2 configuration register */ +#define STM32_ADC_AWD3CR_OFFSET 0x00a4 /* ADC analog watchdog 3 configuration register */ +#define STM32_ADC_DIFSEL_OFFSET 0x00b0 /* ADC differential mode selection register 2 */ +#define STM32_ADC_CALFACT_OFFSET 0x00b4 /* ADC calibration factors */ /* Master and Slave ADC Common Registers */ -#define STM32L4_ADC_CSR_OFFSET 0x0000 /* Common status register */ -#define STM32L4_ADC_CCR_OFFSET 0x0008 /* Common control register */ +#define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ +#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ +# define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_ADC1_ISR (STM32L4_ADC1_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC1_IER (STM32L4_ADC1_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC1_CR (STM32L4_ADC1_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC1_CFGR (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC1_CFGR2 (STM32L4_ADC1_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC1_SMPR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC1_SMPR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC1_TR1 (STM32L4_ADC1_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC1_TR2 (STM32L4_ADC1_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC1_TR3 (STM32L4_ADC1_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC1_SQR1 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC1_SQR2 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC1_SQR3 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC1_SQR4 (STM32L4_ADC1_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC1_DR (STM32L4_ADC1_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC1_JSQR (STM32L4_ADC1_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC1_OFR1 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC1_OFR2 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC1_OFR3 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC1_OFR4 (STM32L4_ADC1_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC1_JDR1 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC1_JDR2 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC1_JDR3 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC1_JDR4 (STM32L4_ADC1_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC1_AWD2CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC1_AWD3CR (STM32L4_ADC1_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC1_DIFSEL (STM32L4_ADC1_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC1_CALFACT (STM32L4_ADC1_BASE+STM32L4_ADC_CALFACT_OFFSET) +#define STM32_ADC1_ISR (STM32_ADC1_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC1_IER (STM32_ADC1_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC1_CR (STM32_ADC1_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC1_CFGR (STM32_ADC1_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC1_CFGR2 (STM32_ADC1_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC1_SMPR1 (STM32_ADC1_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC1_SMPR2 (STM32_ADC1_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC1_TR1 (STM32_ADC1_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC1_TR2 (STM32_ADC1_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC1_TR3 (STM32_ADC1_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC1_SQR1 (STM32_ADC1_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC1_SQR2 (STM32_ADC1_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC1_SQR3 (STM32_ADC1_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC1_SQR4 (STM32_ADC1_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC1_DR (STM32_ADC1_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC1_JSQR (STM32_ADC1_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC1_OFR1 (STM32_ADC1_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC1_OFR2 (STM32_ADC1_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC1_OFR3 (STM32_ADC1_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC1_OFR4 (STM32_ADC1_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC1_JDR1 (STM32_ADC1_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC1_JDR2 (STM32_ADC1_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC1_JDR3 (STM32_ADC1_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC1_JDR4 (STM32_ADC1_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC1_AWD2CR (STM32_ADC1_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC1_AWD3CR (STM32_ADC1_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC1_DIFSEL (STM32_ADC1_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC1_CALFACT (STM32_ADC1_BASE+STM32_ADC_CALFACT_OFFSET) -#define STM32L4_ADC2_ISR (STM32L4_ADC2_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC2_IER (STM32L4_ADC2_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC2_CR (STM32L4_ADC2_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC2_CFGR (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC2_CFGR2 (STM32L4_ADC2_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC2_SMPR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC2_SMPR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC2_TR1 (STM32L4_ADC2_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC2_TR2 (STM32L4_ADC2_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC2_TR3 (STM32L4_ADC2_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC2_SQR1 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC2_SQR2 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC2_SQR3 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC2_SQR4 (STM32L4_ADC2_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC2_DR (STM32L4_ADC2_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC2_JSQR (STM32L4_ADC2_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC2_OFR1 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC2_OFR2 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC2_OFR3 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC2_OFR4 (STM32L4_ADC2_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC2_JDR1 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC2_JDR2 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC2_JDR3 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC2_JDR4 (STM32L4_ADC2_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC2_AWD2CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC2_AWD3CR (STM32L4_ADC2_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC2_DIFSEL (STM32L4_ADC2_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC2_CALFACT (STM32L4_ADC2_BASE+STM32L4_ADC_CALFACT_OFFSET) +#define STM32_ADC2_ISR (STM32_ADC2_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC2_IER (STM32_ADC2_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC2_CR (STM32_ADC2_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC2_CFGR (STM32_ADC2_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC2_CFGR2 (STM32_ADC2_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC2_SMPR1 (STM32_ADC2_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC2_SMPR2 (STM32_ADC2_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC2_TR1 (STM32_ADC2_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC2_TR2 (STM32_ADC2_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC2_TR3 (STM32_ADC2_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC2_SQR1 (STM32_ADC2_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC2_SQR2 (STM32_ADC2_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC2_SQR3 (STM32_ADC2_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC2_SQR4 (STM32_ADC2_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC2_DR (STM32_ADC2_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC2_JSQR (STM32_ADC2_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC2_OFR1 (STM32_ADC2_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC2_OFR2 (STM32_ADC2_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC2_OFR3 (STM32_ADC2_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC2_OFR4 (STM32_ADC2_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC2_JDR1 (STM32_ADC2_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC2_JDR2 (STM32_ADC2_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC2_JDR3 (STM32_ADC2_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC2_JDR4 (STM32_ADC2_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC2_AWD2CR (STM32_ADC2_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC2_AWD3CR (STM32_ADC2_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC2_DIFSEL (STM32_ADC2_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC2_CALFACT (STM32_ADC2_BASE+STM32_ADC_CALFACT_OFFSET) -#define STM32L4_ADC3_ISR (STM32L4_ADC3_BASE+STM32L4_ADC_ISR_OFFSET) -#define STM32L4_ADC3_IER (STM32L4_ADC3_BASE+STM32L4_ADC_IER_OFFSET) -#define STM32L4_ADC3_CR (STM32L4_ADC3_BASE+STM32L4_ADC_CR_OFFSET) -#define STM32L4_ADC3_CFGR (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR_OFFSET) -#define STM32L4_ADC3_CFGR2 (STM32L4_ADC3_BASE+STM32L4_ADC_CFGR2_OFFSET) -#define STM32L4_ADC3_SMPR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR1_OFFSET) -#define STM32L4_ADC3_SMPR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SMPR2_OFFSET) -#define STM32L4_ADC3_TR1 (STM32L4_ADC3_BASE+STM32L4_ADC_TR1_OFFSET) -#define STM32L4_ADC3_TR2 (STM32L4_ADC3_BASE+STM32L4_ADC_TR2_OFFSET) -#define STM32L4_ADC3_TR3 (STM32L4_ADC3_BASE+STM32L4_ADC_TR3_OFFSET) -#define STM32L4_ADC3_SQR1 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR1_OFFSET) -#define STM32L4_ADC3_SQR2 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR2_OFFSET) -#define STM32L4_ADC3_SQR3 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR3_OFFSET) -#define STM32L4_ADC3_SQR4 (STM32L4_ADC3_BASE+STM32L4_ADC_SQR4_OFFSET) -#define STM32L4_ADC3_DR (STM32L4_ADC3_BASE+STM32L4_ADC_DR_OFFSET) -#define STM32L4_ADC3_JSQR (STM32L4_ADC3_BASE+STM32L4_ADC_JSQR_OFFSET) -#define STM32L4_ADC3_OFR1 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR1_OFFSET) -#define STM32L4_ADC3_OFR2 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR2_OFFSET) -#define STM32L4_ADC3_OFR3 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR3_OFFSET) -#define STM32L4_ADC3_OFR4 (STM32L4_ADC3_BASE+STM32L4_ADC_OFR4_OFFSET) -#define STM32L4_ADC3_JDR1 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR1_OFFSET) -#define STM32L4_ADC3_JDR2 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR2_OFFSET) -#define STM32L4_ADC3_JDR3 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR3_OFFSET) -#define STM32L4_ADC3_JDR4 (STM32L4_ADC3_BASE+STM32L4_ADC_JDR4_OFFSET) -#define STM32L4_ADC3_AWD2CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD2CR_OFFSET) -#define STM32L4_ADC3_AWD3CR (STM32L4_ADC3_BASE+STM32L4_ADC_AWD3CR_OFFSET) -#define STM32L4_ADC3_DIFSEL (STM32L4_ADC3_BASE+STM32L4_ADC_DIFSEL_OFFSET) -#define STM32L4_ADC3_CALFACT (STM32L4_ADC3_BASE+STM32L4_ADC_CALFACT_OFFSET) +#define STM32_ADC3_ISR (STM32_ADC3_BASE+STM32_ADC_ISR_OFFSET) +#define STM32_ADC3_IER (STM32_ADC3_BASE+STM32_ADC_IER_OFFSET) +#define STM32_ADC3_CR (STM32_ADC3_BASE+STM32_ADC_CR_OFFSET) +#define STM32_ADC3_CFGR (STM32_ADC3_BASE+STM32_ADC_CFGR_OFFSET) +#define STM32_ADC3_CFGR2 (STM32_ADC3_BASE+STM32_ADC_CFGR2_OFFSET) +#define STM32_ADC3_SMPR1 (STM32_ADC3_BASE+STM32_ADC_SMPR1_OFFSET) +#define STM32_ADC3_SMPR2 (STM32_ADC3_BASE+STM32_ADC_SMPR2_OFFSET) +#define STM32_ADC3_TR1 (STM32_ADC3_BASE+STM32_ADC_TR1_OFFSET) +#define STM32_ADC3_TR2 (STM32_ADC3_BASE+STM32_ADC_TR2_OFFSET) +#define STM32_ADC3_TR3 (STM32_ADC3_BASE+STM32_ADC_TR3_OFFSET) +#define STM32_ADC3_SQR1 (STM32_ADC3_BASE+STM32_ADC_SQR1_OFFSET) +#define STM32_ADC3_SQR2 (STM32_ADC3_BASE+STM32_ADC_SQR2_OFFSET) +#define STM32_ADC3_SQR3 (STM32_ADC3_BASE+STM32_ADC_SQR3_OFFSET) +#define STM32_ADC3_SQR4 (STM32_ADC3_BASE+STM32_ADC_SQR4_OFFSET) +#define STM32_ADC3_DR (STM32_ADC3_BASE+STM32_ADC_DR_OFFSET) +#define STM32_ADC3_JSQR (STM32_ADC3_BASE+STM32_ADC_JSQR_OFFSET) +#define STM32_ADC3_OFR1 (STM32_ADC3_BASE+STM32_ADC_OFR1_OFFSET) +#define STM32_ADC3_OFR2 (STM32_ADC3_BASE+STM32_ADC_OFR2_OFFSET) +#define STM32_ADC3_OFR3 (STM32_ADC3_BASE+STM32_ADC_OFR3_OFFSET) +#define STM32_ADC3_OFR4 (STM32_ADC3_BASE+STM32_ADC_OFR4_OFFSET) +#define STM32_ADC3_JDR1 (STM32_ADC3_BASE+STM32_ADC_JDR1_OFFSET) +#define STM32_ADC3_JDR2 (STM32_ADC3_BASE+STM32_ADC_JDR2_OFFSET) +#define STM32_ADC3_JDR3 (STM32_ADC3_BASE+STM32_ADC_JDR3_OFFSET) +#define STM32_ADC3_JDR4 (STM32_ADC3_BASE+STM32_ADC_JDR4_OFFSET) +#define STM32_ADC3_AWD2CR (STM32_ADC3_BASE+STM32_ADC_AWD2CR_OFFSET) +#define STM32_ADC3_AWD3CR (STM32_ADC3_BASE+STM32_ADC_AWD3CR_OFFSET) +#define STM32_ADC3_DIFSEL (STM32_ADC3_BASE+STM32_ADC_DIFSEL_OFFSET) +#define STM32_ADC3_CALFACT (STM32_ADC3_BASE+STM32_ADC_CALFACT_OFFSET) -#define STM32L4_ADC_CSR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CSR_OFFSET) -#define STM32L4_ADC_CCR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CCR_OFFSET) +#define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) +#define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_ADC_CDR (STM32L4_ADCCMN_BASE+STM32L4_ADC_CDR_OFFSET) +# define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ @@ -286,10 +286,12 @@ # define ADC_CFGR2_OVSR_64X (5 << ADC_CFGR2_OVSR_SHIFT) /* 64X oversampling */ # define ADC_CFGR2_OVSR_128X (6 << ADC_CFGR2_OVSR_SHIFT) /* 128X oversampling */ # define ADC_CFGR2_OVSR_256X (7 << ADC_CFGR2_OVSR_SHIFT) /* 256X oversampling */ + #define ADC_CFGR2_OVSS_SHIFT (5) /* Bits 5-8: Oversampling shift */ #define ADC_CFGR2_OVSS_MASK (0xf << ADC_CFGR2_OVSS_SHIFT) # define ADC_CFGR2_OVSS(value) ((value) << ADC_CFGR2_OVSS_SHIFT) - /* Value = 0..8 */ + /* Value = 0..8 */ + #define ADC_CFGR2_TROVS (1 << 9) /* Bit 9: Triggered Regular Oversampling */ #define ADC_CFGR2_ROVSM (1 << 10) /* Bit 10: Regular Oversampling mode */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_can.h b/arch/arm/src/stm32l4/hardware/stm32l4_can.h index ac0338cd867..5804564e8e2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_can.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_can.h @@ -54,61 +54,61 @@ /* CAN control and status registers */ -#define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ -#define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ -#define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ -#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) -#define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ -#define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ -#define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ -#define STM32L4_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ -#define STM32L4_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ +#define STM32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define STM32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define STM32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) +#define STM32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define STM32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ +#define STM32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define STM32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define STM32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) -#define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ -#define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ -#define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ +#define STM32_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) +#define STM32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define STM32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define STM32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) -#define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ +#define STM32_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) +#define STM32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define STM32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define STM32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) -#define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ -#define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ -#define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ +#define STM32_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) +#define STM32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define STM32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define STM32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) -#define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ -#define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ -#define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ +#define STM32_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) +#define STM32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define STM32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define STM32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) -#define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ -#define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ +#define STM32_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) +#define STM32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define STM32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) -#define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ -#define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ +#define STM32_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) +#define STM32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define STM32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) -#define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ -#define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ +#define STM32_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) +#define STM32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define STM32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) -#define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ -#define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ +#define STM32_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) +#define STM32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define STM32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ /* CAN filter registers */ -#define STM32L4_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ -#define STM32L4_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ -#define STM32L4_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ -#define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ -#define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ +#define STM32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define STM32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define STM32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define STM32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define STM32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ /* There are 14 filter banks on the device. Each filter bank is * composed of two 32-bit registers, CAN_FiR: @@ -119,63 +119,63 @@ * ... */ -#define STM32L4_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) +#define STM32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) /* Register Addresses *******************************************************/ -#if STM32L4_NCAN > 0 -# define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) -# define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET) -# define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET) -# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m)) -# define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET) -# define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET) -# define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET) -# define STM32L4_CAN1_ESR (STM32L4_CAN1_BASE+STM32L4_CAN_ESR_OFFSET) -# define STM32L4_CAN1_BTR (STM32L4_CAN1_BASE+STM32L4_CAN_BTR_OFFSET) +#if STM32_NCAN > 0 +# define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) +# define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) +# define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) +# define STM32_CAN1_RFR(m) (STM32_CAN1_BASE+STM32_CAN_RFR_OFFSET(m)) +# define STM32_CAN1_RF0R (STM32_CAN1_BASE+STM32_CAN_RF0R_OFFSET) +# define STM32_CAN1_RF1R (STM32_CAN1_BASE+STM32_CAN_RF1R_OFFSET) +# define STM32_CAN1_IER (STM32_CAN1_BASE+STM32_CAN_IER_OFFSET) +# define STM32_CAN1_ESR (STM32_CAN1_BASE+STM32_CAN_ESR_OFFSET) +# define STM32_CAN1_BTR (STM32_CAN1_BASE+STM32_CAN_BTR_OFFSET) -# define STM32L4_CAN1_TIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TIR_OFFSET(m)) -# define STM32L4_CAN1_TI0R (STM32L4_CAN1_BASE+STM32L4_CAN_TI0R_OFFSET) -# define STM32L4_CAN1_TI1R (STM32L4_CAN1_BASE+STM32L4_CAN_TI1R_OFFSET) -# define STM32L4_CAN1_TI2R (STM32L4_CAN1_BASE+STM32L4_CAN_TI2R_OFFSET) +# define STM32_CAN1_TIR(m) (STM32_CAN1_BASE+STM32_CAN_TIR_OFFSET(m)) +# define STM32_CAN1_TI0R (STM32_CAN1_BASE+STM32_CAN_TI0R_OFFSET) +# define STM32_CAN1_TI1R (STM32_CAN1_BASE+STM32_CAN_TI1R_OFFSET) +# define STM32_CAN1_TI2R (STM32_CAN1_BASE+STM32_CAN_TI2R_OFFSET) -# define STM32L4_CAN1_TDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDTR_OFFSET(m)) -# define STM32L4_CAN1_TDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT0R_OFFSET) -# define STM32L4_CAN1_TDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT1R_OFFSET) -# define STM32L4_CAN1_TDT2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDT2R_OFFSET) +# define STM32_CAN1_TDTR(m) (STM32_CAN1_BASE+STM32_CAN_TDTR_OFFSET(m)) +# define STM32_CAN1_TDT0R (STM32_CAN1_BASE+STM32_CAN_TDT0R_OFFSET) +# define STM32_CAN1_TDT1R (STM32_CAN1_BASE+STM32_CAN_TDT1R_OFFSET) +# define STM32_CAN1_TDT2R (STM32_CAN1_BASE+STM32_CAN_TDT2R_OFFSET) -# define STM32L4_CAN1_TDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDLR_OFFSET(m)) -# define STM32L4_CAN1_TDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL0R_OFFSET) -# define STM32L4_CAN1_TDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL1R_OFFSET) -# define STM32L4_CAN1_TDL2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDL2R_OFFSET) +# define STM32_CAN1_TDLR(m) (STM32_CAN1_BASE+STM32_CAN_TDLR_OFFSET(m)) +# define STM32_CAN1_TDL0R (STM32_CAN1_BASE+STM32_CAN_TDL0R_OFFSET) +# define STM32_CAN1_TDL1R (STM32_CAN1_BASE+STM32_CAN_TDL1R_OFFSET) +# define STM32_CAN1_TDL2R (STM32_CAN1_BASE+STM32_CAN_TDL2R_OFFSET) -# define STM32L4_CAN1_TDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_TDHR_OFFSET(m)) -# define STM32L4_CAN1_TDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH0R_OFFSET) -# define STM32L4_CAN1_TDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH1R_OFFSET) -# define STM32L4_CAN1_TDH2R (STM32L4_CAN1_BASE+STM32L4_CAN_TDH2R_OFFSET) +# define STM32_CAN1_TDHR(m) (STM32_CAN1_BASE+STM32_CAN_TDHR_OFFSET(m)) +# define STM32_CAN1_TDH0R (STM32_CAN1_BASE+STM32_CAN_TDH0R_OFFSET) +# define STM32_CAN1_TDH1R (STM32_CAN1_BASE+STM32_CAN_TDH1R_OFFSET) +# define STM32_CAN1_TDH2R (STM32_CAN1_BASE+STM32_CAN_TDH2R_OFFSET) -# define STM32L4_CAN1_RIR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RIR_OFFSET(m)) -# define STM32L4_CAN1_RI0R (STM32L4_CAN1_BASE+STM32L4_CAN_RI0R_OFFSET) -# define STM32L4_CAN1_RI1R (STM32L4_CAN1_BASE+STM32L4_CAN_RI1R_OFFSET) +# define STM32_CAN1_RIR(m) (STM32_CAN1_BASE+STM32_CAN_RIR_OFFSET(m)) +# define STM32_CAN1_RI0R (STM32_CAN1_BASE+STM32_CAN_RI0R_OFFSET) +# define STM32_CAN1_RI1R (STM32_CAN1_BASE+STM32_CAN_RI1R_OFFSET) -# define STM32L4_CAN1_RDTR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDTR_OFFSET(m)) -# define STM32L4_CAN1_RDT0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT0R_OFFSET) -# define STM32L4_CAN1_RDT1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDT1R_OFFSET) +# define STM32_CAN1_RDTR(m) (STM32_CAN1_BASE+STM32_CAN_RDTR_OFFSET(m)) +# define STM32_CAN1_RDT0R (STM32_CAN1_BASE+STM32_CAN_RDT0R_OFFSET) +# define STM32_CAN1_RDT1R (STM32_CAN1_BASE+STM32_CAN_RDT1R_OFFSET) -# define STM32L4_CAN1_RDLR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDLR_OFFSET(m)) -# define STM32L4_CAN1_RDL0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL0R_OFFSET) -# define STM32L4_CAN1_RDL1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDL1R_OFFSET) +# define STM32_CAN1_RDLR(m) (STM32_CAN1_BASE+STM32_CAN_RDLR_OFFSET(m)) +# define STM32_CAN1_RDL0R (STM32_CAN1_BASE+STM32_CAN_RDL0R_OFFSET) +# define STM32_CAN1_RDL1R (STM32_CAN1_BASE+STM32_CAN_RDL1R_OFFSET) -# define STM32L4_CAN1_RDHR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RDHR_OFFSET(m)) -# define STM32L4_CAN1_RDH0R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH0R_OFFSET) -# define STM32L4_CAN1_RDH1R (STM32L4_CAN1_BASE+STM32L4_CAN_RDH1R_OFFSET) +# define STM32_CAN1_RDHR(m) (STM32_CAN1_BASE+STM32_CAN_RDHR_OFFSET(m)) +# define STM32_CAN1_RDH0R (STM32_CAN1_BASE+STM32_CAN_RDH0R_OFFSET) +# define STM32_CAN1_RDH1R (STM32_CAN1_BASE+STM32_CAN_RDH1R_OFFSET) -# define STM32L4_CAN1_FMR (STM32L4_CAN1_BASE+STM32L4_CAN_FMR_OFFSET) -# define STM32L4_CAN1_FM1R (STM32L4_CAN1_BASE+STM32L4_CAN_FM1R_OFFSET) -# define STM32L4_CAN1_FS1R (STM32L4_CAN1_BASE+STM32L4_CAN_FS1R_OFFSET) -# define STM32L4_CAN1_FFA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FFA1R_OFFSET) -# define STM32L4_CAN1_FA1R (STM32L4_CAN1_BASE+STM32L4_CAN_FA1R_OFFSET) -# define STM32L4_CAN1_FIR(b,i) (STM32L4_CAN1_BASE+STM32L4_CAN_FIR_OFFSET(b,i)) +# define STM32_CAN1_FMR (STM32_CAN1_BASE+STM32_CAN_FMR_OFFSET) +# define STM32_CAN1_FM1R (STM32_CAN1_BASE+STM32_CAN_FM1R_OFFSET) +# define STM32_CAN1_FS1R (STM32_CAN1_BASE+STM32_CAN_FS1R_OFFSET) +# define STM32_CAN1_FFA1R (STM32_CAN1_BASE+STM32_CAN_FFA1R_OFFSET) +# define STM32_CAN1_FA1R (STM32_CAN1_BASE+STM32_CAN_FA1R_OFFSET) +# define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h index 4c9694ab78d..350f0ab77f7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h @@ -29,15 +29,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_COMP_CSR_OFFSET(n) (((n)-1) << 2) -#define STM32L4_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ -#define STM32L4_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ +#define STM32_COMP_CSR_OFFSET(n) (((n)-1) << 2) +#define STM32_COMP1_CSR_OFFSET 0x0000 /* Comparator 1 control and status register */ +#define STM32_COMP2_CSR_OFFSET 0x0004 /* Comparator 2 control and status register */ /* Register Addresses *******************************************************/ -#define STM32L4_COMP_CSR(n) (STM32L4_COMP_BASE+STM32L4_COMP_CSR_OFFSET(n)) -#define STM32L4_COMP1_CSR (STM32L4_COMP_BASE+STM32L4_COMP1_CSR_OFFSET) -#define STM32L4_COMP2_CSR (STM32L4_COMP_BASE+STM32L4_COMP2_CSR_OFFSET) +#define STM32_COMP_CSR(n) (STM32_COMP_BASE+STM32_COMP_CSR_OFFSET(n)) +#define STM32_COMP1_CSR (STM32_COMP_BASE+STM32_COMP1_CSR_OFFSET) +#define STM32_COMP2_CSR (STM32_COMP_BASE+STM32_COMP2_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -109,7 +109,9 @@ # define COMP_CSR_INMESEL_PIN4 (2 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 4: COMP1=PA4; COMP2=PA4 */ # define COMP_CSR_INMESEL_PIN5 (3 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 5: COMP1=PA5; COMP2=PA5 */ #endif - /* Bits 27-29: Reserved */ + +/* Bits 27-29: Reserved */ + #define COMP_CSR_VALUE (1 << 30) /* Bit 30: Comparator output status bit */ #define COMP_CSR_LOCK_MASK (1 << 31) /* Bit 31: CSR register lock bit */ # define COMP_CSR_LOCK_RW (0) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h index 5ff70d77eaa..c282c4d4ecf 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_crs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_crs.h @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32L4_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32L4_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32L4_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32L4_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32L4_CRS_CR (STM32L4_CRS_BASE + STM32L4_CRS_CR_OFFSET) -#define STM32L4_CRS_CFGR (STM32L4_CRS_BASE + STM32L4_CRS_CFGR_OFFSET) -#define STM32L4_CRS_ISR (STM32L4_CRS_BASE + STM32L4_CRS_ISR_OFFSET) -#define STM32L4_CRS_ICR (STM32L4_CRS_BASE + STM32L4_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h index d8d613212da..5d72eeb08bd 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dac.h @@ -36,51 +36,51 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DAC_CR_OFFSET 0x0000 /* DAC control register */ -#define STM32L4_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ -#define STM32L4_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ -#define STM32L4_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ -#define STM32L4_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ -#define STM32L4_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ -#define STM32L4_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ -#define STM32L4_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ -#define STM32L4_DAC_SR_OFFSET 0x0034 /* DAC status register */ +#define STM32_DAC_CR_OFFSET 0x0000 /* DAC control register */ +#define STM32_DAC_SWTRIGR_OFFSET 0x0004 /* DAC software trigger register */ +#define STM32_DAC_DHR12R1_OFFSET 0x0008 /* DAC channel 1 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12L1_OFFSET 0x000c /* DAC channel 1 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R1_OFFSET 0x0010 /* DAC channel 1 8-bit right aligned data holding register */ +#define STM32_DAC_DHR12R2_OFFSET 0x0014 /* DAC channel 2 12-bit right aligned data holding register */ +#define STM32_DAC_DHR12L2_OFFSET 0x0018 /* DAC channel 2 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8R2_OFFSET 0x001c /* DAC channel 2 8-bit right-aligned data holding register */ +#define STM32_DAC_DHR12RD_OFFSET 0x0020 /* Dual DAC 12-bit right-aligned data holding register */ +#define STM32_DAC_DHR12LD_OFFSET 0x0024 /* DUAL DAC 12-bit left aligned data holding register */ +#define STM32_DAC_DHR8RD_OFFSET 0x0028 /* DUAL DAC 8-bit right aligned data holding register */ +#define STM32_DAC_DOR1_OFFSET 0x002c /* DAC channel 1 data output register */ +#define STM32_DAC_DOR2_OFFSET 0x0030 /* DAC channel 2 data output register */ +#define STM32_DAC_SR_OFFSET 0x0034 /* DAC status register */ /* New registers not in STM32L1: */ -#define STM32L4_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ -#define STM32L4_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ -#define STM32L4_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ -#define STM32L4_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ -#define STM32L4_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ -#define STM32L4_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ +#define STM32_DAC_CCR_OFFSET 0x0038 /* DAC calibration control register */ +#define STM32_DAC_MCR_OFFSET 0x003c /* DAC mode control register */ +#define STM32_DAC_SHSR1_OFFSET 0x0040 /* DAC Sample and Hold sample time register 1 */ +#define STM32_DAC_SHSR2_OFFSET 0x0044 /* DAC Sample and Hold sample time register 2 */ +#define STM32_DAC_SHHR_OFFSET 0x0048 /* DAC Sample and Hold hold time register */ +#define STM32_DAC_SHRR_OFFSET 0x004c /* DAC Sample and Hold refresh time register */ /* Register Addresses *******************************************************/ -#define STM32L4_DAC_CR (STM32L4_DAC_BASE+STM32L4_DAC_CR_OFFSET) -#define STM32L4_DAC_SWTRIGR (STM32L4_DAC_BASE+STM32L4_DAC_SWTRIGR_OFFSET) -#define STM32L4_DAC_DHR12R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R1_OFFSET) -#define STM32L4_DAC_DHR12L1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L1_OFFSET) -#define STM32L4_DAC_DHR8R1 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R1_OFFSET) -#define STM32L4_DAC_DHR12R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12R2_OFFSET) -#define STM32L4_DAC_DHR12L2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR12L2_OFFSET) -#define STM32L4_DAC_DHR8R2 (STM32L4_DAC_BASE+STM32L4_DAC_DHR8R2_OFFSET) -#define STM32L4_DAC_DHR12RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12RD_OFFSET) -#define STM32L4_DAC_DHR12LD (STM32L4_DAC_BASE+STM32L4_DAC_DHR12LD_OFFSET) -#define STM32L4_DAC_DHR8RD (STM32L4_DAC_BASE+STM32L4_DAC_DHR8RD_OFFSET) -#define STM32L4_DAC_DOR1 (STM32L4_DAC_BASE+STM32L4_DAC_DOR1_OFFSET) -#define STM32L4_DAC_DOR2 (STM32L4_DAC_BASE+STM32L4_DAC_DOR2_OFFSET) -#define STM32L4_DAC_SR (STM32L4_DAC_BASE+STM32L4_DAC_SR_OFFSET) -#define STM32L4_DAC_CCR (STM32L4_DAC_BASE+STM32L4_DAC_CCR_OFFSET) -#define STM32L4_DAC_MCR (STM32L4_DAC_BASE+STM32L4_DAC_MCR_OFFSET) -#define STM32L4_DAC_SHSR1 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR1_OFFSET) -#define STM32L4_DAC_SHSR2 (STM32L4_DAC_BASE+STM32L4_DAC_SHSR2_OFFSET) -#define STM32L4_DAC_SHHR (STM32L4_DAC_BASE+STM32L4_DAC_SHHR_OFFSET) -#define STM32L4_DAC_SHRR (STM32L4_DAC_BASE+STM32L4_DAC_SHRR_OFFSET) +#define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET) +#define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET) +#define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET) +#define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET) +#define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET) +#define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET) +#define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET) +#define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET) +#define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET) +#define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET) +#define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET) +#define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET) +#define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET) +#define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET) +#define STM32_DAC_CCR (STM32_DAC_BASE+STM32_DAC_CCR_OFFSET) +#define STM32_DAC_MCR (STM32_DAC_BASE+STM32_DAC_MCR_OFFSET) +#define STM32_DAC_SHSR1 (STM32_DAC_BASE+STM32_DAC_SHSR1_OFFSET) +#define STM32_DAC_SHSR2 (STM32_DAC_BASE+STM32_DAC_SHSR2_OFFSET) +#define STM32_DAC_SHHR (STM32_DAC_BASE+STM32_DAC_SHHR_OFFSET) +#define STM32_DAC_SHRR (STM32_DAC_BASE+STM32_DAC_SHRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index 85546d55bc8..eaa9eae9024 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -41,134 +41,134 @@ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) +#define STM32_DFSDM_CHCFGR1_OFFSET(y) (0x00 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ -#define STM32L4_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ -#define STM32L4_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ -#define STM32L4_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ +#define STM32_DFSDM_CH0CFGR1_OFFSET 0x0000 /* DFSDM channel configuration 0 register */ +#define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ +#define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ +#define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ -# define STM32L4_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ -# define STM32L4_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ -# define STM32L4_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ +# define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ +# define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ +# define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ +# define STM32_DFSDM_CH7CFGR1_OFFSET 0x00e0 /* DFSDM channel configuration 7 register */ #endif -#define STM32L4_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) +#define STM32_DFSDM_CHCFGR2_OFFSET(y) (0x04 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ -#define STM32L4_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ -#define STM32L4_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ -#define STM32L4_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ +#define STM32_DFSDM_CH0CFGR2_OFFSET 0x0004 /* DFSDM channel configuration 0 register 2 */ +#define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ +#define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ +#define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ -# define STM32L4_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ -# define STM32L4_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ -# define STM32L4_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ +# define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ +# define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ +# define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ +# define STM32_DFSDM_CH7CFGR2_OFFSET 0x00e4 /* DFSDM channel configuration 7 register 2 */ #endif -#define STM32L4_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) +#define STM32_DFSDM_CHAWSCDR_OFFSET(y) (0x08 + 0x20 * (y)) -#define STM32L4_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ -#define STM32L4_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH0AWSCDR_OFFSET 0x0008 /* DFSDM channel 0 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ +#define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ -# define STM32L4_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ +# define STM32_DFSDM_CH7AWSCDR_OFFSET 0x00e8 /* DFSDM channel 7 analog watchdog and short-circuit detector register */ #endif -#define STM32L4_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) +#define STM32_DFSDM_CHWDATR_OFFSET(y) (0x0c + 0x20 * (y)) -#define STM32L4_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ -#define STM32L4_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ -#define STM32L4_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ -#define STM32L4_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ +#define STM32_DFSDM_CH0WDATR_OFFSET 0x000c /* DFSDM channel 0 watchdog filter data register */ +#define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ +#define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ +#define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ -# define STM32L4_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ -# define STM32L4_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ -# define STM32L4_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ +# define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ +# define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ +# define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ +# define STM32_DFSDM_CH7WDATR_OFFSET 0x00ec /* DFSDM channel 7 watchdog filter data register */ #endif -#define STM32L4_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ +#define STM32_DFSDM_CHDATINR_OFFSET(ch) (0x10 + 0x20 * (ch)) /* DFSDM channel data input register */ -#define STM32L4_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ -#define STM32L4_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ -#define STM32L4_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ -#define STM32L4_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ +#define STM32_DFSDM_CH0DATINR_OFFSET 0x0010 /* DFSDM channel 0 data input register */ +#define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ +#define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ +#define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ #ifndef CONFIG_STM32L4_STM32L4X3 -# define STM32L4_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ -# define STM32L4_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ -# define STM32L4_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ -# define STM32L4_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ +# define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ +# define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ +# define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ +# define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ #endif #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ +# define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ -# define STM32L4_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ -# define STM32L4_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ -# define STM32L4_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ -# define STM32L4_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ -# define STM32L4_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ -# define STM32L4_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ -# define STM32L4_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ -# define STM32L4_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ +# define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ +# define STM32_DFSDM_CH1DLYR_OFFSET 0x0034 /* DFSDM channel 1 delay register */ +# define STM32_DFSDM_CH2DLYR_OFFSET 0x0054 /* DFSDM channel 2 delay register */ +# define STM32_DFSDM_CH3DLYR_OFFSET 0x0074 /* DFSDM channel 3 delay register */ +# define STM32_DFSDM_CH4DLYR_OFFSET 0x0094 /* DFSDM channel 4 delay register */ +# define STM32_DFSDM_CH5DLYR_OFFSET 0x00b4 /* DFSDM channel 5 delay register */ +# define STM32_DFSDM_CH6DLYR_OFFSET 0x00d4 /* DFSDM channel 6 delay register */ +# define STM32_DFSDM_CH7DLYR_OFFSET 0x00f4 /* DFSDM channel 7 delay register */ #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ -#define STM32L4_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ -#define STM32L4_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ -#define STM32L4_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ -#define STM32L4_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ -#define STM32L4_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ -#define STM32L4_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ -#define STM32L4_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ -#define STM32L4_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ -#define STM32L4_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ -#define STM32L4_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ -#define STM32L4_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ -#define STM32L4_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ -#define STM32L4_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ -#define STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ +#define STM32_DFSDM_FLTCR1_OFFSET(x) (0x100 + 0x80 * (x)) /* DFSDM control register 1 */ +#define STM32_DFSDM_FLTCR2_OFFSET(x) (0x104 + 0x80 * (x)) /* DFSDM control register 2 */ +#define STM32_DFSDM_FLTISR_OFFSET(x) (0x108 + 0x80 * (x)) /* DFSDM interrupt and status register */ +#define STM32_DFSDM_FLTICR_OFFSET(x) (0x10c + 0x80 * (x)) /* DFSDM interrupt flag clear register */ +#define STM32_DFSDM_FLTJCHGR_OFFSET(x) (0x110 + 0x80 * (x)) /* DFSDM injected channel group selection register */ +#define STM32_DFSDM_FLTFCR_OFFSET(x) (0x114 + 0x80 * (x)) /* DFSDM filter control register */ +#define STM32_DFSDM_FLTJDATAR_OFFSET(x) (0x118 + 0x80 * (x)) /* DFSDM data register for injected group */ +#define STM32_DFSDM_FLTRDATAR_OFFSET(x) (0x11c + 0x80 * (x)) /* DFSDM data register for the regular channel */ +#define STM32_DFSDM_FLTAWHTR_OFFSET(x) (0x120 + 0x80 * (x)) /* DFSDM analog watchdog high threshold register */ +#define STM32_DFSDM_FLTAWLTR_OFFSET(x) (0x124 + 0x80 * (x)) /* DFSDM analog watchdog low threshold register */ +#define STM32_DFSDM_FLTAWSR_OFFSET(x) (0x128 + 0x80 * (x)) /* DFSDM analog watchdog status register */ +#define STM32_DFSDM_FLTAWCFR_OFFSET(x) (0x12c + 0x80 * (x)) /* DFSDM analog watchdog clear flag register */ +#define STM32_DFSDM_FLTEXMAX_OFFSET(x) (0x130 + 0x80 * (x)) /* DFSDM Extremes detector maximum register */ +#define STM32_DFSDM_FLTEXMIN_OFFSET(x) (0x134 + 0x80 * (x)) /* DFSDM Extremes detector minimum register */ +#define STM32_DFSDM_FLTCNVTIMR_OFFSET(x) (0x138 + 0x80 * (x)) /* DFSDM conversion timer register */ /* Register Addresses *******************************************************/ /* DFSDM channel y registers (y=0..7 or y=0..3 on STM32L4X3) */ -#define STM32L4_DFSDM_CHCFGR1(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR1_OFFSET(y)) -#define STM32L4_DFSDM_CH0CFGR1 (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CH0CFGR1_OFFSET) +#define STM32_DFSDM_CHCFGR1(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR1_OFFSET(y)) +#define STM32_DFSDM_CH0CFGR1 (STM32_DFSDM_BASE + STM32_DFSDM_CH0CFGR1_OFFSET) -#define STM32L4_DFSDM_CHCFGR2(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHCFGR2_OFFSET(y)) -#define STM32L4_DFSDM_CHAWSCDR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHAWSCDR_OFFSET(y)) -#define STM32L4_DFSDM_CHWDATR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHWDATR_OFFSET(y) -#define STM32L4_DFSDM_CHDATINR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDATINR_OFFSET(y)) +#define STM32_DFSDM_CHCFGR2(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHCFGR2_OFFSET(y)) +#define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y)) +#define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y) +#define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y)) #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_DFSDM_CHDLYR(y) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_CHDLYR_OFFSET(y)) +# define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y)) #endif /* DFSDM filter x module registers (x=0..3 or x=0..1 on STM32L4X3) */ -#define STM32L4_DFSDM_FLTCR1(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR1_OFFSET(x)) -#define STM32L4_DFSDM_FLTCR2(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCR2_OFFSET(x)) -#define STM32L4_DFSDM_FLTISR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTISR_OFFSET(x)) -#define STM32L4_DFSDM_FLTICR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTICR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJCHGR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJCHGR_OFFSET(x)) -#define STM32L4_DFSDM_FLTFCR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTFCR_OFFSET(x)) -#define STM32L4_DFSDM_FLTJDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTJDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTRDATAR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTRDATAR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWHTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWHTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWLTR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWLTR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWSR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWSR_OFFSET(x)) -#define STM32L4_DFSDM_FLTAWCFR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTAWCFR_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMAX(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMAX_OFFSET(x)) -#define STM32L4_DFSDM_FLTEXMIN(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTEXMIN_OFFSET(x)) -#define STM32L4_DFSDM_FLTCNVTIMR(x) (STM32L4_DFSDM_BASE + STM32L4_DFSDM_FLTCNVTIMR_OFFSET(x)) +#define STM32_DFSDM_FLTCR1(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR1_OFFSET(x)) +#define STM32_DFSDM_FLTCR2(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCR2_OFFSET(x)) +#define STM32_DFSDM_FLTISR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTISR_OFFSET(x)) +#define STM32_DFSDM_FLTICR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTICR_OFFSET(x)) +#define STM32_DFSDM_FLTJCHGR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJCHGR_OFFSET(x)) +#define STM32_DFSDM_FLTFCR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTFCR_OFFSET(x)) +#define STM32_DFSDM_FLTJDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTJDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTRDATAR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTRDATAR_OFFSET(x)) +#define STM32_DFSDM_FLTAWHTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWHTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWLTR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWLTR_OFFSET(x)) +#define STM32_DFSDM_FLTAWSR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWSR_OFFSET(x)) +#define STM32_DFSDM_FLTAWCFR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTAWCFR_OFFSET(x)) +#define STM32_DFSDM_FLTEXMAX(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMAX_OFFSET(x)) +#define STM32_DFSDM_FLTEXMIN(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTEXMIN_OFFSET(x)) +#define STM32_DFSDM_FLTCNVTIMR(x) (STM32_DFSDM_BASE + STM32_DFSDM_FLTCNVTIMR_OFFSET(x)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h index f6295dc9c42..d10f7364f16 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_exti.h @@ -34,44 +34,44 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NEXTI1 31 -#define STM32L4_EXTI1_MASK 0xffffffff -#define STM32L4_NEXTI2 9 -#define STM32L4_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff -#define STM32L4_EXTI1_BIT(n) (1 << (n)) -#define STM32L4_EXTI2_BIT(n) (1 << (n)) +#define STM32_EXTI1_BIT(n) (1 << (n)) +#define STM32_EXTI2_BIT(n) (1 << (n)) /* Register Offsets *********************************************************/ -#define STM32L4_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ -#define STM32L4_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ +#define STM32_EXTI1_OFFSET 0x0000 /* Offset to EXTI1 registers */ +#define STM32_EXTI2_OFFSET 0x0020 /* Offset to EXTI2 registers */ -#define STM32L4_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ -#define STM32L4_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ -#define STM32L4_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ -#define STM32L4_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ -#define STM32L4_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ -#define STM32L4_EXTI_PR_OFFSET 0x0014 /* Pending register */ +#define STM32_EXTI_IMR_OFFSET 0x0000 /* Interrupt mask register */ +#define STM32_EXTI_EMR_OFFSET 0x0004 /* Event mask register */ +#define STM32_EXTI_RTSR_OFFSET 0x0008 /* Rising Trigger selection register */ +#define STM32_EXTI_FTSR_OFFSET 0x000c /* Falling Trigger selection register */ +#define STM32_EXTI_SWIER_OFFSET 0x0010 /* Software interrupt event register */ +#define STM32_EXTI_PR_OFFSET 0x0014 /* Pending register */ /* Register Addresses *******************************************************/ -#define STM32L4_EXTI1_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI1_OFFSET) -#define STM32L4_EXTI2_BASE (STM32L4_EXTI_BASE+STM32L4_EXTI2_OFFSET) +#define STM32_EXTI1_BASE (STM32_EXTI_BASE+STM32_EXTI1_OFFSET) +#define STM32_EXTI2_BASE (STM32_EXTI_BASE+STM32_EXTI2_OFFSET) -#define STM32L4_EXTI1_IMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI1_EMR (STM32L4_EXTI1_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI1_RTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI1_FTSR (STM32L4_EXTI1_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI1_SWIER (STM32L4_EXTI1_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI1_PR (STM32L4_EXTI1_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI1_IMR (STM32_EXTI1_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI1_EMR (STM32_EXTI1_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI1_RTSR (STM32_EXTI1_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI1_FTSR (STM32_EXTI1_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI1_SWIER (STM32_EXTI1_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI1_PR (STM32_EXTI1_BASE+STM32_EXTI_PR_OFFSET) -#define STM32L4_EXTI2_IMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_IMR_OFFSET) -#define STM32L4_EXTI2_EMR (STM32L4_EXTI2_BASE+STM32L4_EXTI_EMR_OFFSET) -#define STM32L4_EXTI2_RTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_RTSR_OFFSET) -#define STM32L4_EXTI2_FTSR (STM32L4_EXTI2_BASE+STM32L4_EXTI_FTSR_OFFSET) -#define STM32L4_EXTI2_SWIER (STM32L4_EXTI2_BASE+STM32L4_EXTI_SWIER_OFFSET) -#define STM32L4_EXTI2_PR (STM32L4_EXTI2_BASE+STM32L4_EXTI_PR_OFFSET) +#define STM32_EXTI2_IMR (STM32_EXTI2_BASE+STM32_EXTI_IMR_OFFSET) +#define STM32_EXTI2_EMR (STM32_EXTI2_BASE+STM32_EXTI_EMR_OFFSET) +#define STM32_EXTI2_RTSR (STM32_EXTI2_BASE+STM32_EXTI_RTSR_OFFSET) +#define STM32_EXTI2_FTSR (STM32_EXTI2_BASE+STM32_EXTI_FTSR_OFFSET) +#define STM32_EXTI2_SWIER (STM32_EXTI2_BASE+STM32_EXTI_SWIER_OFFSET) +#define STM32_EXTI2_PR (STM32_EXTI2_BASE+STM32_EXTI_PR_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -105,62 +105,62 @@ /* Interrupt mask register */ -#define EXTI_IMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_IMR1_MASK STM32_EXTI1_MASK -#define EXTI_IMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ +#define EXTI_IMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Interrupt request from line x is not masked */ #define EXTI_IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */ -#define EXTI_IMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_IMR2_MASK STM32_EXTI2_MASK /* Event mask register */ -#define EXTI_EMR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR1_MASK STM32L4_EXTI1_MASK +#define EXTI_EMR1_MASK STM32_EXTI1_MASK -#define EXTI_EMR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ +#define EXTI_EMR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Event request from line x is not mask */ #define EXTI_EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */ -#define EXTI_EMR2_MASK STM32L4_EXTI2_MASK +#define EXTI_EMR2_MASK STM32_EXTI2_MASK /* Rising Trigger selection register */ -#define EXTI_RTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_RTSR1_MASK STM32_EXTI1_MASK -#define EXTI_RTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_RTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */ #define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */ -#define EXTI_RTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_RTSR2_MASK STM32_EXTI2_MASK /* Falling Trigger selection register */ -#define EXTI_FTSR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR1_MASK STM32L4_EXTI1_MASK +#define EXTI_FTSR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR1_MASK STM32_EXTI1_MASK -#define EXTI_FTSR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ -#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ -#define EXTI_FTSR2_MASK STM32L4_EXTI2_MASK +#define EXTI_FTSR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */ +#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */ +#define EXTI_FTSR2_MASK STM32_EXTI2_MASK /* Software interrupt event register */ -#define EXTI_SWIER1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER1_MASK STM32L4_EXTI1_MASK +#define EXTI_SWIER1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER1_MASK STM32_EXTI1_MASK -#define EXTI_SWIER2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ -#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ -#define EXTI_SWIER2_MASK STM32L4_EXTI2_MASK +#define EXTI_SWIER2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */ +#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */ +#define EXTI_SWIER2_MASK STM32_EXTI2_MASK /* Pending register */ -#define EXTI_PR1_BIT(n) STM32L4_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR1_MASK STM32L4_EXTI1_MASK +#define EXTI_PR1_BIT(n) STM32_EXTI1_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR1_MASK STM32_EXTI1_MASK -#define EXTI_PR2_BIT(n) STM32L4_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ -#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ -#define EXTI_PR2_MASK STM32L4_EXTI2_MASK +#define EXTI_PR2_BIT(n) STM32_EXTI2_BIT(n) /* 1=Selected trigger request occurred */ +#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ +#define EXTI_PR2_MASK STM32_EXTI2_MASK #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_EXTI_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 8af1c073dc2..738544c954e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -113,79 +113,79 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */ -# define STM32L4_FLASH_NPAGES 32 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */ -# define STM32L4_FLASH_NPAGES 64 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L4_FLASH_NPAGES 128 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L4_FLASH_NPAGES 256 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ -# define STM32L4_FLASH_NPAGES 512 -# define STM32L4_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L4_FLASH_PAGESIZE -# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L4_FLASH_ACR_OFFSET 0x0000 -#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L4_FLASH_KEYR_OFFSET 0x0008 -#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32L4_FLASH_SR_OFFSET 0x0010 -#define STM32L4_FLASH_CR_OFFSET 0x0014 -#define STM32L4_FLASH_ECCR_OFFSET 0x0018 -#define STM32L4_FLASH_OPTR_OFFSET 0x0020 -#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024 -#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028 -#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c -#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1SR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1ER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044 -# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048 -# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c -# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050 +# define STM32_FLASH_PCROP2SR_OFFSET 0x0044 +# define STM32_FLASH_PCROP2ER_OFFSET 0x0048 +# define STM32_FLASH_WRP2AR_OFFSET 0x004c +# define STM32_FLASH_WRP2BR_OFFSET 0x0050 #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR_OFFSET 0x0130 +# define STM32_FLASH_CFGR_OFFSET 0x0130 #endif /* Register Addresses *******************************************************/ -#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET) -#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET) -#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET) -#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET) -#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET) -#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET) -#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET) -#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET) -#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET) -#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET) -#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET) -#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE+STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1SR_OFFSET) +#define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET) -# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET) -# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET) -# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET) +# define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) +# define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) +# define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) +# define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) #endif #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_FLASH_CFGR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CFGR_OFFSET) +# define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h index 8938d7d983c..e5501893ecb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_gpio.h @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L4_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L4_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L4_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L4_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L4_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L4_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L4_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L4_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L4_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L4_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L4_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L4_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_ASCR_OFFSET 0x002c /* GPIO port analog switch control register */ /* Register Addresses *******************************************************/ -#if STM32L4_NPORTS > 0 -# define STM32L4_GPIOA_MODER (STM32L4_GPIOA_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOA_OTYPER (STM32L4_GPIOA_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOA_OSPEED (STM32L4_GPIOA_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOA_PUPDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOA_IDR (STM32L4_GPIOA_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOA_ODR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOA_BSRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOA_LCKR (STM32L4_GPIOA_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOA_AFRL (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOA_AFRH (STM32L4_GPIOA_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOA_BRR (STM32L4_GPIOA_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOA_ASCR (STM32L4_GPIOA_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 1 -# define STM32L4_GPIOB_MODER (STM32L4_GPIOB_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOB_OTYPER (STM32L4_GPIOB_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOB_OSPEED (STM32L4_GPIOB_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOB_PUPDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOB_IDR (STM32L4_GPIOB_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOB_ODR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOB_BSRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOB_LCKR (STM32L4_GPIOB_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOB_AFRL (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOB_AFRH (STM32L4_GPIOB_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOB_BRR (STM32L4_GPIOB_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOB_ASCR (STM32L4_GPIOB_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 2 -# define STM32L4_GPIOC_MODER (STM32L4_GPIOC_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOC_OTYPER (STM32L4_GPIOC_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOC_OSPEED (STM32L4_GPIOC_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOC_PUPDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOC_IDR (STM32L4_GPIOC_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOC_ODR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOC_BSRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOC_LCKR (STM32L4_GPIOC_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOC_AFRL (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOC_AFRH (STM32L4_GPIOC_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOC_BRR (STM32L4_GPIOC_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOC_ASCR (STM32L4_GPIOC_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 3 -# define STM32L4_GPIOD_MODER (STM32L4_GPIOD_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOD_OTYPER (STM32L4_GPIOD_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOD_OSPEED (STM32L4_GPIOD_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOD_PUPDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOD_IDR (STM32L4_GPIOD_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOD_ODR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOD_BSRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOD_LCKR (STM32L4_GPIOD_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOD_AFRL (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOD_AFRH (STM32L4_GPIOD_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOD_BRR (STM32L4_GPIOD_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOD_ASCR (STM32L4_GPIOD_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_ASCR (STM32_GPIOD_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 4 -# define STM32L4_GPIOE_MODER (STM32L4_GPIOE_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOE_OTYPER (STM32L4_GPIOE_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOE_OSPEED (STM32L4_GPIOE_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOE_PUPDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOE_IDR (STM32L4_GPIOE_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOE_ODR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOE_BSRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOE_LCKR (STM32L4_GPIOE_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOE_AFRL (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOE_AFRH (STM32L4_GPIOE_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOE_BRR (STM32L4_GPIOE_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOE_ASCR (STM32L4_GPIOE_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_ASCR (STM32_GPIOE_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 5 -# define STM32L4_GPIOF_MODER (STM32L4_GPIOF_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOF_OTYPER (STM32L4_GPIOF_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOF_OSPEED (STM32L4_GPIOF_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOF_PUPDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOF_IDR (STM32L4_GPIOF_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOF_ODR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOF_BSRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOF_LCKR (STM32L4_GPIOF_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOF_AFRL (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOF_AFRH (STM32L4_GPIOF_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOF_BRR (STM32L4_GPIOF_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOF_ASCR (STM32L4_GPIOF_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_ASCR (STM32_GPIOF_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 6 -# define STM32L4_GPIOG_MODER (STM32L4_GPIOG_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOG_OTYPER (STM32L4_GPIOG_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOG_OSPEED (STM32L4_GPIOG_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOG_PUPDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOG_IDR (STM32L4_GPIOG_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOG_ODR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOG_BSRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOG_LCKR (STM32L4_GPIOG_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOG_AFRL (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOG_AFRH (STM32L4_GPIOG_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOG_BRR (STM32L4_GPIOG_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOG_ASCR (STM32L4_GPIOG_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_ASCR (STM32_GPIOG_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 7 -# define STM32L4_GPIOH_MODER (STM32L4_GPIOH_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOH_OTYPER (STM32L4_GPIOH_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOH_OSPEED (STM32L4_GPIOH_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOH_PUPDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOH_IDR (STM32L4_GPIOH_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOH_ODR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOH_BSRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOH_LCKR (STM32L4_GPIOH_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOH_AFRL (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOH_AFRH (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOH_BRR (STM32L4_GPIOH_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOH_ASCR (STM32L4_GPIOH_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) #endif -#if STM32L4_NPORTS > 8 -# define STM32L4_GPIOI_MODER (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET) -# define STM32L4_GPIOI_OTYPER (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET) -# define STM32L4_GPIOI_OSPEED (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET) -# define STM32L4_GPIOI_PUPDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET) -# define STM32L4_GPIOI_IDR (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET) -# define STM32L4_GPIOI_ODR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET) -# define STM32L4_GPIOI_BSRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET) -# define STM32L4_GPIOI_LCKR (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET) -# define STM32L4_GPIOI_AFRL (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET) -# define STM32L4_GPIOI_AFRH (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET) -# define STM32L4_GPIOI_BRR (STM32L4_GPIOI_BASE+STM32L4_GPIO_BRR_OFFSET) -# define STM32L4_GPIOI_ASCR (STM32L4_GPIOI_BASE+STM32L4_GPIO_ASCR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE+STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE+STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE+STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE+STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE+STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE+STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE+STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE+STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE+STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE+STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE+STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_ASCR (STM32_GPIOI_BASE+STM32_GPIO_ASCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h index 9ec04ef430a..7fecf9bbd62 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_i2c.h @@ -29,74 +29,74 @@ /* Register Offsets *********************************************************/ -#define STM32L4_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32L4_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32L4_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32L4_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32L4_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32L4_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32L4_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32L4_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32L4_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32L4_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32L4_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NI2C > 0 -# define STM32L4_I2C1_CR1 (STM32L4_I2C1_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C1_CR2 (STM32L4_I2C1_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C1_OAR1 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C1_OAR2 (STM32L4_I2C1_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C1_TIMINGR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C1_TIMEOUTR (STM32L4_I2C1_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C1_ISR (STM32L4_I2C1_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C1_ICR (STM32L4_I2C1_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C1_PECR (STM32L4_I2C1_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C1_RXDR (STM32L4_I2C1_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C1_TXDR (STM32L4_I2C1_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 0 +# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C1_OAR2 (STM32_I2C1_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C1_TIMINGR (STM32_I2C1_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C1_ISR (STM32_I2C1_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C1_ICR (STM32_I2C1_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C1_PECR (STM32_I2C1_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C1_RXDR (STM32_I2C1_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 1 -# define STM32L4_I2C2_CR1 (STM32L4_I2C2_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C2_CR2 (STM32L4_I2C2_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C2_OAR1 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C2_OAR2 (STM32L4_I2C2_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C2_TIMINGR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C2_TIMEOUTR (STM32L4_I2C2_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C2_ISR (STM32L4_I2C2_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C2_ICR (STM32L4_I2C2_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C2_PECR (STM32L4_I2C2_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C2_RXDR (STM32L4_I2C2_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C2_TXDR (STM32L4_I2C2_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 1 +# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C2_OAR2 (STM32_I2C2_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C2_TIMINGR (STM32_I2C2_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C2_TIMEOUTR (STM32_I2C2_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C2_ISR (STM32_I2C2_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C2_ICR (STM32_I2C2_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C2_PECR (STM32_I2C2_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C2_RXDR (STM32_I2C2_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 2 -# define STM32L4_I2C3_CR1 (STM32L4_I2C3_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C3_CR2 (STM32L4_I2C3_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C3_OAR1 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C3_OAR2 (STM32L4_I2C3_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C3_TIMINGR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C3_TIMEOUTR (STM32L4_I2C3_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C3_ISR (STM32L4_I2C3_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C3_ICR (STM32L4_I2C3_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C3_PECR (STM32L4_I2C3_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C3_RXDR (STM32L4_I2C3_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 2 +# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET) #endif -#if STM32L4_NI2C > 3 -# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET) -# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET) -# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET) -# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET) -# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET) -# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) -# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET) -# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET) -# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET) -# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET) -# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET) +#if STM32_NI2C > 3 +# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET) +# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET) +# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET) +# define STM32_I2C4_OAR2 (STM32_I2C4_BASE+STM32_I2C_OAR2_OFFSET) +# define STM32_I2C4_TIMINGR (STM32_I2C4_BASE+STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C4_TIMEOUTR (STM32_I2C4_BASE+STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C4_ISR (STM32_I2C4_BASE+STM32_I2C_ISR_OFFSET) +# define STM32_I2C4_ICR (STM32_I2C4_BASE+STM32_I2C_ICR_OFFSET) +# define STM32_I2C4_PECR (STM32_I2C4_BASE+STM32_I2C_PECR_OFFSET) +# define STM32_I2C4_RXDR (STM32_I2C4_BASE+STM32_I2C_RXDR_OFFSET) +# define STM32_I2C4_TXDR (STM32_I2C4_BASE+STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h index 1da51068e55..0a9c98ab0ba 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_lptim.h @@ -47,36 +47,36 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ -#define STM32L4_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ -#define STM32L4_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ -#define STM32L4_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ -#define STM32L4_LPTIM_CR_OFFSET 0x0010 /* Control Register */ -#define STM32L4_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ -#define STM32L4_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ -#define STM32L4_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ +#define STM32_LPTIM_ISR_OFFSET 0x0000 /* Interrupt and Status Register */ +#define STM32_LPTIM_ICR_OFFSET 0x0004 /* Interrupt Clear Register */ +#define STM32_LPTIM_IER_OFFSET 0x0008 /* Interrupt Enable Register */ +#define STM32_LPTIM_CFGR_OFFSET 0x000c /* Configuration Register */ +#define STM32_LPTIM_CR_OFFSET 0x0010 /* Control Register */ +#define STM32_LPTIM_CMP_OFFSET 0x0014 /* Compare Register */ +#define STM32_LPTIM_ARR_OFFSET 0x0018 /* Autoreload Register */ +#define STM32_LPTIM_CNT_OFFSET 0x001c /* Counter Register */ /* Register Addresses *******************************************************/ /* Low-Power Timers - LPTIM1 and LPTIM2 */ -#define STM32L4_LPTIM1_ISR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM1_ICR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM1_IER (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM1_CFGR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM1_CR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM1_CMP (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM1_ARR (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM1_CNT (STM32L4_LPTIM1_BASE+STM32L4_LPTIM_CNT_OFFSET) +#define STM32_LPTIM1_ISR (STM32_LPTIM1_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM1_ICR (STM32_LPTIM1_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM1_IER (STM32_LPTIM1_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM1_CFGR (STM32_LPTIM1_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM1_CR (STM32_LPTIM1_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM1_CMP (STM32_LPTIM1_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM1_ARR (STM32_LPTIM1_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM1_CNT (STM32_LPTIM1_BASE+STM32_LPTIM_CNT_OFFSET) -#define STM32L4_LPTIM2_ISR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ISR_OFFSET) -#define STM32L4_LPTIM2_ICR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ICR_OFFSET) -#define STM32L4_LPTIM2_IER (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_IER_OFFSET) -#define STM32L4_LPTIM2_CFGR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CFGR_OFFSET) -#define STM32L4_LPTIM2_CR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CR_OFFSET) -#define STM32L4_LPTIM2_CMP (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CMP_OFFSET) -#define STM32L4_LPTIM2_ARR (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_ARR_OFFSET) -#define STM32L4_LPTIM2_CNT (STM32L4_LPTIM2_BASE+STM32L4_LPTIM_CNT_OFFSET) +#define STM32_LPTIM2_ISR (STM32_LPTIM2_BASE+STM32_LPTIM_ISR_OFFSET) +#define STM32_LPTIM2_ICR (STM32_LPTIM2_BASE+STM32_LPTIM_ICR_OFFSET) +#define STM32_LPTIM2_IER (STM32_LPTIM2_BASE+STM32_LPTIM_IER_OFFSET) +#define STM32_LPTIM2_CFGR (STM32_LPTIM2_BASE+STM32_LPTIM_CFGR_OFFSET) +#define STM32_LPTIM2_CR (STM32_LPTIM2_BASE+STM32_LPTIM_CR_OFFSET) +#define STM32_LPTIM2_CMP (STM32_LPTIM2_BASE+STM32_LPTIM_CMP_OFFSET) +#define STM32_LPTIM2_ARR (STM32_LPTIM2_BASE+STM32_LPTIM_ARR_OFFSET) +#define STM32_LPTIM2_CNT (STM32_LPTIM2_BASE+STM32_LPTIM_CNT_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index 0cb4e62cac3..c677abec168 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -29,60 +29,60 @@ /* STM32L4XXX Address Blocks ************************************************/ -#define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -# define STM32L4_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ -#define STM32L4_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L4_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ -#define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ -#define STM32L4_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ -#define STM32L4_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ - /* 0xc0000000-0xdfffffff: 512Mb (not used) */ -#define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +# define STM32_FSMC_BANK2 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FSMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ +#define STM32_QSPI_BASE 0xa0001000 /* 0xa0001000-0xbfffffff: QSPI register block */ +#define STM32_OCTOSPI1_BASE 0xa0001000 /* 0xa0001000-0xa00013ff: OCTOSPI1 register block */ +#define STM32_OCTOSPI2_BASE 0xa0001400 /* 0xa0001400-0xa00017ff: OCTOSPI2 register block */ + /* 0xc0000000-0xdfffffff: 512Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ -#define STM32L4_REGION_MASK 0xf0000000 -#define STM32L4_IS_SRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_SRAM_BASE) -#define STM32L4_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L4_REGION_MASK) == STM32L4_FSMC_BANK1) +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ -#define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32L4_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ - /* 0x10010000-0x1ffeffff: Reserved */ -#define STM32L4_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ -#define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ -#define STM32L4_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ - /* 0x1fff7400-0x1fff77ff: Reserved */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ + /* 0x00100000-0x07ffffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 16k to 64k SRAM2 */ + /* 0x10010000-0x1ffeffff: Reserved */ +#define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x3fffffff: SRAM3 (STM32L4R9xx only, 384k) */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ + /* 0x1fff7400-0x1fff77ff: Reserved */ #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ - /* 0x1ff00010-0x1ff00fff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ - /* 0x1ff01010-0x1ff01fff: Reserved */ +# define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ + /* 0x1ff00010-0x1ff00fff: Reserved */ +# define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ + /* 0x1ff01010-0x1ff01fff: Reserved */ #else -# define STM32L4_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ - /* 0x1fff7810-0x1ffff7ff: Reserved */ -# define STM32L4_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ - /* 0x1ffff810-0x1fffffff: Reserved */ +# define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff7800-0x1fff780f: Option bytes */ + /* 0x1fff7810-0x1ffff7ff: Reserved */ +# define STM32_OPTION2_BASE 0x1ffff800 /* 0x1ffff800-0x1ffff80f: Option bytes 2 */ + /* 0x1ffff810-0x1fffffff: Reserved */ #endif /* System Memory Addresses **************************************************/ -#define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: LQFP64 * 1: WLCSP64 @@ -105,123 +105,123 @@ /* 0x2001c000-0x2001ffff: * 16Kb aliased by bit-banding */ -#define STM32L4_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32L4_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32L4_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ - /* 0x40016400-0x4001ffff: Reserved */ -#define STM32L4_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32L4_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ - /* 0x50060c00-0x5fffffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400163ff: APB2 */ + /* 0x40016400-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x50060bff: AHB2 */ + /* 0x50060c00-0x5fffffff: Reserved */ /* FSMC/QSPI Base Addresses *************************************************/ -#define STM32L4_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ +#define STM32_AHB3_BASE 0x60000000 /* 0x60000000-0xa0000fff: AHB3 */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32L4_LPTIM2_BASE 0x40009400 -#define STM32L4_SWPMI1_BASE 0x40008800 -#define STM32L4_I2C4_BASE 0x40008400 -#define STM32L4_LPUART1_BASE 0x40008000 -#define STM32L4_LPTIM1_BASE 0x40007c00 -#define STM32L4_OPAMP_BASE 0x40007800 -#define STM32L4_DAC_BASE 0x40007400 -#define STM32L4_PWR_BASE 0x40007000 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_SWPMI1_BASE 0x40008800 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 #if defined(CONFIG_STM32L4_STM32L4X3) -# define STM32L4_USB_SRAM_BASE 0x40006c00 -# define STM32L4_USB_FS_BASE 0x40006800 +# define STM32_USB_SRAM_BASE 0x40006c00 +# define STM32_USB_FS_BASE 0x40006800 #else -# define STM32L4_CAN2_BASE 0x40006800 +# define STM32_CAN2_BASE 0x40006800 #endif -#define STM32L4_CAN1_BASE 0x40006400 -#define STM32L4_CRS_BASE 0x40006000 -#define STM32L4_I2C3_BASE 0x40005c00 -#define STM32L4_I2C2_BASE 0x40005800 -#define STM32L4_I2C1_BASE 0x40005400 -#define STM32L4_UART5_BASE 0x40005000 -#define STM32L4_UART4_BASE 0x40004c00 -#define STM32L4_USART3_BASE 0x40004800 -#define STM32L4_USART2_BASE 0x40004400 -#define STM32L4_SPI3_BASE 0x40003c00 -#define STM32L4_SPI2_BASE 0x40003800 -#define STM32L4_IWDG_BASE 0x40003000 -#define STM32L4_WWDG_BASE 0x40002c00 -#define STM32L4_RTC_BASE 0x40002800 -#define STM32L4_LCD_BASE 0x40002400 -#define STM32L4_TIM7_BASE 0x40001400 -#define STM32L4_TIM6_BASE 0x40001000 -#define STM32L4_TIM5_BASE 0x40000c00 -#define STM32L4_TIM4_BASE 0x40000800 -#define STM32L4_TIM3_BASE 0x40000400 -#define STM32L4_TIM2_BASE 0x40000000 +#define STM32_CAN1_BASE 0x40006400 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004c00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003c00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_LCD_BASE 0x40002400 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000c00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L4_DSI_BASE 0x40016c00 -#define STM32L4_LTDC_BASE 0x40016800 -#define STM32L4_DFSDM_BASE 0x40016000 -#define STM32L4_SAI2_BASE 0x40015800 -#define STM32L4_SAI1_BASE 0x40015400 -#define STM32L4_TIM17_BASE 0x40014800 -#define STM32L4_TIM16_BASE 0x40014400 -#define STM32L4_TIM15_BASE 0x40014000 -#define STM32L4_USART1_BASE 0x40013800 -#define STM32L4_TIM8_BASE 0x40013400 -#define STM32L4_SPI1_BASE 0x40013000 -#define STM32L4_TIM1_BASE 0x40012c00 +#define STM32_DSI_BASE 0x40016c00 +#define STM32_LTDC_BASE 0x40016800 +#define STM32_DFSDM_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012c00 #ifndef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x40012800 +# define STM32_SDMMC1_BASE 0x40012800 #endif -#define STM32L4_FIREWALL_BASE 0x40011c00 -#define STM32L4_EXTI_BASE 0x40010400 -#define STM32L4_COMP_BASE 0x40010200 -#define STM32L4_VREFBUF_BASE 0x40010030 -#define STM32L4_SYSCFG_BASE 0x40010000 +#define STM32_FIREWALL_BASE 0x40011c00 +#define STM32_EXTI_BASE 0x40010400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L4_GFXMMU_BASE 0x4002c000 -#define STM32L4_DMA2D_BASE 0x4002b000 -#define STM32L4_TSC_BASE 0x40024000 -#define STM32L4_CRC_BASE 0x40023000 -#define STM32L4_FLASHIF_BASE 0x40022000 -#define STM32L4_RCC_BASE 0x40021000 -#define STM32L4_DMAMUX1_BASE 0x40020800 -#define STM32L4_DMA2_BASE 0x40020400 -#define STM32L4_DMA1_BASE 0x40020000 +#define STM32_GFXMMU_BASE 0x4002c000 +#define STM32_DMA2D_BASE 0x4002b000 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ #ifdef CONFIG_STM32L4_STM32L4XR -# define STM32L4_SDMMC1_BASE 0x50062400 +# define STM32_SDMMC1_BASE 0x50062400 #endif -#define STM32L4_OCTOSPIIOM_BASE 0x50061c00 -#define STM32L4_RNG_BASE 0x50060800 -#define STM32L4_HASH_BASE 0x50060400 -#define STM32L4_AES_BASE 0x50060000 -#define STM32L4_DCMI_BASE 0x50050000 -#define STM32L4_ADC_BASE 0x50040000 -# define STM32L4_ADC1_BASE 0x50040000 /* ADC1 */ -# define STM32L4_ADC2_BASE 0x50040100 /* ADC2 */ -# define STM32L4_ADC3_BASE 0x50040200 /* ADC3 */ -# define STM32L4_ADCCMN_BASE 0x50040300 /* Common */ -#define STM32L4_OTGFS_BASE 0x50000000 -#define STM32L4_GPIOI_BASE 0x48002000 -#define STM32L4_GPIOH_BASE 0x48001c00 -#define STM32L4_GPIOG_BASE 0x48001800 -#define STM32L4_GPIOF_BASE 0x48001400 -#define STM32L4_GPIOE_BASE 0x48001000 -#define STM32L4_GPIOD_BASE 0x48000c00 -#define STM32L4_GPIOC_BASE 0x48000800 -#define STM32L4_GPIOB_BASE 0x48000400 -#define STM32L4_GPIOA_BASE 0x48000000 +#define STM32_OCTOSPIIOM_BASE 0x50061c00 +#define STM32_RNG_BASE 0x50060800 +#define STM32_HASH_BASE 0x50060400 +#define STM32_AES_BASE 0x50060000 +#define STM32_DCMI_BASE 0x50050000 +#define STM32_ADC_BASE 0x50040000 +# define STM32_ADC1_BASE 0x50040000 /* ADC1 */ +# define STM32_ADC2_BASE 0x50040100 /* ADC2 */ +# define STM32_ADC3_BASE 0x50040200 /* ADC3 */ +# define STM32_ADCCMN_BASE 0x50040300 /* Common */ +#define STM32_OTGFS_BASE 0x50000000 +#define STM32_GPIOI_BASE 0x48002000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_GPIOG_BASE 0x48001800 +#define STM32_GPIOF_BASE 0x48001400 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* Cortex-M4 Base Addresses *************************************************/ @@ -229,7 +229,7 @@ * this address range */ -#define STM32L4_SCS_BASE 0xe000e000 -#define STM32L4_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index ab598f0c70a..a6aaf5eba1e 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -36,64 +36,64 @@ /* Register Offsets *********************************************************/ -#define STM32L4_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L4_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L4_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L4_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L4_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L4_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L4_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L4_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L4_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L4_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L4_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L4_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L4_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L4_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L4_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L4_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L4_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L4_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L4_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L4_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L4_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L4_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ -#define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ +#define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ +# define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ #endif /* Register Addresses *******************************************************/ -#define STM32L4_PWR_CR1 (STM32L4_PWR_BASE+STM32L4_PWR_CR1_OFFSET) -#define STM32L4_PWR_CR2 (STM32L4_PWR_BASE+STM32L4_PWR_CR2_OFFSET) -#define STM32L4_PWR_CR3 (STM32L4_PWR_BASE+STM32L4_PWR_CR3_OFFSET) -#define STM32L4_PWR_CR4 (STM32L4_PWR_BASE+STM32L4_PWR_CR4_OFFSET) -#define STM32L4_PWR_SR1 (STM32L4_PWR_BASE+STM32L4_PWR_SR1_OFFSET) -#define STM32L4_PWR_SR2 (STM32L4_PWR_BASE+STM32L4_PWR_SR2_OFFSET) -#define STM32L4_PWR_SCR (STM32L4_PWR_BASE+STM32L4_PWR_SCR_OFFSET) -#define STM32L4_PWR_PUCRA (STM32L4_PWR_BASE+STM32L4_PWR_PUCRA_OFFSET) -#define STM32L4_PWR_PDCRA (STM32L4_PWR_BASE+STM32L4_PWR_PDCRA_OFFSET) -#define STM32L4_PWR_PUCRB (STM32L4_PWR_BASE+STM32L4_PWR_PUCRB_OFFSET) -#define STM32L4_PWR_PDCRB (STM32L4_PWR_BASE+STM32L4_PWR_PDCRB_OFFSET) -#define STM32L4_PWR_PUCRC (STM32L4_PWR_BASE+STM32L4_PWR_PUCRC_OFFSET) -#define STM32L4_PWR_PDCRC (STM32L4_PWR_BASE+STM32L4_PWR_PDCRC_OFFSET) -#define STM32L4_PWR_PUCRD (STM32L4_PWR_BASE+STM32L4_PWR_PUCRD_OFFSET) -#define STM32L4_PWR_PDCRD (STM32L4_PWR_BASE+STM32L4_PWR_PDCRD_OFFSET) -#define STM32L4_PWR_PUCRE (STM32L4_PWR_BASE+STM32L4_PWR_PUCRE_OFFSET) -#define STM32L4_PWR_PDCRE (STM32L4_PWR_BASE+STM32L4_PWR_PDCRE_OFFSET) -#define STM32L4_PWR_PUCRF (STM32L4_PWR_BASE+STM32L4_PWR_PUCRF_OFFSET) -#define STM32L4_PWR_PDCRF (STM32L4_PWR_BASE+STM32L4_PWR_PDCRF_OFFSET) -#define STM32L4_PWR_PUCRG (STM32L4_PWR_BASE+STM32L4_PWR_PUCRG_OFFSET) -#define STM32L4_PWR_PDCRG (STM32L4_PWR_BASE+STM32L4_PWR_PDCRG_OFFSET) -#define STM32L4_PWR_PUCRH (STM32L4_PWR_BASE+STM32L4_PWR_PUCRH_OFFSET) -#define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET) -#define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET) -#define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE+STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE+STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE+STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE+STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE+STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE+STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE+STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE+STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET) +#define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET) #if defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET) +# define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h index 3a1b8214d2c..c4b08173978 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_qspi.h @@ -38,40 +38,40 @@ /* General Characteristics **************************************************/ -#define STM32L4_QSPI_MINBITS 8 /* Minimum word width */ -#define STM32L4_QSPI_MAXBITS 32 /* Maximum word width */ +#define STM32_QSPI_MINBITS 8 /* Minimum word width */ +#define STM32_QSPI_MAXBITS 32 /* Maximum word width */ /* QSPI register offsets ****************************************************/ -#define STM32L4_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ -#define STM32L4_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ -#define STM32L4_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ -#define STM32L4_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ -#define STM32L4_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ -#define STM32L4_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR_OFFSET 0x0000 /* Control Register */ +#define STM32_QUADSPI_DCR_OFFSET 0x0004 /* Device Configuration Register */ +#define STM32_QUADSPI_SR_OFFSET 0x0008 /* Status Register */ +#define STM32_QUADSPI_FCR_OFFSET 0x000c /* Flag Clear Register */ +#define STM32_QUADSPI_DLR_OFFSET 0x0010 /* Data Length Register */ +#define STM32_QUADSPI_CCR_OFFSET 0x0014 /* Communication Configuration Register */ +#define STM32_QUADSPI_AR_OFFSET 0x0018 /* Address Register */ +#define STM32_QUADSPI_ABR_OFFSET 0x001c /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR_OFFSET 0x0020 /* Data Register */ +#define STM32_QUADSPI_PSMKR_OFFSET 0x0024 /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR_OFFSET 0x0028 /* Polling Status match Register */ +#define STM32_QUADSPI_PIR_OFFSET 0x002c /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR_OFFSET 0x0030 /* Low-Power Timeout Register */ /* QSPI register addresses **************************************************/ -#define STM32L4_QUADSPI_CR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CR_OFFSET) /* Control Register */ -#define STM32L4_QUADSPI_DCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ -#define STM32L4_QUADSPI_SR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_SR_OFFSET) /* Status Register */ -#define STM32L4_QUADSPI_FCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ -#define STM32L4_QUADSPI_DLR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DLR_OFFSET) /* Data Length Register */ -#define STM32L4_QUADSPI_CCR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ -#define STM32L4_QUADSPI_AR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_AR_OFFSET) /* Address Register */ -#define STM32L4_QUADSPI_ABR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ -#define STM32L4_QUADSPI_DR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_DR_OFFSET) /* Data Register */ -#define STM32L4_QUADSPI_PSMKR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ -#define STM32L4_QUADSPI_PSMAR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ -#define STM32L4_QUADSPI_PIR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ -#define STM32L4_QUADSPI_LPTR (STM32L4_QSPI_BASE+STM32L4_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ +#define STM32_QUADSPI_CR (STM32_QSPI_BASE+STM32_QUADSPI_CR_OFFSET) /* Control Register */ +#define STM32_QUADSPI_DCR (STM32_QSPI_BASE+STM32_QUADSPI_DCR_OFFSET) /* Device Configuration Register */ +#define STM32_QUADSPI_SR (STM32_QSPI_BASE+STM32_QUADSPI_SR_OFFSET) /* Status Register */ +#define STM32_QUADSPI_FCR (STM32_QSPI_BASE+STM32_QUADSPI_FCR_OFFSET) /* Flag Clear Register */ +#define STM32_QUADSPI_DLR (STM32_QSPI_BASE+STM32_QUADSPI_DLR_OFFSET) /* Data Length Register */ +#define STM32_QUADSPI_CCR (STM32_QSPI_BASE+STM32_QUADSPI_CCR_OFFSET) /* Communication Configuration Register */ +#define STM32_QUADSPI_AR (STM32_QSPI_BASE+STM32_QUADSPI_AR_OFFSET) /* Address Register */ +#define STM32_QUADSPI_ABR (STM32_QSPI_BASE+STM32_QUADSPI_ABR_OFFSET) /* Alternate Bytes Register */ +#define STM32_QUADSPI_DR (STM32_QSPI_BASE+STM32_QUADSPI_DR_OFFSET) /* Data Register */ +#define STM32_QUADSPI_PSMKR (STM32_QSPI_BASE+STM32_QUADSPI_PSMKR_OFFSET) /* Polling Status mask Register */ +#define STM32_QUADSPI_PSMAR (STM32_QSPI_BASE+STM32_QUADSPI_PSMAR_OFFSET) /* Polling Status match Register */ +#define STM32_QUADSPI_PIR (STM32_QSPI_BASE+STM32_QUADSPI_PIR_OFFSET) /* Polling Interval Register */ +#define STM32_QUADSPI_LPTR (STM32_QSPI_BASE+STM32_QUADSPI_LPTR_OFFSET) /* Low-Power Timeout Register */ /* QSPI register bit definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h index 387776eb2ab..b038e5cef49 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rng.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rng.h @@ -36,15 +36,15 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ -#define STM32L4_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ -#define STM32L4_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ +#define STM32_RNG_CR_OFFSET 0x0000 /* RNG Control Register */ +#define STM32_RNG_SR_OFFSET 0x0004 /* RNG Status Register */ +#define STM32_RNG_DR_OFFSET 0x0008 /* RNG Data Register */ /* Register Addresses *******************************************************/ -#define STM32L4_RNG_CR (STM32L4_RNG_BASE+STM32L4_RNG_CR_OFFSET) -#define STM32L4_RNG_SR (STM32L4_RNG_BASE+STM32L4_RNG_SR_OFFSET) -#define STM32L4_RNG_DR (STM32L4_RNG_BASE+STM32L4_RNG_DR_OFFSET) +#define STM32_RNG_CR (STM32_RNG_BASE+STM32_RNG_CR_OFFSET) +#define STM32_RNG_SR (STM32_RNG_BASE+STM32_RNG_SR_OFFSET) +#define STM32_RNG_DR (STM32_RNG_BASE+STM32_RNG_DR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h index d2f1ad30b08..89ae64ee1ba 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_rtcc.h @@ -29,117 +29,117 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32L4_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32L4_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32L4_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32L4_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32L4_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32L4_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32L4_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32L4_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32L4_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32L4_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32L4_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32L4_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32L4_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32L4_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32L4_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32L4_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32L4_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32L4_RTC_OR_OFFSET 0x004c /* RTC option register */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ -#define STM32L4_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) -#define STM32L4_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32L4_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32L4_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32L4_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32L4_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32L4_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32L4_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32L4_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32L4_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32L4_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32L4_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32L4_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32L4_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32L4_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32L4_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32L4_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32L4_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32L4_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32L4_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32L4_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ -#define STM32L4_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ -#define STM32L4_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ -#define STM32L4_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ -#define STM32L4_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ -#define STM32L4_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ -#define STM32L4_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ -#define STM32L4_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ -#define STM32L4_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ -#define STM32L4_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ -#define STM32L4_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ -#define STM32L4_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ -#define STM32L4_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ /* Register Addresses *******************************************************/ -#define STM32L4_RTC_TR (STM32L4_RTC_BASE+STM32L4_RTC_TR_OFFSET) -#define STM32L4_RTC_DR (STM32L4_RTC_BASE+STM32L4_RTC_DR_OFFSET) -#define STM32L4_RTC_CR (STM32L4_RTC_BASE+STM32L4_RTC_CR_OFFSET) -#define STM32L4_RTC_ISR (STM32L4_RTC_BASE+STM32L4_RTC_ISR_OFFSET) -#define STM32L4_RTC_PRER (STM32L4_RTC_BASE+STM32L4_RTC_PRER_OFFSET) -#define STM32L4_RTC_WUTR (STM32L4_RTC_BASE+STM32L4_RTC_WUTR_OFFSET) -#define STM32L4_RTC_ALRMAR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMAR_OFFSET) -#define STM32L4_RTC_ALRMBR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBR_OFFSET) -#define STM32L4_RTC_WPR (STM32L4_RTC_BASE+STM32L4_RTC_WPR_OFFSET) -#define STM32L4_RTC_SSR (STM32L4_RTC_BASE+STM32L4_RTC_SSR_OFFSET) -#define STM32L4_RTC_SHIFTR (STM32L4_RTC_BASE+STM32L4_RTC_SHIFTR_OFFSET) -#define STM32L4_RTC_TSTR (STM32L4_RTC_BASE+STM32L4_RTC_TSTR_OFFSET) -#define STM32L4_RTC_TSDR (STM32L4_RTC_BASE+STM32L4_RTC_TSDR_OFFSET) -#define STM32L4_RTC_TSSSR (STM32L4_RTC_BASE+STM32L4_RTC_TSSSR_OFFSET) -#define STM32L4_RTC_CALR (STM32L4_RTC_BASE+STM32L4_RTC_CALR_OFFSET) -#define STM32L4_RTC_TAMPCR (STM32L4_RTC_BASE+STM32L4_RTC_TAMPCR_OFFSET) -#define STM32L4_RTC_ALRMASSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMASSR_OFFSET) -#define STM32L4_RTC_ALRMBSSR (STM32L4_RTC_BASE+STM32L4_RTC_ALRMBSSR_OFFSET) -#define STM32L4_RTC_OR (STM32L4_RTC_BASE+STM32L4_RTC_OR_OFFSET) +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE+STM32_RTC_OR_OFFSET) -#define STM32L4_RTC_BKR(n) (STM32L4_RTC_BASE+STM32L4_RTC_BKR_OFFSET(n)) -#define STM32L4_RTC_BK0R (STM32L4_RTC_BASE+STM32L4_RTC_BK0R_OFFSET) -#define STM32L4_RTC_BK1R (STM32L4_RTC_BASE+STM32L4_RTC_BK1R_OFFSET) -#define STM32L4_RTC_BK2R (STM32L4_RTC_BASE+STM32L4_RTC_BK2R_OFFSET) -#define STM32L4_RTC_BK3R (STM32L4_RTC_BASE+STM32L4_RTC_BK3R_OFFSET) -#define STM32L4_RTC_BK4R (STM32L4_RTC_BASE+STM32L4_RTC_BK4R_OFFSET) -#define STM32L4_RTC_BK5R (STM32L4_RTC_BASE+STM32L4_RTC_BK5R_OFFSET) -#define STM32L4_RTC_BK6R (STM32L4_RTC_BASE+STM32L4_RTC_BK6R_OFFSET) -#define STM32L4_RTC_BK7R (STM32L4_RTC_BASE+STM32L4_RTC_BK7R_OFFSET) -#define STM32L4_RTC_BK8R (STM32L4_RTC_BASE+STM32L4_RTC_BK8R_OFFSET) -#define STM32L4_RTC_BK9R (STM32L4_RTC_BASE+STM32L4_RTC_BK9R_OFFSET) -#define STM32L4_RTC_BK10R (STM32L4_RTC_BASE+STM32L4_RTC_BK10R_OFFSET) -#define STM32L4_RTC_BK11R (STM32L4_RTC_BASE+STM32L4_RTC_BK11R_OFFSET) -#define STM32L4_RTC_BK12R (STM32L4_RTC_BASE+STM32L4_RTC_BK12R_OFFSET) -#define STM32L4_RTC_BK13R (STM32L4_RTC_BASE+STM32L4_RTC_BK13R_OFFSET) -#define STM32L4_RTC_BK14R (STM32L4_RTC_BASE+STM32L4_RTC_BK14R_OFFSET) -#define STM32L4_RTC_BK15R (STM32L4_RTC_BASE+STM32L4_RTC_BK15R_OFFSET) -#define STM32L4_RTC_BK16R (STM32L4_RTC_BASE+STM32L4_RTC_BK16R_OFFSET) -#define STM32L4_RTC_BK17R (STM32L4_RTC_BASE+STM32L4_RTC_BK17R_OFFSET) -#define STM32L4_RTC_BK18R (STM32L4_RTC_BASE+STM32L4_RTC_BK18R_OFFSET) -#define STM32L4_RTC_BK19R (STM32L4_RTC_BASE+STM32L4_RTC_BK19R_OFFSET) -#define STM32L4_RTC_BK20R (STM32L4_RTC_BASE+STM32L4_RTC_BK20R_OFFSET) -#define STM32L4_RTC_BK21R (STM32L4_RTC_BASE+STM32L4_RTC_BK21R_OFFSET) -#define STM32L4_RTC_BK22R (STM32L4_RTC_BASE+STM32L4_RTC_BK22R_OFFSET) -#define STM32L4_RTC_BK23R (STM32L4_RTC_BASE+STM32L4_RTC_BK23R_OFFSET) -#define STM32L4_RTC_BK24R (STM32L4_RTC_BASE+STM32L4_RTC_BK24R_OFFSET) -#define STM32L4_RTC_BK25R (STM32L4_RTC_BASE+STM32L4_RTC_BK25R_OFFSET) -#define STM32L4_RTC_BK26R (STM32L4_RTC_BASE+STM32L4_RTC_BK26R_OFFSET) -#define STM32L4_RTC_BK27R (STM32L4_RTC_BASE+STM32L4_RTC_BK27R_OFFSET) -#define STM32L4_RTC_BK28R (STM32L4_RTC_BASE+STM32L4_RTC_BK28R_OFFSET) -#define STM32L4_RTC_BK29R (STM32L4_RTC_BASE+STM32L4_RTC_BK29R_OFFSET) -#define STM32L4_RTC_BK30R (STM32L4_RTC_BASE+STM32L4_RTC_BK30R_OFFSET) -#define STM32L4_RTC_BK31R (STM32L4_RTC_BASE+STM32L4_RTC_BK31R_OFFSET) +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) -# define STM32L4_RTC_BKCOUNT 32 +# define STM32_RTC_BKCOUNT 32 /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h index ea33be29c52..d474d0a66c7 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_sai.h @@ -36,67 +36,67 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ +#define STM32_SAI_GCR_OFFSET 0x0000 /* SAI Global Configuration Register */ -#define STM32L4_SAI_A_OFFSET 0x0004 -#define STM32L4_SAI_B_OFFSET 0x0024 +#define STM32_SAI_A_OFFSET 0x0004 +#define STM32_SAI_B_OFFSET 0x0024 -#define STM32L4_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ -#define STM32L4_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ -#define STM32L4_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ -#define STM32L4_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ -#define STM32L4_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ -#define STM32L4_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ -#define STM32L4_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ -#define STM32L4_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ +#define STM32_SAI_CR1_OFFSET 0x0000 /* SAI Configuration Register 1 A */ +#define STM32_SAI_CR2_OFFSET 0x0004 /* SAI Configuration Register 2 A */ +#define STM32_SAI_FRCR_OFFSET 0x0008 /* SAI Frame Configuration Register A */ +#define STM32_SAI_SLOTR_OFFSET 0x000c /* SAI Slot Register A */ +#define STM32_SAI_IM_OFFSET 0x0010 /* SAI Interrupt Mask Register 2 A */ +#define STM32_SAI_SR_OFFSET 0x0014 /* SAI Status Register A */ +#define STM32_SAI_CLRFR_OFFSET 0x0018 /* SAI Clear Flag Register A */ +#define STM32_SAI_DR_OFFSET 0x001c /* SAI Data Register A */ /* Register Addresses *******************************************************/ -#define STM32L4_SAI1_GCR (STM32L4_SAI_GCR_OFFSET) +#define STM32_SAI1_GCR (STM32_SAI_GCR_OFFSET) -#define STM32L4_SAI1_A_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI1_B_BASE (STM32L4_SAI1_BASE+STM32L4_SAI_B_OFFSET) +#define STM32_SAI1_A_BASE (STM32_SAI1_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI1_B_BASE (STM32_SAI1_BASE+STM32_SAI_B_OFFSET) -#define STM32L4_SAI1_ACR1 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI1_ACR2 (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI1_AFRCR (STM32L4_SAI1_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI1_ASLOTR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI1_AIM (STM32L4_SAI1_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI1_ASR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI1_ACLRFR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI1_ADR (STM32L4_SAI1_A_BASE+STM32L4_SAI_ADR_OFFSET) +#define STM32_SAI1_ACR1 (STM32_SAI1_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI1_ACR2 (STM32_SAI1_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI1_AFRCR (STM32_SAI1_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI1_ASLOTR (STM32_SAI1_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI1_AIM (STM32_SAI1_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI1_ASR (STM32_SAI1_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI1_ACLRFR (STM32_SAI1_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI1_ADR (STM32_SAI1_A_BASE+STM32_SAI_ADR_OFFSET) -#define STM32L4_SAI1_BCR1 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI1_BCR2 (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI1_BFRCR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI1_BSLOTR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI1_BIM (STM32L4_SAI1_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI1_BSR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI1_BCLRFR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI1_BDR (STM32L4_SAI1_B_BASE+STM32L4_SAI_BDR_OFFSET) +#define STM32_SAI1_BCR1 (STM32_SAI1_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI1_BCR2 (STM32_SAI1_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI1_BFRCR (STM32_SAI1_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI1_BSLOTR (STM32_SAI1_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI1_BIM (STM32_SAI1_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI1_BSR (STM32_SAI1_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI1_BCLRFR (STM32_SAI1_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI1_BDR (STM32_SAI1_B_BASE+STM32_SAI_BDR_OFFSET) -#define STM32L4_SAI2_GCR (STM32L4_SAI2_BASE+STM32L4_SAI_GCR_OFFSET) +#define STM32_SAI2_GCR (STM32_SAI2_BASE+STM32_SAI_GCR_OFFSET) -#define STM32L4_SAI2_A_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_A_OFFSET) -#define STM32L4_SAI2_B_BASE (STM32L4_SAI2_BASE+STM32L4_SAI_B_OFFSET) +#define STM32_SAI2_A_BASE (STM32_SAI2_BASE+STM32_SAI_A_OFFSET) +#define STM32_SAI2_B_BASE (STM32_SAI2_BASE+STM32_SAI_B_OFFSET) -#define STM32L4_SAI2_ACR1 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR1_OFFSET) -#define STM32L4_SAI2_ACR2 (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACR2_OFFSET) -#define STM32L4_SAI2_AFRCR (STM32L4_SAI2_A_BASE+STM32L4_SAI_AFRCR_OFFSET) -#define STM32L4_SAI2_ASLOTR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASLOTR_OFFSET) -#define STM32L4_SAI2_AIM (STM32L4_SAI2_A_BASE+STM32L4_SAI_AIM_OFFSET) -#define STM32L4_SAI2_ASR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ASR_OFFSET) -#define STM32L4_SAI2_ACLRFR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ACLRFR_OFFSET) -#define STM32L4_SAI2_ADR (STM32L4_SAI2_A_BASE+STM32L4_SAI_ADR_OFFSET) +#define STM32_SAI2_ACR1 (STM32_SAI2_A_BASE+STM32_SAI_ACR1_OFFSET) +#define STM32_SAI2_ACR2 (STM32_SAI2_A_BASE+STM32_SAI_ACR2_OFFSET) +#define STM32_SAI2_AFRCR (STM32_SAI2_A_BASE+STM32_SAI_AFRCR_OFFSET) +#define STM32_SAI2_ASLOTR (STM32_SAI2_A_BASE+STM32_SAI_ASLOTR_OFFSET) +#define STM32_SAI2_AIM (STM32_SAI2_A_BASE+STM32_SAI_AIM_OFFSET) +#define STM32_SAI2_ASR (STM32_SAI2_A_BASE+STM32_SAI_ASR_OFFSET) +#define STM32_SAI2_ACLRFR (STM32_SAI2_A_BASE+STM32_SAI_ACLRFR_OFFSET) +#define STM32_SAI2_ADR (STM32_SAI2_A_BASE+STM32_SAI_ADR_OFFSET) -#define STM32L4_SAI2_BCR1 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR1_OFFSET) -#define STM32L4_SAI2_BCR2 (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCR2_OFFSET) -#define STM32L4_SAI2_BFRCR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BFRCR_OFFSET) -#define STM32L4_SAI2_BSLOTR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSLOTR_OFFSET) -#define STM32L4_SAI2_BIM (STM32L4_SAI2_B_BASE+STM32L4_SAI_BIM_OFFSET) -#define STM32L4_SAI2_BSR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BSR_OFFSET) -#define STM32L4_SAI2_BCLRFR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BCLRFR_OFFSET) -#define STM32L4_SAI2_BDR (STM32L4_SAI2_B_BASE+STM32L4_SAI_BDR_OFFSET) +#define STM32_SAI2_BCR1 (STM32_SAI2_B_BASE+STM32_SAI_BCR1_OFFSET) +#define STM32_SAI2_BCR2 (STM32_SAI2_B_BASE+STM32_SAI_BCR2_OFFSET) +#define STM32_SAI2_BFRCR (STM32_SAI2_B_BASE+STM32_SAI_BFRCR_OFFSET) +#define STM32_SAI2_BSLOTR (STM32_SAI2_B_BASE+STM32_SAI_BSLOTR_OFFSET) +#define STM32_SAI2_BIM (STM32_SAI2_B_BASE+STM32_SAI_BIM_OFFSET) +#define STM32_SAI2_BSR (STM32_SAI2_B_BASE+STM32_SAI_BSR_OFFSET) +#define STM32_SAI2_BCLRFR (STM32_SAI2_B_BASE+STM32_SAI_BCLRFR_OFFSET) +#define STM32_SAI2_BDR (STM32_SAI2_B_BASE+STM32_SAI_BDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h index 6098c3949d3..cada1d6e980 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_spi.h @@ -36,48 +36,48 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32L4_SPI_CLK_MAX 40000000UL +#define STM32_SPI_CLK_MAX 40000000UL /* Register Offsets *********************************************************/ -#define STM32L4_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L4_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L4_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L4_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L4_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L4_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L4_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L4_NSPI > 0 -# define STM32L4_SPI1_CR1 (STM32L4_SPI1_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI1_CR2 (STM32L4_SPI1_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI1_SR (STM32L4_SPI1_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI1_DR (STM32L4_SPI1_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI1_CRCPR (STM32L4_SPI1_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI1_RXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI1_TXCRCR (STM32L4_SPI1_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 1 -# define STM32L4_SPI2_CR1 (STM32L4_SPI2_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI2_CR2 (STM32L4_SPI2_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI2_SR (STM32L4_SPI2_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI2_DR (STM32L4_SPI2_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI2_CRCPR (STM32L4_SPI2_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI2_RXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI2_TXCRCR (STM32L4_SPI2_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L4_NSPI > 2 -# define STM32L4_SPI3_CR1 (STM32L4_SPI3_BASE+STM32L4_SPI_CR1_OFFSET) -# define STM32L4_SPI3_CR2 (STM32L4_SPI3_BASE+STM32L4_SPI_CR2_OFFSET) -# define STM32L4_SPI3_SR (STM32L4_SPI3_BASE+STM32L4_SPI_SR_OFFSET) -# define STM32L4_SPI3_DR (STM32L4_SPI3_BASE+STM32L4_SPI_DR_OFFSET) -# define STM32L4_SPI3_CRCPR (STM32L4_SPI3_BASE+STM32L4_SPI_CRCPR_OFFSET) -# define STM32L4_SPI3_RXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_RXCRCR_OFFSET) -# define STM32L4_SPI3_TXCRCR (STM32L4_SPI3_BASE+STM32L4_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h index b643e79014e..0c632105d7f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L4_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L4_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L4_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L4_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L4_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L4_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L4_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L4_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L4_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L4_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L4_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L4_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L4_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L4_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L4_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L4_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L4_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L4_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L4_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L4_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L4_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L4_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L4_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L4_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L4_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L4_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L4_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L4_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L4_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L4_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L4_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L4_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L4_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L4_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L4_TIM1_CR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM1_CR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM1_SMCR (STM32L4_TIM1_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM1_DIER (STM32L4_TIM1_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM1_SR (STM32L4_TIM1_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM1_EGR (STM32L4_TIM1_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM1_CCMR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM1_CCMR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM1_CCER (STM32L4_TIM1_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM1_CNT (STM32L4_TIM1_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM1_PSC (STM32L4_TIM1_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM1_ARR (STM32L4_TIM1_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM1_RCR (STM32L4_TIM1_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM1_CCR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM1_CCR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM1_CCR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM1_CCR4 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM1_BDTR (STM32L4_TIM1_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM1_DCR (STM32L4_TIM1_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM1_DMAR (STM32L4_TIM1_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM1_OR1 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM1_CCMR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM1_CCR5 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM1_CCR6 (STM32L4_TIM1_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM1_OR2 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM1_OR3 (STM32L4_TIM1_BASE+STM32L4_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) -#define STM32L4_TIM8_CR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR1_OFFSET) -#define STM32L4_TIM8_CR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CR2_OFFSET) -#define STM32L4_TIM8_SMCR (STM32L4_TIM8_BASE+STM32L4_ATIM_SMCR_OFFSET) -#define STM32L4_TIM8_DIER (STM32L4_TIM8_BASE+STM32L4_ATIM_DIER_OFFSET) -#define STM32L4_TIM8_SR (STM32L4_TIM8_BASE+STM32L4_ATIM_SR_OFFSET) -#define STM32L4_TIM8_EGR (STM32L4_TIM8_BASE+STM32L4_ATIM_EGR_OFFSET) -#define STM32L4_TIM8_CCMR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR1_OFFSET) -#define STM32L4_TIM8_CCMR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR2_OFFSET) -#define STM32L4_TIM8_CCER (STM32L4_TIM8_BASE+STM32L4_ATIM_CCER_OFFSET) -#define STM32L4_TIM8_CNT (STM32L4_TIM8_BASE+STM32L4_ATIM_CNT_OFFSET) -#define STM32L4_TIM8_PSC (STM32L4_TIM8_BASE+STM32L4_ATIM_PSC_OFFSET) -#define STM32L4_TIM8_ARR (STM32L4_TIM8_BASE+STM32L4_ATIM_ARR_OFFSET) -#define STM32L4_TIM8_RCR (STM32L4_TIM8_BASE+STM32L4_ATIM_RCR_OFFSET) -#define STM32L4_TIM8_CCR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR1_OFFSET) -#define STM32L4_TIM8_CCR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR2_OFFSET) -#define STM32L4_TIM8_CCR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR3_OFFSET) -#define STM32L4_TIM8_CCR4 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR4_OFFSET) -#define STM32L4_TIM8_BDTR (STM32L4_TIM8_BASE+STM32L4_ATIM_BDTR_OFFSET) -#define STM32L4_TIM8_DCR (STM32L4_TIM8_BASE+STM32L4_ATIM_DCR_OFFSET) -#define STM32L4_TIM8_DMAR (STM32L4_TIM8_BASE+STM32L4_ATIM_DMAR_OFFSET) -#define STM32L4_TIM8_OR1 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR1_OFFSET) -#define STM32L4_TIM8_CCMR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCMR3_OFFSET) -#define STM32L4_TIM8_CCR5 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR5_OFFSET) -#define STM32L4_TIM8_CCR6 (STM32L4_TIM8_BASE+STM32L4_ATIM_CCR6_OFFSET) -#define STM32L4_TIM8_OR2 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR2_OFFSET) -#define STM32L4_TIM8_OR3 (STM32L4_TIM8_BASE+STM32L4_ATIM_OR3_OFFSET) +#define STM32_TIM8_CR1 (STM32_TIM8_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L4_TIM2_CR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM2_CR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM2_SMCR (STM32L4_TIM2_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM2_DIER (STM32L4_TIM2_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM2_SR (STM32L4_TIM2_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM2_EGR (STM32L4_TIM2_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM2_CCMR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM2_CCMR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM2_CCER (STM32L4_TIM2_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM2_CNT (STM32L4_TIM2_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM2_PSC (STM32L4_TIM2_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM2_ARR (STM32L4_TIM2_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM2_CCR1 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM2_CCR2 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM2_CCR3 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM2_CCR4 (STM32L4_TIM2_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM2_DCR (STM32L4_TIM2_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM2_DMAR (STM32L4_TIM2_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM2_OR (STM32L4_TIM2_BASE+STM32L4_GTIM_OR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) -#define STM32L4_TIM3_CR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM3_CR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM3_SMCR (STM32L4_TIM3_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM3_DIER (STM32L4_TIM3_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM3_SR (STM32L4_TIM3_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM3_EGR (STM32L4_TIM3_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM3_CCMR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM3_CCMR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM3_CCER (STM32L4_TIM3_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM3_CNT (STM32L4_TIM3_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM3_PSC (STM32L4_TIM3_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM3_ARR (STM32L4_TIM3_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM3_CCR1 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM3_CCR2 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM3_CCR3 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM3_CCR4 (STM32L4_TIM3_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM3_DCR (STM32L4_TIM3_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM3_DMAR (STM32L4_TIM3_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM3_CR1 (STM32_TIM3_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32L4_TIM4_CR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM4_CR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM4_SMCR (STM32L4_TIM4_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM4_DIER (STM32L4_TIM4_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM4_SR (STM32L4_TIM4_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM4_EGR (STM32L4_TIM4_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM4_CCMR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM4_CCMR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM4_CCER (STM32L4_TIM4_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM4_CNT (STM32L4_TIM4_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM4_PSC (STM32L4_TIM4_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM4_ARR (STM32L4_TIM4_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM4_CCR1 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM4_CCR2 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM4_CCR3 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM4_CCR4 (STM32L4_TIM4_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM4_DCR (STM32L4_TIM4_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM4_DMAR (STM32L4_TIM4_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM4_CR1 (STM32_TIM4_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32L4_TIM5_CR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM5_CR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM5_SMCR (STM32L4_TIM5_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM5_DIER (STM32L4_TIM5_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM5_SR (STM32L4_TIM5_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM5_EGR (STM32L4_TIM5_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM5_CCMR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM5_CCMR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCMR2_OFFSET) -#define STM32L4_TIM5_CCER (STM32L4_TIM5_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM5_CNT (STM32L4_TIM5_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM5_PSC (STM32L4_TIM5_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM5_ARR (STM32L4_TIM5_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM5_CCR1 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM5_CCR2 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM5_CCR3 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR3_OFFSET) -#define STM32L4_TIM5_CCR4 (STM32L4_TIM5_BASE+STM32L4_GTIM_CCR4_OFFSET) -#define STM32L4_TIM5_DCR (STM32L4_TIM5_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM5_DMAR (STM32L4_TIM5_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM5_OR (STM32L4_TIM5_BASE+STM32L4_GTIM_OR_OFFSET) +#define STM32_TIM5_CR1 (STM32_TIM5_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE+STM32_GTIM_OR_OFFSET) -#define STM32L4_TIM15_CR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM15_CR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM15_SMCR (STM32L4_TIM15_BASE+STM32L4_GTIM_SMCR_OFFSET) -#define STM32L4_TIM15_DIER (STM32L4_TIM15_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM15_SR (STM32L4_TIM15_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM15_EGR (STM32L4_TIM15_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM15_CCMR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM15_CCER (STM32L4_TIM15_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM15_CNT (STM32L4_TIM15_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM15_PSC (STM32L4_TIM15_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM15_ARR (STM32L4_TIM15_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM15_RCR (STM32L4_TIM15_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM15_CCR1 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM15_CCR2 (STM32L4_TIM15_BASE+STM32L4_GTIM_CCR2_OFFSET) -#define STM32L4_TIM15_BDTR (STM32L4_TIM15_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM15_DCR (STM32L4_TIM15_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM15_DMAR (STM32L4_TIM15_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM15_CR1 (STM32_TIM15_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE+STM32_GTIM_DMAR_OFFSET) -#define STM32L4_TIM16_CR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM16_CR2 (STM32L4_TIM16_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM16_DIER (STM32L4_TIM16_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM16_SR (STM32L4_TIM16_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM16_EGR (STM32L4_TIM16_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM16_CCMR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM16_CCER (STM32L4_TIM16_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM16_CNT (STM32L4_TIM16_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM16_PSC (STM32L4_TIM16_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM16_ARR (STM32L4_TIM16_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM16_RCR (STM32L4_TIM16_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM16_CCR1 (STM32L4_TIM16_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM16_BDTR (STM32L4_TIM16_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM16_DCR (STM32L4_TIM16_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM16_DMAR (STM32L4_TIM16_BASE+STM32L4_GTIM_DMAR_OFFSET) -#define STM32L4_TIM16_OR (STM32L4_TIM16_BASE+STM32L4_GTIM_OR_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) -#define STM32L4_TIM17_CR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR1_OFFSET) -#define STM32L4_TIM17_CR2 (STM32L4_TIM17_BASE+STM32L4_GTIM_CR2_OFFSET) -#define STM32L4_TIM17_DIER (STM32L4_TIM17_BASE+STM32L4_GTIM_DIER_OFFSET) -#define STM32L4_TIM17_SR (STM32L4_TIM17_BASE+STM32L4_GTIM_SR_OFFSET) -#define STM32L4_TIM17_EGR (STM32L4_TIM17_BASE+STM32L4_GTIM_EGR_OFFSET) -#define STM32L4_TIM17_CCMR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCMR1_OFFSET) -#define STM32L4_TIM17_CCER (STM32L4_TIM17_BASE+STM32L4_GTIM_CCER_OFFSET) -#define STM32L4_TIM17_CNT (STM32L4_TIM17_BASE+STM32L4_GTIM_CNT_OFFSET) -#define STM32L4_TIM17_PSC (STM32L4_TIM17_BASE+STM32L4_GTIM_PSC_OFFSET) -#define STM32L4_TIM17_ARR (STM32L4_TIM17_BASE+STM32L4_GTIM_ARR_OFFSET) -#define STM32L4_TIM17_RCR (STM32L4_TIM17_BASE+STM32L4_GTIM_RCR_OFFSET) -#define STM32L4_TIM17_CCR1 (STM32L4_TIM17_BASE+STM32L4_GTIM_CCR1_OFFSET) -#define STM32L4_TIM17_BDTR (STM32L4_TIM17_BASE+STM32L4_GTIM_BDTR_OFFSET) -#define STM32L4_TIM17_DCR (STM32L4_TIM17_BASE+STM32L4_GTIM_DCR_OFFSET) -#define STM32L4_TIM17_DMAR (STM32L4_TIM17_BASE+STM32L4_GTIM_DMAR_OFFSET) +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L4_TIM6_CR1 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM6_CR2 (STM32L4_TIM6_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM6_DIER (STM32L4_TIM6_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM6_SR (STM32L4_TIM6_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM6_EGR (STM32L4_TIM6_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM6_CNT (STM32L4_TIM6_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM6_PSC (STM32L4_TIM6_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM6_ARR (STM32L4_TIM6_BASE+STM32L4_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE+STM32_BTIM_ARR_OFFSET) -#define STM32L4_TIM7_CR1 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR1_OFFSET) -#define STM32L4_TIM7_CR2 (STM32L4_TIM7_BASE+STM32L4_BTIM_CR2_OFFSET) -#define STM32L4_TIM7_DIER (STM32L4_TIM7_BASE+STM32L4_BTIM_DIER_OFFSET) -#define STM32L4_TIM7_SR (STM32L4_TIM7_BASE+STM32L4_BTIM_SR_OFFSET) -#define STM32L4_TIM7_EGR (STM32L4_TIM7_BASE+STM32L4_BTIM_EGR_OFFSET) -#define STM32L4_TIM7_CNT (STM32L4_TIM7_BASE+STM32L4_BTIM_CNT_OFFSET) -#define STM32L4_TIM7_PSC (STM32L4_TIM7_BASE+STM32L4_BTIM_PSC_OFFSET) -#define STM32L4_TIM7_ARR (STM32L4_TIM7_BASE+STM32L4_BTIM_ARR_OFFSET) +#define STM32_TIM7_CR1 (STM32_TIM7_BASE+STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE+STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE+STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE+STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE+STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE+STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE+STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE+STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h index c904dba002a..d2d43e82eb0 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_uart.h @@ -37,88 +37,88 @@ /* Register Offsets *********************************************************/ -#define STM32L4_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L4_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L4_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L4_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L4_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L4_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L4_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L4_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L4_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L4_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L4_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ /* Register Addresses *******************************************************/ -#if STM32L4_NUSART > 0 -# define STM32L4_USART1_CR1 (STM32L4_USART1_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART1_CR2 (STM32L4_USART1_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART1_CR3 (STM32L4_USART1_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART1_BRR (STM32L4_USART1_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART1_GTPR (STM32L4_USART1_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART1_RTOR (STM32L4_USART1_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART1_RQR (STM32L4_USART1_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART1_ISR (STM32L4_USART1_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART1_ICR (STM32L4_USART1_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART1_RDR (STM32L4_USART1_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART1_TDR (STM32L4_USART1_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 1 -# define STM32L4_USART2_CR1 (STM32L4_USART2_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART2_CR2 (STM32L4_USART2_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART2_CR3 (STM32L4_USART2_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART2_BRR (STM32L4_USART2_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART2_GTPR (STM32L4_USART2_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART2_RTOR (STM32L4_USART2_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART2_RQR (STM32L4_USART2_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART2_ISR (STM32L4_USART2_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART2_ICR (STM32L4_USART2_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART2_RDR (STM32L4_USART2_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART2_TDR (STM32L4_USART2_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 2 -# define STM32L4_USART3_CR1 (STM32L4_USART3_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_USART3_CR2 (STM32L4_USART3_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_USART3_CR3 (STM32L4_USART3_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_USART3_BRR (STM32L4_USART3_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_USART3_GTPR (STM32L4_USART3_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_USART3_RTOR (STM32L4_USART3_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_USART3_RQR (STM32L4_USART3_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_USART3_ISR (STM32L4_USART3_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_USART3_ICR (STM32L4_USART3_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_USART3_RDR (STM32L4_USART3_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_USART3_TDR (STM32L4_USART3_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 3 -# define STM32L4_UART4_CR1 (STM32L4_UART4_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART4_CR2 (STM32L4_UART4_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART4_CR3 (STM32L4_UART4_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART4_BRR (STM32L4_UART4_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART4_GTPR (STM32L4_UART4_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART4_RTOR (STM32L4_UART4_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART4_RQR (STM32L4_UART4_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART4_ISR (STM32L4_UART4_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART4_ICR (STM32L4_UART4_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART4_RDR (STM32L4_UART4_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART4_TDR (STM32L4_UART4_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) #endif -#if STM32L4_NUSART > 4 -# define STM32L4_UART5_CR1 (STM32L4_UART5_BASE+STM32L4_USART_CR1_OFFSET) -# define STM32L4_UART5_CR2 (STM32L4_UART5_BASE+STM32L4_USART_CR2_OFFSET) -# define STM32L4_UART5_CR3 (STM32L4_UART5_BASE+STM32L4_USART_CR3_OFFSET) -# define STM32L4_UART5_BRR (STM32L4_UART5_BASE+STM32L4_USART_BRR_OFFSET) -# define STM32L4_UART5_GTPR (STM32L4_UART5_BASE+STM32L4_USART_GTPR_OFFSET) -# define STM32L4_UART5_RTOR (STM32L4_UART5_BASE+STM32L4_USART_RTOR_OFFSET) -# define STM32L4_UART5_RQR (STM32L4_UART5_BASE+STM32L4_USART_RQR_OFFSET) -# define STM32L4_UART5_ISR (STM32L4_UART5_BASE+STM32L4_USART_ISR_OFFSET) -# define STM32L4_UART5_ICR (STM32L4_UART5_BASE+STM32L4_USART_ICR_OFFSET) -# define STM32L4_UART5_RDR (STM32L4_UART5_BASE+STM32L4_USART_RDR_OFFSET) -# define STM32L4_UART5_TDR (STM32L4_UART5_BASE+STM32L4_USART_TDR_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index acea9cc7e31..1fdac887f95 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -40,71 +40,71 @@ /* Endpoint Registers */ -#define STM32L4_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ +#define STM32_USB_EPR_OFFSET(n) ((n) << 2) /* USB endpoint n register (16-bits) */ -#define STM32L4_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ -#define STM32L4_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ -#define STM32L4_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ -#define STM32L4_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ -#define STM32L4_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ -#define STM32L4_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ -#define STM32L4_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ -#define STM32L4_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ +#define STM32_USB_EP0R_OFFSET 0x0000 /* USB endpoint 0 register (16-bits) */ +#define STM32_USB_EP1R_OFFSET 0x0004 /* USB endpoint 1 register (16-bits) */ +#define STM32_USB_EP2R_OFFSET 0x0008 /* USB endpoint 2 register (16-bits) */ +#define STM32_USB_EP3R_OFFSET 0x000c /* USB endpoint 3 register (16-bits) */ +#define STM32_USB_EP4R_OFFSET 0x0010 /* USB endpoint 4 register (16-bits) */ +#define STM32_USB_EP5R_OFFSET 0x0014 /* USB endpoint 5 register (16-bits) */ +#define STM32_USB_EP6R_OFFSET 0x0018 /* USB endpoint 6 register (16-bits) */ +#define STM32_USB_EP7R_OFFSET 0x001c /* USB endpoint 7 register (16-bits) */ /* Common Registers */ -#define STM32L4_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ -#define STM32L4_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ -#define STM32L4_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ -#define STM32L4_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ -#define STM32L4_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ -#define STM32L4_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ -#define STM32L4_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ +#define STM32_USB_CNTR_OFFSET 0x0040 /* USB control register (16-bits) */ +#define STM32_USB_ISTR_OFFSET 0x0044 /* USB interrupt status register (16-bits) */ +#define STM32_USB_FNR_OFFSET 0x0048 /* USB frame number register (16-bits) */ +#define STM32_USB_DADDR_OFFSET 0x004c /* USB device address (16-bits) */ +#define STM32_USB_BTABLE_OFFSET 0x0050 /* Buffer table address (16-bits) */ +#define STM32_USB_LPMCSR_OFFSET 0x0054 /* LPM control and status register */ +#define STM32_USB_BCDR_OFFSET 0x0058 /* Battery charging detector */ /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ -#define STM32L4_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ -#define STM32L4_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ +#define STM32_USB_ADDR_TX_WOFFSET (0) /* Transmission buffer address n (16-bits) */ +#define STM32_USB_COUNT_TX_WOFFSET (2) /* Transmission byte count n (16-bits) */ +#define STM32_USB_ADDR_RX_WOFFSET (4) /* Reception buffer address n (16-bits) */ +#define STM32_USB_COUNT_RX_WOFFSET (6) /* Reception byte count n (16-bits) */ -#define STM32L4_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32L4_USB_BTABLE) + ((ep) << 3)) + (o)) -#define STM32L4_USB_ADDR_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX_OFFSET(ep) STM32L4_USB_BTABLE_RADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_RADDR(ep,o) (((uint32_t)getreg16(STM32_USB_BTABLE) + ((ep) << 3)) + (o)) +#define STM32_USB_ADDR_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX_OFFSET(ep) STM32_USB_BTABLE_RADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Addresses *******************************************************/ /* Endpoint Registers */ -#define STM32L4_USB_EPR(n) (STM32L4_USB_FS_BASE + STM32L4_USB_EPR_OFFSET(n)) -#define STM32L4_USB_EP0R (STM32L4_USB_FS_BASE + STM32L4_USB_EP0R_OFFSET) -#define STM32L4_USB_EP1R (STM32L4_USB_FS_BASE + STM32L4_USB_EP1R_OFFSET) -#define STM32L4_USB_EP2R (STM32L4_USB_FS_BASE + STM32L4_USB_EP2R_OFFSET) -#define STM32L4_USB_EP3R (STM32L4_USB_FS_BASE + STM32L4_USB_EP3R_OFFSET) -#define STM32L4_USB_EP4R (STM32L4_USB_FS_BASE + STM32L4_USB_EP4R_OFFSET) -#define STM32L4_USB_EP5R (STM32L4_USB_FS_BASE + STM32L4_USB_EP5R_OFFSET) -#define STM32L4_USB_EP6R (STM32L4_USB_FS_BASE + STM32L4_USB_EP6R_OFFSET) -#define STM32L4_USB_EP7R (STM32L4_USB_FS_BASE + STM32L4_USB_EP7R_OFFSET) +#define STM32_USB_EPR(n) (STM32_USB_FS_BASE + STM32_USB_EPR_OFFSET(n)) +#define STM32_USB_EP0R (STM32_USB_FS_BASE + STM32_USB_EP0R_OFFSET) +#define STM32_USB_EP1R (STM32_USB_FS_BASE + STM32_USB_EP1R_OFFSET) +#define STM32_USB_EP2R (STM32_USB_FS_BASE + STM32_USB_EP2R_OFFSET) +#define STM32_USB_EP3R (STM32_USB_FS_BASE + STM32_USB_EP3R_OFFSET) +#define STM32_USB_EP4R (STM32_USB_FS_BASE + STM32_USB_EP4R_OFFSET) +#define STM32_USB_EP5R (STM32_USB_FS_BASE + STM32_USB_EP5R_OFFSET) +#define STM32_USB_EP6R (STM32_USB_FS_BASE + STM32_USB_EP6R_OFFSET) +#define STM32_USB_EP7R (STM32_USB_FS_BASE + STM32_USB_EP7R_OFFSET) /* Common Registers */ -#define STM32L4_USB_CNTR (STM32L4_USB_FS_BASE + STM32L4_USB_CNTR_OFFSET) -#define STM32L4_USB_ISTR (STM32L4_USB_FS_BASE + STM32L4_USB_ISTR_OFFSET) -#define STM32L4_USB_FNR (STM32L4_USB_FS_BASE + STM32L4_USB_FNR_OFFSET) -#define STM32L4_USB_DADDR (STM32L4_USB_FS_BASE + STM32L4_USB_DADDR_OFFSET) -#define STM32L4_USB_BTABLE (STM32L4_USB_FS_BASE + STM32L4_USB_BTABLE_OFFSET) -#define STM32L4_USB_LPMCSR (STM32L4_USB_FS_BASE + STM32L4_USB_LPMCSR_OFFSET) -#define STM32L4_USB_BCDR (STM32L4_USB_FS_BASE + STM32L4_USB_BCDR_OFFSET) +#define STM32_USB_CNTR (STM32_USB_FS_BASE + STM32_USB_CNTR_OFFSET) +#define STM32_USB_ISTR (STM32_USB_FS_BASE + STM32_USB_ISTR_OFFSET) +#define STM32_USB_FNR (STM32_USB_FS_BASE + STM32_USB_FNR_OFFSET) +#define STM32_USB_DADDR (STM32_USB_FS_BASE + STM32_USB_DADDR_OFFSET) +#define STM32_USB_BTABLE (STM32_USB_FS_BASE + STM32_USB_BTABLE_OFFSET) +#define STM32_USB_LPMCSR (STM32_USB_FS_BASE + STM32_USB_LPMCSR_OFFSET) +#define STM32_USB_BCDR (STM32_USB_FS_BASE + STM32_USB_BCDR_OFFSET) /* Buffer Descriptor Table (Relatative to BTABLE address) */ -#define STM32L4_USB_BTABLE_ADDR(ep,o) (STM32L4_USB_SRAM_BASE + STM32L4_USB_BTABLE_RADDR(ep,o)) -#define STM32L4_USB_ADDR_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_TX_WOFFSET) -#define STM32L4_USB_COUNT_TX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_TX_WOFFSET) -#define STM32L4_USB_ADDR_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_ADDR_RX_WOFFSET) -#define STM32L4_USB_COUNT_RX(ep) STM32L4_USB_BTABLE_ADDR(ep,STM32L4_USB_COUNT_RX_WOFFSET) +#define STM32_USB_BTABLE_ADDR(ep,o) (STM32_USB_SRAM_BASE + STM32_USB_BTABLE_RADDR(ep,o)) +#define STM32_USB_ADDR_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_TX_WOFFSET) +#define STM32_USB_COUNT_TX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_TX_WOFFSET) +#define STM32_USB_ADDR_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_ADDR_RX_WOFFSET) +#define STM32_USB_COUNT_RX(ep) STM32_USB_BTABLE_ADDR(ep,STM32_USB_COUNT_RX_WOFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h index 33508659207..1ceca936c55 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_wdg.h @@ -37,27 +37,27 @@ /* Register Offsets *********************************************************/ -#define STM32L4_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ -#define STM32L4_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ -#define STM32L4_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ -#define STM32L4_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ -#define STM32L4_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ +#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */ +#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */ +#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */ +#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */ +#define STM32_IWDG_WINR_OFFSET 0x0010 /* Window register (32-bit) */ -#define STM32L4_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ -#define STM32L4_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ -#define STM32L4_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ +#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */ +#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */ +#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */ /* Register Addresses *******************************************************/ -#define STM32L4_IWDG_KR (STM32L4_IWDG_BASE+STM32L4_IWDG_KR_OFFSET) -#define STM32L4_IWDG_PR (STM32L4_IWDG_BASE+STM32L4_IWDG_PR_OFFSET) -#define STM32L4_IWDG_RLR (STM32L4_IWDG_BASE+STM32L4_IWDG_RLR_OFFSET) -#define STM32L4_IWDG_SR (STM32L4_IWDG_BASE+STM32L4_IWDG_SR_OFFSET) -#define STM32L4_IWDG_WINR (STM32L4_IWDG_BASE+STM32L4_IWDG_WINR_OFFSET) +#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET) +#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET) +#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET) +#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET) +#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET) -#define STM32L4_WWDG_CR (STM32L4_WWDG_BASE+STM32L4_WWDG_CR_OFFSET) -#define STM32L4_WWDG_CFR (STM32L4_WWDG_BASE+STM32L4_WWDG_CFR_OFFSET) -#define STM32L4_WWDG_SR (STM32L4_WWDG_BASE+STM32L4_WWDG_SR_OFFSET) +#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET) +#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET) +#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h index bc4070f7dfc..587031ae934 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,145 +306,145 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h index 153953e705a..7aa56323221 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index 73fcb283519..f7951f4ed79 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h index 968eddee749..94a366dbf51 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h index b56cb00fc70..0ff70f0abf2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -277,21 +277,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -306,167 +306,167 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 3) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 3) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h index 6ca4fea8472..df83782f5a8 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h index 9ca5ed2dbec..7e78f15e171 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ @@ -741,7 +741,7 @@ #define OTGFS_DSTS_SOFFN_ODD OTGFS_DSTS_SOFFN0 #define OTGFS_DSTS_DEVLNSTS_SHIFT (22) /* Bits 22-23: XXX */ #define OTGFS_DSTS_DEVLNSTS_MASK (0x3 << OTGFS_DSTS_DEVLNSTS_SHIFT) - /* Bits 24-31: Reserved, must be kept at reset value */ + /* Bits 24-31: Reserved, must be kept at reset value */ /* Device IN endpoint common interrupt mask register */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index 218ac07c4bb..c3c76f22cb6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -37,69 +37,69 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h index c092d69675a..20d9addcad0 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h @@ -38,33 +38,33 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h index 48c9a9d1d99..f0dbeddab00 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dma.h @@ -34,141 +34,141 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ -#define STM32L4_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ +#define STM32_DMA_CSELR_OFFSET 0x00a8 /* DMA channel selection register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ @@ -276,21 +276,21 @@ * numeric suffix. Additional definitions are required in the board.h file. */ -#define STM32L4_DMA1_CHAN1 (0) -#define STM32L4_DMA1_CHAN2 (1) -#define STM32L4_DMA1_CHAN3 (2) -#define STM32L4_DMA1_CHAN4 (3) -#define STM32L4_DMA1_CHAN5 (4) -#define STM32L4_DMA1_CHAN6 (5) -#define STM32L4_DMA1_CHAN7 (6) +#define STM32_DMA1_CHAN1 (0) +#define STM32_DMA1_CHAN2 (1) +#define STM32_DMA1_CHAN3 (2) +#define STM32_DMA1_CHAN4 (3) +#define STM32_DMA1_CHAN5 (4) +#define STM32_DMA1_CHAN6 (5) +#define STM32_DMA1_CHAN7 (6) -#define STM32L4_DMA2_CHAN1 (7) -#define STM32L4_DMA2_CHAN2 (8) -#define STM32L4_DMA2_CHAN3 (9) -#define STM32L4_DMA2_CHAN4 (10) -#define STM32L4_DMA2_CHAN5 (11) -#define STM32L4_DMA2_CHAN6 (12) -#define STM32L4_DMA2_CHAN7 (13) +#define STM32_DMA2_CHAN1 (7) +#define STM32_DMA2_CHAN2 (8) +#define STM32_DMA2_CHAN3 (9) +#define STM32_DMA2_CHAN4 (10) +#define STM32_DMA2_CHAN5 (11) +#define STM32_DMA2_CHAN6 (12) +#define STM32_DMA2_CHAN7 (13) /* DMA Channel settings include a channel and an alternative function. * Channel is in bits 0..7 @@ -305,186 +305,186 @@ /* ADC */ -#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 0) +#define DMACHAN_ADC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 0) -#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 0) +#define DMACHAN_ADC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 0) -#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 0) -#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 0) +#define DMACHAN_ADC3_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 0) +#define DMACHAN_ADC3_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 0) /* AES */ -#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 6) -#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 6) -#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 6) -#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 6) +#define DMACHAN_AES_IN_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 6) +#define DMACHAN_AES_IN_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 6) +#define DMACHAN_AES_OUT_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 6) +#define DMACHAN_AES_OUT_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 6) /* DAC */ -#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_DAC1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_DAC1_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_DAC2_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_DAC2_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) /* DCMI */ -#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 4) -#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 0) +#define DMACHAN_DCMI_1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 4) +#define DMACHAN_DCMI_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 0) /* DFSDM */ -#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 0) -#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 0) -#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 0) -#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 0) +#define DMACHAN_DFSDM0 DMACHAN_SETTING(STM32_DMA1_CHAN4, 0) +#define DMACHAN_DFSDM1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 0) +#define DMACHAN_DFSDM2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 0) +#define DMACHAN_DFSDM3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 0) /* HASH */ -#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 6) +#define DMACHAN_HASH_IN DMACHAN_SETTING(STM32_DMA2_CHAN7, 6) /* I2C */ -#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 3) -#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 5) -#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 3) -#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 5) +#define DMACHAN_I2C1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 3) +#define DMACHAN_I2C1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 5) +#define DMACHAN_I2C1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 3) +#define DMACHAN_I2C1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 5) -#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 3) -#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 3) +#define DMACHAN_I2C2_RX DMACHAN_SETTING(STM32_DMA1_CHAN5, 3) +#define DMACHAN_I2C2_TX DMACHAN_SETTING(STM32_DMA1_CHAN4, 3) -#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 3) +#define DMACHAN_I2C3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_I2C3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 3) -#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 0) -#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 0) +#define DMACHAN_I2C4_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 0) +#define DMACHAN_I2C4_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 0) /* QUADSPI */ -#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 5) -#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 3) +#define DMACHAN_QUADSPI_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 5) +#define DMACHAN_QUADSPI_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 3) /* SAI */ -#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 1) -#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 1) -#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 1) -#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 1) +#define DMACHAN_SAI1_A_1 DMACHAN_SETTING(STM32_DMA2_CHAN1, 1) +#define DMACHAN_SAI1_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 1) +#define DMACHAN_SAI1_B_1 DMACHAN_SETTING(STM32_DMA2_CHAN2, 1) +#define DMACHAN_SAI1_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 1) -#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 1) -#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 1) -#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 1) -#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 1) +#define DMACHAN_SAI2_A_1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 1) +#define DMACHAN_SAI2_A_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 1) +#define DMACHAN_SAI2_B_1 DMACHAN_SETTING(STM32_DMA1_CHAN7, 1) +#define DMACHAN_SAI2_B_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 1) /* SDMMC */ -#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 7) -#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 7) +#define DMACHAN_SDMMC_1 DMACHAN_SETTING(STM32_DMA2_CHAN4, 7) +#define DMACHAN_SDMMC_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 7) /* SPI */ -#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 1) -#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 4) -#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 1) -#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 4) +#define DMACHAN_SPI1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 1) +#define DMACHAN_SPI1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN3, 4) +#define DMACHAN_SPI1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 1) +#define DMACHAN_SPI1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 4) -#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 1) -#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 1) +#define DMACHAN_SPI2_RX DMACHAN_SETTING(STM32_DMA1_CHAN4, 1) +#define DMACHAN_SPI2_TX DMACHAN_SETTING(STM32_DMA1_CHAN5, 1) -#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 3) -#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 3) +#define DMACHAN_SPI3_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 3) +#define DMACHAN_SPI3_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 3) /* SWPMI */ -#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 4) -#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 4) +#define DMACHAN_SWPMI_RX DMACHAN_SETTING(STM32_DMA2_CHAN1, 4) +#define DMACHAN_SWPMI_TX DMACHAN_SETTING(STM32_DMA2_CHAN2, 4) /* TIM */ -#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 7) -#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 7) -#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 7) -#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 7) -#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 7) +#define DMACHAN_TIM1_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN2, 7) +#define DMACHAN_TIM1_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN3, 7) +#define DMACHAN_TIM1_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN7, 7) +#define DMACHAN_TIM1_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_COM DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN4, 7) +#define DMACHAN_TIM1_UP DMACHAN_SETTING(STM32_DMA1_CHAN6, 7) -#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 4) -#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 4) -#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 4) -#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 4) +#define DMACHAN_TIM2_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 4) +#define DMACHAN_TIM2_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN1, 4) +#define DMACHAN_TIM2_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN7, 4) +#define DMACHAN_TIM2_UP DMACHAN_SETTING(STM32_DMA1_CHAN2, 4) -#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 5) -#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) -#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 5) -#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN2, 5) +#define DMACHAN_TIM3_CH4 DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) +#define DMACHAN_TIM3_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN6, 5) +#define DMACHAN_TIM3_UP DMACHAN_SETTING(STM32_DMA1_CHAN3, 5) -#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 6) -#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 6) -#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 6) -#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 6) +#define DMACHAN_TIM4_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 6) +#define DMACHAN_TIM4_CH2 DMACHAN_SETTING(STM32_DMA1_CHAN4, 6) +#define DMACHAN_TIM4_CH3 DMACHAN_SETTING(STM32_DMA1_CHAN5, 6) +#define DMACHAN_TIM4_UP DMACHAN_SETTING(STM32_DMA1_CHAN7, 6) -#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 5) -#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 5) -#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) -#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 5) -#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN5, 5) +#define DMACHAN_TIM5_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 5) +#define DMACHAN_TIM5_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) +#define DMACHAN_TIM5_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_COM DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN1, 5) +#define DMACHAN_TIM5_UP DMACHAN_SETTING(STM32_DMA2_CHAN2, 5) -#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 6) -#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN4, 3) +#define DMACHAN_TIM6_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 6) +#define DMACHAN_TIM6_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN4, 3) -#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 5) -#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 3) +#define DMACHAN_TIM7_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 5) +#define DMACHAN_TIM7_UP_2 DMACHAN_SETTING(STM32_DMA2_CHAN5, 3) -#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 7) -#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 7) -#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) -#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 7) -#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH1 DMACHAN_SETTING(STM32_DMA2_CHAN6, 7) +#define DMACHAN_TIM8_CH2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 7) +#define DMACHAN_TIM8_CH3 DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) +#define DMACHAN_TIM8_CH4 DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_COM DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_TRIG DMACHAN_SETTING(STM32_DMA2_CHAN2, 7) +#define DMACHAN_TIM8_UP DMACHAN_SETTING(STM32_DMA2_CHAN1, 7) -#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) -#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_CH1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_COM DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_TRIG DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) +#define DMACHAN_TIM15_UP DMACHAN_SETTING(STM32_DMA1_CHAN5, 7) -#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) -#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 4) -#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) +#define DMACHAN_TIM16_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN3, 4) +#define DMACHAN_TIM16_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN6, 4) -#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) -#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN1, 5) -#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_CH1_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_CH1_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) +#define DMACHAN_TIM17_UP_1 DMACHAN_SETTING(STM32_DMA1_CHAN1, 5) +#define DMACHAN_TIM17_UP_2 DMACHAN_SETTING(STM32_DMA1_CHAN7, 5) /* UART */ -#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN5, 2) -#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 2) -#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32L4_DMA1_CHAN4, 2) -#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 2) +#define DMACHAN_USART1_RX_1 DMACHAN_SETTING(STM32_DMA1_CHAN5, 2) +#define DMACHAN_USART1_RX_2 DMACHAN_SETTING(STM32_DMA2_CHAN7, 2) +#define DMACHAN_USART1_TX_1 DMACHAN_SETTING(STM32_DMA1_CHAN4, 2) +#define DMACHAN_USART1_TX_2 DMACHAN_SETTING(STM32_DMA2_CHAN6, 2) -#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN6, 2) -#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN7, 2) +#define DMACHAN_USART2_RX DMACHAN_SETTING(STM32_DMA1_CHAN6, 2) +#define DMACHAN_USART2_TX DMACHAN_SETTING(STM32_DMA1_CHAN7, 2) -#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32L4_DMA1_CHAN3, 2) -#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32L4_DMA1_CHAN2, 2) +#define DMACHAN_USART3_RX DMACHAN_SETTING(STM32_DMA1_CHAN3, 2) +#define DMACHAN_USART3_TX DMACHAN_SETTING(STM32_DMA1_CHAN2, 2) -#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN2, 2) -#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN1, 2) +#define DMACHAN_UART5_RX DMACHAN_SETTING(STM32_DMA2_CHAN2, 2) +#define DMACHAN_UART5_TX DMACHAN_SETTING(STM32_DMA2_CHAN1, 2) -#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN5, 2) -#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN3, 2) +#define DMACHAN_UART4_RX DMACHAN_SETTING(STM32_DMA2_CHAN5, 2) +#define DMACHAN_UART4_TX DMACHAN_SETTING(STM32_DMA2_CHAN3, 2) -#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32L4_DMA2_CHAN7, 4) -#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32L4_DMA2_CHAN6, 4) +#define DMACHAN_LPUART_RX DMACHAN_SETTING(STM32_DMA2_CHAN7, 4) +#define DMACHAN_LPUART_TX DMACHAN_SETTING(STM32_DMA2_CHAN6, 4) #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_DMA_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h index 4272f345b76..19df3fe795c 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h index 12288d4b39f..c92296e69f6 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_otgfs.h @@ -48,182 +48,182 @@ /* Core global control and status registers */ -#define STM32L4_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ -#define STM32L4_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ -#define STM32L4_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ -#define STM32L4_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ -#define STM32L4_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ -#define STM32L4_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ -#define STM32L4_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ -#define STM32L4_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ -#define STM32L4_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ -#define STM32L4_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ -#define STM32L4_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ -#define STM32L4_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ -#define STM32L4_OTGFS_CID_OFFSET 0x003c /* Core ID register */ -#define STM32L4_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ -#define STM32L4_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ -#define STM32L4_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ -#define STM32L4_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ +#define STM32_OTGFS_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTGFS_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTGFS_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTGFS_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTGFS_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTGFS_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTGFS_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTGFS_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTGFS_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTGFS_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTGFS_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTGFS_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTGFS_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTGFS_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTGFS_GLPMCFG_OFFSET 0x0054 /* LPM configuration register */ +#define STM32_OTGFS_GPWRDN_OFFSET 0x0058 /* Power down register */ +#define STM32_OTGFS_GADPCTL_OFSSET 0x0060 /* ADP timer, control and status register */ +#define STM32_OTGFS_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ -#define STM32L4_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) +#define STM32_OTGFS_DIEPTXF_OFFSET(n) (0x0104+(((n)-1) << 2)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ -#define STM32L4_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ -#define STM32L4_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ -#define STM32L4_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ -#define STM32L4_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ -#define STM32L4_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ -#define STM32L4_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ +#define STM32_OTGFS_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTGFS_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTGFS_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTGFS_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTGFS_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTGFS_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTGFS_HPRT_OFFSET 0x0440 /* Host port control and status register */ -#define STM32L4_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) -#define STM32L4_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ -#define STM32L4_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ -#define STM32L4_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ +#define STM32_OTGFS_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTGFS_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTGFS_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTGFS_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTGFS_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ -#define STM32L4_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) +#define STM32_OTGFS_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) -#define STM32L4_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) +#define STM32_OTGFS_HCINT_OFFSET(n) (0x508 + ((n) << 5)) -#define STM32L4_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) +#define STM32_OTGFS_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) -#define STM32L4_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) +#define STM32_OTGFS_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ -#define STM32L4_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ -#define STM32L4_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ -#define STM32L4_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ -#define STM32L4_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ -#define STM32L4_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ -#define STM32L4_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ -#define STM32L4_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ -#define STM32L4_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ +#define STM32_OTGFS_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTGFS_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTGFS_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTGFS_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTGFS_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTGFS_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTGFS_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTGFS_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTGFS_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTGFS_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ -#define STM32L4_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ -#define STM32L4_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ -#define STM32L4_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ -#define STM32L4_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ +#define STM32_OTGFS_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTGFS_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTGFS_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTGFS_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ -#define STM32L4_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTGFS_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) +#define STM32_OTGFS_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) -#define STM32L4_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) +#define STM32_OTGFS_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) -#define STM32L4_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) +#define STM32_OTGFS_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) -#define STM32L4_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ -#define STM32L4_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ -#define STM32L4_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ +#define STM32_OTGFS_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTGFS_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ +#define STM32_OTGFS_DOEPTSIZ_EPOFFSET 0x0010 /* Device endpoint OUT transfer size register */ -#define STM32L4_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTGFS_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) +#define STM32_OTGFS_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) -#define STM32L4_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) +#define STM32_OTGFS_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ +#define STM32_OTGFS_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) -#define STM32L4_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTGFS_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) /* Register Addresses *******************************************************/ -#define STM32L4_OTGFS_GOTGCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGCTL_OFFSET) -#define STM32L4_OTGFS_GOTGINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GOTGINT_OFFSET) -#define STM32L4_OTGFS_GAHBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GAHBCFG_OFFSET) -#define STM32L4_OTGFS_GUSBCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GUSBCFG_OFFSET) -#define STM32L4_OTGFS_GRSTCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRSTCTL_OFFSET) -#define STM32L4_OTGFS_GINTSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTSTS_OFFSET) -#define STM32L4_OTGFS_GINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GINTMSK_OFFSET) -#define STM32L4_OTGFS_GRXSTSR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSR_OFFSET) -#define STM32L4_OTGFS_GRXSTSP (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXSTSP_OFFSET) -#define STM32L4_OTGFS_GRXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GRXFSIZ_OFFSET) -#define STM32L4_OTGFS_HNPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF0 (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF0_OFFSET) -#define STM32L4_OTGFS_HNPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HNPTXSTS_OFFSET) -#define STM32L4_OTGFS_GCCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GCCFG_OFFSET) -#define STM32L4_OTGFS_CID (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CID_OFFSET) -#define STM32L4_OTGFS_GLPMCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GLPMCFG_OFFSET) -#define STM32L4_OTGFS_GPWRDN (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GPWRDN_OFFSET) -#define STM32L4_OTGFS_GADPCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_GADPCTL_OFSSET) -#define STM32L4_OTGFS_HPTXFSIZ (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXFSIZ_OFFSET) +#define STM32_OTGFS_GOTGCTL (STM32_OTGFS_BASE+STM32_OTGFS_GOTGCTL_OFFSET) +#define STM32_OTGFS_GOTGINT (STM32_OTGFS_BASE+STM32_OTGFS_GOTGINT_OFFSET) +#define STM32_OTGFS_GAHBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GAHBCFG_OFFSET) +#define STM32_OTGFS_GUSBCFG (STM32_OTGFS_BASE+STM32_OTGFS_GUSBCFG_OFFSET) +#define STM32_OTGFS_GRSTCTL (STM32_OTGFS_BASE+STM32_OTGFS_GRSTCTL_OFFSET) +#define STM32_OTGFS_GINTSTS (STM32_OTGFS_BASE+STM32_OTGFS_GINTSTS_OFFSET) +#define STM32_OTGFS_GINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_GINTMSK_OFFSET) +#define STM32_OTGFS_GRXSTSR (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSR_OFFSET) +#define STM32_OTGFS_GRXSTSP (STM32_OTGFS_BASE+STM32_OTGFS_GRXSTSP_OFFSET) +#define STM32_OTGFS_GRXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_GRXFSIZ_OFFSET) +#define STM32_OTGFS_HNPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXFSIZ_OFFSET) +#define STM32_OTGFS_DIEPTXF0 (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF0_OFFSET) +#define STM32_OTGFS_HNPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HNPTXSTS_OFFSET) +#define STM32_OTGFS_GCCFG (STM32_OTGFS_BASE+STM32_OTGFS_GCCFG_OFFSET) +#define STM32_OTGFS_CID (STM32_OTGFS_BASE+STM32_OTGFS_CID_OFFSET) +#define STM32_OTGFS_GLPMCFG (STM32_OTGFS_BASE+STM32_OTGFS_GLPMCFG_OFFSET) +#define STM32_OTGFS_GPWRDN (STM32_OTGFS_BASE+STM32_OTGFS_GPWRDN_OFFSET) +#define STM32_OTGFS_GADPCTL (STM32_OTGFS_BASE+STM32_OTGFS_GADPCTL_OFSSET) +#define STM32_OTGFS_HPTXFSIZ (STM32_OTGFS_BASE+STM32_OTGFS_HPTXFSIZ_OFFSET) -#define STM32L4_OTGFS_DIEPTXF(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTXF_OFFSET(n)) +#define STM32_OTGFS_DIEPTXF(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTXF_OFFSET(n)) /* Host-mode control and status registers */ -#define STM32L4_OTGFS_HCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCFG_OFFSET) -#define STM32L4_OTGFS_HFIR (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFIR_OFFSET) -#define STM32L4_OTGFS_HFNUM (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HFNUM_OFFSET) -#define STM32L4_OTGFS_HPTXSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPTXSTS_OFFSET) -#define STM32L4_OTGFS_HAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINT_OFFSET) -#define STM32L4_OTGFS_HAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HAINTMSK_OFFSET) -#define STM32L4_OTGFS_HPRT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HPRT_OFFSET) +#define STM32_OTGFS_HCFG (STM32_OTGFS_BASE+STM32_OTGFS_HCFG_OFFSET) +#define STM32_OTGFS_HFIR (STM32_OTGFS_BASE+STM32_OTGFS_HFIR_OFFSET) +#define STM32_OTGFS_HFNUM (STM32_OTGFS_BASE+STM32_OTGFS_HFNUM_OFFSET) +#define STM32_OTGFS_HPTXSTS (STM32_OTGFS_BASE+STM32_OTGFS_HPTXSTS_OFFSET) +#define STM32_OTGFS_HAINT (STM32_OTGFS_BASE+STM32_OTGFS_HAINT_OFFSET) +#define STM32_OTGFS_HAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_HAINTMSK_OFFSET) +#define STM32_OTGFS_HPRT (STM32_OTGFS_BASE+STM32_OTGFS_HPRT_OFFSET) -#define STM32L4_OTGFS_CHAN(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_CHAN_OFFSET(n)) +#define STM32_OTGFS_CHAN(n) (STM32_OTGFS_BASE+STM32_OTGFS_CHAN_OFFSET(n)) -#define STM32L4_OTGFS_HCCHAR(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCCHAR_OFFSET(n)) +#define STM32_OTGFS_HCCHAR(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCCHAR_OFFSET(n)) -#define STM32L4_OTGFS_HCINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINT_OFFSET(n)) +#define STM32_OTGFS_HCINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINT_OFFSET(n)) -#define STM32L4_OTGFS_HCINTMSK(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCINTMSK_OFFSET(n)) +#define STM32_OTGFS_HCINTMSK(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCINTMSK_OFFSET(n)) -#define STM32L4_OTGFS_HCTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_HCTSIZ_OFFSET(n)) +#define STM32_OTGFS_HCTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_HCTSIZ_OFFSET(n)) /* Device-mode control and status registers */ -#define STM32L4_OTGFS_DCFG (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCFG_OFFSET) -#define STM32L4_OTGFS_DCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DCTL_OFFSET) -#define STM32L4_OTGFS_DSTS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DSTS_OFFSET) -#define STM32L4_OTGFS_DIEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPMSK_OFFSET) -#define STM32L4_OTGFS_DOEPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPMSK_OFFSET) -#define STM32L4_OTGFS_DAINT (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINT_OFFSET) -#define STM32L4_OTGFS_DAINTMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DAINTMSK_OFFSET) -#define STM32L4_OTGFS_DVBUSDIS (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSDIS_OFFSET) -#define STM32L4_OTGFS_DVBUSPULSE (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DVBUSPULSE_OFFSET) -#define STM32L4_OTGFS_DIEPEMPMSK (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPEMPMSK_OFFSET) +#define STM32_OTGFS_DCFG (STM32_OTGFS_BASE+STM32_OTGFS_DCFG_OFFSET) +#define STM32_OTGFS_DCTL (STM32_OTGFS_BASE+STM32_OTGFS_DCTL_OFFSET) +#define STM32_OTGFS_DSTS (STM32_OTGFS_BASE+STM32_OTGFS_DSTS_OFFSET) +#define STM32_OTGFS_DIEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPMSK_OFFSET) +#define STM32_OTGFS_DOEPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DOEPMSK_OFFSET) +#define STM32_OTGFS_DAINT (STM32_OTGFS_BASE+STM32_OTGFS_DAINT_OFFSET) +#define STM32_OTGFS_DAINTMSK (STM32_OTGFS_BASE+STM32_OTGFS_DAINTMSK_OFFSET) +#define STM32_OTGFS_DVBUSDIS (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSDIS_OFFSET) +#define STM32_OTGFS_DVBUSPULSE (STM32_OTGFS_BASE+STM32_OTGFS_DVBUSPULSE_OFFSET) +#define STM32_OTGFS_DIEPEMPMSK (STM32_OTGFS_BASE+STM32_OTGFS_DIEPEMPMSK_OFFSET) -#define STM32L4_OTGFS_DIEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEP_OFFSET(n)) +#define STM32_OTGFS_DIEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEP_OFFSET(n)) -#define STM32L4_OTGFS_DIEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPCTL_OFFSET(n)) +#define STM32_OTGFS_DIEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DIEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPINT_OFFSET(n)) +#define STM32_OTGFS_DIEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DIEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DIEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DIEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DIEPTSIZ_OFFSET(n)) -#define STM32L4_OTGFS_DTXFSTS(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DTXFSTS_OFFSET(n)) +#define STM32_OTGFS_DTXFSTS(n) (STM32_OTGFS_BASE+STM32_OTGFS_DTXFSTS_OFFSET(n)) -#define STM32L4_OTGFS_DOEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEP_OFFSET(n)) +#define STM32_OTGFS_DOEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEP_OFFSET(n)) -#define STM32L4_OTGFS_DOEPCTL(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPCTL_OFFSET(n)) +#define STM32_OTGFS_DOEPCTL(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPCTL_OFFSET(n)) -#define STM32L4_OTGFS_DOEPINT(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPINT_OFFSET(n)) +#define STM32_OTGFS_DOEPINT(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPINT_OFFSET(n)) -#define STM32L4_OTGFS_DOEPTSIZ(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DOEPTSIZ_OFFSET(n)) +#define STM32_OTGFS_DOEPTSIZ(n) (STM32_OTGFS_BASE+STM32_OTGFS_DOEPTSIZ_OFFSET(n)) /* Power and clock gating registers */ -#define STM32L4_OTGFS_PCGCCTL (STM32L4_OTGFS_BASE+STM32L4_OTGFS_PCGCCTL_OFFSET) +#define STM32_OTGFS_PCGCCTL (STM32_OTGFS_BASE+STM32_OTGFS_PCGCCTL_OFFSET) /* Data FIFO (DFIFO) access registers */ -#define STM32L4_OTGFS_DFIFO_DEP(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_DEP_OFFSET(n)) -#define STM32L4_OTGFS_DFIFO_HCH(n) (STM32L4_OTGFS_BASE+STM32L4_OTGFS_DFIFO_HCH_OFFSET(n)) +#define STM32_OTGFS_DFIFO_DEP(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_DEP_OFFSET(n)) +#define STM32_OTGFS_DFIFO_HCH(n) (STM32_OTGFS_BASE+STM32_OTGFS_DFIFO_HCH_OFFSET(n)) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 991c1529756..73d2f0b9785 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h index 1bf04c71f6e..9819f2a7eb1 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h index 8229ac0413c..5f32ee5ef75 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32L4_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ -#define STM32L4_DMACHAN_OFFSET(n) (0x0014*(n)) -#define STM32L4_DMACHAN1_OFFSET 0x0000 -#define STM32L4_DMACHAN2_OFFSET 0x0014 -#define STM32L4_DMACHAN3_OFFSET 0x0028 -#define STM32L4_DMACHAN4_OFFSET 0x003c -#define STM32L4_DMACHAN5_OFFSET 0x0050 -#define STM32L4_DMACHAN6_OFFSET 0x0064 -#define STM32L4_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN_OFFSET(n) (0x0014*(n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32L4_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32L4_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32L4_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32L4_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ -#define STM32L4_DMA_CCR_OFFSET(n) (STM32L4_DMACHAN_CCR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CNDTR_OFFSET(n) (STM32L4_DMACHAN_CNDTR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CPAR_OFFSET(n) (STM32L4_DMACHAN_CPAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CMAR_OFFSET(n) (STM32L4_DMACHAN_CMAR_OFFSET+STM32L4_DMACHAN_OFFSET(n)) +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET+STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET+STM32_DMACHAN_OFFSET(n)) -#define STM32L4_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32L4_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32L4_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32L4_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32L4_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32L4_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32L4_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32L4_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32L4_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32L4_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32L4_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32L4_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32L4_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32L4_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32L4_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32L4_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32L4_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32L4_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32L4_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32L4_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32L4_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32L4_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32L4_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32L4_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32L4_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32L4_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32L4_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32L4_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32L4_DMA1_ISRC (STM32L4_DMA1_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA1_IFCR (STM32L4_DMA1_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA1_CCR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA1_CCR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA1_CCR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA1_CCR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA1_CCR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA1_CCR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA1_CCR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA1_CCR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA1_CNDTR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA1_CNDTR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA1_CNDTR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA1_CNDTR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA1_CNDTR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA1_CNDTR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA1_CNDTR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA1_CNDTR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA1_CPAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA1_CPAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA1_CPAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA1_CPAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA1_CPAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA1_CPAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA1_CPAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA1_CPAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA1_CMAR(n) (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA1_CMAR1 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA1_CMAR2 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA1_CMAR3 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA1_CMAR4 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA1_CMAR5 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA1_CMAR6 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA1_CMAR7 (STM32L4_DMA1_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#define STM32L4_DMA2_ISRC (STM32L4_DMA2_BASE+STM32L4_DMA_ISR_OFFSET) -#define STM32L4_DMA2_IFCR (STM32L4_DMA2_BASE+STM32L4_DMA_IFCR_OFFSET) +#define STM32_DMA2_ISRC (STM32_DMA2_BASE+STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE+STM32_DMA_IFCR_OFFSET) -#define STM32L4_DMA2_CCR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CCR_OFFSET(n)) -#define STM32L4_DMA2_CCR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR1_OFFSET) -#define STM32L4_DMA2_CCR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR2_OFFSET) -#define STM32L4_DMA2_CCR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR3_OFFSET) -#define STM32L4_DMA2_CCR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR4_OFFSET) -#define STM32L4_DMA2_CCR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR5_OFFSET) -#define STM32L4_DMA2_CCR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR6_OFFSET) -#define STM32L4_DMA2_CCR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CCR7_OFFSET) +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE+STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE+STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE+STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) -#define STM32L4_DMA2_CNDTR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR_OFFSET(n)) -#define STM32L4_DMA2_CNDTR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR1_OFFSET) -#define STM32L4_DMA2_CNDTR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR2_OFFSET) -#define STM32L4_DMA2_CNDTR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR3_OFFSET) -#define STM32L4_DMA2_CNDTR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR4_OFFSET) -#define STM32L4_DMA2_CNDTR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR5_OFFSET) -#define STM32L4_DMA2_CNDTR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR6_OFFSET) -#define STM32L4_DMA2_CNDTR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CNDTR7_OFFSET) +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE+STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE+STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE+STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) -#define STM32L4_DMA2_CPAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR_OFFSET(n)) -#define STM32L4_DMA2_CPAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR1_OFFSET) -#define STM32L4_DMA2_CPAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR2_OFFSET) -#define STM32L4_DMA2_CPAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR3_OFFSET) -#define STM32L4_DMA2_CPAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR4_OFFSET) -#define STM32L4_DMA2_CPAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR5_OFFSET) -#define STM32L4_DMA2_CPAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR6_OFFSET) -#define STM32L4_DMA2_CPAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CPAR7_OFFSET) +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE+STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE+STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE+STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) -#define STM32L4_DMA2_CMAR(n) (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR_OFFSET(n)) -#define STM32L4_DMA2_CMAR1 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR1_OFFSET) -#define STM32L4_DMA2_CMAR2 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR2_OFFSET) -#define STM32L4_DMA2_CMAR3 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR3_OFFSET) -#define STM32L4_DMA2_CMAR4 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR4_OFFSET) -#define STM32L4_DMA2_CMAR5 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR5_OFFSET) -#define STM32L4_DMA2_CMAR6 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR6_OFFSET) -#define STM32L4_DMA2_CMAR7 (STM32L4_DMA2_BASE+STM32L4_DMA_CMAR7_OFFSET) +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE+STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE+STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE+STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h index c0572faa6bc..19a79a36e07 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32L4_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32L4_DMAMUX_C0CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(0) -#define STM32L4_DMAMUX_C1CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(1) -#define STM32L4_DMAMUX_C2CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(2) -#define STM32L4_DMAMUX_C3CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(3) -#define STM32L4_DMAMUX_C4CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(4) -#define STM32L4_DMAMUX_C5CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(5) -#define STM32L4_DMAMUX_C6CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(6) -#define STM32L4_DMAMUX_C7CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(7) -#define STM32L4_DMAMUX_C8CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(8) -#define STM32L4_DMAMUX_C9CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(9) -#define STM32L4_DMAMUX_C10CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(10) -#define STM32L4_DMAMUX_C11CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(11) -#define STM32L4_DMAMUX_C12CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(12) -#define STM32L4_DMAMUX_C13CR_OFFSET STM32L4_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32L4_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32L4_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000+0x0004*(x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ -#define STM32L4_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32L4_DMAMUX_RG0CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(0) -#define STM32L4_DMAMUX_RG1CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(1) -#define STM32L4_DMAMUX_RG2CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(2) -#define STM32L4_DMAMUX_RG3CR_OFFSET STM32L4_DMAMUX_RGXCR_OFFSET(3) -#define STM32L4_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32L4_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3FC: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100+0x004*(x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3FC: Reserved */ /* Register Addresses *******************************************************/ -#define STM32L4_DMAMUX1_CXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_C0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C0CR_OFFSET) -#define STM32L4_DMAMUX1_C1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C1CR_OFFSET) -#define STM32L4_DMAMUX1_C2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C2CR_OFFSET) -#define STM32L4_DMAMUX1_C3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C3CR_OFFSET) -#define STM32L4_DMAMUX1_C4CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C4CR_OFFSET) -#define STM32L4_DMAMUX1_C5CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C5CR_OFFSET) -#define STM32L4_DMAMUX1_C6CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C6CR_OFFSET) -#define STM32L4_DMAMUX1_C7CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C7CR_OFFSET) -#define STM32L4_DMAMUX1_C8CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C8CR_OFFSET) -#define STM32L4_DMAMUX1_C9CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C9CR_OFFSET) -#define STM32L4_DMAMUX1_C10CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C10CR_OFFSET) -#define STM32L4_DMAMUX1_C11CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C11CR_OFFSET) -#define STM32L4_DMAMUX1_C12CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C12CR_OFFSET) -#define STM32L4_DMAMUX1_C13CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_C13CR_OFFSET) -#define STM32L4_DMAMUX1_CSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CSR_OFFSET) -#define STM32L4_DMAMUX1_CFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_CFR_OFFSET) +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_CFR_OFFSET) -#define STM32L4_DMAMUX1_RGXCR(x) (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGXCR_OFFSET(x)) -#define STM32L4_DMAMUX1_RG0CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG0CR_OFFSET) -#define STM32L4_DMAMUX1_RG1CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG1CR_OFFSET) -#define STM32L4_DMAMUX1_RG2CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG2CR_OFFSET) -#define STM32L4_DMAMUX1_RG3CR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RG3CR_OFFSET) +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RG3CR_OFFSET) -#define STM32L4_DMAMUX1_RGSR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGSR_OFFSET) -#define STM32L4_DMAMUX1_RGCFR (STM32L4_DMAMUX1_BASE+STM32L4_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE+STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h index 9c2f082d507..d6b08303078 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_firewall.h @@ -38,23 +38,23 @@ /* Register Offsets *********************************************************/ -#define STM32L4_FIREWALL_CSSA_OFFSET 0x0000 -#define STM32L4_FIREWALL_CSL_OFFSET 0x0004 -#define STM32L4_FIREWALL_NVDSSA_OFFSET 0x0008 -#define STM32L4_FIREWALL_NVDSL_OFFSET 0x000c -#define STM32L4_FIREWALL_VDSSA_OFFSET 0x0010 -#define STM32L4_FIREWALL_VDSL_OFFSET 0x0014 -#define STM32L4_FIREWALL_CR_OFFSET 0x0020 +#define STM32_FIREWALL_CSSA_OFFSET 0x0000 +#define STM32_FIREWALL_CSL_OFFSET 0x0004 +#define STM32_FIREWALL_NVDSSA_OFFSET 0x0008 +#define STM32_FIREWALL_NVDSL_OFFSET 0x000c +#define STM32_FIREWALL_VDSSA_OFFSET 0x0010 +#define STM32_FIREWALL_VDSL_OFFSET 0x0014 +#define STM32_FIREWALL_CR_OFFSET 0x0020 /* Register Addresses *******************************************************/ -#define STM32L4_FIREWALL_CSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSSA_OFFSET) -#define STM32L4_FIREWALL_CSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CSL_OFFSET) -#define STM32L4_FIREWALL_NVDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSSA_OFFSET) -#define STM32L4_FIREWALL_NVDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_NVDSL_OFFSET) -#define STM32L4_FIREWALL_VDSSA (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSSA_OFFSET) -#define STM32L4_FIREWALL_VDSL (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_VDSL_OFFSET) -#define STM32L4_FIREWALL_CR (STM32L4_FIREWALL_BASE+STM32L4_FIREWALL_CR_OFFSET) +#define STM32_FIREWALL_CSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_CSSA_OFFSET) +#define STM32_FIREWALL_CSL (STM32_FIREWALL_BASE+STM32_FIREWALL_CSL_OFFSET) +#define STM32_FIREWALL_NVDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSSA_OFFSET) +#define STM32_FIREWALL_NVDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_NVDSL_OFFSET) +#define STM32_FIREWALL_VDSSA (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSSA_OFFSET) +#define STM32_FIREWALL_VDSL (STM32_FIREWALL_BASE+STM32_FIREWALL_VDSL_OFFSET) +#define STM32_FIREWALL_CR (STM32_FIREWALL_BASE+STM32_FIREWALL_CR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index c2bc0db32bc..ecc515f1141 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -37,73 +37,73 @@ /* Register Offsets *********************************************************/ -#define STM32L4_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L4_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L4_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L4_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L4_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L4_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L4_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L4_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L4_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L4_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L4_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L4_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L4_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L4_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L4_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L4_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L4_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L4_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L4_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L4_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L4_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L4_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L4_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L4_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L4_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L4_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L4_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L4_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_RCC_CR (STM32L4_RCC_BASE+STM32L4_RCC_CR_OFFSET) -#define STM32L4_RCC_ICSCR (STM32L4_RCC_BASE+STM32L4_RCC_ICSCR_OFFSET) -#define STM32L4_RCC_CFGR (STM32L4_RCC_BASE+STM32L4_RCC_CFGR_OFFSET) -#define STM32L4_RCC_PLLCFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLCFG_OFFSET) -#define STM32L4_RCC_PLLSAI1CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI1CFG_OFFSET) -#define STM32L4_RCC_PLLSAI2CFG (STM32L4_RCC_BASE+STM32L4_RCC_PLLSAI2CFG_OFFSET) -#define STM32L4_RCC_CIER (STM32L4_RCC_BASE+STM32L4_RCC_CIER_OFFSET) -#define STM32L4_RCC_CIFR (STM32L4_RCC_BASE+STM32L4_RCC_CIFR_OFFSET) -#define STM32L4_RCC_CICR (STM32L4_RCC_BASE+STM32L4_RCC_CICR_OFFSET) -#define STM32L4_RCC_AHB1RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1RSTR_OFFSET) -#define STM32L4_RCC_AHB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2RSTR_OFFSET) -#define STM32L4_RCC_AHB3RSTR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3RSTR_OFFSET) -#define STM32L4_RCC_APB1RSTR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR1_OFFSET) -#define STM32L4_RCC_APB1RSTR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1RSTR2_OFFSET) -#define STM32L4_RCC_APB2RSTR (STM32L4_RCC_BASE+STM32L4_RCC_APB2RSTR_OFFSET) -#define STM32L4_RCC_AHB1ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1ENR_OFFSET) -#define STM32L4_RCC_AHB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2ENR_OFFSET) -#define STM32L4_RCC_AHB3ENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3ENR_OFFSET) -#define STM32L4_RCC_APB1ENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR1_OFFSET) -#define STM32L4_RCC_APB1ENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1ENR2_OFFSET) -#define STM32L4_RCC_APB2ENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2ENR_OFFSET) -#define STM32L4_RCC_AHB1SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB1SMENR_OFFSET) -#define STM32L4_RCC_AHB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB2SMENR_OFFSET) -#define STM32L4_RCC_AHB3SMENR (STM32L4_RCC_BASE+STM32L4_RCC_AHB3SMENR_OFFSET) -#define STM32L4_RCC_APB1SMENR1 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR1_OFFSET) -#define STM32L4_RCC_APB1SMENR2 (STM32L4_RCC_BASE+STM32L4_RCC_APB1SMENR2_OFFSET) -#define STM32L4_RCC_APB2SMENR (STM32L4_RCC_BASE+STM32L4_RCC_APB2SMENR_OFFSET) -#define STM32L4_RCC_CCIPR (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR_OFFSET) -#define STM32L4_RCC_BDCR (STM32L4_RCC_BASE+STM32L4_RCC_BDCR_OFFSET) -#define STM32L4_RCC_CSR (STM32L4_RCC_BASE+STM32L4_RCC_CSR_OFFSET) -#define STM32L4_RCC_CRRCR (STM32L4_RCC_BASE+STM32L4_RCC_CRRCR_OFFSET) -#define STM32L4_RCC_CCIPR2 (STM32L4_RCC_BASE+STM32L4_RCC_CCIPR2_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE+STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE+STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE+STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE+STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE+STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE+STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE+STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE+STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE+STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE+STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE+STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE+STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE+STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE+STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE+STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE+STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE+STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE+STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE+STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE+STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE+STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE+STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE+STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE+STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE+STM32_RCC_CCIPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h index d95a8e75363..4d3b2cad341 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h @@ -38,35 +38,35 @@ /* Register Offsets *********************************************************/ -#define STM32L4_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32L4_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32L4_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32L4_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32L4_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32L4_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32L4_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L4_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32L4_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L4_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32L4_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ /* Register Addresses *******************************************************/ -#define STM32L4_SYSCFG_MEMRMP (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_MEMRMP_OFFSET) -#define STM32L4_SYSCFG_CFGR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR(p) (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR_OFFSET(p)) -#define STM32L4_SYSCFG_EXTICR1 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR1_OFFSET) -#define STM32L4_SYSCFG_EXTICR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR2_OFFSET) -#define STM32L4_SYSCFG_EXTICR3 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR3_OFFSET) -#define STM32L4_SYSCFG_EXTICR4 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_EXTICR4_OFFSET) -#define STM32L4_SYSCFG_SCSR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SCSR_OFFSET) -#define STM32L4_SYSCFG_CFGR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_CFGR2_OFFSET) -#define STM32L4_SYSCFG_SWPR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR_OFFSET) -#define STM32L4_SYSCFG_SKR (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SKR_OFFSET) -#define STM32L4_SYSCFG_SWPR2 (STM32L4_SYSCFG_BASE+STM32L4_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 21f9264bc52..2a4ff88f8f5 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -176,10 +176,10 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, static const struct stm32_1wire_config_s stm32_1wire1_config = { - .usartbase = STM32L4_USART1_BASE, - .apbclock = STM32L4_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART1_TX), - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, }; static struct stm32_1wire_priv_s stm32_1wire1_priv = @@ -200,10 +200,10 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = static const struct stm32_1wire_config_s stm32_1wire2_config = { - .usartbase = STM32L4_USART2_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART2_TX), - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, }; static struct stm32_1wire_priv_s stm32_1wire2_priv = @@ -224,10 +224,10 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = static const struct stm32_1wire_config_s stm32_1wire3_config = { - .usartbase = STM32L4_USART3_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_USART3_TX), - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, }; static struct stm32_1wire_priv_s stm32_1wire3_priv = @@ -248,10 +248,10 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = static const struct stm32_1wire_config_s stm32_1wire4_config = { - .usartbase = STM32L4_UART4_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART4_TX), - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, }; static struct stm32_1wire_priv_s stm32_1wire4_priv = @@ -272,10 +272,10 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = static const struct stm32_1wire_config_s stm32_1wire5_config = { - .usartbase = STM32L4_UART5_BASE, - .apbclock = STM32L4_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, .data_pin = PIN_OPENDRAIN(GPIO_UART5_TX), - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, }; static struct stm32_1wire_priv_s stm32_1wire5_priv = @@ -338,7 +338,7 @@ static inline void stm32_1wire_out(struct stm32_1wire_priv_s *priv, static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) { - return stm32_1wire_in(priv, STM32L4_USART_RDR_OFFSET) & 0xff; + return stm32_1wire_in(priv, STM32_USART_RDR_OFFSET) & 0xff; } /**************************************************************************** @@ -351,7 +351,7 @@ static int stm32_1wire_recv(struct stm32_1wire_priv_s *priv) static void stm32_1wire_send(struct stm32_1wire_priv_s *priv, int ch) { - stm32_1wire_out(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); + stm32_1wire_out(priv, STM32_USART_TDR_OFFSET, (uint32_t)(ch & 0xff)); } /**************************************************************************** @@ -377,13 +377,13 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) * for baud changing. */ - cr1 = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); enabled = cr1 & USART_CR1_UE; if (enabled) { cr1 &= ~USART_CR1_UE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); } /* In case of oversampling by 8, the equation is: @@ -428,12 +428,12 @@ static void stm32_1wire_set_baud(struct stm32_1wire_priv_s *priv) cr1 |= USART_CR1_OVER8; } - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32_1wire_out(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_1wire_out(priv, STM32_USART_BRR_OFFSET, brr); if (enabled) { - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, cr1 | USART_CR1_UE); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_UE); } } @@ -464,37 +464,37 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, return; #ifdef CONFIG_STM32L4_USART1_1WIREDRIVER - case STM32L4_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L4_USART2_1WIREDRIVER - case STM32L4_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_USART3_1WIREDRIVER - case STM32L4_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART4_1WIREDRIVER - case STM32L4_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART5_1WIREDRIVER - case STM32L4_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -534,33 +534,33 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) * Set LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); regval |= USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 * Clear TE, REm, all interrupt enable bits, PCE, PS and M * Set RXNEIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS | USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); regval |= USART_CR1_RXNEIE; - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 * Clear CTSE, RTSE, and all interrupt enable bits * Set ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); regval |= (USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Set baud rate */ @@ -569,9 +569,9 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Enable Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Configure pins for USART use */ @@ -608,21 +608,21 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Disable RXNEIE, Rx, Tx, and the USART */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE); - stm32_1wire_out(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR1_OFFSET, regval); /* Clear LBDIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR2_OFFSET); regval &= ~USART_CR2_LBDIE; - stm32_1wire_out(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR2_OFFSET, regval); /* Clear ONEBIT, HDSEL and EIE */ - regval = stm32_1wire_in(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32_1wire_in(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_ONEBIT | USART_CR3_HDSEL | USART_CR3_EIE); - stm32_1wire_out(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32_1wire_out(priv, STM32_USART_CR3_OFFSET, regval); /* Disable USART APB1/2 clock */ @@ -765,7 +765,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) /* Get the masked USART status word. */ - sr = stm32_1wire_in(priv, STM32L4_USART_ISR_OFFSET); + sr = stm32_1wire_in(priv, STM32_USART_ISR_OFFSET); /* Receive loop */ @@ -858,7 +858,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); if (priv->msgs != NULL) @@ -873,7 +873,7 @@ static int stm32_1wire_isr(int irq, void *context, void *arg) if ((sr & USART_ISR_LBDF) != 0) { - stm32_1wire_out(priv, STM32L4_USART_ICR_OFFSET, USART_ICR_LBDCF); + stm32_1wire_out(priv, STM32_USART_ICR_OFFSET, USART_ICR_LBDCF); if (priv->msgs != NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index d6f484eed91..52d7977f353 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -81,7 +81,7 @@ /* RCC reset ****************************************************************/ -#define STM32L4_RCC_RSTR STM32L4_RCC_AHB2RSTR +#define STM32_RCC_RSTR STM32_RCC_AHB2RSTR #define RCC_RSTR_ADC1RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC2RST RCC_AHB2RSTR_ADCRST #define RCC_RSTR_ADC3RST RCC_AHB2RSTR_ADCRST @@ -89,7 +89,7 @@ /* ADC interrupts ***********************************************************/ #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# define STM32L4_IRQ_ADC12 STM32L4_IRQ_ADC1 +# define STM32_IRQ_ADC12 STM32_IRQ_ADC1 #endif /* ADC Channels/DMA *********************************************************/ @@ -425,14 +425,14 @@ static struct stm32_dev_s g_adcpriv1 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 1, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC1_RESOLUTION, #endif - .base = STM32L4_ADC1_BASE, + .base = STM32_ADC1_BASE, #if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG) .extcfg = ADC1_EXTCFG_VALUE, #endif @@ -485,14 +485,14 @@ static struct stm32_dev_s g_adcpriv2 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC12, + .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 2, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC2_RESOLUTION, #endif - .base = STM32L4_ADC2_BASE, + .base = STM32_ADC2_BASE, #if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG) .extcfg = ADC2_EXTCFG_VALUE, #endif @@ -545,14 +545,14 @@ static struct stm32_dev_s g_adcpriv3 = .llops = &g_adc_llops, #endif #ifndef CONFIG_STM32L4_ADC_NOIRQ - .irq = STM32L4_IRQ_ADC3, + .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, #endif /* CONFIG_STM32L4_ADC_NOIRQ */ .intf = 3, #ifdef HAVE_ADC_RESOLUTION .resolution = CONFIG_STM32L4_ADC3_RESOLUTION, #endif - .base = STM32L4_ADC3_BASE, + .base = STM32_ADC3_BASE, #if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG) .extcfg = ADC3_EXTCFG_VALUE, #endif @@ -771,38 +771,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -830,14 +830,14 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -870,7 +870,7 @@ static int adc_timinit(struct stm32_dev_s *priv) uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; uint32_t channel = priv->channel - 1; /* If the timer base address is zero, then this ADC was not configured to @@ -955,30 +955,30 @@ static int adc_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* Handle channel specific setup */ /* Assume that channel is disabled and polarity is active high */ - ccer_val = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer_val = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -995,41 +995,41 @@ static int adc_timinit(struct stm32_dev_s *priv) if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = tim_getreg(priv, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; tim_putreg(priv, ccmr_offset, ccmr_orig); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer_val); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer_val); switch (channel) { case 0: /* TIMx CC1 */ { - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; case 1: /* TIMx CC2 */ { - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; case 2: /* TIMx CC3 */ { - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; case 3: /* TIMx CC4 */ { - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -1063,7 +1063,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, container_of(cb, struct stm32_dev_s, pm_callback); uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if ((state >= PM_IDLE) && (regval & ADC_CR_ADSTART)) { return -EBUSY; @@ -1087,16 +1087,16 @@ static void adc_wdog_enable(struct stm32_dev_s *priv) /* Initialize the Analog watchdog enable */ - regval = adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CFGR_OFFSET); regval |= ADC_CFGR_AWD1EN | ADC_CFGR_CONT | ADC_CFGR_OVRMOD; - adc_putreg(priv, STM32L4_ADC_CFGR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CFGR_OFFSET, regval); /* Switch to analog watchdog interrupt */ - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); regval |= ADC_INT_AWD1; regval &= ~ADC_INT_EOC; - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1119,7 +1119,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) ainfo("enable: %d\n", enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); if (enable) { /* Start conversion of regular channels */ @@ -1133,7 +1133,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable) regval |= ADC_CR_ADSTP; } - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); } #ifdef ADC_HAVE_INJECTED @@ -1162,11 +1162,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Start the conversion of regular channels */ - adc_modifyreg(priv, STM32L4_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); + adc_modifyreg(priv, STM32_ADC_CR_OFFSET, 0, ADC_CR_JADSTART); } else { - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Is a conversion ongoing? */ @@ -1174,11 +1174,11 @@ static void adc_inj_startconv(struct stm32_dev_s *priv, bool enable) { /* Stop the conversion */ - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval | ADC_CR_JADSTP); /* Wait for the conversion to stop */ - while ((adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & + while ((adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_JADSTP) != 0); } } @@ -1216,7 +1216,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the AHB2 reset register */ - regval = getreg32(STM32L4_RCC_AHB2RSTR); + regval = getreg32(STM32_RCC_AHB2RSTR); if (reset) { regval |= RCC_AHB2RSTR_ADCRST; @@ -1226,7 +1226,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_AHB2RSTR_ADCRST; } - putreg32(regval, STM32L4_RCC_AHB2RSTR); + putreg32(regval, STM32_RCC_AHB2RSTR); leave_critical_section(flags); } @@ -1247,13 +1247,13 @@ static void adc_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); /* Exit deep power down mode and enable voltage regulator */ regval &= ~ADC_CR_DEEPPWD; regval |= ADC_CR_ADVREGEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for voltage regulator to power up */ @@ -1264,11 +1264,11 @@ static void adc_enable(struct stm32_dev_s *priv) */ regval |= ADC_CR_ADCAL; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for calibration to complete */ - while (adc_getreg(priv, STM32L4_ADC_CR_OFFSET) & ADC_CR_ADCAL); + while (adc_getreg(priv, STM32_ADC_CR_OFFSET) & ADC_CR_ADCAL); /* Enable ADC * Note: ADEN bit cannot be set during ADCAL=1 and 4 ADC clock cycle @@ -1277,13 +1277,13 @@ static void adc_enable(struct stm32_dev_s *priv) * ARM instructions. */ - regval = adc_getreg(priv, STM32L4_ADC_CR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_CR_OFFSET); regval |= ADC_CR_ADEN; - adc_putreg(priv, STM32L4_ADC_CR_OFFSET, regval); + adc_putreg(priv, STM32_ADC_CR_OFFSET, regval); /* Wait for hardware to be ready for conversions */ - while (!(adc_getreg(priv, STM32L4_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); + while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); } /**************************************************************************** @@ -1400,7 +1400,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Set CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); /* Configuration of the channel conversions */ @@ -1432,7 +1432,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_internal(priv, &setbits); - stm32_modifyreg32(STM32L4_ADC_CCR, clrbits, setbits); + stm32_modifyreg32(STM32_ADC_CCR, clrbits, setbits); #ifdef ADC_HAVE_DMA if (priv->hasdma) @@ -1569,7 +1569,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) ainfo("intf: %d enable: %d\n", priv->intf, enable ? 1 : 0); - regval = adc_getreg(priv, STM32L4_ADC_IER_OFFSET); + regval = adc_getreg(priv, STM32_ADC_IER_OFFSET); if (enable) { /* Enable end of conversion interrupt */ @@ -1592,7 +1592,7 @@ static void adc_rxint(struct adc_dev_s *dev, bool enable) regval &= ~ADC_INT_MASK; } - adc_putreg(priv, STM32L4_ADC_IER_OFFSET, regval); + adc_putreg(priv, STM32_ADC_IER_OFFSET, regval); } /**************************************************************************** @@ -1615,7 +1615,7 @@ static int adc_resolution_set(struct adc_dev_s *dev, uint8_t res) /* Modify appropriate register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_RES_MASK, res << ADC_CFGR_RES_SHIFT); errout: @@ -1635,8 +1635,8 @@ static void adc_sample_time_set(struct adc_dev_s *dev) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; - adc_putreg(priv, STM32L4_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); - adc_putreg(priv, STM32L4_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR1_OFFSET, ADC_SMPR1_DEFAULT); + adc_putreg(priv, STM32_ADC_SMPR2_OFFSET, ADC_SMPR2_DEFAULT); } /**************************************************************************** @@ -1673,7 +1673,7 @@ static int adc_extsel_set(struct stm32_dev_s *priv, uint32_t extcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } return OK; @@ -1714,7 +1714,7 @@ static int adc_jextsel_set(struct stm32_dev_s *priv, uint32_t jextcfg) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); } return OK; @@ -1731,25 +1731,25 @@ static void adc_dumpregs(struct stm32_dev_s *priv) ainfo("ISR: 0x%08" PRIx32 " IER: 0x%08" PRIx32 " CR: 0x%08" PRIx32 " CFGR1: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_ISR_OFFSET), - adc_getreg(priv, STM32L4_ADC_IER_OFFSET), - adc_getreg(priv, STM32L4_ADC_CR_OFFSET), - adc_getreg(priv, STM32L4_ADC_CFGR_OFFSET)); + adc_getreg(priv, STM32_ADC_ISR_OFFSET), + adc_getreg(priv, STM32_ADC_IER_OFFSET), + adc_getreg(priv, STM32_ADC_CR_OFFSET), + adc_getreg(priv, STM32_ADC_CFGR_OFFSET)); ainfo("SQR1: 0x%08" PRIx32 " SQR2: 0x%08" PRIx32 " SQR3: 0x%08" PRIx32 " SQR4: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SQR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR2_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR3_OFFSET), - adc_getreg(priv, STM32L4_ADC_SQR4_OFFSET)); + adc_getreg(priv, STM32_ADC_SQR1_OFFSET), + adc_getreg(priv, STM32_ADC_SQR2_OFFSET), + adc_getreg(priv, STM32_ADC_SQR3_OFFSET), + adc_getreg(priv, STM32_ADC_SQR4_OFFSET)); ainfo("SMPR1: 0x%08" PRIx32 " SMPR2: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_SMPR1_OFFSET), - adc_getreg(priv, STM32L4_ADC_SMPR2_OFFSET)); + adc_getreg(priv, STM32_ADC_SMPR1_OFFSET), + adc_getreg(priv, STM32_ADC_SMPR2_OFFSET)); #ifdef ADC_HAVE_INJECTED ainfo("JSQR: 0x%08" PRIx32 "\n", - adc_getreg(priv, STM32L4_ADC_JSQR_OFFSET)); + adc_getreg(priv, STM32_ADC_JSQR_OFFSET)); #endif } @@ -1841,7 +1841,7 @@ static int adc_offset_set(struct stm32_dev_s *priv, goto errout; } - reg = STM32L4_ADC_OFR1_OFFSET + i * 4; + reg = STM32_ADC_OFR1_OFFSET + i * 4; regval = ADC_OFR_OFFSETY_EN; adc_putreg(priv, reg, regval); @@ -1898,23 +1898,23 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); + STM32_ADC_SQR4_OFFSET, ~ADC_SQR4_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR3_FIRST, ADC_SQR3_LAST, ADC_SQR3_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); + STM32_ADC_SQR3_OFFSET, ~ADC_SQR3_RESERVED, bits); bits = adc_sqrbits(priv, ADC_SQR2_FIRST, ADC_SQR2_LAST, ADC_SQR2_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); + STM32_ADC_SQR2_OFFSET, ~ADC_SQR2_RESERVED, bits); bits = ((uint32_t)priv->rnchannels - 1) << ADC_SQR1_L_SHIFT | adc_sqrbits(priv, ADC_SQR1_FIRST, ADC_SQR1_LAST, ADC_SQR1_SQ_OFFSET); adc_modifyreg(priv, - STM32L4_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); + STM32_ADC_SQR1_OFFSET, ~ADC_SQR1_RESERVED, bits); #ifdef ADC_HAVE_DFSDM if (priv->hasdfsdm) @@ -1966,7 +1966,7 @@ static int adc_inj_set_ch(struct adc_dev_s *dev, uint8_t ch) /* Write register */ - adc_modifyreg(priv, STM32L4_ADC_JSQR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_JSQR_OFFSET, clrbits, setbits); return OK; } @@ -2026,7 +2026,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new upper threshold greater than lower threshold */ @@ -2041,7 +2041,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_HT_MASK; regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2051,7 +2051,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */ { - regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + regval = adc_getreg(priv, STM32_ADC_TR1_OFFSET); /* Verify new lower threshold less than upper threshold */ @@ -2066,7 +2066,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) regval &= ~ADC_TR1_LT_MASK; regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK); - adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + adc_putreg(priv, STM32_ADC_TR1_OFFSET, regval); /* Ensure analog watchdog is enabled */ @@ -2133,7 +2133,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) if ((adcisr & ADC_INT_AWD1) != 0) { - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; awarn("WARNING: Analog Watchdog, " @@ -2158,7 +2158,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * (It is cleared by reading the ADC_DR) */ - value = adc_getreg(priv, STM32L4_ADC_DR_OFFSET); + value = adc_getreg(priv, STM32_ADC_DR_OFFSET); value &= ADC_DR_MASK; /* Verify that the upper-half driver has bound its callback functions */ @@ -2198,7 +2198,7 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) { for (i = 0; i < priv->cjchannels; i++) { - value = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * i)) & + value = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * i)) & ADC_JDR_MASK; if (priv->cb != NULL) @@ -2232,7 +2232,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) uint32_t pending; #ifdef CONFIG_STM32L4_ADC1 - regval = getreg32(STM32L4_ADC1_ISR); + regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2240,12 +2240,12 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC1_ISR); + putreg32(regval, STM32_ADC1_ISR); } #endif #ifdef CONFIG_STM32L4_ADC2 - regval = getreg32(STM32L4_ADC2_ISR); + regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2253,7 +2253,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC2_ISR); + putreg32(regval, STM32_ADC2_ISR); } #endif @@ -2279,7 +2279,7 @@ static int adc3_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_ADC3_ISR); + regval = getreg32(STM32_ADC3_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) { @@ -2287,7 +2287,7 @@ static int adc3_interrupt(int irq, void *context, void *arg) /* Clear interrupts */ - putreg32(regval, STM32L4_ADC3_ISR); + putreg32(regval, STM32_ADC3_ISR); } return OK; @@ -2339,7 +2339,7 @@ static void adc_dma_cfg(struct stm32_dev_s *priv) /* Modify CFGR configuration */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, clrbits, setbits); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); } /**************************************************************************** @@ -2362,7 +2362,7 @@ static void adc_dma_start(struct adc_dev_s *dev) #ifndef CONFIG_STM32L4_ADC_NOIRQ stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); @@ -2418,8 +2418,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, /* Restart DMA for the next conversion series */ - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); - adc_modifyreg(priv, STM32L4_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, ADC_CFGR_DMAEN, 0); + adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, 0, ADC_CFGR_DMAEN); } #endif #endif /* ADC_HAVE_DMA */ @@ -2437,7 +2437,7 @@ static void adc_llops_intack(struct stm32_adc_dev_s *dev, /* Clear pending interrupts */ - adc_putreg(priv, STM32L4_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); + adc_putreg(priv, STM32_ADC_ISR_OFFSET, (source & ADC_ISR_ALLINTS)); } /**************************************************************************** @@ -2451,7 +2451,7 @@ static void adc_llops_inten(struct stm32_adc_dev_s *dev, /* Enable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, 0, (source & ADC_IER_ALLINTS)); } /**************************************************************************** @@ -2465,7 +2465,7 @@ static void adc_llops_intdis(struct stm32_adc_dev_s *dev, /* Disable interrupts */ - adc_modifyreg(priv, STM32L4_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); + adc_modifyreg(priv, STM32_ADC_IER_OFFSET, (source & ADC_IER_ALLINTS), 0); } /**************************************************************************** @@ -2478,7 +2478,7 @@ static uint32_t adc_llops_intget(struct stm32_adc_dev_s *dev) uint32_t regval; uint32_t pending; - regval = adc_getreg(priv, STM32L4_ADC_ISR_OFFSET); + regval = adc_getreg(priv, STM32_ADC_ISR_OFFSET); pending = regval & ADC_ISR_ALLINTS; return pending; @@ -2492,7 +2492,7 @@ static uint32_t adc_llops_regget(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - return adc_getreg(priv, STM32L4_ADC_DR_OFFSET) & ADC_DR_MASK; + return adc_getreg(priv, STM32_ADC_DR_OFFSET) & ADC_DR_MASK; } /**************************************************************************** @@ -2545,7 +2545,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; stm32l4_dmasetup(priv->dma, - priv->base + STM32L4_ADC_DR_OFFSET, + priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2578,7 +2578,7 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, dev->dma = stm32l4_dmachannel(dev->dmachan); stm32l4_dmasetup(dev->dma, - dev->base + STM32L4_ADC_DR_OFFSET, + dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); @@ -2639,7 +2639,7 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, goto errout; } - regval = adc_getreg(priv, STM32L4_ADC_JDR1_OFFSET + (4 * chan)) & + regval = adc_getreg(priv, STM32_ADC_JDR1_OFFSET + (4 * chan)) & ADC_JDR_MASK; errout: diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index b2f2c16b7f9..34980e8ccb8 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -91,15 +91,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32L4_ADC3 #endif -#if STM32L4_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32L4_ADC2 #endif -#if STM32L4_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32L4_ADC1 #endif @@ -178,38 +178,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM1_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC1_TIMER_BASE STM32_TIM1_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM2_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC1_TIMER_BASE STM32_TIM2_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM3_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC1_TIMER_BASE STM32_TIM3_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM4_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC1_TIMER_BASE STM32_TIM4_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM6_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC1_TIMER_BASE STM32_TIM6_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM8_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC1_TIMER_BASE STM32_TIM8_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 -# define ADC1_TIMER_BASE STM32L4_TIM15_BASE -# define ADC1_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC1_TIMER_BASE STM32_TIM15_BASE +# define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER @@ -227,38 +227,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM1_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC2_TIMER_BASE STM32_TIM1_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM2_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC2_TIMER_BASE STM32_TIM2_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM3_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC2_TIMER_BASE STM32_TIM3_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM4_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC2_TIMER_BASE STM32_TIM4_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM6_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC2_TIMER_BASE STM32_TIM6_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM8_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC2_TIMER_BASE STM32_TIM8_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 -# define ADC2_TIMER_BASE STM32L4_TIM15_BASE -# define ADC2_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC2_TIMER_BASE STM32_TIM15_BASE +# define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER @@ -276,38 +276,38 @@ #if defined(CONFIG_STM32L4_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM1_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define ADC3_TIMER_BASE STM32_TIM1_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM2_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM2_CLKIN +# define ADC3_TIMER_BASE STM32_TIM2_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM3_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define ADC3_TIMER_BASE STM32_TIM3_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM4_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define ADC3_TIMER_BASE STM32_TIM4_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM6_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define ADC3_TIMER_BASE STM32_TIM6_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM8_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define ADC3_TIMER_BASE STM32_TIM8_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN #elif defined(CONFIG_STM32L4_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 -# define ADC3_TIMER_BASE STM32L4_TIM15_BASE -# define ADC3_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM15_CLKIN +# define ADC3_TIMER_BASE STM32_TIM15_BASE +# define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN # define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 1edbe3d122a..3669cf0233a 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L4_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L4_SRAM3_SIZE -# define SRAM3_START STM32L4_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L4_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 71e397a6325..2d53c1edba8 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -181,13 +181,13 @@ static struct stm32l4_can_s g_can1priv = .port = 1, .canrx = { - STM32L4_IRQ_CAN1RX0, - STM32L4_IRQ_CAN1RX1, + STM32_IRQ_CAN1RX0, + STM32_IRQ_CAN1RX1, }, - .cantx = STM32L4_IRQ_CAN1TX, + .cantx = STM32_IRQ_CAN1TX, .filter = 0, - .base = STM32L4_CAN1_BASE, - .fbase = STM32L4_CAN1_BASE, + .base = STM32_CAN1_BASE, + .fbase = STM32_CAN1_BASE, .baud = CONFIG_STM32L4_CAN1_BAUD, }; @@ -381,18 +381,18 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, /* CAN control and status registers */ caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_MCR_OFFSET), - getreg32(priv->base + STM32L4_CAN_MSR_OFFSET), - getreg32(priv->base + STM32L4_CAN_TSR_OFFSET)); + getreg32(priv->base + STM32_CAN_MCR_OFFSET), + getreg32(priv->base + STM32_CAN_MSR_OFFSET), + getreg32(priv->base + STM32_CAN_TSR_OFFSET)); caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RF0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RF1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RF0R_OFFSET), + getreg32(priv->base + STM32_CAN_RF1R_OFFSET)); caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_IER_OFFSET), - getreg32(priv->base + STM32L4_CAN_ESR_OFFSET), - getreg32(priv->base + STM32L4_CAN_BTR_OFFSET)); + getreg32(priv->base + STM32_CAN_IER_OFFSET), + getreg32(priv->base + STM32_CAN_ESR_OFFSET), + getreg32(priv->base + STM32_CAN_BTR_OFFSET)); } #endif @@ -427,38 +427,38 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" PRIx32 " TDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH0R_OFFSET)); caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" PRIx32 " TDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH1R_OFFSET)); caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" PRIx32 " TDH2R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_TI2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDT2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDL2R_OFFSET), - getreg32(priv->base + STM32L4_CAN_TDH2R_OFFSET)); + getreg32(priv->base + STM32_CAN_TI2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDT2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDL2R_OFFSET), + getreg32(priv->base + STM32_CAN_TDH2R_OFFSET)); caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" PRIx32 " RDH0R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL0R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH0R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL0R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH0R_OFFSET)); caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" PRIx32 " RDH1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_RI1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDT1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDL1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_RDH1R_OFFSET)); + getreg32(priv->base + STM32_CAN_RI1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDT1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDL1R_OFFSET), + getreg32(priv->base + STM32_CAN_RDH1R_OFFSET)); } #endif @@ -494,17 +494,17 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", - getreg32(priv->base + STM32L4_CAN_FMR_OFFSET), - getreg32(priv->base + STM32L4_CAN_FM1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FS1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FFA1R_OFFSET), - getreg32(priv->base + STM32L4_CAN_FA1R_OFFSET)); + getreg32(priv->base + STM32_CAN_FMR_OFFSET), + getreg32(priv->base + STM32_CAN_FM1R_OFFSET), + getreg32(priv->base + STM32_CAN_FS1R_OFFSET), + getreg32(priv->base + STM32_CAN_FFA1R_OFFSET), + getreg32(priv->base + STM32_CAN_FA1R_OFFSET)); for (i = 0; i < CAN_NFILTERS; i++) { caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 1)), - i, getreg32(priv->base + STM32L4_CAN_FIR_OFFSET(i, 2))); + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + STM32_CAN_FIR_OFFSET(i, 2))); } } #endif @@ -555,12 +555,12 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Reset the CAN */ - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); regval &= ~regbit; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); } @@ -714,7 +714,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) /* Enable/disable the FIFO 0/1 message pending interrupt */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); if (enable) { regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; @@ -724,7 +724,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } /**************************************************************************** @@ -752,9 +752,9 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) if (!enable) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval &= ~CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } } @@ -806,7 +806,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t brp; DEBUGASSERT(bt != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> CAN_BTR_SJW_SHIFT) + 1; bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> @@ -815,7 +815,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, CAN_BTR_TS2_SHIFT) + 1; brp = ((regval & CAN_BTR_BRP_MASK) >> CAN_BTR_BRP_SHIFT) + 1; - bt->bt_baud = STM32L4_PCLK1_FREQUENCY / + bt->bt_baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); ret = OK; } @@ -848,18 +848,18 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32L4_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); /* Extract bit timing data. * tmp is in clocks per bit time. */ - tmp = STM32L4_PCLK1_FREQUENCY / bt->bt_baud; + tmp = STM32_PCLK1_FREQUENCY / bt->bt_baud; /* This value is dynamic as requested by user */ @@ -904,12 +904,12 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); if (ret >= 0) { - priv->baud = STM32L4_PCLK1_FREQUENCY / + priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } @@ -934,7 +934,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); @@ -961,7 +961,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, DEBUGASSERT(bm != NULL); - regval = stm32l4can_getreg(priv, STM32L4_CAN_BTR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_BTR_OFFSET); if (bm->bm_loopback) { @@ -989,7 +989,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, break; } - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); } @@ -1078,7 +1078,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_NART; @@ -1088,7 +1088,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_NART; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1102,7 +1102,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, return ret; } - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); if (arg == 1) { regval |= CAN_MCR_ABOM; @@ -1112,7 +1112,7 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, regval &= ~CAN_MCR_ABOM; } - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); return stm32l4can_exitinitmode(priv); } break; @@ -1185,7 +1185,7 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Select one empty transmit mailbox */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); if ((regval & CAN_TSR_TME0) != 0 && (regval & CAN_TSR_RQCP0) == 0) { txmb = 0; @@ -1206,10 +1206,10 @@ static int stm32l4can_send(struct can_dev_s *dev, /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the ID, standard 11-bit or extended 29-bit. */ @@ -1233,15 +1233,15 @@ static int stm32l4can_send(struct can_dev_s *dev, regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); #endif #endif - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); /* Set up the DLC */ dlc = msg->cm_hdr.ch_dlc; - regval = stm32l4can_getreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TDTR_OFFSET(txmb)); regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; - stm32l4can_putreg(priv, STM32L4_CAN_TDTR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDTR_OFFSET(txmb), regval); /* Set up the data fields */ @@ -1272,7 +1272,7 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDLR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); regval = 0; if (dlc > 4) @@ -1299,19 +1299,19 @@ static int stm32l4can_send(struct can_dev_s *dev, } } - stm32l4can_putreg(priv, STM32L4_CAN_TDHR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); /* Enable the transmit mailbox empty interrupt (may already be enabled) */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_IER_OFFSET); regval |= CAN_IER_TMEIE; - stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_IER_OFFSET, regval); /* Request transmission */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_TIR_OFFSET(txmb)); regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ - stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); + stm32l4can_putreg(priv, STM32_CAN_TIR_OFFSET(txmb), regval); stm32l4can_dumpmbregs(priv, "After send"); return OK; @@ -1338,7 +1338,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev) /* Return true if any mailbox is available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) != 0; @@ -1369,7 +1369,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) /* Return true if all mailboxes are available */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08" PRIx32 "\n", priv->port, regval); return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES; @@ -1406,7 +1406,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Verify that a message is pending in the FIFO */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; if (npending < 1) { @@ -1425,7 +1425,7 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the CAN identifier. */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RIR_OFFSET(rxmb)); #ifdef CONFIG_CAN_EXTID if ((regval & CAN_RIR_IDE) != 0) @@ -1462,18 +1462,18 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) /* Get the DLC */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDTR_OFFSET(rxmb)); hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; /* Save the message data */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDLR_OFFSET(rxmb)); data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RDHR_OFFSET(rxmb)); data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; @@ -1488,9 +1488,9 @@ static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) #ifndef CONFIG_CAN_EXTID errout: #endif - regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); + regval = stm32l4can_getreg(priv, STM32_CAN_RFR_OFFSET(rxmb)); regval |= CAN_RFR_RFOM; - stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval); + stm32l4can_putreg(priv, STM32_CAN_RFR_OFFSET(rxmb), regval); return ret; } @@ -1560,7 +1560,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) /* Get the transmit status */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_TSR_OFFSET); /* Check for RQCP0: Request completed mailbox 0 */ @@ -1570,7 +1570,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST0 and TERR0) for Mailbox 0. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); /* Check for errors */ @@ -1590,7 +1590,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST1 and TERR1) for Mailbox 1. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); /* Check for errors */ @@ -1610,7 +1610,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ALST2 and TERR2) for Mailbox 2. */ - stm32l4can_putreg(priv, STM32L4_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + stm32l4can_putreg(priv, STM32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); /* Check for errors */ @@ -1690,7 +1690,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) uint32_t ts2; caninfo("CAN%d PCLK1: %d baud: %d\n", - priv->port, STM32L4_PCLK1_FREQUENCY, priv->baud); + priv->port, STM32_PCLK1_FREQUENCY, priv->baud); /* Try to get CAN_BIT_QUANTA quanta in one bit_time. * @@ -1708,7 +1708,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 */ - tmp = STM32L4_PCLK1_FREQUENCY / priv->baud; + tmp = STM32_PCLK1_FREQUENCY / priv->baud; if (tmp < CAN_BIT_QUANTA) { /* At the smallest brp value (1), there are already too few bit times @@ -1762,7 +1762,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) tmp |= CAN_BTR_LBKM; #endif - stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, tmp); + stm32l4can_putreg(priv, STM32_CAN_BTR_OFFSET, tmp); return OK; } @@ -1791,15 +1791,15 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) /* Enter initialization mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval |= CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until initialization mode is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) != 0) { /* We are in initialization mode */ @@ -1840,15 +1840,15 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) /* Exit Initialization mode, enter Normal mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_INRQ; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Wait until the initialization mode exit is acknowledged */ for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) { - regval = stm32l4can_getreg(priv, STM32L4_CAN_MSR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MSR_OFFSET); if ((regval & CAN_MSR_INAK) == 0) { /* We are out of initialization mode */ @@ -1893,9 +1893,9 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) /* Exit from sleep mode */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_SLEEP; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); ret = stm32l4can_enterinitmode(priv); if (ret != 0) @@ -1913,10 +1913,10 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * - Transmit FIFO priority */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); + regval = stm32l4can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); + stm32l4can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); /* Configure bit timing. */ @@ -1975,52 +1975,52 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) /* Enter filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval |= CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); /* Disable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Select the 32-bit scale for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FS1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FS1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FS1R_OFFSET, regval); /* There are 14 or 28 filter banks (depending) on the device. * Each filter bank is composed of two 32-bit registers, CAN_FiR: */ - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32l4can_putfreg(priv, STM32_CAN_FIR_OFFSET(priv->filter, 2), 0); /* Set Id/Mask mode for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FM1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FM1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FM1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FM1R_OFFSET, regval); /* Assign FIFO 0 for the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FFA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FFA1R_OFFSET); regval &= ~bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FFA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FFA1R_OFFSET, regval); /* Enable the filter */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FA1R_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FA1R_OFFSET); regval |= bitmask; - stm32l4can_putfreg(priv, STM32L4_CAN_FA1R_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FA1R_OFFSET, regval); /* Exit filter initialization mode */ - regval = stm32l4can_getfreg(priv, STM32L4_CAN_FMR_OFFSET); + regval = stm32l4can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= ~CAN_FMR_FINIT; - stm32l4can_putfreg(priv, STM32L4_CAN_FMR_OFFSET, regval); + stm32l4can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 8328d9a13fb..2a33a504bf3 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -42,7 +42,7 @@ /* Up to 1 CAN interfaces are supported */ -#if STM32L4_NCAN < 1 +#if STM32_NCAN < 1 # undef CONFIG_STM32L4_CAN1 #endif diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 6bc365394b3..a2af78f8421 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -104,12 +104,12 @@ static struct stm32l4_comp_config_s g_comp1priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_2, - .inm = STM32L4_COMP_INM_VREF, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_2, + .inm = STM32_COMP_INM_VREF, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP1_CSR, + .csr = STM32_COMP1_CSR, }; static struct comp_dev_s g_comp1dev = @@ -126,12 +126,12 @@ static struct stm32l4_comp_config_s g_comp2priv = .rising = true, .falling = false }, - .inp = STM32L4_COMP_INP_PIN_1, - .inm = STM32L4_COMP_INM_DAC_1, - .hyst = STM32L4_COMP_HYST_LOW, - .speed = STM32L4_COMP_SPEED_MEDIUM, + .inp = STM32_COMP_INP_PIN_1, + .inm = STM32_COMP_INM_DAC_1, + .hyst = STM32_COMP_HYST_LOW, + .speed = STM32_COMP_SPEED_MEDIUM, .inverted = false, - .csr = STM32L4_COMP2_CSR, + .csr = STM32_COMP2_CSR, }; static struct comp_dev_s g_comp2dev = @@ -324,7 +324,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); - ainfo("isr: %d\n", (cfg->csr == STM32L4_COMP1_CSR ? 0 : 1)); + ainfo("isr: %d\n", (cfg->csr == STM32_COMP1_CSR ? 0 : 1)); cfg->interrupt.cb->au_notify(dev, comp_read(dev)); @@ -356,28 +356,28 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) int cmp; cfg = dev->ad_priv; - cmp = cfg->csr == STM32L4_COMP1_CSR ? STM32L4_COMP1 : STM32L4_COMP2; + cmp = cfg->csr == STM32_COMP1_CSR ? STM32_COMP1 : STM32_COMP2; /* Input plus */ mask |= COMP_CSR_INPSEL_MASK; switch (cfg->inp) { - case STM32L4_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_1 : + case STM32_COMP_INP_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; - case STM32L4_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_2 : + case STM32_COMP_INP_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; #if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INP_3 : + case STM32_COMP_INP_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -392,46 +392,46 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_INMSEL_MASK; switch (cfg->inm) { - case STM32L4_COMP_INM_1_4_VREF: + case STM32_COMP_INM_1_4_VREF: regval |= COMP_CSR_INMSEL_25PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_1_2_VREF: + case STM32_COMP_INM_1_2_VREF: regval |= COMP_CSR_INMSEL_50PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_3_4_VREF: + case STM32_COMP_INM_3_4_VREF: regval |= COMP_CSR_INMSEL_75PCT; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); break; - case STM32L4_COMP_INM_VREF: + case STM32_COMP_INM_VREF: regval |= COMP_CSR_INMSEL_VREF; mask |= (COMP_CSR_SCALEN | COMP_CSR_BRGEN); regval |= COMP_CSR_SCALEN; break; - case STM32L4_COMP_INM_DAC_1: + case STM32_COMP_INM_DAC_1: regval |= COMP_CSR_INMSEL_DAC1; break; - case STM32L4_COMP_INM_DAC_2: + case STM32_COMP_INM_DAC_2: regval |= COMP_CSR_INMSEL_DAC2; break; - case STM32L4_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_1 : + case STM32_COMP_INM_PIN_1: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; - case STM32L4_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_2 : + case STM32_COMP_INM_PIN_2: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) @@ -444,24 +444,24 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; #if defined(CONFIG_STM32L4_STM32L4X3) - case STM32L4_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_3 : + case STM32_COMP_INM_PIN_3: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN3; break; - case STM32L4_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_4 : + case STM32_COMP_INM_PIN_4: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; regval |= COMP_CSR_INMESEL_PIN4; break; - case STM32L4_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32L4_COMP1 ? GPIO_COMP1_INM_5 : + case STM32_COMP_INM_PIN_5: + stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -478,19 +478,19 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_HYST_MASK; switch (cfg->hyst) { - case STM32L4_COMP_HYST_NONE: + case STM32_COMP_HYST_NONE: regval |= COMP_CSR_HYST_NONE; break; - case STM32L4_COMP_HYST_LOW: + case STM32_COMP_HYST_LOW: regval |= COMP_CSR_HYST_LOW; break; - case STM32L4_COMP_HYST_MEDIUM: + case STM32_COMP_HYST_MEDIUM: regval |= COMP_CSR_HYST_MEDIUM; break; - case STM32L4_COMP_HYST_HIGH: + case STM32_COMP_HYST_HIGH: regval |= COMP_CSR_HYST_HIGH; break; @@ -503,15 +503,15 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) mask |= COMP_CSR_PWRMODE_MASK; switch (cfg->speed) { - case STM32L4_COMP_SPEED_HIGH: + case STM32_COMP_SPEED_HIGH: regval |= COMP_CSR_PWRMODE_HIGH; break; - case STM32L4_COMP_SPEED_MEDIUM: + case STM32_COMP_SPEED_MEDIUM: regval |= COMP_CSR_PWRMODE_MEDIUM; break; - case STM32L4_COMP_SPEED_LOW: + case STM32_COMP_SPEED_LOW: regval |= COMP_CSR_PWRMODE_LOW; break; diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index d862d14a9ee..0414ed9f774 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -56,35 +56,35 @@ enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ - STM32L4_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_3 /* COMP1: PA1, COMP2: PA3 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ - STM32L4_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ - STM32L4_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ - STM32L4_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2, /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_PIN_3, /* COMP1: PA0, COMP2: PA2 */ + STM32_COMP_INM_PIN_4, /* COMP1: PA4, COMP2: PA4 */ + STM32_COMP_INM_PIN_5 /* COMP1: PA5, COMP2: PA5 */ }; #else @@ -93,31 +93,31 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_e { - STM32L4_COMP1, - STM32L4_COMP2, - STM32L4_COMP_NUM /* Number of comparators */ + STM32_COMP1, + STM32_COMP2, + STM32_COMP_NUM /* Number of comparators */ }; /* Plus input */ enum stm32l4_comp_inp_e { - STM32L4_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ - STM32L4_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ + STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ + STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ }; /* Minus input */ enum stm32l4_comp_inm_e { - STM32L4_COMP_INM_1_4_VREF, - STM32L4_COMP_INM_1_2_VREF, - STM32L4_COMP_INM_3_4_VREF, - STM32L4_COMP_INM_VREF, - STM32L4_COMP_INM_DAC_1, - STM32L4_COMP_INM_DAC_2, - STM32L4_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ - STM32L4_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ + STM32_COMP_INM_1_4_VREF, + STM32_COMP_INM_1_2_VREF, + STM32_COMP_INM_3_4_VREF, + STM32_COMP_INM_VREF, + STM32_COMP_INM_DAC_1, + STM32_COMP_INM_DAC_2, + STM32_COMP_INM_PIN_1, /* COMP1: PB1, COMP2: PB3 */ + STM32_COMP_INM_PIN_2 /* COMP1: PC4, COMP2: PB7 */ }; #endif @@ -125,19 +125,19 @@ enum stm32l4_comp_inm_e enum stm32l4_comp_hyst_e { - STM32L4_COMP_HYST_NONE, - STM32L4_COMP_HYST_LOW, - STM32L4_COMP_HYST_MEDIUM, - STM32L4_COMP_HYST_HIGH + STM32_COMP_HYST_NONE, + STM32_COMP_HYST_LOW, + STM32_COMP_HYST_MEDIUM, + STM32_COMP_HYST_HIGH }; /* Power/Speed Modes */ enum stm32l4_comp_speed_e { - STM32L4_COMP_SPEED_HIGH, - STM32L4_COMP_SPEED_MEDIUM, - STM32L4_COMP_SPEED_LOW + STM32_COMP_SPEED_HIGH, + STM32_COMP_SPEED_MEDIUM, + STM32_COMP_SPEED_LOW }; /* Comparator configuration *************************************************/ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index a2c59beca17..a529515e70e 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -55,18 +55,18 @@ /* Up to 1 DAC interface for up to 2 channels are supported */ -#if STM32L4_NDAC > 2 +#if STM32_NDAC > 2 # warning "Extra DAC channels. Only DAC1 and DAC2 are supported" #endif -#if STM32L4_NDAC < 2 +#if STM32_NDAC < 2 # undef CONFIG_STM32L4_DAC2 # undef CONFIG_STM32L4_DAC2_DMA # undef CONFIG_STM32L4_DAC2_TIMER # undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY #endif -#if STM32L4_NDAC < 1 +#if STM32_NDAC < 1 # undef CONFIG_STM32L4_DAC1 # undef CONFIG_STM32L4_DAC1_DMA # undef CONFIG_STM32L4_DAC1_TIMER @@ -178,47 +178,47 @@ # endif # define NEED_TIM6 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC1_TIMER_BASE STM32L4_TIM6_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM6_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 8 # ifndef CONFIG_STM32L4_TIM8_DAC # error "CONFIG_STM32L4_TIM8_DAC required for DAC1" # endif # define NEED_TIM8 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC1_TIMER_BASE STM32L4_TIM8_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM8_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 7 # ifndef CONFIG_STM32L4_TIM7_DAC # error "CONFIG_STM32L4_TIM7_DAC required for DAC1" # endif # define NEED_TIM7 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC1_TIMER_BASE STM32L4_TIM7_BASE +# define DAC1_TIMER_BASE STM32_TIM7_BASE # elif CONFIG_STM32L4_DAC1_TIMER == 5 # ifndef CONFIG_STM32L4_TIM5_DAC # error "CONFIG_STM32L4_TIM5_DAC required for DAC1" # endif # define NEED_TIM5 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC1_TIMER_BASE STM32L4_TIM5_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM5_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 2 # ifndef CONFIG_STM32L4_TIM2_DAC # error "CONFIG_STM32L4_TIM2_DAC required for DAC1" # endif # define NEED_TIM2 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC1_TIMER_BASE STM32L4_TIM2_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM2_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC1_TIMER == 4 # ifndef CONFIG_STM32L4_TIM4_DAC # error "CONFIG_STM32L4_TIM4_DAC required for DAC1" # endif # define NEED_TIM4 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC1_TIMER_BASE STM32L4_TIM4_BASE -# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC1_TIMER_BASE STM32_TIM4_BASE +# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else # error "Unsupported CONFIG_STM32L4_DAC1_TIMER" # endif @@ -232,43 +232,43 @@ # error "CONFIG_STM32L4_TIM6_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6 -# define DAC2_TIMER_BASE STM32L4_TIM6_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM6_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 8 # ifndef CONFIG_STM32L4_TIM8_DAC # error "CONFIG_STM32L4_TIM8_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8 -# define DAC2_TIMER_BASE STM32L4_TIM8_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK2_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM8_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 7 # ifndef CONFIG_STM32L4_TIM7_DAC # error "CONFIG_STM32L4_TIM7_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7 -# define DAC2_TIMER_BASE STM32L4_TIM7_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM7_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 5 # ifndef CONFIG_STM32L4_TIM5_DAC # error "CONFIG_STM32L4_TIM5_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5 -# define DAC2_TIMER_BASE STM32L4_TIM5_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM5_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 2 # ifndef CONFIG_STM32L4_TIM2_DAC # error "CONFIG_STM32L4_TIM2_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2 -# define DAC2_TIMER_BASE STM32L4_TIM2_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM2_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # elif CONFIG_STM32L4_DAC2_TIMER == 4 # ifndef CONFIG_STM32L4_TIM4_DAC # error "CONFIG_STM32L4_TIM4_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4 -# define DAC2_TIMER_BASE STM32L4_TIM4_BASE -# define DAC2_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY +# define DAC2_TIMER_BASE STM32_TIM4_BASE +# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else # error "Unsupported CONFIG_STM32L4_DAC2_TIMER" # endif @@ -422,8 +422,8 @@ static struct stm32_chan_s g_dac1priv = #else .pin = GPIO_DAC1_OUT, #endif - .dro = STM32L4_DAC_DHR12R1, - .cr = STM32L4_DAC_CR, + .dro = STM32_DAC_DHR12R1, + .cr = STM32_DAC_CR, #ifdef CONFIG_STM32L4_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, @@ -462,8 +462,8 @@ static struct stm32_chan_s g_dac2priv = #else .pin = GPIO_DAC2_OUT, #endif - .dro = STM32L4_DAC_DHR12R2, - .cr = STM32L4_DAC_CR, + .dro = STM32_DAC_DHR12R2, + .cr = STM32_DAC_CR, #ifdef CONFIG_STM32L4_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, @@ -507,7 +507,7 @@ static struct stm32_dac_s g_dacblock; static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) { - return getreg32(STM32L4_DAC_BASE + offset); + return getreg32(STM32_DAC_BASE + offset); } /**************************************************************************** @@ -532,7 +532,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC[1]_CR control register. If + /* DAC channels 1 and 2 share the STM32_DAC[1]_CR control register. If * future chips have DAC channel 3 (and perhaps channel 4) they likely have * their own register like in STM32. In either case, bit 0 of the interface * number provides the correct shift. @@ -567,7 +567,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, { unsigned int shift; - /* DAC channels 1 and 2 share the STM32L4_DAC_MCR control register. + /* DAC channels 1 and 2 share the STM32_DAC_MCR control register. * Bit 0 of the interface number provides the correct shift. * * Bit 0 = 0: Shift = 0 @@ -575,7 +575,7 @@ static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, */ shift = (chan->intf & 1) << 4; - modifyreg32(STM32L4_DAC_MCR, clearbits << shift, setbits << shift); + modifyreg32(STM32_DAC_MCR, clearbits << shift, setbits << shift); } /**************************************************************************** @@ -588,10 +588,10 @@ static void dac_dumpregs(struct stm32_chan_s *priv) ainfo("CR: 0x%08" PRIx32 " SWTRGR: 0x%08" PRIx32 "SR: 0x%08" PRIx32 " MCR: 0x%08" PRIx32 "\n", - dac_getreg(priv, STM32L4_DAC_CR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SWTRIGR_OFFSET), - dac_getreg(priv, STM32L4_DAC_SR_OFFSET), - dac_getreg(priv, STM32L4_DAC_MCR_OFFSET)); + dac_getreg(priv, STM32_DAC_CR_OFFSET), + dac_getreg(priv, STM32_DAC_SWTRIGR_OFFSET), + dac_getreg(priv, STM32_DAC_SR_OFFSET), + dac_getreg(priv, STM32_DAC_MCR_OFFSET)); } /**************************************************************************** @@ -867,7 +867,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Reset counters (generate an update) */ #ifdef HAVE_DMA - tim_modifyreg(chan, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(chan, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); #endif return OK; } @@ -923,7 +923,7 @@ static int dac_timinit(struct stm32_chan_s *chan) * default) will be enabled */ - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; switch (chan->timer) { @@ -965,7 +965,7 @@ static int dac_timinit(struct stm32_chan_s *chan) #endif #ifdef NEED_TIM8 case 8: - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; setbits = RCC_APB2ENR_TIM8EN; pclk = BOARD_TIM8_FREQUENCY; break; @@ -1036,26 +1036,26 @@ static int dac_timinit(struct stm32_chan_s *chan) /* Set the reload and prescaler values */ - tim_putreg(chan, STM32L4_GTIM_ARR_OFFSET, (uint16_t)reload); - tim_putreg(chan, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + tim_putreg(chan, STM32_GTIM_ARR_OFFSET, (uint16_t)reload); + tim_putreg(chan, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); /* Count mode up, auto reload */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Selection TRGO selection: update */ - tim_modifyreg(chan, STM32L4_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, + tim_modifyreg(chan, STM32_GTIM_CR2_OFFSET, GTIM_CR2_MMS_MASK, GTIM_CR2_MMS_UPDATE); /* Update DMA request enable ???? */ #if 0 - tim_modifyreg(chan, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); + tim_modifyreg(chan, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UDE); #endif /* Enable the counter */ - tim_modifyreg(chan, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(chan, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); return OK; } #endif @@ -1200,14 +1200,14 @@ static void dac_blockinit(void) /* Put the entire DAC block in reset state */ flags = enter_critical_section(); - regval = getreg32(STM32L4_RCC_APB1RSTR1); + regval = getreg32(STM32_RCC_APB1RSTR1); regval |= RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); /* Take the DAC out of reset state */ regval &= ~RCC_APB1RSTR1_DAC1RST; - putreg32(regval, STM32L4_RCC_APB1RSTR1); + putreg32(regval, STM32_RCC_APB1RSTR1); leave_critical_section(flags); /* Mark the DAC block as initialized */ @@ -1286,7 +1286,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) /* Reset counters (generate an update) */ - tim_modifyreg(priv, STM32L4_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); + tim_modifyreg(priv, STM32_GTIM_EGR_OFFSET, 0, GTIM_EGR_UG); } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 0c4d0c95344..451f8050480 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -75,21 +75,21 @@ /* Abbreviated register access **********************************************/ -#define CHCFGR1_OFFSET(priv) STM32L4_DFSDM_CHCFGR1_OFFSET((priv)->current) -#define CHCFGR2_OFFSET(priv) STM32L4_DFSDM_CHCFGR2_OFFSET((priv)->current) +#define CHCFGR1_OFFSET(priv) STM32_DFSDM_CHCFGR1_OFFSET((priv)->current) +#define CHCFGR2_OFFSET(priv) STM32_DFSDM_CHCFGR2_OFFSET((priv)->current) -#define FLTCR1_OFFSET(priv) STM32L4_DFSDM_FLTCR1_OFFSET((priv)->intf) -#define FLTCR2_OFFSET(priv) STM32L4_DFSDM_FLTCR2_OFFSET((priv)->intf) -#define FLTISR_OFFSET(priv) STM32L4_DFSDM_FLTISR_OFFSET((priv)->intf) -#define FLTICR_OFFSET(priv) STM32L4_DFSDM_FLTICR_OFFSET((priv)->intf) -#define FLTFCR_OFFSET(priv) STM32L4_DFSDM_FLTFCR_OFFSET((priv)->intf) -#define FLTRDATAR_OFFSET(priv) STM32L4_DFSDM_FLTRDATAR_OFFSET((priv)->intf) -#define FLTAWHTR_OFFSET(priv) STM32L4_DFSDM_FLTAWHTR_OFFSET((priv)->intf) -#define FLTAWLTR_OFFSET(priv) STM32L4_DFSDM_FLTAWLTR_OFFSET((priv)->intf) -#define FLTAWSR_OFFSET(priv) STM32L4_DFSDM_FLTAWSR_OFFSET((priv)->intf) -#define FLTAWCFR_OFFSET(priv) STM32L4_DFSDM_FLTAWCFR_OFFSET((priv)->intf) -#define FLTEXMAX_OFFSET(priv) STM32L4_DFSDM_FLTEXMAX_OFFSET((priv)->intf) -#define FLTEXMIN_OFFSET(priv) STM32L4_DFSDM_FLTEXMIN_OFFSET((priv)->intf) +#define FLTCR1_OFFSET(priv) STM32_DFSDM_FLTCR1_OFFSET((priv)->intf) +#define FLTCR2_OFFSET(priv) STM32_DFSDM_FLTCR2_OFFSET((priv)->intf) +#define FLTISR_OFFSET(priv) STM32_DFSDM_FLTISR_OFFSET((priv)->intf) +#define FLTICR_OFFSET(priv) STM32_DFSDM_FLTICR_OFFSET((priv)->intf) +#define FLTFCR_OFFSET(priv) STM32_DFSDM_FLTFCR_OFFSET((priv)->intf) +#define FLTRDATAR_OFFSET(priv) STM32_DFSDM_FLTRDATAR_OFFSET((priv)->intf) +#define FLTAWHTR_OFFSET(priv) STM32_DFSDM_FLTAWHTR_OFFSET((priv)->intf) +#define FLTAWLTR_OFFSET(priv) STM32_DFSDM_FLTAWLTR_OFFSET((priv)->intf) +#define FLTAWSR_OFFSET(priv) STM32_DFSDM_FLTAWSR_OFFSET((priv)->intf) +#define FLTAWCFR_OFFSET(priv) STM32_DFSDM_FLTAWCFR_OFFSET((priv)->intf) +#define FLTEXMAX_OFFSET(priv) STM32_DFSDM_FLTEXMAX_OFFSET((priv)->intf) +#define FLTEXMIN_OFFSET(priv) STM32_DFSDM_FLTEXMIN_OFFSET((priv)->intf) /* DFSDM Filter interrupts **************************************************/ @@ -277,10 +277,10 @@ static const struct adc_ops_s g_adcops = #if defined(CONFIG_STM32L4_DFSDM1_FLT0) static struct stm32_dev_s g_dfsdmpriv0 = { - .irq = STM32L4_IRQ_DFSDM0, + .irq = STM32_IRQ_DFSDM0, .isr = dfsdm_flt0_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -306,10 +306,10 @@ static struct adc_dev_s g_dfsdmdev0 = #if defined(CONFIG_STM32L4_DFSDM1_FLT1) static struct stm32_dev_s g_dfsdmpriv1 = { - .irq = STM32L4_IRQ_DFSDM1, + .irq = STM32_IRQ_DFSDM1, .isr = dfsdm_flt1_interrupt, .intf = 1, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -335,10 +335,10 @@ static struct adc_dev_s g_dfsdmdev1 = #if defined(CONFIG_STM32L4_DFSDM1_FLT2) static struct stm32_dev_s g_dfsdmpriv2 = { - .irq = STM32L4_IRQ_DFSDM2, + .irq = STM32_IRQ_DFSDM2, .isr = dfsdm_flt2_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -364,10 +364,10 @@ static struct adc_dev_s g_dfsdmdev2 = #if defined(CONFIG_STM32L4_DFSDM1_FLT3) static struct stm32_dev_s g_dfsdmpriv3 = { - .irq = STM32L4_IRQ_DFSDM3, + .irq = STM32_IRQ_DFSDM3, .isr = dfsdm_flt3_interrupt, .intf = 0, - .base = STM32L4_DFSDM_BASE, + .base = STM32_DFSDM_BASE, #ifdef DFSDM_HAVE_TIMER .trigger = CONFIG_STM32L4_DFSDM_TIMTRIG, .tbase = DFSDM_TIMER_BASE, @@ -548,38 +548,38 @@ static void tim_dumpregs(struct stm32_dev_s *priv, const char *msg) { ainfo("%s:\n", msg); ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + tim_getreg(priv, STM32_GTIM_CR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CR2_OFFSET), + tim_getreg(priv, STM32_GTIM_SMCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DIER_OFFSET)); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - tim_getreg(priv, STM32L4_GTIM_SR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + tim_getreg(priv, STM32_GTIM_SR_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - tim_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - tim_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCER_OFFSET), + tim_getreg(priv, STM32_GTIM_CNT_OFFSET), + tim_getreg(priv, STM32_GTIM_PSC_OFFSET), + tim_getreg(priv, STM32_GTIM_ARR_OFFSET)); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - tim_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - tim_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + tim_getreg(priv, STM32_GTIM_CCR1_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR2_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR3_OFFSET), + tim_getreg(priv, STM32_GTIM_CCR4_OFFSET)); - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_ATIM_RCR_OFFSET), + tim_getreg(priv, STM32_ATIM_BDTR_OFFSET), + tim_getreg(priv, STM32_ATIM_DCR_OFFSET), + tim_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - tim_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - tim_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + tim_getreg(priv, STM32_GTIM_DCR_OFFSET), + tim_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -607,13 +607,13 @@ static void dfsdm_timstart(struct stm32_dev_s *priv, bool enable) { /* Start the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable the counter */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } } #endif @@ -747,24 +747,24 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) clrbits = GTIM_CR1_DIR | GTIM_CR1_CMS_MASK | GTIM_CR1_CKD_MASK; setbits = GTIM_CR1_EDGE; - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, clrbits, setbits); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, clrbits, setbits); /* Set the reload and prescaler values */ - tim_putreg(priv, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - tim_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); + tim_putreg(priv, STM32_GTIM_PSC_OFFSET, prescaler - 1); + tim_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); /* Clear the advanced timers repetition counter in TIM1 */ - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { - tim_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); - tim_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ + tim_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); + tim_putreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE); /* Check me */ } /* TIMx event generation: Bit 0 UG: Update generation */ - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Handle channel specific setup */ @@ -788,7 +788,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR1_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR1_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -808,7 +808,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR2_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR2_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -828,7 +828,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR3_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR3_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -848,7 +848,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -866,7 +866,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) * channel */ - tim_putreg(priv, STM32L4_GTIM_CCR4_OFFSET, + tim_putreg(priv, STM32_GTIM_CCR4_OFFSET, (uint16_t)(reload >> 1)); } break; @@ -878,15 +878,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Disable the Channel by resetting the CCxE Bit in the CCER register */ - ccer = tim_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = tim_getreg(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~ccenable; - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Fetch the CR2, CCMR1, and CCMR2 register (already have ccer) */ - cr2 = tim_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccmr1 = tim_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccmr2 = tim_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET); + cr2 = tim_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccmr1 = tim_getreg(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr2 = tim_getreg(priv, STM32_GTIM_CCMR2_OFFSET); /* Reset the Output Compare Mode Bits and set the select output compare * mode @@ -912,7 +912,7 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) ATIM_CCER_CC3E | ATIM_CCER_CC4E); ccer |= ccenable; - if (priv->tbase == STM32L4_TIM1_BASE || priv->tbase == STM32L4_TIM8_BASE) + if (priv->tbase == STM32_TIM1_BASE || priv->tbase == STM32_TIM8_BASE) { /* Reset output N polarity level, output N state, output compare state, * output compare N idle state. @@ -937,15 +937,15 @@ static int dfsdm_timinit(struct stm32_dev_s *priv) /* Save the modified register values */ - tim_putreg(priv, STM32L4_GTIM_CR2_OFFSET, cr2); - tim_putreg(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - tim_putreg(priv, STM32L4_GTIM_CCMR2_OFFSET, ccmr2); - tim_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); - tim_putreg(priv, STM32L4_GTIM_EGR_OFFSET, egr); + tim_putreg(priv, STM32_GTIM_CR2_OFFSET, cr2); + tim_putreg(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + tim_putreg(priv, STM32_GTIM_CCMR2_OFFSET, ccmr2); + tim_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); + tim_putreg(priv, STM32_GTIM_EGR_OFFSET, egr); /* Set the ARR Preload Bit */ - tim_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); + tim_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_ARPE); /* Enable the timer counter */ @@ -1050,7 +1050,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) /* Set or clear the selected bit in the APB2 reset register */ - regval = getreg32(STM32L4_RCC_APB2RSTR); + regval = getreg32(STM32_RCC_APB2RSTR); if (reset) { regval |= RCC_APB2RSTR_DFSDMRST; @@ -1060,7 +1060,7 @@ static void dfsdm_rccreset(struct stm32_dev_s *priv, bool reset) regval &= ~RCC_APB2RSTR_DFSDMRST; } - putreg32(regval, STM32L4_RCC_APB2RSTR); + putreg32(regval, STM32_RCC_APB2RSTR); leave_critical_section(flags); } @@ -1079,12 +1079,12 @@ static void dfsdm_enable(struct stm32_dev_s *priv) { uint32_t regval; - regval = dfsdm_getreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET); + regval = dfsdm_getreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET); /* Enable DFSMDM */ regval |= DFSDM_CH0CFGR1_DFSDMEN; - dfsdm_putreg(priv, STM32L4_DFSDM_CH0CFGR1_OFFSET, regval); + dfsdm_putreg(priv, STM32_DFSDM_CH0CFGR1_OFFSET, regval); } /**************************************************************************** @@ -1588,7 +1588,7 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(0)); + regval = getreg32(STM32_DFSDM_FLTISR(0)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1613,7 +1613,7 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(1)); + regval = getreg32(STM32_DFSDM_FLTISR(1)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1638,7 +1638,7 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(2)); + regval = getreg32(STM32_DFSDM_FLTISR(2)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { @@ -1663,7 +1663,7 @@ static int dfsdm_flt3_interrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t pending; - regval = getreg32(STM32L4_DFSDM_FLTISR(3)); + regval = getreg32(STM32_DFSDM_FLTISR(3)); pending = regval & DFSDM_ISR_MASK; if (pending != 0) { diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 6039443f5ab..5e763736b20 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -91,32 +91,32 @@ #if defined(CONFIG_STM32L4_TIM1_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM1_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM1_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM1_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN #elif defined(CONFIG_STM32L4_TIM3_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM3_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM3_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM3_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN #elif defined(CONFIG_STM32L4_TIM4_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM4_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM4_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM4_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN #elif defined(CONFIG_STM32L4_TIM6_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM6_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM6_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM6_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN #elif defined(CONFIG_STM32L4_TIM7_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM7_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB1_TIM7_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM7_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB1_TIM7_CLKIN #elif defined(CONFIG_STM32L4_TIM8_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM8_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM8_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM8_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN #elif defined(CONFIG_STM32L4_TIM16_DFSDM) # define DFSDM_HAVE_TIMER 1 -# define DFSDM_TIMER_BASE STM32L4_TIM16_BASE -# define DFSDM_TIMER_PCLK_FREQUENCY STM32L4_APB2_TIM16_CLKIN +# define DFSDM_TIMER_BASE STM32_TIM16_BASE +# define DFSDM_TIMER_PCLK_FREQUENCY STM32_APB2_TIM16_CLKIN #else # undef DFSDM_HAVE_TIMER #endif diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 026c03f7bcb..19c87426f6c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -51,67 +51,67 @@ static inline void rcc_reset(void) /* Enable the MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); - while (!(getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY)); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY)); /* Set MSI to 4MHz */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSIRGSEL; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset enable bits for other clocks than MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSEON | RCC_CR_HSIASFS | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_PLLSAI2ON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); - putreg32(0, STM32L4_RCC_PLLSAI1CFG); - putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); - putreg32(0, STM32L4_RCC_PLLSAI2CFG); - putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32L4_RCC_PLLSAI1CFG); + putreg32(0, STM32_RCC_PLLSAI2CFG); + putreg32(RCC_PLLSAI2CFG_PLLN(16), STM32_RCC_PLLSAI1CFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } static inline void apb_reset(void) { - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR1); - putreg32(0xffffffff, STM32L4_RCC_APB1RSTR2); - putreg32(0xffffffff, STM32L4_RCC_APB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB1RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB2RSTR); - putreg32(0xffffffff, STM32L4_RCC_AHB3RSTR); + putreg32(0xffffffff, STM32_RCC_APB1RSTR1); + putreg32(0xffffffff, STM32_RCC_APB1RSTR2); + putreg32(0xffffffff, STM32_RCC_APB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB1RSTR); + putreg32(0xffffffff, STM32_RCC_AHB2RSTR); + putreg32(0xffffffff, STM32_RCC_AHB3RSTR); - putreg32(0, STM32L4_RCC_APB1RSTR1); - putreg32(0, STM32L4_RCC_APB1RSTR2); - putreg32(0, STM32L4_RCC_APB2RSTR); - putreg32(0, STM32L4_RCC_AHB1RSTR); - putreg32(0, STM32L4_RCC_AHB2RSTR); - putreg32(0, STM32L4_RCC_AHB3RSTR); + putreg32(0, STM32_RCC_APB1RSTR1); + putreg32(0, STM32_RCC_APB1RSTR2); + putreg32(0, STM32_RCC_APB2RSTR); + putreg32(0, STM32_RCC_AHB1RSTR); + putreg32(0, STM32_RCC_AHB2RSTR); + putreg32(0, STM32_RCC_AHB3RSTR); } #endif @@ -144,10 +144,10 @@ void stm32l4_dfumode(void) /* remap ROM at address zero */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); regval |= RCC_APB2ENR_SYSCFGEN; - putreg32(regval, STM32L4_RCC_APB2ENR); - putreg32(SYSCFG_MEMRMP_SYSTEM, STM32L4_SYSCFG_MEMRMP); + putreg32(regval, STM32_RCC_APB2ENR); + putreg32(SYSCFG_MEMRMP_SYSTEM, STM32_SYSCFG_MEMRMP); /* set stack pointer and program-counter to ROM values */ diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index a9f32ad8a82..48d4cace763 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L4_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L4_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L4_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L4_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L4_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L4_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L4_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L4_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L4_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L4_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L4_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L4_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L4_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l4_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L4_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L4_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_MODER_OFFSET), - getreg32(base + STM32L4_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L4_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L4_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04x\n", - getreg32(base + STM32L4_GPIO_IDR_OFFSET), - getreg32(base + STM32L4_GPIO_ODR_OFFSET), - getreg32(base + STM32L4_GPIO_BSRR_OFFSET), - getreg32(base + STM32L4_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L4_GPIO_AFRH_OFFSET), - getreg32(base + STM32L4_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L4_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index c67451e4437..2ad3d44cde5 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -73,7 +73,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32L4_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_ALARM, risingedge ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_ALARM, fallingedge ? EXTI1_RTC_ALARM : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_ALARM, event ? EXTI1_RTC_ALARM : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_ALARM, func ? EXTI1_RTC_ALARM : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index b3b39ce340f..35fd4128668 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -64,11 +64,11 @@ struct comp_callback_s /* Interrupt handlers attached to the COMP EXTI lines */ -static struct comp_callback_s g_comp_handlers[STM32L4_COMP_NUM]; +static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM]; /* Comparator EXTI lines */ -static const uint32_t g_comp_lines[STM32L4_COMP_NUM] = +static const uint32_t g_comp_lines[STM32_COMP_NUM] = { #if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) @@ -92,15 +92,15 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) /* Examine the state of each comparator line and dispatch interrupts */ - pr = getreg32(STM32L4_EXTI1_PR); - for (i = 0; i < STM32L4_COMP_NUM; i++) + pr = getreg32(STM32_EXTI1_PR); + for (i = 0; i < STM32_COMP_NUM; i++) { ln = g_comp_lines[i]; if ((pr & ln) != 0) { /* Clear the pending interrupt */ - putreg32(ln, STM32L4_EXTI1_PR); + putreg32(ln, STM32_EXTI1_PR); if (g_comp_handlers[i].callback != NULL) { xcpt_t callback = g_comp_handlers[i].callback; @@ -152,25 +152,25 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32L4_IRQ_COMP, stm32l4_exti_comp_isr, NULL); - up_enable_irq(STM32L4_IRQ_COMP); + irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL); + up_enable_irq(STM32_IRQ_COMP); } else { - up_disable_irq(STM32L4_IRQ_COMP); + up_disable_irq(STM32_IRQ_COMP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, risingedge ? + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : ln, risingedge ? ln : 0); - modifyreg32(STM32L4_EXTI1_FTSR, fallingedge ? + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : ln, fallingedge ? ln : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); - modifyreg32(STM32L4_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); + modifyreg32(STM32_EXTI1_EMR, event ? 0 : ln, event ? ln : 0); + modifyreg32(STM32_EXTI1_IMR, func ? 0 : ln, func ? ln : 0); /* Get the previous IRQ handler and save the new IRQ handler. */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 2b02e9d15aa..767bffb83ca 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32L4_EXTI1_PR); + putreg32(0x0001, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32L4_EXTI1_PR); + putreg32(0x0002, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32L4_EXTI1_PR); + putreg32(0x0004, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32L4_EXTI1_PR); + putreg32(0x0008, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32L4_EXTI1_PR); + putreg32(0x0010, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32L4_EXTI1_PR); + pr = getreg32(STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32L4_EXTI1_PR); + putreg32(mask, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -257,7 +257,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { struct gpio_callback_s *shared_cbs; uint32_t pin = pinset & GPIO_PIN_MASK; - uint32_t exti = STM32L4_EXTI1_BIT(pin); + uint32_t exti = STM32_EXTI1_BIT(pin); int irq; xcpt_t handler; int nshared; @@ -267,7 +267,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32L4_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32L4_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32l4_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32L4_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32l4_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index b18efc39ef7..854df35b913 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -71,7 +71,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_PVD_LINE, STM32L4_EXTI1_PR); + putreg32(EXTI1_PVD_LINE, STM32_EXTI1_PR); /* And dispatch the interrupt to the handler */ @@ -116,29 +116,29 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); - up_enable_irq(STM32L4_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32L4_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_PVD_LINE, risingedge ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_PVD_LINE, fallingedge ? EXTI1_PVD_LINE : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_PVD_LINE, event ? EXTI1_PVD_LINE : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_PVD_LINE, func ? EXTI1_PVD_LINE : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 24f4e00b305..2bcf7b22ef3 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -73,7 +73,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI1_RTC_WAKEUP, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_WAKEUP, STM32_EXTI1_PR); return ret; } @@ -109,29 +109,29 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32L4_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); - up_enable_irq(STM32L4_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32L4_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32L4_EXTI1_RTSR, + modifyreg32(STM32_EXTI1_RTSR, risingedge ? 0 : EXTI1_RTC_WAKEUP, risingedge ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_FTSR, + modifyreg32(STM32_EXTI1_FTSR, fallingedge ? 0 : EXTI1_RTC_WAKEUP, fallingedge ? EXTI1_RTC_WAKEUP : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L4_EXTI1_EMR, + modifyreg32(STM32_EXTI1_EMR, event ? 0 : EXTI1_RTC_WAKEUP, event ? EXTI1_RTC_WAKEUP : 0); - modifyreg32(STM32L4_EXTI1_IMR, + modifyreg32(STM32_EXTI1_IMR, func ? 0 : EXTI1_RTC_WAKEUP, func ? EXTI1_RTC_WAKEUP : 0); diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index 56b92cf9b08..c4597da0e98 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -67,34 +67,34 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) * data must be in SRAM1 */ - if ((setup->codestart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->codestart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } - if ((setup->nvdatastart & STM32L4_FLASH_MASK) != STM32L4_FLASH_BASE) + if ((setup->nvdatastart & STM32_FLASH_MASK) != STM32_FLASH_BASE) { return -EINVAL; } /* Define address and length registers */ - modifyreg32(STM32L4_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, + modifyreg32(STM32_FIREWALL_CSSA, FIREWALL_CSSADD_MASK, setup->codestart); - modifyreg32(STM32L4_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, + modifyreg32(STM32_FIREWALL_CSL, FIREWALL_CSSLENG_MASK, setup->codelen); - modifyreg32(STM32L4_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, + modifyreg32(STM32_FIREWALL_NVDSSA, FIREWALL_NVDSADD_MASK, setup->nvdatastart); - modifyreg32(STM32L4_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, + modifyreg32(STM32_FIREWALL_NVDSL, FIREWALL_NVDSLENG_MASK, setup->nvdatalen); - modifyreg32(STM32L4_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, + modifyreg32(STM32_FIREWALL_VDSSA, FIREWALL_VDSADD_MASK, setup->datastart); - modifyreg32(STM32L4_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, + modifyreg32(STM32_FIREWALL_VDSL, FIREWALL_VDSLENG_MASK, setup->datalen); /* Define access options */ - reg = getreg32(STM32L4_FIREWALL_CR); + reg = getreg32(STM32_FIREWALL_CR); if (setup->datashared) { reg |= FIREWALL_CR_VDS; @@ -105,13 +105,13 @@ int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) reg |= FIREWALL_CR_VDE; } - putreg32(reg, STM32L4_FIREWALL_CR); + putreg32(reg, STM32_FIREWALL_CR); /* Enable firewall */ - reg = getreg32(STM32L4_SYSCFG_CFGR1); + reg = getreg32(STM32_SYSCFG_CFGR1); reg &= ~SYSCFG_CFGR1_FWDIS; - putreg32(reg, STM32L4_SYSCFG_CFGR1); + putreg32(reg, STM32_SYSCFG_CFGR1); /* Now protected code can only be accessed by jumping to the FW gate */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index dc6983cd00f..914e213005a 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -70,7 +70,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L4_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -78,7 +78,7 @@ #elif FLASH_PAGE_SIZE == 4096 # define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ #else -# error Unsupported STM32L4_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -104,35 +104,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L4_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32L4_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L4_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L4_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L4_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -149,8 +149,8 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); #if defined(CONFIG_STM32L4_STM32L4X5) || \ @@ -160,41 +160,41 @@ static inline void flash_erase(size_t page) { /* Select bank 1 */ - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_BKER, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_BKER, 0); } else { /* Select bank 2 */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_BKER); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_BKER); } #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) static void data_cache_disable(void) { - modifyreg32(STM32L4_FLASH_ACR, FLASH_ACR_DCEN, 0); + modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); } static void data_cache_enable(void) { /* Reset data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCRST); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST); /* Enable data cache */ - modifyreg32(STM32L4_FLASH_ACR, 0, FLASH_ACR_DCEN); + modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); } #endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ @@ -274,20 +274,20 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L4_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L4_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } @@ -300,42 +300,42 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L4_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L4_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L4_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L4_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L4_FLASH_PAGESIZE + STM32L4_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L4_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -347,7 +347,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32L4_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -385,7 +385,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L4_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -419,12 +419,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L4_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L4_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L4_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -498,7 +498,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) data_cache_disable(); #endif - modifyreg32(STM32L4_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -506,14 +506,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L4_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32l4_waste(); } /* Verify */ - if (getreg32(STM32L4_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -527,7 +527,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) @@ -547,7 +547,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32L4_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); #if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif @@ -560,9 +560,9 @@ out: if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32L4_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32L4_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 433a55288f2..37f2a2b8c9f 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -69,7 +69,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); return OK; } @@ -117,7 +117,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, return -EBUSY; } - STM32L4_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. @@ -128,17 +128,17 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32L4_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); /* Set timer period */ - STM32L4_TIM_SETPERIOD(freerun->tch, UINT32_MAX); + STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); /* Start the counter */ - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_UP); - STM32L4_TIM_ACKINT(freerun->tch, 0); - STM32L4_TIM_ENABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + STM32_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ENABLEINT(freerun->tch, 0); return OK; } @@ -184,9 +184,9 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32L4_TIM_GETCOUNTER(freerun->tch); - pending = STM32L4_TIM_CHECKINT(freerun->tch, 0); - verify = STM32L4_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -194,7 +194,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, if (pending) { - STM32L4_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ACKINT(freerun->tch, 0); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -260,9 +260,9 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32L4_TIM_DISABLEINT(freerun->tch, 0); - STM32L4_TIM_SETMODE(freerun->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 1cf19f3dac6..228dec79877 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -54,34 +54,34 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L4_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L4_NPORTS > 0 - STM32L4_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L4_NPORTS > 1 - STM32L4_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L4_NPORTS > 2 - STM32L4_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L4_NPORTS > 3 - STM32L4_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L4_NPORTS > 4 - STM32L4_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L4_NPORTS > 5 - STM32L4_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L4_NPORTS > 6 - STM32L4_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L4_NPORTS > 7 - STM32L4_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif -#if STM32L4_NPORTS > 8 - STM32L4_GPIOI_BASE, +#if STM32_NPORTS > 8 + STM32_GPIOI_BASE, #endif }; @@ -144,7 +144,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L4_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -202,10 +202,10 @@ int stm32l4_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L4_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -228,10 +228,10 @@ int stm32l4_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L4_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -246,12 +246,12 @@ int stm32l4_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L4_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L4_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -289,14 +289,14 @@ int stm32l4_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L4_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L4_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L4_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -309,7 +309,7 @@ int stm32l4_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L4_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -331,7 +331,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32L4_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -351,11 +351,11 @@ int stm32l4_configgpio(uint32_t cfgset) if (pinmode == GPIO_MODER_ANALOG) { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, 0, GPIO_ASCR(pin)); } else { - modifyreg32(base + STM32L4_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); + modifyreg32(base + STM32_GPIO_ASCR_OFFSET, GPIO_ASCR(pin), 0); } #endif @@ -412,7 +412,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -433,7 +433,7 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L4_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -452,7 +452,7 @@ bool stm32l4_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L4_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -461,7 +461,7 @@ bool stm32l4_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L4_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 2df58191ee1..4969756362b 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -244,7 +244,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L4_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index 75ab0311ff4..e34c588f6a1 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -80,13 +80,13 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * enabled. */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32L4_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -100,7 +100,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -119,7 +119,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) break; } - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -127,9 +127,9 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -152,17 +152,17 @@ void stm32l4_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32L4_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32L4_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32L4_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; - putreg32(regval, STM32L4_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32L4_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32L4_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 15dfac9e14e..4e42d3beb51 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -520,14 +520,14 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_STM32L4_I2C1 static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = { - .base = STM32L4_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C1EV, - .er_irq = STM32L4_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -556,14 +556,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = #ifdef CONFIG_STM32L4_I2C2 static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = { - .base = STM32L4_I2C2_BASE, + .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, .reset_bit = RCC_APB1RSTR1_I2C2RST, .scl_pin = GPIO_I2C2_SCL, .sda_pin = GPIO_I2C2_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C2EV, - .er_irq = STM32L4_IRQ_I2C2ER + .ev_irq = STM32_IRQ_I2C2EV, + .er_irq = STM32_IRQ_I2C2ER #endif }; @@ -592,14 +592,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = #ifdef CONFIG_STM32L4_I2C3 static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = { - .base = STM32L4_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C3EV, - .er_irq = STM32L4_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -628,14 +628,14 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = #ifdef CONFIG_STM32L4_I2C4 static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = { - .base = STM32L4_I2C4_BASE, + .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, .reset_bit = RCC_APB1RSTR2_I2C4RST, .scl_pin = GPIO_I2C4_SCL, .sda_pin = GPIO_I2C4_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32L4_IRQ_I2C4EV, - .er_irq = STM32L4_IRQ_I2C4ER + .ev_irq = STM32_IRQ_I2C4EV, + .er_irq = STM32_IRQ_I2C4ER #endif }; @@ -791,7 +791,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -823,7 +823,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -861,7 +861,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -930,7 +930,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } @@ -945,7 +945,7 @@ static inline void stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -959,7 +959,7 @@ stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, static inline void stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -972,7 +972,7 @@ stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -986,7 +986,7 @@ stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -1000,7 +1000,7 @@ stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1253,20 +1253,20 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, /* I2C peripheral must be disabled to update clocking configuration */ pe = (stm32l4_i2c_getreg32(priv, - STM32L4_I2C_CR1_OFFSET) & I2C_CR1_PE); + STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32L4_I2C_USE_HSI16) || (STM32L4_PCLK1_FREQUENCY == 16000000) +#if defined(STM32_I2C_USE_HSI16) || (STM32_PCLK1_FREQUENCY == 16000000) i2cclk_mhz = 16; -#elif STM32L4_PCLK1_FREQUENCY == 48000000 +#elif STM32_PCLK1_FREQUENCY == 48000000 i2cclk_mhz = 48; -#elif STM32L4_PCLK1_FREQUENCY == 80000000 +#elif STM32_PCLK1_FREQUENCY == 80000000 i2cclk_mhz = 80; -#elif STM32L4_PCLK1_FREQUENCY == 120000000 +#elif STM32_PCLK1_FREQUENCY == 120000000 i2cclk_mhz = 120; #else # warning STM32_I2C_INIT: Peripheral clock is PCLK and the speed/timing calculations need to be redone. @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32L4_I2C_TIMINGR_OFFSET, timingr); + stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1605,7 +1605,7 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1626,7 +1626,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR2_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1641,7 +1641,7 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) static inline uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32L4_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1655,7 +1655,7 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) static inline void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1684,7 +1684,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1853,7 +1853,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32L4_I2C_TXDR_OFFSET, *priv->ptr); + stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32L4_I2C_RXDR_OFFSET); + *priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1949,7 +1949,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Unsupported state */ stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2193,7 +2193,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -2216,7 +2216,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_ICR_OFFSET, + stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,7 +2281,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32L4_I2C_ISR_OFFSET); + status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -2320,18 +2320,18 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable power and reset the peripheral */ #ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR2, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR2, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR2, priv->config->reset_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32L4_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); } /* Configure pins */ @@ -2368,7 +2368,7 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32L4_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2385,7 +2385,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32L4_I2C_CR1_OFFSET, 0); + stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2405,14 +2405,14 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) /* Disable clocking */ #ifdef CONFIG_STM32L4_I2C4 - if (priv->config->base == STM32L4_I2C4_BASE) + if (priv->config->base == STM32_I2C4_BASE) { - modifyreg32(STM32L4_RCC_APB1ENR2, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); } else #endif { - modifyreg32(STM32L4_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); } return OK; @@ -2493,8 +2493,8 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, waitrc = stm32l4_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32L4_I2C_CR2_OFFSET); + cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 3cbb653dd08..77c20d24e4a 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -204,13 +204,13 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L4_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -220,19 +220,19 @@ static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L4_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L4_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L4_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L4_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -262,7 +262,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -316,13 +316,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L4_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L4_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L4_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -332,23 +332,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L4_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L4_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L4_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L4_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L4_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L4_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L4_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L4_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL); #endif stm32l4_dumpnvic("initial", NR_IRQS); @@ -384,7 +384,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -419,7 +419,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L4_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -462,10 +462,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L4_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L4_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -478,7 +478,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L4_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 2c0894c78be..05f19076f09 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -65,7 +65,7 @@ * 1000 * 4095 / Fmin = 34,944 MSec */ -#define IWDG_FMIN (STM32L4_LSI_FREQUENCY / 256) +#define IWDG_FMIN (STM32_LSI_FREQUENCY / 256) #define IWDG_MAXTIMEOUT (1000 * IWDG_RLR_MAX / IWDG_FMIN) /* Configuration ************************************************************/ @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32L4_IWDG_PR); + stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32L4_IWDG_RLR); + stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,7 +289,7 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32L4_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32L4_IWDG_KR); + stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -629,7 +629,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32l4_rcc_enablelsi(); - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32L4_RCC_CSR)); + wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 56a8fc03911..440c185a92c 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_LPUART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR2 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L4_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART1_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK2_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB2ENR -# define STM32L4_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART1_TX -# define STM32L4_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART2_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART2_TX -# define STM32L4_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_USART3_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L4_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L4_CONSOLE_TX GPIO_USART3_TX -# define STM32L4_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART4_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART4_TX -# define STM32L4_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L4_CONSOLE_BASE STM32L4_UART5_BASE -# define STM32L4_APBCLOCK STM32L4_PCLK1_FREQUENCY -# define STM32L4_CONSOLE_APBREG STM32L4_RCC_APB1ENR1 -# define STM32L4_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L4_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L4_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L4_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L4_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L4_CONSOLE_TX GPIO_UART5_TX -# define STM32L4_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L4_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L4_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L4_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L4_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L4_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L4_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L4_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L4_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -234,19 +234,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L4_USARTDIV8 \ - (((STM32L4_APBCLOCK << 1) + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) -# define STM32L4_USARTDIV16 \ - ((STM32L4_APBCLOCK + (STM32L4_CONSOLE_BAUD >> 1)) / STM32L4_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L4_USARTDIV8 > 100 -# define STM32L4_BRR_VALUE STM32L4_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L4_BRR_VALUE \ - ((STM32L4_USARTDIV8 & 0xfff0) | ((STM32L4_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -288,22 +288,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L4_CONSOLE_BASE + STM32L4_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L4_CONSOLE_RS485_DIR - while ((getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -329,7 +329,7 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L4_CONSOLE_APBREG, 0, STM32L4_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -338,17 +338,17 @@ void stm32l4_lowsetup(void) * stm32l4_rcc.c */ -#ifdef STM32L4_CONSOLE_TX - stm32l4_configgpio(STM32L4_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l4_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L4_CONSOLE_RX - stm32l4_configgpio(STM32L4_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l4_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L4_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32L4_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32L4_CONSOLE_RS485_DIR, - !STM32L4_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l4_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -356,42 +356,42 @@ void stm32l4_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L4_BRR_VALUE, - STM32L4_CONSOLE_BASE + STM32L4_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L4_CONSOLE_BASE + STM32L4_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 0426016bd44..f376a1fd169 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -154,9 +154,9 @@ static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM1_BASE, - .freq = STM32L4_LPTIM1_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM1_BASE, + .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -164,9 +164,9 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = { .ops = &stm32l4_lptim_ops, - .mode = STM32L4_LPTIM_MODE_UNUSED, - .base = STM32L4_LPTIM2_BASE, - .freq = STM32L4_LPTIM2_FREQUENCY, /* Must be defined in board.h */ + .mode = STM32_LPTIM_MODE_UNUSED, + .base = STM32_LPTIM2_BASE, + .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ }; #endif @@ -218,13 +218,13 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); break; #endif @@ -246,13 +246,13 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); break; #endif @@ -274,15 +274,15 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); - modifyreg32(STM32L4_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); + case STM32_LPTIM1_BASE: + modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); + modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); break; #endif #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: - modifyreg32(STM32L4_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); - modifyreg32(STM32L4_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); + case STM32_LPTIM2_BASE: + modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); + modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); break; #endif } @@ -300,12 +300,12 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL && cfg != NULL); - channel &= STM32L4_LPTIM_CH_MASK; + channel &= STM32_LPTIM_CH_MASK; switch (((struct stm32l4_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: switch (channel) { # if defined(GPIO_LPTIM1_OUT_1) @@ -330,7 +330,7 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, #endif /* CONFIG_STM32L4_LPTIM1 */ #if defined(CONFIG_STM32L4_LPTIM2) - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: switch (channel) { # if defined(GPIO_LPTIM2_OUT_1) @@ -369,24 +369,24 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, stm32l4_lptim_mode_t mode) { const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + - STM32L4_LPTIM_CR_OFFSET; + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); /* Mode */ - switch (mode & STM32L4_LPTIM_MODE_MASK) + switch (mode & STM32_LPTIM_MODE_MASK) { - case STM32L4_LPTIM_MODE_DISABLED: + case STM32_LPTIM_MODE_DISABLED: modifyreg32(addr, LPTIM_CR_ENABLE, 0); break; - case STM32L4_LPTIM_MODE_SINGLE: + case STM32_LPTIM_MODE_SINGLE: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_SNGSTRT); break; - case STM32L4_LPTIM_MODE_CONTINUOUS: + case STM32_LPTIM_MODE_CONTINUOUS: modifyreg32(addr, 0, LPTIM_CR_ENABLE); modifyreg32(addr, 0, LPTIM_CR_CNTSTRT); break; @@ -469,7 +469,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); stm32l4_lptim_enable(dev); @@ -519,9 +519,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, DEBUGASSERT(dev != NULL); - if (clksrc == STM32L4_LPTIM_CLK_EXT) + if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -532,12 +532,12 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; break; #endif @@ -547,61 +547,61 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, switch (clksrc) { - case STM32L4_LPTIM_CLK_PCLK: + case STM32_LPTIM_CLK_PCLK: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; break; #endif } break; - case STM32L4_LPTIM_CLK_HSI: + case STM32_LPTIM_CLK_HSI: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSI: + case STM32_LPTIM_CLK_LSI: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; break; #endif } break; - case STM32L4_LPTIM_CLK_LSE: + case STM32_LPTIM_CLK_LSE: switch (priv->base) { #ifdef CONFIG_STM32L4_LPTIM1 - case STM32L4_LPTIM1_BASE: + case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; break; #endif #ifdef CONFIG_STM32L4_LPTIM2 - case STM32L4_LPTIM2_BASE: + case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; break; #endif @@ -611,9 +611,9 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, break; } - modifyreg32(STM32L4_RCC_CCIPR, ccr_mask, ccr_bits); + modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -632,7 +632,7 @@ static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - putreg32(period, (uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -645,7 +645,7 @@ static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) (struct stm32l4_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); - return getreg32((uintptr_t)(priv->base + STM32L4_LPTIM_ARR_OFFSET)); + return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** @@ -657,14 +657,14 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, { DEBUGASSERT(dev != NULL); - if (cntmode == STM32L4_LPTIM_COUNT_CLOCK) + if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } - else if (cntmode == STM32L4_LPTIM_COUNT_EXTTRIG) + else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -686,20 +686,20 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, switch (polarity) { - case STM32L4_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_RISING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; - case STM32L4_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_FALLING: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; - case STM32L4_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32L4_LPTIM_CFGR_OFFSET, + case STM32_LPTIM_CLKPOL_BOTH: + stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -725,9 +725,9 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) do { counter1 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); counter2 = getreg32((uintptr_t)(priv->base + - STM32L4_LPTIM_CNT_OFFSET)); + STM32_LPTIM_CNT_OFFSET)); } while (counter1 != counter2); @@ -757,7 +757,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ if (((struct stm32l4_lptim_priv_s *)dev)->mode != - STM32L4_LPTIM_MODE_UNUSED) + STM32_LPTIM_MODE_UNUSED) { return NULL; } @@ -772,7 +772,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_DISABLED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } @@ -791,7 +791,7 @@ int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32L4_LPTIM_MODE_UNUSED; + ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index 1f57f6ac9ed..db940b524c3 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -86,14 +86,14 @@ /* Helpers ******************************************************************/ -#define STM32L4_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) -#define STM32L4_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) -#define STM32L4_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) -#define STM32L4_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_LPTIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_LPTIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_LPTIM_SETCHANNEL(d,ch,en) ((d)->ops->setchannel(d,ch,en)) +#define STM32_LPTIM_SETCLOCKSOURCE(d,s) ((d)->ops->setclocksource(d,s)) +#define STM32_LPTIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_LPTIM_SETCOUNTMODE(d,m) ((d)->ops->setcountmode(d,m)) +#define STM32_LPTIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_LPTIM_GETPERIOD(d) ((d)->ops->getperiod(d)) /**************************************************************************** * Public Types @@ -121,14 +121,14 @@ struct stm32l4_lptim_dev_s typedef enum { - STM32L4_LPTIM_MODE_UNUSED = -1, + STM32_LPTIM_MODE_UNUSED = -1, /* MODES */ - STM32L4_LPTIM_MODE_DISABLED = 0x0000, - STM32L4_LPTIM_MODE_SINGLE = 0x0001, - STM32L4_LPTIM_MODE_CONTINUOUS = 0x0002, - STM32L4_LPTIM_MODE_MASK = 0x000f, + STM32_LPTIM_MODE_DISABLED = 0x0000, + STM32_LPTIM_MODE_SINGLE = 0x0001, + STM32_LPTIM_MODE_CONTINUOUS = 0x0002, + STM32_LPTIM_MODE_MASK = 0x000f, } stm32l4_lptim_mode_t; /* LPTIM Clock Source */ @@ -137,11 +137,11 @@ typedef enum { /* Clock Sources */ - STM32L4_LPTIM_CLK_PCLK = 0x0000, - STM32L4_LPTIM_CLK_LSI = 0x0001, - STM32L4_LPTIM_CLK_HSI = 0x0002, - STM32L4_LPTIM_CLK_LSE = 0x0003, - STM32L4_LPTIM_CLK_EXT = 0x0004, + STM32_LPTIM_CLK_PCLK = 0x0000, + STM32_LPTIM_CLK_LSI = 0x0001, + STM32_LPTIM_CLK_HSI = 0x0002, + STM32_LPTIM_CLK_LSE = 0x0003, + STM32_LPTIM_CLK_EXT = 0x0004, } stm32l4_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -150,8 +150,8 @@ typedef enum { /* Modes */ - STM32L4_LPTIM_COUNT_CLOCK = 0x0000, - STM32L4_LPTIM_COUNT_EXTTRIG = 0x0001, + STM32_LPTIM_COUNT_CLOCK = 0x0000, + STM32_LPTIM_COUNT_EXTTRIG = 0x0001, } stm32l4_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -160,24 +160,24 @@ typedef enum { /* MODES */ - STM32L4_LPTIM_CLKPOL_RISING = 0x0000, - STM32L4_LPTIM_CLKPOL_FALLING = 0x0001, - STM32L4_LPTIM_CLKPOL_BOTH = 0x0002, + STM32_LPTIM_CLKPOL_RISING = 0x0000, + STM32_LPTIM_CLKPOL_FALLING = 0x0001, + STM32_LPTIM_CLKPOL_BOTH = 0x0002, } stm32l4_lptim_clkpol_t; /* LPTIM Channel Modes */ typedef enum { - STM32L4_LPTIM_CH_DISABLED = 0x0000, + STM32_LPTIM_CH_DISABLED = 0x0000, /* CHANNELS */ - STM32L4_LPTIM_CH_CHINVALID = 0x0000, - STM32L4_LPTIM_CH_CH1 = 0x0001, - STM32L4_LPTIM_CH_CH2 = 0x0002, - STM32L4_LPTIM_CH_CH3 = 0x0003, - STM32L4_LPTIM_CH_MASK = 0x000f, + STM32_LPTIM_CH_CHINVALID = 0x0000, + STM32_LPTIM_CH_CH1 = 0x0001, + STM32_LPTIM_CH_CH2 = 0x0002, + STM32_LPTIM_CH_CH3 = 0x0003, + STM32_LPTIM_CH_MASK = 0x000f, } stm32l4_lptim_channel_t; /* LPTIM Operations */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 19914bc5b05..6859cfec064 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -68,7 +68,7 @@ void stm32l4_rcc_enablelse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32L4_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -94,11 +94,11 @@ void stm32l4_rcc_enablelse(void) RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32L4_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32l4_waste(); } @@ -116,7 +116,7 @@ void stm32l4_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L4_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index fb26a31ba16..2897d3646ba 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -46,11 +46,11 @@ void stm32l4_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L4_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l4_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L4_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 0b70b905db8..68ff5860cf2 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -86,10 +86,10 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, 0); /* The timer is no longer running */ @@ -200,7 +200,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, return -EBUSY; } - STM32L4_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -302,19 +302,19 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32L4_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32L4_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32L4_TIM_ACKINT(oneshot->tch, 0); - STM32L4_TIM_ENABLEINT(oneshot->tch, 0); + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_ENABLEINT(oneshot->tch, 0); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -389,14 +389,14 @@ int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32L4_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32L4_TIM_DISABLEINT(oneshot->tch, 0); - STM32L4_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32L4_TIM_SETMODE(oneshot->tch, STM32L4_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index bce7dcc0742..00fb8ba0b30 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -49,7 +49,7 @@ /* Number of endpoints */ -#define STM32L4_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +#define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ /**************************************************************************** * Public Functions Prototypes diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index cfaf97f4473..ef8f20ba9da 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -115,8 +115,8 @@ */ #if CONFIG_USBDEV_EP1_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 1 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 1 # undef CONFIG_USBDEV_EP2_TXFIFO_SIZE # define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE @@ -126,8 +126,8 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP2_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 2 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 2 # undef CONFIG_USBDEV_EP3_TXFIFO_SIZE # define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE @@ -135,20 +135,20 @@ # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP3_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 3 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 3 # undef CONFIG_USBDEV_EP4_TXFIFO_SIZE # define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP4_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 4 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 4 # undef CONFIG_USBDEV_EP5_TXFIFO_SIZE # define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 #elif CONFIG_USBDEV_EP5_TXFIFO_SIZE == 0 -# undef STM32L4_NENDPOINTS -# define STM32L4_NENDPOINTS 5 +# undef STM32_NENDPOINTS +# define STM32_NENDPOINTS 5 #endif /* Sanity check on allocations specified. */ @@ -168,48 +168,48 @@ * boundaries; FIFO sizes must be provided in units of 32-bit words. */ -#define STM32L4_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) -#define STM32L4_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) -#define STM32L4_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP0_TXFIFO_WORDS < 16 || STM32L4_EP0_TXFIFO_WORDS > 256 +#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256 # error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP1_TXFIFO_BYTES != 0 && STM32L4_EP1_TXFIFO_WORDS < 16 +#if STM32_EP1_TXFIFO_BYTES != 0 && STM32_EP1_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP2_TXFIFO_BYTES != 0 && STM32L4_EP2_TXFIFO_WORDS < 16 +#if STM32_EP2_TXFIFO_BYTES != 0 && STM32_EP2_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP3_TXFIFO_BYTES != 0 && STM32L4_EP3_TXFIFO_WORDS < 16 +#if STM32_EP3_TXFIFO_BYTES != 0 && STM32_EP3_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP4_TXFIFO_BYTES != 0 && STM32L4_EP4_TXFIFO_WORDS < 16 +#if STM32_EP4_TXFIFO_BYTES != 0 && STM32_EP4_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP4_TXFIFO_SIZE is out of range" #endif -#define STM32L4_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) -#define STM32L4_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) -#if STM32L4_EP5_TXFIFO_BYTES != 0 && STM32L4_EP5_TXFIFO_WORDS < 16 +#if STM32_EP5_TXFIFO_BYTES != 0 && STM32_EP5_TXFIFO_WORDS < 16 # error "CONFIG_USBDEV_EP5_TXFIFO_SIZE is out of range" #endif @@ -238,95 +238,95 @@ /* Trace error codes */ -#define STM32L4_TRACEERR_ALLOCFAIL 0x01 -#define STM32L4_TRACEERR_BADCLEARFEATURE 0x02 -#define STM32L4_TRACEERR_BADDEVGETSTATUS 0x03 -#define STM32L4_TRACEERR_BADEPNO 0x04 -#define STM32L4_TRACEERR_BADEPGETSTATUS 0x05 -#define STM32L4_TRACEERR_BADGETCONFIG 0x06 -#define STM32L4_TRACEERR_BADGETSETDESC 0x07 -#define STM32L4_TRACEERR_BADGETSTATUS 0x08 -#define STM32L4_TRACEERR_BADSETADDRESS 0x09 -#define STM32L4_TRACEERR_BADSETCONFIG 0x0a -#define STM32L4_TRACEERR_BADSETFEATURE 0x0b -#define STM32L4_TRACEERR_BADTESTMODE 0x0c -#define STM32L4_TRACEERR_BINDFAILED 0x0d -#define STM32L4_TRACEERR_DISPATCHSTALL 0x0e -#define STM32L4_TRACEERR_DRIVER 0x0f -#define STM32L4_TRACEERR_DRIVERREGISTERED 0x10 -#define STM32L4_TRACEERR_EP0NOSETUP 0x11 -#define STM32L4_TRACEERR_EP0SETUPSTALLED 0x12 -#define STM32L4_TRACEERR_EPINNULLPACKET 0x13 -#define STM32L4_TRACEERR_EPINUNEXPECTED 0x14 -#define STM32L4_TRACEERR_EPOUTNULLPACKET 0x15 -#define STM32L4_TRACEERR_EPOUTUNEXPECTED 0x16 -#define STM32L4_TRACEERR_INVALIDCTRLREQ 0x17 -#define STM32L4_TRACEERR_INVALIDPARMS 0x18 -#define STM32L4_TRACEERR_IRQREGISTRATION 0x19 -#define STM32L4_TRACEERR_NOEP 0x1a -#define STM32L4_TRACEERR_NOTCONFIGURED 0x1b -#define STM32L4_TRACEERR_EPOUTQEMPTY 0x1c -#define STM32L4_TRACEERR_EPINREQEMPTY 0x1d -#define STM32L4_TRACEERR_NOOUTSETUP 0x1e -#define STM32L4_TRACEERR_POLLTIMEOUT 0x1f +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f /* Trace interrupt codes */ -#define STM32L4_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ -#define STM32L4_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ -#define STM32L4_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ -#define STM32L4_TRACEINTID_EPIN (10 + 1) -#define STM32L4_TRACEINTID_MISMATCH (10 + 2) -#define STM32L4_TRACEINTID_WAKEUP (10 + 3) -#define STM32L4_TRACEINTID_SUSPEND (10 + 4) -#define STM32L4_TRACEINTID_SOF (10 + 5) -#define STM32L4_TRACEINTID_RXFIFO (10 + 6) -#define STM32L4_TRACEINTID_DEVRESET (10 + 7) -#define STM32L4_TRACEINTID_ENUMDNE (10 + 8) -#define STM32L4_TRACEINTID_IISOIXFR (10 + 9) -#define STM32L4_TRACEINTID_IISOOXFR (10 + 10) -#define STM32L4_TRACEINTID_SRQ (10 + 11) -#define STM32L4_TRACEINTID_OTG (10 + 12) +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) -#define STM32L4_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ -#define STM32L4_TRACEINTID_EPOUT_EPDISD (40 + 1) -#define STM32L4_TRACEINTID_EPOUT_SETUP (40 + 2) -#define STM32L4_TRACEINTID_DISPATCH (40 + 3) +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) -#define STM32L4_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ -#define STM32L4_TRACEINTID_EPGETSTATUS (50 + 1) -#define STM32L4_TRACEINTID_DEVGETSTATUS (50 + 2) -#define STM32L4_TRACEINTID_IFGETSTATUS (50 + 3) -#define STM32L4_TRACEINTID_CLEARFEATURE (50 + 4) -#define STM32L4_TRACEINTID_SETFEATURE (50 + 5) -#define STM32L4_TRACEINTID_SETADDRESS (50 + 6) -#define STM32L4_TRACEINTID_GETSETDESC (50 + 7) -#define STM32L4_TRACEINTID_GETCONFIG (50 + 8) -#define STM32L4_TRACEINTID_SETCONFIG (50 + 9) -#define STM32L4_TRACEINTID_GETSETIF (50 + 10) -#define STM32L4_TRACEINTID_SYNCHFRAME (50 + 11) +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) -#define STM32L4_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ -#define STM32L4_TRACEINTID_EPIN_TOC (70 + 1) -#define STM32L4_TRACEINTID_EPIN_ITTXFE (70 + 2) -#define STM32L4_TRACEINTID_EPIN_EPDISD (70 + 3) -#define STM32L4_TRACEINTID_EPIN_TXFE (70 + 4) +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) -#define STM32L4_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ -#define STM32L4_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ -#define STM32L4_TRACEINTID_OUTRECVD (90 + 1) -#define STM32L4_TRACEINTID_OUTDONE (90 + 2) -#define STM32L4_TRACEINTID_SETUPDONE (90 + 3) -#define STM32L4_TRACEINTID_SETUPRECVD (90 + 4) +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) /* Endpoints ****************************************************************/ /* Odd physical endpoint numbers are IN; even are OUT */ -#define STM32L4_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) -#define STM32L4_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) /* Endpoint 0 */ @@ -336,16 +336,16 @@ * This is a bitmap, and the first endpoint (0) is reserved. */ -#define STM32L4_EP_AVAILABLE (((1 << STM32L4_NENDPOINTS) - 1) & ~1) +#define STM32_EP_AVAILABLE (((1 << STM32_NENDPOINTS) - 1) & ~1) /* Maximum packet sizes for full speed endpoints */ -#define STM32L4_MAXPACKET (64) /* Max packet size (1-64) */ +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 -#define STM32L4_FLUSH_DELAY 200000 +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 /* Request queue operations *************************************************/ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32L4_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32L4_NENDPOINTS]; + struct stm32l4_ep_s epin[STM32_NENDPOINTS]; + struct stm32l4_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -789,37 +789,37 @@ static const struct usbdev_ops_s g_devops = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_deverror[] = { - TRACE_STR(STM32L4_TRACEERR_ALLOCFAIL), - TRACE_STR(STM32L4_TRACEERR_BADCLEARFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADDEVGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADEPNO), - TRACE_STR(STM32L4_TRACEERR_BADEPGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADGETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADGETSETDESC), - TRACE_STR(STM32L4_TRACEERR_BADGETSTATUS), - TRACE_STR(STM32L4_TRACEERR_BADSETADDRESS), - TRACE_STR(STM32L4_TRACEERR_BADSETCONFIG), - TRACE_STR(STM32L4_TRACEERR_BADSETFEATURE), - TRACE_STR(STM32L4_TRACEERR_BADTESTMODE), - TRACE_STR(STM32L4_TRACEERR_BINDFAILED), - TRACE_STR(STM32L4_TRACEERR_DISPATCHSTALL), - TRACE_STR(STM32L4_TRACEERR_DRIVER), - TRACE_STR(STM32L4_TRACEERR_DRIVERREGISTERED), - TRACE_STR(STM32L4_TRACEERR_EP0NOSETUP), - TRACE_STR(STM32L4_TRACEERR_EP0SETUPSTALLED), - TRACE_STR(STM32L4_TRACEERR_EPINNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPINUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_EPOUTNULLPACKET), - TRACE_STR(STM32L4_TRACEERR_EPOUTUNEXPECTED), - TRACE_STR(STM32L4_TRACEERR_INVALIDCTRLREQ), - TRACE_STR(STM32L4_TRACEERR_INVALIDPARMS), - TRACE_STR(STM32L4_TRACEERR_IRQREGISTRATION), - TRACE_STR(STM32L4_TRACEERR_NOEP), - TRACE_STR(STM32L4_TRACEERR_NOTCONFIGURED), - TRACE_STR(STM32L4_TRACEERR_EPOUTQEMPTY), - TRACE_STR(STM32L4_TRACEERR_EPINREQEMPTY), - TRACE_STR(STM32L4_TRACEERR_NOOUTSETUP), - TRACE_STR(STM32L4_TRACEERR_POLLTIMEOUT), + TRACE_STR(STM32_TRACEERR_ALLOCFAIL), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADEPNO), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE), + TRACE_STR(STM32_TRACEERR_BADTESTMODE), + TRACE_STR(STM32_TRACEERR_BINDFAILED), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL), + TRACE_STR(STM32_TRACEERR_DRIVER), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION), + TRACE_STR(STM32_TRACEERR_NOEP), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT), TRACE_STR_END }; #endif @@ -831,48 +831,48 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = #ifdef CONFIG_USBDEV_TRACE_STRINGS const struct trace_msg_t g_usb_trace_strings_intdecode[] = { - TRACE_STR(STM32L4_TRACEINTID_USB), - TRACE_STR(STM32L4_TRACEINTID_INTPENDING), - TRACE_STR(STM32L4_TRACEINTID_EPOUT), - TRACE_STR(STM32L4_TRACEINTID_EPIN), - TRACE_STR(STM32L4_TRACEINTID_MISMATCH), - TRACE_STR(STM32L4_TRACEINTID_WAKEUP), - TRACE_STR(STM32L4_TRACEINTID_SUSPEND), - TRACE_STR(STM32L4_TRACEINTID_SOF), - TRACE_STR(STM32L4_TRACEINTID_RXFIFO), - TRACE_STR(STM32L4_TRACEINTID_DEVRESET), - TRACE_STR(STM32L4_TRACEINTID_ENUMDNE), - TRACE_STR(STM32L4_TRACEINTID_IISOIXFR), - TRACE_STR(STM32L4_TRACEINTID_IISOOXFR), - TRACE_STR(STM32L4_TRACEINTID_SRQ), - TRACE_STR(STM32L4_TRACEINTID_OTG), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPOUT_SETUP), - TRACE_STR(STM32L4_TRACEINTID_DISPATCH), - TRACE_STR(STM32L4_TRACEINTID_GETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_EPGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_DEVGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_IFGETSTATUS), - TRACE_STR(STM32L4_TRACEINTID_CLEARFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETFEATURE), - TRACE_STR(STM32L4_TRACEINTID_SETADDRESS), - TRACE_STR(STM32L4_TRACEINTID_GETSETDESC), - TRACE_STR(STM32L4_TRACEINTID_GETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_SETCONFIG), - TRACE_STR(STM32L4_TRACEINTID_GETSETIF), - TRACE_STR(STM32L4_TRACEINTID_SYNCHFRAME), - TRACE_STR(STM32L4_TRACEINTID_EPIN_XFRC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TOC), - TRACE_STR(STM32L4_TRACEINTID_EPIN_ITTXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EPDISD), - TRACE_STR(STM32L4_TRACEINTID_EPIN_TXFE), - TRACE_STR(STM32L4_TRACEINTID_EPIN_EMPWAIT), - TRACE_STR(STM32L4_TRACEINTID_OUTNAK), - TRACE_STR(STM32L4_TRACEINTID_OUTRECVD), - TRACE_STR(STM32L4_TRACEINTID_OUTDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPDONE), - TRACE_STR(STM32L4_TRACEINTID_SETUPRECVD), + TRACE_STR(STM32_TRACEINTID_USB), + TRACE_STR(STM32_TRACEINTID_INTPENDING), + TRACE_STR(STM32_TRACEINTID_EPOUT), + TRACE_STR(STM32_TRACEINTID_EPIN), + TRACE_STR(STM32_TRACEINTID_MISMATCH), + TRACE_STR(STM32_TRACEINTID_WAKEUP), + TRACE_STR(STM32_TRACEINTID_SUSPEND), + TRACE_STR(STM32_TRACEINTID_SOF), + TRACE_STR(STM32_TRACEINTID_RXFIFO), + TRACE_STR(STM32_TRACEINTID_DEVRESET), + TRACE_STR(STM32_TRACEINTID_ENUMDNE), + TRACE_STR(STM32_TRACEINTID_IISOIXFR), + TRACE_STR(STM32_TRACEINTID_IISOOXFR), + TRACE_STR(STM32_TRACEINTID_SRQ), + TRACE_STR(STM32_TRACEINTID_OTG), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP), + TRACE_STR(STM32_TRACEINTID_DISPATCH), + TRACE_STR(STM32_TRACEINTID_GETSTATUS), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE), + TRACE_STR(STM32_TRACEINTID_SETADDRESS), + TRACE_STR(STM32_TRACEINTID_GETSETDESC), + TRACE_STR(STM32_TRACEINTID_GETCONFIG), + TRACE_STR(STM32_TRACEINTID_SETCONFIG), + TRACE_STR(STM32_TRACEINTID_GETSETIF), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK), + TRACE_STR(STM32_TRACEINTID_OUTRECVD), + TRACE_STR(STM32_TRACEINTID_OUTDONE), + TRACE_STR(STM32_TRACEINTID_SETUPDONE), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD), TRACE_STR_END }; #endif @@ -1068,7 +1068,7 @@ static void stm32l4_ep0in_activate(void) /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,13 +1083,13 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -1109,13 +1109,13 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPTSIZ(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(0)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(0)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** @@ -1140,7 +1140,7 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Get the TxFIFO for this endpoint (same as the endpoint number) */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(privep->epphy); + regaddr = STM32_OTGFS_DFIFO_DEP(privep->epphy); /* Then transfer each word to the TxFIFO */ @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTSIZ(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32L4_OTGFS_DSTS); + uint32_t status = stm32l4_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,7 +1254,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(privep->epphy)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the @@ -1308,7 +1308,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINREQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); /* There is no TX transfer in progress and no new pending TX * requests to send. To stop transmitting any data on a particular @@ -1316,7 +1316,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * bit, the following field must be programmed. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1419,7 +1419,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * n: n words available */ - regaddr = STM32L4_OTGFS_DTXFSTS(privep->epphy); + regaddr = STM32_OTGFS_DTXFSTS(privep->epphy); /* Check for space in the TxFIFO. If space in the TxFIFO is not * available, then set up an interrupt to resume the transfer when @@ -1429,23 +1429,23 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, regval = stm32l4_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EMPWAIT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); /* There is insufficient space in the TxFIFO. Wait for a TxFIFO * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32L4_OTG_DIEPTXF(privep->epphy)); + regval = stm32l4_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1519,7 +1519,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits and write 4 x 8-bits at time * (to avoid unaligned accesses) @@ -1565,7 +1565,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * we might as well use the address associated with EP0. */ - regaddr = STM32L4_OTGFS_DFIFO_DEP(EP0); + regaddr = STM32_OTGFS_DFIFO_DEP(EP0); /* Read 32-bits at time */ @@ -1607,7 +1607,7 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * should not happen. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), privep->epphy); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); privep->active = false; return; } @@ -1681,7 +1681,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * does not become constipated. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOOUTSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); stm32l4_rxfifo_discard(privep, bcnt); privep->active = false; } @@ -1732,7 +1732,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * NAKing is working as expected. */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* Discard the data in the RxFIFO */ @@ -1814,7 +1814,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, privreq = stm32l4_rqpeek(privep); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTQEMPTY), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); /* There are no read requests to be setup. Configure the @@ -1823,7 +1823,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * NAK after a transfer is completed until SNAK is cleared). */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; stm32l4_putreg(regval, regaddr); @@ -1842,7 +1842,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_req_complete(privep, OK); } @@ -1870,7 +1870,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ - regaddr = STM32L4_OTGFS_DOEPTSIZ(privep->epphy); + regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); @@ -1879,7 +1879,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then enable the transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must @@ -2021,7 +2021,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { return NULL; } @@ -2057,7 +2057,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { int ret = -EIO; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -2070,7 +2070,7 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->stalled = true; } @@ -2093,9 +2093,9 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ @@ -2112,17 +2112,17 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Mark all endpoints as available */ - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Disable all end point interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS ; i++) + for (i = 0; i < STM32_NENDPOINTS ; i++) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ @@ -2143,22 +2143,22 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPMSK); + stm32l4_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ @@ -2212,7 +2212,7 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADTESTMODE), testmode); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); priv->dotest = false; priv->testmode = OTGFS_TESTMODE_DISABLED; priv->stalled = true; @@ -2249,7 +2249,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); if (!priv->addressed || ctrlreq->len != 2 || USB_REQ_ISOUT(ctrlreq->type) || @@ -2264,12 +2264,12 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_ENDPOINT: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_EPGETSTATUS), 0); + STM32_TRACEINTID_EPGETSTATUS), 0); privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), 0); + STM32_TRACEERR_BADEPGETSTATUS), 0); priv->stalled = true; } else @@ -2294,7 +2294,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if (ctrlreq->index == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), 0); + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup and self-powered */ @@ -2309,7 +2309,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), 0); + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->stalled = true; } } @@ -2318,7 +2318,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, case USB_REQ_RECIPIENT_INTERFACE: { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_IFGETSTATUS), 0); + STM32_TRACEINTID_IFGETSTATUS), 0); priv->ep0data[0] = 0; priv->ep0data[1] = 0; @@ -2329,7 +2329,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, default: { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADGETSTATUS), 0); + STM32_TRACEERR_BADGETSTATUS), 0); priv->stalled = true; } break; @@ -2346,7 +2346,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2373,7 +2373,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->stalled = true; } } @@ -2387,7 +2387,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); if (priv->addressed != 0 && ctrlreq->len == 0) { uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; @@ -2419,13 +2419,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->stalled = true; } } @@ -2439,7 +2439,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2457,7 +2457,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->stalled = true; } } @@ -2478,7 +2478,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { @@ -2486,7 +2486,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSETDESC), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); priv->stalled = true; } } @@ -2500,7 +2500,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2512,7 +2512,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->stalled = true; } } @@ -2526,7 +2526,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); if (priv->addressed && (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2559,7 +2559,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->stalled = true; } } @@ -2580,7 +2580,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); stm32l4_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2593,13 +2593,13 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); priv->stalled = true; } break; @@ -2623,7 +2623,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->ep0state != EP0STATE_SETUP_READY) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0NOSETUP), priv->ep0state); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); return; } @@ -2673,7 +2673,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) if (priv->stalled) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); stm32l4_ep0_stall(priv); } @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); + regval &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,10 +2777,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINT); + regval = stm32l4_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTUNEXPECTED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), (uint16_t)regval); epno = 0; @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(epno)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,8 +2811,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32L4_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32L4_OTGFS_DOEPMSK); + doepint = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32l4_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. * This interrupt is triggered when stm32l4_rxinterrupt() removes @@ -2823,13 +2823,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_XFRC, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ @@ -2844,13 +2844,13 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); /* Clear the bit in DOEPINTn for this interrupt */ stm32l4_putreg(OTGFS_DOEPINT_EPDISD, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2858,7 +2858,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if ((doepint & OTGFS_DOEPINT_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT_SETUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); /* Handle the receipt of the IN SETUP packets now (OUT setup @@ -2872,7 +2872,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } stm32l4_putreg(OTGFS_DOEPINT_SETUP, - STM32L4_OTGFS_DOEPINT(epno)); + STM32_OTGFS_DOEPINT(epno)); } } @@ -2892,10 +2892,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) static inline void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + uint32_t regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + daint &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,8 +3022,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32L4_OTGFS_DAINT); - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPINUNEXPECTED), + daint = stm32l4_getreg(STM32_OTGFS_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); daint &= OTGFS_DAINT_IEP_MASK; @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(epno)); + epno, stm32l4_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32L4_OTGFS_DIEPMSK); + mask = stm32l4_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32L4_OTGFS_DIEPEMPMSK); + empty = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32L4_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32l4_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3086,7 +3086,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_XFRC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_XFRC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), (uint16_t)diepint); /* It is possible that logic may be waiting for a the @@ -3096,9 +3096,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); stm32l4_putreg(OTGFS_DIEPINT_XFRC, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ @@ -3109,9 +3109,9 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TOC) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TOC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32L4_OTGFS_DIEPINT(epno)); + stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3123,11 +3123,11 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_ITTXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_ITTXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); stm32l4_epin_request(priv, &priv->epin[epno]); stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } /* IN endpoint NAK effective (ignored as this used only in polled @@ -3136,10 +3136,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_INEPNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_INEPNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_INEPNE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3149,10 +3149,10 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) #if 0 if ((diepint & OTGFS_DIEPINT_EPDISD) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_EPDISD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); stm32l4_putreg(OTGFS_DIEPINT_EPDISD, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3160,7 +3160,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((diepint & OTGFS_DIEPINT_TXFE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN_TXFE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); /* If we were waiting for TxFIFO to become empty, the we might @@ -3176,7 +3176,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32L4_OTGFS_DIEPEMPMSK); + stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ @@ -3186,7 +3186,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the pending TxFIFO empty interrupt */ stm32l4_putreg(OTGFS_DIEPINT_TXFE, - STM32L4_OTGFS_DIEPINT(epno)); + STM32_OTGFS_DIEPINT(epno)); } } @@ -3210,16 +3210,16 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3305,23 +3305,23 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + regval = stm32l4_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ epphy = (regval & OTGFS_GRXSTSD_EPNUM_MASK) >> OTGFS_GRXSTSD_EPNUM_SHIFT; - /* Workaround for bad values read from the STM32L4_OTGFS_GRXSTSP + /* Workaround for bad values read from the STM32_OTGFS_GRXSTSP * register happens regval is 0xb4e48168 or 0xa80c9367 or 267E781c * All of which provide out of range indexes for epout[epphy] */ - if (epphy < STM32L4_NENDPOINTS) + if (epphy < STM32_NENDPOINTS) { privep = &priv->epout[epphy]; @@ -3338,7 +3338,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTNAK: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTNAK), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); } break; @@ -3351,7 +3351,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTRECVD: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); bcnt = (regval & OTGFS_GRXSTSD_BCNT_MASK) >> OTGFS_GRXSTSD_BCNT_SHIFT; @@ -3375,7 +3375,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_OUTDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OUTDONE), epphy); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); } break; @@ -3392,7 +3392,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) case OTGFS_GRXSTSD_PKTSTS_SETUPDONE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPDONE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); /* On the L4 This event does not occur on the next SETUP @@ -3412,7 +3412,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { uint16_t datlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETUPRECVD), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); /* Read EP0 setup data. NOTE: If multiple SETUP packets are @@ -3459,7 +3459,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), (regval & OTGFS_GRXSTSD_PKTSTS_MASK) >> OTGFS_GRXSTSD_PKTSTS_SHIFT); } @@ -3489,10 +3489,10 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) * PHY interface. */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** @@ -3515,7 +3515,7 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * transfers. */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous IN endpoint? */ @@ -3538,9 +3538,9 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3599,7 +3599,7 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * DOEPCTLx:EPENA = 1 */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Is this an isochronous OUT endpoint? */ @@ -3622,9 +3622,9 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32L4_OTGFS_DSTS); + dsts = stm32l4_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3684,7 +3684,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Check for session end detected */ - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGINT); + regval = stm32l4_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,7 +3692,7 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(regval, STM32_OTGFS_GOTGINT); } #endif @@ -3717,11 +3717,11 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) uint32_t regval; uint32_t reserved; - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), priv->ep0state); /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,16 +3733,16 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), - STM32L4_OTGFS_GINTSTS); + STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and * unmasked) interrupts to be processes. @@ -3753,7 +3753,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) break; } - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_INTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); /* OUT endpoint interrupt. The core sets this bit to indicate that an @@ -3762,7 +3762,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUT), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); stm32l4_epout_interrupt(priv); } @@ -3773,7 +3773,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IEP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPIN), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); stm32l4_epin_interrupt(priv); } @@ -3783,7 +3783,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_DEBUG_FEATURES if ((regval & OTGFS_GINT_MMIS) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_MISMATCH), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); } #endif @@ -3792,7 +3792,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_WKUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WAKEUP), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); stm32l4_resumeinterrupt(priv); } @@ -3801,7 +3801,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_USBSUSP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSPEND), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); stm32l4_suspendinterrupt(priv); } @@ -3811,7 +3811,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_SOFINTERRUPT if ((regval & OTGFS_GINT_SOF) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SOF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); } @@ -3823,7 +3823,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_RXFLVL) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RXFIFO), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); stm32l4_rxinterrupt(priv); } @@ -3832,13 +3832,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & (OTGFS_GINT_USBRST | OTGFS_GINT_RSTDET)) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DEVRESET), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); /* Perform the device reset */ stm32l4_usbreset(priv); - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3846,7 +3846,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_ENUMDNE) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ENUMDNE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); stm32l4_enuminterrupt(priv); } @@ -3860,7 +3860,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_ISOCHRONOUS if ((regval & OTGFS_GINT_IISOIXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOIXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); stm32l4_isocininterrupt(priv); } @@ -3877,7 +3877,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_IISOOXFR) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IISOOXFR), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); stm32l4_isocoutinterrupt(priv); } @@ -3888,7 +3888,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) #ifdef CONFIG_USBDEV_VBUSSENSING if ((regval & OTGFS_GINT_SRQ) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SRQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); stm32l4_sessioninterrupt(priv); } @@ -3897,14 +3897,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) if ((regval & OTGFS_GINT_OTG) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_OTG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); stm32l4_otginterrupt(priv); } #endif } - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USB), priv->ep0state); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3927,14 +3927,14 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32L4_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32L4_OTGFS_GINTSTS); + while ((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,7 +3954,7 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32L4_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32l4_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } @@ -3972,9 +3972,9 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** @@ -4042,7 +4042,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { @@ -4066,9 +4066,9 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4138,7 +4138,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * register. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4164,9 +4164,9 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } @@ -4264,7 +4264,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) * int DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); @@ -4275,7 +4275,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,7 +4285,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32L4_OTGFS_DOEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. @@ -4295,9 +4295,9 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ @@ -4326,7 +4326,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * hardware. Trying to disable again will just hang in the wait. */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { @@ -4342,11 +4342,11 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32L4_OTGFS_DIEPINT(privep->epphy)); + stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4356,7 +4356,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * NAK mode */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ @@ -4369,7 +4369,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); @@ -4379,7 +4379,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * endpoint is completely disabled. */ - regaddr = STM32L4_OTGFS_DIEPINT(privep->epphy); + regaddr = STM32_OTGFS_DIEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ @@ -4392,9 +4392,9 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_DAINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ @@ -4417,7 +4417,7 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4457,7 +4457,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -4468,7 +4468,7 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -4492,7 +4492,7 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -4566,7 +4566,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -4579,7 +4579,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); return -ESHUTDOWN; } @@ -4658,7 +4658,7 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -4704,7 +4704,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * in the DOECPTL register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); stm32l4_putreg(regval, regaddr); @@ -4714,7 +4714,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) */ #if 0 /* Doesn't happen */ - regaddr = STM32L4_OTGFS_DOEPINT(privep->epphy); + regaddr = STM32_OTGFS_DOEPINT(privep->epphy); while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4742,7 +4742,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) * register. */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; stm32l4_putreg(regval, regaddr); @@ -4769,7 +4769,7 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) /* Get the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); regval = stm32l4_getreg(regaddr); /* Then stall the endpoint */ @@ -4830,7 +4830,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DIEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); stallbit = OTGFS_DIEPCTL_STALL; data0bit = OTGFS_DIEPCTL_SD0PID; } @@ -4838,7 +4838,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) { /* Clear the stall bit in the IN endpoint device control register */ - regaddr = STM32L4_OTGFS_DOEPCTL(privep->epphy); + regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); stallbit = OTGFS_DOEPCTL_STALL; data0bit = OTGFS_DOEPCTL_SD0PID; } @@ -4966,9 +4966,9 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * by the hardware. */ - if (epphy >= STM32L4_NENDPOINTS) + if (epphy >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); return NULL; } @@ -4988,7 +4988,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, * endpoints. */ - for (epno = 1; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 1; epno < STM32_NENDPOINTS; epno++) { uint8_t bit = 1 << epno; if ((epavail & bit) != 0) @@ -5007,7 +5007,7 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, /* We should not get here */ } - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOEP), (uint16_t)eplog); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); leave_critical_section(flags); return NULL; } @@ -5055,7 +5055,7 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32L4_OTGFS_DSTS); + regval = stm32l4_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32L4_OTGFS_PCGCCTL); + regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5124,7 +5124,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_FEATURES if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -5148,7 +5148,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_OTGFS_DCTL); + regval = stm32l4_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,7 +5166,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32L4_OTGFS_DCTL); + stm32l4_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } @@ -5186,10 +5186,10 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5257,13 +5257,13 @@ static int stm32l4_rxfifo_flush(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32L4_OTGFS_GRSTCTL); + stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5296,12 +5296,12 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; - priv->epavail[0] = STM32L4_EP_AVAILABLE; - priv->epavail[1] = STM32L4_EP_AVAILABLE; + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; /* Initialize the IN endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5319,7 +5319,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYIN2LOG(i); + privep->ep.eplog = STM32_EPPHYIN2LOG(i); /* Control until endpoint is activated */ @@ -5329,7 +5329,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) /* Initialize the OUT endpoint list */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -5346,7 +5346,7 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) */ privep->epphy = i; - privep->ep.eplog = STM32L4_EPPHYOUT2LOG(i); + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); /* Control until endpoint is activated */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32L4_OTGFS_GAHBCFG); + stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5390,10 +5390,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32L4_OTGFS_GRSTCTL); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,101 +5426,101 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GCCFG); + stm32l4_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32L4_OTGFS_GOTGCTL); + regval = stm32l4_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32L4_OTGFS_GOTGCTL); + stm32l4_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32L4_OTGFS_GUSBCFG); + stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32L4_OTGFS_PCGCCTL); + stm32l4_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32L4_OTGFS_DCFG); + regval = stm32l4_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32L4_OTGFS_DCFG); + stm32l4_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32L4_RXFIFO_WORDS, STM32L4_OTGFS_GRXFSIZ); + stm32l4_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); -#if STM32L4_NENDPOINTS > 0 +#if STM32_NENDPOINTS > 0 /* EP0 TX */ - address = STM32L4_RXFIFO_WORDS; + address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | - (STM32L4_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF0); + (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif -#if STM32L4_NENDPOINTS > 1 +#if STM32_NENDPOINTS > 1 /* EP1 TX */ - address += STM32L4_EP0_TXFIFO_WORDS; + address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(1)); + (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif -#if STM32L4_NENDPOINTS > 2 +#if STM32_NENDPOINTS > 2 /* EP2 TX */ - address += STM32L4_EP1_TXFIFO_WORDS; + address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(2)); + (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif -#if STM32L4_NENDPOINTS > 3 +#if STM32_NENDPOINTS > 3 /* EP3 TX */ - address += STM32L4_EP2_TXFIFO_WORDS; + address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(3)); + (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif -#if STM32L4_NENDPOINTS > 4 +#if STM32_NENDPOINTS > 4 /* EP4 TX */ - address += STM32L4_EP3_TXFIFO_WORDS; + address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(4)); + (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif -#if STM32L4_NENDPOINTS > 5 +#if STM32_NENDPOINTS > 5 /* EP5 TX */ - address += STM32L4_EP4_TXFIFO_WORDS; + address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | - (STM32L4_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPTXF(5)); + (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); + stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ @@ -5530,17 +5530,17 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DIEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32L4_OTGFS_DOEPCTL(i)); + regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32L4_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32l4_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_GOTGINT); + stm32l4_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); + regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32L4_OTGFS_GINTSTS); + stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32L4_OTGFS_GINTMSK); + stm32l4_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5622,7 +5622,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) */ stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, - STM32L4_OTGFS_GAHBCFG); + STM32_OTGFS_GAHBCFG); } /**************************************************************************** @@ -5703,7 +5703,7 @@ void arm_usbinitialize(void) /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32L4_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5724,7 +5724,7 @@ void arm_usbinitialize(void) /* Enable USB controller interrupts at the NVIC */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return; errout: @@ -5752,7 +5752,7 @@ void arm_usbuninitialize(void) if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -5764,22 +5764,22 @@ void arm_usbuninitialize(void) /* Disable and detach IRQs */ - up_disable_irq(STM32L4_IRQ_OTGFS); - irq_detach(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); + irq_detach(STM32_IRQ_OTGFS); /* Disable all endpoint interrupts */ - for (i = 0; i < STM32L4_NENDPOINTS; i++) + for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32L4_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32L4_OTGFS_DOEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32L4_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32L4_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32L4_OTGFS_DAINT); + stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); + stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); + stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ @@ -5819,13 +5819,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -5839,14 +5839,14 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); priv->driver = NULL; } else { /* Enable USB controller interrupts */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set * the RS bit to enable the controller. It kind of makes sense @@ -5891,7 +5891,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_FEATURES if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -5911,7 +5911,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupts */ flags = enter_critical_section(); - up_disable_irq(STM32L4_IRQ_OTGFS); + up_disable_irq(STM32_IRQ_OTGFS); /* Disconnect device */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index fa712e94944..955e9d78d80 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -131,20 +131,20 @@ /* Hardware capabilities */ -#define STM32L4_NHOST_CHANNELS 8 /* Number of host channels */ -#define STM32L4_MAX_PACKET_SIZE 64 /* Full speed max packet size */ -#define STM32L4_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ -#define STM32L4_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ -#define STM32L4_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ -#define STM32L4_MAX_PKTCOUNT 256 /* Max packet count */ -#define STM32L4_RETRY_COUNT 3 /* Number of ctrl transfer retries */ +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ /* Delays *******************************************************************/ -#define STM32L4_READY_DELAY 200000 /* In loop counts */ -#define STM32L4_FLUSH_DELAY 200000 /* In loop counts */ -#define STM32L4_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ -#define STM32L4_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ /**************************************************************************** * Private Types @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32L4_MAX_TX_FIFOS]; + struct stm32l4_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -659,7 +659,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) /* Search the table of channels */ - for (chidx = 0; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) { /* Is this channel available? */ @@ -687,7 +687,7 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) { - DEBUGASSERT((unsigned)chidx < STM32L4_NHOST_CHANNELS); + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ @@ -712,7 +712,7 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) /* Free all host channels */ - for (chidx = 2; chidx < STM32L4_NHOST_CHANNELS; chidx++) + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { stm32l4_chan_free(priv, chidx); } @@ -736,7 +736,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32L4_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32l4_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,7 +876,7 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS) & + avail = stm32l4_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,13 +957,13 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + intmsk = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), intmsk); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** @@ -1193,7 +1193,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1218,7 +1218,7 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, chan->funcaddr = funcaddr; chan->speed = speed; chan->interval = 0; - chan->maxpacket = STM32L4_EP0_DEF_PACKET_SIZE; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; chan->indata1 = false; chan->outdata1 = false; @@ -1413,10 +1413,10 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * packets that can be transferred (this should not happen). */ - if (npackets > STM32L4_MAX_PKTCOUNT) + if (npackets > STM32_MAX_PKTCOUNT) { - npackets = STM32L4_MAX_PKTCOUNT; - chan->buflen = STM32L4_MAX_PKTCOUNT * maxpacket; + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; usbhost_trace2(OTGFS_TRACE2_CLIP, chidx, chan->buflen); } } @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32L4_OTGFS_HCTSIZ(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32L4_OTGFS_HFNUM) & 1) == 0) + if ((stm32l4_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1572,7 +1572,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, static inline uint16_t stm32l4_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32L4_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32l4_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif @@ -1647,7 +1647,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_SETUP_DELAY); + while (elapsed < STM32_SETUP_DELAY); return -ETIMEDOUT; } @@ -1893,7 +1893,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, */ clock_t elapsed = clock_systime_ticks() - start; - if (elapsed >= STM32L4_DATANAK_DELAY) + if (elapsed >= STM32_DATANAK_DELAY) { /* Timeout out... break out returning the NAK as * as a failure. @@ -2247,7 +2247,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, elapsed = clock_systime_ticks() - start; if (ret != -EAGAIN || /* Not a NAK condition OR */ - elapsed >= STM32L4_DATANAK_DELAY || /* Timeout has elapsed OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ chan->xfrd > 0) /* Data has been partially * transferred */ { @@ -2419,7 +2419,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, /* Get the address of the Tx FIFO associated with this channel */ - fifo = STM32L4_OTGFS_DFIFO_HCH(chidx); + fifo = STM32_OTGFS_DFIFO_HCH(chidx); /* Transfer all of the data into the Tx FIFO */ @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,7 +2489,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is @@ -2517,7 +2517,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2531,7 +2531,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2556,15 +2556,15 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * logic as each packet was received. */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2633,7 +2633,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2671,10 +2671,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else @@ -2685,7 +2685,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the NAK condition */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32L4_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2751,7 +2751,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2772,7 +2772,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,7 +2781,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. @@ -2800,7 +2800,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2815,7 +2815,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2829,7 +2829,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2845,7 +2845,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCINTMSK(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(chidx), regval); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,7 +2913,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32L4_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ @@ -3018,7 +3018,7 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + intmsk = stm32l4_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32L4_OTGFS_GRXSTSP); + grxsts = stm32l4_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(chidx)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3077,7 +3077,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Transfer the packet from the Rx FIFO into the user buffer */ dest = (uint32_t *)priv->chan[chidx].buffer; - fifo = STM32L4_OTGFS_DFIFO_HCH(0); + fifo = STM32_OTGFS_DFIFO_HCH(0); bcnt32 = (bcnt + 3) >> 2; for (i = 0; i < bcnt32; i++) @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32L4_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32l4_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(chidx), hcchar); + stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,7 +3121,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, intmsk); + stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HNPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPTXSTS); + regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32L4_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3319,12 +3319,12 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) int i = 0; /* Read the Host all channels interrupt register and test each bit in the - * register. Each bit i, i=0...(STM32L4_NHOST_CHANNELS-1), corresponds to + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32L4_OTGFS_HAINT); - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + haint = stm32l4_getreg(STM32_OTGFS_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(i)); + hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32L4_OTGFS_HPRT); + hprt = stm32l4_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3425,7 +3425,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32L4_OTGFS_HCFG); + hcfg = stm32l4_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 6000); + stm32l4_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,7 +3449,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3459,7 +3459,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32L4_OTGFS_HFIR, 48000); + stm32l4_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,7 +3472,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, hcfg); + stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ @@ -3484,7 +3484,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32L4_OTGFS_HPRT, newhprt); + stm32l4_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** @@ -3503,7 +3503,7 @@ static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** @@ -3522,13 +3522,13 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCCHAR(0)); + regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32L4_OTGFS_HCCHAR(0), regval); + stm32l4_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32L4_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + pending = stm32l4_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32l4_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3669,9 +3669,9 @@ static void stm32l4_gint_enable(void) /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } static void stm32l4_gint_disable(void) @@ -3680,9 +3680,9 @@ static void stm32l4_gint_disable(void) /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32L4_OTGFS_GAHBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32L4_OTGFS_GAHBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** @@ -3705,19 +3705,19 @@ static inline void stm32l4_hostinit_enable(void) /* Disable all interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, 0); + stm32l4_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GOTGINT, 0xffffffff); + stm32l4_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTSTS, 0xbfffffff); + stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3753,7 +3753,7 @@ static inline void stm32l4_hostinit_enable(void) regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32L4_OTGFS_GINTMSK); + regval = stm32l4_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32L4_OTGFS_GINTMSK, regval); + stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3972,7 +3972,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Get the current device speed */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -4205,11 +4205,11 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ret = nxmutex_lock(&priv->lock); /* A single channel is represent by an index in the range of 0 to - * STM32L4_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an + * STM32_MAX_TX_FIFOS. Otherwise, the ep must be a pointer to an * allocated control endpoint structure. */ - if ((uintptr_t)ep < STM32L4_MAX_TX_FIFOS) + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) { /* Halt the channel and mark the channel available */ @@ -4480,7 +4480,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4526,7 +4526,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4569,7 +4569,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Loop, retrying until the retry time expires */ - for (retries = 0; retries < STM32L4_RETRY_COUNT; retries++) + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) { /* Send the SETUP request */ @@ -4619,7 +4619,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, elapsed = clock_systime_ticks() - start; } - while (elapsed < STM32L4_DATANAK_DELAY); + while (elapsed < STM32_DATANAK_DELAY); } /* All failures exit here after all retries and timeouts are exhausted */ @@ -4678,7 +4678,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4750,7 +4750,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uvdbg("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); - DEBUGASSERT(priv && buffer && chidx < STM32L4_MAX_TX_FIFOS && buflen > 0); + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); /* We must have exclusive access to the USB host hardware and structures */ @@ -4804,7 +4804,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) uvdbg("chidx: %u: %d\n", chidx); - DEBUGASSERT(priv && chidx < STM32L4_MAX_TX_FIFOS); + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); chan = &priv->chan[chidx]; /* We need to disable interrupts to avoid race conditions with the @@ -4976,16 +4976,16 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, regval); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5051,13 +5051,13 @@ static void stm32l4_flush_rxfifo(void) /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ - for (timeout = 0; timeout < STM32L4_FLUSH_DELAY; timeout++) + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5094,20 +5094,20 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32L4_OTGFS_HPRT); + regval = stm32l4_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32L4_OTGFS_HPRT, regval); + stm32l4_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); @@ -5138,14 +5138,14 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32L4_OTGFS_PCGCCTL, 0); + stm32l4_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ @@ -5153,9 +5153,9 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32L4_OTGFS_HCFG); + regval = stm32l4_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32L4_OTGFS_HCFG, regval); + stm32l4_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,7 +5163,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32L4_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); + stm32l4_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ @@ -5171,7 +5171,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HNPTXFSIZ, regval); + stm32l4_putreg(STM32_OTGFS_HNPTXFSIZ, regval); offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ @@ -5179,7 +5179,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32L4_OTGFS_HPTXFSIZ, regval); + stm32l4_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5192,10 +5192,10 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Clear all pending HC Interrupts */ - for (i = 0; i < STM32L4_NHOST_CHANNELS; i++) + for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32L4_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32L4_OTGFS_HCINTMSK(i), 0); + stm32l4_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32l4_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG @@ -5275,11 +5275,11 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32L4_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); /* Initialize each channel */ - for (i = 0; i < STM32L4_MAX_TX_FIFOS; i++) + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { struct stm32l4_chan_s *chan = &priv->chan[i]; @@ -5311,18 +5311,18 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. */ - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32L4_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); - for (timeout = 0; timeout < STM32L4_READY_DELAY; timeout++) + stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32L4_OTGFS_GRSTCTL); + regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5355,7 +5355,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32L4_OTGFS_GCCFG, regval); + stm32l4_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,10 +5364,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32L4_OTGFS_GUSBCFG); + regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32L4_OTGFS_GUSBCFG, regval); + stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ @@ -5467,7 +5467,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32L4_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5479,7 +5479,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable interrupts at the interrupt controller */ - up_enable_irq(STM32L4_IRQ_OTGFS); + up_enable_irq(STM32_IRQ_OTGFS); return &g_usbconn; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index 100de46b5d0..d43ae86f66f 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -75,7 +75,7 @@ int stm32l4_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ @@ -83,27 +83,27 @@ int stm32l4_pmlpr(void) regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ regval |= RCC_CR_MSIRGSEL; /* Select new MSIRANGE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index da50343ec39..0866f7a2f5a 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -79,15 +79,15 @@ int stm32l4_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32L4_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index 8718d575322..c67a19a27aa 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -114,7 +114,7 @@ int stm32l4_pmstop(bool lpds) * register 1. */ - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -124,7 +124,7 @@ int stm32l4_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1LPR; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -149,7 +149,7 @@ int stm32l4_pmstop2(void) { uint32_t regval; - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); #ifdef CONFIG_STM32L4_SRAM3_HEAP /* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */ @@ -160,7 +160,7 @@ int stm32l4_pmstop2(void) regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 08807a2334e..866af2489de 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -233,9 +233,9 @@ static struct stm32l4_tim_s g_pulsecount1dev = .timid = 1, .timtype = TIMTYPE_TIM1, .t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM1UP, - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .irq = STM32_IRQ_TIM1UP, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ @@ -284,9 +284,9 @@ static struct stm32l4_tim_s g_pulsecount8dev = .timid = 8, .timtype = TIMTYPE_TIM8, .t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS, - .irq = STM32L4_IRQ_TIM8UP, - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .irq = STM32_IRQ_TIM8UP, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ @@ -407,30 +407,30 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_DIER_OFFSET)); _info(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_SR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_EGR_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); _info(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CNT_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_PSC_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET)); _info(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pulsecount_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pulsecount_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pulsecount_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pulsecount_getreg(priv, STM32_GTIM_CCR4_OFFSET)); _info(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pulsecount_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pulsecount_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pulsecount_getreg(priv, STM32_ATIM_RCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DCR_OFFSET), + pulsecount_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } #endif @@ -450,25 +450,25 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, { case 1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } case 2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } case 3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } case 4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } @@ -520,7 +520,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, /* Get the reload values */ - reload = pulsecount_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + reload = pulsecount_getreg(priv, STM32_GTIM_ARR_OFFSET); /* Duty cycle: * @@ -617,8 +617,8 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, /* Set the reload and prescaler values */ - pulsecount_putreg(priv, STM32L4_GTIM_ARR_OFFSET, reload); - pulsecount_putreg(priv, STM32L4_GTIM_PSC_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_ARR_OFFSET, reload); + pulsecount_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; @@ -638,7 +638,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Set up the advanced timer CR1 register. */ - cr1 = pulsecount_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pulsecount_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Pulsecount always uses edge-aligned up-counting mode. */ @@ -653,7 +653,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) /* Write CR1 */ - pulsecount_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pulsecount_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); return OK; } @@ -689,14 +689,14 @@ static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, case 1: case 2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } case 3: case 4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } @@ -773,8 +773,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Get current registers state */ - cr2 = pulsecount_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pulsecount_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx | IDLE | advanced timers | CR2 register * | CCxP | POL | all pulsecount timers | CCER register @@ -807,8 +807,8 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, /* Write registers */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pulsecount_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pulsecount_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pulsecount_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -838,7 +838,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Get current register state */ - ccer = pulsecount_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pulsecount_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ @@ -865,7 +865,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, /* Write register */ - pulsecount_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pulsecount_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -881,11 +881,11 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, if (enable) { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } else { - pulsecount_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pulsecount_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } } @@ -933,7 +933,7 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) /* Disable the timer until we get it configured */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); /* Get configured outputs */ @@ -1015,8 +1015,8 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, /* Disable all interrupts and DMA requests, clear all pending status */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Set timer frequency */ @@ -1051,14 +1051,14 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, */ priv->prev = pulsecount_count(info->count); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->prev - 1); /* Generate an update event to reload the prescaler. This should * preload the RCR into active repetition counter. */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* Now set the value of the RCR that will be loaded on the next * update event. @@ -1066,7 +1066,7 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, priv->count = info->count; priv->curr = pulsecount_count(info->count - priv->prev); - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1076,11 +1076,11 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Set the repetition counter to zero */ - pulsecount_putreg(priv, STM32L4_GTIM_RCR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ - pulsecount_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pulsecount_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); } /* Get configured outputs */ @@ -1105,12 +1105,12 @@ static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, { /* Clear all pending interrupts and enable the update interrupt. */ - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE); /* Enable the timer */ - pulsecount_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pulsecount_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); /* And enable timer interrupts at the NVIC */ @@ -1144,12 +1144,12 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) /* Verify that this is an update interrupt. Nothing else is expected. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_SR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - pulsecount_putreg(priv, STM32L4_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); + pulsecount_putreg(priv, STM32_ATIM_SR_OFFSET, regval & ~ATIM_SR_UIF); /* Calculate the new count by subtracting the number of pulses * since the last interrupt. @@ -1161,9 +1161,9 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * quickly as possible. */ - regval = pulsecount_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + regval = pulsecount_getreg(priv, STM32_ATIM_BDTR_OFFSET); regval &= ~ATIM_BDTR_MOE; - pulsecount_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, regval); + pulsecount_putreg(priv, STM32_ATIM_BDTR_OFFSET, regval); /* Disable first interrupts, stop and reset the timer */ @@ -1194,7 +1194,7 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) priv->prev = priv->curr; priv->curr = pulsecount_count(priv->count - priv->prev); - pulsecount_putreg(priv, STM32L4_ATIM_RCR_OFFSET, + pulsecount_putreg(priv, STM32_ATIM_RCR_OFFSET, (uint16_t)priv->curr - 1); } @@ -1311,7 +1311,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } @@ -1320,7 +1320,7 @@ static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -1484,13 +1484,13 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1506,8 +1506,8 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pulsecount_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pulsecount_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pulsecount_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pulsecount_start() can be called. diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 46d0aff8193..edb4452d0a2 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -451,11 +451,11 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM1_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM1_TRGO) - .trgo = STM32L4_TIM1_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) + .trgo = STM32_TIM1_TRGO, #endif - .base = STM32L4_TIM1_BASE, - .pclk = STM32L4_APB2_TIM1_CLKIN, + .base = STM32_TIM1_BASE, + .pclk = STM32_APB2_TIM1_CLKIN, }; #endif /* CONFIG_STM32L4_TIM1_PWM */ @@ -547,11 +547,11 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM2_TRGO) - .trgo = STM32L4_TIM2_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM2_TRGO) + .trgo = STM32_TIM2_TRGO, #endif - .base = STM32L4_TIM2_BASE, - .pclk = STM32L4_APB1_TIM2_CLKIN, + .base = STM32_TIM2_BASE, + .pclk = STM32_APB1_TIM2_CLKIN, }; #endif /* CONFIG_STM32L4_TIM2_PWM */ @@ -644,11 +644,11 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM3_TRGO) - .trgo = STM32L4_TIM3_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM3_TRGO) + .trgo = STM32_TIM3_TRGO, #endif - .base = STM32L4_TIM3_BASE, - .pclk = STM32L4_APB1_TIM3_CLKIN, + .base = STM32_TIM3_BASE, + .pclk = STM32_APB1_TIM3_CLKIN, }; #endif /* CONFIG_STM32L4_TIM3_PWM */ @@ -740,11 +740,11 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM4_TRGO) - .trgo = STM32L4_TIM4_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM4_TRGO) + .trgo = STM32_TIM4_TRGO, #endif - .base = STM32L4_TIM4_BASE, - .pclk = STM32L4_APB1_TIM4_CLKIN, + .base = STM32_TIM4_BASE, + .pclk = STM32_APB1_TIM4_CLKIN, }; #endif /* CONFIG_STM32L4_TIM4_PWM */ @@ -834,11 +834,11 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = 0, /* No deadtime */ #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM5_TRGO) - .trgo = STM32L4_TIM5_TRGO +#if defined(HAVE_TRGO) && defined(STM32_TIM5_TRGO) + .trgo = STM32_TIM5_TRGO #endif - .base = STM32L4_TIM5_BASE, - .pclk = STM32L4_APB1_TIM5_CLKIN, + .base = STM32_TIM5_BASE, + .pclk = STM32_APB1_TIM5_CLKIN, }; #endif /* CONFIG_STM32L4_TIM5_PWM */ @@ -997,11 +997,11 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM8_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM8_TRGO) - .trgo = STM32L4_TIM8_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) + .trgo = STM32_TIM8_TRGO, #endif - .base = STM32L4_TIM8_BASE, - .pclk = STM32L4_APB2_TIM8_CLKIN, + .base = STM32_TIM8_BASE, + .pclk = STM32_APB2_TIM8_CLKIN, }; #endif /* CONFIG_STM32L4_TIM8_PWM */ @@ -1073,17 +1073,17 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = .chan_num = PWM_TIM15_NCHANNELS, .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM15_LOCK, .t_dts = CONFIG_STM32L4_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY .deadtime = CONFIG_STM32L4_TIM15_DEADTIME, #endif -#if defined(HAVE_TRGO) && defined(STM32L4_TIM15_TRGO) - .trgo = STM32L4_TIM15_TRGO, +#if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) + .trgo = STM32_TIM15_TRGO, #endif - .base = STM32L4_TIM15_BASE, - .pclk = STM32L4_APB2_TIM15_CLKIN, + .base = STM32_TIM15_BASE, + .pclk = STM32_APB2_TIM15_CLKIN, }; #endif /* CONFIG_STM32L4_TIM15_PWM */ @@ -1139,7 +1139,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = .chan_num = PWM_TIM16_NCHANNELS, .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM16_LOCK, .t_dts = CONFIG_STM32L4_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY @@ -1148,8 +1148,8 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ #endif - .base = STM32L4_TIM16_BASE, - .pclk = STM32L4_APB2_TIM16_CLKIN, + .base = STM32_TIM16_BASE, + .pclk = STM32_APB2_TIM16_CLKIN, }; #endif /* CONFIG_STM32L4_TIM16_PWM */ @@ -1205,7 +1205,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = .chan_num = PWM_TIM17_NCHANNELS, .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = CONFIG_STM32L4_TIM17_LOCK, .t_dts = CONFIG_STM32L4_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY @@ -1214,8 +1214,8 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ #endif - .base = STM32L4_TIM17_BASE, - .pclk = STM32L4_APB2_TIM17_CLKIN, + .base = STM32_TIM17_BASE, + .pclk = STM32_APB2_TIM17_CLKIN, }; #endif /* CONFIG_STM32L4_TIM17_PWM */ @@ -1253,7 +1253,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = .chan_num = PWM_LPTIM1_NCHANNELS, .channels = g_pwmlp1channels, .timtype = TIMTYPE_LPTIM1, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1262,15 +1262,15 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM1 */ #endif - .base = STM32L4_LPTIM1_BASE, + .base = STM32_LPTIM1_BASE, #if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, + .pclk = STM32_PCLK1_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, + .pclk = STM32_LSE_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, + .pclk = STM32_LSI_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .pclk = STM32_HSI_FREQUENCY, #endif }; #endif /* CONFIG_STM32L4_LPTIM1_PWM */ @@ -1309,7 +1309,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = .chan_num = PWM_LPTIM2_NCHANNELS, .channels = g_pwmlp2channels, .timtype = TIMTYPE_LPTIM2, - .mode = STM32L4_TIMMODE_COUNTUP, + .mode = STM32_TIMMODE_COUNTUP, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -1318,15 +1318,15 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for LPTIM2 */ #endif - .base = STM32L4_LPTIM2_BASE, + .base = STM32_LPTIM2_BASE, #if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) - .pclk = STM32L4_PCLK1_FREQUENCY, + .pclk = STM32_PCLK1_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) - .pclk = STM32L4_LSE_FREQUENCY, + .pclk = STM32_LSE_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) - .pclk = STM32L4_LSI_FREQUENCY, + .pclk = STM32_LSI_FREQUENCY, #elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) - .pclk = STM32L4_HSI_FREQUENCY, + .pclk = STM32_HSI_FREQUENCY, #endif }; #endif /* CONFIG_STM32L4_LPTIM2_PWM */ @@ -1374,12 +1374,12 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1416,12 +1416,12 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && - (offset == STM32L4_GTIM_CNT_OFFSET || - offset == STM32L4_GTIM_ARR_OFFSET || - offset == STM32L4_GTIM_CCR1_OFFSET || - offset == STM32L4_GTIM_CCR2_OFFSET || - offset == STM32L4_GTIM_CCR3_OFFSET || - offset == STM32L4_GTIM_CCR4_OFFSET)) + (offset == STM32_GTIM_CNT_OFFSET || + offset == STM32_GTIM_ARR_OFFSET || + offset == STM32_GTIM_CCR1_OFFSET || + offset == STM32_GTIM_CCR2_OFFSET || + offset == STM32_GTIM_CCR3_OFFSET || + offset == STM32_GTIM_CCR4_OFFSET)) { /* a 32 bit access is required for a 32 bit register: * if only a 16 bit write would be performed, then the @@ -1462,52 +1462,52 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, { pwminfo("%s:\n", msg); pwminfo(" CFGR: %04x CR: %04x CMP: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CMP_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CMP_OFFSET), + pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET)); pwminfo(" ISR: %04x CNT: %04x\n", - pwm_getreg(priv, STM32L4_LPTIM_ISR_OFFSET), - pwm_getreg(priv, STM32L4_LPTIM_CNT_OFFSET)); + pwm_getreg(priv, STM32_LPTIM_ISR_OFFSET), + pwm_getreg(priv, STM32_LPTIM_CNT_OFFSET)); } else { pwminfo("%s:\n", msg); pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_SMCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DIER_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_SMCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DIER_OFFSET)); pwminfo(" SR: %04x EGR: %04x CCMR1: %04x CCMR2: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_SR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_EGR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCMR2_OFFSET)); + pwm_getreg(priv, STM32_GTIM_SR_OFFSET), + pwm_getreg(priv, STM32_GTIM_EGR_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCMR2_OFFSET)); pwminfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CNT_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_PSC_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCER_OFFSET), + pwm_getreg(priv, STM32_GTIM_CNT_OFFSET), + pwm_getreg(priv, STM32_GTIM_PSC_OFFSET), + pwm_getreg(priv, STM32_GTIM_ARR_OFFSET)); pwminfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_CCR1_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR2_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR3_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_CCR4_OFFSET)); + pwm_getreg(priv, STM32_GTIM_CCR1_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), + pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_ATIM_RCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_ATIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_ATIM_RCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DCR_OFFSET), + pwm_getreg(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { pwminfo(" DCR: %04x DMAR: %04x\n", - pwm_getreg(priv, STM32L4_GTIM_DCR_OFFSET), - pwm_getreg(priv, STM32L4_GTIM_DMAR_OFFSET)); + pwm_getreg(priv, STM32_GTIM_DCR_OFFSET), + pwm_getreg(priv, STM32_GTIM_DMAR_OFFSET)); } } } @@ -1528,7 +1528,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, { /* REVISIT: What about index? Is it necessary for LPTIM? */ - offset = STM32L4_LPTIM_CMP_OFFSET; + offset = STM32_LPTIM_CMP_OFFSET; pwm_putreg(priv, offset, ccr); return OK; @@ -1547,39 +1547,39 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1609,39 +1609,39 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) switch (index) { - case STM32L4_PWM_CHAN1: + case STM32_PWM_CHAN1: { - offset = STM32L4_GTIM_CCR1_OFFSET; + offset = STM32_GTIM_CCR1_OFFSET; break; } - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCR2_OFFSET; + offset = STM32_GTIM_CCR2_OFFSET; break; } - case STM32L4_PWM_CHAN3: + case STM32_PWM_CHAN3: { - offset = STM32L4_GTIM_CCR3_OFFSET; + offset = STM32_GTIM_CCR3_OFFSET; break; } - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCR4_OFFSET; + offset = STM32_GTIM_CCR4_OFFSET; break; } - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN5: { - offset = STM32L4_ATIM_CCR5_OFFSET; + offset = STM32_ATIM_CCR5_OFFSET; break; } - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCR6_OFFSET; + offset = STM32_ATIM_CCR6_OFFSET; break; } @@ -1670,11 +1670,11 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) if (priv->timtype == TIMTYPE_LOWPOWER) { - pwm_putreg(priv, STM32L4_LPTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_LPTIM_ARR_OFFSET, arr); } else { - pwm_putreg(priv, STM32L4_GTIM_ARR_OFFSET, arr); + pwm_putreg(priv, STM32_GTIM_ARR_OFFSET, arr); } return OK; @@ -1690,11 +1690,11 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) if (priv->timtype == TIMTYPE_LOWPOWER) { - return pwm_getreg(priv, STM32L4_LPTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_LPTIM_ARR_OFFSET); } else { - return pwm_getreg(priv, STM32L4_GTIM_ARR_OFFSET); + return pwm_getreg(priv, STM32_GTIM_ARR_OFFSET); } } @@ -1766,13 +1766,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, 0, GTIM_CR1_CEN); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CEN, 0); } #ifdef HAVE_LPTIM } @@ -1782,13 +1782,13 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { /* Enable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, 0, LPTIM_CR_ENABLE); } else { /* Disable timer counter */ - pwm_modifyreg(priv, STM32L4_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); + pwm_modifyreg(priv, STM32_LPTIM_CR_OFFSET, LPTIM_CR_ENABLE, 0); } } #endif @@ -1849,9 +1849,9 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, * intended so multiply by x2 */ - if ((priv->mode == STM32L4_TIMMODE_CENTER1) || - (priv->mode == STM32L4_TIMMODE_CENTER2) || - (priv->mode == STM32L4_TIMMODE_CENTER3)) + if ((priv->mode == STM32_TIMMODE_CENTER1) || + (priv->mode == STM32_TIMMODE_CENTER2) || + (priv->mode == STM32_TIMMODE_CENTER3)) { frequency = frequency * 2; } @@ -1889,7 +1889,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the reload and prescaler values */ pwm_arr_update(dev, reload); - pwm_putreg(priv, STM32L4_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); + pwm_putreg(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)(prescaler - 1)); return OK; } @@ -1961,12 +1961,12 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, /* Set the prescaler value */ - cfgr = pwm_getreg(priv, STM32L4_LPTIM_CFGR_OFFSET); + cfgr = pwm_getreg(priv, STM32_LPTIM_CFGR_OFFSET); cfgr &= ~LPTIM_CFGR_PRESC_MASK; cfgr |= (prescaler << LPTIM_CFGR_PRESC_SHIFT); - pwm_putreg(priv, STM32L4_LPTIM_CFGR_OFFSET, cfgr); + pwm_putreg(priv, STM32_LPTIM_CFGR_OFFSET, cfgr); return OK; } @@ -1994,7 +1994,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) * 15-17 CKD[1:0] ARPE OPM URS UDIS CEN */ - cr1 = pwm_getreg(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = pwm_getreg(priv, STM32_GTIM_CR1_OFFSET); /* Set the counter mode for the advanced timers (1,8) and most general * purpose timers (all 2-5, but not 9-17), i.e., all but TIMTYPE_COUNTUP16 @@ -2016,31 +2016,31 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) switch (priv->mode) { - case STM32L4_TIMMODE_COUNTUP: + case STM32_TIMMODE_COUNTUP: { cr1 |= GTIM_CR1_EDGE; break; } - case STM32L4_TIMMODE_COUNTDOWN: + case STM32_TIMMODE_COUNTDOWN: { cr1 |= GTIM_CR1_EDGE | GTIM_CR1_DIR; break; } - case STM32L4_TIMMODE_CENTER1: + case STM32_TIMMODE_CENTER1: { cr1 |= GTIM_CR1_CENTER1; break; } - case STM32L4_TIMMODE_CENTER2: + case STM32_TIMMODE_CENTER2: { cr1 |= GTIM_CR1_CENTER2; break; } - case STM32L4_TIMMODE_CENTER3: + case STM32_TIMMODE_CENTER3: { cr1 |= GTIM_CR1_CENTER3; break; @@ -2064,7 +2064,7 @@ static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) /* Write CR1 */ - pwm_putreg(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + pwm_putreg(priv, STM32_GTIM_CR1_OFFSET, cr1); errout: return ret; @@ -2104,76 +2104,76 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, switch (mode) { - case STM32L4_CHANMODE_FRZN: + case STM32_CHANMODE_FRZN: { chanmode = GTIM_CCMR_MODE_FRZN; break; } - case STM32L4_CHANMODE_CHACT: + case STM32_CHANMODE_CHACT: { chanmode = GTIM_CCMR_MODE_CHACT; break; } - case STM32L4_CHANMODE_CHINACT: + case STM32_CHANMODE_CHINACT: { chanmode = GTIM_CCMR_MODE_CHINACT; break; } - case STM32L4_CHANMODE_OCREFTOG: + case STM32_CHANMODE_OCREFTOG: { chanmode = GTIM_CCMR_MODE_OCREFTOG; break; } - case STM32L4_CHANMODE_OCREFLO: + case STM32_CHANMODE_OCREFLO: { chanmode = GTIM_CCMR_MODE_OCREFLO; break; } - case STM32L4_CHANMODE_OCREFHI: + case STM32_CHANMODE_OCREFHI: { chanmode = GTIM_CCMR_MODE_OCREFHI; break; } - case STM32L4_CHANMODE_PWM1: + case STM32_CHANMODE_PWM1: { chanmode = GTIM_CCMR_MODE_PWM1; break; } - case STM32L4_CHANMODE_PWM2: + case STM32_CHANMODE_PWM2: { chanmode = GTIM_CCMR_MODE_PWM2; break; } - case STM32L4_CHANMODE_COMBINED1: + case STM32_CHANMODE_COMBINED1: { chanmode = ATIM_CCMR_MODE_COMBINED1; ocmbit = true; break; } - case STM32L4_CHANMODE_COMBINED2: + case STM32_CHANMODE_COMBINED2: { chanmode = ATIM_CCMR_MODE_COMBINED2; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC1: + case STM32_CHANMODE_ASYMMETRIC1: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC1; ocmbit = true; break; } - case STM32L4_CHANMODE_ASYMMETRIC2: + case STM32_CHANMODE_ASYMMETRIC2: { chanmode = ATIM_CCMR_MODE_ASYMMETRIC2; ocmbit = true; @@ -2194,24 +2194,24 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Get CCMR offset */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN2: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN2: { - offset = STM32L4_GTIM_CCMR1_OFFSET; + offset = STM32_GTIM_CCMR1_OFFSET; break; } - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN4: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN4: { - offset = STM32L4_GTIM_CCMR2_OFFSET; + offset = STM32_GTIM_CCMR2_OFFSET; break; } - case STM32L4_PWM_CHAN5: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN5: + case STM32_PWM_CHAN6: { - offset = STM32L4_ATIM_CCMR3_OFFSET; + offset = STM32_ATIM_CCMR3_OFFSET; break; } @@ -2235,9 +2235,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, { /* Configure channel 1/3/5 */ - case STM32L4_PWM_CHAN1: - case STM32L4_PWM_CHAN3: - case STM32L4_PWM_CHAN5: + case STM32_PWM_CHAN1: + case STM32_PWM_CHAN3: + case STM32_PWM_CHAN5: { /* Reset current channel 1/3/5 mode configuration */ @@ -2271,9 +2271,9 @@ static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, /* Configure channel 2/4/6 */ - case STM32L4_PWM_CHAN2: - case STM32L4_PWM_CHAN4: - case STM32L4_PWM_CHAN6: + case STM32_PWM_CHAN2: + case STM32_PWM_CHAN4: + case STM32_PWM_CHAN6: { /* Reset current channel 2/4/6 mode configuration */ @@ -2334,8 +2334,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Get current registers state */ - cr2 = pwm_getreg(priv, STM32L4_GTIM_CR2_OFFSET); - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + cr2 = pwm_getreg(priv, STM32_GTIM_CR2_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* | OISx/OISxN | IDLE | for ADVANCED and COUNTUP16 | CR2 register * | CCxP/CCxNP | POL | all PWM timers | CCER register @@ -2343,7 +2343,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure output polarity (all PWM timers) */ - if (priv->channels[channel - 1].out1.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out1.pol == STM32_POL_NEG) { ccer |= (GTIM_CCER_CC1P << ((channel - 1) * 4)); } @@ -2358,7 +2358,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, { /* Configure output IDLE State */ - if (priv->channels[channel - 1].out1.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out1.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1 << ((channel - 1) * 2)); } @@ -2370,7 +2370,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, #ifdef HAVE_PWM_COMPLEMENTARY /* Configure complementary output IDLE state */ - if (priv->channels[channel - 1].out2.idle == STM32L4_IDLE_ACTIVE) + if (priv->channels[channel - 1].out2.idle == STM32_IDLE_ACTIVE) { cr2 |= (ATIM_CR2_OIS1N << ((channel - 1) * 2)); } @@ -2381,7 +2381,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Configure complementary output polarity */ - if (priv->channels[channel - 1].out2.pol == STM32L4_POL_NEG) + if (priv->channels[channel - 1].out2.pol == STM32_POL_NEG) { ccer |= (ATIM_CCER_CC1NP << ((channel - 1) * 4)); } @@ -2417,8 +2417,8 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, /* Write registers */ - pwm_modifyreg(priv, STM32L4_GTIM_CR2_OFFSET, 0, cr2); - pwm_modifyreg(priv, STM32L4_GTIM_CCER_OFFSET, 0, ccer); + pwm_modifyreg(priv, STM32_GTIM_CR2_OFFSET, 0, cr2); + pwm_modifyreg(priv, STM32_GTIM_CCER_OFFSET, 0, ccer); return OK; } @@ -2448,23 +2448,23 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Get current register state */ - ccer = pwm_getreg(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = pwm_getreg(priv, STM32_GTIM_CCER_OFFSET); /* Get outputs configuration */ - regval |= ((outputs & STM32L4_PWM_OUT1) ? GTIM_CCER_CC1E : 0); - regval |= ((outputs & STM32L4_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT2) ? GTIM_CCER_CC2E : 0); - regval |= ((outputs & STM32L4_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT3) ? GTIM_CCER_CC3E : 0); - regval |= ((outputs & STM32L4_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); - regval |= ((outputs & STM32L4_PWM_OUT4) ? GTIM_CCER_CC4E : 0); + regval |= ((outputs & STM32_PWM_OUT1) ? GTIM_CCER_CC1E : 0); + regval |= ((outputs & STM32_PWM_OUT1N) ? ATIM_CCER_CC1NE : 0); + regval |= ((outputs & STM32_PWM_OUT2) ? GTIM_CCER_CC2E : 0); + regval |= ((outputs & STM32_PWM_OUT2N) ? ATIM_CCER_CC2NE : 0); + regval |= ((outputs & STM32_PWM_OUT3) ? GTIM_CCER_CC3E : 0); + regval |= ((outputs & STM32_PWM_OUT3N) ? ATIM_CCER_CC3NE : 0); + regval |= ((outputs & STM32_PWM_OUT4) ? GTIM_CCER_CC4E : 0); /* NOTE: CC4N does not exist, but some docs show configuration bits for it */ - regval |= ((outputs & STM32L4_PWM_OUT5) ? ATIM_CCER_CC5E : 0); - regval |= ((outputs & STM32L4_PWM_OUT6) ? ATIM_CCER_CC6E : 0); + regval |= ((outputs & STM32_PWM_OUT5) ? ATIM_CCER_CC5E : 0); + regval |= ((outputs & STM32_PWM_OUT6) ? ATIM_CCER_CC6E : 0); if (state == true) { @@ -2481,7 +2481,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, /* Write register */ - pwm_putreg(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + pwm_putreg(priv, STM32_GTIM_CCER_OFFSET, ccer); return OK; } @@ -2508,7 +2508,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Get current register state */ - bdtr = pwm_getreg(priv, STM32L4_ATIM_BDTR_OFFSET); + bdtr = pwm_getreg(priv, STM32_ATIM_BDTR_OFFSET); /* TODO: check if BDTR not locked */ @@ -2519,7 +2519,7 @@ static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) /* Write BDTR register */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); errout: return ret; @@ -2538,7 +2538,7 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; - pwm_putreg(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); return OK; } @@ -2565,13 +2565,13 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { /* Reset MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, ATIM_BDTR_MOE, 0); } else { /* Set MOE bit */ - pwm_modifyreg(priv, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + pwm_modifyreg(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } return OK; @@ -2606,7 +2606,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out1.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1 << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1 << ((channel - 1) * 2)); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -2614,7 +2614,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) if (priv->channels[i].out2.in_use == 1) { - outputs |= (STM32L4_PWM_OUT1N << ((channel - 1) * 2)); + outputs |= (STM32_PWM_OUT1N << ((channel - 1) * 2)); } #endif } @@ -2644,7 +2644,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) * should be no basic timers in this context */ - pwm_modifyreg(priv, STM32L4_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, + pwm_modifyreg(priv, STM32_GTIM_CR1_OFFSET, GTIM_CR1_CKD_MASK, priv->t_dts << GTIM_CR1_CKD_SHIFT); #ifdef HAVE_PWM_COMPLEMENTARY @@ -2664,7 +2664,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 1 polarity */ - bdtr |= (priv->brk.pol1 == STM32L4_POL_NEG ? ATIM_BDTR_BKP : 0); + bdtr |= (priv->brk.pol1 == STM32_POL_NEG ? ATIM_BDTR_BKP : 0); } /* Configure Break 1 */ @@ -2677,7 +2677,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Set Break 2 polarity */ - bdtr |= (priv->brk.pol2 == STM32L4_POL_NEG ? ATIM_BDTR_BK2P : 0); + bdtr |= (priv->brk.pol2 == STM32_POL_NEG ? ATIM_BDTR_BK2P : 0); /* Configure BRK2 filter */ @@ -2699,7 +2699,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) /* Write BDTR register at once */ - pwm_putreg(priv, STM32L4_ATIM_BDTR_OFFSET, bdtr); + pwm_putreg(priv, STM32_ATIM_BDTR_OFFSET, bdtr); return OK; } @@ -2956,7 +2956,7 @@ static int pwm_timer(struct pwm_lowerhalf_s *dev, /* Set the repetition counter to zero */ - pwm_putreg(priv, STM32L4_ATIM_RCR_OFFSET, 0); + pwm_putreg(priv, STM32_ATIM_RCR_OFFSET, 0); /* Generate an update event to reload the prescaler */ @@ -3047,9 +3047,9 @@ static int pwm_lptimer(struct pwm_lowerhalf_s *dev, /* Start counter */ - cr = pwm_getreg(priv, STM32L4_LPTIM_CR_OFFSET); + cr = pwm_getreg(priv, STM32_LPTIM_CR_OFFSET); cr |= LPTIM_CR_CNTSTRT; - pwm_putreg(priv, STM32L4_LPTIM_CR_OFFSET, cr); + pwm_putreg(priv, STM32_LPTIM_CR_OFFSET, cr); pwm_dumpregs(dev, "After starting"); @@ -3086,7 +3086,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM1_PWM case 1: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; } @@ -3095,7 +3095,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM2_PWM case 2: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM2EN; break; } @@ -3104,7 +3104,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM3_PWM case 3: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM3EN; break; } @@ -3113,7 +3113,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM4_PWM case 4: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM4EN; break; } @@ -3122,7 +3122,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM5_PWM case 5: { - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; en_bit = RCC_APB1ENR1_TIM5EN; break; } @@ -3131,7 +3131,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM8_PWM case 8: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM8EN; break; } @@ -3140,7 +3140,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM15_PWM case 15: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; } @@ -3149,7 +3149,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM16_PWM case 16: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; } @@ -3158,7 +3158,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #ifdef CONFIG_STM32L4_TIM17_PWM case 17: { - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; break; } @@ -3198,12 +3198,12 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, if (on) { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR1, + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); } @@ -3217,7 +3217,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #endif /* Choose which clock will be used for LPTIM1 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM1SEL_MASK, clock_bits); break; } @@ -3231,12 +3231,12 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, if (on) { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); } else { - modifyreg32(STM32L4_RCC_APB1ENR2, + modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); } @@ -3250,7 +3250,7 @@ static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, #endif /* Choose which clock will be used for LPTIM2 */ - modifyreg32(STM32L4_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, + modifyreg32(STM32_RCC_CCIPR, RCC_CCIPR_LPTIM2SEL_MASK, clock_bits); break; } @@ -3543,49 +3543,49 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_TIM1_PWM case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif #ifdef CONFIG_STM32L4_TIM3_PWM case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif #ifdef CONFIG_STM32L4_TIM4_PWM case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif #ifdef CONFIG_STM32L4_TIM5_PWM case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_PWM case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif #ifdef CONFIG_STM32L4_TIM16_PWM case 16: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif #ifdef CONFIG_STM32L4_TIM17_PWM case 17: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; break; #endif @@ -3599,13 +3599,13 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { #ifdef CONFIG_STM32L4_LPTIM1_PWM case 1: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_LPTIM1RST; break; #endif #ifdef CONFIG_STM32L4_LPTIM2_PWM case 2: - regaddr = STM32L4_RCC_APB1RSTR2; + regaddr = STM32_RCC_APB1RSTR2; resetbit = RCC_APB1RSTR2_LPTIM2RST; break; #endif @@ -3626,8 +3626,8 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) /* Disable further interrupts and stop the timer */ - pwm_putreg(priv, STM32L4_GTIM_DIER_OFFSET, 0); - pwm_putreg(priv, STM32L4_GTIM_SR_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_DIER_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_SR_OFFSET, 0); /* Reset the timer - stopping the output and putting the timer back * into a state where pwm_start() can be called. diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 14c75affd5f..08b8e021a4f 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -844,80 +844,80 @@ enum stm32l4_timmode_e { - STM32L4_TIMMODE_COUNTUP = 0, - STM32L4_TIMMODE_COUNTDOWN = 1, - STM32L4_TIMMODE_CENTER1 = 2, - STM32L4_TIMMODE_CENTER2 = 3, - STM32L4_TIMMODE_CENTER3 = 4, + STM32_TIMMODE_COUNTUP = 0, + STM32_TIMMODE_COUNTDOWN = 1, + STM32_TIMMODE_CENTER1 = 2, + STM32_TIMMODE_CENTER2 = 3, + STM32_TIMMODE_CENTER3 = 4, }; /* Timer output polarity */ enum stm32l4_pwm_pol_e { - STM32L4_POL_POS = 0, - STM32L4_POL_NEG = 1, + STM32_POL_POS = 0, + STM32_POL_NEG = 1, }; /* Timer output IDLE state */ enum stm32l4_pwm_idle_e { - STM32L4_IDLE_INACTIVE = 0, - STM32L4_IDLE_ACTIVE = 1 + STM32_IDLE_INACTIVE = 0, + STM32_IDLE_ACTIVE = 1 }; /* PWM channel mode */ enum stm32l4_chanmode_e { - STM32L4_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ - STM32L4_CHANMODE_CHACT = 1, /* OCxREF active on match */ - STM32L4_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ - STM32L4_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ - STM32L4_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ - STM32L4_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ - STM32L4_CHANMODE_PWM1 = 6, /* PWM mode 1 */ - STM32L4_CHANMODE_PWM2 = 7, /* PWM mode 2 */ - STM32L4_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ - STM32L4_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ - STM32L4_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ - STM32L4_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ + STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ + STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ + STM32_CHANMODE_CHINACT = 2, /* OCxREF inactive on match */ + STM32_CHANMODE_OCREFTOG = 3, /* OCxREF toggles when TIMy_CNT=TIMyCCRx */ + STM32_CHANMODE_OCREFLO = 4, /* OCxREF is forced low */ + STM32_CHANMODE_OCREFHI = 5, /* OCxREF is forced high */ + STM32_CHANMODE_PWM1 = 6, /* PWM mode 1 */ + STM32_CHANMODE_PWM2 = 7, /* PWM mode 2 */ + STM32_CHANMODE_COMBINED1 = 8, /* Combined PWM mode 1 */ + STM32_CHANMODE_COMBINED2 = 9, /* Combined PWM mode 2 */ + STM32_CHANMODE_ASYMMETRIC1 = 10, /* Asymmetric PWM mode 1 */ + STM32_CHANMODE_ASYMMETRIC2 = 11, /* Asymmetric PWM mode 2 */ }; /* PWM timer channel */ enum stm32l4_pwm_chan_e { - STM32L4_PWM_CHAN1 = 1, - STM32L4_PWM_CHAN2 = 2, - STM32L4_PWM_CHAN3 = 3, - STM32L4_PWM_CHAN4 = 4, - STM32L4_PWM_CHAN5 = 5, - STM32L4_PWM_CHAN6 = 6, + STM32_PWM_CHAN1 = 1, + STM32_PWM_CHAN2 = 2, + STM32_PWM_CHAN3 = 3, + STM32_PWM_CHAN4 = 4, + STM32_PWM_CHAN5 = 5, + STM32_PWM_CHAN6 = 6, }; /* PWM timer channel output */ enum stm32l4_pwm_output_e { - STM32L4_PWM_OUT1 = (1 << 0), - STM32L4_PWM_OUT1N = (1 << 1), - STM32L4_PWM_OUT2 = (1 << 2), - STM32L4_PWM_OUT2N = (1 << 3), - STM32L4_PWM_OUT3 = (1 << 4), - STM32L4_PWM_OUT3N = (1 << 5), - STM32L4_PWM_OUT4 = (1 << 6), + STM32_PWM_OUT1 = (1 << 0), + STM32_PWM_OUT1N = (1 << 1), + STM32_PWM_OUT2 = (1 << 2), + STM32_PWM_OUT2N = (1 << 3), + STM32_PWM_OUT3 = (1 << 4), + STM32_PWM_OUT3N = (1 << 5), + STM32_PWM_OUT4 = (1 << 6), /* 1 << 7 reserved - no complementary output for CH4 */ /* Only available inside micro */ - STM32L4_PWM_OUT5 = (1 << 8), + STM32_PWM_OUT5 = (1 << 8), /* 1 << 9 reserved - no complementary output for CH5 */ - STM32L4_PWM_OUT6 = (1 << 10), + STM32_PWM_OUT6 = (1 << 10), /* 1 << 11 reserved - no complementary output for CH6 */ }; diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index cd78d8d6d43..1da59b2797a 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L4_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L4_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l4_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l4_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR1_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32L4_PWR_CR1_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l4_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l4_pwr_enableusv(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -228,7 +228,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -238,7 +238,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,14 +248,14 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -283,7 +283,7 @@ bool stm32l4_pwr_get_pvmo2(void) uint32_t regval; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -293,7 +293,7 @@ bool stm32l4_pwr_get_pvmo2(void) /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_SR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { @@ -325,7 +325,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -335,7 +335,7 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32L4_PWR_CR2_OFFSET); + regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,14 +345,14 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32L4_PWR_CR2_OFFSET, regval); + stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -392,7 +392,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32L4_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -404,5 +404,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32L4_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 7f12c3b3990..d3e065ba9c4 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -94,62 +94,62 @@ #ifdef CONFIG_STM32L4_QENCODER_FILTER # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) # if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 # elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32L4_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32L4_QENCODER_ICF -# define STM32L4_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32L4_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -275,11 +275,11 @@ static const struct qe_ops_s g_qecallbacks = static const struct stm32l4_qeconfig_s g_tim1config = { .timid = 1, - .irq = STM32L4_IRQ_TIM1UP, + .irq = STM32_IRQ_TIM1UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM1_BITWIDTH, #endif - .base = STM32L4_TIM1_BASE, + .base = STM32_TIM1_BASE, .psc = CONFIG_STM32L4_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, @@ -299,11 +299,11 @@ static struct stm32l4_lowerhalf_s g_tim1lower = static const struct stm32l4_qeconfig_s g_tim2config = { .timid = 2, - .irq = STM32L4_IRQ_TIM2, + .irq = STM32_IRQ_TIM2, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM2_BITWIDTH, #endif - .base = STM32L4_TIM2_BASE, + .base = STM32_TIM2_BASE, .psc = CONFIG_STM32L4_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, @@ -323,11 +323,11 @@ static struct stm32l4_lowerhalf_s g_tim2lower = static const struct stm32l4_qeconfig_s g_tim3config = { .timid = 3, - .irq = STM32L4_IRQ_TIM3, + .irq = STM32_IRQ_TIM3, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM3_BITWIDTH, #endif - .base = STM32L4_TIM3_BASE, + .base = STM32_TIM3_BASE, .psc = CONFIG_STM32L4_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, @@ -347,11 +347,11 @@ static struct stm32l4_lowerhalf_s g_tim3lower = static const struct stm32l4_qeconfig_s g_tim4config = { .timid = 4, - .irq = STM32L4_IRQ_TIM4, + .irq = STM32_IRQ_TIM4, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM4_BITWIDTH, #endif - .base = STM32L4_TIM4_BASE, + .base = STM32_TIM4_BASE, .psc = CONFIG_STM32L4_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, @@ -371,11 +371,11 @@ static struct stm32l4_lowerhalf_s g_tim4lower = static const struct stm32l4_qeconfig_s g_tim5config = { .timid = 5, - .irq = STM32L4_IRQ_TIM5, + .irq = STM32_IRQ_TIM5, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM5_BITWIDTH, #endif - .base = STM32L4_TIM5_BASE, + .base = STM32_TIM5_BASE, .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, @@ -395,11 +395,11 @@ static struct stm32l4_lowerhalf_s g_tim5lower = static const struct stm32l4_qeconfig_s g_tim8config = { .timid = 8, - .irq = STM32L4_IRQ_TIM8UP, + .irq = STM32_IRQ_TIM8UP, #ifdef HAVE_MIXEDWIDTH_TIMERS .width = TIM8_BITWIDTH, #endif - .base = STM32L4_TIM8_BASE, + .base = STM32_TIM8_BASE, .psc = CONFIG_STM32L4_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, @@ -531,43 +531,43 @@ static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCMR2_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_ARR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR2_OFFSET)); + stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32L4_GTIM_CCR4_OFFSET)); + stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32L4_GTIM_ARR_OFFSET, 0xffffffff); + stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32L4_GTIM_ARR_OFFSET, 0xffff); + stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -737,14 +737,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ stm32l4_putreg16(priv, - STM32L4_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); + STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32L4_ATIM_RCR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,7 +752,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32L4_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ @@ -761,27 +761,27 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32L4_GTIM_SMCR_OFFSET); + smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32L4_GTIM_SMCR_OFFSET, smcr); + stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -790,34 +790,34 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32L4_GTIM_CCER_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32L4_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32L4_GTIM_CCER_OFFSET, ccer); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32L4_GTIM_CCMR1_OFFSET); + ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32L4_GTIM_CCMR1_OFFSET, ccmr1); + stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,22 +886,22 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32L4_GTIM_DIER_OFFSET); + dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, dier); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32L4_GTIM_CR1_OFFSET); + cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32L4_GTIM_CR1_OFFSET, cr1); + stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); stm32l4_dumpregs(priv, "After setup"); @@ -943,8 +943,8 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32L4_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32L4_GTIM_SR_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ @@ -952,37 +952,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) { #ifdef CONFIG_STM32L4_TIM1_QE case 1: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif #ifdef CONFIG_STM32L4_TIM2_QE case 2: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif #ifdef CONFIG_STM32L4_TIM3_QE case 3: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif #ifdef CONFIG_STM32L4_TIM4_QE case 4: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif #ifdef CONFIG_STM32L4_TIM5_QE case 5: - regaddr = STM32L4_RCC_APB1RSTR1; + regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif #ifdef CONFIG_STM32L4_TIM8_QE case 8: - regaddr = STM32L4_RCC_APB2RSTR; + regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif @@ -1010,14 +1010,14 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32L4_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32l4_configgpio(pincfg); return OK; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,7 +1062,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32L4_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,7 +1099,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32L4_GTIM_CNT_OFFSET, 0); + stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 954f8b460ce..f3d3bc994a3 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(STM32L4_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) +#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -162,7 +162,7 @@ struct stm32l4_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ @@ -220,7 +220,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif @@ -332,11 +332,11 @@ static struct stm32l4_qspidev_s g_qspi0dev = { .ops = &g_qspi0ops, }, - .base = STM32L4_QSPI_BASE, + .base = STM32_QSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, - .irq = STM32L4_IRQ_QUADSPI, + .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, @@ -478,7 +478,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) * output. */ - regval = getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET); /* Control Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CR_OFFSET); /* Control Register */ spiinfo("CR:%08" PRIx32 "\n", regval); spiinfo(" EN:%1d ABORT:%1d DMAEN:%1d TCEN:%1d SSHIFT:%1d\n" " FTHRES: %d\n" @@ -499,14 +499,14 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CR_PMM) ? 1 : 0, (regval & QSPI_CR_PRESCALER_MASK) >> QSPI_CR_PRESCALER_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET); /* Device Configuration Register */ spiinfo("DCR:%08" PRIx32 "\n", regval); spiinfo(" CKMODE:%1d CSHT:%d FSIZE:%d\n", (regval & QSPI_DCR_CKMODE) ? 1 : 0, (regval & QSPI_DCR_CSHT_MASK) >> QSPI_DCR_CSHT_SHIFT, (regval & QSPI_DCR_FSIZE_MASK) >> QSPI_DCR_FSIZE_SHIFT); - regval = getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ + regval = getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET); /* Communication Configuration Register */ spiinfo("CCR:%08" PRIx32 "\n", regval); spiinfo(" INST:%02x IMODE:%d ADMODE:%d ADSIZE:%d ABMODE:%d\n" " ABSIZE:%d DCYC:%d DMODE:%d FMODE:%d\n" @@ -523,7 +523,7 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) (regval & QSPI_CCR_SIOO) ? 1 : 0, (regval & QSPI_CCR_DDRM) ? 1 : 0); - regval = getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET); /* Status Register */ + regval = getreg32(priv->base + STM32_QUADSPI_SR_OFFSET); /* Status Register */ spiinfo("SR:%08" PRIx32 "\n", regval); spiinfo(" TEF:%1d TCF:%1d FTF:%1d SMF:%1d TOF:%1d BUSY:%1d FLEVEL:%d\n", (regval & QSPI_SR_TEF) ? 1 : 0, @@ -537,19 +537,19 @@ static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) #else spiinfo(" CR:%08" PRIx32 " DCR:%08" PRIx32 " CCR:%08" PRIx32 " SR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_CR_OFFSET), /* Control Register */ - getreg32(priv->base + STM32L4_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ - getreg32(priv->base + STM32L4_QUADSPI_SR_OFFSET)); /* Status Register */ + getreg32(priv->base + STM32_QUADSPI_CR_OFFSET), /* Control Register */ + getreg32(priv->base + STM32_QUADSPI_DCR_OFFSET), /* Device Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_CCR_OFFSET), /* Communication Configuration Register */ + getreg32(priv->base + STM32_QUADSPI_SR_OFFSET)); /* Status Register */ spiinfo(" DLR:%08" PRIx32 " ABR:%08" PRIx32 " PSMKR:%08" PRIx32 " PSMAR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_DLR_OFFSET), /* Data Length Register */ - getreg32(priv->base + STM32L4_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ - getreg32(priv->base + STM32L4_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ + getreg32(priv->base + STM32_QUADSPI_DLR_OFFSET), /* Data Length Register */ + getreg32(priv->base + STM32_QUADSPI_ABR_OFFSET), /* Alternate Bytes Register */ + getreg32(priv->base + STM32_QUADSPI_PSMKR_OFFSET), /* Polling Status mask Register */ + getreg32(priv->base + STM32_QUADSPI_PSMAR_OFFSET)); /* Polling Status match Register */ spiinfo(" PIR:%08" PRIx32 " LPTR:%08" PRIx32 "\n", - getreg32(priv->base + STM32L4_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ - getreg32(priv->base + STM32L4_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ + getreg32(priv->base + STM32_QUADSPI_PIR_OFFSET), /* Polling Interval Register */ + getreg32(priv->base + STM32_QUADSPI_LPTR_OFFSET)); /* Low-Power Timeout Register */ UNUSED(regval); #endif } @@ -561,22 +561,22 @@ static void qspi_dumpgpioconfig(const char *msg) uint32_t regval; spiinfo("%s:\n", msg); - regval = getreg32(STM32L4_GPIOE_MODER); + regval = getreg32(STM32_GPIOE_MODER); spiinfo("E_MODER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OTYPER); + regval = getreg32(STM32_GPIOE_OTYPER); spiinfo("E_OTYPER:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_OSPEED); + regval = getreg32(STM32_GPIOE_OSPEED); spiinfo("E_OSPEED:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_PUPDR); + regval = getreg32(STM32_GPIOE_PUPDR); spiinfo("E_PUPDR:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRL); + regval = getreg32(STM32_GPIOE_AFRL); spiinfo("E_AFRL:%08" PRIx32 "\n", regval); - regval = getreg32(STM32L4_GPIOE_AFRH); + regval = getreg32(STM32_GPIOE_AFRH); spiinfo("E_AFRH:%08" PRIx32 "\n", regval); } #endif @@ -787,7 +787,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -918,7 +918,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -951,12 +951,12 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, if (polarity) { - while (!((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (!((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } else { - while (((regval = qspi_getreg(priv, STM32L4_QUADSPI_SR_OFFSET)) + while (((regval = qspi_getreg(priv, STM32_QUADSPI_SR_OFFSET)) & mask)); } } @@ -979,9 +979,9 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) { uint32_t regval; - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_ABORT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /**************************************************************************** @@ -1010,14 +1010,14 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, if (CCR_DMODE_NONE != xctn->datamode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->datasize - 1, STM32L4_QUADSPI_DLR_OFFSET); + qspi_putreg(priv, xctn->datasize - 1, STM32_QUADSPI_DLR_OFFSET); } /* If we have alternate bytes, stick them in now */ if (CCR_ABMODE_NONE != xctn->altbytesmode) { - qspi_putreg(priv, xctn->altbytes, STM32L4_QUADSPI_ABR_OFFSET); + qspi_putreg(priv, xctn->altbytes, STM32_QUADSPI_ABR_OFFSET); } /* Build the CCR value and set it */ @@ -1033,17 +1033,17 @@ static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, QSPI_CCR_FMODE(fctn) | (xctn->isddr ? QSPI_CCR_SIOO : 0) | (xctn->issioo ? QSPI_CCR_DDRM : 0); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* If we have and need and address, set that now, too */ if (CCR_ADMODE_NONE != xctn->addrmode && CCR_FMODE_MEMMAP != fctn) { - qspi_putreg(priv, xctn->addr, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, xctn->addr, STM32_QUADSPI_AR_OFFSET); } } -#if defined(STM32L4_QSPI_INTERRUPTS) +#if defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1068,22 +1068,22 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Let's find out what is going on */ - status = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_SR_OFFSET); - cr = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + status = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_SR_OFFSET); + cr = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); /* Is it 'FIFO Threshold'? */ if ((status & QSPI_SR_FTF) && (cr & QSPI_CR_FTIE)) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); if (g_qspi0dev.xctn->function == CCR_FMODE_INDWR) { /* Write data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1105,7 +1105,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) /* Read data until we have no more or have no place to put it */ while ((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FTF) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1131,27 +1131,27 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer * complete Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Do the last bit of read if needed */ if (g_qspi0dev.xctn->function == CCR_FMODE_INDRD) { volatile uint32_t *datareg = (volatile uint32_t *) - (g_qspi0dev.base + STM32L4_QUADSPI_DR_OFFSET); + (g_qspi0dev.base + STM32_QUADSPI_DR_OFFSET); /* Read any remaining data */ while (((regval = qspi_getreg(&g_qspi0dev, - STM32L4_QUADSPI_SR_OFFSET)) & + STM32_QUADSPI_SR_OFFSET)) & QSPI_SR_FLEVEL_MASK) != 0) { if (g_qspi0dev.xctn->idxnow < g_qspi0dev.xctn->datasize) @@ -1189,7 +1189,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CSMF, STM32_QUADSPI_FCR); /* If 'automatic poll mode stop' is activated, we're done */ @@ -1197,9 +1197,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Disable the QSPI Transfer Error and Status Match Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_SMIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set success status */ @@ -1223,14 +1223,14 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTEF, STM32_QUADSPI_FCR); /* Disable all the QSPI Interrupts */ - regval = qspi_getreg(&g_qspi0dev, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(&g_qspi0dev, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); - qspi_putreg(&g_qspi0dev, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(&g_qspi0dev, regval, STM32_QUADSPI_CR_OFFSET); /* Set error status; 'transfer error' means that, in 'indirect mode', * an invalid address is attempted to be accessed. 'Invalid' is @@ -1251,7 +1251,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) { /* Acknowledge interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); /* XXX this interrupt simply means that, in 'memory mapped mode', * the QSPI memory has not been accessed for a while, and the @@ -1426,16 +1426,16 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, - STM32L4_QUADSPI_DR_OFFSET), + STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); qspi_dma_sample(priv, DMA_AFTER_SETUP); /* Enable the memory transfer */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command info */ @@ -1481,9 +1481,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, if (ret < 0) { DEBUGPANIC(); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); return ret; } @@ -1512,9 +1512,9 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, stm32l4_dmastop(priv->dmach); - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Complain if the DMA fails */ @@ -1527,7 +1527,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, } #endif -#if !defined(STM32L4_QSPI_INTERRUPTS) +#if !defined(STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -1548,12 +1548,12 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *dest = (uint8_t *)xctn->buffer; uint32_t addrval; uint32_t regval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); if (dest != NULL) { /* Counter of remaining data */ @@ -1562,14 +1562,14 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Ensure CCR register specifies indirect read */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CCR_OFFSET); regval &= ~QSPI_CCR_FMODE_MASK; regval |= QSPI_CCR_FMODE(CCR_FMODE_INDRD); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CCR_OFFSET); /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Transfer loop */ @@ -1589,7 +1589,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the busy flag, and ditch any extra bytes in * fifo @@ -1626,7 +1626,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, { int ret = OK; volatile uint32_t *datareg = - (volatile uint32_t *)(priv->base + STM32L4_QUADSPI_DR_OFFSET); + (volatile uint32_t *)(priv->base + STM32_QUADSPI_DR_OFFSET); uint8_t *src = (uint8_t *)xctn->buffer; if (src != NULL) @@ -1652,7 +1652,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, /* Wait for transfer complete, then clear it */ qspi_waitstatusflags(priv, QSPI_SR_TCF, 1); - qspi_putreg(priv, QSPI_FCR_CTCF, STM32L4_QUADSPI_FCR); + qspi_putreg(priv, QSPI_FCR_CTCF, STM32_QUADSPI_FCR); /* Use Abort to clear the Busy flag */ @@ -1765,7 +1765,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) * prescaler = STL32L4_QSPI_CLOCK / frequency * * Where prescaler can have the range 1 to 256 and the - * STM32L4_QUADSPI_CR_OFFSET register field holds prescaler - 1. + * STM32_QUADSPI_CR_OFFSET register field holds prescaler - 1. * NOTE that a "ceiling" type of calculation is performed. * 'frequency' is treated as a not-to-exceed value. */ @@ -1785,10 +1785,10 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) /* Save the new prescaler value (minus one) */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK); regval |= (prescaler - 1) << QSPI_CR_PRESCALER_SHIFT; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Calculate the new actual frequency */ @@ -1850,7 +1850,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) * 3 1 1 */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR); regval &= ~(QSPI_DCR_CKMODE); switch (mode) @@ -1870,7 +1870,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) return; } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR); spiinfo("DCR=%08" PRIx32 "\n", regval); /* Save the mode so that subsequent re-configurations will be faster */ @@ -1957,9 +1957,9 @@ static int qspi_command(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -1983,16 +1983,16 @@ static int qspi_command(struct qspi_dev_s *dev, * Complete' interrupts. */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2002,15 +2002,15 @@ static int qspi_command(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer * Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } } else @@ -2023,9 +2023,9 @@ static int qspi_command(struct qspi_dev_s *dev, /* Enable 'Transfer Error' and 'Transfer Complete' interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2139,9 +2139,9 @@ static int qspi_memory(struct qspi_dev_s *dev, qspi_putreg(priv, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, - STM32L4_QUADSPI_FCR); + STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2163,16 +2163,16 @@ static int qspi_memory(struct qspi_dev_s *dev, * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } else { uint32_t regval; uint32_t addrval; - addrval = qspi_getreg(priv, STM32L4_QUADSPI_AR_OFFSET); + addrval = qspi_getreg(priv, STM32_QUADSPI_AR_OFFSET); /* Set up the Communications Configuration Register as per command * info @@ -2182,15 +2182,15 @@ static int qspi_memory(struct qspi_dev_s *dev, /* Start the transfer by re-writing the address in AR register */ - qspi_putreg(priv, addrval, STM32L4_QUADSPI_AR_OFFSET); + qspi_putreg(priv, addrval, STM32_QUADSPI_AR_OFFSET); /* Enable 'Transfer Error' 'FIFO Threshhold' and 'Transfer Complete' * interrupts */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TEIE | QSPI_CR_FTIE | QSPI_CR_TCIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* Wait for the interrupt routine to finish it's magic */ @@ -2356,7 +2356,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval = 0; regval &= ~(QSPI_CR_EN); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2364,7 +2364,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Disable all interrupt sources for starters */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE); @@ -2373,7 +2373,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval &= ~(QSPI_CR_FTHRES_MASK); regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2381,15 +2381,15 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) /* Configure QSPI Clock Prescaler and Sample Shift */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~(QSPI_CR_PRESCALER_MASK | QSPI_CR_SSHIFT); regval |= (0x01 << QSPI_CR_PRESCALER_SHIFT); regval |= (0x00); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Configure QSPI Flash Size, CS High Time and Clock Mode */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_DCR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); @@ -2406,13 +2406,13 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) regval |= ((nlog2size - 1) << QSPI_DCR_FSIZE_SHIFT); } - qspi_putreg(priv, regval, STM32L4_QUADSPI_DCR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET); /* Enable QSPI */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= QSPI_CR_EN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); /* Wait till BUSY flag reset */ @@ -2467,18 +2467,18 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Enable clocking to the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); regval |= RCC_AHB3ENR_QSPIEN; - putreg32(regval, STM32L4_RCC_AHB3ENR); - regval = getreg32(STM32L4_RCC_AHB3ENR); + putreg32(regval, STM32_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); /* Reset the QSPI peripheral */ - regval = getreg32(STM32L4_RCC_AHB3RSTR); + regval = getreg32(STM32_RCC_AHB3RSTR); regval |= RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); regval &= ~RCC_AHB3RSTR_QSPIRST; - putreg32(regval, STM32L4_RCC_AHB3RSTR); + putreg32(regval, STM32_RCC_AHB3RSTR); /* Configure multiplexed pins as connected on the board. */ @@ -2515,7 +2515,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) } #endif -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2541,7 +2541,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2549,7 +2549,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: @@ -2614,32 +2614,32 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * CS if memory is not accessed for a while) */ - qspi_putreg(priv, lpto, STM32L4_QUADSPI_LPTR_OFFSET); + qspi_putreg(priv, lpto, STM32_QUADSPI_LPTR_OFFSET); /* Clear Timeout interrupt */ - qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32L4_QUADSPI_FCR); + qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval |= (QSPI_CR_TCEN | QSPI_CR_TOIE); - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); #endif } else { - regval = qspi_getreg(priv, STM32L4_QUADSPI_CR_OFFSET); + regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_TCEN; - qspi_putreg(priv, regval, STM32L4_QUADSPI_CR_OFFSET); + qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); } /* create a transaction object */ qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef STM32L4_QSPI_INTERRUPTS +#ifdef STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index f59a6be1753..04af2e8fcfe 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -108,14 +108,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l4_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L4_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L4_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -128,19 +128,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L4_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L4_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L4_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l4_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 29c8257c00b..e17ed34b7b1 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -88,10 +88,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCO_MASK); regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 142890ddad9..c5480f1af84 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -93,7 +93,7 @@ static int stm32l4_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32L4_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -113,24 +113,24 @@ static void stm32l4_rngenable(void) /* Enable generation and interrupts */ - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval |= RNG_CR_RNGEN; regval |= RNG_CR_IE; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); - up_enable_irq(STM32L4_IRQ_RNG); + up_enable_irq(STM32_IRQ_RNG); } static void stm32l4_rngdisable(void) { uint32_t regval; - up_disable_irq(STM32L4_IRQ_RNG); + up_disable_irq(STM32_IRQ_RNG); - regval = getreg32(STM32L4_RNG_CR); + regval = getreg32(STM32_RNG_CR); regval &= ~RNG_CR_IE; regval &= ~RNG_CR_RNGEN; - putreg32(regval, STM32L4_RNG_CR); + putreg32(regval, STM32_RNG_CR); } static int stm32l4_rnginterrupt(int irq, void *context, void *arg) @@ -138,12 +138,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) uint32_t rngsr; uint32_t data; - rngsr = getreg32(STM32L4_RNG_SR); + rngsr = getreg32(STM32_RNG_SR); if (rngsr & RNG_SR_CEIS) /* Check for clock error int stat */ { /* Clear it, we will try again. */ - putreg32(rngsr & ~RNG_SR_CEIS, STM32L4_RNG_SR); + putreg32(rngsr & ~RNG_SR_CEIS, STM32_RNG_SR); return OK; } @@ -153,12 +153,12 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) /* Clear seed error, then disable/enable the rng and try again. */ - putreg32(rngsr & ~RNG_SR_SEIS, STM32L4_RNG_SR); - crval = getreg32(STM32L4_RNG_CR); + putreg32(rngsr & ~RNG_SR_SEIS, STM32_RNG_SR); + crval = getreg32(STM32_RNG_CR); crval &= ~RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); crval |= RNG_CR_RNGEN; - putreg32(crval, STM32L4_RNG_CR); + putreg32(crval, STM32_RNG_CR); return OK; } @@ -169,7 +169,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) return OK; } - data = getreg32(STM32L4_RNG_DR); + data = getreg32(STM32_RNG_DR); /* As required by the FIPS PUB (Federal Information Processing Standard * Publication) 140-2, the first random number generated after setting the diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 17cd5e349f3..bc554c7564b 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -142,23 +142,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32L4_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_WUTR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBSSR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -220,8 +220,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(0xca, STM32L4_RTC_WPR); - putreg32(0x53, STM32L4_RTC_WPR); + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); } /**************************************************************************** @@ -242,7 +242,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32L4_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -272,16 +272,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -316,21 +316,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32L4_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -360,9 +360,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -434,13 +434,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 18 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI1_RTC_ALARM, STM32L4_EXTI1_PR); + putreg32(EXTI1_RTC_ALARM, STM32_EXTI1_PR); #endif } @@ -478,10 +478,10 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -500,17 +500,17 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32L4_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -529,9 +529,9 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -574,7 +574,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -600,7 +600,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -639,12 +639,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -656,13 +656,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32L4_RTC_ALRMAR); - putreg32(0, STM32L4_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -682,12 +682,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32L4_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32L4_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -699,13 +699,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32L4_RTC_ALRMBR); - putreg32(0, STM32L4_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32L4_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32L4_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -870,13 +870,13 @@ int up_rtc_initialize(void) stm32l4_pwr_enablebkp(true); #if defined(CONFIG_STM32L4_RTC_HSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); #elif defined(CONFIG_STM32L4_RTC_LSICLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); #elif defined(CONFIG_STM32L4_RTC_LSECLOCK) - modifyreg32(STM32L4_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -884,7 +884,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32L4_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -912,9 +912,9 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ @@ -930,7 +930,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #elif defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) @@ -938,13 +938,13 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32L4_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1038,18 +1038,18 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32L4_RTC_DR); - tr = getreg32(STM32L4_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); #ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32L4_RTC_SSR); - tmp = getreg32(STM32L4_RTC_TR); + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32L4_RTC_DR); + tmp = getreg32(STM32_RTC_DR); if (tmp == dr) { break; @@ -1108,7 +1108,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32L4_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1255,8 +1255,8 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32L4_RTC_TR); - putreg32(dr, STM32L4_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1452,7 +1452,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1462,8 +1462,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMAR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(-1, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1483,7 +1483,7 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32L4_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1493,8 +1493,8 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(-1, STM32L4_RTC_ALRMBR); - modifyreg32(STM32L4_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(-1, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1541,7 +1541,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32L4_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1550,7 +1550,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32L4_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32l4_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1588,9 +1588,9 @@ static int stm32l4_rtc_wakeup_handler(int irq, void *context, stm32l4_pwr_enablebkp(true); - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32l4_pwr_enablebkp(false); @@ -1636,10 +1636,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1675,7 +1675,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32L4_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32L4_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1713,9 +1713,9 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1724,7 +1724,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1748,7 +1748,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32L4_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1769,17 +1769,17 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32L4_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32L4_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1811,9 +1811,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32L4_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32L4_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1822,7 +1822,7 @@ int stm32l4_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32L4_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1834,9 +1834,9 @@ int stm32l4_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32L4_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32L4_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index b89807b7c07..7a202e90d22 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -38,8 +38,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ -#define STM32L4_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ #if !defined(CONFIG_STM32L4_RTC_MAGIC) # define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) @@ -55,7 +55,7 @@ #define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32L4_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index bac80beef62..27e3aaabfc0 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32L4_NALARMS]; + struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 5344b764b36..f30d0564e79 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -233,9 +233,9 @@ static const struct i2s_ops_s g_i2sops = static struct stm32l4_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_A_BASE, + .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -254,9 +254,9 @@ static struct stm32l4_sai_s g_sai1a_priv = static struct stm32l4_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI1_B_BASE, + .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI1_FREQUENCY, + .frequency = STM32_SAI1_FREQUENCY, #ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -277,9 +277,9 @@ static struct stm32l4_sai_s g_sai1b_priv = static struct stm32l4_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_A_BASE, + .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -298,9 +298,9 @@ static struct stm32l4_sai_s g_sai2a_priv = static struct stm32l4_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, - .base = STM32L4_SAI2_B_BASE, + .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, - .frequency = STM32L4_SAI2_FREQUENCY, + .frequency = STM32_SAI2_FREQUENCY, #ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else @@ -433,14 +433,14 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) i2sinfo("CR1:%08" PRIx32 " CR2:%08" PRIx32 " FRCR:%08" PRIx32 " SLOTR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_CR1_OFFSET), - sai_getreg(priv, STM32L4_SAI_CR2_OFFSET), - sai_getreg(priv, STM32L4_SAI_FRCR_OFFSET), - sai_getreg(priv, STM32L4_SAI_SLOTR_OFFSET)); + sai_getreg(priv, STM32_SAI_CR1_OFFSET), + sai_getreg(priv, STM32_SAI_CR2_OFFSET), + sai_getreg(priv, STM32_SAI_FRCR_OFFSET), + sai_getreg(priv, STM32_SAI_SLOTR_OFFSET)); i2sinfo(" IM:%08" PRIx32 " SR:%08" PRIx32 " CLRFR:%08" PRIx32 "\n", - sai_getreg(priv, STM32L4_SAI_IM_OFFSET), - sai_getreg(priv, STM32L4_SAI_SR_OFFSET), - sai_getreg(priv, STM32L4_SAI_CLRFR_OFFSET)); + sai_getreg(priv, STM32_SAI_IM_OFFSET), + sai_getreg(priv, STM32_SAI_SR_OFFSET), + sai_getreg(priv, STM32_SAI_CLRFR_OFFSET)); } #endif @@ -474,7 +474,7 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) mckdiv = priv->frequency / (priv->samplerate * 2 * 256); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MCKDIV_MASK, mckdiv << SAI_CR1_MCKDIV_SHIFT); } @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32L4_SAI_DR_OFFSET, + stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -634,7 +634,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Enable the transmitter */ - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_SAIEN); /* Start a watchdog to catch DMA timeouts */ @@ -901,9 +901,9 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) return 0; } - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_DS_MASK, setbits); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSALL_MASK | SAI_FRCR_FRL_MASK, SAI_FRCR_FSALL(bits) | SAI_FRCR_FRL(bits * 2)); @@ -981,7 +981,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_RX : SAI_CR1_MODE_MASTER_RX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->rxenab = true; /* Add a reference to the audio buffer */ @@ -1086,7 +1086,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } mode = priv->syncen ? SAI_CR1_MODE_SLAVE_TX : SAI_CR1_MODE_MASTER_TX; - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_MODE_MASK, mode); priv->txenab = true; /* Add a reference to the audio buffer */ @@ -1275,21 +1275,21 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) priv->dma = stm32l4_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); #endif - sai_modifyreg(priv, STM32L4_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, + sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, SAI_CR1_SYNCEN_MASK, priv->syncen); - sai_modifyreg(priv, STM32L4_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, + sai_modifyreg(priv, STM32_SAI_CR2_OFFSET, SAI_CR2_FTH_MASK, SAI_CR2_FTH_1QF); - sai_modifyreg(priv, STM32L4_SAI_FRCR_OFFSET, + sai_modifyreg(priv, STM32_SAI_FRCR_OFFSET, SAI_FRCR_FSDEF | SAI_FRCR_FSPOL | SAI_FRCR_FSOFF, SAI_FRCR_FSDEF_CHID | SAI_FRCR_FSPOL_LOW | SAI_FRCR_FSOFF_BFB); - sai_modifyreg(priv, STM32L4_SAI_SLOTR_OFFSET, + sai_modifyreg(priv, STM32_SAI_SLOTR_OFFSET, SAI_SLOTR_NBSLOT_MASK | SAI_SLOTR_SLOTEN_MASK, SAI_SLOTR_NBSLOT(2) | SAI_SLOTR_SLOTEN_0 | SAI_SLOTR_SLOTEN_1); diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index 49e54607c34..c1a1de20f1b 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -561,8 +561,8 @@ struct stm32_dev_s g_sdmmcdev1 = #endif #endif }, - .base = STM32L4_SDMMC1_BASE, - .nirq = STM32L4_IRQ_SDMMC1, + .base = STM32_SDMMC1_BASE, + .nirq = STM32_IRQ_SDMMC1, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index bf78be0ddf8..084ae78ac50 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -467,13 +467,13 @@ static struct stm32l4_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L4_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -529,13 +529,13 @@ static struct stm32l4_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L4_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L4_PCLK2_FREQUENCY, - .usartbase = STM32L4_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -591,13 +591,13 @@ static struct stm32l4_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L4_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -653,13 +653,13 @@ static struct stm32l4_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L4_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -715,7 +715,7 @@ static struct stm32l4_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L4_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -728,8 +728,8 @@ static struct stm32l4_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -777,7 +777,7 @@ static struct stm32l4_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L4_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -790,8 +790,8 @@ static struct stm32l4_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L4_PCLK1_FREQUENCY, - .usartbase = STM32L4_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -814,7 +814,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l4_serial_s * -const g_uart_devs[STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -891,15 +891,15 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * enable/usage table above) */ - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - cr3 = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1035,8 +1035,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - brr = stm32l4serial_getreg(priv, STM32L4_USART_BRR_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32l4serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -1062,8 +1062,8 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -1099,7 +1099,7 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32l4serial_putreg(priv, STM32L4_USART_BRR_OFFSET, brr); + stm32l4serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -1122,7 +1122,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L4_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { stm32l4serial_setbaud_lpuart(priv); } @@ -1134,7 +1134,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1172,11 +1172,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1184,11 +1184,11 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) @@ -1205,7 +1205,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1250,7 +1250,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + while ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1356,7 +1356,7 @@ static void stm32l4serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -1396,39 +1396,39 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER - case STM32L4_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L4_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32L4_USART1_SERIALDRIVER - case STM32L4_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L4_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L4_USART2_SERIALDRIVER - case STM32L4_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_USART3_SERIALDRIVER - case STM32L4_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART4_SERIALDRIVER - case STM32L4_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L4_UART5_SERIALDRIVER - case STM32L4_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L4_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1515,7 +1515,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1526,26 +1526,26 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1553,9 +1553,9 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1608,7 +1608,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1619,7 +1619,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1633,9 +1633,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1693,9 +1693,9 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + regval = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, regval); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1859,7 +1859,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1931,7 +1931,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2002,19 +2002,19 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR3_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -2050,11 +2050,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l4serial_putreg(priv, STM32L4_USART_CR3_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2071,17 +2071,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2101,11 +2101,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2122,17 +2122,17 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l4serial_getreg(priv, STM32L4_USART_CR2_OFFSET); + uint32_t cr = stm32l4serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2143,11 +2143,11 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l4serial_putreg(priv, STM32L4_USART_CR2_OFFSET, cr); + stm32l4serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2304,8 +2304,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2317,8 +2317,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l4serial_getreg(priv, STM32L4_USART_CR1_OFFSET); - stm32l4serial_putreg(priv, STM32L4_USART_CR1_OFFSET, + cr1 = stm32l4serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l4serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2354,7 +2354,7 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l4serial_getreg(priv, STM32L4_USART_RDR_OFFSET); + rdr = stm32l4serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2444,7 +2444,7 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2607,7 +2607,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2618,7 +2618,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l4_dmasetup(priv->rxdma, - priv->usartbase + STM32L4_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2787,7 +2787,7 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l4serial_putreg(priv, STM32L4_USART_TDR_OFFSET, (uint32_t)ch); + stm32l4serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2875,7 +2875,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) { struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; - return ((stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET) & + return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2918,11 +2918,11 @@ static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l4serial_getreg(priv, STM32L4_USART_ISR_OFFSET); + priv->sr = stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l4serial_putreg(priv, STM32L4_USART_ICR_OFFSET, + stm32l4serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -3058,7 +3058,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l4_serial_s *priv = g_uart_devs[n]; @@ -3128,7 +3128,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3197,7 +3197,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L4_NLPUART + STM32L4_NUSART + STM32L4_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index b53213580ea..c2864c40c2c 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -285,10 +285,10 @@ static struct stm32l4_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L4_SPI1_BASE, - .spiclock = STM32L4_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32L4_SPI_DMA /* lines must be configured in board.h */ @@ -343,10 +343,10 @@ static struct stm32l4_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L4_SPI2_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -399,10 +399,10 @@ static struct stm32l4_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L4_SPI3_BASE, - .spiclock = STM32L4_PCLK1_FREQUENCY, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L4_SPI_INTERRUPTS - .spiirq = STM32L4_IRQ_SPI3, + .spiirq = STM32_IRQ_SPI3, #endif #ifdef CONFIG_STM32L4_SPI_DMA .rxch = DMACHAN_SPI3_RX, @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L4_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L4_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L4_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L4_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32L4_SPI_DR_OFFSET, + stm32l4_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -985,11 +985,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L4_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L4_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L4_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1055,9 +1055,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1127,9 +1127,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1193,9 +1193,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1248,9 +1248,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1316,7 +1316,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L4_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1738,11 +1738,11 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1754,7 +1754,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L4_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32L4_SPI_DMA /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA @@ -1769,13 +1769,13 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) priv->txdma = stm32l4_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L4_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L4_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 64aacd7fc9a..cda08e167a4 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -60,8 +60,8 @@ * the stack + 4; */ -#define SRAM2_START STM32L4_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 6facb4e747f..24776426fab 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -309,16 +309,16 @@ static const struct stm32l4_tim_ops_s stm32l4_tim_ops = struct stm32l4_tim_priv_s stm32l4_tim1_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM2 struct stm32l4_tim_priv_s stm32l4_tim2_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -326,8 +326,8 @@ struct stm32l4_tim_priv_s stm32l4_tim2_priv = struct stm32l4_tim_priv_s stm32l4_tim3_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -335,8 +335,8 @@ struct stm32l4_tim_priv_s stm32l4_tim3_priv = struct stm32l4_tim_priv_s stm32l4_tim4_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -344,8 +344,8 @@ struct stm32l4_tim_priv_s stm32l4_tim4_priv = struct stm32l4_tim_priv_s stm32l4_tim5_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -353,8 +353,8 @@ struct stm32l4_tim_priv_s stm32l4_tim5_priv = struct stm32l4_tim_priv_s stm32l4_tim6_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -362,8 +362,8 @@ struct stm32l4_tim_priv_s stm32l4_tim6_priv = struct stm32l4_tim_priv_s stm32l4_tim7_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -371,8 +371,8 @@ struct stm32l4_tim_priv_s stm32l4_tim7_priv = struct stm32l4_tim_priv_s stm32l4_tim8_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -380,8 +380,8 @@ struct stm32l4_tim_priv_s stm32l4_tim8_priv = struct stm32l4_tim_priv_s stm32l4_tim15_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -389,8 +389,8 @@ struct stm32l4_tim_priv_s stm32l4_tim15_priv = struct stm32l4_tim_priv_s stm32l4_tim16_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -398,8 +398,8 @@ struct stm32l4_tim_priv_s stm32l4_tim16_priv = struct stm32l4_tim_priv_s stm32l4_tim17_priv = { .ops = &stm32l4_tim_ops, - .mode = STM32L4_TIM_MODE_UNUSED, - .base = STM32L4_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -487,9 +487,9 @@ static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_EGR_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32L4_GTIM_EGR_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -498,11 +498,11 @@ static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -511,9 +511,9 @@ static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET); + uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -527,7 +527,7 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_DISABLED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l4_tim_disable(dev); } @@ -547,7 +547,7 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, * Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L4_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l4_configgpio(cfg); } @@ -567,42 +567,42 @@ static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DIER_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCMR2_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_ARR_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_CCR4_OFFSET) + stm32l4_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); - if (priv->base == STM32L4_TIM1_BASE || priv->base == STM32L4_TIM8_BASE) + if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_ATIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32L4_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32L4_GTIM_DMAR_OFFSET)); + stm32l4_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32l4_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } @@ -621,13 +621,13 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -636,21 +636,21 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L4_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L4_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L4_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val &= ~GTIM_CR1_DIR; break; - case STM32L4_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: @@ -659,7 +659,7 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, break; - case STM32L4_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -668,15 +668,15 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32L4_GTIM_CR1_OFFSET, val); + stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L4_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM8_BASE) + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32L4_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l4_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -714,66 +714,66 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -838,8 +838,8 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32L4_GTIM_ARR_OFFSET, reload); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32l4_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -873,66 +873,66 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -963,7 +963,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32L4_GTIM_PSC_OFFSET, prescaler); + stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } @@ -987,64 +987,64 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -1054,7 +1054,7 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32L4_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -1066,7 +1066,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32L4_GTIM_ARR_OFFSET, period); + stm32l4_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -1076,7 +1076,7 @@ static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32L4_GTIM_ARR_OFFSET); + return stm32l4_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -1086,7 +1086,7 @@ static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32L4_GTIM_CNT_OFFSET); + uint32_t counter = stm32l4_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -1096,10 +1096,10 @@ static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -1123,7 +1123,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L4_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32L4_GTIM_CCER_OFFSET); + ccer_val = stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1144,13 +1144,13 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L4_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L4_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32L4_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L4_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -1159,12 +1159,12 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L4_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L4_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L4_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -1176,7 +1176,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L4_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -1191,21 +1191,21 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L4_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32L4_GTIM_CCER_OFFSET, ccer_val); + stm32l4_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1238,7 +1238,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1271,7 +1271,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1304,7 +1304,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1336,7 +1336,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1369,7 +1369,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1402,7 +1402,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1435,7 +1435,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1468,7 +1468,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR1_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR2_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR3_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32L4_GTIM_CCR4_OFFSET, compare); + stm32l4_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1554,16 +1554,16 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR1_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR2_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR3_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32L4_GTIM_CCR4_OFFSET); + return stm32l4_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1584,66 +1584,66 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - vectorno = STM32L4_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - vectorno = STM32L4_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - vectorno = STM32L4_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - vectorno = STM32L4_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - vectorno = STM32L4_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - vectorno = STM32L4_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - vectorno = STM32L4_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - vectorno = STM32L4_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - vectorno = STM32L4_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - vectorno = STM32L4_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - vectorno = STM32L4_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1676,7 +1676,7 @@ static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1687,7 +1687,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32L4_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1696,7 +1696,7 @@ static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32L4_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l4_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1706,7 +1706,7 @@ static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32L4_GTIM_SR_OFFSET); + uint16_t regval = stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1729,76 +1729,76 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) #ifdef CONFIG_STM32L4_TIM1 case 1: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L4_TIM2 case 2: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L4_TIM3 case 3: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L4_TIM4 case 4: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L4_TIM5 case 5: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L4_TIM6 case 6: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L4_TIM7 case 7: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; - modifyreg32(STM32L4_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L4_TIM8 case 8: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L4_TIM15 case 15: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L4_TIM16 case 16: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L4_TIM17 case 17: dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; - modifyreg32(STM32L4_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,7 +1808,7 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32L4_TIM_MODE_UNUSED) + if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1834,67 +1834,67 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) switch (((struct stm32l4_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 - case STM32L4_TIM1_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM2 - case STM32L4_TIM2_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM3 - case STM32L4_TIM3_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM4 - case STM32L4_TIM4_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM5 - case STM32L4_TIM5_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM6 - case STM32L4_TIM6_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM7 - case STM32L4_TIM7_BASE: - modifyreg32(STM32L4_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM8 - case STM32L4_TIM8_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM15 - case STM32L4_TIM15_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM16 - case STM32L4_TIM16_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32L4_TIM17 - case STM32L4_TIM17_BASE: - modifyreg32(STM32L4_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1904,7 +1904,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32L4_TIM_MODE_UNUSED; + ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 06a800a3519..338ca644aa2 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -38,24 +38,24 @@ /* Helpers ******************************************************************/ -#define STM32L4_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L4_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32L4_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L4_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L4_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L4_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L4_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L4_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L4_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L4_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L4_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L4_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L4_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L4_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L4_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32L4_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32L4_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32L4_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -83,34 +83,34 @@ struct stm32l4_tim_dev_s enum stm32l4_tim_mode_e { - STM32L4_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L4_TIM_MODE_MASK = 0x0310, - STM32L4_TIM_MODE_DISABLED = 0x0000, - STM32L4_TIM_MODE_UP = 0x0100, - STM32L4_TIM_MODE_DOWN = 0x0110, - STM32L4_TIM_MODE_UPDOWN = 0x0200, - STM32L4_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L4_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L4_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L4_TIM_MODE_CK_EXT = 0x0800, - STM32L4_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L4_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L4_TIM_MODE_CK_CH1 = 0x0001, - STM32L4_TIM_MODE_CK_CH2 = 0x0002, - STM32L4_TIM_MODE_CK_CH3 = 0x0003, - STM32L4_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -120,32 +120,32 @@ enum stm32l4_tim_mode_e enum stm32l4_tim_channel_e { - STM32L4_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L4_TIM_CH_POLARITY_POS = 0x00, - STM32L4_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L4_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L4_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32L4_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L4_TIM_CH_INCAPTURE = 0x10, - STM32L4_TIM_CH_INPWM = 0x20 - STM32L4_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 0f2d6376b29..35f42694a4a 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -71,17 +71,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L4_TIM1_RES 16 -#define STM32L4_TIM2_RES 32 -#define STM32L4_TIM3_RES 16 -#define STM32L4_TIM4_RES 16 -#define STM32L4_TIM5_RES 32 -#define STM32L4_TIM6_RES 16 -#define STM32L4_TIM7_RES 16 -#define STM32L4_TIM8_RES 16 -#define STM32L4_TIM15_RES 16 -#define STM32L4_TIM16_RES 16 -#define STM32L4_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -141,7 +141,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -149,7 +149,7 @@ static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -157,7 +157,7 @@ static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -165,7 +165,7 @@ static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -173,7 +173,7 @@ static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -181,7 +181,7 @@ static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -189,7 +189,7 @@ static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -197,7 +197,7 @@ static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -205,7 +205,7 @@ static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -213,7 +213,7 @@ static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -221,7 +221,7 @@ static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L4_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -247,13 +247,13 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) (struct stm32l4_lowerhalf_s *) arg; uint32_t next_interval_us = 0; - STM32L4_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L4_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -286,12 +286,12 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -325,9 +325,9 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L4_TIM_SETMODE(priv->tim, STM32L4_TIM_MODE_DISABLED); - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -382,8 +382,8 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L4_TIM_GETCLOCK(priv->tim); - period = STM32L4_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -399,7 +399,7 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L4_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -436,13 +436,13 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L4_TIM_SETCLOCK(priv->tim, freq); - STM32L4_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L4_TIM_SETCLOCK(priv->tim, 1000000); - STM32L4_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -482,13 +482,13 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L4_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); - STM32L4_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L4_TIM_DISABLEINT(priv->tim, 0); - STM32L4_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index 1a37a689243..d943d75bb3d 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -58,9 +58,9 @@ /* And I don't know now to re-configure it yet */ #ifdef CONFIG_STM32L4_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L4_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L4_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); /* Enable SysTick interrupts */ @@ -143,5 +143,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L4_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c index ef9d52da064..eb955770cb6 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32l4_memorymap.h" #include "stm32l4_uid.h" -#ifdef STM32L4_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32l4_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L4_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32L4_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index f3424f388a3..2df8f8bd83f 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -75,17 +75,17 @@ /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ -#define STM32L4_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) +#define STM32_CNTR_SETUP (USB_CNTR_RESETM|USB_CNTR_SUSPM|USB_CNTR_CTRM) /* Endpoint identifiers. The STM32L4 supports up to 16 mono-directional or 8 * bidirectional endpoints. However, when you take into account PMA buffer * usage (see below) and the fact that EP0 is bidirectional, then there is * a functional limitation of EP0 + 5 mono-directional endpoints = 6. We'll - * define STM32L4_NENDPOINTS to be 8, however, because that is how many + * define STM32_NENDPOINTS to be 8, however, because that is how many * endpoint register sets there are. */ -#define STM32L4_NENDPOINTS (8) +#define STM32_NENDPOINTS (8) #define EP0 (0) #define EP1 (1) #define EP2 (2) @@ -95,47 +95,47 @@ #define EP6 (6) #define EP7 (7) -#define STM32L4_ENDP_BIT(ep) (1 << (ep)) -#define STM32L4_ENDP_ALLSET 0xff +#define STM32_ENDP_BIT(ep) (1 << (ep)) +#define STM32_ENDP_ALLSET 0xff /* Packet sizes. We us a fixed 64 max packet size for all endpoint types */ -#define STM32L4_MAXPACKET_SHIFT (6) -#define STM32L4_MAXPACKET_SIZE (1 << (STM32L4_MAXPACKET_SHIFT)) -#define STM32L4_MAXPACKET_MASK (STM32L4_MAXPACKET_SIZE-1) +#define STM32_MAXPACKET_SHIFT (6) +#define STM32_MAXPACKET_SIZE (1 << (STM32_MAXPACKET_SHIFT)) +#define STM32_MAXPACKET_MASK (STM32_MAXPACKET_SIZE-1) -#define STM32L4_EP0MAXPACKET STM32L4_MAXPACKET_SIZE +#define STM32_EP0MAXPACKET STM32_MAXPACKET_SIZE /* Buffer descriptor table. * The buffer table is positioned at the beginning of the 1024-byte - * USB memory. We will use the first STM32L4_NENDPOINTS*8 bytes for + * USB memory. We will use the first STM32_NENDPOINTS*8 bytes for * the buffer table. That is exactly 64 bytes, leaving 15*64 bytes for * endpoint buffers. */ -#define STM32L4_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB +#define STM32_BTABLE_ADDRESS (0x00) /* Start at the beginning of USB * RAM */ -#define STM32L4_DESC_SIZE (8) /* Each descriptor is 4*2=8 +#define STM32_DESC_SIZE (8) /* Each descriptor is 4*2=8 * bytes in size */ -#define STM32L4_BTABLE_SIZE (STM32L4_NENDPOINTS*STM32L4_DESC_SIZE) +#define STM32_BTABLE_SIZE (STM32_NENDPOINTS*STM32_DESC_SIZE) /* Buffer layout. Assume that all buffers are 64-bytes (maxpacketsize), * then we have space for only 7 buffers; endpoint 0 will require two * buffers, leaving 5 for other endpoints. */ -#define STM32L4_BUFFER_START STM32L4_BTABLE_SIZE -#define STM32L4_EP0_RXADDR STM32L4_BUFFER_START -#define STM32L4_EP0_TXADDR (STM32L4_EP0_RXADDR+STM32L4_EP0MAXPACKET) +#define STM32_BUFFER_START STM32_BTABLE_SIZE +#define STM32_EP0_RXADDR STM32_BUFFER_START +#define STM32_EP0_TXADDR (STM32_EP0_RXADDR+STM32_EP0MAXPACKET) -#define STM32L4_BUFFER_EP0 0x03 -#define STM32L4_NBUFFERS 7 -#define STM32L4_BUFFER_BIT(bn) (1 << (bn)) -#define STM32L4_BUFFER_ALLSET 0x7f -#define STM32L4_BUFNO2BUF(bn) (STM32L4_BUFFER_START+((bn)<ep.eplog)); /* Save the result in the request structure */ @@ -1333,7 +1333,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, * requests to send. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINQEMPTY), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINQEMPTY), 0); return -ENOENT; } @@ -1449,7 +1449,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUTDATA), readlen); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); stm32l4_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ @@ -1482,7 +1482,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, * soon. */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTQEMPTY), epno); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTQEMPTY), epno); return -ENOENT; } @@ -1493,7 +1493,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPOUTNULLPACKET), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); stm32l4_reqcomplete(privep, OK); return OK; } @@ -1556,7 +1556,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { int ret; - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_DISPATCH), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); if (priv && priv->driver) { /* Forward to the control request to the class driver implementation */ @@ -1567,7 +1567,7 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) { /* Stall on failure */ - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DISPATCHSTALL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1584,7 +1584,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32L4_USB_EPR(epno)); + epr = stm32l4_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1594,7 +1594,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTDONE), epr); /* Handle read requests. First check if a read request is available to * accept the host data. @@ -1618,7 +1618,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) if (stm32l4_rqempty(privep)) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPOUTPENDING), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); /* Mark the RX processing as pending and NAK any OUT actions @@ -1648,7 +1648,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear interrupt status */ stm32l4_clrepctrtx(epno); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPINDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ @@ -1678,7 +1678,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set address in every allocated endpoint */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { if (stm32l4_epreserved(priv, epno)) { @@ -1688,7 +1688,7 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32L4_USB_DADDR); + stm32l4_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** @@ -1755,7 +1755,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (USB_REQ_ISOUT(priv->ctrl.type) && len.w > 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPOUT), len.w); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUT), len.w); /* At this point priv->ctrl is the setup packet. */ @@ -1772,7 +1772,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if ((priv->ctrl.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_NOSTDREQ), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_NOSTDREQ), priv->ctrl.type); /* Let the class implementation handle all non-standar requests */ @@ -1795,12 +1795,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 2; data = status */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), priv->ctrl.type); if (len.w != 2 || (priv->ctrl.type & USB_REQ_DIR_IN) == 0 || index.b[MSB] != 0 || value.w != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } else @@ -1810,12 +1810,12 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_ENDPOINT: { epno = USB_EPNO(index.b[LSB]); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EPGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), epno); - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADEPGETSTATUS), + STM32_TRACEERR_BADEPGETSTATUS), epno); priv->ep0state = EP0STATE_STALLED; } @@ -1855,7 +1855,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) if (index.w == 0) { usbtrace(TRACE_INTDECODE( - STM32L4_TRACEINTID_DEVGETSTATUS), + STM32_TRACEINTID_DEVGETSTATUS), 0); /* Features: Remote Wakeup=YES; selfpowered=? */ @@ -1869,7 +1869,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) else { usbtrace(TRACE_DEVERROR( - STM32L4_TRACEERR_BADDEVGETSTATUS), + STM32_TRACEERR_BADDEVGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1878,7 +1878,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) case USB_REQ_RECIPIENT_INTERFACE: { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_IFGETSTATUS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); response.w = 0; nbytes = 2; /* Response size: 2 bytes */ @@ -1887,7 +1887,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETSTATUS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); priv->ep0state = EP0STATE_STALLED; } break; @@ -1904,7 +1904,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: zero, data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_CLEARFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_ENDPOINT) @@ -1921,7 +1921,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Endpoint recipient */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1930,7 +1930,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADCLEARFEATURE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } @@ -1946,7 +1946,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETFEATURE), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), priv->ctrl.type); if (((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) && value.w == USB_FEATURE_TESTMODE) @@ -1970,7 +1970,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Handler recipient=endpoint */ epno = USB_EPNO(index.b[LSB]); - if (epno < STM32L4_NENDPOINTS && index.b[MSB] == 0 && + if (epno < STM32_NENDPOINTS && index.b[MSB] == 0 && value.w == USB_FEATURE_ENDPOINTHALT && len.w == 0) { privep = &priv->eplist[epno]; @@ -1979,7 +1979,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETFEATURE), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -1994,13 +1994,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * len: 0; data = none */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPSETADDRESS), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPSETADDRESS), value.w); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) != USB_REQ_RECIPIENT_DEVICE || index.w != 0 || len.w != 0 || value.w > 127) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETADDRESS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); priv->ep0state = EP0STATE_STALLED; } @@ -2026,7 +2026,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETDESC), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), priv->ctrl.type); /* The request seems valid... @@ -2046,7 +2046,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && @@ -2061,7 +2061,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADGETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2075,7 +2075,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SETCONFIG), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), priv->ctrl.type); if ((priv->ctrl.type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && index.w == 0 && len.w == 0) @@ -2089,7 +2089,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADSETCONFIG), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); priv->ep0state = EP0STATE_STALLED; } } @@ -2112,7 +2112,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* Let the class implementation handle the request */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_GETSETIF), + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); stm32l4_dispatchrequest(priv); handled = true; @@ -2127,13 +2127,13 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) */ { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SYNCHFRAME), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); } break; default: { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDCTRLREQ), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), priv->ctrl.req); priv->ep0state = EP0STATE_STALLED; } @@ -2288,7 +2288,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 IN: device-to-host (DIR=0) */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0IN), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2296,7 +2296,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32L4_USB_EPR(EP0)); + epr = stm32l4_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2304,7 +2304,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0INDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); stm32l4_clrepctrtx(EP0); stm32l4_ep0in(priv); } @@ -2315,7 +2315,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0SETUPDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0setup(priv); } @@ -2326,7 +2326,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_EP0OUTDONE), epr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); stm32l4_clrepctrrx(EP0); stm32l4_ep0out(priv); } @@ -2335,14 +2335,14 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0BADCTR), epr); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0BADCTR), epr); return; /* Does this ever happen? */ } } /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2359,7 +2359,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if (priv->ep0state == EP0STATE_STALLED) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EP0SETUPSTALLED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); priv->rxstatus = USB_EPR_STATRX_STALL; priv->txstatus = USB_EPR_STATTX_STALL; @@ -2394,9 +2394,9 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32L4_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32l4_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32L4_USB_ISTR); + stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2430,9 +2430,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) */ struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32L4_USB_ISTR); + uint16_t istr = stm32l4_getreg(STM32_USB_ISTR); - usbtrace(TRACE_INTENTRY(STM32L4_TRACEINTID_USBINTERRUPT), istr); + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); /* Handle Reset interrupts. When this event occurs, the peripheral is left * in the same conditions it is left by the system reset (but with the @@ -2443,8 +2443,8 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_RESET), istr); + stm32l4_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. @@ -2464,9 +2464,9 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_WKUP), - stm32l4_getreg(STM32L4_USB_FNR)); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), + stm32l4_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ @@ -2480,28 +2480,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_SUSP), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); stm32l4_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_ESOF), 0); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); stm32l4_esofpoll(priv); } @@ -2509,13 +2509,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Low priority endpoint correct transfer interrupt */ - usbtrace(TRACE_INTDECODE(STM32L4_TRACEINTID_USBCTR), istr); + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); stm32l4_lptransfer(priv); } out: - usbtrace(TRACE_INTEXIT(STM32L4_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32L4_USB_EP0R)); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), + stm32l4_getreg(STM32_USB_EP0R)); return OK; } @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2567,15 +2567,15 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) */ stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,9 +2586,9 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend @@ -2616,9 +2616,9 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ @@ -2626,7 +2626,7 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32L4_CNTR_SETUP, STM32L4_USB_CNTR); + stm32l4_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,9 +2666,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32L4_USB_CNTR); + regval = stm32l4_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32L4_USB_CNTR); + stm32l4_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable @@ -2677,7 +2677,7 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2711,9 +2711,9 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) * (skipping EP0) */ - for (epndx = 1; epndx < STM32L4_NENDPOINTS; epndx++) + for (epndx = 1; epndx < STM32_NENDPOINTS; epndx++) { - uint8_t bit = STM32L4_ENDP_BIT(epndx); + uint8_t bit = STM32_ENDP_BIT(epndx); if ((epset & bit) != 0) { /* Mark the endpoint no longer available */ @@ -2741,7 +2741,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(USB_EPNO(privep->ep.eplog)); + priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); leave_critical_section(flags); } @@ -2752,7 +2752,7 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, static inline bool stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) { - return ((priv->epavail & STM32L4_ENDP_BIT(epno)) == 0); + return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** @@ -2766,11 +2766,11 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) int bufndx; flags = enter_critical_section(); - for (bufndx = 2; bufndx < STM32L4_NBUFFERS; bufndx++) + for (bufndx = 2; bufndx < STM32_NBUFFERS; bufndx++) { /* Check if this buffer is available */ - uint8_t bit = STM32L4_BUFFER_BIT(bufndx); + uint8_t bit = STM32_BUFFER_BIT(bufndx); if ((priv->bufavail & bit) != 0) { /* Yes.. Mark the endpoint no longer available */ @@ -2796,7 +2796,7 @@ static inline void stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) { irqstate_t flags = enter_critical_section(); - priv->epavail |= STM32L4_ENDP_BIT(privep->bufno); + priv->epavail |= STM32_ENDP_BIT(privep->bufno); leave_critical_section(flags); } @@ -2821,7 +2821,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !desc) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p desc=%p\n", ep, desc); return -EINVAL; } @@ -2855,7 +2855,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, break; default: - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPTYPE), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPTYPE), (uint16_t)desc->type); return -EINVAL; } @@ -2865,12 +2865,12 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Get the address of the PMA buffer allocated for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - pma = STM32L4_BUFNO2BUF(privep->bufno); + pma = STM32_BUFNO2BUF(privep->bufno); /* Get the maxpacket size of the endpoint. */ maxpacket = GETUINT16(desc->mxpacketsize); - DEBUGASSERT(maxpacket <= STM32L4_MAXPACKET_SIZE); + DEBUGASSERT(maxpacket <= STM32_MAXPACKET_SIZE); ep->maxpacket = maxpacket; /* Get the subset matching the requested direction */ @@ -2918,7 +2918,7 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: ep=%p\n", ep); return -EINVAL; } @@ -2953,7 +2953,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_FEATURES if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -2963,7 +2963,7 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); if (!privreq) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_ALLOCFAIL), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } @@ -2983,7 +2983,7 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3009,7 +3009,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!req || !req->callback || !req->buf || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); uerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); return -EINVAL; @@ -3022,7 +3022,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_FEATURES if (!priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_NOTCONFIGURED), + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); uerr("ERROR: driver=%p\n", priv->driver); return -ESHUTDOWN; @@ -3123,7 +3123,7 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) #ifdef CONFIG_DEBUG_USB if (!ep || !req) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3151,7 +3151,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) #ifdef CONFIG_DEBUG_USB if (!ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3180,7 +3180,7 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (status == 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPDISABLED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPDISABLED), 0); if (epno == 0) { @@ -3291,14 +3291,14 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, { struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; struct stm32l4_ep_s *privep = NULL; - uint8_t epset = STM32L4_ENDP_ALLSET; + uint8_t epset = STM32_ENDP_ALLSET; int bufno; usbtrace(TRACE_DEVALLOCEP, (uint16_t)epno); #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return NULL; } #endif @@ -3319,9 +3319,9 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * by the hardware. */ - if (epno >= STM32L4_NENDPOINTS) + if (epno >= STM32_NENDPOINTS) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BADEPNO), (uint16_t)epno); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epno); return NULL; } @@ -3330,7 +3330,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, * the IN/OUT pair for this logical address. */ - epset = STM32L4_ENDP_BIT(epno); + epset = STM32_ENDP_BIT(epno); } /* Check if the selected endpoint number is available */ @@ -3338,7 +3338,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, privep = stm32l4_epreserve(priv, epset); if (!privep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPRESERVE), (uint16_t)epset); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); goto errout; } @@ -3348,7 +3348,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, bufno = stm32l4_epallocpma(priv); if (bufno < 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_EPBUFFER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); goto errout_with_ep; } @@ -3373,7 +3373,7 @@ static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) #ifdef CONFIG_DEBUG_USB if (!dev || !ep) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return; } #endif @@ -3405,14 +3405,14 @@ static int stm32l4_getframe(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32L4_USB_FNR); + fnr = stm32l4_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } @@ -3430,7 +3430,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3450,7 +3450,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32L4_USB_ISTR); + stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } @@ -3468,7 +3468,7 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) #ifdef CONFIG_DEBUG_USB if (!dev) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -ENODEV; } #endif @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32L4_USB_BCDR); + regval = stm32l4_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32L4_USB_BCDR); + stm32l4_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3526,7 +3526,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3542,7 +3542,7 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Reset endpoints */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { struct stm32l4_ep_s *privep = &priv->eplist[epno]; @@ -3578,24 +3578,24 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32L4_USB_CNTR); + stm32l4_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32L4_BTABLE_ADDRESS & 0xfff8, STM32L4_USB_BTABLE); + stm32l4_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32L4_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32L4_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32L4_EP0_TXADDR); + stm32l4_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32l4_seteptxaddr(EP0, STM32_EP0_TXADDR); stm32l4_clrstatusout(EP0); stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); @@ -3605,12 +3605,12 @@ static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32L4_CNTR_SETUP, - (USB_CNTR_ALLINTS & ~STM32L4_CNTR_SETUP)); + stm32l4_setimask(priv, STM32_CNTR_SETUP, + (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); stm32l4_dumpep(EP0); } @@ -3626,7 +3626,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. @@ -3642,12 +3642,12 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; - priv->epavail = STM32L4_ENDP_ALLSET & ~STM32L4_ENDP_BIT(EP0); - priv->bufavail = STM32L4_BUFFER_ALLSET & ~STM32L4_BUFFER_EP0; + priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); + priv->bufavail = STM32_BUFFER_ALLSET & ~STM32_BUFFER_EP0; /* Initialize the endpoint list */ - for (epno = 0; epno < STM32L4_NENDPOINTS; epno++) + for (epno = 0; epno < STM32_NENDPOINTS; epno++) { /* Set endpoint operations, reference to driver structure (not * really necessary because there is only one controller), and @@ -3664,13 +3664,13 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * packet size can be selected when the endpoint is configured. */ - priv->eplist[epno].ep.maxpacket = STM32L4_MAXPACKET_SIZE; + priv->eplist[epno].ep.maxpacket = STM32_MAXPACKET_SIZE; } /* Select a smaller endpoint size for EP0 */ -#if STM32L4_EP0MAXPACKET < STM32L4_MAXPACKET_SIZE - priv->eplist[EP0].ep.maxpacket = STM32L4_EP0MAXPACKET; +#if STM32_EP0MAXPACKET < STM32_MAXPACKET_SIZE + priv->eplist[EP0].ep.maxpacket = STM32_EP0MAXPACKET; #endif /* Configure the USB controller. USB uses the following GPIO pins: @@ -3691,7 +3691,7 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } @@ -3705,11 +3705,11 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32L4_USB_ISTR); + stm32l4_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ @@ -3717,7 +3717,7 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32L4_USB_CNTR); + stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3757,10 +3757,10 @@ void arm_usbinitialize(void) * driver is bound. */ - if (irq_attach(STM32L4_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_IRQREGISTRATION), - (uint16_t)STM32L4_IRQ_USB_FS); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), + (uint16_t)STM32_IRQ_USB_FS); arm_usbuninitialize(); } } @@ -3788,12 +3788,12 @@ void arm_usbuninitialize(void) /* Disable and detach the USB IRQ */ - up_disable_irq(STM32L4_IRQ_USB_FS); - irq_detach(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); + irq_detach(STM32_IRQ_USB_FS); if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVERREGISTERED), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); usbdev_unregister(priv->driver); } @@ -3833,13 +3833,13 @@ int usbdev_register(struct usbdevclass_driver_s *driver) if (!driver || !driver->ops->bind || !driver->ops->unbind || !driver->ops->disconnect || !driver->ops->setup) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } if (priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_DRIVER), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); return -EBUSY; } #endif @@ -3853,7 +3853,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) ret = CLASS_BIND(driver, &priv->usbdev); if (ret) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_BINDFAILED), (uint16_t)-ret); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); } else { @@ -3865,7 +3865,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) /* Enable USB controller interrupt at the NVIC */ - up_enable_irq(STM32L4_IRQ_USB_FS); + up_enable_irq(STM32_IRQ_USB_FS); /* Enable pull-up to connect the device. * The host should enumerate us some time after this @@ -3904,7 +3904,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) #ifdef CONFIG_DEBUG_USB if (driver != priv->driver) { - usbtrace(TRACE_DEVERROR(STM32L4_TRACEERR_INVALIDPARMS), 0); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); return -EINVAL; } #endif @@ -3922,7 +3922,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disable USB controller interrupt (but keep attached) */ - up_disable_irq(STM32L4_IRQ_USB_FS); + up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up * in the reset state (this is probably not necessary, the stm32l4_reset() diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 31e48e84d61..99cce2c222b 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -154,7 +154,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -173,26 +173,26 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif /* These chips have no GPIOF, GPIOG or GPIOI */ -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -216,7 +216,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -235,7 +235,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_QSPI /* QuadSPI module clock enable */ @@ -243,7 +243,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -262,7 +262,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -354,8 +354,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_USBFSEN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -387,11 +387,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -417,7 +417,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -436,7 +436,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -500,7 +500,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -520,9 +520,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -541,16 +541,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) @@ -572,20 +572,20 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -606,12 +606,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -619,7 +619,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -628,17 +628,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -649,10 +649,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -660,7 +660,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -668,12 +668,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -681,7 +681,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -705,122 +705,122 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -828,31 +828,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -867,18 +867,18 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -889,7 +889,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -914,14 +914,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -939,10 +939,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index b6c1903edd9..0c90408ee34 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -74,33 +74,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -119,7 +119,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -145,7 +145,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -164,31 +164,31 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -212,7 +212,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -231,7 +231,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -245,7 +245,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -264,7 +264,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -386,11 +386,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -410,7 +410,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -429,7 +429,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -511,7 +511,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -531,9 +531,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -552,16 +552,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) @@ -577,7 +577,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -596,12 +596,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -609,7 +609,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -618,17 +618,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -639,10 +639,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -650,7 +650,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -658,12 +658,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -671,7 +671,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -695,122 +695,122 @@ static void stm32l4_stdclockconfig(void) #if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. */ - regval = getreg32(STM32L4_PWR_CR); + regval = getreg32(STM32_PWR_CR); regval &= ~PWR_CR_VOS_MASK; regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); + putreg32(regval, STM32_PWR_CR); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -818,31 +818,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -857,18 +857,18 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -879,7 +879,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -904,14 +904,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 355b3929c1d..61ba84d2491 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -48,7 +48,7 @@ ****************************************************************************/ #define DMA1_NCHANNELS 7 -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 # define DMA2_NCHANNELS 7 # define DMA_NCHANNELS (DMA1_NCHANNELS+DMA2_NCHANNELS) #else @@ -86,88 +86,88 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, -#if STM32L4_NDMA > 1 +#if STM32_NDMA > 1 { .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .sem = SEM_INITIALIZER(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -226,17 +226,17 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmach->chan)); } @@ -256,19 +256,19 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the channel structure from the interrupt number */ - if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - chndx = irq - STM32L4_IRQ_DMA1CH1; + chndx = irq - STM32_IRQ_DMA1CH1; } else -#if STM32L4_NDMA > 1 - if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) +#if STM32_NDMA > 1 + if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - chndx = irq - STM32L4_IRQ_DMA2CH1 + DMA1_NCHANNELS; + chndx = irq - STM32_IRQ_DMA2CH1 + DMA1_NCHANNELS; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - chndx = irq - STM32L4_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; + chndx = irq - STM32_IRQ_DMA2CH6 + DMA1_NCHANNELS + 5; } #endif else @@ -280,7 +280,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmach->chan); /* Invoke the callback */ @@ -293,7 +293,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmach, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmach, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -457,28 +457,28 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * disabled. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmach, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmach, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmach, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -486,7 +486,7 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, * interrupt after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -494,14 +494,14 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, regval); /* define peripheral indicated in dmach->function */ - regval = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); + regval = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); regval &= ~(0x0f << (dmach->chan << 2)); regval |= (dmach->function << (dmach->chan << 2)); - dmabase_putreg(dmach, STM32L4_DMA_CSELR_OFFSET, regval); + dmabase_putreg(dmach, STM32_DMA_CSELR_OFFSET, regval); } /**************************************************************************** @@ -534,7 +534,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -567,7 +567,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmach, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmach, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -604,7 +604,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) { struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - return dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -667,22 +667,22 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) /* Verify that the transfer is to a memory region that supports DMA. */ - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_FSMC_BANK4: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_FSMC_BANK4: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ @@ -715,12 +715,12 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) irqstate_t flags; flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmach, STM32L4_DMA_ISR_OFFSET); - regs->cselr = dmabase_getreg(dmach, STM32L4_DMA_CSELR_OFFSET); - regs->ccr = dmachan_getreg(dmach, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmach, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmach, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmach, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmach, STM32_DMA_ISR_OFFSET); + regs->cselr = dmabase_getreg(dmach, STM32_DMA_CSELR_OFFSET); + regs->ccr = dmachan_getreg(dmach, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmach, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmach, STM32_DMACHAN_CMAR_OFFSET); leave_critical_section(flags); } #endif @@ -745,16 +745,16 @@ void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, dmainfo("DMA Registers: %s\n", msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, regs->isr); + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CSELR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_CSELR_OFFSET, regs->cselr); + dmabase + STM32_DMA_CSELR_OFFSET, regs->cselr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CCR_OFFSET, regs->ccr); + dmach->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CNDTR_OFFSET, regs->cndtr); + dmach->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CPAR_OFFSET, regs->cpar); + dmach->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmach->base + STM32L4_DMACHAN_CMAR_OFFSET, regs->cmar); + dmach->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); } #endif diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 1673c9a2abd..c89579c15ac 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMA1 /* DMA 1 clock enable */ @@ -160,7 +160,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -179,34 +179,34 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); @@ -248,7 +248,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_RNGEN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -267,7 +267,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -281,7 +281,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_QSPIEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -300,7 +300,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -410,8 +410,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_CAN2EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -443,11 +443,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -473,7 +473,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -492,7 +492,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -574,7 +574,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -594,9 +594,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -615,16 +615,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) @@ -640,20 +640,20 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; regval |= RCC_CCIPR2_I2C4SEL_HSI; - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -689,23 +689,23 @@ static void stm32l4_stdclockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Wait until the requested number of wait states is set */ - while ((getreg32(STM32L4_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != + while ((getreg32(STM32_FLASH_ACR) & FLASH_ACR_LATENCY_MASK) != FLASH_ACR_LATENCY_4) { } /* Proceed to clock configuration */ -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -713,7 +713,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -722,17 +722,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L4_RCC_CR)), (regval & RCC_CR_MSIRDY) || + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -743,18 +743,18 @@ static void stm32l4_stdclockconfig(void) /* Choose MSI frequency */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSIRGSEL); + putreg32(regval, STM32_RCC_CR); if (!(regval & RCC_CR_MSION)) { /* Enable MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -762,7 +762,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -771,12 +771,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -784,7 +784,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -804,7 +804,7 @@ static void stm32l4_stdclockconfig(void) if (timeout > 0) { - if (STM32L4_SYSCLK_FREQUENCY > 24000000ul) + if (STM32_SYSCLK_FREQUENCY > 24000000ul) { /* Select regulator voltage output Scale 1 mode to support system * frequencies up to 168 MHz. @@ -828,75 +828,75 @@ static void stm32l4_stdclockconfig(void) /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif /* Use the main PLL as SYSCLK, so enable it first */ - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #endif @@ -904,34 +904,34 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -939,60 +939,60 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif /* Select the system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; -#ifndef STM32L4_BOARD_NOPLL +#ifndef STM32_BOARD_NOPLL regval |= RCC_CFGR_SW_PLL; -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI regval |= RCC_CFGR_SW_MSI; -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI regval |= RCC_CFGR_SW_HSI; -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE regval |= RCC_CFGR_SW_HSE; #endif - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != -#ifndef STM32L4_BOARD_NOPLL + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != +#ifndef STM32_BOARD_NOPLL RCC_CFGR_SWS_PLL -#elif STM32L4_BOARD_USEMSI +#elif STM32_BOARD_USEMSI RCC_CFGR_SWS_MSI -#elif STM32L4_BOARD_USEHSI +#elif STM32_BOARD_USEHSI RCC_CFGR_SWS_HSI -#elif STM32L4_BOARD_USEHSE +#elif STM32_BOARD_USEHSE RCC_CFGR_SWS_HSE #endif ) @@ -1005,15 +1005,15 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Enable wake-up to HSI from Stop modes */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval |= RCC_CFGR_STOPWUCK_HSI; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -1038,14 +1038,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -1063,10 +1063,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 38ecf403e11..056a18024d3 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -260,7 +260,7 @@ static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32L4_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -271,7 +271,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32L4_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -281,7 +281,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32L4_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -299,57 +299,57 @@ static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA1, .chan = 0, - .irq = STM32L4_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32L4_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32L4_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32L4_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32L4_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32L4_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32L4_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA1_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif @@ -359,57 +359,57 @@ static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA2, .chan = 0, - .irq = STM32L4_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32L4_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32L4_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32L4_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32L4_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32L4_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32L4_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32L4_DMA2_BASE + STM32L4_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -589,17 +589,17 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -624,21 +624,21 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) { } #ifdef CONFIG_STM32L4_DMA1 - else if (irq >= STM32L4_IRQ_DMA1CH1 && irq <= STM32L4_IRQ_DMA1CH7) + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32L4_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif #ifdef CONFIG_STM32L4_DMA2 - else if (irq >= STM32L4_IRQ_DMA2CH1 && irq <= STM32L4_IRQ_DMA2CH5) + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32L4_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32L4_IRQ_DMA2CH6 && irq <= STM32L4_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32L4_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -654,7 +654,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -667,7 +667,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32L4_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -704,28 +704,28 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -733,7 +733,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -741,7 +741,7 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -769,7 +769,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -803,7 +803,7 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -816,7 +816,7 @@ static size_t stm32l4_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -831,11 +831,11 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32L4_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32L4_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32L4_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -864,19 +864,19 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmabase + STM32L4_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmachan->base + STM32L4_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -895,13 +895,13 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32l4_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32L4_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32L4_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -915,20 +915,20 @@ static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08" PRIx32 "]: %08" PRIx32 "\n", - dmamux->base + STM32L4_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1186,7 +1186,7 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1231,7 +1231,7 @@ void stm32l4_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32L4_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1322,23 +1322,23 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32L4_REGION_MASK) != (mend & STM32L4_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32L4_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32L4_PERIPH_BASE: - case STM32L4_FSMC_BASE: - case STM32L4_FSMC_BANK1: - case STM32L4_FSMC_BANK2: - case STM32L4_FSMC_BANK3: - case STM32L4_QSPI_BANK: - case STM32L4_SRAM_BASE: - case STM32L4_SRAM2_BASE: - case STM32L4_SRAM3_BASE: - case STM32L4_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 0add98c9003..607f2e9cc1b 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32L4_USE_CLK48) -# if STM32L4_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_USE_HSI48 +#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -83,33 +83,33 @@ static inline void rcc_reset(void) /* Enable the Internal High Speed clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - putreg32(0x00000000, STM32L4_RCC_CFGR); + putreg32(0x00000000, STM32_RCC_CFGR); /* Reset HSION, HSEON, CSSON and PLLON bits */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset PLLCFGR register to reset default */ - putreg32(RCC_PLLCFG_RESET, STM32L4_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset HSEBYP bit */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_HSEBYP; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Disable all interrupts */ - putreg32(0x00000000, STM32L4_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -128,7 +128,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L4_DMAMUX1 /* DMAMUX 1 clock enable */ @@ -166,7 +166,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DMA2DEN; #endif - putreg32(regval, STM32L4_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -185,34 +185,34 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOI */ -#if STM32L4_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L4_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L4_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L4_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L4_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L4_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L4_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L4_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif -#if STM32L4_NPORTS > 8 +#if STM32_NPORTS > 8 | RCC_AHB2ENR_GPIOIEN #endif ); @@ -260,7 +260,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L4_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -279,7 +279,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L4_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L4_FSMC /* Flexible static memory controller module clock enable */ @@ -287,7 +287,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FSMCEN; #endif - putreg32(regval, STM32L4_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,7 +306,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L4_TIM2 /* TIM2 clock enable */ @@ -404,8 +404,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef STM32L4_USE_HSI48 - if (STM32L4_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -437,11 +437,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L4_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L4_LPUART1 /* Low power uart clock enable */ @@ -461,7 +461,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32L4_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -480,7 +480,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L4_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) /* System configuration controller, comparators, and voltage reference @@ -556,7 +556,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L4_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -576,9 +576,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32L4_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -597,16 +597,16 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32L4_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32L4_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32L4_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ regval &= ~RCC_CCIPR_CLK48SEL_MASK; - regval |= STM32L4_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32L4_ADC1) @@ -616,13 +616,13 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* Some peripherals have their clock selection in CCIPR2 register. */ - regval = getreg32(STM32L4_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); -#if defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32L4_I2C4 /* Select HSI16 as I2C4 clock source. */ @@ -642,7 +642,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR2_DFSDMSEL_PCLK; #endif - putreg32(regval, STM32L4_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); } /**************************************************************************** @@ -661,12 +661,12 @@ static void stm32l4_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L4_BOARD_USEHSI) || defined(STM32L4_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -674,7 +674,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -683,17 +683,17 @@ static void stm32l4_stdclockconfig(void) } #endif -#if defined(STM32L4_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -705,10 +705,10 @@ static void stm32l4_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32L4_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L4_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -716,7 +716,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -724,12 +724,12 @@ static void stm32l4_stdclockconfig(void) } } -#elif defined(STM32L4_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -737,7 +737,7 @@ static void stm32l4_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32L4_BOARD_USEHSI, STM32L4_BOARD_USEMSI, STM32L4_BOARD_USEHSE defined +# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -760,9 +760,9 @@ static void stm32l4_stdclockconfig(void) #warning todo: regulator voltage according to clock freq /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); /* Switch to Range 1 boost mode to support system frequencies up to * 120 MHz. @@ -772,115 +772,115 @@ static void stm32l4_stdclockconfig(void) * Range 2 is not supported. */ -#if STM32L4_SYSCLK_FREQUENCY > 80000000 || \ +#if STM32_SYSCLK_FREQUENCY > 80000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 80000000) - regval = getreg32(STM32L4_PWR_CR5); + regval = getreg32(STM32_PWR_CR5); regval &= ~PWR_CR5_R1MODE; - putreg32(regval, STM32L4_PWR_CR5); + putreg32(regval, STM32_PWR_CR5); #endif /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | - STM32L4_PLLCFG_PLLP | STM32L4_PLLCFG_PLLQ | - STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L4_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L4_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L4_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L4_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI; -#elif defined(STM32L4_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L4_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L4_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP - | STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L4_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -888,31 +888,31 @@ static void stm32l4_stdclockconfig(void) #ifdef CONFIG_STM32L4_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L4_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -932,18 +932,18 @@ static void stm32l4_stdclockconfig(void) #else regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -954,7 +954,7 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -969,14 +969,14 @@ static void stm32l4_stdclockconfig(void) stm32l4_rcc_enablelse(); -# if defined(STM32L4_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L4_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif @@ -994,10 +994,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32L4_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32L4_HSI48_SYNCSRC); + stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 3782cd80078..47a7f317e0d 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -56,20 +56,20 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -85,13 +85,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -130,7 +130,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -225,7 +225,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -235,13 +235,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -255,72 +255,72 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1, when - * NOT define STM32L4_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. + * NOT define STM32_RCC_CFGR_PPRE1 as RCC_CFGR_PPRE1_HCLK. */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM3_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM4_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM5_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM6_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_TIM7_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM1_CLKIN STM32L4_PCLK1_FREQUENCY -#define STM32L4_APB1_LPTIM2_CLKIN STM32L4_PCLK1_FREQUENCY +#define STM32_APB1_TIM2_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM3_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM4_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM5_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM6_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_TIM7_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM1_CLKIN STM32_PCLK1_FREQUENCY +#define STM32_APB1_LPTIM2_CLKIN STM32_PCLK1_FREQUENCY /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM8_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM15_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM16_CLKIN STM32L4_PCLK2_FREQUENCY -#define STM32L4_APB2_TIM17_CLKIN STM32L4_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM8_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM15_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -335,7 +335,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -343,78 +343,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -422,71 +422,71 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -495,19 +495,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32L4_APB1_TIM2_CLKIN -#define BOARD_TIM3_FREQUENCY STM32L4_APB1_TIM3_CLKIN -#define BOARD_TIM4_FREQUENCY STM32L4_APB1_TIM4_CLKIN -#define BOARD_TIM5_FREQUENCY STM32L4_APB1_TIM5_CLKIN -#define BOARD_TIM6_FREQUENCY STM32L4_APB1_TIM6_CLKIN -#define BOARD_TIM7_FREQUENCY STM32L4_APB1_TIM7_CLKIN -#define BOARD_TIM8_FREQUENCY STM32L4_APB2_TIM8_CLKIN -#define BOARD_TIM15_FREQUENCY STM32L4_APB2_TIM15_CLKIN -#define BOARD_TIM16_FREQUENCY STM32L4_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32L4_APB2_TIM17_CLKIN -#define BOARD_LPTIM1_FREQUENCY STM32L4_APB1_LPTIM1_CLKIN -#define BOARD_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN +#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN +#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN +#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN +#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN +#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN +#define BOARD_TIM15_FREQUENCY STM32_APB2_TIM15_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN +#define BOARD_LPTIM1_FREQUENCY STM32_APB1_LPTIM1_CLKIN +#define BOARD_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN /**************************************************************************** * Public Data @@ -534,4 +534,4 @@ extern "C" #endif #endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_ARMSTM32L4__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ +#endif /* __BOARDS_ARMSTM32__B_L475E_IOT01A_INCLUDE_B_L475E_IOT01A_CLOCK */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index cc2f750933f..8b8519497ca 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -265,7 +265,7 @@ */ #if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) -# define STM32L4_LPTIM2_FREQUENCY STM32L4_APB1_LPTIM2_CLKIN +# define STM32_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN #endif #if 1 diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index bc2cd77d6dd..cacbf3ea929 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -57,20 +57,20 @@ * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL * configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) * (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) * (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -86,11 +86,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -127,7 +127,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -216,7 +216,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -226,13 +226,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -246,45 +246,45 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -293,16 +293,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -311,9 +311,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -321,7 +321,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -329,59 +329,59 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -390,14 +390,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -406,16 +406,16 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -423,74 +423,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM1_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_LPTIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM1_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -500,14 +500,14 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 63bcbcb47b9..ad672643696 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -336,7 +336,7 @@ static void tim6_handler(void) /* TODO: Software update */ - STM32L4_TIM_ACKINT(tim, ATIM_SR_UIF); + STM32_TIM_ACKINT(tim, ATIM_SR_UIF); } /**************************************************************************** @@ -368,12 +368,12 @@ static int spwm_tim6_setup(struct spwm_s *spwm) freq = spwm->samples * spwm->waveform_freq; - STM32L4_TIM_SETFREQ(tim, freq); - STM32L4_TIM_ENABLE(tim); + STM32_TIM_SETFREQ(tim, freq); + STM32_TIM_ENABLE(tim); /* Attach TIM6 ram vector */ - ret = arm_ramvec_attach(STM32L4_IRQ_TIM6, tim6_handler); + ret = arm_ramvec_attach(STM32_IRQ_TIM6, tim6_handler); if (ret < 0) { printf("ERROR: arm_ramvec_attach failed: %d\n", ret); @@ -383,7 +383,7 @@ static int spwm_tim6_setup(struct spwm_s *spwm) /* Set the priority of the TIM6 interrupt vector */ - ret = up_prioritize_irq(STM32L4_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); + ret = up_prioritize_irq(STM32_IRQ_TIM6, NVIC_SYSH_HIGH_PRIORITY); if (ret < 0) { printf("ERROR: up_prioritize_irq failed: %d\n", ret); @@ -407,8 +407,8 @@ static int spwm_tim6_start(struct spwm_s *spwm) /* Enable the timer interrupt at the NVIC and at TIM6 */ - up_enable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_ENABLEINT(tim, BTIM_DIER_UIE); + up_enable_irq(STM32_IRQ_TIM6); + STM32_TIM_ENABLEINT(tim, BTIM_DIER_UIE); return OK; } @@ -423,8 +423,8 @@ static int spwm_tim6_stop(struct spwm_s *spwm) /* Disable the timer interrupt at the NVIC and at TIM6 */ - up_disable_irq(STM32L4_IRQ_TIM6); - STM32L4_TIM_DISABLEINT(tim, BTIM_DIER_UIE); + up_disable_irq(STM32_IRQ_TIM6); + STM32_TIM_DISABLEINT(tim, BTIM_DIER_UIE); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 0dd3430e3bd..55c553e4927 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -44,16 +44,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -69,9 +69,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #if 1 # define HSI_CLOCK_CONFIG /* HSI-16 clock configuration */ @@ -85,7 +85,7 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -125,7 +125,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -221,7 +221,7 @@ * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -232,55 +232,55 @@ * want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from HSI48 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK / 1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -289,17 +289,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -308,9 +308,9 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* TODO SDMMC */ @@ -318,7 +318,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -326,82 +326,82 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -409,75 +409,75 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ 0 -#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -487,17 +487,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 4ab69149c5d..08cecef4150 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -65,14 +65,14 @@ /* How many SPI modules does this chip support? */ -#if STM32L4_NSPI < 1 +#if STM32_NSPI < 1 # undef CONFIG_STM32L4_SPI1 # undef CONFIG_STM32L4_SPI2 # undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 2 +#elif STM32_NSPI < 2 # undef CONFIG_STM32L4_SPI2 # undef CONFIG_STM32L4_SPI3 -#elif STM32L4_NSPI < 3 +#elif STM32_NSPI < 3 # undef CONFIG_STM32L4_SPI3 #endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 39623ef7e56..48a4b158b7d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -55,16 +55,16 @@ * * System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -80,11 +80,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -124,7 +124,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -219,7 +219,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -230,13 +230,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -250,68 +250,68 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -326,7 +326,7 @@ /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -334,81 +334,81 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -416,74 +416,74 @@ /* prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -492,19 +492,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 7aa8a010e5a..30d1bcd22eb 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -55,20 +55,20 @@ * LSE: 32.768 kHz */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY 8000000ul /* 8 MHz from MCO output */ +#define STM32_LSE_FREQUENCY 32768 #define MSI_CLOCK_CONFIG #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI +#define STM32_BOARD_USEHSI /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -79,13 +79,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -99,71 +99,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -174,11 +174,11 @@ #elif defined(HSE_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSE +#define STM32_BOARD_USEHSE /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz @@ -189,13 +189,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -209,71 +209,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -284,12 +284,12 @@ #elif defined(MSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEMSI -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz @@ -300,13 +300,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -320,71 +320,71 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -400,19 +400,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /* SDMMC dividers. * Note that slower clocking is required when DMA is disabled diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 83b338839af..0ad0e10887d 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -48,15 +48,15 @@ /* Up to 3 ADC interfaces are supported */ -#if STM32L4_NADC < 3 +#if STM32_NADC < 3 # undef CONFIG_STM32L4_ADC3 #endif -#if STM32L4_NADC < 2 +#if STM32_NADC < 2 # undef CONFIG_STM32L4_ADC2 #endif -#if STM32L4_NADC < 1 +#if STM32_NADC < 1 # undef CONFIG_STM32L4_ADC1 #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 7c5ffc6ddfb..4ecb2c970fb 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -37,16 +37,16 @@ /* System Clock source : PLL (HSI) * SYSCLK(Hz) : 80000000 Determined by PLL configuration - * HCLK(Hz) : 80000000 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * AHB Prescaler : 1 (STM32L4_RCC_CFGR_HPRE) (Max 80 MHz) - * APB1 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE1) (Max 80 MHz) - * APB2 Prescaler : 1 (STM32L4_RCC_CFGR_PPRE2) (Max 80 MHz) + * HCLK(Hz) : 80000000 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 80 MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 80 MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 80 MHz) * HSI Frequency(Hz) : 16000000 (nominal) - * PLLM : 1 (STM32L4_PLLCFG_PLLM) - * PLLN : 10 (STM32L4_PLLCFG_PLLN) - * PLLP : 0 (STM32L4_PLLCFG_PLLP) - * PLLQ : 0 (STM32L4_PLLCFG_PLLQ) - * PLLR : 2 (STM32L4_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 10 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * PLLSAI1N : 12 * PLLSAI1Q : 4 * Flash Latency(WS) : 4 @@ -62,11 +62,11 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* XXX sysclk mux = pllclk */ @@ -106,7 +106,7 @@ * * PLL source is HSI * - * PLL_REF = STM32L4_HSI_FREQUENCY / PLLM + * PLL_REF = STM32_HSI_FREQUENCY / PLLM * = 16,000,000 / 1 * = 16,000,000 * @@ -165,7 +165,7 @@ * as per comment above HSI) . */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -176,13 +176,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -196,87 +196,87 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2 * STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM15_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM16_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM17_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define STM32L4_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define STM32L4_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define STM32_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index ce9c293eddc..d73085956e0 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -59,9 +59,9 @@ * LSE - not installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -79,13 +79,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -96,13 +96,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,65 +116,65 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB1 will be twice PCLK1 */ /* REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) /* Timers driven from APB2 will be twice PCLK2 */ /* REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -185,76 +185,76 @@ /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Disable LSE (for the RTC) */ -#undef STM32L4_USE_LSE +#undef STM32_USE_LSE /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1) -#define STM32L4_APB2_TIM1_CLKIN (2*STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (2*STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) #endif @@ -263,19 +263,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM3_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM4_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM5_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM6_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM7_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -#define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM3_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM4_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM5_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM6_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +#define BOARD_LPTIM2_FREQUENCY (STM32_HCLK_FREQUENCY / 2) /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 328eb3c834a..bf16becc8f3 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index d336955276e..65da2b2da59 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -51,9 +51,9 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 #define BOARD_AHB_FREQUENCY 80000000ul @@ -75,13 +75,13 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly * as per comment above HSI) */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz @@ -91,13 +91,13 @@ * may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -111,42 +111,42 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#define STM32L4_USE_CLK48 1 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* AHB clock (HCLK) is SYSCLK (80MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -155,17 +155,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (80MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -174,14 +174,14 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* XXX sysclk mux = pllclk */ @@ -189,78 +189,78 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* XXX sysclk mux = pllclk */ @@ -268,71 +268,71 @@ /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ 0 -#undef STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L4_SYSCLK_FREQUENCY 80000000ul +#define STM32_SYSCLK_FREQUENCY 80000000ul /* Enable CLK48; get it from PLLSAI1 */ -#define STM32L4_USE_CLK48 -#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +#define STM32_USE_CLK48 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif @@ -343,19 +343,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index 5257fe5408b..b2a93e9b22b 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index ddc8d01fb14..bb33ba52a60 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -53,13 +53,13 @@ * LSE - 32.768 kHz installed */ -#define STM32L4_HSI_FREQUENCY 16000000ul -#define STM32L4_LSI_FREQUENCY 32000 -#define STM32L4_LSE_FREQUENCY 32768 -#define STM32L4_HSE_FREQUENCY 16000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 16000000ul -#define STM32L4_SYSCLK_FREQUENCY 120000000ul -#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_SYSCLK_FREQUENCY 120000000ul +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY /* Higher SYSCLK requires more flash wait states. */ @@ -81,11 +81,11 @@ #if defined(HSI_CLOCK_CONFIG) -#define STM32L4_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -96,13 +96,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 13, and enable @@ -116,47 +116,47 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* AHB clock (HCLK) is SYSCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -165,17 +165,17 @@ * REVISIT : this can be configured */ -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* APB2 clock (PCLK2) is HCLK (120 MHz) */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the @@ -184,18 +184,18 @@ * REVISIT : this can be configured */ -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32L4_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz @@ -206,13 +206,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -226,73 +226,73 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI; frequ = 4 MHz; autotrim from LSE */ -#define STM32L4_BOARD_USEMSI 1 -#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* Prescaler common to all PLL inputs */ -#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz @@ -303,13 +303,13 @@ * applications may want things done this way. */ -#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) -#define STM32L4_PLLCFG_PLLP 0 -#undef STM32L4_PLLCFG_PLLP_ENABLED -#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 -#define STM32L4_PLLCFG_PLLQ_ENABLED -#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L4_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2 +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't * do that with the main PLL's N value. We set N = 12, and enable @@ -323,62 +323,62 @@ * that is selected via a #define here, like all these other params. */ -#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L4_PLLSAI1CFG_PLLP 0 -#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED -#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 -#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L4_PLLSAI1CFG_PLLR 0 -#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2 +#define STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L4_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L4_PLLSAI2CFG_PLLP 0 -#undef STM32L4_PLLSAI2CFG_PLLP_ENABLED -#define STM32L4_PLLSAI2CFG_PLLR 0 -#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32L4_SDMMC) || defined(CONFIG_STM32L4_RNG) -# define STM32L4_USE_CLK48 1 -# define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 -# define STM32L4_HSI48_SYNCSRC SYNCSRC_NONE +#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC) */ -#define STM32L4_USE_LSE 1 +#define STM32_USE_LSE 1 /* HSI16 used as I2C clock */ -#define STM32L4_I2C_USE_HSI16 1 +#define STM32_I2C_USE_HSI16 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY) -#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY) -#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY) #endif /* clock selection */ @@ -388,19 +388,19 @@ * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM8_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L4_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L4_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Public Data diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index e17b57ba7fd..cfd2d047792 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -59,115 +59,115 @@ void stm32l4_board_clockconfig(void) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_HSIRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) == 0) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L4_RCC_CFGR_HPRE; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L4_RCC_CFGR_PPRE2; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L4_RCC_CFGR_PPRE1; - putreg32(regval, STM32L4_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PLL source and main divider */ - regval = getreg32(STM32L4_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP - | STM32L4_PLLCFG_PLLQ | STM32L4_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP + | STM32_PLLCFG_PLLQ | STM32_PLLCFG_PLLR); regval |= RCC_PLLCFG_PLLQEN; regval |= RCC_PLLCFG_PLLREN; /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L4_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval |= RCC_PLLCFG_PLLSRC_HSI; - putreg32(regval, STM32L4_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure SAI1 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L4_PLLSAI1CFG_PLLN | STM32L4_PLLSAI1CFG_PLLP | - STM32L4_PLLSAI1CFG_PLLQ | STM32L4_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP | + STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); regval |= RCC_PLLSAI1CFG_PLLQEN; - putreg32(regval, STM32L4_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } /* Configure SAI2 PLL */ - regval = getreg32(STM32L4_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | - STM32L4_PLLSAI2CFG_PLLR); - putreg32(regval, STM32L4_RCC_PLLSAI2CFG); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L4_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L4_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L4_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } @@ -181,18 +181,18 @@ void stm32l4_board_clockconfig(void) #else regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif - putreg32(regval, STM32L4_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L4_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L4_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -204,7 +204,7 @@ void stm32l4_board_clockconfig(void) stm32l4_rcc_enablelsi(); #endif -#if defined(STM32L4_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * From 62e029cb0b970ffd196822fa785f65571449a01a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 052/268] !arch/stm32l5: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32L5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32l5/chip.h | 60 +-- arch/arm/include/stm32l5/stm32l562xx_irq.h | 222 ++++---- arch/arm/include/stm32l5/stm32l5_irq.h | 30 +- arch/arm/src/stm32l5/chip.h | 2 +- .../src/stm32l5/hardware/stm32l562xx_rcc.h | 160 +++--- .../src/stm32l5/hardware/stm32l562xx_syscfg.h | 44 +- arch/arm/src/stm32l5/hardware/stm32l5_exti.h | 92 ++-- arch/arm/src/stm32l5/hardware/stm32l5_flash.h | 144 ++--- arch/arm/src/stm32l5/hardware/stm32l5_gpio.h | 258 ++++----- .../src/stm32l5/hardware/stm32l5_memorymap.h | 194 +++---- arch/arm/src/stm32l5/hardware/stm32l5_pwr.h | 100 ++-- arch/arm/src/stm32l5/hardware/stm32l5_spi.h | 64 +-- arch/arm/src/stm32l5/hardware/stm32l5_tim.h | 492 +++++++++--------- arch/arm/src/stm32l5/hardware/stm32l5_uart.h | 154 +++--- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 202 +++---- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 14 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 52 +- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 16 +- arch/arm/src/stm32l5/stm32l5_flash.c | 82 +-- arch/arm/src/stm32l5/stm32l5_gpio.c | 64 +-- arch/arm/src/stm32l5/stm32l5_gpio.h | 2 +- arch/arm/src/stm32l5/stm32l5_irq.c | 50 +- arch/arm/src/stm32l5/stm32l5_lowputc.c | 244 ++++----- arch/arm/src/stm32l5/stm32l5_lse.c | 16 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 6 +- arch/arm/src/stm32l5/stm32l5_pwr.c | 32 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 16 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 4 +- arch/arm/src/stm32l5/stm32l5_serial.c | 192 +++---- arch/arm/src/stm32l5/stm32l5_spi.c | 80 +-- arch/arm/src/stm32l5/stm32l5_start.c | 4 +- arch/arm/src/stm32l5/stm32l5_tim.c | 332 ++++++------ arch/arm/src/stm32l5/stm32l5_tim.h | 78 +-- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 82 +-- arch/arm/src/stm32l5/stm32l5_timerisr.c | 8 +- arch/arm/src/stm32l5/stm32l5_uid.c | 6 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 130 ++--- .../arm/stm32l5/stm32l562e-dk/include/board.h | 38 +- 38 files changed, 1883 insertions(+), 1883 deletions(-) diff --git a/arch/arm/include/stm32l5/chip.h b/arch/arm/include/stm32l5/chip.h index 25fae6e32e0..e6948539e5f 100644 --- a/arch/arm/include/stm32l5/chip.h +++ b/arch/arm/include/stm32l5/chip.h @@ -34,41 +34,41 @@ ****************************************************************************/ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ -# define STM32L5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_NFSMC 1 /* Have FSMC memory controller */ -# define STM32L5_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32L5_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ -# define STM32L5_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ -# define STM32L5_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ -# define STM32L5_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32L5_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -# define STM32L5_NRNG 1 /* Random number generator (RNG) */ -# define STM32L5_NUART 2 /* UART 4-5 */ -# define STM32L5_NUSART 3 /* USART 1-3 */ -# define STM32L5_NLPUART 1 /* LPUART 1 */ -# define STM32L5_QSPI 0 /* No QuadSPI1 */ -# define STM32L5_OCTOSPI 2 /* OCTOSPI1-2 */ -# define STM32L5_NSPI 3 /* SPI1-3 */ -# define STM32L5_NI2C 4 /* I2C1-4 */ -# define STM32L5_NSWPMI 0 /* No SWPMI1 */ -# define STM32L5_NUSBOTGFS 1 /* USB OTG FS */ -# define STM32L5_NUSBFS 0 /* No USB FS */ -# define STM32L5_NCAN 1 /* CAN1 */ -# define STM32L5_NSAI 2 /* SAI1-2 */ -# define STM32L5_NSDMMC 1 /* SDMMC interface */ -# define STM32L5_NDMA 2 /* DMA1-2 */ -# define STM32L5_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L5_NADC 1 /* 12-bit ADC1, up to 20 channels */ -# define STM32L5_NDAC 2 /* 12-bit DAC1-2 */ -# define STM32L5_NCRC 1 /* CRC */ -# define STM32L5_NCOMP 2 /* Comparators */ -# define STM32L5_NOPAMP 2 /* Operational Amplifiers */ +# define STM32_NFSMC 1 /* Have FSMC memory controller */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM15-17 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUART 2 /* UART 4-5 */ +# define STM32_NUSART 3 /* USART 1-3 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_QSPI 0 /* No QuadSPI1 */ +# define STM32_OCTOSPI 2 /* OCTOSPI1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NSWPMI 0 /* No SWPMI1 */ +# define STM32_NUSBOTGFS 1 /* USB OTG FS */ +# define STM32_NUSBFS 0 /* No USB FS */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSAI 2 /* SAI1-2 */ +# define STM32_NSDMMC 1 /* SDMMC interface */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ +# define STM32_NADC 1 /* 12-bit ADC1, up to 20 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1-2 */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NCOMP 2 /* Comparators */ +# define STM32_NOPAMP 2 /* Operational Amplifiers */ #endif /* CONFIG_STM32L5_STM32L562XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index a8e283dcc95..731567e7ffa 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -50,124 +50,124 @@ * */ -#define STM32L5_IRQ_WWDG (STM32L5_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32L5_IRQ_PVD_PVM (STM32L5_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ -#define STM32L5_IRQ_RTC (STM32L5_IRQ_FIRST + 2) /* 2: RTC global interrupts */ -#define STM32L5_IRQ_RTC_S (STM32L5_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ -#define STM32L5_IRQ_TAMP (STM32L5_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ -#define STM32L5_IRQ_TAMP_S (STM32L5_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ -#define STM32L5_IRQ_FLASH (STM32L5_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ -#define STM32L5_IRQ_FLASH_S (STM32L5_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ -#define STM32L5_IRQ_GTZC (STM32L5_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ -#define STM32L5_IRQ_RCC (STM32L5_IRQ_FIRST + 9) /* 9: RCC global interrupt */ -#define STM32L5_IRQ_RCC_S (STM32L5_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ -#define STM32L5_IRQ_EXTI0 (STM32L5_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ -#define STM32L5_IRQ_EXTI1 (STM32L5_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ -#define STM32L5_IRQ_EXTI2 (STM32L5_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ -#define STM32L5_IRQ_EXTI3 (STM32L5_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ -#define STM32L5_IRQ_EXTI4 (STM32L5_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ -#define STM32L5_IRQ_EXTI5 (STM32L5_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ -#define STM32L5_IRQ_EXTI6 (STM32L5_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ -#define STM32L5_IRQ_EXTI7 (STM32L5_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ -#define STM32L5_IRQ_EXTI8 (STM32L5_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ -#define STM32L5_IRQ_EXTI9 (STM32L5_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ -#define STM32L5_IRQ_EXTI10 (STM32L5_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ -#define STM32L5_IRQ_EXTI11 (STM32L5_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ -#define STM32L5_IRQ_EXTI12 (STM32L5_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ -#define STM32L5_IRQ_EXTI13 (STM32L5_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ -#define STM32L5_IRQ_EXTI14 (STM32L5_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ -#define STM32L5_IRQ_EXTI15 (STM32L5_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR (STM32L5_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ -#define STM32L5_IRQ_DMAMUX1_OVR_S (STM32L5_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ -#define STM32L5_IRQ_DMA1CH1 (STM32L5_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA1CH2 (STM32L5_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA1CH3 (STM32L5_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA1CH4 (STM32L5_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA1CH5 (STM32L5_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA1CH6 (STM32L5_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA1CH7 (STM32L5_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA1CH8 (STM32L5_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ -#define STM32L5_IRQ_ADC1_2 (STM32L5_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ -#define STM32L5_IRQ_DAC (STM32L5_IRQ_FIRST + 38) /* 38: DAC global interrupt */ -#define STM32L5_IRQ_FDCAN1_IT0 (STM32L5_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ -#define STM32L5_IRQ_FDCAN1_IT1 (STM32L5_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ -#define STM32L5_IRQ_TIM1_BRK (STM32L5_IRQ_FIRST + 41) /* 41: TIM1 break */ -#define STM32L5_IRQ_TIM1_UP (STM32L5_IRQ_FIRST + 42) /* 42: TIM1 update */ -#define STM32L5_IRQ_TIM1_TRG_COM (STM32L5_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ -#define STM32L5_IRQ_TIM1_CC (STM32L5_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ -#define STM32L5_IRQ_TIM2 (STM32L5_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ -#define STM32L5_IRQ_TIM3 (STM32L5_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ -#define STM32L5_IRQ_TIM4 (STM32L5_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ -#define STM32L5_IRQ_TIM5 (STM32L5_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ -#define STM32L5_IRQ_TIM6 (STM32L5_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ -#define STM32L5_IRQ_TIM7 (STM32L5_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ -#define STM32L5_IRQ_TIM8_BRK (STM32L5_IRQ_FIRST + 51) /* 51: TIM8 break */ -#define STM32L5_IRQ_TIM8_UP (STM32L5_IRQ_FIRST + 52) /* 52: TIM8 update */ -#define STM32L5_IRQ_TIM8_TRG_COM (STM32L5_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ -#define STM32L5_IRQ_TIM8_CC (STM32L5_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ -#define STM32L5_IRQ_I2C1_EV (STM32L5_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ -#define STM32L5_IRQ_I2C1_ER (STM32L5_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ -#define STM32L5_IRQ_I2C2_EV (STM32L5_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ -#define STM32L5_IRQ_I2C2_ER (STM32L5_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ -#define STM32L5_IRQ_SPI1 (STM32L5_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ -#define STM32L5_IRQ_SPI2 (STM32L5_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ -#define STM32L5_IRQ_USART1 (STM32L5_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ -#define STM32L5_IRQ_USART2 (STM32L5_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ -#define STM32L5_IRQ_USART3 (STM32L5_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ -#define STM32L5_IRQ_UART4 (STM32L5_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ -#define STM32L5_IRQ_UART5 (STM32L5_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ -#define STM32L5_IRQ_LPUART1 (STM32L5_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ -#define STM32L5_IRQ_LPTIM1 (STM32L5_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ -#define STM32L5_IRQ_LPTIM2 (STM32L5_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ -#define STM32L5_IRQ_TIM15 (STM32L5_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ -#define STM32L5_IRQ_TIM16 (STM32L5_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ -#define STM32L5_IRQ_TIM17 (STM32L5_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ -#define STM32L5_IRQ_COMP (STM32L5_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ -#define STM32L5_IRQ_USB_FS (STM32L5_IRQ_FIRST + 73) /* 73: USB global interrupt */ -#define STM32L5_IRQ_CRS (STM32L5_IRQ_FIRST + 74) /* 74: CRS global interrupt */ -#define STM32L5_IRQ_FMC (STM32L5_IRQ_FIRST + 75) /* 75: FMC global interrupt */ -#define STM32L5_IRQ_OCTOSPI1 (STM32L5_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ - /* 77: Reserved */ -#define STM32L5_IRQ_SDMMC1 (STM32L5_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ - /* 79: Reserved */ -#define STM32L5_IRQ_DMA2CH1 (STM32L5_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ -#define STM32L5_IRQ_DMA2CH2 (STM32L5_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ -#define STM32L5_IRQ_DMA2CH3 (STM32L5_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ -#define STM32L5_IRQ_DMA2CH4 (STM32L5_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ -#define STM32L5_IRQ_DMA2CH5 (STM32L5_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ -#define STM32L5_IRQ_DMA2CH6 (STM32L5_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ -#define STM32L5_IRQ_DMA2CH7 (STM32L5_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ -#define STM32L5_IRQ_DMA2CH8 (STM32L5_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ -#define STM32L5_IRQ_I2C3_EV (STM32L5_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ -#define STM32L5_IRQ_I2C3_ER (STM32L5_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ -#define STM32L5_IRQ_SAI1 (STM32L5_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ -#define STM32L5_IRQ_SAI2 (STM32L5_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ -#define STM32L5_IRQ_TSC (STM32L5_IRQ_FIRST + 92) /* 92: TSC global interrupt */ -#define STM32L5_IRQ_AES (STM32L5_IRQ_FIRST + 93) /* 93: AES global interrupt */ -#define STM32L5_IRQ_RNG (STM32L5_IRQ_FIRST + 94) /* 94: RNG global interrupt */ -#define STM32L5_IRQ_FPU (STM32L5_IRQ_FIRST + 95) /* 95: FPU global interrupt */ -#define STM32L5_IRQ_HASH (STM32L5_IRQ_FIRST + 96) /* 96: HASH global interrupt */ -#define STM32L5_IRQ_PKA (STM32L5_IRQ_FIRST + 97) /* 97: PKA global interrupt */ -#define STM32L5_IRQ_LPTIM3 (STM32L5_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ -#define STM32L5_IRQ_SPI3 (STM32L5_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ -#define STM32L5_IRQ_I2C4_EV (STM32L5_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ -#define STM32L5_IRQ_I2C4_ER (STM32L5_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT0 (STM32L5_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT1 (STM32L5_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT2 (STM32L5_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ -#define STM32L5_IRQ_DFSDM1_FLT3 (STM32L5_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ -#define STM32L5_IRQ_UCPD1 (STM32L5_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ -#define STM32L5_IRQ_ICACHE (STM32L5_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ -#define STM32L5_IRQ_OTFDEC1 (STM32L5_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD_PVM (STM32_IRQ_FIRST + 1) /* 1: PVD/PVM1/PVM2/PVM3/PVM4 */ +#define STM32_IRQ_RTC (STM32_IRQ_FIRST + 2) /* 2: RTC global interrupts */ +#define STM32_IRQ_RTC_S (STM32_IRQ_FIRST + 3) /* 3: RTC secure global interrupts */ +#define STM32_IRQ_TAMP (STM32_IRQ_FIRST + 4) /* 4: Tamper global interrupt */ +#define STM32_IRQ_TAMP_S (STM32_IRQ_FIRST + 5) /* 5: Tamper secure global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 6) /* 6: Flash memory global interrupt */ +#define STM32_IRQ_FLASH_S (STM32_IRQ_FIRST + 7) /* 7: Flash memory secure global interrupt */ +#define STM32_IRQ_GTZC (STM32_IRQ_FIRST + 8) /* 8: TZIC secure global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 9) /* 9: RCC global interrupt */ +#define STM32_IRQ_RCC_S (STM32_IRQ_FIRST + 10) /* 10: RCC secure global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 11) /* 11: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 12) /* 12: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 13) /* 13: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 14) /* 14: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 15) /* 15: EXTI Line 4 interrupt */ +#define STM32_IRQ_EXTI5 (STM32_IRQ_FIRST + 16) /* 16: EXTI Line 5 interrupt */ +#define STM32_IRQ_EXTI6 (STM32_IRQ_FIRST + 17) /* 17: EXTI Line 6 interrupt */ +#define STM32_IRQ_EXTI7 (STM32_IRQ_FIRST + 18) /* 18: EXTI Line 7 interrupt */ +#define STM32_IRQ_EXTI8 (STM32_IRQ_FIRST + 19) /* 19: EXTI Line 8 interrupt */ +#define STM32_IRQ_EXTI9 (STM32_IRQ_FIRST + 20) /* 20: EXTI Line 9 interrupt */ +#define STM32_IRQ_EXTI10 (STM32_IRQ_FIRST + 21) /* 21: EXTI Line 10 interrupt */ +#define STM32_IRQ_EXTI11 (STM32_IRQ_FIRST + 22) /* 22: EXTI Line 11 interrupt */ +#define STM32_IRQ_EXTI12 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line 12 interrupt */ +#define STM32_IRQ_EXTI13 (STM32_IRQ_FIRST + 24) /* 24: EXTI Line 13 interrupt */ +#define STM32_IRQ_EXTI14 (STM32_IRQ_FIRST + 25) /* 25: EXTI Line 14 interrupt */ +#define STM32_IRQ_EXTI15 (STM32_IRQ_FIRST + 26) /* 26: EXTI Line 15 interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 27) /* 27: DMAMUX1 overRun interrupt */ +#define STM32_IRQ_DMAMUX1_OVR_S (STM32_IRQ_FIRST + 28) /* 28: DMAMUX1 secure overRun interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 29) /* 29: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 30) /* 30: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 31) /* 31: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 32) /* 32: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 33) /* 33: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 34) /* 34: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 35) /* 35: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_DMA1CH8 (STM32_IRQ_FIRST + 36) /* 36: DMA1 Channel 8 global interrupt */ +#define STM32_IRQ_ADC1_2 (STM32_IRQ_FIRST + 37) /* 37: ADC1_2 global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 38) /* 38: DAC global interrupt */ +#define STM32_IRQ_FDCAN1_IT0 (STM32_IRQ_FIRST + 39) /* 39: FDCAN1_IT0: FDCAN1 Interrupt 0 */ +#define STM32_IRQ_FDCAN1_IT1 (STM32_IRQ_FIRST + 40) /* 40: FDCAN1_IT0: FDCAN1 Interrupt 1 */ +#define STM32_IRQ_TIM1_BRK (STM32_IRQ_FIRST + 41) /* 41: TIM1 break */ +#define STM32_IRQ_TIM1_UP (STM32_IRQ_FIRST + 42) /* 42: TIM1 update */ +#define STM32_IRQ_TIM1_TRG_COM (STM32_IRQ_FIRST + 43) /* 43: TIM1 trigger and communication */ +#define STM32_IRQ_TIM1_CC (STM32_IRQ_FIRST + 44) /* 44: TIM1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 45) /* 45: TIM2 global interrupt */ +#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 46) /* 46: TIM3 global interrupt */ +#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 47) /* 47: TIM4 global interrupt */ +#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 48) /* 48: TIM5 global interrupt */ +#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 49) /* 49: TIM6 global interrupt */ +#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 50) /* 50: TIM7 global interrupt */ +#define STM32_IRQ_TIM8_BRK (STM32_IRQ_FIRST + 51) /* 51: TIM8 break */ +#define STM32_IRQ_TIM8_UP (STM32_IRQ_FIRST + 52) /* 52: TIM8 update */ +#define STM32_IRQ_TIM8_TRG_COM (STM32_IRQ_FIRST + 53) /* 53: TIM8 trigger and communication */ +#define STM32_IRQ_TIM8_CC (STM32_IRQ_FIRST + 54) /* 54: TIM8 capture compare interrupt */ +#define STM32_IRQ_I2C1_EV (STM32_IRQ_FIRST + 55) /* 55: I2C1 event interrupt */ +#define STM32_IRQ_I2C1_ER (STM32_IRQ_FIRST + 56) /* 56: I2C1 error interrupt */ +#define STM32_IRQ_I2C2_EV (STM32_IRQ_FIRST + 57) /* 57: I2C2 event interrupt */ +#define STM32_IRQ_I2C2_ER (STM32_IRQ_FIRST + 58) /* 58: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 59) /* 59: SPI1 global interrupt */ +#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 60) /* 60: SPI2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 61) /* 61: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 62) /* 62: USART2 global interrupt */ +#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 63) /* 63: USART3 global interrupt */ +#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 64) /* 64: UART4 global interrupt */ +#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 65) /* 65: UART5 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 66) /* 66: LPUART 1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 67) /* 67: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 68) /* 68: LPTIM2 global interrupt */ +#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 69) /* 69: TIM15 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 70) /* 70: TIM16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ +#define STM32_IRQ_USB_FS (STM32_IRQ_FIRST + 73) /* 73: USB global interrupt */ +#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 74) /* 74: CRS global interrupt */ +#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 75) /* 75: FMC global interrupt */ +#define STM32_IRQ_OCTOSPI1 (STM32_IRQ_FIRST + 76) /* 76: OCTOSPI1 global interrupt */ + /* 77: Reserved */ +#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 78) /* 78: SDMMC1 global interrupt */ + /* 79: Reserved */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 80) /* 80: DMA2 Channel 1 global interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 81) /* 81: DMA2 Channel 2 global interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 82) /* 82: DMA2 Channel 3 global interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 83) /* 83: DMA2 Channel 4 global interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 84) /* 84: DMA2 Channel 5 global interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 85) /* 85: DMA2 Channel 6 global interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 86) /* 86: DMA2 Channel 7 global interrupt */ +#define STM32_IRQ_DMA2CH8 (STM32_IRQ_FIRST + 87) /* 87: DMA2 Channel 8 global interrupt */ +#define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 88) /* 88: I2C3 event interrupt */ +#define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 89) /* 89: I2C3 error interrupt */ +#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 90) /* 90: SAI1 global interrupt */ +#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */ +#define STM32_IRQ_TSC (STM32_IRQ_FIRST + 92) /* 92: TSC global interrupt */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 93) /* 93: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 94) /* 94: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 95) /* 95: FPU global interrupt */ +#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 96) /* 96: HASH global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 97) /* 97: PKA global interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 98) /* 98: LPTIM3 global interrupt */ +#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 99) /* 99: SPI3 global interrupt */ +#define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 100) /* 100: I2C4 event interrupt */ +#define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 101) /* 101: I2C4 error interrupt */ +#define STM32_IRQ_DFSDM1_FLT0 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 filter 0 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT1 (STM32_IRQ_FIRST + 103) /* 103: DFSDM1 filter 1 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT2 (STM32_IRQ_FIRST + 104) /* 104: DFSDM1 filter 2 global interrupt */ +#define STM32_IRQ_DFSDM1_FLT3 (STM32_IRQ_FIRST + 105) /* 105: DFSDM1 filter 3 global interrupt */ +#define STM32_IRQ_UCPD1 (STM32_IRQ_FIRST + 106) /* 106: UCPD1 global interrupt */ +#define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ +#define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_IRQ_NEXTINTS 109 +# define STM32_IRQ_NEXTINTS 109 #else # error "Unsupported STM32L5 chip" #endif /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32L5_IRQ_FIRST + STM32L5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) #endif /* __ARCH_ARM_INCLUDE_STM32L5_STM32L562XX_IRQ_H */ diff --git a/arch/arm/include/stm32l5/stm32l5_irq.h b/arch/arm/include/stm32l5/stm32l5_irq.h index 8ffbc2ac9a9..3e7709a902b 100644 --- a/arch/arm/include/stm32l5/stm32l5_irq.h +++ b/arch/arm/include/stm32l5/stm32l5_irq.h @@ -46,26 +46,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32L5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32L5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32L5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32L5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32L5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32L5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32L5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32L5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32L5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32L5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). * These definitions are chip-specific */ -#define STM32L5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32l5/chip.h b/arch/arm/src/stm32l5/chip.h index a8a0ea51390..33c22b102ca 100644 --- a/arch/arm/src/stm32l5/chip.h +++ b/arch/arm/src/stm32l5/chip.h @@ -48,6 +48,6 @@ * arch/stm32l5/chip.h header file. */ -#define ARMV8M_PERIPHERAL_INTERRUPTS STM32L5_IRQ_NEXTINTS +#define ARMV8M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS #endif /* __ARCH_ARM_SRC_STM32L5_CHIP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index 9f1f8865629..3e2b1449eb8 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -37,89 +37,89 @@ /* Register Offsets *********************************************************/ -#define STM32L5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32L5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32L5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32L5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32L5_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32L5_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ -#define STM32L5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32L5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32L5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32L5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32L5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32L5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32L5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32L5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32L5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32L5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32L5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32L5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32L5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32L5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32L5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32L5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32L5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32L5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32L5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32L5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32L5_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32L5_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ -#define STM32L5_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ -#define STM32L5_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ -#define STM32L5_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ -#define STM32L5_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ -#define STM32L5_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ -#define STM32L5_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ -#define STM32L5_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ -#define STM32L5_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_PLLSAI2CFG_OFFSET 0x0014 /* PLLSAI2 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_CCIPR2_OFFSET 0x009c /* Peripherals independent clock configuration register 2 */ +#define STM32_RCC_SECCFGR_OFFSET 0x00b8 /* Secure configuration register */ +#define STM32_RCC_SECSR_OFFSET 0x00bc /* Secure status register */ +#define STM32_RCC_AHB1SECSR_OFFSET 0x00e8 /* AHB1 security status register */ +#define STM32_RCC_AHB2SECSR_OFFSET 0x00ec /* AHB2 security status register */ +#define STM32_RCC_AHB3SECSR_OFFSET 0x00f0 /* AHB3 security status register */ +#define STM32_RCC_APB1SECSR1_OFFSET 0x00f8 /* APB1 security status register 1 */ +#define STM32_RCC_APB1SECSR2_OFFSET 0x00fc /* APB1 security status register 2 */ +#define STM32_RCC_APB2SECSR_OFFSET 0x0100 /* APB2 security status register */ /* Register Addresses *******************************************************/ -#define STM32L5_RCC_CR (STM32L5_RCC_BASE + STM32L5_RCC_CR_OFFSET) -#define STM32L5_RCC_ICSCR (STM32L5_RCC_BASE + STM32L5_RCC_ICSCR_OFFSET) -#define STM32L5_RCC_CFGR (STM32L5_RCC_BASE + STM32L5_RCC_CFGR_OFFSET) -#define STM32L5_RCC_PLLCFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLCFG_OFFSET) -#define STM32L5_RCC_PLLSAI1CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI1CFG_OFFSET) -#define STM32L5_RCC_PLLSAI2CFG (STM32L5_RCC_BASE + STM32L5_RCC_PLLSAI2CFG_OFFSET) -#define STM32L5_RCC_CIER (STM32L5_RCC_BASE + STM32L5_RCC_CIER_OFFSET) -#define STM32L5_RCC_CIFR (STM32L5_RCC_BASE + STM32L5_RCC_CIFR_OFFSET) -#define STM32L5_RCC_CICR (STM32L5_RCC_BASE + STM32L5_RCC_CICR_OFFSET) -#define STM32L5_RCC_AHB1RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1RSTR_OFFSET) -#define STM32L5_RCC_AHB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2RSTR_OFFSET) -#define STM32L5_RCC_AHB3RSTR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3RSTR_OFFSET) -#define STM32L5_RCC_APB1RSTR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR1_OFFSET) -#define STM32L5_RCC_APB1RSTR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1RSTR2_OFFSET) -#define STM32L5_RCC_APB2RSTR (STM32L5_RCC_BASE + STM32L5_RCC_APB2RSTR_OFFSET) -#define STM32L5_RCC_AHB1ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1ENR_OFFSET) -#define STM32L5_RCC_AHB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2ENR_OFFSET) -#define STM32L5_RCC_AHB3ENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3ENR_OFFSET) -#define STM32L5_RCC_APB1ENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR1_OFFSET) -#define STM32L5_RCC_APB1ENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1ENR2_OFFSET) -#define STM32L5_RCC_APB2ENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2ENR_OFFSET) -#define STM32L5_RCC_AHB1SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SMENR_OFFSET) -#define STM32L5_RCC_AHB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SMENR_OFFSET) -#define STM32L5_RCC_AHB3SMENR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SMENR_OFFSET) -#define STM32L5_RCC_APB1SMENR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR1_OFFSET) -#define STM32L5_RCC_APB1SMENR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SMENR2_OFFSET) -#define STM32L5_RCC_APB2SMENR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SMENR_OFFSET) -#define STM32L5_RCC_CCIPR (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR_OFFSET) -#define STM32L5_RCC_BDCR (STM32L5_RCC_BASE + STM32L5_RCC_BDCR_OFFSET) -#define STM32L5_RCC_CSR (STM32L5_RCC_BASE + STM32L5_RCC_CSR_OFFSET) -#define STM32L5_RCC_CRRCR (STM32L5_RCC_BASE + STM32L5_RCC_CRRCR_OFFSET) -#define STM32L5_RCC_CCIPR2 (STM32L5_RCC_BASE + STM32L5_RCC_CCIPR2_OFFSET) -#define STM32L5_RCC_SECCFGR (STM32L5_RCC_BASE + STM32L5_RCC_SECCFGR_OFFSET) -#define STM32L5_RCC_SECSR (STM32L5_RCC_BASE + STM32L5_RCC_SECSR_OFFSET) -#define STM32L5_RCC_AHB1SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB1SECSR_OFFSET) -#define STM32L5_RCC_AHB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB2SECSR_OFFSET) -#define STM32L5_RCC_AHB3SECSR (STM32L5_RCC_BASE + STM32L5_RCC_AHB3SECSR_OFFSET) -#define STM32L5_RCC_APB1SECSR1 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR1_OFFSET) -#define STM32L5_RCC_APB1SECSR2 (STM32L5_RCC_BASE + STM32L5_RCC_APB1SECSR2_OFFSET) -#define STM32L5_RCC_APB2SECSR (STM32L5_RCC_BASE + STM32L5_RCC_APB2SECSR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_PLLSAI2CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI2CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_CCIPR2 (STM32_RCC_BASE + STM32_RCC_CCIPR2_OFFSET) +#define STM32_RCC_SECCFGR (STM32_RCC_BASE + STM32_RCC_SECCFGR_OFFSET) +#define STM32_RCC_SECSR (STM32_RCC_BASE + STM32_RCC_SECSR_OFFSET) +#define STM32_RCC_AHB1SECSR (STM32_RCC_BASE + STM32_RCC_AHB1SECSR_OFFSET) +#define STM32_RCC_AHB2SECSR (STM32_RCC_BASE + STM32_RCC_AHB2SECSR_OFFSET) +#define STM32_RCC_AHB3SECSR (STM32_RCC_BASE + STM32_RCC_AHB3SECSR_OFFSET) +#define STM32_RCC_APB1SECSR1 (STM32_RCC_BASE + STM32_RCC_APB1SECSR1_OFFSET) +#define STM32_RCC_APB1SECSR2 (STM32_RCC_BASE + STM32_RCC_APB1SECSR2_OFFSET) +#define STM32_RCC_APB2SECSR (STM32_RCC_BASE + STM32_RCC_APB2SECSR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h index db365f94974..fd82d211a58 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h @@ -38,31 +38,31 @@ /* Register Offsets *********************************************************/ -#define STM32L5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32L5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32L5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32L5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32L5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32L5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32L5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32L5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32L5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32L5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32L5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32L5_SYSCFG_SECCFGR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SECCFGR_OFFSET) -#define STM32L5_SYSCFG_CFGR1 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR1_OFFSET) -#define STM32L5_SYSCFG_FPUIMR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_FPUIMR_OFFSET) -#define STM32L5_SYSCFG_CNSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CNSLCKR_OFFSET) -#define STM32L5_SYSCFG_CSLCKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CSLCKR_OFFSET) -#define STM32L5_SYSCFG_CFGR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_CFGR2_OFFSET) -#define STM32L5_SYSCFG_SCSR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SCSR_OFFSET) -#define STM32L5_SYSCFG_SKR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SKR_OFFSET) -#define STM32L5_SYSCFG_SWPR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR_OFFSET) -#define STM32L5_SYSCFG_SWPR2 (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_SWPR2_OFFSET) -#define STM32L5_SYSCFG_RSSCMDR (STM32L5_SYSCFG_BASE + STM32L5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h index b321ad3f4cc..11b113e55e5 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_exti.h @@ -36,55 +36,55 @@ /* Register Offsets *********************************************************/ -#define STM32L5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ -#define STM32L5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ -#define STM32L5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ -#define STM32L5_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ -#define STM32L5_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ -#define STM32L5_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ -#define STM32L5_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ -#define STM32L5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ -#define STM32L5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ -#define STM32L5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ -#define STM32L5_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ -#define STM32L5_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ -#define STM32L5_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ -#define STM32L5_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ -#define STM32L5_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ -#define STM32L5_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ -#define STM32L5_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ -#define STM32L5_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ -#define STM32L5_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ -#define STM32L5_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ -#define STM32L5_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ -#define STM32L5_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ -#define STM32L5_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */ +#define STM32_EXTI_RPR1_OFFSET 0x000c /* Rising Edge Pending 1 */ +#define STM32_EXTI_FPR1_OFFSET 0x0010 /* Falling Edge Pending 1 */ +#define STM32_EXTI_SECCFGR1_OFFSET 0x0014 /* Security Configuration 1 */ +#define STM32_EXTI_PRIVCFGR1_OFFSET 0x0018 /* Privilege Configuration 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */ +#define STM32_EXTI_RPR2_OFFSET 0x002c /* Rising Edge Pending 2 */ +#define STM32_EXTI_FPR2_OFFSET 0x0030 /* Falling Edge Pending 2 */ +#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */ +#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */ +#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */ +#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */ +#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */ +#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */ +#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */ +#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */ +#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */ +#define STM32_EXTI_IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 */ +#define STM32_EXTI_EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 */ /* Register Addresses *******************************************************/ -#define STM32L5_EXTI_RTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR1_OFFSET) -#define STM32L5_EXTI_FTSR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR1_OFFSET) -#define STM32L5_EXTI_SWIER1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER1_OFFSET) -#define STM32L5_EXTI_RPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR1_OFFSET) -#define STM32L5_EXTI_FPR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR1_OFFSET) -#define STM32L5_EXTI_SECCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR1_OFFSET) -#define STM32L5_EXTI_PRIVCFGR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR1_OFFSET) -#define STM32L5_EXTI_RTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RTSR2_OFFSET) -#define STM32L5_EXTI_FTSR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FTSR2_OFFSET) -#define STM32L5_EXTI_SWIER2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SWIER2_OFFSET) -#define STM32L5_EXTI_RPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_RPR2_OFFSET) -#define STM32L5_EXTI_FPR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_FPR2_OFFSET) -#define STM32L5_EXTI_SECCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_SECCFGR2_OFFSET) -#define STM32L5_EXTI_PRIVCFGR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_PRIVCFGR2_OFFSET) -#define STM32L5_EXTI_EXTICR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR1_OFFSET) -#define STM32L5_EXTI_EXTICR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR2_OFFSET) -#define STM32L5_EXTI_EXTICR3 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR3_OFFSET) -#define STM32L5_EXTI_EXTICR4 (STM32L5_EXTI_BASE + STM32L5_EXTI_EXTICR4_OFFSET) -#define STM32L5_EXTI_LOCKR (STM32L5_EXTI_BASE + STM32L5_EXTI_LOCKR_OFFSET) -#define STM32L5_EXTI_IMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR1_OFFSET) -#define STM32L5_EXTI_EMR1 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR1_OFFSET) -#define STM32L5_EXTI_IMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_IMR2_OFFSET) -#define STM32L5_EXTI_EMR2 (STM32L5_EXTI_BASE + STM32L5_EXTI_EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_RPR1 (STM32_EXTI_BASE + STM32_EXTI_RPR1_OFFSET) +#define STM32_EXTI_FPR1 (STM32_EXTI_BASE + STM32_EXTI_FPR1_OFFSET) +#define STM32_EXTI_SECCFGR1 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR1_OFFSET) +#define STM32_EXTI_PRIVCFGR1 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_RPR2 (STM32_EXTI_BASE + STM32_EXTI_RPR2_OFFSET) +#define STM32_EXTI_FPR2 (STM32_EXTI_BASE + STM32_EXTI_FPR2_OFFSET) +#define STM32_EXTI_SECCFGR2 (STM32_EXTI_BASE + STM32_EXTI_SECCFGR2_OFFSET) +#define STM32_EXTI_PRIVCFGR2 (STM32_EXTI_BASE + STM32_EXTI_PRIVCFGR2_OFFSET) +#define STM32_EXTI_EXTICR1 (STM32_EXTI_BASE + STM32_EXTI_EXTICR1_OFFSET) +#define STM32_EXTI_EXTICR2 (STM32_EXTI_BASE + STM32_EXTI_EXTICR2_OFFSET) +#define STM32_EXTI_EXTICR3 (STM32_EXTI_BASE + STM32_EXTI_EXTICR3_OFFSET) +#define STM32_EXTI_EXTICR4 (STM32_EXTI_BASE + STM32_EXTI_EXTICR4_OFFSET) +#define STM32_EXTI_LOCKR (STM32_EXTI_BASE + STM32_EXTI_LOCKR_OFFSET) +#define STM32_EXTI_IMR1 (STM32_EXTI_BASE + STM32_EXTI_IMR1_OFFSET) +#define STM32_EXTI_EMR1 (STM32_EXTI_BASE + STM32_EXTI_EMR1_OFFSET) +#define STM32_EXTI_IMR2 (STM32_EXTI_BASE + STM32_EXTI_IMR2_OFFSET) +#define STM32_EXTI_EMR2 (STM32_EXTI_BASE + STM32_EXTI_EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index 3f9c343e0e7..4020e680781 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -70,90 +70,90 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32L5_FLASH_NPAGES 64 -# define STM32L5_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 4096 #elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32L5_FLASH_NPAGES 128 -# define STM32L5_FLASH_PAGESIZE 4096 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 4096 #else # error "unknown flash configuration!" #endif -#ifdef STM32L5_FLASH_PAGESIZE -# define STM32L5_FLASH_SIZE (STM32L5_FLASH_NPAGES * STM32L5_FLASH_PAGESIZE) +#ifdef STM32_FLASH_PAGESIZE +# define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif /* Register Offsets *********************************************************/ -#define STM32L5_FLASH_ACR_OFFSET 0x0000 -#define STM32L5_FLASH_PDKEYR_OFFSET 0x0004 -#define STM32L5_FLASH_NSKEYR_OFFSET 0x0008 -#define STM32L5_FLASH_SECKEYR_OFFSET 0x000c -#define STM32L5_FLASH_OPTKEYR_OFFSET 0x0010 -#define STM32L5_FLASH_LVEKEYR_OFFSET 0x0014 -#define STM32L5_FLASH_NSSR_OFFSET 0x0020 -#define STM32L5_FLASH_SECSR_OFFSET 0x0024 -#define STM32L5_FLASH_NSCR_OFFSET 0x0028 -#define STM32L5_FLASH_SECCR_OFFSET 0x002c -#define STM32L5_FLASH_ECCR_OFFSET 0x0030 -#define STM32L5_FLASH_OPTR_OFFSET 0x0040 -#define STM32L5_FLASH_NSBOOTADDR0R_OFFSET 0x0044 -#define STM32L5_FLASH_NSBOOTADDR1R_OFFSET 0x0048 -#define STM32L5_FLASH_SECBOOTADDR0R_OFFSET 0x004c -#define STM32L5_FLASH_SECWM1R1_OFFSET 0x0050 -#define STM32L5_FLASH_SECWM1R2_OFFSET 0x0054 -#define STM32L5_FLASH_WRP1AR_OFFSET 0x0058 -#define STM32L5_FLASH_WRP1BR_OFFSET 0x005c -#define STM32L5_FLASH_SECWM2R1_OFFSET 0x0060 -#define STM32L5_FLASH_SECWM2R2_OFFSET 0x0064 -#define STM32L5_FLASH_WRP2AR_OFFSET 0x0068 -#define STM32L5_FLASH_WRP2BR_OFFSET 0x006c -#define STM32L5_FLASH_SECBB1R1_OFFSET 0x0080 -#define STM32L5_FLASH_SECBB1R2_OFFSET 0x0084 -#define STM32L5_FLASH_SECBB1R3_OFFSET 0x0088 -#define STM32L5_FLASH_SECBB1R4_OFFSET 0x008c -#define STM32L5_FLASH_SECBB2R1_OFFSET 0x00a0 -#define STM32L5_FLASH_SECBB2R2_OFFSET 0x00a4 -#define STM32L5_FLASH_SECBB2R3_OFFSET 0x00a8 -#define STM32L5_FLASH_SECBB2R4_OFFSET 0x00ac -#define STM32L5_FLASH_SECHDPCR_OFFSET 0x00c0 -#define STM32L5_FLASH_PRIVCFGR_OFFSET 0x00c4 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_PDKEYR_OFFSET 0x0004 +#define STM32_FLASH_NSKEYR_OFFSET 0x0008 +#define STM32_FLASH_SECKEYR_OFFSET 0x000c +#define STM32_FLASH_OPTKEYR_OFFSET 0x0010 +#define STM32_FLASH_LVEKEYR_OFFSET 0x0014 +#define STM32_FLASH_NSSR_OFFSET 0x0020 +#define STM32_FLASH_SECSR_OFFSET 0x0024 +#define STM32_FLASH_NSCR_OFFSET 0x0028 +#define STM32_FLASH_SECCR_OFFSET 0x002c +#define STM32_FLASH_ECCR_OFFSET 0x0030 +#define STM32_FLASH_OPTR_OFFSET 0x0040 +#define STM32_FLASH_NSBOOTADDR0R_OFFSET 0x0044 +#define STM32_FLASH_NSBOOTADDR1R_OFFSET 0x0048 +#define STM32_FLASH_SECBOOTADDR0R_OFFSET 0x004c +#define STM32_FLASH_SECWM1R1_OFFSET 0x0050 +#define STM32_FLASH_SECWM1R2_OFFSET 0x0054 +#define STM32_FLASH_WRP1AR_OFFSET 0x0058 +#define STM32_FLASH_WRP1BR_OFFSET 0x005c +#define STM32_FLASH_SECWM2R1_OFFSET 0x0060 +#define STM32_FLASH_SECWM2R2_OFFSET 0x0064 +#define STM32_FLASH_WRP2AR_OFFSET 0x0068 +#define STM32_FLASH_WRP2BR_OFFSET 0x006c +#define STM32_FLASH_SECBB1R1_OFFSET 0x0080 +#define STM32_FLASH_SECBB1R2_OFFSET 0x0084 +#define STM32_FLASH_SECBB1R3_OFFSET 0x0088 +#define STM32_FLASH_SECBB1R4_OFFSET 0x008c +#define STM32_FLASH_SECBB2R1_OFFSET 0x00a0 +#define STM32_FLASH_SECBB2R2_OFFSET 0x00a4 +#define STM32_FLASH_SECBB2R3_OFFSET 0x00a8 +#define STM32_FLASH_SECBB2R4_OFFSET 0x00ac +#define STM32_FLASH_SECHDPCR_OFFSET 0x00c0 +#define STM32_FLASH_PRIVCFGR_OFFSET 0x00c4 /* Register Addresses *******************************************************/ -#define STM32L5_FLASH_ACR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ACR_OFFSET) -#define STM32L5_FLASH_PDKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PDKEYR_OFFSET) -#define STM32L5_FLASH_NSKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSKEYR_OFFSET) -#define STM32L5_FLASH_SECKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECKEYR_OFFSET) -#define STM32L5_FLASH_OPTKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTKEYR_OFFSET) -#define STM32L5_FLASH_LVEKEYR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_LVEKEYR_OFFSET) -#define STM32L5_FLASH_NSSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSSR_OFFSET) -#define STM32L5_FLASH_SECSR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECSR_OFFSET) -#define STM32L5_FLASH_NSCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSCR_OFFSET) -#define STM32L5_FLASH_SECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECCR_OFFSET) -#define STM32L5_FLASH_ECCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_ECCR_OFFSET) -#define STM32L5_FLASH_OPTR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_OPTR_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_NSBOOTADDR1R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_NSBOOTADDR1R_OFFSET) -#define STM32L5_FLASH_SECBOOTADDR0R (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBOOTADDR0R_OFFSET) -#define STM32L5_FLASH_SECWM1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R1_OFFSET) -#define STM32L5_FLASH_SECWM1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM1R2_OFFSET) -#define STM32L5_FLASH_WRP1AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1AR_OFFSET) -#define STM32L5_FLASH_WRP1BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP1BR_OFFSET) -#define STM32L5_FLASH_SECWM2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R1_OFFSET) -#define STM32L5_FLASH_SECWM2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECWM2R2_OFFSET) -#define STM32L5_FLASH_WRP2AR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2AR_OFFSET) -#define STM32L5_FLASH_WRP2BR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_WRP2BR_OFFSET) -#define STM32L5_FLASH_SECBB1R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R1_OFFSET) -#define STM32L5_FLASH_SECBB1R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R2_OFFSET) -#define STM32L5_FLASH_SECBB1R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R3_OFFSET) -#define STM32L5_FLASH_SECBB1R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB1R4_OFFSET) -#define STM32L5_FLASH_SECBB2R1 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R1_OFFSET) -#define STM32L5_FLASH_SECBB2R2 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R2_OFFSET) -#define STM32L5_FLASH_SECBB2R3 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R3_OFFSET) -#define STM32L5_FLASH_SECBB2R4 (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECBB2R4_OFFSET) -#define STM32L5_FLASH_SECHDPCR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_SECHDPCR_OFFSET) -#define STM32L5_FLASH_PRIVCFGR (STM32L5_FLASHIF_BASE + STM32L5_FLASH_PRIVCFGR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_PDKEYR (STM32_FLASHIF_BASE + STM32_FLASH_PDKEYR_OFFSET) +#define STM32_FLASH_NSKEYR (STM32_FLASHIF_BASE + STM32_FLASH_NSKEYR_OFFSET) +#define STM32_FLASH_SECKEYR (STM32_FLASHIF_BASE + STM32_FLASH_SECKEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_LVEKEYR (STM32_FLASHIF_BASE + STM32_FLASH_LVEKEYR_OFFSET) +#define STM32_FLASH_NSSR (STM32_FLASHIF_BASE + STM32_FLASH_NSSR_OFFSET) +#define STM32_FLASH_SECSR (STM32_FLASHIF_BASE + STM32_FLASH_SECSR_OFFSET) +#define STM32_FLASH_NSCR (STM32_FLASHIF_BASE + STM32_FLASH_NSCR_OFFSET) +#define STM32_FLASH_SECCR (STM32_FLASHIF_BASE + STM32_FLASH_SECCR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_NSBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR0R_OFFSET) +#define STM32_FLASH_NSBOOTADDR1R (STM32_FLASHIF_BASE + STM32_FLASH_NSBOOTADDR1R_OFFSET) +#define STM32_FLASH_SECBOOTADDR0R (STM32_FLASHIF_BASE + STM32_FLASH_SECBOOTADDR0R_OFFSET) +#define STM32_FLASH_SECWM1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R1_OFFSET) +#define STM32_FLASH_SECWM1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM1R2_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_SECWM2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R1_OFFSET) +#define STM32_FLASH_SECWM2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECWM2R2_OFFSET) +#define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2AR_OFFSET) +#define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE + STM32_FLASH_WRP2BR_OFFSET) +#define STM32_FLASH_SECBB1R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R1_OFFSET) +#define STM32_FLASH_SECBB1R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R2_OFFSET) +#define STM32_FLASH_SECBB1R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R3_OFFSET) +#define STM32_FLASH_SECBB1R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB1R4_OFFSET) +#define STM32_FLASH_SECBB2R1 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R1_OFFSET) +#define STM32_FLASH_SECBB2R2 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R2_OFFSET) +#define STM32_FLASH_SECBB2R3 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R3_OFFSET) +#define STM32_FLASH_SECBB2R4 (STM32_FLASHIF_BASE + STM32_FLASH_SECBB2R4_OFFSET) +#define STM32_FLASH_SECHDPCR (STM32_FLASHIF_BASE + STM32_FLASH_SECHDPCR_OFFSET) +#define STM32_FLASH_PRIVCFGR (STM32_FLASHIF_BASE + STM32_FLASH_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h index 0037ae1ad08..7b4d880bca0 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_gpio.h @@ -36,154 +36,154 @@ /* Register Offsets *********************************************************/ -#define STM32L5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32L5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32L5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32L5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32L5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32L5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32L5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32L5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32L5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32L5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32L5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ -#define STM32L5_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_SECCFGR_OFFSET 0x0030 /* GPIO secure configuration register */ /* Register Addresses *******************************************************/ -#if STM32L5_NPORTS > 0 -# define STM32L5_GPIOA_MODER (STM32L5_GPIOA_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOA_OTYPER (STM32L5_GPIOA_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOA_OSPEED (STM32L5_GPIOA_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOA_PUPDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOA_IDR (STM32L5_GPIOA_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOA_ODR (STM32L5_GPIOA_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOA_BSRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOA_LCKR (STM32L5_GPIOA_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOA_AFRL (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOA_AFRH (STM32L5_GPIOA_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOA_BRR (STM32L5_GPIOA_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOA_SECCFGR (STM32L5_GPIOA_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 0 +# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 1 -# define STM32L5_GPIOB_MODER (STM32L5_GPIOB_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOB_OTYPER (STM32L5_GPIOB_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOB_OSPEED (STM32L5_GPIOB_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOB_PUPDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOB_IDR (STM32L5_GPIOB_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOB_ODR (STM32L5_GPIOB_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOB_BSRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOB_LCKR (STM32L5_GPIOB_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOB_AFRL (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOB_AFRH (STM32L5_GPIOB_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOB_BRR (STM32L5_GPIOB_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOB_SECCFGR (STM32L5_GPIOB_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 1 +# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 2 -# define STM32L5_GPIOC_MODER (STM32L5_GPIOC_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOC_OTYPER (STM32L5_GPIOC_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOC_OSPEED (STM32L5_GPIOC_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOC_PUPDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOC_IDR (STM32L5_GPIOC_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOC_ODR (STM32L5_GPIOC_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOC_BSRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOC_LCKR (STM32L5_GPIOC_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOC_AFRL (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOC_AFRH (STM32L5_GPIOC_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOC_BRR (STM32L5_GPIOC_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOC_SECCFGR (STM32L5_GPIOC_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 2 +# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 3 -# define STM32L5_GPIOD_MODER (STM32L5_GPIOD_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOD_OTYPER (STM32L5_GPIOD_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOD_OSPEED (STM32L5_GPIOD_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOD_PUPDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOD_IDR (STM32L5_GPIOD_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOD_ODR (STM32L5_GPIOD_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOD_BSRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOD_LCKR (STM32L5_GPIOD_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOD_AFRL (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOD_AFRH (STM32L5_GPIOD_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOD_BRR (STM32L5_GPIOD_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOD_SECCFGR (STM32L5_GPIOD_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 3 +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 4 -# define STM32L5_GPIOE_MODER (STM32L5_GPIOE_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOE_OTYPER (STM32L5_GPIOE_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOE_OSPEED (STM32L5_GPIOE_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOE_PUPDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOE_IDR (STM32L5_GPIOE_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOE_ODR (STM32L5_GPIOE_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOE_BSRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOE_LCKR (STM32L5_GPIOE_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOE_AFRL (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOE_AFRH (STM32L5_GPIOE_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOE_BRR (STM32L5_GPIOE_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOE_SECCFGR (STM32L5_GPIOE_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 4 +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_AFRH (STM32_GPIOE_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 5 -# define STM32L5_GPIOF_MODER (STM32L5_GPIOF_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOF_OTYPER (STM32L5_GPIOF_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOF_OSPEED (STM32L5_GPIOF_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOF_PUPDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOF_IDR (STM32L5_GPIOF_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOF_ODR (STM32L5_GPIOF_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOF_BSRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOF_LCKR (STM32L5_GPIOF_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOF_AFRL (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOF_AFRH (STM32L5_GPIOF_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOF_BRR (STM32L5_GPIOF_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOF_SECCFGR (STM32L5_GPIOF_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 5 +# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOF_PUPDR (STM32_GPIOF_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOF_IDR (STM32_GPIOF_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOF_ODR (STM32_GPIOF_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOF_AFRL (STM32_GPIOF_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOF_AFRH (STM32_GPIOF_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOF_BRR (STM32_GPIOF_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 6 -# define STM32L5_GPIOG_MODER (STM32L5_GPIOG_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOG_OTYPER (STM32L5_GPIOG_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOG_OSPEED (STM32L5_GPIOG_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOG_PUPDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOG_IDR (STM32L5_GPIOG_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOG_ODR (STM32L5_GPIOG_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOG_BSRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOG_LCKR (STM32L5_GPIOG_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOG_AFRL (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOG_AFRH (STM32L5_GPIOG_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOG_BRR (STM32L5_GPIOG_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOG_SECCFGR (STM32L5_GPIOG_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 6 +# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOG_PUPDR (STM32_GPIOG_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOG_IDR (STM32_GPIOG_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOG_ODR (STM32_GPIOG_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOG_AFRL (STM32_GPIOG_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOG_AFRH (STM32_GPIOG_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOG_BRR (STM32_GPIOG_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 7 -# define STM32L5_GPIOH_MODER (STM32L5_GPIOH_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOH_OTYPER (STM32L5_GPIOH_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOH_OSPEED (STM32L5_GPIOH_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOH_PUPDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOH_IDR (STM32L5_GPIOH_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOH_ODR (STM32L5_GPIOH_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOH_BSRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOH_LCKR (STM32L5_GPIOH_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOH_AFRL (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOH_AFRH (STM32L5_GPIOH_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOH_BRR (STM32L5_GPIOH_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOH_SECCFGR (STM32L5_GPIOH_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 7 +# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOH_AFRH (STM32_GPIOH_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif -#if STM32L5_NPORTS > 8 -# define STM32L5_GPIOI_MODER (STM32L5_GPIOI_BASE + STM32L5_GPIO_MODER_OFFSET) -# define STM32L5_GPIOI_OTYPER (STM32L5_GPIOI_BASE + STM32L5_GPIO_OTYPER_OFFSET) -# define STM32L5_GPIOI_OSPEED (STM32L5_GPIOI_BASE + STM32L5_GPIO_OSPEED_OFFSET) -# define STM32L5_GPIOI_PUPDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_PUPDR_OFFSET) -# define STM32L5_GPIOI_IDR (STM32L5_GPIOI_BASE + STM32L5_GPIO_IDR_OFFSET) -# define STM32L5_GPIOI_ODR (STM32L5_GPIOI_BASE + STM32L5_GPIO_ODR_OFFSET) -# define STM32L5_GPIOI_BSRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BSRR_OFFSET) -# define STM32L5_GPIOI_LCKR (STM32L5_GPIOI_BASE + STM32L5_GPIO_LCKR_OFFSET) -# define STM32L5_GPIOI_AFRL (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRL_OFFSET) -# define STM32L5_GPIOI_AFRH (STM32L5_GPIOI_BASE + STM32L5_GPIO_AFRH_OFFSET) -# define STM32L5_GPIOI_BRR (STM32L5_GPIOI_BASE + STM32L5_GPIO_BRR_OFFSET) -# define STM32L5_GPIOI_SECCFGR (STM32L5_GPIOI_BASE + STM32L5_GPIO_SECCFGR_OFFSET) +#if STM32_NPORTS > 8 +# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOI_PUPDR (STM32_GPIOI_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOI_IDR (STM32_GPIOI_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOI_ODR (STM32_GPIOI_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOI_BSRR (STM32_GPIOI_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOI_LCKR (STM32_GPIOI_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOI_AFRL (STM32_GPIOI_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOI_AFRH (STM32_GPIOI_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOI_BRR (STM32_GPIOI_BASE + STM32_GPIO_BRR_OFFSET) +# define STM32_GPIOI_SECCFGR (STM32_GPIOI_BASE + STM32_GPIO_SECCFGR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h index 4fefb89201f..b697627f594 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_memorymap.h @@ -29,127 +29,127 @@ /* STM32L5XXX Address Blocks ************************************************/ -#define STM32L5_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L5_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ -#define STM32L5_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ -#define STM32L5_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ -# define STM32L5_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ -#define STM32L5_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ -# define STM32L5_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ -# define STM32L5_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ -#define STM32L5_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ +#define STM32_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ +# define STM32_FMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ +#define STM32_FSMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FSMC bank3 / QSPI block */ +# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */ +# define STM32_OCTOSPI1_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI */ +#define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ -#define STM32L5_REGION_MASK 0xF0000000 -#define STM32L5_IS_SRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_SRAM_BASE) -#define STM32L5_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32L5_REGION_MASK) == STM32L5_FMC_BANK1) +#define STM32_REGION_MASK 0xF0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ -#define STM32L5_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32L5_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ -#define STM32L5_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ -#define STM32L5_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x0807ffff: FLASH memory */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ +#define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32L5_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ -#define STM32L5_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ -#define STM32L5_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ +#define STM32_SYSMEM_UID 0x0BFA0590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x0BFA05E0 /* Size of Flash memory in Kbytes. */ +#define STM32_SYSMEM_PACKAGE 0x0BFA0500 /* Indicates the device's package type. */ /* Peripheral Base Addresses ************************************************/ -#define STM32L5_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ -#define STM32L5_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ -#define STM32L5_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ -#define STM32L5_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ -#define STM32L5_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x4000dfff: APB1 */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400167ff: APB2 */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400333ff: AHB1 */ +#define STM32_AHB2_BASE 0x42020000 /* 0x42020000-0x420c83ff: AHB2 */ +#define STM32_AHB3_BASE 0x44020000 /* 0x44020000-0x440213ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32L5_UCPD1_BASE 0x4000DC00 -#define STM32L5_USB_SRAM_BASE 0x4000D800 -#define STM32L5_USB_FS_BASE 0x4000D400 -#define STM32L5_FDCAN_RAM_BASE 0x4000AC00 -#define STM32L5_FDCAN1_BASE 0x4000A400 -#define STM32L5_LPTIM3_BASE 0x40009800 -#define STM32L5_LPTIM2_BASE 0x40009400 -#define STM32L5_I2C4_BASE 0x40008400 -#define STM32L5_LPUART1_BASE 0x40008000 -#define STM32L5_LPTIM1_BASE 0x40007C00 -#define STM32L5_OPAMP_BASE 0x40007800 -#define STM32L5_DAC_BASE 0x40007400 -#define STM32L5_PWR_BASE 0x40007000 -#define STM32L5_CRS_BASE 0x40006000 -#define STM32L5_I2C3_BASE 0x40005C00 -#define STM32L5_I2C2_BASE 0x40005800 -#define STM32L5_I2C1_BASE 0x40005400 -#define STM32L5_UART5_BASE 0x40005000 -#define STM32L5_UART4_BASE 0x40004C00 -#define STM32L5_USART3_BASE 0x40004800 -#define STM32L5_USART2_BASE 0x40004400 -#define STM32L5_SPI3_BASE 0x40003C00 -#define STM32L5_SPI2_BASE 0x40003800 -#define STM32L5_TAMP_BASE 0x40003400 -#define STM32L5_IWDG_BASE 0x40003000 -#define STM32L5_WWDG_BASE 0x40002C00 -#define STM32L5_RTC_BASE 0x40002800 -#define STM32L5_TIM7_BASE 0x40001400 -#define STM32L5_TIM6_BASE 0x40001000 -#define STM32L5_TIM5_BASE 0x40000C00 -#define STM32L5_TIM4_BASE 0x40000800 -#define STM32L5_TIM3_BASE 0x40000400 -#define STM32L5_TIM2_BASE 0x40000000 +#define STM32_UCPD1_BASE 0x4000DC00 +#define STM32_USB_SRAM_BASE 0x4000D800 +#define STM32_USB_FS_BASE 0x4000D400 +#define STM32_FDCAN_RAM_BASE 0x4000AC00 +#define STM32_FDCAN1_BASE 0x4000A400 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_I2C4_BASE 0x40008400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_OPAMP_BASE 0x40007800 +#define STM32_DAC_BASE 0x40007400 +#define STM32_PWR_BASE 0x40007000 +#define STM32_CRS_BASE 0x40006000 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_UART5_BASE 0x40005000 +#define STM32_UART4_BASE 0x40004C00 +#define STM32_USART3_BASE 0x40004800 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI3_BASE 0x40003C00 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_TAMP_BASE 0x40003400 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM7_BASE 0x40001400 +#define STM32_TIM6_BASE 0x40001000 +#define STM32_TIM5_BASE 0x40000C00 +#define STM32_TIM4_BASE 0x40000800 +#define STM32_TIM3_BASE 0x40000400 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32L5_DFSDM1_BASE 0x40016000 -#define STM32L5_SAI2_BASE 0x40015800 -#define STM32L5_SAI1_BASE 0x40015400 -#define STM32L5_TIM17_BASE 0x40014800 -#define STM32L5_TIM16_BASE 0x40014400 -#define STM32L5_TIM15_BASE 0x40014000 -#define STM32L5_USART1_BASE 0x40013800 -#define STM32L5_TIM8_BASE 0x40013400 -#define STM32L5_SPI1_BASE 0x40013000 -#define STM32L5_TIM1_BASE 0x40012C00 -#define STM32L5_COMP_BASE 0x40010200 -#define STM32L5_VREFBUF_BASE 0x40010100 -#define STM32L5_SYSCFG_BASE 0x40010000 +#define STM32_DFSDM1_BASE 0x40016000 +#define STM32_SAI2_BASE 0x40015800 +#define STM32_SAI1_BASE 0x40015400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM15_BASE 0x40014000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM8_BASE 0x40013400 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_COMP_BASE 0x40010200 +#define STM32_VREFBUF_BASE 0x40010100 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32L5_GTZC_BASE 0x40032400 -#define STM32L5_ICACHE_BASE 0x40030400 -#define STM32L5_EXTI_BASE 0x4002F400 -#define STM32L5_TSC_BASE 0x40024000 -#define STM32L5_CRC_BASE 0x40023000 -#define STM32L5_FLASHIF_BASE 0x40022000 -#define STM32L5_RCC_BASE 0x40021000 -#define STM32L5_DMAMUX1_BASE 0x40020800 -#define STM32L5_DMA2_BASE 0x40020400 -#define STM32L5_DMA1_BASE 0x40020000 +#define STM32_GTZC_BASE 0x40032400 +#define STM32_ICACHE_BASE 0x40030400 +#define STM32_EXTI_BASE 0x4002F400 +#define STM32_TSC_BASE 0x40024000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_FLASHIF_BASE 0x40022000 +#define STM32_RCC_BASE 0x40021000 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_SDMMC1_BASE 0x420C8000 -#define STM32L5_OTFDEC1_BASE 0x420C5000 -#define STM32L5_PKA_BASE 0x420C2000 -#define STM32L5_RNG_BASE 0x420C0800 -#define STM32L5_HASH_BASE 0x420C0400 -#define STM32L5_AES_BASE 0x420C0000 -#define STM32L5_ADC_BASE 0x42028000 -#define STM32L5_GPIOH_BASE 0x42021C00 -#define STM32L5_GPIOG_BASE 0x42021800 -#define STM32L5_GPIOF_BASE 0x42021400 -#define STM32L5_GPIOE_BASE 0x42021000 -#define STM32L5_GPIOD_BASE 0x42020c00 -#define STM32L5_GPIOC_BASE 0x42020800 -#define STM32L5_GPIOB_BASE 0x42020400 -#define STM32L5_GPIOA_BASE 0x42020000 +#define STM32_SDMMC1_BASE 0x420C8000 +#define STM32_OTFDEC1_BASE 0x420C5000 +#define STM32_PKA_BASE 0x420C2000 +#define STM32_RNG_BASE 0x420C0800 +#define STM32_HASH_BASE 0x420C0400 +#define STM32_AES_BASE 0x420C0000 +#define STM32_ADC_BASE 0x42028000 +#define STM32_GPIOH_BASE 0x42021C00 +#define STM32_GPIOG_BASE 0x42021800 +#define STM32_GPIOF_BASE 0x42021400 +#define STM32_GPIOE_BASE 0x42021000 +#define STM32_GPIOD_BASE 0x42020c00 +#define STM32_GPIOC_BASE 0x42020800 +#define STM32_GPIOB_BASE 0x42020400 +#define STM32_GPIOA_BASE 0x42020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32L5_OCTOSPI1_BASE 0x44021000 -#define STM32L5_FMC_BASE 0x44020000 +#define STM32_OCTOSPI1_BASE 0x44021000 +#define STM32_FMC_BASE 0x44020000 #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L5_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h index 44cbde1b598..9ef6dc03f31 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pwr.h @@ -36,59 +36,59 @@ /* Register Offsets *********************************************************/ -#define STM32L5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32L5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32L5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32L5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32L5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32L5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32L5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32L5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32L5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32L5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32L5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32L5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32L5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32L5_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32L5_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32L5_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32L5_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ -#define STM32L5_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ -#define STM32L5_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ -#define STM32L5_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ -#define STM32L5_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ -#define STM32L5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32L5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32L5_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ -#define STM32L5_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PDCRE_OFFSET 0x0044 /* Power Port E pull-down control register */ +#define STM32_PWR_PUCRF_OFFSET 0x0048 /* Power Port F pull-up control register */ +#define STM32_PWR_PDCRF_OFFSET 0x004C /* Power Port F pull-down control register */ +#define STM32_PWR_PUCRG_OFFSET 0x0050 /* Power Port G pull-up control register */ +#define STM32_PWR_PDCRG_OFFSET 0x0054 /* Power Port G pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_SECCFGR_OFFSET 0x0078 /* Power secure configuration register */ +#define STM32_PWR_PRIVCFGR_OFFSET 0x0078 /* Power privilege configuration register */ /* Register Addresses *******************************************************/ -#define STM32L5_PWR_CR1 (STM32L5_PWR_BASE + STM32L5_PWR_CR1_OFFSET) -#define STM32L5_PWR_CR2 (STM32L5_PWR_BASE + STM32L5_PWR_CR2_OFFSET) -#define STM32L5_PWR_CR3 (STM32L5_PWR_BASE + STM32L5_PWR_CR3_OFFSET) -#define STM32L5_PWR_CR4 (STM32L5_PWR_BASE + STM32L5_PWR_CR4_OFFSET) -#define STM32L5_PWR_SR1 (STM32L5_PWR_BASE + STM32L5_PWR_SR1_OFFSET) -#define STM32L5_PWR_SR2 (STM32L5_PWR_BASE + STM32L5_PWR_SR2_OFFSET) -#define STM32L5_PWR_SCR (STM32L5_PWR_BASE + STM32L5_PWR_SCR_OFFSET) -#define STM32L5_PWR_PUCRA (STM32L5_PWR_BASE + STM32L5_PWR_PUCRA_OFFSET) -#define STM32L5_PWR_PDCRA (STM32L5_PWR_BASE + STM32L5_PWR_PDCRA_OFFSET) -#define STM32L5_PWR_PUCRB (STM32L5_PWR_BASE + STM32L5_PWR_PUCRB_OFFSET) -#define STM32L5_PWR_PDCRB (STM32L5_PWR_BASE + STM32L5_PWR_PDCRB_OFFSET) -#define STM32L5_PWR_PUCRC (STM32L5_PWR_BASE + STM32L5_PWR_PUCRC_OFFSET) -#define STM32L5_PWR_PDCRC (STM32L5_PWR_BASE + STM32L5_PWR_PDCRC_OFFSET) -#define STM32L5_PWR_PUCRD (STM32L5_PWR_BASE + STM32L5_PWR_PUCRD_OFFSET) -#define STM32L5_PWR_PDCRD (STM32L5_PWR_BASE + STM32L5_PWR_PDCRD_OFFSET) -#define STM32L5_PWR_PUCRE (STM32L5_PWR_BASE + STM32L5_PWR_PUCRE_OFFSET) -#define STM32L5_PWR_PDCRE (STM32L5_PWR_BASE + STM32L5_PWR_PDCRE_OFFSET) -#define STM32L5_PWR_PUCRF (STM32L5_PWR_BASE + STM32L5_PWR_PUCRF_OFFSET) -#define STM32L5_PWR_PDCRF (STM32L5_PWR_BASE + STM32L5_PWR_PDCRF_OFFSET) -#define STM32L5_PWR_PUCRG (STM32L5_PWR_BASE + STM32L5_PWR_PUCRG_OFFSET) -#define STM32L5_PWR_PDCRG (STM32L5_PWR_BASE + STM32L5_PWR_PDCRG_OFFSET) -#define STM32L5_PWR_PUCRH (STM32L5_PWR_BASE + STM32L5_PWR_PUCRH_OFFSET) -#define STM32L5_PWR_PDCRH (STM32L5_PWR_BASE + STM32L5_PWR_PDCRH_OFFSET) -#define STM32L5_PWR_SECCFGR (STM32L5_PWR_BASE + STM32L5_PWR_SECCFGR_OFFSET) -#define STM32L5_PWR_PRIVCFGR (STM32L5_PWR_BASE + STM32L5_PWR_PRIVCFGR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRF (STM32_PWR_BASE + STM32_PWR_PUCRF_OFFSET) +#define STM32_PWR_PDCRF (STM32_PWR_BASE + STM32_PWR_PDCRF_OFFSET) +#define STM32_PWR_PUCRG (STM32_PWR_BASE + STM32_PWR_PUCRG_OFFSET) +#define STM32_PWR_PDCRG (STM32_PWR_BASE + STM32_PWR_PDCRG_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE + STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_PRIVCFGR (STM32_PWR_BASE + STM32_PWR_PRIVCFGR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index 91b92dc5a6a..e449f201f10 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -37,51 +37,51 @@ /* Maximum allowed speed as per specifications for all SPIs */ #if defined(CONFIG_STM32L5_STM32L562XX) -# define STM32L5_SPI_CLK_MAX 55000000UL +# define STM32_SPI_CLK_MAX 55000000UL #else # error "Unsupported STM32 L5 chip" #endif /* Register Offsets *********************************************************/ -#define STM32L5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32L5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32L5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32L5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32L5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32L5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32L5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#if STM32L5_NSPI > 0 -# define STM32L5_SPI1_CR1 (STM32L5_SPI1_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI1_CR2 (STM32L5_SPI1_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI1_SR (STM32L5_SPI1_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI1_DR (STM32L5_SPI1_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI1_CRCPR (STM32L5_SPI1_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI1_RXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI1_TXCRCR (STM32L5_SPI1_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 1 -# define STM32L5_SPI2_CR1 (STM32L5_SPI2_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI2_CR2 (STM32L5_SPI2_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI2_SR (STM32L5_SPI2_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI2_DR (STM32L5_SPI2_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI2_CRCPR (STM32L5_SPI2_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI2_RXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI2_TXCRCR (STM32L5_SPI2_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32L5_NSPI > 2 -# define STM32L5_SPI3_CR1 (STM32L5_SPI3_BASE + STM32L5_SPI_CR1_OFFSET) -# define STM32L5_SPI3_CR2 (STM32L5_SPI3_BASE + STM32L5_SPI_CR2_OFFSET) -# define STM32L5_SPI3_SR (STM32L5_SPI3_BASE + STM32L5_SPI_SR_OFFSET) -# define STM32L5_SPI3_DR (STM32L5_SPI3_BASE + STM32L5_SPI_DR_OFFSET) -# define STM32L5_SPI3_CRCPR (STM32L5_SPI3_BASE + STM32L5_SPI_CRCPR_OFFSET) -# define STM32L5_SPI3_RXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_RXCRCR_OFFSET) -# define STM32L5_SPI3_TXCRCR (STM32L5_SPI3_BASE + STM32L5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 2 +# define STM32_SPI3_CR1 (STM32_SPI3_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI3_CR2 (STM32_SPI3_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI3_SR (STM32_SPI3_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI3_DR (STM32_SPI3_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI3_CRCPR (STM32_SPI3_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h index 1e99dba009a..bb27ee0f1c1 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32L5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32L5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32L5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32L5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32L5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32L5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32L5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32L5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32L5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32L5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32L5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32L5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32L5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32L5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32L5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32L5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32L5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32L5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32L5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32L5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32L5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32L5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32L5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32L5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32L5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32L5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32L5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32L5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32L5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32L5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32L5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32L5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32L5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32L5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32L5_TIM1_CR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM1_CR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM1_SMCR (STM32L5_TIM1_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM1_DIER (STM32L5_TIM1_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM1_SR (STM32L5_TIM1_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM1_EGR (STM32L5_TIM1_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM1_CCMR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM1_CCMR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM1_CCER (STM32L5_TIM1_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM1_CNT (STM32L5_TIM1_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM1_PSC (STM32L5_TIM1_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM1_ARR (STM32L5_TIM1_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM1_RCR (STM32L5_TIM1_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM1_CCR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM1_CCR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM1_CCR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM1_CCR4 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM1_BDTR (STM32L5_TIM1_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM1_DCR (STM32L5_TIM1_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM1_DMAR (STM32L5_TIM1_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM1_OR1 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM1_CCMR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM1_CCR5 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM1_CCR6 (STM32L5_TIM1_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM1_OR2 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM1_OR3 (STM32L5_TIM1_BASE + STM32L5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) -#define STM32L5_TIM8_CR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR1_OFFSET) -#define STM32L5_TIM8_CR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CR2_OFFSET) -#define STM32L5_TIM8_SMCR (STM32L5_TIM8_BASE + STM32L5_ATIM_SMCR_OFFSET) -#define STM32L5_TIM8_DIER (STM32L5_TIM8_BASE + STM32L5_ATIM_DIER_OFFSET) -#define STM32L5_TIM8_SR (STM32L5_TIM8_BASE + STM32L5_ATIM_SR_OFFSET) -#define STM32L5_TIM8_EGR (STM32L5_TIM8_BASE + STM32L5_ATIM_EGR_OFFSET) -#define STM32L5_TIM8_CCMR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR1_OFFSET) -#define STM32L5_TIM8_CCMR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR2_OFFSET) -#define STM32L5_TIM8_CCER (STM32L5_TIM8_BASE + STM32L5_ATIM_CCER_OFFSET) -#define STM32L5_TIM8_CNT (STM32L5_TIM8_BASE + STM32L5_ATIM_CNT_OFFSET) -#define STM32L5_TIM8_PSC (STM32L5_TIM8_BASE + STM32L5_ATIM_PSC_OFFSET) -#define STM32L5_TIM8_ARR (STM32L5_TIM8_BASE + STM32L5_ATIM_ARR_OFFSET) -#define STM32L5_TIM8_RCR (STM32L5_TIM8_BASE + STM32L5_ATIM_RCR_OFFSET) -#define STM32L5_TIM8_CCR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR1_OFFSET) -#define STM32L5_TIM8_CCR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR2_OFFSET) -#define STM32L5_TIM8_CCR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR3_OFFSET) -#define STM32L5_TIM8_CCR4 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR4_OFFSET) -#define STM32L5_TIM8_BDTR (STM32L5_TIM8_BASE + STM32L5_ATIM_BDTR_OFFSET) -#define STM32L5_TIM8_DCR (STM32L5_TIM8_BASE + STM32L5_ATIM_DCR_OFFSET) -#define STM32L5_TIM8_DMAR (STM32L5_TIM8_BASE + STM32L5_ATIM_DMAR_OFFSET) -#define STM32L5_TIM8_OR1 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR1_OFFSET) -#define STM32L5_TIM8_CCMR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCMR3_OFFSET) -#define STM32L5_TIM8_CCR5 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR5_OFFSET) -#define STM32L5_TIM8_CCR6 (STM32L5_TIM8_BASE + STM32L5_ATIM_CCR6_OFFSET) -#define STM32L5_TIM8_OR2 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR2_OFFSET) -#define STM32L5_TIM8_OR3 (STM32L5_TIM8_BASE + STM32L5_ATIM_OR3_OFFSET) +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32L5_TIM2_CR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM2_CR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM2_SMCR (STM32L5_TIM2_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM2_DIER (STM32L5_TIM2_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM2_SR (STM32L5_TIM2_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM2_EGR (STM32L5_TIM2_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM2_CCMR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM2_CCMR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM2_CCER (STM32L5_TIM2_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM2_CNT (STM32L5_TIM2_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM2_PSC (STM32L5_TIM2_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM2_ARR (STM32L5_TIM2_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM2_CCR1 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM2_CCR2 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM2_CCR3 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM2_CCR4 (STM32L5_TIM2_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM2_DCR (STM32L5_TIM2_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM2_DMAR (STM32L5_TIM2_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM2_OR (STM32L5_TIM2_BASE + STM32L5_GTIM_OR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) -#define STM32L5_TIM3_CR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM3_CR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM3_SMCR (STM32L5_TIM3_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM3_DIER (STM32L5_TIM3_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM3_SR (STM32L5_TIM3_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM3_EGR (STM32L5_TIM3_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM3_CCMR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM3_CCMR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM3_CCER (STM32L5_TIM3_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM3_CNT (STM32L5_TIM3_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM3_PSC (STM32L5_TIM3_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM3_ARR (STM32L5_TIM3_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM3_CCR1 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM3_CCR2 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM3_CCR3 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM3_CCR4 (STM32L5_TIM3_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM3_DCR (STM32L5_TIM3_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM3_DMAR (STM32L5_TIM3_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32L5_TIM4_CR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM4_CR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM4_SMCR (STM32L5_TIM4_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM4_DIER (STM32L5_TIM4_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM4_SR (STM32L5_TIM4_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM4_EGR (STM32L5_TIM4_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM4_CCMR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM4_CCMR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM4_CCER (STM32L5_TIM4_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM4_CNT (STM32L5_TIM4_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM4_PSC (STM32L5_TIM4_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM4_ARR (STM32L5_TIM4_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM4_CCR1 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM4_CCR2 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM4_CCR3 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM4_CCR4 (STM32L5_TIM4_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM4_DCR (STM32L5_TIM4_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM4_DMAR (STM32L5_TIM4_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32L5_TIM5_CR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM5_CR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM5_SMCR (STM32L5_TIM5_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM5_DIER (STM32L5_TIM5_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM5_SR (STM32L5_TIM5_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM5_EGR (STM32L5_TIM5_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM5_CCMR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM5_CCMR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCMR2_OFFSET) -#define STM32L5_TIM5_CCER (STM32L5_TIM5_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM5_CNT (STM32L5_TIM5_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM5_PSC (STM32L5_TIM5_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM5_ARR (STM32L5_TIM5_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM5_CCR1 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM5_CCR2 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM5_CCR3 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR3_OFFSET) -#define STM32L5_TIM5_CCR4 (STM32L5_TIM5_BASE + STM32L5_GTIM_CCR4_OFFSET) -#define STM32L5_TIM5_DCR (STM32L5_TIM5_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM5_DMAR (STM32L5_TIM5_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM5_OR (STM32L5_TIM5_BASE + STM32L5_GTIM_OR_OFFSET) +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) -#define STM32L5_TIM15_CR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM15_CR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM15_SMCR (STM32L5_TIM15_BASE + STM32L5_GTIM_SMCR_OFFSET) -#define STM32L5_TIM15_DIER (STM32L5_TIM15_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM15_SR (STM32L5_TIM15_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM15_EGR (STM32L5_TIM15_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM15_CCMR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM15_CCER (STM32L5_TIM15_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM15_CNT (STM32L5_TIM15_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM15_PSC (STM32L5_TIM15_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM15_ARR (STM32L5_TIM15_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM15_RCR (STM32L5_TIM15_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM15_CCR1 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM15_CCR2 (STM32L5_TIM15_BASE + STM32L5_GTIM_CCR2_OFFSET) -#define STM32L5_TIM15_BDTR (STM32L5_TIM15_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM15_DCR (STM32L5_TIM15_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM15_DMAR (STM32L5_TIM15_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32L5_TIM16_CR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM16_CR2 (STM32L5_TIM16_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM16_DIER (STM32L5_TIM16_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM16_SR (STM32L5_TIM16_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM16_EGR (STM32L5_TIM16_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM16_CCMR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM16_CCER (STM32L5_TIM16_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM16_CNT (STM32L5_TIM16_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM16_PSC (STM32L5_TIM16_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM16_ARR (STM32L5_TIM16_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM16_RCR (STM32L5_TIM16_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM16_CCR1 (STM32L5_TIM16_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM16_BDTR (STM32L5_TIM16_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM16_DCR (STM32L5_TIM16_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM16_DMAR (STM32L5_TIM16_BASE + STM32L5_GTIM_DMAR_OFFSET) -#define STM32L5_TIM16_OR (STM32L5_TIM16_BASE + STM32L5_GTIM_OR_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) -#define STM32L5_TIM17_CR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR1_OFFSET) -#define STM32L5_TIM17_CR2 (STM32L5_TIM17_BASE + STM32L5_GTIM_CR2_OFFSET) -#define STM32L5_TIM17_DIER (STM32L5_TIM17_BASE + STM32L5_GTIM_DIER_OFFSET) -#define STM32L5_TIM17_SR (STM32L5_TIM17_BASE + STM32L5_GTIM_SR_OFFSET) -#define STM32L5_TIM17_EGR (STM32L5_TIM17_BASE + STM32L5_GTIM_EGR_OFFSET) -#define STM32L5_TIM17_CCMR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCMR1_OFFSET) -#define STM32L5_TIM17_CCER (STM32L5_TIM17_BASE + STM32L5_GTIM_CCER_OFFSET) -#define STM32L5_TIM17_CNT (STM32L5_TIM17_BASE + STM32L5_GTIM_CNT_OFFSET) -#define STM32L5_TIM17_PSC (STM32L5_TIM17_BASE + STM32L5_GTIM_PSC_OFFSET) -#define STM32L5_TIM17_ARR (STM32L5_TIM17_BASE + STM32L5_GTIM_ARR_OFFSET) -#define STM32L5_TIM17_RCR (STM32L5_TIM17_BASE + STM32L5_GTIM_RCR_OFFSET) -#define STM32L5_TIM17_CCR1 (STM32L5_TIM17_BASE + STM32L5_GTIM_CCR1_OFFSET) -#define STM32L5_TIM17_BDTR (STM32L5_TIM17_BASE + STM32L5_GTIM_BDTR_OFFSET) -#define STM32L5_TIM17_DCR (STM32L5_TIM17_BASE + STM32L5_GTIM_DCR_OFFSET) -#define STM32L5_TIM17_DMAR (STM32L5_TIM17_BASE + STM32L5_GTIM_DMAR_OFFSET) +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32L5_TIM6_CR1 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM6_CR2 (STM32L5_TIM6_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM6_DIER (STM32L5_TIM6_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM6_SR (STM32L5_TIM6_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM6_EGR (STM32L5_TIM6_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM6_CNT (STM32L5_TIM6_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM6_PSC (STM32L5_TIM6_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM6_ARR (STM32L5_TIM6_BASE + STM32L5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) -#define STM32L5_TIM7_CR1 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR1_OFFSET) -#define STM32L5_TIM7_CR2 (STM32L5_TIM7_BASE + STM32L5_BTIM_CR2_OFFSET) -#define STM32L5_TIM7_DIER (STM32L5_TIM7_BASE + STM32L5_BTIM_DIER_OFFSET) -#define STM32L5_TIM7_SR (STM32L5_TIM7_BASE + STM32L5_BTIM_SR_OFFSET) -#define STM32L5_TIM7_EGR (STM32L5_TIM7_BASE + STM32L5_BTIM_EGR_OFFSET) -#define STM32L5_TIM7_CNT (STM32L5_TIM7_BASE + STM32L5_BTIM_CNT_OFFSET) -#define STM32L5_TIM7_PSC (STM32L5_TIM7_BASE + STM32L5_BTIM_PSC_OFFSET) -#define STM32L5_TIM7_ARR (STM32L5_TIM7_BASE + STM32L5_BTIM_ARR_OFFSET) +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h index b987bc43921..65880b3175f 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_uart.h @@ -37,94 +37,94 @@ /* Register Offsets *********************************************************/ -#define STM32L5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32L5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32L5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32L5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32L5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32L5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32L5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32L5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32L5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32L5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32L5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32L5_USART_PRESC_OFFSET 0x002c /* Prescaler register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler register */ /* Register Addresses *******************************************************/ -#if STM32L5_NUSART > 0 -# define STM32L5_USART1_CR1 (STM32L5_USART1_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART1_CR2 (STM32L5_USART1_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART1_CR3 (STM32L5_USART1_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART1_BRR (STM32L5_USART1_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART1_GTPR (STM32L5_USART1_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART1_RTOR (STM32L5_USART1_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART1_RQR (STM32L5_USART1_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART1_ISR (STM32L5_USART1_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART1_ICR (STM32L5_USART1_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART1_RDR (STM32L5_USART1_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART1_TDR (STM32L5_USART1_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART1_PRESC (STM32L5_USART1_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 1 -# define STM32L5_USART2_CR1 (STM32L5_USART2_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART2_CR2 (STM32L5_USART2_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART2_CR3 (STM32L5_USART2_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART2_BRR (STM32L5_USART2_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART2_GTPR (STM32L5_USART2_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART2_RTOR (STM32L5_USART2_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART2_RQR (STM32L5_USART2_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART2_ISR (STM32L5_USART2_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART2_ICR (STM32L5_USART2_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART2_RDR (STM32L5_USART2_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART2_TDR (STM32L5_USART2_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART2_PRESC (STM32L5_USART2_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 1 +# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 2 -# define STM32L5_USART3_CR1 (STM32L5_USART3_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_USART3_CR2 (STM32L5_USART3_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_USART3_CR3 (STM32L5_USART3_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_USART3_BRR (STM32L5_USART3_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_USART3_GTPR (STM32L5_USART3_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_USART3_RTOR (STM32L5_USART3_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_USART3_RQR (STM32L5_USART3_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_USART3_ISR (STM32L5_USART3_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_USART3_ICR (STM32L5_USART3_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_USART3_RDR (STM32L5_USART3_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_USART3_TDR (STM32L5_USART3_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_USART3_PRESC (STM32L5_USART3_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 2 +# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 3 -# define STM32L5_UART4_CR1 (STM32L5_UART4_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART4_CR2 (STM32L5_UART4_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART4_CR3 (STM32L5_UART4_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART4_BRR (STM32L5_UART4_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART4_GTPR (STM32L5_UART4_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART4_RTOR (STM32L5_UART4_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART4_RQR (STM32L5_UART4_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART4_ISR (STM32L5_UART4_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART4_ICR (STM32L5_UART4_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART4_RDR (STM32L5_UART4_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART4_TDR (STM32L5_UART4_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART4_PRESC (STM32L5_UART4_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 3 +# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) #endif -#if STM32L5_NUSART > 4 -# define STM32L5_UART5_CR1 (STM32L5_UART5_BASE + STM32L5_USART_CR1_OFFSET) -# define STM32L5_UART5_CR2 (STM32L5_UART5_BASE + STM32L5_USART_CR2_OFFSET) -# define STM32L5_UART5_CR3 (STM32L5_UART5_BASE + STM32L5_USART_CR3_OFFSET) -# define STM32L5_UART5_BRR (STM32L5_UART5_BASE + STM32L5_USART_BRR_OFFSET) -# define STM32L5_UART5_GTPR (STM32L5_UART5_BASE + STM32L5_USART_GTPR_OFFSET) -# define STM32L5_UART5_RTOR (STM32L5_UART5_BASE + STM32L5_USART_RTOR_OFFSET) -# define STM32L5_UART5_RQR (STM32L5_UART5_BASE + STM32L5_USART_RQR_OFFSET) -# define STM32L5_UART5_ISR (STM32L5_UART5_BASE + STM32L5_USART_ISR_OFFSET) -# define STM32L5_UART5_ICR (STM32L5_UART5_BASE + STM32L5_USART_ICR_OFFSET) -# define STM32L5_UART5_RDR (STM32L5_UART5_BASE + STM32L5_USART_RDR_OFFSET) -# define STM32L5_UART5_TDR (STM32L5_UART5_BASE + STM32L5_USART_TDR_OFFSET) -# define STM32L5_UART5_PRESC (STM32L5_UART5_BASE + STM32L5_USART_PRESC_OFFSET) +#if STM32_NUSART > 4 +# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) +# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) +# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) +# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) +# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) +# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) +# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index b1f582519e6..39636e57719 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -56,13 +56,13 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* HSE divisor to yield ~1MHz RTC clock */ -#define HSE_DIVISOR (STM32L5_HSE_FREQUENCY + 500000) / 1000000 +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32L5_USE_CLK48) -# if STM32L5_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_USE_HSI48 +#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -90,7 +90,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32L5_DMA1 /* DMA 1 clock enable */ @@ -134,7 +134,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_GTZEN; #endif - putreg32(regval, STM32L5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -153,31 +153,31 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32L5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32L5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32L5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32L5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIODEN #endif -#if STM32L5_NPORTS > 4 +#if STM32_NPORTS > 4 | RCC_AHB2ENR_GPIOEEN #endif -#if STM32L5_NPORTS > 5 +#if STM32_NPORTS > 5 | RCC_AHB2ENR_GPIOFEN #endif -#if STM32L5_NPORTS > 6 +#if STM32_NPORTS > 6 | RCC_AHB2ENR_GPIOGEN #endif -#if STM32L5_NPORTS > 7 +#if STM32_NPORTS > 7 | RCC_AHB2ENR_GPIOHEN #endif ); @@ -225,7 +225,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_SDMMC1EN; #endif - putreg32(regval, STM32L5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -244,7 +244,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32L5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32L5_FMC /* Flexible memory controller clock enable */ @@ -258,7 +258,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_OSPI1EN; #endif - putreg32(regval, STM32L5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -277,7 +277,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32L5_TIM2 /* TIM2 clock enable */ @@ -381,8 +381,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32L5_USE_HSI48 - if (STM32L5_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -414,11 +414,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32L5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32L5_LPUART1 /* Low power uart clock enable */ @@ -462,7 +462,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_UCPD1EN; #endif - putreg32(regval, STM32L5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -481,7 +481,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32L5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP) /* System configuration controller, comparators, and voltage reference @@ -551,7 +551,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_DFSDMEN; #endif - putreg32(regval, STM32L5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -604,12 +604,12 @@ void stm32l5_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32L5_BOARD_USEHSI) || defined(STM32L5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -617,7 +617,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -626,17 +626,17 @@ void stm32l5_stdclockconfig(void) } #endif -#if defined(STM32L5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - if ((regval = getreg32(STM32L5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out with timeout > 0 */ @@ -647,9 +647,9 @@ void stm32l5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32L5_RCC_CR); - regval |= (STM32L5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -657,7 +657,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -665,12 +665,12 @@ void stm32l5_stdclockconfig(void) } } -#elif defined(STM32L5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -678,7 +678,7 @@ void stm32l5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32L5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32L5_BOARD_USEHSI, STM32L5_BOARD_USEMSI, STM32L5_BOARD_USEHSE defined +# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -708,14 +708,14 @@ void stm32l5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32L5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32L5_SYSCLK_FREQUENCY > 80000000) + if (STM32_SYSCLK_FREQUENCY > 80000000) { regval |= PWR_CR1_VOS_RANGE0; } - else if (STM32L5_SYSCLK_FREQUENCY > 26000000) + else if (STM32_SYSCLK_FREQUENCY > 26000000) { regval |= PWR_CR1_VOS_RANGE1; } @@ -724,125 +724,125 @@ void stm32l5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE0; } - putreg32(regval, STM32L5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32L5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32L5_RCC_CFGR_HPRE; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32L5_RCC_CFGR_PPRE2; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32L5_RCC_CFGR_PPRE1; - putreg32(regval, STM32L5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); #ifdef CONFIG_STM32L5_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32L5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32L5_PLLCFG_PLLM | STM32L5_PLLCFG_PLLN | - STM32L5_PLLCFG_PLLP | STM32L5_PLLCFG_PLLQ | - STM32L5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32L5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32L5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32L5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32L5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32L5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32L5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32L5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32L5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32L5_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ - regval = (STM32L5_PLLSAI1CFG_PLLN | STM32L5_PLLSAI1CFG_PLLP - | STM32L5_PLLSAI1CFG_PLLQ | STM32L5_PLLSAI1CFG_PLLR); + regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP + | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR); -#ifdef STM32L5_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval |= RCC_PLLSAI1CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval |= RCC_PLLSAI1CFG_PLLQEN; #endif -#ifdef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval |= RCC_PLLSAI1CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif @@ -850,31 +850,31 @@ void stm32l5_stdclockconfig(void) #ifdef CONFIG_STM32L5_SAI2PLL /* Configure SAI2 PLL */ - regval = getreg32(STM32L5_RCC_PLLSAI2CFG); + regval = getreg32(STM32_RCC_PLLSAI2CFG); /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ - regval = (STM32L5_PLLSAI2CFG_PLLN | STM32L5_PLLSAI2CFG_PLLP | - STM32L5_PLLSAI2CFG_PLLR); + regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP | + STM32_PLLSAI2CFG_PLLR); -#ifdef STM32L5_PLLSAI2CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED regval |= RCC_PLLSAI2CFG_PLLPEN; #endif -#ifdef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED regval |= RCC_PLLSAI2CFG_PLLREN; #endif - putreg32(regval, STM32L5_RCC_PLLSAI2CFG); + putreg32(regval, STM32_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI2ON; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32L5_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0) { } #endif @@ -882,18 +882,18 @@ void stm32l5_stdclockconfig(void) /* Enable FLASH 5 wait states */ regval = FLASH_ACR_LATENCY_5; - putreg32(regval, STM32L5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -904,7 +904,7 @@ void stm32l5_stdclockconfig(void) stm32l5_rcc_enablelsi(); #endif -#if defined(STM32L5_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -929,14 +929,14 @@ void stm32l5_stdclockconfig(void) stm32l5_rcc_enablelse(); -# if defined(STM32L5_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32L5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32L5_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32L5_USE_LSE */ +#endif /* STM32_USE_LSE */ } } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 8809fc4a200..5547109564e 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -96,19 +96,19 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32L5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32L5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Set the range of SRAM3, requiring a third memory region */ -#ifdef STM32L5_SRAM3_SIZE -# define SRAM3_START STM32L5_SRAM3_BASE -# define SRAM3_END (SRAM3_START + STM32L5_SRAM3_SIZE) +#ifdef STM32_SRAM3_SIZE +# define SRAM3_START STM32_SRAM3_BASE +# define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index 0c79a6cc60d..f5dc0ed6ce7 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -50,31 +50,31 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32L5_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { -#if STM32L5_NPORTS > 11 +#if STM32_NPORTS > 11 # error "Additional support required for this number of GPIOs" -#elif STM32L5_NPORTS > 10 +#elif STM32_NPORTS > 10 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K' -#elif STM32L5_NPORTS > 9 +#elif STM32_NPORTS > 9 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J' -#elif STM32L5_NPORTS > 8 +#elif STM32_NPORTS > 8 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I' -#elif STM32L5_NPORTS > 7 +#elif STM32_NPORTS > 7 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' -#elif STM32L5_NPORTS > 6 +#elif STM32_NPORTS > 6 'A', 'B', 'C', 'D', 'E', 'F', 'G' -#elif STM32L5_NPORTS > 5 +#elif STM32_NPORTS > 5 'A', 'B', 'C', 'D', 'E', 'F' -#elif STM32L5_NPORTS > 4 +#elif STM32_NPORTS > 4 'A', 'B', 'C', 'D', 'E' -#elif STM32L5_NPORTS > 3 +#elif STM32_NPORTS > 3 'A', 'B', 'C', 'D' -#elif STM32L5_NPORTS > 2 +#elif STM32_NPORTS > 2 'A', 'B', 'C' -#elif STM32L5_NPORTS > 1 +#elif STM32_NPORTS > 1 'A', 'B' -#elif STM32L5_NPORTS > 0 +#elif STM32_NPORTS > 0 'A' #else # error "Bad number of GPIOs" @@ -108,33 +108,33 @@ int stm32l5_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32L5_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32L5_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08" PRIx32 " OTYPE: %04" PRIx32 " OSPEED: %08" PRIx32 " PUPDR: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_MODER_OFFSET), - getreg32(base + STM32L5_GPIO_OTYPER_OFFSET), - getreg32(base + STM32L5_GPIO_OSPEED_OFFSET), - getreg32(base + STM32L5_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04" PRIx32 " ODR: %04" PRIx32 " BSRR: %08" PRIx32 " LCKR: %04" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_IDR_OFFSET), - getreg32(base + STM32L5_GPIO_ODR_OFFSET), - getreg32(base + STM32L5_GPIO_BSRR_OFFSET), - getreg32(base + STM32L5_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08" PRIx32 " AFRL: %08" PRIx32 "\n", - getreg32(base + STM32L5_GPIO_AFRH_OFFSET), - getreg32(base + STM32L5_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08" PRIx32 "\n", - g_portchar[port], getreg32(STM32L5_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index cc632e2df5a..67a6a051e23 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -72,13 +72,13 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) int ret = OK; int exti; - exti = irq - STM32L5_IRQ_EXTI0; + exti = irq - STM32_IRQ_EXTI0; DEBUGASSERT((exti >= 0) && (exti <= 15)); /* Clear the pending interrupt for both rising and falling edges. */ - putreg32(0x0001 << exti, STM32L5_EXTI_RPR1); - putreg32(0x0001 << exti, STM32L5_EXTI_FPR1); + putreg32(0x0001 << exti, STM32_EXTI_RPR1); + putreg32(0x0001 << exti, STM32_EXTI_FPR1); /* And dispatch the interrupt to the handler */ @@ -125,7 +125,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, { uint32_t pin = pinset & GPIO_PIN_MASK; uint32_t exti = 1 << pin; - int irq = STM32L5_IRQ_EXTI0 + pin; + int irq = STM32_IRQ_EXTI0 + pin; g_gpio_handlers[pin].callback = func; g_gpio_handlers[pin].arg = arg; @@ -155,19 +155,19 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32L5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32L5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32L5_EXTI_EMR1, + modifyreg32(STM32_EXTI_EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32L5_EXTI_IMR1, + modifyreg32(STM32_EXTI_IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 62f7f863705..d7d9915e709 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -69,7 +69,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32L5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #if FLASH_PAGE_SIZE == 2048 @@ -79,7 +79,7 @@ #elif FLASH_PAGE_SIZE == 8192 # define FLASH_PAGE_SHIFT (13) /* 2**13 = 8192B */ #else -# error Unsupported STM32L5_FLASH_PAGESIZE +# error Unsupported STM32_FLASH_PAGESIZE #endif #define FLASH_BYTE2PAGE(o) ((o) >> FLASH_PAGE_SHIFT) @@ -105,35 +105,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32L5_FLASH_NSKEYR); - putreg32(FLASH_KEY2, STM32L5_FLASH_NSKEYR); + putreg32(FLASH_KEY1, STM32_FLASH_NSKEYR); + putreg32(FLASH_KEY2, STM32_FLASH_NSKEYR); } } static void flash_lock(void) { - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32L5_FLASH_NSCR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32L5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32L5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -150,16 +150,16 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page)); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_START); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -214,20 +214,20 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32L5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%x\n", (unsigned)regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32L5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%x\n", (unsigned)regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } @@ -240,42 +240,42 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32L5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32L5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32L5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32L5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32L5_FLASH_PAGESIZE + STM32L5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32L5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -285,7 +285,7 @@ bool up_progmem_isuniform(void) ssize_t up_progmem_eraseblock(size_t block) { - if (block >= STM32L5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -318,7 +318,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32L5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -351,12 +351,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32L5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32L5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32L5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -422,23 +422,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32L5_FLASH_NSCR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_NSCR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { stm32l5_waste(); } /* Verify */ - if (getreg32(STM32L5_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_NSSR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -446,13 +446,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32L5_FLASH_NSCR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -473,8 +473,8 @@ out: if (ret != OK) { ferr("flash write error: %d, status: 0x%x\n", ret, - (unsigned)getreg32(STM32L5_FLASH_NSSR)); - modifyreg32(STM32L5_FLASH_NSSR, 0, FLASH_SR_ALLERRS); + (unsigned)getreg32(STM32_FLASH_NSSR)); + modifyreg32(STM32_FLASH_NSSR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 581a5b6bfc0..2d9afa34849 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -54,31 +54,31 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32L5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32L5_NPORTS > 0 - STM32L5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32L5_NPORTS > 1 - STM32L5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32L5_NPORTS > 2 - STM32L5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32L5_NPORTS > 3 - STM32L5_GPIOD_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOD_BASE, #endif -#if STM32L5_NPORTS > 4 - STM32L5_GPIOE_BASE, +#if STM32_NPORTS > 4 + STM32_GPIOE_BASE, #endif -#if STM32L5_NPORTS > 5 - STM32L5_GPIOF_BASE, +#if STM32_NPORTS > 5 + STM32_GPIOF_BASE, #endif -#if STM32L5_NPORTS > 6 - STM32L5_GPIOG_BASE, +#if STM32_NPORTS > 6 + STM32_GPIOG_BASE, #endif -#if STM32L5_NPORTS > 7 - STM32L5_GPIOH_BASE, +#if STM32_NPORTS > 7 + STM32_GPIOH_BASE, #endif }; @@ -141,7 +141,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32L5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -190,10 +190,10 @@ int stm32l5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32L5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -216,10 +216,10 @@ int stm32l5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32L5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -234,12 +234,12 @@ int stm32l5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32L5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32L5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -277,14 +277,14 @@ int stm32l5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32L5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32L5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32L5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -297,7 +297,7 @@ int stm32l5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32L5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); spin_unlock_irqrestore(&g_configgpio_lock, flags); return OK; @@ -352,7 +352,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -373,7 +373,7 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32L5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -392,7 +392,7 @@ bool stm32l5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32L5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -401,7 +401,7 @@ bool stm32l5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32L5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index e14436202a5..2bb1f035651 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -241,7 +241,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32L5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index 757b7315fff..f42f2dda2ab 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -186,13 +186,13 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32L5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32L5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -202,19 +202,19 @@ static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32L5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32L5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32L5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32L5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -244,7 +244,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32L5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -298,14 +298,14 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32L5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32L5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32L5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif @@ -316,23 +316,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32L5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32L5_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32L5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32L5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32L5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32L5_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32L5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32L5_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); #endif stm32l5_dumpnvic("initial", NR_IRQS); @@ -368,7 +368,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -403,7 +403,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32L5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -446,10 +446,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32L5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32L5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -462,7 +462,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32L5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index bcc1075c80a..6229979f9a2 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -46,127 +46,127 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_LPUART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR2 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32L5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART1_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK2_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB2ENR -# define STM32L5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART1_TX -# define STM32L5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART2_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART2_TX -# define STM32L5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART3_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_USART3_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_USART3EN -# define STM32L5_CONSOLE_BAUD CONFIG_USART3_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_USART3_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_USART3_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_USART3_2STOP -# define STM32L5_CONSOLE_TX GPIO_USART3_TX -# define STM32L5_CONSOLE_RX GPIO_USART3_RX +# define STM32_CONSOLE_BASE STM32_USART3_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART3EN +# define STM32_CONSOLE_BAUD CONFIG_USART3_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART3_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART3_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART3_2STOP +# define STM32_CONSOLE_TX GPIO_USART3_TX +# define STM32_CONSOLE_RX GPIO_USART3_RX # ifdef CONFIG_USART3_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR # if (CONFIG_USART3_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART4_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART4_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART4EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART4_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART4_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART4_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART4_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART4_TX -# define STM32L5_CONSOLE_RX GPIO_UART4_RX +# define STM32_CONSOLE_BASE STM32_UART4_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART4EN +# define STM32_CONSOLE_BAUD CONFIG_UART4_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART4_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART4_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART4_2STOP +# define STM32_CONSOLE_TX GPIO_UART4_TX +# define STM32_CONSOLE_RX GPIO_UART4_RX # ifdef CONFIG_UART4_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR # if (CONFIG_UART4_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_UART5_SERIAL_CONSOLE) -# define STM32L5_CONSOLE_BASE STM32L5_UART5_BASE -# define STM32L5_APBCLOCK STM32L5_PCLK1_FREQUENCY -# define STM32L5_CONSOLE_APBREG STM32L5_RCC_APB1ENR1 -# define STM32L5_CONSOLE_APBEN RCC_APB1ENR1_UART5EN -# define STM32L5_CONSOLE_BAUD CONFIG_UART5_BAUD -# define STM32L5_CONSOLE_BITS CONFIG_UART5_BITS -# define STM32L5_CONSOLE_PARITY CONFIG_UART5_PARITY -# define STM32L5_CONSOLE_2STOP CONFIG_UART5_2STOP -# define STM32L5_CONSOLE_TX GPIO_UART5_TX -# define STM32L5_CONSOLE_RX GPIO_UART5_RX +# define STM32_CONSOLE_BASE STM32_UART5_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_UART5EN +# define STM32_CONSOLE_BAUD CONFIG_UART5_BAUD +# define STM32_CONSOLE_BITS CONFIG_UART5_BITS +# define STM32_CONSOLE_PARITY CONFIG_UART5_PARITY +# define STM32_CONSOLE_2STOP CONFIG_UART5_2STOP +# define STM32_CONSOLE_TX GPIO_UART5_TX +# define STM32_CONSOLE_RX GPIO_UART5_RX # ifdef CONFIG_UART5_RS485 -# define STM32L5_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR # if (CONFIG_UART5_RS485_DIR_POLARITY == 0) -# define STM32L5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32L5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32L5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32L5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -174,9 +174,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32L5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32L5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -192,7 +192,7 @@ /* CR2 settings */ -# if STM32L5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -232,8 +232,8 @@ * LPUARTDIV must be in range [0x300, 0xFFFFF]. */ -# define STM32L5_BRR_VALUE \ - ((((uint64_t)STM32L5_APBCLOCK << 8) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_BRR_VALUE \ + ((((uint64_t)STM32_APBCLOCK << 8) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) # else @@ -249,19 +249,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32L5_USARTDIV8 \ - (((STM32L5_APBCLOCK << 1) + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) -# define STM32L5_USARTDIV16 \ - ((STM32L5_APBCLOCK + (STM32L5_CONSOLE_BAUD >> 1)) / STM32L5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32L5_USARTDIV8 > 2000 -# define STM32L5_BRR_VALUE STM32L5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32L5_BRR_VALUE \ - ((STM32L5_USARTDIV8 & 0xfff0) | ((STM32L5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -305,22 +305,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32L5_CONSOLE_BASE + STM32L5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32L5_CONSOLE_RS485_DIR - while ((getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -346,7 +346,7 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32L5_CONSOLE_APBREG, 0, STM32L5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -355,17 +355,17 @@ void stm32l5_lowsetup(void) * stm32l5_rcc.c */ -#ifdef STM32L5_CONSOLE_TX - stm32l5_configgpio(STM32L5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32l5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32L5_CONSOLE_RX - stm32l5_configgpio(STM32L5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32l5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32L5_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32L5_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32L5_CONSOLE_RS485_DIR, - !STM32L5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -373,42 +373,42 @@ void stm32l5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32L5_BRR_VALUE, - STM32L5_CONSOLE_BASE + STM32L5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32L5_CONSOLE_BASE + STM32L5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index b990134a4f7..f3e6827279b 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -88,7 +88,7 @@ void stm32l5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -116,7 +116,7 @@ void stm32l5_rcc_enablelse(void) regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif @@ -125,11 +125,11 @@ void stm32l5_rcc_enablelse(void) { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -138,7 +138,7 @@ void stm32l5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32L5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -166,11 +166,11 @@ void stm32l5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32L5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32l5_waste(); @@ -183,7 +183,7 @@ void stm32l5_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32L5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index 507e7a1a8b2..a47bd5ea1dd 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -46,11 +46,11 @@ void stm32l5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32L5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32l5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32L5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 925be6f7c90..3b306923e8e 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -41,12 +41,12 @@ static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32L5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32L5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } /**************************************************************************** @@ -75,7 +75,7 @@ bool stm32l5_pwr_enableclk(bool enable) uint32_t regval; bool wasenabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); wasenabled = ((regval & RCC_APB1ENR1_PWREN) != 0); /* Power interface clock enable. */ @@ -85,14 +85,14 @@ bool stm32l5_pwr_enableclk(bool enable) /* Disable power interface clock */ regval &= ~RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } else if (!wasenabled && enable) { /* Enable power interface clock */ regval |= RCC_APB1ENR1_PWREN; - putreg32(regval, STM32L5_RCC_APB1ENR1); + putreg32(regval, STM32_RCC_APB1ENR1); } return wasenabled; @@ -120,7 +120,7 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR1_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32L5_PWR_CR1_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -169,7 +169,7 @@ bool stm32l5_pwr_enableusv(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -179,7 +179,7 @@ bool stm32l5_pwr_enableusv(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,14 +189,14 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) @@ -229,7 +229,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) bool was_set; bool was_clk_enabled; - regval = getreg32(STM32L5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); was_clk_enabled = ((regval & RCC_APB1ENR1_PWREN) != 0); if (!was_clk_enabled) @@ -239,7 +239,7 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32L5_PWR_CR2_OFFSET); + regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,14 +249,14 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32L5_PWR_CR2_OFFSET, regval); + stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index c2f6421d7cc..8164097f5a0 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32l5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32L5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32L5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32L5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32L5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32L5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32L5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32L5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32l5_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index b756d9656d0..5157e85ce53 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -81,10 +81,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32L5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32L5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index 514c57477d5..e39dad2f74e 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -471,13 +471,13 @@ static struct stm32l5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32L5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -531,13 +531,13 @@ static struct stm32l5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32L5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32L5_PCLK2_FREQUENCY, - .usartbase = STM32L5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -593,13 +593,13 @@ static struct stm32l5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32L5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -655,13 +655,13 @@ static struct stm32l5_serial_s g_usart3priv = .priv = &g_usart3priv, }, - .irq = STM32L5_IRQ_USART3, + .irq = STM32_IRQ_USART3, .parity = CONFIG_USART3_PARITY, .bits = CONFIG_USART3_BITS, .stopbits2 = CONFIG_USART3_2STOP, .baud = CONFIG_USART3_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_USART3_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART3_BASE, .tx_gpio = GPIO_USART3_TX, .rx_gpio = GPIO_USART3_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART3_OFLOWCONTROL) @@ -717,7 +717,7 @@ static struct stm32l5_serial_s g_uart4priv = .priv = &g_uart4priv, }, - .irq = STM32L5_IRQ_UART4, + .irq = STM32_IRQ_UART4, .parity = CONFIG_UART4_PARITY, .bits = CONFIG_UART4_BITS, .stopbits2 = CONFIG_UART4_2STOP, @@ -730,8 +730,8 @@ static struct stm32l5_serial_s g_uart4priv = .rts_gpio = GPIO_UART4_RTS, # endif .baud = CONFIG_UART4_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART4_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART4_BASE, .tx_gpio = GPIO_UART4_TX, .rx_gpio = GPIO_UART4_RX, # ifdef CONFIG_UART4_RXDMA @@ -779,7 +779,7 @@ static struct stm32l5_serial_s g_uart5priv = .priv = &g_uart5priv, }, - .irq = STM32L5_IRQ_UART5, + .irq = STM32_IRQ_UART5, .parity = CONFIG_UART5_PARITY, .bits = CONFIG_UART5_BITS, .stopbits2 = CONFIG_UART5_2STOP, @@ -792,8 +792,8 @@ static struct stm32l5_serial_s g_uart5priv = .rts_gpio = GPIO_UART5_RTS, # endif .baud = CONFIG_UART5_BAUD, - .apbclock = STM32L5_PCLK1_FREQUENCY, - .usartbase = STM32L5_UART5_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_UART5_BASE, .tx_gpio = GPIO_UART5_TX, .rx_gpio = GPIO_UART5_RX, # ifdef CONFIG_UART5_RXDMA @@ -816,7 +816,7 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ static struct stm32l5_serial_s * const - g_uart_devs[STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -896,15 +896,15 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * above) */ - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -959,8 +959,8 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - cr3 = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -1022,20 +1022,20 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) uint32_t brr; #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32L5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* LPUART BRR = 256 * fCK / baud */ brr = (((uint64_t)priv->apbclock << 8) + (priv->baud >> 1)) / priv->baud; - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } else #endif { usartdiv8 = ((priv->apbclock << 1) + (priv->baud >> 1)) / priv->baud; - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { brr = (usartdiv8 + 1) >> 1; @@ -1048,13 +1048,13 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); - stm32l5serial_putreg(priv, STM32L5_USART_BRR_OFFSET, brr); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } /* Configure parity mode */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -1092,11 +1092,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -1104,11 +1104,11 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) @@ -1125,7 +1125,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1170,7 +1170,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + while ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1276,7 +1276,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -1316,39 +1316,39 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER - case STM32L5_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32L5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32L5_USART1_SERIALDRIVER - case STM32L5_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32L5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32L5_USART2_SERIALDRIVER - case STM32L5_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_USART3_SERIALDRIVER - case STM32L5_USART3_BASE: + case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_UART4_SERIALDRIVER - case STM32L5_UART4_BASE: + case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif #ifdef CONFIG_STM32L5_UART5_SERIALDRIVER - case STM32L5_UART5_BASE: + case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; - regaddr = STM32L5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1435,7 +1435,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1446,26 +1446,26 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1473,9 +1473,9 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1528,7 +1528,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1539,7 +1539,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1553,9 +1553,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1613,9 +1613,9 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + regval = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, regval); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1780,7 +1780,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1847,7 +1847,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1920,19 +1920,19 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR3_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1977,11 +1977,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32l5serial_putreg(priv, STM32L5_USART_CR3_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1998,17 +1998,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -2028,11 +2028,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2049,17 +2049,17 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32l5serial_getreg(priv, STM32L5_USART_CR2_OFFSET); + uint32_t cr = stm32l5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -2070,11 +2070,11 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32l5serial_putreg(priv, STM32L5_USART_CR2_OFFSET, cr); + stm32l5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -2231,8 +2231,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2244,8 +2244,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32l5serial_getreg(priv, STM32L5_USART_CR1_OFFSET); - stm32l5serial_putreg(priv, STM32L5_USART_CR1_OFFSET, + cr1 = stm32l5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32l5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2281,7 +2281,7 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32l5serial_getreg(priv, STM32L5_USART_RDR_OFFSET); + rdr = stm32l5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2368,7 +2368,7 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2531,7 +2531,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2542,7 +2542,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32l5_dmasetup(priv->rxdma, - priv->usartbase + STM32L5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2711,7 +2711,7 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32l5serial_putreg(priv, STM32L5_USART_TDR_OFFSET, (uint32_t)ch); + stm32l5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2796,7 +2796,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; - return ((stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET) & + return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2838,11 +2838,11 @@ static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32l5serial_getreg(priv, STM32L5_USART_ISR_OFFSET); + priv->sr = stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32l5serial_putreg(priv, STM32L5_USART_ICR_OFFSET, + stm32l5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2978,7 +2978,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { struct stm32l5_serial_s *priv = g_uart_devs[n]; @@ -3048,7 +3048,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { if (g_uart_devs[i]) { @@ -3117,7 +3117,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32L5_NLPUART + STM32L5_NUSART + STM32L5_NUART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 80f3005edea..6fc62e9eaab 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -285,10 +285,10 @@ static struct stm32l5_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32L5_SPI1_BASE, - .spiclock = STM32L5_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32L5_SPI_DMA /* lines must be configured in board.h */ @@ -343,10 +343,10 @@ static struct stm32l5_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32L5_SPI2_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -399,10 +399,10 @@ static struct stm32l5_spidev_s g_spi3dev = { .ops = &g_spi3ops, }, - .spibase = STM32L5_SPI3_BASE, - .spiclock = STM32L5_PCLK1_FREQUENCY, + .spibase = STM32_SPI3_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32L5_SPI_INTERRUPTS - .spiirq = STM32L5_IRQ_SPI3, + .spiirq = STM32_IRQ_SPI3, #endif #ifdef CONFIG_STM32L5_SPI_DMA .rxch = DMACHAN_SPI3_RX, @@ -522,11 +522,11 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -547,11 +547,11 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32L5_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -574,11 +574,11 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32L5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -601,11 +601,11 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32L5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32L5_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32L5_SPI_DR_OFFSET, + stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -983,11 +983,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32L5_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32L5_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32L5_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -1053,9 +1053,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, actual = priv->spiclock >> 8; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1125,9 +1125,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster @@ -1192,9 +1192,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so the subsequence re-configurations will be * faster @@ -1247,9 +1247,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1315,7 +1315,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32L5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1730,11 +1730,11 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) SPI_CR1_BR_MASK | SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1746,7 +1746,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32L5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32L5_SPI_DMA /* Get DMA channels. @@ -1763,13 +1763,13 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) priv->txdma = stm32l5_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32L5_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32L5_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 94e500d149a..6978b6013b4 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -62,8 +62,8 @@ * 0x2003:ffff - End of internal SRAM2 */ -#define SRAM2_START STM32L5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32L5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index a53bf043a34..7e2d91bc1fd 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -305,16 +305,16 @@ static const struct stm32l5_tim_ops_s stm32l5_tim_ops = struct stm32l5_tim_priv_s stm32l5_tim1_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM2 struct stm32l5_tim_priv_s stm32l5_tim2_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32l5_tim_priv_s stm32l5_tim2_priv = struct stm32l5_tim_priv_s stm32l5_tim3_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32l5_tim_priv_s stm32l5_tim3_priv = struct stm32l5_tim_priv_s stm32l5_tim4_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32l5_tim_priv_s stm32l5_tim4_priv = struct stm32l5_tim_priv_s stm32l5_tim5_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32l5_tim_priv_s stm32l5_tim5_priv = struct stm32l5_tim_priv_s stm32l5_tim6_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32l5_tim_priv_s stm32l5_tim6_priv = struct stm32l5_tim_priv_s stm32l5_tim7_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32l5_tim_priv_s stm32l5_tim7_priv = struct stm32l5_tim_priv_s stm32l5_tim8_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32l5_tim_priv_s stm32l5_tim8_priv = struct stm32l5_tim_priv_s stm32l5_tim15_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32l5_tim_priv_s stm32l5_tim15_priv = struct stm32l5_tim_priv_s stm32l5_tim16_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32l5_tim_priv_s stm32l5_tim16_priv = struct stm32l5_tim_priv_s stm32l5_tim17_priv = { .ops = &stm32l5_tim_ops, - .mode = STM32L5_TIM_MODE_UNUSED, - .base = STM32L5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_EGR_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32L5_GTIM_EGR_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32L5_GTIM_CR1_OFFSET); + uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_DISABLED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32l5_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32l5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32L5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32l5_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32L5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32L5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32L5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32L5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32L5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, break; - case STM32L5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32L5_GTIM_CR1_OFFSET, val); + stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32L5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM8_BASE) + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32L5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32L5_GTIM_PSC_OFFSET, prescaler); + stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32l5_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32L5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32L5_GTIM_ARR_OFFSET, period); + stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32L5_GTIM_ARR_OFFSET); + return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32L5_GTIM_CNT_OFFSET); + uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32L5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32L5_GTIM_CCER_OFFSET); + ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32L5_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32L5_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32L5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32L5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32L5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32L5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32L5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32L5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32L5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32L5_GTIM_CCER_OFFSET, ccer_val); + stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR1_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR2_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR3_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32L5_GTIM_CCR4_OFFSET, compare); + stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR1_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR2_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR3_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32L5_GTIM_CCR4_OFFSET); + return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - vectorno = STM32L5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - vectorno = STM32L5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - vectorno = STM32L5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - vectorno = STM32L5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - vectorno = STM32L5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - vectorno = STM32L5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - vectorno = STM32L5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - vectorno = STM32L5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - vectorno = STM32L5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - vectorno = STM32L5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - vectorno = STM32L5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32L5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32L5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32L5_GTIM_SR_OFFSET); + uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) #ifdef CONFIG_STM32L5_TIM1 case 1: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L5_TIM2 case 2: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L5_TIM3 case 3: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L5_TIM4 case 4: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L5_TIM5 case 5: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L5_TIM6 case 6: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L5_TIM7 case 7: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; - modifyreg32(STM32L5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L5_TIM8 case 8: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L5_TIM15 case 15: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L5_TIM16 case 16: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L5_TIM17 case 17: dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; - modifyreg32(STM32L5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32L5_TIM_MODE_UNUSED) + if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) switch (((struct stm32l5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 - case STM32L5_TIM1_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM2 - case STM32L5_TIM2_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM3 - case STM32L5_TIM3_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM4 - case STM32L5_TIM4_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM5 - case STM32L5_TIM5_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM6 - case STM32L5_TIM6_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM7 - case STM32L5_TIM7_BASE: - modifyreg32(STM32L5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM8 - case STM32L5_TIM8_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM15 - case STM32L5_TIM15_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM16 - case STM32L5_TIM16_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32L5_TIM17 - case STM32L5_TIM17_BASE: - modifyreg32(STM32L5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32L5_TIM_MODE_UNUSED; + ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index f114ff9c618..9e420265f79 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32L5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32L5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32L5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32L5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32L5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32L5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32L5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32L5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32L5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32L5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32L5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32L5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32L5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32L5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32l5_tim_dev_s enum stm32l5_tim_mode_e { - STM32L5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32L5_TIM_MODE_MASK = 0x0310, - STM32L5_TIM_MODE_DISABLED = 0x0000, - STM32L5_TIM_MODE_UP = 0x0100, - STM32L5_TIM_MODE_DOWN = 0x0110, - STM32L5_TIM_MODE_UPDOWN = 0x0200, - STM32L5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32L5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32L5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32L5_TIM_MODE_CK_EXT = 0x0800, - STM32L5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32L5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32L5_TIM_MODE_CK_CH1 = 0x0001, - STM32L5_TIM_MODE_CK_CH2 = 0x0002, - STM32L5_TIM_MODE_CK_CH3 = 0x0003, - STM32L5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,30 +118,30 @@ enum stm32l5_tim_mode_e enum stm32l5_tim_channel_e { - STM32L5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32L5_TIM_CH_POLARITY_POS = 0x00, - STM32L5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32L5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32L5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32L5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32L5_TIM_CH_INCAPTURE = 0x10, - STM32L5_TIM_CH_INPWM = 0x20 - STM32L5_TIM_CH_DRIVE_OC = open collector mode + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC = open collector mode #endif }; diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index 0d21c17b049..b5e7ebcf759 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32L5_TIM1_RES 16 -#define STM32L5_TIM2_RES 32 -#define STM32L5_TIM3_RES 16 -#define STM32L5_TIM4_RES 16 -#define STM32L5_TIM5_RES 32 -#define STM32L5_TIM6_RES 16 -#define STM32L5_TIM7_RES 16 -#define STM32L5_TIM8_RES 16 -#define STM32L5_TIM15_RES 16 -#define STM32L5_TIM16_RES 16 -#define STM32L5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32L5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) (struct stm32l5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32L5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32L5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32L5_TIM_SETMODE(priv->tim, STM32L5_TIM_MODE_DISABLED); - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32L5_TIM_GETCLOCK(priv->tim); - period = STM32L5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32L5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32L5_TIM_SETCLOCK(priv->tim, freq); - STM32L5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32L5_TIM_SETCLOCK(priv->tim, 1000000); - STM32L5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32L5_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); - STM32L5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32L5_TIM_DISABLEINT(priv->tim, 0); - STM32L5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 4ee9481fb82..85089050ec0 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -61,9 +61,9 @@ #undef CONFIG_STM32L5_SYSTICK_HCLKd8 #ifdef CONFIG_STM32L5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32L5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32L5_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -146,5 +146,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32L5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index e8242cd559f..1b354bc4b7b 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32l5_memorymap.h" #include "stm32l5_uid.h" -#ifdef STM32L5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32l5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32L5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32L5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 1cea1f1689e..86a474e5a64 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -45,16 +45,16 @@ * * System Clock source : PLL (MSI) * SYSCLK(Hz) : 110000000 Determined by PLL configuration - * HCLK(Hz) : 110000000 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * AHB Prescaler : 1 (STM32L5_RCC_CFGR_HPRE) (Max 110MHz) - * APB1 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE1) (Max 110MHz) - * APB2 Prescaler : 1 (STM32L5_RCC_CFGR_PPRE2) (Max 110MHz) + * HCLK(Hz) : 110000000 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 110MHz) + * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 110MHz) + * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 110MHz) * MSI Frequency(Hz) : 4000000 (nominal) - * PLLM : 1 (STM32L5_PLLCFG_PLLM) - * PLLN : 55 (STM32L5_PLLCFG_PLLN) - * PLLP : 0 (STM32L5_PLLCFG_PLLP) - * PLLQ : 0 (STM32L5_PLLCFG_PLLQ) - * PLLR : 2 (STM32L5_PLLCFG_PLLR) + * PLLM : 1 (STM32_PLLCFG_PLLM) + * PLLN : 55 (STM32_PLLCFG_PLLN) + * PLLP : 0 (STM32_PLLCFG_PLLP) + * PLLQ : 0 (STM32_PLLCFG_PLLQ) + * PLLR : 2 (STM32_PLLCFG_PLLR) * Flash Latency(WS) : 5 */ @@ -65,84 +65,84 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_BOARD_USEMSI 1 -#define STM32L5_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_USEMSI 1 +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M /* prescaler common to all PLL inputs */ -#define STM32L5_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock */ -#define STM32L5_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) -#define STM32L5_PLLCFG_PLLP 0 -#undef STM32L5_PLLCFG_PLLP_ENABLED -#define STM32L5_PLLCFG_PLLQ 0 -#undef STM32L5_PLLCFG_PLLQ_ENABLED -#define STM32L5_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 -#define STM32L5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55) +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2 +#define STM32_PLLCFG_PLLR_ENABLED /* 'SAIPLL1' is not used in this application */ -#define STM32L5_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) -#define STM32L5_PLLSAI1CFG_PLLP 0 -#undef STM32L5_PLLSAI1CFG_PLLP_ENABLED -#define STM32L5_PLLSAI1CFG_PLLQ 0 -#undef STM32L5_PLLSAI1CFG_PLLQ_ENABLED -#define STM32L5_PLLSAI1CFG_PLLR 0 -#undef STM32L5_PLLSAI1CFG_PLLR_ENABLED +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24) +#define STM32_PLLSAI1CFG_PLLP 0 +#undef STM32_PLLSAI1CFG_PLLP_ENABLED +#define STM32_PLLSAI1CFG_PLLQ 0 +#undef STM32_PLLSAI1CFG_PLLQ_ENABLED +#define STM32_PLLSAI1CFG_PLLR 0 +#undef STM32_PLLSAI1CFG_PLLR_ENABLED /* 'SAIPLL2' is not used in this application */ -#define STM32L5_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) -#define STM32L5_PLLSAI2CFG_PLLP 0 -#undef STM32L5_PLLSAI2CFG_PLLP_ENABLED -#define STM32L5_PLLSAI2CFG_PLLR 0 -#undef STM32L5_PLLSAI2CFG_PLLR_ENABLED +#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8) +#define STM32_PLLSAI2CFG_PLLP 0 +#undef STM32_PLLSAI2CFG_PLLP_ENABLED +#define STM32_PLLSAI2CFG_PLLR 0 +#undef STM32_PLLSAI2CFG_PLLR_ENABLED -#define STM32L5_SYSCLK_FREQUENCY 110000000ul +#define STM32_SYSCLK_FREQUENCY 110000000ul /* Enable CLK48; get it from HSI48 */ #if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG) -# define STM32L5_USE_CLK48 1 -# define STM32L5_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -# define STM32L5_HSI48_SYNCSRC SYNCSRC_NONE +# define STM32_USE_CLK48 1 +# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif /* Enable LSE (for the RTC and for MSI autotrimming) */ -#define STM32L5_USE_LSE 1 +#define STM32_USE_LSE 1 /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32L5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32L5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32L5_PCLK1_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB1_TIM2_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM3_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM4_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM5_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM6_CLKIN (STM32L5_PCLK1_FREQUENCY) -#define STM32L5_APB1_TIM7_CLKIN (STM32L5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32L5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) -#define STM32L5_APB2_TIM1_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM15_CLKIN (STM32L5_PCLK2_FREQUENCY) -#define STM32L5_APB2_TIM16_CLKIN (STM32L5_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -150,17 +150,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 395095c7b9c..256110d0743 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -67,15 +67,15 @@ * LSE - 32.768 kHz installed */ -#define STM32L5_HSI_FREQUENCY 16000000ul -#define STM32L5_LSI_FREQUENCY 32000 -#define STM32L5_MSI_FREQUENCY 4000000ul -#define STM32L5_LSE_FREQUENCY 32768 +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_MSI_FREQUENCY 4000000ul +#define STM32_LSE_FREQUENCY 32768 -#define STM32L5_SYSCLK_FREQUENCY 110000000ul -#define STM32L5_HCLK_FREQUENCY STM32L5_SYSCLK_FREQUENCY -#define STM32L5_PCLK1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define STM32L5_PCLK2_FREQUENCY (STM32L5_HCLK_FREQUENCY / 1) +#define STM32_SYSCLK_FREQUENCY 110000000ul +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_PCLK1_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -83,17 +83,17 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM3_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM4_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM5_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM6_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM7_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM15_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32L5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32L5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY /* DMA Channel/Stream Selections ********************************************/ From 65e3f68af821b4b54e4a9262c373fc84d22222e0 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 053/268] !arch/stm32u5: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32U5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- .../src/stm32u5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_tim.h | 492 +++++++++--------- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 44 +- arch/arm/src/stm32u5/stm32_rcc.c | 16 +- arch/arm/src/stm32u5/stm32_tim.c | 332 ++++++------ arch/arm/src/stm32u5/stm32_tim.h | 72 +-- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 82 +-- arch/arm/src/stm32u5/stm32_uid.c | 6 +- .../nucleo-u5a5zj-q/src/stm32_bringup.c | 2 +- 9 files changed, 525 insertions(+), 525 deletions(-) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 616cb5e855e..90fe085d6ee 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -40,8 +40,8 @@ #define STM32_CORTEX_BASE 0xE0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32_REGION_MASK 0xF0000000 -#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_SRAM_BASE) -#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32U5_REGION_MASK) == STM32U5_FMC_BANK1) +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) +#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FMC_BANK1) /* Code Base Addresses ******************************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32_tim.h b/arch/arm/src/stm32u5/hardware/stm32_tim.h index d9adc748102..e180a60d773 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_tim.h +++ b/arch/arm/src/stm32u5/hardware/stm32_tim.h @@ -31,14 +31,14 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -46,119 +46,119 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32U5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32U5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32U5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32U5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32U5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32U5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32U5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32U5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32U5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32U5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32U5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32U5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32U5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32U5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32U5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32U5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32U5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32U5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32U5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32U5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32U5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32U5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32U5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32U5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32U5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32U5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32U5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32U5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32U5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32U5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32U5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32U5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32U5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32U5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32U5_TIM1_CR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM1_CR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM1_SMCR (STM32U5_TIM1_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM1_DIER (STM32U5_TIM1_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM1_SR (STM32U5_TIM1_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM1_EGR (STM32U5_TIM1_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM1_CCMR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM1_CCMR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM1_CCER (STM32U5_TIM1_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM1_CNT (STM32U5_TIM1_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM1_PSC (STM32U5_TIM1_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM1_ARR (STM32U5_TIM1_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM1_RCR (STM32U5_TIM1_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM1_CCR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM1_CCR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM1_CCR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM1_CCR4 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM1_BDTR (STM32U5_TIM1_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM1_DCR (STM32U5_TIM1_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM1_DMAR (STM32U5_TIM1_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM1_OR1 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM1_CCMR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM1_CCR5 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM1_CCR6 (STM32U5_TIM1_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM1_OR2 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM1_OR3 (STM32U5_TIM1_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE + STM32_ATIM_OR3_OFFSET) -#define STM32U5_TIM8_CR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR1_OFFSET) -#define STM32U5_TIM8_CR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CR2_OFFSET) -#define STM32U5_TIM8_SMCR (STM32U5_TIM8_BASE + STM32U5_ATIM_SMCR_OFFSET) -#define STM32U5_TIM8_DIER (STM32U5_TIM8_BASE + STM32U5_ATIM_DIER_OFFSET) -#define STM32U5_TIM8_SR (STM32U5_TIM8_BASE + STM32U5_ATIM_SR_OFFSET) -#define STM32U5_TIM8_EGR (STM32U5_TIM8_BASE + STM32U5_ATIM_EGR_OFFSET) -#define STM32U5_TIM8_CCMR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR1_OFFSET) -#define STM32U5_TIM8_CCMR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR2_OFFSET) -#define STM32U5_TIM8_CCER (STM32U5_TIM8_BASE + STM32U5_ATIM_CCER_OFFSET) -#define STM32U5_TIM8_CNT (STM32U5_TIM8_BASE + STM32U5_ATIM_CNT_OFFSET) -#define STM32U5_TIM8_PSC (STM32U5_TIM8_BASE + STM32U5_ATIM_PSC_OFFSET) -#define STM32U5_TIM8_ARR (STM32U5_TIM8_BASE + STM32U5_ATIM_ARR_OFFSET) -#define STM32U5_TIM8_RCR (STM32U5_TIM8_BASE + STM32U5_ATIM_RCR_OFFSET) -#define STM32U5_TIM8_CCR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR1_OFFSET) -#define STM32U5_TIM8_CCR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR2_OFFSET) -#define STM32U5_TIM8_CCR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR3_OFFSET) -#define STM32U5_TIM8_CCR4 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR4_OFFSET) -#define STM32U5_TIM8_BDTR (STM32U5_TIM8_BASE + STM32U5_ATIM_BDTR_OFFSET) -#define STM32U5_TIM8_DCR (STM32U5_TIM8_BASE + STM32U5_ATIM_DCR_OFFSET) -#define STM32U5_TIM8_DMAR (STM32U5_TIM8_BASE + STM32U5_ATIM_DMAR_OFFSET) -#define STM32U5_TIM8_OR1 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR1_OFFSET) -#define STM32U5_TIM8_CCMR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCMR3_OFFSET) -#define STM32U5_TIM8_CCR5 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR5_OFFSET) -#define STM32U5_TIM8_CCR6 (STM32U5_TIM8_BASE + STM32U5_ATIM_CCR6_OFFSET) -#define STM32U5_TIM8_OR2 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR2_OFFSET) -#define STM32U5_TIM8_OR3 (STM32U5_TIM8_BASE + STM32U5_ATIM_OR3_OFFSET) +#define STM32_TIM8_CR1 (STM32_TIM8_BASE + STM32_ATIM_CR1_OFFSET) +#define STM32_TIM8_CR2 (STM32_TIM8_BASE + STM32_ATIM_CR2_OFFSET) +#define STM32_TIM8_SMCR (STM32_TIM8_BASE + STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM8_DIER (STM32_TIM8_BASE + STM32_ATIM_DIER_OFFSET) +#define STM32_TIM8_SR (STM32_TIM8_BASE + STM32_ATIM_SR_OFFSET) +#define STM32_TIM8_EGR (STM32_TIM8_BASE + STM32_ATIM_EGR_OFFSET) +#define STM32_TIM8_CCMR1 (STM32_TIM8_BASE + STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM8_CCMR2 (STM32_TIM8_BASE + STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM8_CCER (STM32_TIM8_BASE + STM32_ATIM_CCER_OFFSET) +#define STM32_TIM8_CNT (STM32_TIM8_BASE + STM32_ATIM_CNT_OFFSET) +#define STM32_TIM8_PSC (STM32_TIM8_BASE + STM32_ATIM_PSC_OFFSET) +#define STM32_TIM8_ARR (STM32_TIM8_BASE + STM32_ATIM_ARR_OFFSET) +#define STM32_TIM8_RCR (STM32_TIM8_BASE + STM32_ATIM_RCR_OFFSET) +#define STM32_TIM8_CCR1 (STM32_TIM8_BASE + STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM8_CCR2 (STM32_TIM8_BASE + STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM8_CCR3 (STM32_TIM8_BASE + STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM8_CCR4 (STM32_TIM8_BASE + STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM8_BDTR (STM32_TIM8_BASE + STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM8_DCR (STM32_TIM8_BASE + STM32_ATIM_DCR_OFFSET) +#define STM32_TIM8_DMAR (STM32_TIM8_BASE + STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM8_OR1 (STM32_TIM8_BASE + STM32_ATIM_OR1_OFFSET) +#define STM32_TIM8_CCMR3 (STM32_TIM8_BASE + STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM8_CCR5 (STM32_TIM8_BASE + STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM8_CCR6 (STM32_TIM8_BASE + STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM8_OR2 (STM32_TIM8_BASE + STM32_ATIM_OR2_OFFSET) +#define STM32_TIM8_OR3 (STM32_TIM8_BASE + STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM3, TIM4, TIM5, and TIM15-17. * TIM3 and 4 are 16-bit. @@ -166,154 +166,154 @@ * TIM15, 16 and 17 are 16-bit. */ -#define STM32U5_TIM2_CR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM2_CR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM2_SMCR (STM32U5_TIM2_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM2_DIER (STM32U5_TIM2_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM2_SR (STM32U5_TIM2_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM2_EGR (STM32U5_TIM2_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM2_CCMR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM2_CCMR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM2_CCER (STM32U5_TIM2_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM2_CNT (STM32U5_TIM2_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM2_PSC (STM32U5_TIM2_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM2_ARR (STM32U5_TIM2_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM2_CCR1 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM2_CCR2 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM2_CCR3 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM2_CCR4 (STM32U5_TIM2_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM2_DCR (STM32U5_TIM2_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM2_DMAR (STM32U5_TIM2_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM2_OR (STM32U5_TIM2_BASE + STM32U5_GTIM_OR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE + STM32_GTIM_OR_OFFSET) -#define STM32U5_TIM3_CR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM3_CR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM3_SMCR (STM32U5_TIM3_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM3_DIER (STM32U5_TIM3_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM3_SR (STM32U5_TIM3_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM3_EGR (STM32U5_TIM3_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM3_CCMR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM3_CCMR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM3_CCER (STM32U5_TIM3_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM3_CNT (STM32U5_TIM3_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM3_PSC (STM32U5_TIM3_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM3_ARR (STM32U5_TIM3_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM3_CCR1 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM3_CCR2 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM3_CCR3 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM3_CCR4 (STM32U5_TIM3_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM3_DCR (STM32U5_TIM3_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM3_DMAR (STM32U5_TIM3_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM3_CR1 (STM32_TIM3_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM3_CR2 (STM32_TIM3_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM3_SMCR (STM32_TIM3_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM3_DIER (STM32_TIM3_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM3_SR (STM32_TIM3_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM3_EGR (STM32_TIM3_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM3_CCMR1 (STM32_TIM3_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM3_CCMR2 (STM32_TIM3_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM3_CCER (STM32_TIM3_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM3_CNT (STM32_TIM3_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM3_PSC (STM32_TIM3_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM3_ARR (STM32_TIM3_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM3_CCR1 (STM32_TIM3_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM3_CCR2 (STM32_TIM3_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM3_CCR3 (STM32_TIM3_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM3_CCR4 (STM32_TIM3_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM3_DCR (STM32_TIM3_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM3_DMAR (STM32_TIM3_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32U5_TIM4_CR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM4_CR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM4_SMCR (STM32U5_TIM4_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM4_DIER (STM32U5_TIM4_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM4_SR (STM32U5_TIM4_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM4_EGR (STM32U5_TIM4_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM4_CCMR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM4_CCMR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM4_CCER (STM32U5_TIM4_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM4_CNT (STM32U5_TIM4_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM4_PSC (STM32U5_TIM4_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM4_ARR (STM32U5_TIM4_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM4_CCR1 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM4_CCR2 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM4_CCR3 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM4_CCR4 (STM32U5_TIM4_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM4_DCR (STM32U5_TIM4_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM4_DMAR (STM32U5_TIM4_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM4_CR1 (STM32_TIM4_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM4_CR2 (STM32_TIM4_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM4_SMCR (STM32_TIM4_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM4_DIER (STM32_TIM4_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM4_SR (STM32_TIM4_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM4_EGR (STM32_TIM4_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM4_CCMR1 (STM32_TIM4_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM4_CCMR2 (STM32_TIM4_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM4_CCER (STM32_TIM4_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM4_CNT (STM32_TIM4_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM4_PSC (STM32_TIM4_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM4_ARR (STM32_TIM4_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM4_CCR1 (STM32_TIM4_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM4_CCR2 (STM32_TIM4_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM4_CCR3 (STM32_TIM4_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM4_CCR4 (STM32_TIM4_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM4_DCR (STM32_TIM4_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM4_DMAR (STM32_TIM4_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_CR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM5_CR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM5_SMCR (STM32U5_TIM5_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM5_DIER (STM32U5_TIM5_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM5_SR (STM32U5_TIM5_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM5_EGR (STM32U5_TIM5_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM5_CCMR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM5_CCMR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCMR2_OFFSET) -#define STM32U5_TIM5_CCER (STM32U5_TIM5_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM5_CNT (STM32U5_TIM5_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM5_PSC (STM32U5_TIM5_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM5_ARR (STM32U5_TIM5_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM5_CCR1 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM5_CCR2 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM5_CCR3 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR3_OFFSET) -#define STM32U5_TIM5_CCR4 (STM32U5_TIM5_BASE + STM32U5_GTIM_CCR4_OFFSET) -#define STM32U5_TIM5_DCR (STM32U5_TIM5_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM5_DMAR (STM32U5_TIM5_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM5_OR (STM32U5_TIM5_BASE + STM32U5_GTIM_OR_OFFSET) +#define STM32_TIM5_CR1 (STM32_TIM5_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM5_CR2 (STM32_TIM5_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM5_SMCR (STM32_TIM5_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM5_DIER (STM32_TIM5_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM5_SR (STM32_TIM5_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM5_EGR (STM32_TIM5_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM5_CCMR1 (STM32_TIM5_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM5_CCMR2 (STM32_TIM5_BASE + STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM5_CCER (STM32_TIM5_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM5_CNT (STM32_TIM5_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM5_PSC (STM32_TIM5_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM5_ARR (STM32_TIM5_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM5_CCR1 (STM32_TIM5_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM5_CCR2 (STM32_TIM5_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM5_CCR3 (STM32_TIM5_BASE + STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM5_CCR4 (STM32_TIM5_BASE + STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM5_DCR (STM32_TIM5_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM5_DMAR (STM32_TIM5_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM5_OR (STM32_TIM5_BASE + STM32_GTIM_OR_OFFSET) -#define STM32U5_TIM15_CR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM15_CR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM15_SMCR (STM32U5_TIM15_BASE + STM32U5_GTIM_SMCR_OFFSET) -#define STM32U5_TIM15_DIER (STM32U5_TIM15_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM15_SR (STM32U5_TIM15_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM15_EGR (STM32U5_TIM15_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM15_CCMR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM15_CCER (STM32U5_TIM15_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM15_CNT (STM32U5_TIM15_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM15_PSC (STM32U5_TIM15_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM15_ARR (STM32U5_TIM15_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM15_RCR (STM32U5_TIM15_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM15_CCR1 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM15_CCR2 (STM32U5_TIM15_BASE + STM32U5_GTIM_CCR2_OFFSET) -#define STM32U5_TIM15_BDTR (STM32U5_TIM15_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM15_DCR (STM32U5_TIM15_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM15_DMAR (STM32U5_TIM15_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM15_CR1 (STM32_TIM15_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM15_CR2 (STM32_TIM15_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM15_SMCR (STM32_TIM15_BASE + STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM15_DIER (STM32_TIM15_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM15_SR (STM32_TIM15_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM15_EGR (STM32_TIM15_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM15_CCMR1 (STM32_TIM15_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM15_CCER (STM32_TIM15_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM15_CNT (STM32_TIM15_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM15_PSC (STM32_TIM15_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM15_ARR (STM32_TIM15_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM15_RCR (STM32_TIM15_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM15_CCR1 (STM32_TIM15_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM15_CCR2 (STM32_TIM15_BASE + STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM15_BDTR (STM32_TIM15_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM15_DCR (STM32_TIM15_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM15_DMAR (STM32_TIM15_BASE + STM32_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_CR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM16_CR2 (STM32U5_TIM16_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM16_DIER (STM32U5_TIM16_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM16_SR (STM32U5_TIM16_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM16_EGR (STM32U5_TIM16_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM16_CCMR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM16_CCER (STM32U5_TIM16_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM16_CNT (STM32U5_TIM16_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM16_PSC (STM32U5_TIM16_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM16_ARR (STM32U5_TIM16_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM16_RCR (STM32U5_TIM16_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM16_CCR1 (STM32U5_TIM16_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM16_BDTR (STM32U5_TIM16_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM16_DCR (STM32U5_TIM16_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM16_DMAR (STM32U5_TIM16_BASE + STM32U5_GTIM_DMAR_OFFSET) -#define STM32U5_TIM16_OR (STM32U5_TIM16_BASE + STM32U5_GTIM_OR_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE + STM32_GTIM_OR_OFFSET) -#define STM32U5_TIM17_CR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR1_OFFSET) -#define STM32U5_TIM17_CR2 (STM32U5_TIM17_BASE + STM32U5_GTIM_CR2_OFFSET) -#define STM32U5_TIM17_DIER (STM32U5_TIM17_BASE + STM32U5_GTIM_DIER_OFFSET) -#define STM32U5_TIM17_SR (STM32U5_TIM17_BASE + STM32U5_GTIM_SR_OFFSET) -#define STM32U5_TIM17_EGR (STM32U5_TIM17_BASE + STM32U5_GTIM_EGR_OFFSET) -#define STM32U5_TIM17_CCMR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCMR1_OFFSET) -#define STM32U5_TIM17_CCER (STM32U5_TIM17_BASE + STM32U5_GTIM_CCER_OFFSET) -#define STM32U5_TIM17_CNT (STM32U5_TIM17_BASE + STM32U5_GTIM_CNT_OFFSET) -#define STM32U5_TIM17_PSC (STM32U5_TIM17_BASE + STM32U5_GTIM_PSC_OFFSET) -#define STM32U5_TIM17_ARR (STM32U5_TIM17_BASE + STM32U5_GTIM_ARR_OFFSET) -#define STM32U5_TIM17_RCR (STM32U5_TIM17_BASE + STM32U5_GTIM_RCR_OFFSET) -#define STM32U5_TIM17_CCR1 (STM32U5_TIM17_BASE + STM32U5_GTIM_CCR1_OFFSET) -#define STM32U5_TIM17_BDTR (STM32U5_TIM17_BASE + STM32U5_GTIM_BDTR_OFFSET) -#define STM32U5_TIM17_DCR (STM32U5_TIM17_BASE + STM32U5_GTIM_DCR_OFFSET) -#define STM32U5_TIM17_DMAR (STM32U5_TIM17_BASE + STM32U5_GTIM_DMAR_OFFSET) +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_GTIM_DMAR_OFFSET) /* Basic Timers - TIM6 and TIM7 */ -#define STM32U5_TIM6_CR1 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM6_CR2 (STM32U5_TIM6_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM6_DIER (STM32U5_TIM6_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM6_SR (STM32U5_TIM6_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM6_EGR (STM32U5_TIM6_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM6_CNT (STM32U5_TIM6_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM6_PSC (STM32U5_TIM6_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM6_ARR (STM32U5_TIM6_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM6_CR1 (STM32_TIM6_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM6_CR2 (STM32_TIM6_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM6_DIER (STM32_TIM6_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM6_SR (STM32_TIM6_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM6_EGR (STM32_TIM6_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM6_CNT (STM32_TIM6_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM6_PSC (STM32_TIM6_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM6_ARR (STM32_TIM6_BASE + STM32_BTIM_ARR_OFFSET) -#define STM32U5_TIM7_CR1 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR1_OFFSET) -#define STM32U5_TIM7_CR2 (STM32U5_TIM7_BASE + STM32U5_BTIM_CR2_OFFSET) -#define STM32U5_TIM7_DIER (STM32U5_TIM7_BASE + STM32U5_BTIM_DIER_OFFSET) -#define STM32U5_TIM7_SR (STM32U5_TIM7_BASE + STM32U5_BTIM_SR_OFFSET) -#define STM32U5_TIM7_EGR (STM32U5_TIM7_BASE + STM32U5_BTIM_EGR_OFFSET) -#define STM32U5_TIM7_CNT (STM32U5_TIM7_BASE + STM32U5_BTIM_CNT_OFFSET) -#define STM32U5_TIM7_PSC (STM32U5_TIM7_BASE + STM32U5_BTIM_PSC_OFFSET) -#define STM32U5_TIM7_ARR (STM32U5_TIM7_BASE + STM32U5_BTIM_ARR_OFFSET) +#define STM32_TIM7_CR1 (STM32_TIM7_BASE + STM32_BTIM_CR1_OFFSET) +#define STM32_TIM7_CR2 (STM32_TIM7_BASE + STM32_BTIM_CR2_OFFSET) +#define STM32_TIM7_DIER (STM32_TIM7_BASE + STM32_BTIM_DIER_OFFSET) +#define STM32_TIM7_SR (STM32_TIM7_BASE + STM32_BTIM_SR_OFFSET) +#define STM32_TIM7_EGR (STM32_TIM7_BASE + STM32_BTIM_EGR_OFFSET) +#define STM32_TIM7_CNT (STM32_TIM7_BASE + STM32_BTIM_CNT_OFFSET) +#define STM32_TIM7_PSC (STM32_TIM7_BASE + STM32_BTIM_PSC_OFFSET) +#define STM32_TIM7_ARR (STM32_TIM7_BASE + STM32_BTIM_ARR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 56fc25f0624..20bb8da6654 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -41,31 +41,31 @@ /* Register Offsets *********************************************************/ -#define STM32U5_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ -#define STM32U5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32U5_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ -#define STM32U5_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ -#define STM32U5_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ -#define STM32U5_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ -#define STM32U5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32U5_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ -#define STM32U5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32U5_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32U5_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ +#define STM32_SYSCFG_SECCFGR_OFFSET 0x0000 /* SYSCFG secure configuration register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_FPUIMR_OFFSET 0x0008 /* SYSCFG FPU interrupt mask register */ +#define STM32_SYSCFG_CNSLCKR_OFFSET 0x000c /* SYSCFG CPU non-secure lock register */ +#define STM32_SYSCFG_CSLCKR_OFFSET 0x0010 /* SYSCFG CPU secure lock register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x0014 /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_SKR_OFFSET 0x001c /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0024 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_RSSCMDR_OFFSET 0x002c /* SYSCFG RSS command register */ /* Register Addresses *******************************************************/ -#define STM32U5_SYSCFG_SECCFGR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SECCFGR_OFFSET) -#define STM32U5_SYSCFG_CFGR1 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR1_OFFSET) -#define STM32U5_SYSCFG_FPUIMR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_FPUIMR_OFFSET) -#define STM32U5_SYSCFG_CNSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CNSLCKR_OFFSET) -#define STM32U5_SYSCFG_CSLCKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CSLCKR_OFFSET) -#define STM32U5_SYSCFG_CFGR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_CFGR2_OFFSET) -#define STM32U5_SYSCFG_SCSR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SCSR_OFFSET) -#define STM32U5_SYSCFG_SKR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SKR_OFFSET) -#define STM32U5_SYSCFG_SWPR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR_OFFSET) -#define STM32U5_SYSCFG_SWPR2 (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_SWPR2_OFFSET) -#define STM32U5_SYSCFG_RSSCMDR (STM32U5_SYSCFG_BASE + STM32U5_SYSCFG_RSSCMDR_OFFSET) +#define STM32_SYSCFG_SECCFGR (STM32_SYSCFG_BASE + STM32_SYSCFG_SECCFGR_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_FPUIMR (STM32_SYSCFG_BASE + STM32_SYSCFG_FPUIMR_OFFSET) +#define STM32_SYSCFG_CNSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CNSLCKR_OFFSET) +#define STM32_SYSCFG_CSLCKR (STM32_SYSCFG_BASE + STM32_SYSCFG_CSLCKR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_RSSCMDR (STM32_SYSCFG_BASE + STM32_SYSCFG_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index aa334d99305..2b2972cde72 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -93,14 +93,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32U5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32U5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -113,19 +113,19 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32U5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32U5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32U5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32U5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32U5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } stm32_pwr_enablebkp(false); diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 5e15c461d18..7dbdba50ce4 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -305,16 +305,16 @@ static const struct stm32_tim_ops_s stm32_tim_ops = struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32U5_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -322,8 +322,8 @@ struct stm32_tim_priv_s stm32_tim2_priv = struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -331,8 +331,8 @@ struct stm32_tim_priv_s stm32_tim3_priv = struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -340,8 +340,8 @@ struct stm32_tim_priv_s stm32_tim4_priv = struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -349,8 +349,8 @@ struct stm32_tim_priv_s stm32_tim5_priv = struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -358,8 +358,8 @@ struct stm32_tim_priv_s stm32_tim6_priv = struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -367,8 +367,8 @@ struct stm32_tim_priv_s stm32_tim7_priv = struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -376,8 +376,8 @@ struct stm32_tim_priv_s stm32_tim8_priv = struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -385,8 +385,8 @@ struct stm32_tim_priv_s stm32_tim15_priv = struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -394,8 +394,8 @@ struct stm32_tim_priv_s stm32_tim16_priv = struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, - .mode = STM32U5_TIM_MODE_UNUSED, - .base = STM32U5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -483,9 +483,9 @@ static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32_putreg16(dev, STM32U5_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -494,10 +494,10 @@ static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -506,9 +506,9 @@ static void stm32_tim_enable(struct stm32_tim_dev_s *dev) static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32_getreg16(dev, STM32U5_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -522,7 +522,7 @@ static void stm32_tim_disable(struct stm32_tim_dev_s *dev) static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_DISABLED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32_tim_disable(dev); } @@ -540,7 +540,7 @@ static void stm32_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32U5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32_configgpio(cfg); } @@ -566,13 +566,13 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -581,19 +581,19 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32U5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32U5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32U5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32U5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32U5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -602,7 +602,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, break; - case STM32U5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -611,15 +611,15 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, } stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32U5_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32U5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32_modifyreg16(dev, STM32U5_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -655,66 +655,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -745,7 +745,7 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, prescaler = 0xffff; } - stm32_putreg16(dev, STM32U5_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32_tim_enable(dev); return prescaler; @@ -770,64 +770,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -837,7 +837,7 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32_getreg16(dev, STM32U5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -849,7 +849,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32_putreg32(dev, STM32U5_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -859,7 +859,7 @@ static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32_getreg32 (dev, STM32U5_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -869,7 +869,7 @@ static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32_getreg32(dev, STM32U5_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -879,10 +879,10 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -906,7 +906,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32U5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -919,7 +919,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32_getreg16(dev, STM32U5_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -927,13 +927,13 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32U5_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32U5_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32U5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32U5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -942,12 +942,12 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32U5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32U5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32U5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32U5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -974,21 +974,21 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32U5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32_putreg16(dev, ccmr_offset, ccmr_orig); - stm32_putreg16(dev, STM32U5_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1021,7 +1021,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1054,7 +1054,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1087,7 +1087,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1119,7 +1119,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1152,7 +1152,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1185,7 +1185,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1251,7 +1251,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1303,19 +1303,19 @@ static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - stm32_putreg32(dev, STM32U5_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32_putreg32(dev, STM32U5_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32_putreg32(dev, STM32U5_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32_putreg32(dev, STM32U5_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1337,16 +1337,16 @@ static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, switch (channel) { case 1: - return stm32_getreg32(dev, STM32U5_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32_getreg32(dev, STM32U5_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32_getreg32(dev, STM32U5_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32_getreg32(dev, STM32U5_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1367,66 +1367,66 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - vectorno = STM32U5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - vectorno = STM32U5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - vectorno = STM32U5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - vectorno = STM32U5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - vectorno = STM32U5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - vectorno = STM32U5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - vectorno = STM32U5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - vectorno = STM32U5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - vectorno = STM32U5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - vectorno = STM32U5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - vectorno = STM32U5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1459,7 +1459,7 @@ static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1470,7 +1470,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32U5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1479,7 +1479,7 @@ static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32_putreg16(dev, STM32U5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1489,7 +1489,7 @@ static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32_getreg16(dev, STM32U5_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1512,76 +1512,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) #ifdef CONFIG_STM32U5_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32U5_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32U5_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32U5_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32U5_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32U5_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32U5_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; - modifyreg32(STM32U5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32U5_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32U5_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32U5_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32U5_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; - modifyreg32(STM32U5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,7 +1591,7 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32_tim_priv_s *)dev)->mode != STM32U5_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1617,67 +1617,67 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32U5_TIM1 - case STM32U5_TIM1_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM2 - case STM32U5_TIM2_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM3 - case STM32U5_TIM3_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM4 - case STM32U5_TIM4_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM5 - case STM32U5_TIM5_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM6 - case STM32U5_TIM6_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM7 - case STM32U5_TIM7_BASE: - modifyreg32(STM32U5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM8 - case STM32U5_TIM8_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM15 - case STM32U5_TIM15_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM16 - case STM32U5_TIM16_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32U5_TIM17 - case STM32U5_TIM17_BASE: - modifyreg32(STM32U5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1687,7 +1687,7 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32_tim_priv_s *)dev)->mode = STM32U5_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32u5/stm32_tim.h b/arch/arm/src/stm32u5/stm32_tim.h index e043e98f0e0..f61751552dd 100644 --- a/arch/arm/src/stm32u5/stm32_tim.h +++ b/arch/arm/src/stm32u5/stm32_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32U5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32U5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32U5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32U5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32U5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32U5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32U5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32U5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32U5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32U5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32U5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32U5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32U5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32U5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32_tim_dev_s enum stm32_tim_mode_e { - STM32U5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32U5_TIM_MODE_MASK = 0x0310, - STM32U5_TIM_MODE_DISABLED = 0x0000, - STM32U5_TIM_MODE_UP = 0x0100, - STM32U5_TIM_MODE_DOWN = 0x0110, - STM32U5_TIM_MODE_UPDOWN = 0x0200, - STM32U5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32U5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32U5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32U5_TIM_MODE_CK_EXT = 0x0800, - STM32U5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32U5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32U5_TIM_MODE_CK_CH1 = 0x0001, - STM32U5_TIM_MODE_CK_CH2 = 0x0002, - STM32U5_TIM_MODE_CK_CH3 = 0x0003, - STM32U5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32_tim_mode_e enum stm32_tim_channel_e { - STM32U5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32U5_TIM_CH_POLARITY_POS = 0x00, - STM32U5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32U5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32U5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32U5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 92e5739a233..7752a4fda1b 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32U5_TIM1_RES 16 -#define STM32U5_TIM2_RES 32 -#define STM32U5_TIM3_RES 16 -#define STM32U5_TIM4_RES 16 -#define STM32U5_TIM5_RES 32 -#define STM32U5_TIM6_RES 16 -#define STM32U5_TIM7_RES 16 -#define STM32U5_TIM8_RES 16 -#define STM32U5_TIM15_RES 16 -#define STM32U5_TIM16_RES 16 -#define STM32U5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32U5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32_timer_handler(int irq, void *context, void *arg) (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32U5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32U5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32U5_TIM_SETMODE(priv->tim, STM32U5_TIM_MODE_DISABLED); - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32U5_TIM_GETCLOCK(priv->tim); - period = STM32U5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000) ? 1 : (clock / 1000000); - status->timeleft = (timeout - STM32U5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32U5_TIM_SETCLOCK(priv->tim, freq); - STM32U5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32U5_TIM_SETCLOCK(priv->tim, 1000000); - STM32U5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32U5_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); - STM32U5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32U5_TIM_DISABLEINT(priv->tim, 0); - STM32U5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32u5/stm32_uid.c b/arch/arm/src/stm32u5/stm32_uid.c index 55b3aa8e82a..479826dafd2 100644 --- a/arch/arm/src/stm32u5/stm32_uid.c +++ b/arch/arm/src/stm32u5/stm32_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32_memorymap.h" #include "stm32_uid.h" -#ifdef STM32U5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32U5_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32U5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c index 2d246c3377f..5cde87263ab 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_bringup.c @@ -118,7 +118,7 @@ int stm32_bringup(void) return -1; } -#if defined(STM32U5_I2C2) +#if defined(STM32_I2C2) i2c2_m = stm32_i2cbus_initialize(2); if (i2c2_m == NULL) { From 61e6b87ddec2387689870e8f487017b79f3f7a47 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 054/268] !arch/stm32wb: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32WB non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32wb/chip.h | 106 +++---- arch/arm/include/stm32wb/irq.h | 30 +- arch/arm/include/stm32wb/stm32wb_irq.h | 148 ++++----- arch/arm/src/stm32wb/chip.h | 2 +- arch/arm/src/stm32wb/hardware/stm32wb_crs.h | 16 +- arch/arm/src/stm32wb/hardware/stm32wb_dma.h | 228 +++++++------- .../arm/src/stm32wb/hardware/stm32wb_dmamux.h | 103 +++---- arch/arm/src/stm32wb/hardware/stm32wb_exti.h | 64 ++-- arch/arm/src/stm32wb/hardware/stm32wb_flash.h | 90 +++--- arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 150 +++++----- arch/arm/src/stm32wb/hardware/stm32wb_i2c.h | 66 ++-- arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h | 32 +- .../src/stm32wb/hardware/stm32wb_memorymap.h | 168 +++++------ arch/arm/src/stm32wb/hardware/stm32wb_pwr.h | 90 +++--- arch/arm/src/stm32wb/hardware/stm32wb_rcc.h | 192 ++++++------ arch/arm/src/stm32wb/hardware/stm32wb_rtc.h | 162 +++++----- arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 44 +-- .../arm/src/stm32wb/hardware/stm32wb_syscfg.h | 58 ++-- arch/arm/src/stm32wb/hardware/stm32wb_tim.h | 282 +++++++++--------- arch/arm/src/stm32wb/hardware/stm32wb_uart.h | 50 ++-- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 12 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 92 +++--- arch/arm/src/stm32wb/stm32wb_dma.c | 180 +++++------ arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 16 +- arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 16 +- arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 16 +- arch/arm/src/stm32wb/stm32wb_flash.c | 80 ++--- arch/arm/src/stm32wb/stm32wb_freerun.c | 32 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 50 ++-- arch/arm/src/stm32wb/stm32wb_gpio.h | 8 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 90 +++--- arch/arm/src/stm32wb/stm32wb_ipcc.c | 30 +- arch/arm/src/stm32wb/stm32wb_ipcc.h | 22 +- arch/arm/src/stm32wb/stm32wb_irq.c | 50 ++-- arch/arm/src/stm32wb/stm32wb_lowputc.c | 136 ++++----- arch/arm/src/stm32wb/stm32wb_mbox.c | 102 +++---- arch/arm/src/stm32wb/stm32wb_mbox.h | 36 +-- arch/arm/src/stm32wb/stm32wb_mbox_shci.h | 108 +++---- arch/arm/src/stm32wb/stm32wb_oneshot.c | 28 +- arch/arm/src/stm32wb/stm32wb_pmlpr.c | 14 +- arch/arm/src/stm32wb/stm32wb_pmstandby.c | 6 +- arch/arm/src/stm32wb/stm32wb_pmstop.c | 8 +- arch/arm/src/stm32wb/stm32wb_pwr.c | 22 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 244 +++++++-------- arch/arm/src/stm32wb/stm32wb_rcc.h | 4 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 26 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 8 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 6 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 198 ++++++------ arch/arm/src/stm32wb/stm32wb_rtc.h | 6 +- arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 4 +- arch/arm/src/stm32wb/stm32wb_serial.c | 154 +++++----- arch/arm/src/stm32wb/stm32wb_spi.c | 74 ++--- arch/arm/src/stm32wb/stm32wb_start.c | 4 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 60 ++-- arch/arm/src/stm32wb/stm32wb_tim.c | 234 +++++++-------- arch/arm/src/stm32wb/stm32wb_tim.h | 88 +++--- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 54 ++-- arch/arm/src/stm32wb/stm32wb_timerisr.c | 8 +- arch/arm/src/stm32wb/stm32wb_uid.c | 6 +- .../arm/stm32wb/flipperzero/include/board.h | 8 +- .../include/flipperzero-clocking.h | 122 ++++---- .../flipperzero/src/stm32_lcd_st7565.c | 24 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 4 +- .../nucleo-wb55rg/include/nucleo-wb55rg.h | 122 ++++---- 67 files changed, 2375 insertions(+), 2374 deletions(-) diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 56d7912fe51..61ffe8eb774 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -33,83 +33,83 @@ * Pre-processor Prototypes ****************************************************************************/ -#define STM32WB_NFSMC 0 /* No FSMC */ -#define STM32WB_NBTIM 0 /* No basic timers */ -#define STM32WB_NATIM 1 /* One advanced timers TIM1 */ -#define STM32WB_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ -#define STM32WB_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ -#define STM32WB_NGTIMNDMA 0 /* No general timers without DMA */ +#define STM32_NFSMC 0 /* No FSMC */ +#define STM32_NBTIM 0 /* No basic timers */ +#define STM32_NATIM 1 /* One advanced timers TIM1 */ +#define STM32_NGTIM32 1 /* 32-bit general timers TIM2 with DMA */ +#define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ +#define STM32_NGTIMNDMA 0 /* No general timers without DMA */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else -# define STM32WB_NGTIM16 0 /* No 16-bit general timers */ +# define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NDMA 2 /* DMA1-2 with 7 channels each */ -# define STM32WB_NI2S 1 /* SAI1 (dual channel high quality audio) */ -# define STM32WB_NI2C 2 /* I2C1, I2C3 */ -# define STM32WB_NUSBOTG 1 /* USB 2.0 FS */ -# define STM32WB_NCMP 2 /* Two Comparators */ +# define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ +# define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ +# define STM32_NI2C 2 /* I2C1, I2C3 */ +# define STM32_NUSBOTG 1 /* USB 2.0 FS */ +# define STM32_NCMP 2 /* Two Comparators */ # if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NSPI 3 /* SPI1-2, QSPI */ +# define STM32_NSPI 3 /* SPI1-2, QSPI */ # else -# define STM32WB_NSPI 2 /* SPI1, QSPI */ +# define STM32_NSPI 2 /* SPI1, QSPI */ # endif #else -# define STM32WB_NDMA 1 /* DMA1 with 7 channels */ -# define STM32WB_NI2S 0 /* No SAI */ -# define STM32WB_NI2C 1 /* I2C1 */ -# define STM32WB_NUSBOTG 0 /* No USB */ -# define STM32WB_NCMP 0 /* No Comparators */ -# define STM32WB_NSPI 1 /* SPI1 */ +# define STM32_NDMA 1 /* DMA1 with 7 channels */ +# define STM32_NI2S 0 /* No SAI */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NUSBOTG 0 /* No USB */ +# define STM32_NCMP 0 /* No Comparators */ +# define STM32_NSPI 1 /* SPI1 */ #endif #if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLPUART 1 /* LPUART1 */ +# define STM32_NLPUART 1 /* LPUART1 */ #else -# define STM32WB_NLPUART 0 /* No LPUART */ +# define STM32_NLPUART 0 /* No LPUART */ #endif #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NCAPSENSE 18 /* Capacitive sensing channels */ +# define STM32_NCAPSENSE 18 /* Capacitive sensing channels */ #else -# define STM32WB_NCAPSENSE 0 /* No Capacitive sensing */ +# define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_NLCD 1 /* One LCD controller with up to 8x40 +# define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 * 55Rx: 4x28 * 55Vx: 4x44, 8x40 */ #else -# define STM32WB_NLCD 0 /* No LCD */ +# define STM32_NLCD 0 /* No LCD */ #endif -#define STM32WB_NUSART 1 /* USART1 */ -#define STM32WB_NCAN 0 /* No CAN */ -#define STM32WB_NSDIO 0 /* No SDIO interface */ -#define STM32WB_NADC 1 /* ADC1, up to 19-channels */ -#define STM32WB_NDAC 0 /* No DAC */ -#define STM32WB_NCRC 1 /* CRC */ -#define STM32WB_NETHERNET 0 /* No ethernet */ -#define STM32WB_NRNG 1 /* Random number generator (RNG) */ -#define STM32WB_NDCMI 0 /* No digital camera interface (DCMI) */ +#define STM32_NUSART 1 /* USART1 */ +#define STM32_NCAN 0 /* No CAN */ +#define STM32_NSDIO 0 /* No SDIO interface */ +#define STM32_NADC 1 /* ADC1, up to 19-channels */ +#define STM32_NDAC 0 /* No DAC */ +#define STM32_NCRC 1 /* CRC */ +#define STM32_NETHERNET 0 /* No ethernet */ +#define STM32_NRNG 1 /* Random number generator (RNG) */ +#define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ #if defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_NGPIO 30 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 30 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_48E) -# define STM32WB_NGPIO 37 /* GPIO[A,B,C,E,H] */ +# define STM32_NGPIO 37 /* GPIO[A,B,C,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_C_49) -# define STM32WB_NGPIO 25 /* GPIO[A,B,C,H] */ +# define STM32_NGPIO 25 /* GPIO[A,B,C,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_R) -# define STM32WB_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 49 /* GPIO[A,B,C,D,E,H] */ #elif defined(CONFIG_STM32WB_IO_CONFIG_V) -# define STM32WB_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ +# define STM32_NGPIO 72 /* GPIO[A,B,C,D,E,H] */ #else # error "Unsupported STM32WB chip" #endif @@ -139,23 +139,23 @@ */ #if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_SRAM1_SIZE (12*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (4*1024) +# define STM32_SRAM1_SIZE (12*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (4*1024) #elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) -# define STM32WB_SRAM1_SIZE (32*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (32*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ && defined(CONFIG_STM32WB_IO_CONFIG_C) -# define STM32WB_SRAM1_SIZE (64*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (64*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #elif defined(CONFIG_STM32WB_STM32WB55) && \ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) -# define STM32WB_SRAM1_SIZE (192*1024) -# define STM32WB_SRAM2A_SIZE (32*1024) -# define STM32WB_SRAM2B_SIZE (32*1024) +# define STM32_SRAM1_SIZE (192*1024) +# define STM32_SRAM2A_SIZE (32*1024) +# define STM32_SRAM2B_SIZE (32*1024) #else # error "Unsupported STM32WB chip" #endif diff --git a/arch/arm/include/stm32wb/irq.h b/arch/arm/include/stm32wb/irq.h index 6bd24af39e9..381c7e9778d 100644 --- a/arch/arm/include/stm32wb/irq.h +++ b/arch/arm/include/stm32wb/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WB_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WB_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WB_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WB_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WB_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WB_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WB_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WB_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WB_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WB_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WB_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index 4efaba3559f..f61881f6a7c 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -51,146 +51,146 @@ * */ -#define STM32WB_IRQ_WWDG (STM32WB_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ -#define STM32WB_IRQ_PVD (STM32WB_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PVM1 (STM32WB_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ +# define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_PVM3 (STM32WB_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ +# define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ #endif -#define STM32WB_IRQ_TAMPER (STM32WB_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ -#define STM32WB_IRQ_TIMESTAMP (STM32WB_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ -#define STM32WB_IRQ_LSECSS (STM32WB_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ -#define STM32WB_IRQ_RTC_WKUP (STM32WB_IRQ_FIRST + 3) /* 3: RTC global interrupt */ -#define STM32WB_IRQ_FLASH (STM32WB_IRQ_FIRST + 4) /* 4: Flash global interrupt */ -#define STM32WB_IRQ_RCC (STM32WB_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WB_IRQ_EXTI0 (STM32WB_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ -#define STM32WB_IRQ_EXTI1 (STM32WB_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ -#define STM32WB_IRQ_EXTI2 (STM32WB_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ -#define STM32WB_IRQ_EXTI3 (STM32WB_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ -#define STM32WB_IRQ_EXTI4 (STM32WB_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ -#define STM32WB_IRQ_DMA1CH1 (STM32WB_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ -#define STM32WB_IRQ_DMA1CH2 (STM32WB_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ -#define STM32WB_IRQ_DMA1CH3 (STM32WB_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ -#define STM32WB_IRQ_DMA1CH4 (STM32WB_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ -#define STM32WB_IRQ_DMA1CH5 (STM32WB_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ -#define STM32WB_IRQ_DMA1CH6 (STM32WB_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ -#define STM32WB_IRQ_DMA1CH7 (STM32WB_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ -#define STM32WB_IRQ_ADC1 (STM32WB_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI[18] interrupts */ +#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Time stamp through EXTI[18] interrupts */ +#define STM32_IRQ_LSECSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS through EXTI[18] interrupts */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ +#define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) - #define STM32WB_IRQ_USB_HP (STM32WB_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ - #define STM32WB_IRQ_USB_LP (STM32WB_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ + #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ + #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif -#define STM32WB_IRQ_C2SEV (STM32WB_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_COMP (STM32WB_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ +# define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif -#define STM32WB_IRQ_EXTI95 (STM32WB_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ -#define STM32WB_IRQ_TIM1BRK (STM32WB_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ -#define STM32WB_IRQ_TIM1UP (STM32WB_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ -#define STM32WB_IRQ_TIM1TRGCOM (STM32WB_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Lines [9:5] Interrupt */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ +#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TIM16 (STM32WB_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ -# define STM32WB_IRQ_TIM17 (STM32WB_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ +# define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ +# define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif -#define STM32WB_IRQ_TIM1CC (STM32WB_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ -#define STM32WB_IRQ_TIM2 (STM32WB_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ -#define STM32WB_IRQ_PKA (STM32WB_IRQ_FIRST + 29) /* 29: PKA Interrupt */ -#define STM32WB_IRQ_I2C1EV (STM32WB_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WB_IRQ_I2C1ER (STM32WB_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 29) /* 29: PKA Interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_I2C3EV (STM32WB_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ -# define STM32WB_IRQ_I2C3ER (STM32WB_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ +# define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ +# define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif -#define STM32WB_IRQ_SPI1 (STM32WB_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SPI2 (STM32WB_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ +# define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif -#define STM32WB_IRQ_USART1 (STM32WB_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ || defined(CONFIG_STM32WB_STM32WB15) -# define STM32WB_IRQ_LPUART1 (STM32WB_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ +# define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_SAI1 (STM32WB_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ +# define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_TSC (STM32WB_IRQ_FIRST + 39) /* 39: TSC global interrupt */ +# define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif -#define STM32WB_IRQ_EXTI1510 (STM32WB_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ -#define STM32WB_IRQ_RTCALRM (STM32WB_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_CRS (STM32WB_IRQ_FIRST + 42) /* 42: CRS interrupt */ +# define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif -#define STM32WB_IRQ_PWRSOTF (STM32WB_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ -#define STM32WB_IRQ_PWRBLEACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ -#define STM32WB_IRQ_PWRRFPHASE (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ +#define STM32_IRQ_PWRSOTF (STM32_IRQ_FIRST + 43) /* 43: PWR switching on the fly interrupt */ +#define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ +#define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ #if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_PWR802ACT (STM32WB_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ +# define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif -#define STM32WB_IRQ_IPCCRX (STM32WB_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ -#define STM32WB_IRQ_IPCCTX (STM32WB_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ -#define STM32WB_IRQ_HSEM (STM32WB_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ -#define STM32WB_IRQ_LPTIM1 (STM32WB_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ -#define STM32WB_IRQ_LPTIM2 (STM32WB_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ +#define STM32_IRQ_IPCCRX (STM32_IRQ_FIRST + 44) /* 44: IPCC RX occupied interrupt */ +#define STM32_IRQ_IPCCTX (STM32_IRQ_FIRST + 45) /* 45: IPCC TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 46) /* 46: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ #if defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_LCD (STM32WB_IRQ_FIRST + 49) /* 49: LCD global interrupt */ +# define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_QUADSPI (STM32WB_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ -# define STM32WB_IRQ_AES1 (STM32WB_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ +# define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ +# define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif -#define STM32WB_IRQ_AES2 (STM32WB_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ -#define STM32WB_IRQ_RNG (STM32WB_IRQ_FIRST + 53) /* 53: RNG global interrupt */ -#define STM32WB_IRQ_FPU (STM32WB_IRQ_FIRST + 54) /* 54: FPU global interrupt */ +#define STM32_IRQ_AES2 (STM32_IRQ_FIRST + 52) /* 52: AES2 crypto global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ +#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ #if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) -# define STM32WB_IRQ_DMA2CH1 (STM32WB_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ -# define STM32WB_IRQ_DMA2CH2 (STM32WB_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ -# define STM32WB_IRQ_DMA2CH3 (STM32WB_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ -# define STM32WB_IRQ_DMA2CH4 (STM32WB_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ -# define STM32WB_IRQ_DMA2CH5 (STM32WB_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ -# define STM32WB_IRQ_DMA2CH6 (STM32WB_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ -# define STM32WB_IRQ_DMA2CH7 (STM32WB_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ +# define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ +# define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ +# define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ +# define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Channel 4 global interrupt */ +# define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Channel 5 global interrupt */ +# define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Channel 6 global interrupt */ +# define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 61) /* 61: DMA2 Channel 7 global interrupt */ #endif -#define STM32WB_IRQ_DMAMUX1 (STM32WB_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ +#define STM32_IRQ_DMAMUX1 (STM32_IRQ_FIRST + 62) /* 62: DMAMUX1 overrun interrupt */ -#define STM32WB_IRQ_NEXTINTS 63 +#define STM32_IRQ_NEXTINTS 63 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WB_IRQ_FIRST + STM32WB_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/chip.h b/arch/arm/src/stm32wb/chip.h index 1c263402e68..cddd9871d03 100644 --- a/arch/arm/src/stm32wb/chip.h +++ b/arch/arm/src/stm32wb/chip.h @@ -49,7 +49,7 @@ * arch/stm32wb/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WB_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WB */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h index fcac2dde6db..946f0fe73c7 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_crs.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_crs.h @@ -29,17 +29,17 @@ /* Register Offsets *********************************************************/ -#define STM32WB_CRS_CR_OFFSET 0x0000 /* CRS control register */ -#define STM32WB_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ -#define STM32WB_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ -#define STM32WB_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ +#define STM32_CRS_CR_OFFSET 0x0000 /* CRS control register */ +#define STM32_CRS_CFGR_OFFSET 0x0004 /* CRS configuration register */ +#define STM32_CRS_ISR_OFFSET 0x0008 /* CRS interrupt and status register */ +#define STM32_CRS_ICR_OFFSET 0x000c /* CRS interrupt flag clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_CRS_CR (STM32WB_CRS_BASE + STM32WB_CRS_CR_OFFSET) -#define STM32WB_CRS_CFGR (STM32WB_CRS_BASE + STM32WB_CRS_CFGR_OFFSET) -#define STM32WB_CRS_ISR (STM32WB_CRS_BASE + STM32WB_CRS_ISR_OFFSET) -#define STM32WB_CRS_ICR (STM32WB_CRS_BASE + STM32WB_CRS_ICR_OFFSET) +#define STM32_CRS_CR (STM32_CRS_BASE + STM32_CRS_CR_OFFSET) +#define STM32_CRS_CFGR (STM32_CRS_BASE + STM32_CRS_CFGR_OFFSET) +#define STM32_CRS_ISR (STM32_CRS_BASE + STM32_CRS_ISR_OFFSET) +#define STM32_CRS_ICR (STM32_CRS_BASE + STM32_CRS_ICR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h index dfd6e1050db..a87c1aaf3d1 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dma.h @@ -41,139 +41,139 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ -#define STM32WB_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ +#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */ +#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */ -#define STM32WB_DMACHAN_OFFSET(n) (0x0014 * (n)) -#define STM32WB_DMACHAN1_OFFSET 0x0000 -#define STM32WB_DMACHAN2_OFFSET 0x0014 -#define STM32WB_DMACHAN3_OFFSET 0x0028 -#define STM32WB_DMACHAN4_OFFSET 0x003c -#define STM32WB_DMACHAN5_OFFSET 0x0050 -#define STM32WB_DMACHAN6_OFFSET 0x0064 -#define STM32WB_DMACHAN7_OFFSET 0x0078 +#define STM32_DMACHAN_OFFSET(n) (0x0014 * (n)) +#define STM32_DMACHAN1_OFFSET 0x0000 +#define STM32_DMACHAN2_OFFSET 0x0014 +#define STM32_DMACHAN3_OFFSET 0x0028 +#define STM32_DMACHAN4_OFFSET 0x003c +#define STM32_DMACHAN5_OFFSET 0x0050 +#define STM32_DMACHAN6_OFFSET 0x0064 +#define STM32_DMACHAN7_OFFSET 0x0078 -#define STM32WB_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ -#define STM32WB_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ -#define STM32WB_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ -#define STM32WB_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ +#define STM32_DMACHAN_CCR_OFFSET 0x0008 /* DMA channel configuration register */ +#define STM32_DMACHAN_CNDTR_OFFSET 0x000c /* DMA channel number of data register */ +#define STM32_DMACHAN_CPAR_OFFSET 0x0010 /* DMA channel peripheral address register */ +#define STM32_DMACHAN_CMAR_OFFSET 0x0014 /* DMA channel memory address register */ -#define STM32WB_DMA_CCR_OFFSET(n) (STM32WB_DMACHAN_CCR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CNDTR_OFFSET(n) (STM32WB_DMACHAN_CNDTR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CPAR_OFFSET(n) (STM32WB_DMACHAN_CPAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CMAR_OFFSET(n) (STM32WB_DMACHAN_CMAR_OFFSET + STM32WB_DMACHAN_OFFSET(n)) +#define STM32_DMA_CCR_OFFSET(n) (STM32_DMACHAN_CCR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CNDTR_OFFSET(n) (STM32_DMACHAN_CNDTR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CPAR_OFFSET(n) (STM32_DMACHAN_CPAR_OFFSET + STM32_DMACHAN_OFFSET(n)) +#define STM32_DMA_CMAR_OFFSET(n) (STM32_DMACHAN_CMAR_OFFSET + STM32_DMACHAN_OFFSET(n)) -#define STM32WB_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ -#define STM32WB_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ -#define STM32WB_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ -#define STM32WB_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ -#define STM32WB_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ -#define STM32WB_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ -#define STM32WB_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ +#define STM32_DMA_CCR1_OFFSET 0x0008 /* DMA channel 1 configuration register */ +#define STM32_DMA_CCR2_OFFSET 0x001c /* DMA channel 2 configuration register */ +#define STM32_DMA_CCR3_OFFSET 0x0030 /* DMA channel 3 configuration register */ +#define STM32_DMA_CCR4_OFFSET 0x0044 /* DMA channel 4 configuration register */ +#define STM32_DMA_CCR5_OFFSET 0x0058 /* DMA channel 5 configuration register */ +#define STM32_DMA_CCR6_OFFSET 0x006c /* DMA channel 6 configuration register */ +#define STM32_DMA_CCR7_OFFSET 0x0080 /* DMA channel 7 configuration register */ -#define STM32WB_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ -#define STM32WB_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ -#define STM32WB_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ -#define STM32WB_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ -#define STM32WB_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ -#define STM32WB_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ -#define STM32WB_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ +#define STM32_DMA_CNDTR1_OFFSET 0x000c /* DMA channel 1 number of data register */ +#define STM32_DMA_CNDTR2_OFFSET 0x0020 /* DMA channel 2 number of data register */ +#define STM32_DMA_CNDTR3_OFFSET 0x0034 /* DMA channel 3 number of data register */ +#define STM32_DMA_CNDTR4_OFFSET 0x0048 /* DMA channel 4 number of data register */ +#define STM32_DMA_CNDTR5_OFFSET 0x005c /* DMA channel 5 number of data register */ +#define STM32_DMA_CNDTR6_OFFSET 0x0070 /* DMA channel 6 number of data register */ +#define STM32_DMA_CNDTR7_OFFSET 0x0084 /* DMA channel 7 number of data register */ -#define STM32WB_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ -#define STM32WB_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ -#define STM32WB_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ -#define STM32WB_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ -#define STM32WB_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ -#define STM32WB_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ -#define STM32WB_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ +#define STM32_DMA_CPAR1_OFFSET 0x0010 /* DMA channel 1 peripheral address register */ +#define STM32_DMA_CPAR2_OFFSET 0x0024 /* DMA channel 2 peripheral address register */ +#define STM32_DMA_CPAR3_OFFSET 0x0038 /* DMA channel 3 peripheral address register */ +#define STM32_DMA_CPAR4_OFFSET 0x004c /* DMA channel 4 peripheral address register */ +#define STM32_DMA_CPAR5_OFFSET 0x0060 /* DMA channel 5 peripheral address register */ +#define STM32_DMA_CPAR6_OFFSET 0x0074 /* DMA channel 6 peripheral address register */ +#define STM32_DMA_CPAR7_OFFSET 0x0088 /* DMA channel 7 peripheral address register */ -#define STM32WB_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ -#define STM32WB_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ -#define STM32WB_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ -#define STM32WB_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ -#define STM32WB_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ -#define STM32WB_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ -#define STM32WB_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ +#define STM32_DMA_CMAR1_OFFSET 0x0014 /* DMA channel 1 memory address register */ +#define STM32_DMA_CMAR2_OFFSET 0x0028 /* DMA channel 2 memory address register */ +#define STM32_DMA_CMAR3_OFFSET 0x003c /* DMA channel 3 memory address register */ +#define STM32_DMA_CMAR4_OFFSET 0x0050 /* DMA channel 4 memory address register */ +#define STM32_DMA_CMAR5_OFFSET 0x0064 /* DMA channel 5 memory address register */ +#define STM32_DMA_CMAR6_OFFSET 0x0078 /* DMA channel 6 memory address register */ +#define STM32_DMA_CMAR7_OFFSET 0x008c /* DMA channel 7 memory address register */ /* Register Addresses *******************************************************/ -#define STM32WB_DMA1_ISRC (STM32WB_DMA1_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA1_IFCR (STM32WB_DMA1_BASE + STM32WB_DMA_IFCR_OFFSET) +#define STM32_DMA1_ISRC (STM32_DMA1_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA1_IFCR (STM32_DMA1_BASE + STM32_DMA_IFCR_OFFSET) -#define STM32WB_DMA1_CCR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA1_CCR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA1_CCR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA1_CCR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA1_CCR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA1_CCR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA1_CCR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA1_CCR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CCR7_OFFSET) +#define STM32_DMA1_CCR(n) (STM32_DMA1_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA1_CCR1 (STM32_DMA1_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA1_CCR2 (STM32_DMA1_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA1_CCR3 (STM32_DMA1_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA1_CCR4 (STM32_DMA1_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA1_CCR5 (STM32_DMA1_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA1_CCR6 (STM32_DMA1_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA1_CCR7 (STM32_DMA1_BASE + STM32_DMA_CCR7_OFFSET) -#define STM32WB_DMA1_CNDTR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA1_CNDTR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA1_CNDTR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA1_CNDTR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA1_CNDTR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA1_CNDTR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA1_CNDTR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA1_CNDTR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CNDTR7_OFFSET) +#define STM32_DMA1_CNDTR(n) (STM32_DMA1_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA1_CNDTR1 (STM32_DMA1_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA1_CNDTR2 (STM32_DMA1_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA1_CNDTR3 (STM32_DMA1_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA1_CNDTR4 (STM32_DMA1_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE + STM32_DMA_CNDTR7_OFFSET) -#define STM32WB_DMA1_CPAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA1_CPAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA1_CPAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA1_CPAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA1_CPAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA1_CPAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA1_CPAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA1_CPAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CPAR7_OFFSET) +#define STM32_DMA1_CPAR(n) (STM32_DMA1_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA1_CPAR1 (STM32_DMA1_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA1_CPAR2 (STM32_DMA1_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA1_CPAR3 (STM32_DMA1_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA1_CPAR4 (STM32_DMA1_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA1_CPAR5 (STM32_DMA1_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA1_CPAR6 (STM32_DMA1_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA1_CPAR7 (STM32_DMA1_BASE + STM32_DMA_CPAR7_OFFSET) -#define STM32WB_DMA1_CMAR(n) (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA1_CMAR1 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA1_CMAR2 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA1_CMAR3 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA1_CMAR4 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA1_CMAR5 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA1_CMAR6 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA1_CMAR7 (STM32WB_DMA1_BASE + STM32WB_DMA_CMAR7_OFFSET) +#define STM32_DMA1_CMAR(n) (STM32_DMA1_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA1_CMAR1 (STM32_DMA1_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA1_CMAR2 (STM32_DMA1_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA1_CMAR3 (STM32_DMA1_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA1_CMAR4 (STM32_DMA1_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA1_CMAR5 (STM32_DMA1_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA1_CMAR6 (STM32_DMA1_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA1_CMAR7 (STM32_DMA1_BASE + STM32_DMA_CMAR7_OFFSET) -#define STM32WB_DMA2_ISRC (STM32WB_DMA2_BASE + STM32WB_DMA_ISR_OFFSET) -#define STM32WB_DMA2_IFCR (STM32WB_DMA2_BASE + STM32WB_DMA_IFCR_OFFSET) +#define STM32_DMA2_ISRC (STM32_DMA2_BASE + STM32_DMA_ISR_OFFSET) +#define STM32_DMA2_IFCR (STM32_DMA2_BASE + STM32_DMA_IFCR_OFFSET) -#define STM32WB_DMA2_CCR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CCR_OFFSET(n)) -#define STM32WB_DMA2_CCR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR1_OFFSET) -#define STM32WB_DMA2_CCR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR2_OFFSET) -#define STM32WB_DMA2_CCR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR3_OFFSET) -#define STM32WB_DMA2_CCR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR4_OFFSET) -#define STM32WB_DMA2_CCR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR5_OFFSET) -#define STM32WB_DMA2_CCR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR6_OFFSET) -#define STM32WB_DMA2_CCR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CCR7_OFFSET) +#define STM32_DMA2_CCR(n) (STM32_DMA2_BASE + STM32_DMA_CCR_OFFSET(n)) +#define STM32_DMA2_CCR1 (STM32_DMA2_BASE + STM32_DMA_CCR1_OFFSET) +#define STM32_DMA2_CCR2 (STM32_DMA2_BASE + STM32_DMA_CCR2_OFFSET) +#define STM32_DMA2_CCR3 (STM32_DMA2_BASE + STM32_DMA_CCR3_OFFSET) +#define STM32_DMA2_CCR4 (STM32_DMA2_BASE + STM32_DMA_CCR4_OFFSET) +#define STM32_DMA2_CCR5 (STM32_DMA2_BASE + STM32_DMA_CCR5_OFFSET) +#define STM32_DMA2_CCR6 (STM32_DMA2_BASE + STM32_DMA_CCR6_OFFSET) +#define STM32_DMA2_CCR7 (STM32_DMA2_BASE + STM32_DMA_CCR7_OFFSET) -#define STM32WB_DMA2_CNDTR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR_OFFSET(n)) -#define STM32WB_DMA2_CNDTR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR1_OFFSET) -#define STM32WB_DMA2_CNDTR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR2_OFFSET) -#define STM32WB_DMA2_CNDTR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR3_OFFSET) -#define STM32WB_DMA2_CNDTR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR4_OFFSET) -#define STM32WB_DMA2_CNDTR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR5_OFFSET) -#define STM32WB_DMA2_CNDTR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR6_OFFSET) -#define STM32WB_DMA2_CNDTR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CNDTR7_OFFSET) +#define STM32_DMA2_CNDTR(n) (STM32_DMA2_BASE + STM32_DMA_CNDTR_OFFSET(n)) +#define STM32_DMA2_CNDTR1 (STM32_DMA2_BASE + STM32_DMA_CNDTR1_OFFSET) +#define STM32_DMA2_CNDTR2 (STM32_DMA2_BASE + STM32_DMA_CNDTR2_OFFSET) +#define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE + STM32_DMA_CNDTR3_OFFSET) +#define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE + STM32_DMA_CNDTR4_OFFSET) +#define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE + STM32_DMA_CNDTR5_OFFSET) +#define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE + STM32_DMA_CNDTR6_OFFSET) +#define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE + STM32_DMA_CNDTR7_OFFSET) -#define STM32WB_DMA2_CPAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR_OFFSET(n)) -#define STM32WB_DMA2_CPAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR1_OFFSET) -#define STM32WB_DMA2_CPAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR2_OFFSET) -#define STM32WB_DMA2_CPAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR3_OFFSET) -#define STM32WB_DMA2_CPAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR4_OFFSET) -#define STM32WB_DMA2_CPAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR5_OFFSET) -#define STM32WB_DMA2_CPAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR6_OFFSET) -#define STM32WB_DMA2_CPAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CPAR7_OFFSET) +#define STM32_DMA2_CPAR(n) (STM32_DMA2_BASE + STM32_DMA_CPAR_OFFSET(n)) +#define STM32_DMA2_CPAR1 (STM32_DMA2_BASE + STM32_DMA_CPAR1_OFFSET) +#define STM32_DMA2_CPAR2 (STM32_DMA2_BASE + STM32_DMA_CPAR2_OFFSET) +#define STM32_DMA2_CPAR3 (STM32_DMA2_BASE + STM32_DMA_CPAR3_OFFSET) +#define STM32_DMA2_CPAR4 (STM32_DMA2_BASE + STM32_DMA_CPAR4_OFFSET) +#define STM32_DMA2_CPAR5 (STM32_DMA2_BASE + STM32_DMA_CPAR5_OFFSET) +#define STM32_DMA2_CPAR6 (STM32_DMA2_BASE + STM32_DMA_CPAR6_OFFSET) +#define STM32_DMA2_CPAR7 (STM32_DMA2_BASE + STM32_DMA_CPAR7_OFFSET) -#define STM32WB_DMA2_CMAR(n) (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR_OFFSET(n)) -#define STM32WB_DMA2_CMAR1 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR1_OFFSET) -#define STM32WB_DMA2_CMAR2 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR2_OFFSET) -#define STM32WB_DMA2_CMAR3 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR3_OFFSET) -#define STM32WB_DMA2_CMAR4 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR4_OFFSET) -#define STM32WB_DMA2_CMAR5 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR5_OFFSET) -#define STM32WB_DMA2_CMAR6 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR6_OFFSET) -#define STM32WB_DMA2_CMAR7 (STM32WB_DMA2_BASE + STM32WB_DMA_CMAR7_OFFSET) +#define STM32_DMA2_CMAR(n) (STM32_DMA2_BASE + STM32_DMA_CMAR_OFFSET(n)) +#define STM32_DMA2_CMAR1 (STM32_DMA2_BASE + STM32_DMA_CMAR1_OFFSET) +#define STM32_DMA2_CMAR2 (STM32_DMA2_BASE + STM32_DMA_CMAR2_OFFSET) +#define STM32_DMA2_CMAR3 (STM32_DMA2_BASE + STM32_DMA_CMAR3_OFFSET) +#define STM32_DMA2_CMAR4 (STM32_DMA2_BASE + STM32_DMA_CMAR4_OFFSET) +#define STM32_DMA2_CMAR5 (STM32_DMA2_BASE + STM32_DMA_CMAR5_OFFSET) +#define STM32_DMA2_CMAR6 (STM32_DMA2_BASE + STM32_DMA_CMAR6_OFFSET) +#define STM32_DMA2_CMAR7 (STM32_DMA2_BASE + STM32_DMA_CMAR7_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h index f4a8b5d47c9..929269f5a6d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_dmamux.h @@ -39,64 +39,65 @@ /* Register Offsets *********************************************************/ -#define STM32WB_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ -#define STM32WB_DMAMUX_C0CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(0) -#define STM32WB_DMAMUX_C1CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(1) -#define STM32WB_DMAMUX_C2CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(2) -#define STM32WB_DMAMUX_C3CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(3) -#define STM32WB_DMAMUX_C4CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(4) -#define STM32WB_DMAMUX_C5CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(5) -#define STM32WB_DMAMUX_C6CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(6) -#define STM32WB_DMAMUX_C7CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(7) -#define STM32WB_DMAMUX_C8CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(8) -#define STM32WB_DMAMUX_C9CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(9) -#define STM32WB_DMAMUX_C10CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(10) -#define STM32WB_DMAMUX_C11CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(11) -#define STM32WB_DMAMUX_C12CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(12) -#define STM32WB_DMAMUX_C13CR_OFFSET STM32WB_DMAMUX_CXCR_OFFSET(13) - /* 0x034-0x07C: Reserved */ -#define STM32WB_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ -#define STM32WB_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ - /* 0x088-0x0FC: Reserved */ +#define STM32_DMAMUX_CXCR_OFFSET(x) (0x0000 + 0x0004 * (x)) /* DMAMUX1 request line multiplexer channel x configuration register */ +#define STM32_DMAMUX_C0CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(0) +#define STM32_DMAMUX_C1CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(1) +#define STM32_DMAMUX_C2CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(2) +#define STM32_DMAMUX_C3CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(3) +#define STM32_DMAMUX_C4CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(4) +#define STM32_DMAMUX_C5CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(5) +#define STM32_DMAMUX_C6CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(6) +#define STM32_DMAMUX_C7CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(7) +#define STM32_DMAMUX_C8CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(8) +#define STM32_DMAMUX_C9CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(9) +#define STM32_DMAMUX_C10CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(10) +#define STM32_DMAMUX_C11CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(11) +#define STM32_DMAMUX_C12CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(12) +#define STM32_DMAMUX_C13CR_OFFSET STM32_DMAMUX_CXCR_OFFSET(13) +/* 0x034-0x07C: Reserved */ -#define STM32WB_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ -#define STM32WB_DMAMUX_RG0CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(0) -#define STM32WB_DMAMUX_RG1CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(1) -#define STM32WB_DMAMUX_RG2CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(2) -#define STM32WB_DMAMUX_RG3CR_OFFSET STM32WB_DMAMUX_RGXCR_OFFSET(3) -#define STM32WB_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ -#define STM32WB_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ - /* 0x148-0x3fc: Reserved */ +#define STM32_DMAMUX_CSR_OFFSET 0x0080 /* DMAMUX1 request line multiplexer interrupt channel status register */ +#define STM32_DMAMUX_CFR_OFFSET 0x0084 /* DMAMUX1 request line multiplexer interrupt clear flag register */ + /* 0x088-0x0FC: Reserved */ + +#define STM32_DMAMUX_RGXCR_OFFSET(x) (0x0100 + 0x004 * (x)) /* DMAMUX1 request generator channel x configuration register */ +#define STM32_DMAMUX_RG0CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(0) +#define STM32_DMAMUX_RG1CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(1) +#define STM32_DMAMUX_RG2CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(2) +#define STM32_DMAMUX_RG3CR_OFFSET STM32_DMAMUX_RGXCR_OFFSET(3) +#define STM32_DMAMUX_RGSR_OFFSET 0x0140 /* DMAMUX1 request generator interrupt status register */ +#define STM32_DMAMUX_RGCFR_OFFSET 0x0144 /* DMAMUX1 request generator interrupt clear flag register */ + /* 0x148-0x3fc: Reserved */ /* Register Addresses *******************************************************/ -#define STM32WB_DMAMUX1_CXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_C0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C0CR_OFFSET) -#define STM32WB_DMAMUX1_C1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C1CR_OFFSET) -#define STM32WB_DMAMUX1_C2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C2CR_OFFSET) -#define STM32WB_DMAMUX1_C3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C3CR_OFFSET) -#define STM32WB_DMAMUX1_C4CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C4CR_OFFSET) -#define STM32WB_DMAMUX1_C5CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C5CR_OFFSET) -#define STM32WB_DMAMUX1_C6CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C6CR_OFFSET) -#define STM32WB_DMAMUX1_C7CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C7CR_OFFSET) -#define STM32WB_DMAMUX1_C8CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C8CR_OFFSET) -#define STM32WB_DMAMUX1_C9CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C9CR_OFFSET) -#define STM32WB_DMAMUX1_C10CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C10CR_OFFSET) -#define STM32WB_DMAMUX1_C11CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C11CR_OFFSET) -#define STM32WB_DMAMUX1_C12CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C12CR_OFFSET) -#define STM32WB_DMAMUX1_C13CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_C13CR_OFFSET) +#define STM32_DMAMUX1_CXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_CXCR_OFFSET(x)) +#define STM32_DMAMUX1_C0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C0CR_OFFSET) +#define STM32_DMAMUX1_C1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C1CR_OFFSET) +#define STM32_DMAMUX1_C2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C2CR_OFFSET) +#define STM32_DMAMUX1_C3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C3CR_OFFSET) +#define STM32_DMAMUX1_C4CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C4CR_OFFSET) +#define STM32_DMAMUX1_C5CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C5CR_OFFSET) +#define STM32_DMAMUX1_C6CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C6CR_OFFSET) +#define STM32_DMAMUX1_C7CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C7CR_OFFSET) +#define STM32_DMAMUX1_C8CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C8CR_OFFSET) +#define STM32_DMAMUX1_C9CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C9CR_OFFSET) +#define STM32_DMAMUX1_C10CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C10CR_OFFSET) +#define STM32_DMAMUX1_C11CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C11CR_OFFSET) +#define STM32_DMAMUX1_C12CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C12CR_OFFSET) +#define STM32_DMAMUX1_C13CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_C13CR_OFFSET) -#define STM32WB_DMAMUX1_CSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CSR_OFFSET) -#define STM32WB_DMAMUX1_CFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_CFR_OFFSET) +#define STM32_DMAMUX1_CSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CSR_OFFSET) +#define STM32_DMAMUX1_CFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_CFR_OFFSET) -#define STM32WB_DMAMUX1_RGXCR(x) (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGXCR_OFFSET(x)) -#define STM32WB_DMAMUX1_RG0CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG0CR_OFFSET) -#define STM32WB_DMAMUX1_RG1CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG1CR_OFFSET) -#define STM32WB_DMAMUX1_RG2CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG2CR_OFFSET) -#define STM32WB_DMAMUX1_RG3CR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RG3CR_OFFSET) +#define STM32_DMAMUX1_RGXCR(x) (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGXCR_OFFSET(x)) +#define STM32_DMAMUX1_RG0CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG0CR_OFFSET) +#define STM32_DMAMUX1_RG1CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG1CR_OFFSET) +#define STM32_DMAMUX1_RG2CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG2CR_OFFSET) +#define STM32_DMAMUX1_RG3CR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RG3CR_OFFSET) -#define STM32WB_DMAMUX1_RGSR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGSR_OFFSET) -#define STM32WB_DMAMUX1_RGCFR (STM32WB_DMAMUX1_BASE + STM32WB_DMAMUX_RGCFR_OFFSET) +#define STM32_DMAMUX1_RGSR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGSR_OFFSET) +#define STM32_DMAMUX1_RGCFR (STM32_DMAMUX1_BASE + STM32_DMAMUX_RGCFR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h index 1169438501b..2c6bba71c1d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_exti.h @@ -36,41 +36,41 @@ /* Register Offsets *********************************************************/ -#define STM32WB_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ -#define STM32WB_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ -#define STM32WB_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ -#define STM32WB_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ -#define STM32WB_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ -#define STM32WB_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ -#define STM32WB_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ -#define STM32WB_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ -#define STM32WB_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ -#define STM32WB_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ -#define STM32WB_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ -#define STM32WB_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ -#define STM32WB_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection register 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection register 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event register 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending register 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection register 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection register 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event register 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending register 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* CPU1 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* CPU1 wakeup with event mask register 1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* CPU1 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* CPU1 wakeup with event mask register 2 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU2 wakeup with interrupt mask register 1 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU2 wakeup with event mask register 1 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU2 wakeup with interrupt mask register 2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU2 wakeup with event mask register 2 */ /* Register Addresses *******************************************************/ -#define STM32WB_EXTI_RTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR1_OFFSET) -#define STM32WB_EXTI_FTSR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR1_OFFSET) -#define STM32WB_EXTI_SWIER1 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER1_OFFSET) -#define STM32WB_EXTI_PR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR1_OFFSET) -#define STM32WB_EXTI_RTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_RTSR2_OFFSET) -#define STM32WB_EXTI_FTSR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_FTSR2_OFFSET) -#define STM32WB_EXTI_SWIER2 (STM32WB_EXTI_BASE + STM32WB_EXTI_SWIER2_OFFSET) -#define STM32WB_EXTI_PR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_PR2_OFFSET) -#define STM32WB_EXTI_C1IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR1_OFFSET) -#define STM32WB_EXTI_C1EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR1_OFFSET) -#define STM32WB_EXTI_C1IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1IMR2_OFFSET) -#define STM32WB_EXTI_C1EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C1EMR2_OFFSET) -#define STM32WB_EXTI_C2IMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR1_OFFSET) -#define STM32WB_EXTI_C2EMR1 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR1_OFFSET) -#define STM32WB_EXTI_C2IMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2IMR2_OFFSET) -#define STM32WB_EXTI_C2EMR2 (STM32WB_EXTI_BASE + STM32WB_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE + STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE + STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE + STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE + STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE + STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE + STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE + STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE + STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE + STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE + STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE + STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE + STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE + STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE + STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE + STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE + STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 8f2fe45b9dd..90991b1ee21 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -87,67 +87,67 @@ /* Define the valid configuration */ -#define STM32WB_FLASH_PAGESIZE 4096 +#define STM32_FLASH_PAGESIZE 4096 #if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ -# define STM32WB_FLASH_NPAGES 64 +# define STM32_FLASH_NPAGES 64 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ -# define STM32WB_FLASH_NPAGES 80 +# define STM32_FLASH_NPAGES 80 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ -# define STM32WB_FLASH_NPAGES 128 +# define STM32_FLASH_NPAGES 128 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ -# define STM32WB_FLASH_NPAGES 160 +# define STM32_FLASH_NPAGES 160 #elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ -# define STM32WB_FLASH_NPAGES 256 +# define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" #endif -#define STM32WB_FLASH_SIZE (STM32WB_FLASH_NPAGES * STM32WB_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WB_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ -#define STM32WB_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ -#define STM32WB_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ -#define STM32WB_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ -#define STM32WB_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ -#define STM32WB_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ -#define STM32WB_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ -#define STM32WB_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ -#define STM32WB_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ -#define STM32WB_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ -#define STM32WB_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ -#define STM32WB_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ -#define STM32WB_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ -#define STM32WB_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ -#define STM32WB_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ -#define STM32WB_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ -#define STM32WB_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ -#define STM32WB_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ -#define STM32WB_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ +#define STM32_FLASH_ACR_OFFSET 0x0000 /* Flash Access Control Register */ +#define STM32_FLASH_KEYR_OFFSET 0x0008 /* Flash Key Register */ +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c /* Flash Option Key Register */ +#define STM32_FLASH_SR_OFFSET 0x0010 /* Flash Status Register */ +#define STM32_FLASH_CR_OFFSET 0x0014 /* Flash Control Register */ +#define STM32_FLASH_ECCR_OFFSET 0x0018 /* Flash ECC Register */ +#define STM32_FLASH_OPTR_OFFSET 0x0020 /* Flash Option Register */ +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 /* Flash PCROP zone A Start address Register */ +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 /* Flash PCROP zone A End address Register */ +#define STM32_FLASH_WRP1AR_OFFSET 0x002c /* Flash WRP area A Address Register */ +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 /* Flash WRP area B Address Register */ +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 /* Flash PCROP zone B Start address Register */ +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 /* Flash PCROP zone B End address Register */ +#define STM32_FLASH_IPCCBR_OFFSET 0x003C /* Flash IPCC mailbox data buffer address Register */ +#define STM32_FLASH_C2ACR_OFFSET 0x005C /* CPU2 flash Access Control Register */ +#define STM32_FLASH_C2SR_OFFSET 0x0060 /* CPU2 flash Status Register */ +#define STM32_FLASH_C2CR_OFFSET 0x0064 /* CPU2 flash Control Register */ +#define STM32_FLASH_SFR_OFFSET 0x0080 /* Secure Flash start address Register */ +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* SRAM2 start address and CPU2 Reset Vector Register */ /* Register Addresses *******************************************************/ -#define STM32WB_FLASH_ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ACR_OFFSET) -#define STM32WB_FLASH_KEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_KEYR_OFFSET) -#define STM32WB_FLASH_OPTKEYR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTKEYR_OFFSET) -#define STM32WB_FLASH_SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SR_OFFSET) -#define STM32WB_FLASH_CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_CR_OFFSET) -#define STM32WB_FLASH_ECCR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_ECCR_OFFSET) -#define STM32WB_FLASH_OPTR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_OPTR_OFFSET) -#define STM32WB_FLASH_PCROP1ASR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1ASR_OFFSET) -#define STM32WB_FLASH_PCROP1AER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1AER_OFFSET) -#define STM32WB_FLASH_WRP1AR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1AR_OFFSET) -#define STM32WB_FLASH_WRP1BR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_WRP1BR_OFFSET) -#define STM32WB_FLASH_PCROP1BSR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BSR_OFFSET) -#define STM32WB_FLASH_PCROP1BER (STM32WB_FLASHREG_BASE + STM32WB_FLASH_PCROP1BER_OFFSET) -#define STM32WB_FLASH_IPCCBR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_IPCCBR_OFFSET) -#define STM32WB_FLASH_C2ACR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2ACR_OFFSET) -#define STM32WB_FLASH_C2SR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2SR_OFFSET) -#define STM32WB_FLASH_C2CR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_C2CR_OFFSET) -#define STM32WB_FLASH_SFR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SFR_OFFSET) -#define STM32WB_FLASH_SRRVR (STM32WB_FLASHREG_BASE + STM32WB_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHREG_BASE + STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHREG_BASE + STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHREG_BASE + STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHREG_BASE + STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHREG_BASE + STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHREG_BASE + STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHREG_BASE + STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHREG_BASE + STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHREG_BASE + STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHREG_BASE + STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHREG_BASE + STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHREG_BASE + STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHREG_BASE + STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHREG_BASE + STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHREG_BASE + STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index cc3b8621687..390dc47c2e0 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WB_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WB_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WB_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WB_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WB_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WB_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WB_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WB_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WB_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WB_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WB_GPIOA_MODER (STM32WB_GPIOA_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOA_OTYPER (STM32WB_GPIOA_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOA_OSPEED (STM32WB_GPIOA_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOA_PUPDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOA_IDR (STM32WB_GPIOA_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOA_ODR (STM32WB_GPIOA_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOA_BSRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOA_LCKR (STM32WB_GPIOA_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOA_AFRL (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOA_AFRH (STM32WB_GPIOA_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOA_BRR (STM32WB_GPIOA_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE + STM32_GPIO_BRR_OFFSET) -#define STM32WB_GPIOB_MODER (STM32WB_GPIOB_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOB_OTYPER (STM32WB_GPIOB_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOB_OSPEED (STM32WB_GPIOB_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOB_PUPDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOB_IDR (STM32WB_GPIOB_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOB_ODR (STM32WB_GPIOB_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOB_BSRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOB_LCKR (STM32WB_GPIOB_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOB_AFRL (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOB_AFRH (STM32WB_GPIOB_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOB_BRR (STM32WB_GPIOB_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE + STM32_GPIO_BRR_OFFSET) -#define STM32WB_GPIOC_MODER (STM32WB_GPIOC_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOC_OTYPER (STM32WB_GPIOC_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOC_OSPEED (STM32WB_GPIOC_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOC_PUPDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOC_IDR (STM32WB_GPIOC_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOC_ODR (STM32WB_GPIOC_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOC_BSRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOC_LCKR (STM32WB_GPIOC_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOC_AFRL (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOC_AFRH (STM32WB_GPIOC_BASE + STM32WB_GPIO_AFRH_OFFSET) -#define STM32WB_GPIOC_BRR (STM32WB_GPIOC_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) -# define STM32WB_GPIOD_MODER (STM32WB_GPIOD_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOD_OTYPER (STM32WB_GPIOD_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOD_OSPEED (STM32WB_GPIOD_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOD_PUPDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOD_IDR (STM32WB_GPIOD_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOD_ODR (STM32WB_GPIOD_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOD_BSRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOD_LCKR (STM32WB_GPIOD_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOD_AFRL (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOD_AFRH (STM32WB_GPIOD_BASE + STM32WB_GPIO_AFRH_OFFSET) -# define STM32WB_GPIOD_BRR (STM32WB_GPIOD_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOD_PUPDR (STM32_GPIOD_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOD_IDR (STM32_GPIOD_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOD_ODR (STM32_GPIOD_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOD_AFRL (STM32_GPIOD_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOD_AFRH (STM32_GPIOD_BASE + STM32_GPIO_AFRH_OFFSET) +# define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_GPIOE_MODER (STM32WB_GPIOE_BASE + STM32WB_GPIO_MODER_OFFSET) -# define STM32WB_GPIOE_OTYPER (STM32WB_GPIOE_BASE + STM32WB_GPIO_OTYPER_OFFSET) -# define STM32WB_GPIOE_OSPEED (STM32WB_GPIOE_BASE + STM32WB_GPIO_OSPEED_OFFSET) -# define STM32WB_GPIOE_PUPDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_PUPDR_OFFSET) -# define STM32WB_GPIOE_IDR (STM32WB_GPIOE_BASE + STM32WB_GPIO_IDR_OFFSET) -# define STM32WB_GPIOE_ODR (STM32WB_GPIOE_BASE + STM32WB_GPIO_ODR_OFFSET) -# define STM32WB_GPIOE_BSRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BSRR_OFFSET) -# define STM32WB_GPIOE_LCKR (STM32WB_GPIOE_BASE + STM32WB_GPIO_LCKR_OFFSET) -# define STM32WB_GPIOE_AFRL (STM32WB_GPIOE_BASE + STM32WB_GPIO_AFRL_OFFSET) -# define STM32WB_GPIOE_BRR (STM32WB_GPIOE_BASE + STM32WB_GPIO_BRR_OFFSET) +# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) +# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) +# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) +# define STM32_GPIOE_PUPDR (STM32_GPIOE_BASE + STM32_GPIO_PUPDR_OFFSET) +# define STM32_GPIOE_IDR (STM32_GPIOE_BASE + STM32_GPIO_IDR_OFFSET) +# define STM32_GPIOE_ODR (STM32_GPIOE_BASE + STM32_GPIO_ODR_OFFSET) +# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE + STM32_GPIO_BSRR_OFFSET) +# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE + STM32_GPIO_LCKR_OFFSET) +# define STM32_GPIOE_AFRL (STM32_GPIOE_BASE + STM32_GPIO_AFRL_OFFSET) +# define STM32_GPIOE_BRR (STM32_GPIOE_BASE + STM32_GPIO_BRR_OFFSET) #endif -#define STM32WB_GPIOH_MODER (STM32WB_GPIOH_BASE + STM32WB_GPIO_MODER_OFFSET) -#define STM32WB_GPIOH_OTYPER (STM32WB_GPIOH_BASE + STM32WB_GPIO_OTYPER_OFFSET) -#define STM32WB_GPIOH_OSPEED (STM32WB_GPIOH_BASE + STM32WB_GPIO_OSPEED_OFFSET) -#define STM32WB_GPIOH_PUPDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_PUPDR_OFFSET) -#define STM32WB_GPIOH_IDR (STM32WB_GPIOH_BASE + STM32WB_GPIO_IDR_OFFSET) -#define STM32WB_GPIOH_ODR (STM32WB_GPIOH_BASE + STM32WB_GPIO_ODR_OFFSET) -#define STM32WB_GPIOH_BSRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BSRR_OFFSET) -#define STM32WB_GPIOH_LCKR (STM32WB_GPIOH_BASE + STM32WB_GPIO_LCKR_OFFSET) -#define STM32WB_GPIOH_AFRL (STM32WB_GPIOH_BASE + STM32WB_GPIO_AFRL_OFFSET) -#define STM32WB_GPIOH_BRR (STM32WB_GPIOH_BASE + STM32WB_GPIO_BRR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE + STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE + STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE + STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE + STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE + STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE + STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE + STM32_GPIO_BRR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index 0e86bb64675..d5e25cae2f5 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -29,44 +29,44 @@ /* Register Offsets *********************************************************/ -#define STM32WB_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ -#define STM32WB_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ -#define STM32WB_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ -#define STM32WB_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ -#define STM32WB_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ -#define STM32WB_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ -#define STM32WB_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ -#define STM32WB_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ -#define STM32WB_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ -#define STM32WB_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ -#define STM32WB_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ +#define STM32_I2C_CR1_OFFSET 0x0000 /* Control register 1 (32-bit) */ +#define STM32_I2C_CR2_OFFSET 0x0004 /* Control register 2 (32-bit) */ +#define STM32_I2C_OAR1_OFFSET 0x0008 /* Own address register 1 (16-bit) */ +#define STM32_I2C_OAR2_OFFSET 0x000c /* Own address register 2 (16-bit) */ +#define STM32_I2C_TIMINGR_OFFSET 0x0010 /* Timing register */ +#define STM32_I2C_TIMEOUTR_OFFSET 0x0014 /* Timeout register */ +#define STM32_I2C_ISR_OFFSET 0x0018 /* Interrupt and Status register */ +#define STM32_I2C_ICR_OFFSET 0x001c /* Interrupt clear register */ +#define STM32_I2C_PECR_OFFSET 0x0020 /* Packet error checking register */ +#define STM32_I2C_RXDR_OFFSET 0x0024 /* Receive data register */ +#define STM32_I2C_TXDR_OFFSET 0x0028 /* Transmit data register */ /* Register Addresses *******************************************************/ -#define STM32WB_I2C1_CR1 (STM32WB_I2C1_BASE + STM32WB_I2C_CR1_OFFSET) -#define STM32WB_I2C1_CR2 (STM32WB_I2C1_BASE + STM32WB_I2C_CR2_OFFSET) -#define STM32WB_I2C1_OAR1 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR1_OFFSET) -#define STM32WB_I2C1_OAR2 (STM32WB_I2C1_BASE + STM32WB_I2C_OAR2_OFFSET) -#define STM32WB_I2C1_TIMINGR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMINGR_OFFSET) -#define STM32WB_I2C1_TIMEOUTR (STM32WB_I2C1_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -#define STM32WB_I2C1_ISR (STM32WB_I2C1_BASE + STM32WB_I2C_ISR_OFFSET) -#define STM32WB_I2C1_ICR (STM32WB_I2C1_BASE + STM32WB_I2C_ICR_OFFSET) -#define STM32WB_I2C1_PECR (STM32WB_I2C1_BASE + STM32WB_I2C_PECR_OFFSET) -#define STM32WB_I2C1_RXDR (STM32WB_I2C1_BASE + STM32WB_I2C_RXDR_OFFSET) -#define STM32WB_I2C1_TXDR (STM32WB_I2C1_BASE + STM32WB_I2C_TXDR_OFFSET) +#define STM32_I2C1_CR1 (STM32_I2C1_BASE + STM32_I2C_CR1_OFFSET) +#define STM32_I2C1_CR2 (STM32_I2C1_BASE + STM32_I2C_CR2_OFFSET) +#define STM32_I2C1_OAR1 (STM32_I2C1_BASE + STM32_I2C_OAR1_OFFSET) +#define STM32_I2C1_OAR2 (STM32_I2C1_BASE + STM32_I2C_OAR2_OFFSET) +#define STM32_I2C1_TIMINGR (STM32_I2C1_BASE + STM32_I2C_TIMINGR_OFFSET) +#define STM32_I2C1_TIMEOUTR (STM32_I2C1_BASE + STM32_I2C_TIMEOUTR_OFFSET) +#define STM32_I2C1_ISR (STM32_I2C1_BASE + STM32_I2C_ISR_OFFSET) +#define STM32_I2C1_ICR (STM32_I2C1_BASE + STM32_I2C_ICR_OFFSET) +#define STM32_I2C1_PECR (STM32_I2C1_BASE + STM32_I2C_PECR_OFFSET) +#define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) +#define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) #ifdef CONFIG_STM32WB_HAVE_I2C3 -# define STM32WB_I2C3_CR1 (STM32WB_I2C3_BASE + STM32WB_I2C_CR1_OFFSET) -# define STM32WB_I2C3_CR2 (STM32WB_I2C3_BASE + STM32WB_I2C_CR2_OFFSET) -# define STM32WB_I2C3_OAR1 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR1_OFFSET) -# define STM32WB_I2C3_OAR2 (STM32WB_I2C3_BASE + STM32WB_I2C_OAR2_OFFSET) -# define STM32WB_I2C3_TIMINGR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMINGR_OFFSET) -# define STM32WB_I2C3_TIMEOUTR (STM32WB_I2C3_BASE + STM32WB_I2C_TIMEOUTR_OFFSET) -# define STM32WB_I2C3_ISR (STM32WB_I2C3_BASE + STM32WB_I2C_ISR_OFFSET) -# define STM32WB_I2C3_ICR (STM32WB_I2C3_BASE + STM32WB_I2C_ICR_OFFSET) -# define STM32WB_I2C3_PECR (STM32WB_I2C3_BASE + STM32WB_I2C_PECR_OFFSET) -# define STM32WB_I2C3_RXDR (STM32WB_I2C3_BASE + STM32WB_I2C_RXDR_OFFSET) -# define STM32WB_I2C3_TXDR (STM32WB_I2C3_BASE + STM32WB_I2C_TXDR_OFFSET) +# define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) +# define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) +# define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) +# define STM32_I2C3_OAR2 (STM32_I2C3_BASE + STM32_I2C_OAR2_OFFSET) +# define STM32_I2C3_TIMINGR (STM32_I2C3_BASE + STM32_I2C_TIMINGR_OFFSET) +# define STM32_I2C3_TIMEOUTR (STM32_I2C3_BASE + STM32_I2C_TIMEOUTR_OFFSET) +# define STM32_I2C3_ISR (STM32_I2C3_BASE + STM32_I2C_ISR_OFFSET) +# define STM32_I2C3_ICR (STM32_I2C3_BASE + STM32_I2C_ICR_OFFSET) +# define STM32_I2C3_PECR (STM32_I2C3_BASE + STM32_I2C_PECR_OFFSET) +# define STM32_I2C3_RXDR (STM32_I2C3_BASE + STM32_I2C_RXDR_OFFSET) +# define STM32_I2C3_TXDR (STM32_I2C3_BASE + STM32_I2C_TXDR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h index 6e1d597ff1c..8e42686f310 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_ipcc.h @@ -29,25 +29,25 @@ /* Register Offsets *********************************************************/ -#define STM32WB_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ -#define STM32WB_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ -#define STM32WB_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ -#define STM32WB_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ -#define STM32WB_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ -#define STM32WB_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ -#define STM32WB_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ -#define STM32WB_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ +#define STM32_IPCC_C1CR_OFFSET 0x0000 /* CPU1 control register */ +#define STM32_IPCC_C1MR_OFFSET 0x0004 /* CPU1 mask register */ +#define STM32_IPCC_C1SCR_OFFSET 0x0008 /* CPU1 status set/clear register */ +#define STM32_IPCC_C1TOC2SR_OFFSET 0x000c /* CPU1 to CPU2 status register */ +#define STM32_IPCC_C2CR_OFFSET 0x0010 /* CPU2 control register */ +#define STM32_IPCC_C2MR_OFFSET 0x0014 /* CPU2 mask register */ +#define STM32_IPCC_C2SCR_OFFSET 0x0018 /* CPU2 status set/clear register */ +#define STM32_IPCC_C2TOC1SR_OFFSET 0x001c /* CPU2 to CPU1 status register */ /* Register Addresses *******************************************************/ -#define STM32WB_IPCC_C1CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1CR_OFFSET) -#define STM32WB_IPCC_C1MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1MR_OFFSET) -#define STM32WB_IPCC_C1SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1SCR_OFFSET) -#define STM32WB_IPCC_C1TOC2SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C1TOC2SR_OFFSET) -#define STM32WB_IPCC_C2CR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2CR_OFFSET) -#define STM32WB_IPCC_C2MR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2MR_OFFSET) -#define STM32WB_IPCC_C2SCR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2SCR_OFFSET) -#define STM32WB_IPCC_C2TOC1SR (STM32WB_IPCC_BASE + STM32WB_IPCC_C2TOC1SR_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE + STM32_IPCC_C1CR_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE + STM32_IPCC_C1MR_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE + STM32_IPCC_C1SCR_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE + STM32_IPCC_C1TOC2SR_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE + STM32_IPCC_C2CR_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE + STM32_IPCC_C2MR_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE + STM32_IPCC_C2SCR_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE + STM32_IPCC_C2TOC1SR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h index 58d3d249b66..474f7a90510 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_memorymap.h @@ -29,33 +29,33 @@ /* STM32WBXXX Address Blocks ************************************************/ -#define STM32WB_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32WB_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ -#define STM32WB_PERIPH_BASE 0x40000000 /* Peripheral base address */ -#define STM32WB_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x2003ffff: 256k RAM block */ +#define STM32_PERIPH_BASE 0x40000000 /* Peripheral base address */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ /* Code Base Addresses ******************************************************/ -#define STM32WB_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ -#define STM32WB_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ -#define STM32WB_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ -#define STM32WB_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ -#define STM32WB_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ -#define STM32WB_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ +#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ +#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ +#define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192к RAM1 block */ +#define STM32_SRAM2A_BASE 0x20030000 /* 0x20030000-0x20037fff: 32k RAM2a block */ +#define STM32_SRAM2B_BASE 0x20038000 /* 0x20038000-0x2003ffff: 32k RAM2b block */ -#define STM32WB_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ -#define STM32WB_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ -#define STM32WB_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x20006fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ +#define STM32_OPTION_BASE 0x1fff8000 /* 0x1fff8000-0x1fff8fff: Option bytes */ /* System Memory Addresses **************************************************/ -#define STM32WB_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WB_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75e0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. */ -#define STM32WB_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. 5 LSB corresponds to: * 0x11: WLCSP100 / UFBGA129 * 0x13: VFQFPN68 @@ -64,96 +64,96 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WB_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000-0x227fffff: SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WB_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ - /* 0x40009800-0x4000ffff: Reserved */ -#define STM32WB_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ - /* 0x40015800-0x4001ffff: Reserved */ -#define STM32WB_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ - /* 0x40024400-0x47ffffff: Reserved */ -#define STM32WB_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ - /* 0x50060400-0x57ffffff: Reserved */ -#define STM32WB_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ - /* 0x58004400-0x5fffffff: Reserved */ -#define STM32WB_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ - /* 0x60002000-0x8fffffff: Reserved */ -#define STM32WB_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ +#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x400097ff: APB1 */ + /* 0x40009800-0x4000ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x400157ff: APB2 */ + /* 0x40015800-0x4001ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: AHB1 */ + /* 0x40024400-0x47ffffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x500603ff: AHB2 */ + /* 0x50060400-0x57ffffff: Reserved */ +#define STM32_AHB4_BASE 0x58000000 /* 0x58000000-0x580043ff: AHB4 */ + /* 0x58004400-0x5fffffff: Reserved */ +#define STM32_APB3_BASE 0x60000000 /* 0x60000000-0x60001fff: APB3 */ + /* 0x60002000-0x8fffffff: Reserved */ +#define STM32_AHB3_BASE 0x90000000 /* 0x90000000-0xA00013ff: AHB3 */ /* APB1 Base Addresses ******************************************************/ -#define STM32WB_TIM2_BASE 0x40000000 -#define STM32WB_LCD_BASE 0x40002400 -#define STM32WB_RTC_BASE 0x40002800 -#define STM32WB_WWDG_BASE 0x40002c00 -#define STM32WB_IWDG_BASE 0x40003000 -#define STM32WB_SPI2_BASE 0x40003800 -#define STM32WB_I2C1_BASE 0x40005400 -#define STM32WB_I2C3_BASE 0x40005c00 -#define STM32WB_CRS_BASE 0x40006000 -#define STM32WB_USB1_BASE 0x40006800 -#define STM32WB_USB1_PMAADDR 0x40006c00 -#define STM32WB_LPTIM1_BASE 0x40007c00 -#define STM32WB_LPUART1_BASE 0x40008000 -#define STM32WB_LPTIM2_BASE 0x40009400 +#define STM32_TIM2_BASE 0x40000000 +#define STM32_LCD_BASE 0x40002400 +#define STM32_RTC_BASE 0x40002800 +#define STM32_WWDG_BASE 0x40002c00 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_SPI2_BASE 0x40003800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_I2C3_BASE 0x40005c00 +#define STM32_CRS_BASE 0x40006000 +#define STM32_USB1_BASE 0x40006800 +#define STM32_USB1_PMAADDR 0x40006c00 +#define STM32_LPTIM1_BASE 0x40007c00 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM2_BASE 0x40009400 /* APB2 Base Addresses ******************************************************/ -#define STM32WB_SYSCFG_BASE 0x40010000 -#define STM32WB_VREFBUF_BASE 0x40010030 -#define STM32WB_COMP1_BASE 0x40010200 -#define STM32WB_COMP2_BASE 0x40010204 -#define STM32WB_TIM1_BASE 0x40012c00 -#define STM32WB_SPI1_BASE 0x40013000 -#define STM32WB_USART1_BASE 0x40013800 -#define STM32WB_TIM16_BASE 0x40014400 -#define STM32WB_TIM17_BASE 0x40014800 -#define STM32WB_SAI1_BASE 0x40015400 +#define STM32_SYSCFG_BASE 0x40010000 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_COMP1_BASE 0x40010200 +#define STM32_COMP2_BASE 0x40010204 +#define STM32_TIM1_BASE 0x40012c00 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_USART1_BASE 0x40013800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_SAI1_BASE 0x40015400 /* AHB1 Base Addresses ******************************************************/ -#define STM32WB_DMA1_BASE 0x40020000 -#define STM32WB_DMA2_BASE 0x40020400 -#define STM32WB_DMAMUX1_BASE 0x40020800 -#define STM32WB_CRC_BASE 0x40023000 -#define STM32WB_TSC_BASE 0x40024000 +#define STM32_DMA1_BASE 0x40020000 +#define STM32_DMA2_BASE 0x40020400 +#define STM32_DMAMUX1_BASE 0x40020800 +#define STM32_CRC_BASE 0x40023000 +#define STM32_TSC_BASE 0x40024000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WB_GPIOA_BASE 0x48000000 -#define STM32WB_GPIOB_BASE 0x48000400 -#define STM32WB_GPIOC_BASE 0x48000800 -#define STM32WB_GPIOD_BASE 0x48000c00 -#define STM32WB_GPIOE_BASE 0x48001000 -#define STM32WB_GPIOH_BASE 0x48001c00 -#define STM32WB_ADC1_BASE 0x50040000 -#define STM32WB_AES1_BASE 0x50060000 +#define STM32_GPIOA_BASE 0x48000000 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOD_BASE 0x48000c00 +#define STM32_GPIOE_BASE 0x48001000 +#define STM32_GPIOH_BASE 0x48001c00 +#define STM32_ADC1_BASE 0x50040000 +#define STM32_AES1_BASE 0x50060000 /* AHB4 Base Addresses ******************************************************/ -#define STM32WB_RCC_BASE 0x58000000 -#define STM32WB_PWR_BASE 0x58000400 -#define STM32WB_EXTI_BASE 0x58000800 -#define STM32WB_IPCC_BASE 0x58000c00 -#define STM32WB_RNG_BASE 0x58001000 -#define STM32WB_HSEM_BASE 0x58001400 -#define STM32WB_AES2_BASE 0x58001800 -#define STM32WB_PKA_BASE 0x58002000 -#define STM32WB_FLASHREG_BASE 0x58004000 +#define STM32_RCC_BASE 0x58000000 +#define STM32_PWR_BASE 0x58000400 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_IPCC_BASE 0x58000c00 +#define STM32_RNG_BASE 0x58001000 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_AES2_BASE 0x58001800 +#define STM32_PKA_BASE 0x58002000 +#define STM32_FLASHREG_BASE 0x58004000 /* APB3 Base Addresses ******************************************************/ -#define STM32WB_BLE_BASE 0x60000000 -#define STM32WB_RADIO_BASE 0x60000400 -#define STM32WB_802154_BASE 0x60001000 +#define STM32_BLE_BASE 0x60000000 +#define STM32_RADIO_BASE 0x60000400 +#define STM32_802154_BASE 0x60001000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WB_QSPI_BASE 0x90000000 -#define STM32WB_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ -#define STM32WB_QSPIREF_BASE 0xa0001000 +#define STM32_QSPI_BASE 0x90000000 +#define STM32_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QSPI memory mapping */ +#define STM32_QSPIREF_BASE 0xa0001000 /* Cortex-M4 Base Addresses *************************************************/ @@ -161,7 +161,7 @@ * this address range */ -#define STM32WB_SCS_BASE 0xe000e000 -#define STM32WB_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WB_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h index 8e161735c05..6fb75537322 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pwr.h @@ -36,54 +36,54 @@ /* Register Offsets *********************************************************/ -#define STM32WB_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WB_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WB_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WB_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WB_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WB_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WB_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WB_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WB_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WB_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WB_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WB_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WB_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WB_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WB_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ -#define STM32WB_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ -#define STM32WB_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ -#define STM32WB_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WB_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WB_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ -#define STM32WB_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ -#define STM32WB_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRD_OFFSET 0x0038 /* Power Port D pull-up control register */ +#define STM32_PWR_PDCRD_OFFSET 0x003C /* Power Port D pull-down control register */ +#define STM32_PWR_PUCRE_OFFSET 0x0040 /* Power Port E pull-up control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* CPU2 control register 1 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* CPU2 control register 3 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Extended status and status clear register */ /* Register Addresses *******************************************************/ -#define STM32WB_PWR_CR1 (STM32WB_PWR_BASE + STM32WB_PWR_CR1_OFFSET) -#define STM32WB_PWR_CR2 (STM32WB_PWR_BASE + STM32WB_PWR_CR2_OFFSET) -#define STM32WB_PWR_CR3 (STM32WB_PWR_BASE + STM32WB_PWR_CR3_OFFSET) -#define STM32WB_PWR_CR4 (STM32WB_PWR_BASE + STM32WB_PWR_CR4_OFFSET) -#define STM32WB_PWR_SR1 (STM32WB_PWR_BASE + STM32WB_PWR_SR1_OFFSET) -#define STM32WB_PWR_SR2 (STM32WB_PWR_BASE + STM32WB_PWR_SR2_OFFSET) -#define STM32WB_PWR_SCR (STM32WB_PWR_BASE + STM32WB_PWR_SCR_OFFSET) -#define STM32WB_PWR_CR5 (STM32WB_PWR_BASE + STM32WB_PWR_CR5_OFFSET) -#define STM32WB_PWR_PUCRA (STM32WB_PWR_BASE + STM32WB_PWR_PUCRA_OFFSET) -#define STM32WB_PWR_PDCRA (STM32WB_PWR_BASE + STM32WB_PWR_PDCRA_OFFSET) -#define STM32WB_PWR_PUCRB (STM32WB_PWR_BASE + STM32WB_PWR_PUCRB_OFFSET) -#define STM32WB_PWR_PDCRB (STM32WB_PWR_BASE + STM32WB_PWR_PDCRB_OFFSET) -#define STM32WB_PWR_PUCRC (STM32WB_PWR_BASE + STM32WB_PWR_PUCRC_OFFSET) -#define STM32WB_PWR_PDCRC (STM32WB_PWR_BASE + STM32WB_PWR_PDCRC_OFFSET) -#define STM32WB_PWR_PUCRD (STM32WB_PWR_BASE + STM32WB_PWR_PUCRD_OFFSET) -#define STM32WB_PWR_PDCRD (STM32WB_PWR_BASE + STM32WB_PWR_PDCRD_OFFSET) -#define STM32WB_PWR_PUCRE (STM32WB_PWR_BASE + STM32WB_PWR_PUCRE_OFFSET) -#define STM32WB_PWR_PDCRE (STM32WB_PWR_BASE + STM32WB_PWR_PDCRE_OFFSET) -#define STM32WB_PWR_PUCRH (STM32WB_PWR_BASE + STM32WB_PWR_PUCRH_OFFSET) -#define STM32WB_PWR_PDCRH (STM32WB_PWR_BASE + STM32WB_PWR_PDCRH_OFFSET) -#define STM32WB_PWR_C2CR1 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR1_OFFSET) -#define STM32WB_PWR_C2CR3 (STM32WB_PWR_BASE + STM32WB_PWR_C2CR3_OFFSET) -#define STM32WB_PWR_EXTSCR (STM32WB_PWR_BASE + STM32WB_PWR_EXTSCR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE + STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE + STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE + STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE + STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE + STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE + STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE + STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE + STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE + STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE + STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE + STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE + STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE + STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE + STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRD (STM32_PWR_BASE + STM32_PWR_PUCRD_OFFSET) +#define STM32_PWR_PDCRD (STM32_PWR_BASE + STM32_PWR_PDCRD_OFFSET) +#define STM32_PWR_PUCRE (STM32_PWR_BASE + STM32_PWR_PUCRE_OFFSET) +#define STM32_PWR_PDCRE (STM32_PWR_BASE + STM32_PWR_PDCRE_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE + STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE + STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE + STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE + STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE + STM32_PWR_EXTSCR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h index 2f861e3fed2..568d362051d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rcc.h @@ -35,105 +35,105 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WB_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WB_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WB_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WB_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ -#define STM32WB_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WB_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WB_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WB_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ -#define STM32WB_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WB_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WB_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WB_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WB_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WB_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WB_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ -#define STM32WB_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ -#define STM32WB_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WB_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WB_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ -#define STM32WB_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ -#define STM32WB_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ -#define STM32WB_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WB_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WB_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WB_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WB_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ -#define STM32WB_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ -#define STM32WB_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ -#define STM32WB_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_PLLSAI1CFG_OFFSET 0x0010 /* PLLSAI1 configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_SMPSCR_OFFSET 0x0024 /* Step-down converter control register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_APB3RSTR_OFFSET 0x0044 /* APB3 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_CRRCR_OFFSET 0x0098 /* Clock recovery RC register */ +#define STM32_RCC_HSECR_OFFSET 0x009c /* Clock HSE register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 /* Extended clock recovery register */ +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 AHB1 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 AHB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 AHB3 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 APB1 clock enable in sleep and stop modes register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 APB1 clock enable in sleep and stop modes register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 APB2 clock enable in sleep and stop modes register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 APB3 clock enable in sleep and stop modes register */ /* Register Addresses *******************************************************/ -#define STM32WB_RCC_CR (STM32WB_RCC_BASE + STM32WB_RCC_CR_OFFSET) -#define STM32WB_RCC_ICSCR (STM32WB_RCC_BASE + STM32WB_RCC_ICSCR_OFFSET) -#define STM32WB_RCC_CFGR (STM32WB_RCC_BASE + STM32WB_RCC_CFGR_OFFSET) -#define STM32WB_RCC_PLLCFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLCFG_OFFSET) -#define STM32WB_RCC_PLLSAI1CFG (STM32WB_RCC_BASE + STM32WB_RCC_PLLSAI1CFG_OFFSET) -#define STM32WB_RCC_CIER (STM32WB_RCC_BASE + STM32WB_RCC_CIER_OFFSET) -#define STM32WB_RCC_CIFR (STM32WB_RCC_BASE + STM32WB_RCC_CIFR_OFFSET) -#define STM32WB_RCC_CICR (STM32WB_RCC_BASE + STM32WB_RCC_CICR_OFFSET) -#define STM32WB_RCC_SMPSCR (STM32WB_RCC_BASE + STM32WB_RCC_SMPSCR_OFFSET) -#define STM32WB_RCC_AHB1RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1RSTR_OFFSET) -#define STM32WB_RCC_AHB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2RSTR_OFFSET) -#define STM32WB_RCC_AHB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3RSTR_OFFSET) -#define STM32WB_RCC_APB1RSTR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR1_OFFSET) -#define STM32WB_RCC_APB1RSTR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1RSTR2_OFFSET) -#define STM32WB_RCC_APB2RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB2RSTR_OFFSET) -#define STM32WB_RCC_APB3RSTR (STM32WB_RCC_BASE + STM32WB_RCC_APB3RSTR_OFFSET) -#define STM32WB_RCC_AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1ENR_OFFSET) -#define STM32WB_RCC_AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2ENR_OFFSET) -#define STM32WB_RCC_AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3ENR_OFFSET) -#define STM32WB_RCC_APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR1_OFFSET) -#define STM32WB_RCC_APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1ENR2_OFFSET) -#define STM32WB_RCC_APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2ENR_OFFSET) -#define STM32WB_RCC_AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB1SMENR_OFFSET) -#define STM32WB_RCC_AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB2SMENR_OFFSET) -#define STM32WB_RCC_AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_AHB3SMENR_OFFSET) -#define STM32WB_RCC_APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR1_OFFSET) -#define STM32WB_RCC_APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_APB1SMENR2_OFFSET) -#define STM32WB_RCC_APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_APB2SMENR_OFFSET) -#define STM32WB_RCC_CCIPR (STM32WB_RCC_BASE + STM32WB_RCC_CCIPR_OFFSET) -#define STM32WB_RCC_BDCR (STM32WB_RCC_BASE + STM32WB_RCC_BDCR_OFFSET) -#define STM32WB_RCC_CSR (STM32WB_RCC_BASE + STM32WB_RCC_CSR_OFFSET) -#define STM32WB_RCC_CRRCR (STM32WB_RCC_BASE + STM32WB_RCC_CRRCR_OFFSET) -#define STM32WB_RCC_HSECR (STM32WB_RCC_BASE + STM32WB_RCC_HSECR_OFFSET) -#define STM32WB_RCC_EXTCFGR (STM32WB_RCC_BASE + STM32WB_RCC_EXTCFGR_OFFSET) -#define STM32WB_RCC_C2AHB1ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1ENR_OFFSET) -#define STM32WB_RCC_C2AHB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2ENR_OFFSET) -#define STM32WB_RCC_C2AHB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3ENR_OFFSET) -#define STM32WB_RCC_C2APB1ENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR1_OFFSET) -#define STM32WB_RCC_C2APB1ENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1ENR2_OFFSET) -#define STM32WB_RCC_C2APB2ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2ENR_OFFSET) -#define STM32WB_RCC_C2APB3ENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3ENR_OFFSET) -#define STM32WB_RCC_C2AHB1SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB1SMENR_OFFSET) -#define STM32WB_RCC_C2AHB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB2SMENR_OFFSET) -#define STM32WB_RCC_C2AHB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2AHB3SMENR_OFFSET) -#define STM32WB_RCC_C2APB1SMENR1 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR1_OFFSET) -#define STM32WB_RCC_C2APB1SMENR2 (STM32WB_RCC_BASE + STM32WB_RCC_C2APB1SMENR2_OFFSET) -#define STM32WB_RCC_C2APB2SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB2SMENR_OFFSET) -#define STM32WB_RCC_C2APB3SMENR (STM32WB_RCC_BASE + STM32WB_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_PLLSAI1CFG (STM32_RCC_BASE + STM32_RCC_PLLSAI1CFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_SMPSCR (STM32_RCC_BASE + STM32_RCC_SMPSCR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_APB3RSTR (STM32_RCC_BASE + STM32_RCC_APB3RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_CRRCR (STM32_RCC_BASE + STM32_RCC_CRRCR_OFFSET) +#define STM32_RCC_HSECR (STM32_RCC_BASE + STM32_RCC_HSECR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h index b02dfbcd959..6f8db9d0b9e 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_rtc.h @@ -29,93 +29,93 @@ /* Register Offsets *********************************************************/ -#define STM32WB_RTC_TR_OFFSET 0x0000 /* RTC time register */ -#define STM32WB_RTC_DR_OFFSET 0x0004 /* RTC date register */ -#define STM32WB_RTC_CR_OFFSET 0x0008 /* RTC control register */ -#define STM32WB_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ -#define STM32WB_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ -#define STM32WB_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ -#define STM32WB_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ -#define STM32WB_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ -#define STM32WB_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ -#define STM32WB_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ -#define STM32WB_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ -#define STM32WB_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ -#define STM32WB_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ -#define STM32WB_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ -#define STM32WB_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ -#define STM32WB_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ -#define STM32WB_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ -#define STM32WB_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ -#define STM32WB_RTC_OR_OFFSET 0x004c /* RTC option register */ +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ -#define STM32WB_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) -#define STM32WB_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ -#define STM32WB_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ -#define STM32WB_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ -#define STM32WB_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ -#define STM32WB_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ -#define STM32WB_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ -#define STM32WB_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ -#define STM32WB_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ -#define STM32WB_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ -#define STM32WB_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ -#define STM32WB_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ -#define STM32WB_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ -#define STM32WB_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ -#define STM32WB_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ -#define STM32WB_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ -#define STM32WB_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ -#define STM32WB_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ -#define STM32WB_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ -#define STM32WB_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ -#define STM32WB_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BKPR_OFFSET(n) (0x0050 + ((n) << 2)) +#define STM32_RTC_BKP0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BKP1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BKP2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BKP3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BKP4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BKP5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BKP6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BKP7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BKP8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BKP9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BKP10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BKP11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BKP12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BKP13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BKP14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BKP15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BKP16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BKP17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BKP18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BKP19R_OFFSET 0x009c /* RTC backup register 19 */ /* Register Addresses *******************************************************/ -#define STM32WB_RTC_TR (STM32WB_RTC_BASE + STM32WB_RTC_TR_OFFSET) -#define STM32WB_RTC_DR (STM32WB_RTC_BASE + STM32WB_RTC_DR_OFFSET) -#define STM32WB_RTC_CR (STM32WB_RTC_BASE + STM32WB_RTC_CR_OFFSET) -#define STM32WB_RTC_ISR (STM32WB_RTC_BASE + STM32WB_RTC_ISR_OFFSET) -#define STM32WB_RTC_PRER (STM32WB_RTC_BASE + STM32WB_RTC_PRER_OFFSET) -#define STM32WB_RTC_WUTR (STM32WB_RTC_BASE + STM32WB_RTC_WUTR_OFFSET) -#define STM32WB_RTC_ALRMAR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMAR_OFFSET) -#define STM32WB_RTC_ALRMBR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBR_OFFSET) -#define STM32WB_RTC_WPR (STM32WB_RTC_BASE + STM32WB_RTC_WPR_OFFSET) -#define STM32WB_RTC_SSR (STM32WB_RTC_BASE + STM32WB_RTC_SSR_OFFSET) -#define STM32WB_RTC_SHIFTR (STM32WB_RTC_BASE + STM32WB_RTC_SHIFTR_OFFSET) -#define STM32WB_RTC_TSTR (STM32WB_RTC_BASE + STM32WB_RTC_TSTR_OFFSET) -#define STM32WB_RTC_TSDR (STM32WB_RTC_BASE + STM32WB_RTC_TSDR_OFFSET) -#define STM32WB_RTC_TSSSR (STM32WB_RTC_BASE + STM32WB_RTC_TSSSR_OFFSET) -#define STM32WB_RTC_CALR (STM32WB_RTC_BASE + STM32WB_RTC_CALR_OFFSET) -#define STM32WB_RTC_TAMPCR (STM32WB_RTC_BASE + STM32WB_RTC_TAMPCR_OFFSET) -#define STM32WB_RTC_ALRMASSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMASSR_OFFSET) -#define STM32WB_RTC_ALRMBSSR (STM32WB_RTC_BASE + STM32WB_RTC_ALRMBSSR_OFFSET) -#define STM32WB_RTC_OR (STM32WB_RTC_BASE + STM32WB_RTC_OR_OFFSET) +#define STM32_RTC_TR (STM32_RTC_BASE + STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE + STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE + STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE + STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE + STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE + STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE + STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE + STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE + STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE + STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE + STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE + STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE + STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE + STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE + STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE + STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE + STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE + STM32_RTC_ALRMBSSR_OFFSET) +#define STM32_RTC_OR (STM32_RTC_BASE + STM32_RTC_OR_OFFSET) -#define STM32WB_RTC_BKPR(n) (STM32WB_RTC_BASE + STM32WB_RTC_BKPR_OFFSET(n)) -#define STM32WB_RTC_BKP0R (STM32WB_RTC_BASE + STM32WB_RTC_BKP0R_OFFSET) -#define STM32WB_RTC_BKP1R (STM32WB_RTC_BASE + STM32WB_RTC_BKP1R_OFFSET) -#define STM32WB_RTC_BKP2R (STM32WB_RTC_BASE + STM32WB_RTC_BKP2R_OFFSET) -#define STM32WB_RTC_BKP3R (STM32WB_RTC_BASE + STM32WB_RTC_BKP3R_OFFSET) -#define STM32WB_RTC_BKP4R (STM32WB_RTC_BASE + STM32WB_RTC_BKP4R_OFFSET) -#define STM32WB_RTC_BKP5R (STM32WB_RTC_BASE + STM32WB_RTC_BKP5R_OFFSET) -#define STM32WB_RTC_BKP6R (STM32WB_RTC_BASE + STM32WB_RTC_BKP6R_OFFSET) -#define STM32WB_RTC_BKP7R (STM32WB_RTC_BASE + STM32WB_RTC_BKP7R_OFFSET) -#define STM32WB_RTC_BKP8R (STM32WB_RTC_BASE + STM32WB_RTC_BKP8R_OFFSET) -#define STM32WB_RTC_BKP9R (STM32WB_RTC_BASE + STM32WB_RTC_BKP9R_OFFSET) -#define STM32WB_RTC_BKP10R (STM32WB_RTC_BASE + STM32WB_RTC_BKP10R_OFFSET) -#define STM32WB_RTC_BKP11R (STM32WB_RTC_BASE + STM32WB_RTC_BKP11R_OFFSET) -#define STM32WB_RTC_BKP12R (STM32WB_RTC_BASE + STM32WB_RTC_BKP12R_OFFSET) -#define STM32WB_RTC_BKP13R (STM32WB_RTC_BASE + STM32WB_RTC_BKP13R_OFFSET) -#define STM32WB_RTC_BKP14R (STM32WB_RTC_BASE + STM32WB_RTC_BKP14R_OFFSET) -#define STM32WB_RTC_BKP15R (STM32WB_RTC_BASE + STM32WB_RTC_BKP15R_OFFSET) -#define STM32WB_RTC_BKP16R (STM32WB_RTC_BASE + STM32WB_RTC_BKP16R_OFFSET) -#define STM32WB_RTC_BKP17R (STM32WB_RTC_BASE + STM32WB_RTC_BKP17R_OFFSET) -#define STM32WB_RTC_BKP18R (STM32WB_RTC_BASE + STM32WB_RTC_BKP18R_OFFSET) -#define STM32WB_RTC_BKP19R (STM32WB_RTC_BASE + STM32WB_RTC_BKP19R_OFFSET) +#define STM32_RTC_BKPR(n) (STM32_RTC_BASE + STM32_RTC_BKPR_OFFSET(n)) +#define STM32_RTC_BKP0R (STM32_RTC_BASE + STM32_RTC_BKP0R_OFFSET) +#define STM32_RTC_BKP1R (STM32_RTC_BASE + STM32_RTC_BKP1R_OFFSET) +#define STM32_RTC_BKP2R (STM32_RTC_BASE + STM32_RTC_BKP2R_OFFSET) +#define STM32_RTC_BKP3R (STM32_RTC_BASE + STM32_RTC_BKP3R_OFFSET) +#define STM32_RTC_BKP4R (STM32_RTC_BASE + STM32_RTC_BKP4R_OFFSET) +#define STM32_RTC_BKP5R (STM32_RTC_BASE + STM32_RTC_BKP5R_OFFSET) +#define STM32_RTC_BKP6R (STM32_RTC_BASE + STM32_RTC_BKP6R_OFFSET) +#define STM32_RTC_BKP7R (STM32_RTC_BASE + STM32_RTC_BKP7R_OFFSET) +#define STM32_RTC_BKP8R (STM32_RTC_BASE + STM32_RTC_BKP8R_OFFSET) +#define STM32_RTC_BKP9R (STM32_RTC_BASE + STM32_RTC_BKP9R_OFFSET) +#define STM32_RTC_BKP10R (STM32_RTC_BASE + STM32_RTC_BKP10R_OFFSET) +#define STM32_RTC_BKP11R (STM32_RTC_BASE + STM32_RTC_BKP11R_OFFSET) +#define STM32_RTC_BKP12R (STM32_RTC_BASE + STM32_RTC_BKP12R_OFFSET) +#define STM32_RTC_BKP13R (STM32_RTC_BASE + STM32_RTC_BKP13R_OFFSET) +#define STM32_RTC_BKP14R (STM32_RTC_BASE + STM32_RTC_BKP14R_OFFSET) +#define STM32_RTC_BKP15R (STM32_RTC_BASE + STM32_RTC_BKP15R_OFFSET) +#define STM32_RTC_BKP16R (STM32_RTC_BASE + STM32_RTC_BKP16R_OFFSET) +#define STM32_RTC_BKP17R (STM32_RTC_BASE + STM32_RTC_BKP17R_OFFSET) +#define STM32_RTC_BKP18R (STM32_RTC_BASE + STM32_RTC_BKP18R_OFFSET) +#define STM32_RTC_BKP19R (STM32_RTC_BASE + STM32_RTC_BKP19R_OFFSET) -# define STM32WB_RTC_BKCOUNT 20 +# define STM32_RTC_BKCOUNT 20 /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index 62851ed7634..ddf8e305d01 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -36,36 +36,36 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#define STM32WB_SPI_CLK_MAX 32000000ul +#define STM32_SPI_CLK_MAX 32000000ul /* Register Offsets *********************************************************/ -#define STM32WB_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WB_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WB_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WB_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WB_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WB_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WB_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ /* Register Addresses *******************************************************/ -#define STM32WB_SPI1_CR1 (STM32WB_SPI1_BASE + STM32WB_SPI_CR1_OFFSET) -#define STM32WB_SPI1_CR2 (STM32WB_SPI1_BASE + STM32WB_SPI_CR2_OFFSET) -#define STM32WB_SPI1_SR (STM32WB_SPI1_BASE + STM32WB_SPI_SR_OFFSET) -#define STM32WB_SPI1_DR (STM32WB_SPI1_BASE + STM32WB_SPI_DR_OFFSET) -#define STM32WB_SPI1_CRCPR (STM32WB_SPI1_BASE + STM32WB_SPI_CRCPR_OFFSET) -#define STM32WB_SPI1_RXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_RXCRCR_OFFSET) -#define STM32WB_SPI1_TXCRCR (STM32WB_SPI1_BASE + STM32WB_SPI_TXCRCR_OFFSET) +#define STM32_SPI1_CR1 (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +#define STM32_SPI1_CR2 (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +#define STM32_SPI1_SR (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +#define STM32_SPI1_DR (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +#define STM32_SPI1_CRCPR (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +#define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +#define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #if CONFIG_STM32WB_HAVE_SPI2 -# define STM32WB_SPI2_CR1 (STM32WB_SPI2_BASE + STM32WB_SPI_CR1_OFFSET) -# define STM32WB_SPI2_CR2 (STM32WB_SPI2_BASE + STM32WB_SPI_CR2_OFFSET) -# define STM32WB_SPI2_SR (STM32WB_SPI2_BASE + STM32WB_SPI_SR_OFFSET) -# define STM32WB_SPI2_DR (STM32WB_SPI2_BASE + STM32WB_SPI_DR_OFFSET) -# define STM32WB_SPI2_CRCPR (STM32WB_SPI2_BASE + STM32WB_SPI_CRCPR_OFFSET) -# define STM32WB_SPI2_RXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_RXCRCR_OFFSET) -# define STM32WB_SPI2_TXCRCR (STM32WB_SPI2_BASE + STM32WB_SPI_TXCRCR_OFFSET) +# define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2_DR (STM32_SPI2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2_CRCPR (STM32_SPI2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE + STM32_SPI_TXCRCR_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h index a4cfa546324..2fe834387c4 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_syscfg.h @@ -35,42 +35,42 @@ /* Register Offsets *********************************************************/ -#define STM32WB_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WB_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x0c)) /* Pin p = 0..15 */ -#define STM32WB_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WB_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WB_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WB_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WB_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WB_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WB_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ -#define STM32WB_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WB_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR1_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register 1 */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_SWPR2_OFFSET 0x0028 /* SYSCFG SRAM2 write protection register 2 */ -#define STM32WB_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ -#define STM32WB_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ -#define STM32WB_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ -#define STM32WB_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ -#define STM32WB_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG Interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG Interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG CPU2 Interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG CPU2 Interrupt mask register 2 */ +#define STM32_SYSCFG_SIPCR_OFFSET 0x0110 /* SYSCFG Secure IP control register */ /* Register Addresses *******************************************************/ -#define STM32WB_SYSCFG_MEMRMP (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_MEMRMP_OFFSET) -#define STM32WB_SYSCFG_CFGR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR(p) (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WB_SYSCFG_EXTICR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR1_OFFSET) -#define STM32WB_SYSCFG_EXTICR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR2_OFFSET) -#define STM32WB_SYSCFG_EXTICR3 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR3_OFFSET) -#define STM32WB_SYSCFG_EXTICR4 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_EXTICR4_OFFSET) -#define STM32WB_SYSCFG_SCSR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SCSR_OFFSET) -#define STM32WB_SYSCFG_CFGR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_CFGR2_OFFSET) -#define STM32WB_SYSCFG_SWPR1 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR1_OFFSET) -#define STM32WB_SYSCFG_SKR (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SKR_OFFSET) -#define STM32WB_SYSCFG_SWPR2 (STM32WB_SYSCFG_BASE + STM32WB_SYSCFG_SWPR2_OFFSET) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE + STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR1_OFFSET) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR2_OFFSET) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR3_OFFSET) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE + STM32_SYSCFG_EXTICR4_OFFSET) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE + STM32_SYSCFG_SCSR_OFFSET) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_CFGR2_OFFSET) +#define STM32_SYSCFG_SWPR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR1_OFFSET) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE + STM32_SYSCFG_SKR_OFFSET) +#define STM32_SYSCFG_SWPR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_SWPR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h index 6e646a6dc2f..447d8bdf784 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_tim.h @@ -29,150 +29,150 @@ /* Register Offsets *********************************************************/ -#define STM32WB_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WB_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WB_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ -#define STM32WB_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ -#define STM32WB_TIM_SR_OFFSET 0x0010 /* Status register */ -#define STM32WB_TIM_EGR_OFFSET 0x0014 /* Event generation register */ -#define STM32WB_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ -#define STM32WB_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WB_TIM_CNT_OFFSET 0x0024 /* Counter */ -#define STM32WB_TIM_PSC_OFFSET 0x0028 /* Prescaler */ -#define STM32WB_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ -#define STM32WB_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ -#define STM32WB_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ -#define STM32WB_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ -#define STM32WB_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ -#define STM32WB_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ -#define STM32WB_TIM_DCR_OFFSET 0x0048 /* DMA control register */ -#define STM32WB_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ -#define STM32WB_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WB_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ -#define STM32WB_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ -#define STM32WB_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ -#define STM32WB_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ -#define STM32WB_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ -#define STM32WB_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ +#define STM32_TIM_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_TIM_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_TIM_SMCR_OFFSET 0x0008 /* Slave mode control register (TIM1, TIM2) */ +#define STM32_TIM_DIER_OFFSET 0x000c /* DMA / Interrupt enable register */ +#define STM32_TIM_SR_OFFSET 0x0010 /* Status register */ +#define STM32_TIM_EGR_OFFSET 0x0014 /* Event generation register */ +#define STM32_TIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 */ +#define STM32_TIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_TIM_CNT_OFFSET 0x0024 /* Counter */ +#define STM32_TIM_PSC_OFFSET 0x0028 /* Prescaler */ +#define STM32_TIM_ARR_OFFSET 0x002c /* Auto-reload register */ +#define STM32_TIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM1, TIM16/TIM17) */ +#define STM32_TIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 */ +#define STM32_TIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (TIM1, TIM2) */ +#define STM32_TIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (TIM1, TIM2) */ +#define STM32_TIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (TIM1, TIM2) */ +#define STM32_TIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM1, TIM16/17) */ +#define STM32_TIM_DCR_OFFSET 0x0048 /* DMA control register */ +#define STM32_TIM_DMAR_OFFSET 0x004c /* DMA address for burst mode */ +#define STM32_TIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_TIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (TIM1) */ +#define STM32_TIM_CCR5_OFFSET 0x0058 /* Capture/compare register 5 (TIM1) */ +#define STM32_TIM_CCR6_OFFSET 0x005C /* Capture/compare register 6 (TIM1) */ +#define STM32_TIM_AF1_OFFSET 0x0060 /* Alternate function register 1 */ +#define STM32_TIM_AF2_OFFSET 0x0064 /* Alternate function register 2 (TIM1) */ +#define STM32_TIM_TISEL_OFFSET 0x0068 /* Input selector register */ /* Register Addresses *******************************************************/ /* Advanced Timer TIM1 */ -#define STM32WB_TIM1_CR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM1_CR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM1_SMCR (STM32WB_TIM1_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM1_DIER (STM32WB_TIM1_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM1_SR (STM32WB_TIM1_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM1_EGR (STM32WB_TIM1_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM1_CCMR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM1_CCMR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM1_CCER (STM32WB_TIM1_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM1_CNT (STM32WB_TIM1_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM1_PSC (STM32WB_TIM1_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM1_ARR (STM32WB_TIM1_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM1_RCR (STM32WB_TIM1_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM1_CCR1 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM1_CCR2 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM1_CCR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM1_CCR4 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM1_BDTR (STM32WB_TIM1_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM1_DCR (STM32WB_TIM1_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM1_DMAR (STM32WB_TIM1_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM1_OR1 (STM32WB_TIM1_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM1_CCMR3 (STM32WB_TIM1_BASE + STM32WB_TIM_CCMR3_OFFSET) -#define STM32WB_TIM1_CCR5 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR5_OFFSET) -#define STM32WB_TIM1_CCR6 (STM32WB_TIM1_BASE + STM32WB_TIM_CCR6_OFFSET) -#define STM32WB_TIM1_AF1 (STM32WB_TIM1_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM1_AF2 (STM32WB_TIM1_BASE + STM32WB_TIM_AF2_OFFSET) -#define STM32WB_TIM1_TISEL (STM32WB_TIM1_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE + STM32_TIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE + STM32_TIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE + STM32_TIM_CCR6_OFFSET) +#define STM32_TIM1_AF1 (STM32_TIM1_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM1_AF2 (STM32_TIM1_BASE + STM32_TIM_AF2_OFFSET) +#define STM32_TIM1_TISEL (STM32_TIM1_BASE + STM32_TIM_TISEL_OFFSET) /* General 32-bit Timer TIM2 */ -#define STM32WB_TIM2_CR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM2_CR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM2_SMCR (STM32WB_TIM2_BASE + STM32WB_TIM_SMCR_OFFSET) -#define STM32WB_TIM2_DIER (STM32WB_TIM2_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM2_SR (STM32WB_TIM2_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM2_EGR (STM32WB_TIM2_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM2_CCMR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM2_CCMR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCMR2_OFFSET) -#define STM32WB_TIM2_CCER (STM32WB_TIM2_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM2_CNT (STM32WB_TIM2_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM2_PSC (STM32WB_TIM2_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM2_ARR (STM32WB_TIM2_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM2_CCR1 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM2_CCR2 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR2_OFFSET) -#define STM32WB_TIM2_CCR3 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR3_OFFSET) -#define STM32WB_TIM2_CCR4 (STM32WB_TIM2_BASE + STM32WB_TIM_CCR4_OFFSET) -#define STM32WB_TIM2_DCR (STM32WB_TIM2_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM2_DMAR (STM32WB_TIM2_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM2_OR1 (STM32WB_TIM2_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM2_AF1 (STM32WB_TIM2_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM2_TISEL (STM32WB_TIM2_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE + STM32_TIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE + STM32_TIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE + STM32_TIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE + STM32_TIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE + STM32_TIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM2_OR1 (STM32_TIM2_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM2_AF1 (STM32_TIM2_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM2_TISEL (STM32_TIM2_BASE + STM32_TIM_TISEL_OFFSET) /* General Timers TIM16/TIM17 */ -#define STM32WB_TIM16_CR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM16_CR2 (STM32WB_TIM16_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM16_DIER (STM32WB_TIM16_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM16_SR (STM32WB_TIM16_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM16_EGR (STM32WB_TIM16_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM16_CCMR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM16_CCER (STM32WB_TIM16_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM16_CNT (STM32WB_TIM16_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM16_PSC (STM32WB_TIM16_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM16_ARR (STM32WB_TIM16_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM16_RCR (STM32WB_TIM16_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM16_CCR1 (STM32WB_TIM16_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM16_BDTR (STM32WB_TIM16_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM16_DCR (STM32WB_TIM16_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM16_DMAR (STM32WB_TIM16_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM16_OR1 (STM32WB_TIM16_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM16_AF1 (STM32WB_TIM16_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM16_TISEL (STM32WB_TIM16_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM16_OR1 (STM32_TIM16_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM16_AF1 (STM32_TIM16_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM16_TISEL (STM32_TIM16_BASE + STM32_TIM_TISEL_OFFSET) -#define STM32WB_TIM17_CR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CR1_OFFSET) -#define STM32WB_TIM17_CR2 (STM32WB_TIM17_BASE + STM32WB_TIM_CR2_OFFSET) -#define STM32WB_TIM17_DIER (STM32WB_TIM17_BASE + STM32WB_TIM_DIER_OFFSET) -#define STM32WB_TIM17_SR (STM32WB_TIM17_BASE + STM32WB_TIM_SR_OFFSET) -#define STM32WB_TIM17_EGR (STM32WB_TIM17_BASE + STM32WB_TIM_EGR_OFFSET) -#define STM32WB_TIM17_CCMR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCMR1_OFFSET) -#define STM32WB_TIM17_CCER (STM32WB_TIM17_BASE + STM32WB_TIM_CCER_OFFSET) -#define STM32WB_TIM17_CNT (STM32WB_TIM17_BASE + STM32WB_TIM_CNT_OFFSET) -#define STM32WB_TIM17_PSC (STM32WB_TIM17_BASE + STM32WB_TIM_PSC_OFFSET) -#define STM32WB_TIM17_ARR (STM32WB_TIM17_BASE + STM32WB_TIM_ARR_OFFSET) -#define STM32WB_TIM17_RCR (STM32WB_TIM17_BASE + STM32WB_TIM_RCR_OFFSET) -#define STM32WB_TIM17_CCR1 (STM32WB_TIM17_BASE + STM32WB_TIM_CCR1_OFFSET) -#define STM32WB_TIM17_BDTR (STM32WB_TIM17_BASE + STM32WB_TIM_BDTR_OFFSET) -#define STM32WB_TIM17_DCR (STM32WB_TIM17_BASE + STM32WB_TIM_DCR_OFFSET) -#define STM32WB_TIM17_DMAR (STM32WB_TIM17_BASE + STM32WB_TIM_DMAR_OFFSET) -#define STM32WB_TIM17_OR1 (STM32WB_TIM17_BASE + STM32WB_TIM_OR1_OFFSET) -#define STM32WB_TIM17_AF1 (STM32WB_TIM17_BASE + STM32WB_TIM_AF1_OFFSET) -#define STM32WB_TIM17_TISEL (STM32WB_TIM17_BASE + STM32WB_TIM_TISEL_OFFSET) +#define STM32_TIM17_CR1 (STM32_TIM17_BASE + STM32_TIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE + STM32_TIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE + STM32_TIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE + STM32_TIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE + STM32_TIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE + STM32_TIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE + STM32_TIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE + STM32_TIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE + STM32_TIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE + STM32_TIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE + STM32_TIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE + STM32_TIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE + STM32_TIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE + STM32_TIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE + STM32_TIM_DMAR_OFFSET) +#define STM32_TIM17_OR1 (STM32_TIM17_BASE + STM32_TIM_OR1_OFFSET) +#define STM32_TIM17_AF1 (STM32_TIM17_BASE + STM32_TIM_AF1_OFFSET) +#define STM32_TIM17_TISEL (STM32_TIM17_BASE + STM32_TIM_TISEL_OFFSET) /* Register Value Constants *************************************************/ /* Digital Filter options */ -#define STM32WB_DF_NOFILT (0x0) /* 0000: No filter */ -#define STM32WB_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ -#define STM32WB_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ -#define STM32WB_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ -#define STM32WB_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ -#define STM32WB_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ -#define STM32WB_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ -#define STM32WB_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ -#define STM32WB_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ -#define STM32WB_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ -#define STM32WB_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ -#define STM32WB_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ -#define STM32WB_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ -#define STM32WB_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ -#define STM32WB_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ -#define STM32WB_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ +#define STM32_DF_NOFILT (0x0) /* 0000: No filter */ +#define STM32_DF_FCKINTn2 (0x1) /* 0001: fSAMPLING = fCK_INT, N=2 */ +#define STM32_DF_FCKINTn4 (0x2) /* 0010: fSAMPLING = fCK_INT, N=4 */ +#define STM32_DF_FCKINTn8 (0x3) /* 0011: fSAMPLING = fCK_INT, N=8 */ +#define STM32_DF_FDTSd2n6 (0x4) /* 0100: fSAMPLING = fDTS/2, N=6 */ +#define STM32_DF_FDTSd2n8 (0x5) /* 0101: fSAMPLING = fDTS/2, N=8 */ +#define STM32_DF_FDTSd4n6 (0x6) /* 0110: fSAMPLING = fDTS/4, N=6 */ +#define STM32_DF_FDTSd4n8 (0x7) /* 0111: fSAMPLING = fDTS/4, N=8 */ +#define STM32_DF_FDTSd8n6 (0x8) /* 1000: fSAMPLING = fDTS/8, N=6 */ +#define STM32_DF_FDTSd8n8 (0x9) /* 1001: fSAMPLING = fDTS/8, N=8 */ +#define STM32_DF_FDTSd16n5 (0xa) /* 1010: fSAMPLING = fDTS/16, N=5 */ +#define STM32_DF_FDTSd16n6 (0xb) /* 1011: fSAMPLING = fDTS/16, N=6 */ +#define STM32_DF_FDTSd16n8 (0xc) /* 1100: fSAMPLING = fDTS/16, N=8 */ +#define STM32_DF_FDTSd32n5 (0xd) /* 1101: fSAMPLING = fDTS/32, N=5 */ +#define STM32_DF_FDTSd32n6 (0xe) /* 1110: fSAMPLING = fDTS/32, N=6 */ +#define STM32_DF_FDTSd32n8 (0xf) /* 1111: fSAMPLING = fDTS/32, N=8 */ /* Register Bitfield Definitions ********************************************/ @@ -397,7 +397,7 @@ #define TIM1_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM1_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM1_SMCR_ETF_MASK (0xf << TIM1_SMCR_ETF_SHIFT) -# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_SMCR_ETF(f) ((f) << TIM1_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM1_SMCR_ETPS_MASK (0x3 << TIM1_SMCR_ETPS_SHIFT) @@ -450,7 +450,7 @@ #define TIM2_SMCR_MSM (1 << 7) /* Bit 7: Master/slave mode */ #define TIM2_SMCR_ETF_SHIFT (8) /* Bits 8-11: External trigger filter */ #define TIM2_SMCR_ETF_MASK (0xf << TIM2_SMCR_ETF_SHIFT) -# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_SMCR_ETF(f) ((f) << TIM2_SMCR_ETF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_SMCR_ETPS_SHIFT (12) /* Bits 12-13: External trigger prescaler */ #define TIM2_SMCR_ETPS_MASK (0x3 << TIM2_SMCR_ETPS_SHIFT) @@ -920,7 +920,7 @@ #define TIM1_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM1_CCMR1_IC1F_MASK (0xf << TIM1_CCMR1_IC1F_SHIFT) -# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC1F(f) ((f) << TIM1_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM1_CCMR1_IC2PSC_MASK (0x3 << TIM1_CCMR1_IC2PSC_SHIFT) @@ -931,7 +931,7 @@ #define TIM1_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM1_CCMR1_IC2F_MASK (0xf << TIM1_CCMR1_IC2F_SHIFT) -# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR1_IC2F(f) ((f) << TIM1_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM1_CCMR2_IC3PSC_MASK (0x3 << TIM1_CCMR2_IC3PSC_SHIFT) @@ -942,7 +942,7 @@ #define TIM1_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM1_CCMR2_IC3F_MASK (0xf << TIM1_CCMR2_IC3F_SHIFT) -# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC3F(f) ((f) << TIM1_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM1_CCMR2_IC4PSC_MASK (0x3 << TIM1_CCMR2_IC4PSC_SHIFT) @@ -953,7 +953,7 @@ #define TIM1_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM1_CCMR2_IC4F_MASK (0xf << TIM1_CCMR2_IC4F_SHIFT) -# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_CCMR2_IC4F(f) ((f) << TIM1_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM2_CCMR1_IC1PSC_MASK (0x3 << TIM2_CCMR1_IC1PSC_SHIFT) @@ -964,7 +964,7 @@ #define TIM2_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM2_CCMR1_IC1F_MASK (0xf << TIM2_CCMR1_IC1F_SHIFT) -# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC1F(f) ((f) << TIM2_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR1_IC2PSC_SHIFT (10) /* Bits 10-11: Input Capture 2 Prescaler */ #define TIM2_CCMR1_IC2PSC_MASK (0x3 << TIM2_CCMR1_IC2PSC_SHIFT) @@ -975,7 +975,7 @@ #define TIM2_CCMR1_IC2F_SHIFT (12) /* Bits 12-15: Input Capture 2 Filter */ #define TIM2_CCMR1_IC2F_MASK (0xf << TIM2_CCMR1_IC2F_SHIFT) -# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR1_IC2F(f) ((f) << TIM2_CCMR1_IC2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC3PSC_SHIFT (2) /* Bits 2-3: Input Capture 3 Prescaler */ #define TIM2_CCMR2_IC3PSC_MASK (0x3 << TIM2_CCMR2_IC3PSC_SHIFT) @@ -986,7 +986,7 @@ #define TIM2_CCMR2_IC3F_SHIFT (4) /* Bits 4-7: Input Capture 3 Filter */ #define TIM2_CCMR2_IC3F_MASK (0xf << TIM2_CCMR2_IC3F_SHIFT) -# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC3F(f) ((f) << TIM2_CCMR2_IC3F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM2_CCMR2_IC4PSC_SHIFT (10) /* Bits 10-11: Input Capture 4 Prescaler */ #define TIM2_CCMR2_IC4PSC_MASK (0x3 << TIM2_CCMR2_IC4PSC_SHIFT) @@ -997,7 +997,7 @@ #define TIM2_CCMR2_IC4F_SHIFT (12) /* Bits 12-15: Input Capture 4 Filter */ #define TIM2_CCMR2_IC4F_MASK (0xf << TIM2_CCMR2_IC4F_SHIFT) -# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM2_CCMR2_IC4F(f) ((f) << TIM2_CCMR2_IC4F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM16_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM16_CCMR1_IC1PSC_MASK (0x3 << TIM16_CCMR1_IC1PSC_SHIFT) @@ -1008,7 +1008,7 @@ #define TIM16_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM16_CCMR1_IC1F_MASK (0xf << TIM16_CCMR1_IC1F_SHIFT) -# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM16_CCMR1_IC1F(f) ((f) << TIM16_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM17_CCMR1_IC1PSC_SHIFT (2) /* Bits 2-3: Input Capture 1 Prescaler */ #define TIM17_CCMR1_IC1PSC_MASK (0x3 << TIM17_CCMR1_IC1PSC_SHIFT) @@ -1019,7 +1019,7 @@ #define TIM17_CCMR1_IC1F_SHIFT (4) /* Bits 4-7: Input Capture 1 Filter */ #define TIM17_CCMR1_IC1F_MASK (0xf << TIM17_CCMR1_IC1F_SHIFT) -# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM17_CCMR1_IC1F(f) ((f) << TIM17_CCMR1_IC1F_SHIFT) /* f = STM32_DF_[digital filter option] */ /* Capture/compare enable register */ @@ -1178,11 +1178,11 @@ #define TIM1_BDTR_MOE (1 << 15) /* Bit 15: Main Output enable */ #define TIM1_BDTR_BKF_SHIFT (16) /* Bits 16-19: Break filter */ #define TIM1_BDTR_BKF_MASK (0xf << TIM1_BDTR_BKF_SHIFT) -# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BKF(f) ((f) << TIM1_BDTR_BKF_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2F_SHIFT (20) /* Bits 20-23: Break 2 filter */ #define TIM1_BDTR_BK2F_MASK (0xf << TIM1_BDTR_BK2F_SHIFT) -# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32WB_DF_[digital filter option] */ +# define TIM1_BDTR_BK2F(f) ((f) << TIM1_BDTR_BK2F_SHIFT) /* f = STM32_DF_[digital filter option] */ #define TIM1_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */ #define TIM1_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */ diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h index 2ce1c1b6268..e0dc620c613 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_uart.h @@ -37,34 +37,34 @@ /* Register Offsets *********************************************************/ -#define STM32WB_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32WB_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32WB_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32WB_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ -#define STM32WB_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32WB_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32WB_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32WB_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32WB_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ -#define STM32WB_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32WB_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32WB_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag Clear Register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ /* Register Addresses *******************************************************/ -#if STM32WB_NUSART > 0 -# define STM32WB_USART1_CR1 (STM32WB_USART1_BASE + STM32WB_USART_CR1_OFFSET) -# define STM32WB_USART1_CR2 (STM32WB_USART1_BASE + STM32WB_USART_CR2_OFFSET) -# define STM32WB_USART1_CR3 (STM32WB_USART1_BASE + STM32WB_USART_CR3_OFFSET) -# define STM32WB_USART1_BRR (STM32WB_USART1_BASE + STM32WB_USART_BRR_OFFSET) -# define STM32WB_USART1_GTPR (STM32WB_USART1_BASE + STM32WB_USART_GTPR_OFFSET) -# define STM32WB_USART1_RTOR (STM32WB_USART1_BASE + STM32WB_USART_RTOR_OFFSET) -# define STM32WB_USART1_RQR (STM32WB_USART1_BASE + STM32WB_USART_RQR_OFFSET) -# define STM32WB_USART1_ISR (STM32WB_USART1_BASE + STM32WB_USART_ISR_OFFSET) -# define STM32WB_USART1_ICR (STM32WB_USART1_BASE + STM32WB_USART_ICR_OFFSET) -# define STM32WB_USART1_RDR (STM32WB_USART1_BASE + STM32WB_USART_RDR_OFFSET) -# define STM32WB_USART1_TDR (STM32WB_USART1_BASE + STM32WB_USART_TDR_OFFSET) -# define STM32WB_USART1_PRESC (STM32WB_USART1_BASE + STM32WB_USART_PRESC_OFFSET) +#if STM32_NUSART > 0 +# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) +# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) +# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) +# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) +# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) +# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) +# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) +# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) #endif /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index 1192100de8f..fb2f6dc9451 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -60,20 +60,20 @@ /* Set the range of system SRAM1 */ -#define SRAM1_START STM32WB_SRAM1_BASE -#define SRAM1_END (SRAM1_START + STM32WB_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM1_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2a as well, requires a second memory region */ #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) # define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE +# define SRAM2B_START STM32_SRAM2B_BASE # define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) #endif @@ -83,13 +83,13 @@ */ #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# if SRAM2A_END > STM32WB_SRAM2A_BASE + STM32WB_SRAM2A_SIZE +# if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# if SRAM2B_END > STM32WB_SRAM2B_BASE + STM32WB_SRAM2B_SIZE +# if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 4e5de9fc88a..3b41a7bee2c 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -45,61 +45,61 @@ /* HCI event header fields helpers */ -#define STM32WB_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) -#define STM32WB_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) +#define STM32_BLEHCI_CCEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 3)) +#define STM32_BLEHCI_CCEVT_STATUS(e) (*((uint8_t *)(e) + 5)) -#define STM32WB_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) -#define STM32WB_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) +#define STM32_BLEHCI_CSEVT_OPCODE(e) (*(uint16_t *)((uint8_t *)(e) + 4)) +#define STM32_BLEHCI_CSEVT_STATUS(e) (*((uint8_t *)(e) + 2)) /* BLE init configuration params */ -#define STM32WB_BLE_PREP_WRITE_NUM \ - STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) +#define STM32_BLE_PREP_WRITE_NUM \ + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) -#define STM32WB_C2_MEM_BLOCK_NUM \ - STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ +#define STM32_C2_MEM_BLOCK_NUM \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ CONFIG_STM32WB_BLE_MAX_CONN, \ - STM32WB_BLE_PREP_WRITE_NUM) + STM32_BLE_PREP_WRITE_NUM) #ifdef CONFIG_STM32WB_BLE_C2HOST -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else -# define STM32WB_BLE_C2HOST STM32WB_SHCI_BLE_INIT_OPT_STACK_LL +# define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif #ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else -# define STM32WB_BLE_SVC_CHANGED_CHAR STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED +# define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif #ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else -# define STM32WB_BLE_DEVICE_NAME_MODE STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO +# define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif #ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else -# define STM32WB_BLE_CS_ALG2 STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED +# define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif #ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else -# define STM32WB_BLE_POWER_CLASS STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 +# define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 #endif -#define STM32WB_BLE_INIT_OPTIONS \ - (STM32WB_BLE_C2HOST | STM32WB_BLE_SVC_CHANGED_CHAR | \ - STM32WB_BLE_DEVICE_NAME_MODE | STM32WB_BLE_CS_ALG2 | \ - STM32WB_BLE_POWER_CLASS) +#define STM32_BLE_INIT_OPTIONS \ + (STM32_BLE_C2HOST | STM32_BLE_SVC_CHANGED_CHAR | \ + STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ + STM32_BLE_POWER_CLASS) #ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else -# define STM32WB_BLE_RXMOD_AGC_RSSI STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY +# define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY #endif /**************************************************************************** @@ -200,21 +200,21 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) switch (evt->type) { - case STM32WB_MBOX_HCIEVT: + case STM32_MBOX_HCIEVT: len = sizeof(evt->evt_hdr) + evt->evt_hdr.len; if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_COMPLETE) { wlinfo("received command COMPLETE event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CCEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CCEVT_STATUS(&evt->evt_hdr)); } else if (evt->evt_hdr.evt == BT_HCI_EVT_CMD_STATUS) { wlinfo("received command STATUS event from mailbox " "(opcode: 0x%04x, status: %u)\n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); #ifdef CONFIG_NIMBLE /* During initialisation NimBLE host stack sends unsupported @@ -223,18 +223,18 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) * with minimal impact we shim the response as succeeded. */ - if (STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && - (STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == + if (STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) != 0 && + (STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr) == BT_OP(BT_OGF_BASEBAND, 0x0063))) { wlwarn("suppress FAILED command STATUS event from mailbox, " "(opcode: 0x%04x, status: %u) \n", - STM32WB_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); + STM32_BLEHCI_CSEVT_OPCODE(&evt->evt_hdr), + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr)); /* Suppress status field error value */ - STM32WB_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; + STM32_BLEHCI_CSEVT_STATUS(&evt->evt_hdr) = 0; } #endif } @@ -247,29 +247,29 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) bt_netdev_receive(&g_blehci_driver, BT_EVT, &evt->evt_hdr, len); break; - case STM32WB_MBOX_HCIACL: + case STM32_MBOX_HCIACL: len = sizeof(evt->acl_hdr) + evt->acl_hdr.len; wlinfo("received HCI ACL from mailbox (handle: 0x%04x, len: %u)\n", evt->acl_hdr.handle, evt->acl_hdr.len); bt_netdev_receive(&g_blehci_driver, BT_ACL_IN, &evt->acl_hdr, len); break; - case STM32WB_MBOX_SYSEVT: + case STM32_MBOX_SYSEVT: wlinfo("received SYS EVT 0x%02x from mailbox\n", evt->evt_hdr.evt); - if (evt->evt_hdr.evt == STM32WB_SHCI_ASYNC_EVT && - *(uint16_t *)(&evt->evt_hdr + 1) == STM32WB_SHCI_ASYNC_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && + *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { stm32wb_blehci_bleinit(); } break; - case STM32WB_MBOX_SYSACK: + case STM32_MBOX_SYSACK: /* CPU2 Ready is the only expected response */ - DEBUGASSERT(evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY); + DEBUGASSERT(evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY); - if (evt->evt_hdr.evt == STM32WB_SHCI_ACK_EVT_C2RDY) + if (evt->evt_hdr.evt == STM32_SHCI_ACK_EVT_C2RDY) { wlinfo("system command ACK response"); @@ -304,8 +304,8 @@ static void stm32wb_blehci_bleinit(void) .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, .dle_enable = CONFIG_STM32WB_BLE_DLE, - .prep_write_op_num = STM32WB_BLE_PREP_WRITE_NUM, - .mem_block_num = STM32WB_C2_MEM_BLOCK_NUM, + .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, + .mem_block_num = STM32_C2_MEM_BLOCK_NUM, .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, @@ -313,12 +313,12 @@ static void stm32wb_blehci_bleinit(void) .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, - .options = STM32WB_BLE_INIT_OPTIONS, + .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, - .rx_model_config = STM32WB_BLE_RXMOD_AGC_RSSI + .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; /* Initialise BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index ae37c4e53e0..9789c80b45c 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -253,7 +253,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = { .id = 1, .nchan = 14, /* 0-6 - DMA1, 7-13 - DMA2 */ - .base = STM32WB_DMAMUX1_BASE + .base = STM32_DMAMUX1_BASE } }; @@ -264,7 +264,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 0 - DMA1 */ { - .base = STM32WB_DMA1_BASE, + .base = STM32_DMA1_BASE, .first = DMA1_FIRST, .nchan = DMA1_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 0-6 */ @@ -274,7 +274,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* 1 - DMA2 */ { - .base = STM32WB_DMA2_BASE, + .base = STM32_DMA2_BASE, .first = DMA2_FIRST, .nchan = DMA2_NCHAN, .dmamux = &g_dmamux[DMAMUX1], /* DMAMUX1 channels 7-13 */ @@ -292,57 +292,57 @@ static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA1, .chan = 0, - .irq = STM32WB_IRQ_DMA1CH1, + .irq = STM32_IRQ_DMA1CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA1, .chan = 1, - .irq = STM32WB_IRQ_DMA1CH2, + .irq = STM32_IRQ_DMA1CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA1, .chan = 2, - .irq = STM32WB_IRQ_DMA1CH3, + .irq = STM32_IRQ_DMA1CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA1, .chan = 3, - .irq = STM32WB_IRQ_DMA1CH4, + .irq = STM32_IRQ_DMA1CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA1, .chan = 4, - .irq = STM32WB_IRQ_DMA1CH5, + .irq = STM32_IRQ_DMA1CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA1, .chan = 5, - .irq = STM32WB_IRQ_DMA1CH6, + .irq = STM32_IRQ_DMA1CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA1, .chan = 6, - .irq = STM32WB_IRQ_DMA1CH7, + .irq = STM32_IRQ_DMA1CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA1_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA1_BASE + STM32_DMACHAN_OFFSET(6), }, #endif @@ -352,57 +352,57 @@ static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = { .ctrl = DMA2, .chan = 0, - .irq = STM32WB_IRQ_DMA2CH1, + .irq = STM32_IRQ_DMA2CH1, .shift = DMA_CHAN_SHIFT(0), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(0), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(0), }, { .ctrl = DMA2, .chan = 1, - .irq = STM32WB_IRQ_DMA2CH2, + .irq = STM32_IRQ_DMA2CH2, .shift = DMA_CHAN_SHIFT(1), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(1), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(1), }, { .ctrl = DMA2, .chan = 2, - .irq = STM32WB_IRQ_DMA2CH3, + .irq = STM32_IRQ_DMA2CH3, .shift = DMA_CHAN_SHIFT(2), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(2), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(2), }, { .ctrl = DMA2, .chan = 3, - .irq = STM32WB_IRQ_DMA2CH4, + .irq = STM32_IRQ_DMA2CH4, .shift = DMA_CHAN_SHIFT(3), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(3), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(3), }, { .ctrl = DMA2, .chan = 4, - .irq = STM32WB_IRQ_DMA2CH5, + .irq = STM32_IRQ_DMA2CH5, .shift = DMA_CHAN_SHIFT(4), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(4), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(4), }, { .ctrl = DMA2, .chan = 5, - .irq = STM32WB_IRQ_DMA2CH6, + .irq = STM32_IRQ_DMA2CH6, .shift = DMA_CHAN_SHIFT(5), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(5), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(5), }, { .ctrl = DMA2, .chan = 6, - .irq = STM32WB_IRQ_DMA2CH7, + .irq = STM32_IRQ_DMA2CH7, .shift = DMA_CHAN_SHIFT(6), - .base = STM32WB_DMA2_BASE + STM32WB_DMACHAN_OFFSET(6), + .base = STM32_DMA2_BASE + STM32_DMACHAN_OFFSET(6), }, #endif }; @@ -582,17 +582,17 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) /* Disable all interrupts at the DMA controller */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~DMA_CCR_ALLINTS; /* Disable the DMA channel */ regval &= ~DMA_CCR_EN; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Clear pending channel interrupts */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, DMA_ISR_CHAN_MASK(dmachan->chan)); } @@ -617,21 +617,21 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) { } #ifdef CONFIG_STM32WB_DMA1 - else if (irq >= STM32WB_IRQ_DMA1CH1 && irq <= STM32WB_IRQ_DMA1CH7) + else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { - channel = irq - STM32WB_IRQ_DMA1CH1; + channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif #ifdef CONFIG_STM32WB_DMA2 - else if (irq >= STM32WB_IRQ_DMA2CH1 && irq <= STM32WB_IRQ_DMA2CH5) + else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { - channel = irq - STM32WB_IRQ_DMA2CH1; + channel = irq - STM32_IRQ_DMA2CH1; controller = DMA2; } - else if (irq >= STM32WB_IRQ_DMA2CH6 && irq <= STM32WB_IRQ_DMA2CH7) + else if (irq >= STM32_IRQ_DMA2CH6 && irq <= STM32_IRQ_DMA2CH7) { - channel = irq - STM32WB_IRQ_DMA2CH6 + (6 - 1); + channel = irq - STM32_IRQ_DMA2CH6 + (6 - 1); controller = DMA2; } #endif @@ -647,7 +647,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the interrupt status (for this channel only) */ - isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET) & + isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET) & DMA_ISR_CHAN_MASK(dmachan->chan); /* Invoke the callback */ @@ -660,7 +660,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Clear the interrupts we are handling */ - dmabase_putreg(dmachan, STM32WB_DMA_IFCR_OFFSET, isr); + dmabase_putreg(dmachan, STM32_DMA_IFCR_OFFSET, isr); return OK; } @@ -697,28 +697,28 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * disabled. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_EN); - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); /* Set the peripheral register address in the DMA_CPARx register. The data * will be moved from/to this address to/from the memory after the * peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET, paddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CPAR_OFFSET, paddr); /* Set the memory address in the DMA_CMARx register. The data will be * written to or read from this memory after the peripheral event. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET, maddr); + dmachan_putreg(dmachan, STM32_DMACHAN_CMAR_OFFSET, maddr); /* Configure the total number of data to be transferred in the DMA_CNDTRx * register. After each peripheral event, this value will be decremented. */ - dmachan_putreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET, ntransfers); + dmachan_putreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET, ntransfers); /* Configure the channel priority using the PL[1:0] bits in the DMA_CCRx * register. Configure data transfer direction, circular mode, peripheral @@ -726,7 +726,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, * after half and/or full transfer in the DMA_CCRx register. */ - regval = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + regval = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); regval &= ~(DMA_CCR_MEM2MEM | DMA_CCR_PL_MASK | DMA_CCR_MSIZE_MASK | DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); @@ -734,7 +734,7 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, DMA_CCR_PSIZE_MASK | DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | DMA_CCR_DIR); regval |= ccr; - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, regval); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, regval); } /**************************************************************************** @@ -762,7 +762,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, * peripheral connected on the channel. */ - ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); + ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); ccr |= DMA_CCR_EN; /* In normal mode, interrupt at either half or full completion. In circular @@ -796,7 +796,7 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, ccr |= (half ? DMA_CCR_HTIE : 0) | DMA_CCR_TCIE | DMA_CCR_TEIE; } - dmachan_putreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET, ccr); + dmachan_putreg(dmachan, STM32_DMACHAN_CCR_OFFSET, ccr); } /**************************************************************************** @@ -809,7 +809,7 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) DEBUGASSERT(dmachan->ctrl == DMA1 || dmachan->ctrl == DMA2); - return dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); + return dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** @@ -824,11 +824,11 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) flags = enter_critical_section(); - regs->isr = dmabase_getreg(dmachan, STM32WB_DMA_ISR_OFFSET); - regs->ccr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CCR_OFFSET); - regs->cndtr = dmachan_getreg(dmachan, STM32WB_DMACHAN_CNDTR_OFFSET); - regs->cpar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CPAR_OFFSET); - regs->cmar = dmachan_getreg(dmachan, STM32WB_DMACHAN_CMAR_OFFSET); + regs->isr = dmabase_getreg(dmachan, STM32_DMA_ISR_OFFSET); + regs->ccr = dmachan_getreg(dmachan, STM32_DMACHAN_CCR_OFFSET); + regs->cndtr = dmachan_getreg(dmachan, STM32_DMACHAN_CNDTR_OFFSET); + regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); + regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, @@ -857,19 +857,19 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->ctrl + 1, msg); dmainfo(" ISR[%08x]: %08x\n", - dmabase + STM32WB_DMA_ISR_OFFSET, + dmabase + STM32_DMA_ISR_OFFSET, regs->isr); dmainfo(" CCR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CCR_OFFSET, + dmachan->base + STM32_DMACHAN_CCR_OFFSET, regs->ccr); dmainfo(" CNDTR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CNDTR_OFFSET, + dmachan->base + STM32_DMACHAN_CNDTR_OFFSET, regs->cndtr); dmainfo(" CPAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CPAR_OFFSET, + dmachan->base + STM32_DMACHAN_CPAR_OFFSET, regs->cpar); dmainfo(" CMAR[%08x]: %08x\n", - dmachan->base + STM32WB_DMACHAN_CMAR_OFFSET, + dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, @@ -888,13 +888,13 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, struct stm32wb_dmaregs_s *regs) { - regs->dmamux.ccr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(chan)); - regs->dmamux.csr = dmamux_getreg(dmamux, STM32WB_DMAMUX_CSR_OFFSET); - regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG0CR_OFFSET); - regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG1CR_OFFSET); - regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG2CR_OFFSET); - regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RG3CR_OFFSET); - regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32WB_DMAMUX_RGSR_OFFSET); + regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); + regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); + regs->dmamux.rg0cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG0CR_OFFSET); + regs->dmamux.rg1cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG1CR_OFFSET); + regs->dmamux.rg2cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG2CR_OFFSET); + regs->dmamux.rg3cr = dmamux_getreg(dmamux, STM32_DMAMUX_RG3CR_OFFSET); + regs->dmamux.rgsr = dmamux_getreg(dmamux, STM32_DMAMUX_RGSR_OFFSET); } #endif @@ -908,20 +908,20 @@ static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CXCR_OFFSET(channel), + dmamux->base + STM32_DMAMUX_CXCR_OFFSET(channel), regs->dmamux.ccr); dmainfo(" CSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_CSR_OFFSET, regs->dmamux.csr); + dmamux->base + STM32_DMAMUX_CSR_OFFSET, regs->dmamux.csr); dmainfo(" RG0CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); + dmamux->base + STM32_DMAMUX_RG0CR_OFFSET, regs->dmamux.rg0cr); dmainfo(" RG1CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); + dmamux->base + STM32_DMAMUX_RG1CR_OFFSET, regs->dmamux.rg1cr); dmainfo(" RG2CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); + dmamux->base + STM32_DMAMUX_RG2CR_OFFSET, regs->dmamux.rg2cr); dmainfo(" RG3CR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); + dmamux->base + STM32_DMAMUX_RG3CR_OFFSET, regs->dmamux.rg3cr); dmainfo(" RGSR[%08x]: %08x\n", - dmamux->base + STM32WB_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); + dmamux->base + STM32_DMAMUX_RGSR_OFFSET, regs->dmamux.rgsr); }; #endif @@ -1179,7 +1179,7 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, /* DMAMUX Set DMA channel source */ regval = dmachan->dmamux_req << DMAMUX_CCR_DMAREQID_SHIFT; - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), regval); /* Enable DMA channel */ @@ -1224,7 +1224,7 @@ void stm32wb_dmastop(DMA_HANDLE handle) /* DMAMUX Clear DMA channel source */ - dmamux_putreg(dmamux, STM32WB_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); + dmamux_putreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(dmamux_chan), 0); } /**************************************************************************** @@ -1315,23 +1315,23 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) mend = maddr + (count << msize_shift) - 1; - if ((maddr & STM32WB_REGION_MASK) != (mend & STM32WB_REGION_MASK)) + if ((maddr & STM32_REGION_MASK) != (mend & STM32_REGION_MASK)) { return false; } - switch (maddr & STM32WB_REGION_MASK) + switch (maddr & STM32_REGION_MASK) { - case STM32WB_PERIPH_BASE: - case STM32WB_FSMC_BASE: - case STM32WB_FSMC_BANK1: - case STM32WB_FSMC_BANK2: - case STM32WB_FSMC_BANK3: - case STM32WB_QSPI_BANK: - case STM32WB_SRAM_BASE: - case STM32WB_SRAM2_BASE: - case STM32WB_SRAM3_BASE: - case STM32WB_CODE_BASE: + case STM32_PERIPH_BASE: + case STM32_FSMC_BASE: + case STM32_FSMC_BANK1: + case STM32_FSMC_BANK2: + case STM32_FSMC_BANK3: + case STM32_QSPI_BANK: + case STM32_SRAM_BASE: + case STM32_SRAM2_BASE: + case STM32_SRAM3_BASE: + case STM32_CODE_BASE: /* All RAM and flash is supported */ diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index a0e29b306f1..3a45d0e54c7 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -49,7 +49,7 @@ /* Port letters for prettier debug output */ -static const char g_portchar[STM32WB_NPORTS] = +static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) @@ -88,31 +88,31 @@ int stm32wb_dumpgpio(uint32_t pinset, const char *msg) flags = enter_critical_section(); - DEBUGASSERT(port < STM32WB_NPORTS); + DEBUGASSERT(port < STM32_NPORTS); _info("GPIO%c pinset: %08x base: %08x -- %s\n", g_portchar[port], pinset, base, msg); - if ((getreg32(STM32WB_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) + if ((getreg32(STM32_RCC_AHB2ENR) & RCC_AHB2ENR_GPIOEN(port)) != 0) { _info(" MODE: %08x OTYPE: %04x OSPEED: %08x PUPDR: %08x\n", - getreg32(base + STM32WB_GPIO_MODER_OFFSET), - getreg32(base + STM32WB_GPIO_OTYPER_OFFSET), - getreg32(base + STM32WB_GPIO_OSPEED_OFFSET), - getreg32(base + STM32WB_GPIO_PUPDR_OFFSET)); + getreg32(base + STM32_GPIO_MODER_OFFSET), + getreg32(base + STM32_GPIO_OTYPER_OFFSET), + getreg32(base + STM32_GPIO_OSPEED_OFFSET), + getreg32(base + STM32_GPIO_PUPDR_OFFSET)); _info(" IDR: %04x ODR: %04x BSRR: %08x LCKR: %04x\n", - getreg32(base + STM32WB_GPIO_IDR_OFFSET), - getreg32(base + STM32WB_GPIO_ODR_OFFSET), - getreg32(base + STM32WB_GPIO_BSRR_OFFSET), - getreg32(base + STM32WB_GPIO_LCKR_OFFSET)); + getreg32(base + STM32_GPIO_IDR_OFFSET), + getreg32(base + STM32_GPIO_ODR_OFFSET), + getreg32(base + STM32_GPIO_BSRR_OFFSET), + getreg32(base + STM32_GPIO_LCKR_OFFSET)); _info(" AFRH: %08x AFRL: %08x\n", - getreg32(base + STM32WB_GPIO_AFRH_OFFSET), - getreg32(base + STM32WB_GPIO_AFRL_OFFSET)); + getreg32(base + STM32_GPIO_AFRH_OFFSET), + getreg32(base + STM32_GPIO_AFRL_OFFSET)); } else { _info(" GPIO%c not enabled: AHB2ENR: %08x\n", - g_portchar[port], getreg32(STM32WB_RCC_AHB2ENR)); + g_portchar[port], getreg32(STM32_RCC_AHB2ENR)); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index a0076663dba..8a4b9cf1538 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -71,7 +71,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTCALRM); + irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + up_enable_irq(STM32_IRQ_RTCALRM); } else { - up_disable_irq(STM32WB_IRQ_RTCALRM); + up_disable_irq(STM32_IRQ_RTCALRM); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCALARM), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCALARM), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCALARM) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCALARM) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCALARM) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 8ef567ccd1d..6d5afe56e69 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -71,7 +71,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(0), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(0), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -92,7 +92,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(1), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(1), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -113,7 +113,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(2), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(2), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -134,7 +134,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(3), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(3), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -155,7 +155,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(EXTI_PR1_PIF(4), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(4), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -179,7 +179,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WB_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -192,7 +192,7 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WB_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -265,7 +265,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WB_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -293,14 +293,14 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WB_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wb_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WB_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wb_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -351,19 +351,19 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(pin), risingedge ? EXTI_RTSR1_RT(pin) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(pin), fallingedge ? EXTI_FTSR1_FT(pin) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(pin), event ? EXTI_C1EMR1_EM(pin) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(pin), func ? EXTI_C1IMR1_IM(pin) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index d470837ff4d..8caaed92019 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -69,7 +69,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_PVD), STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,29 +114,29 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); - up_enable_irq(STM32WB_IRQ_PVD); + irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + up_enable_irq(STM32_IRQ_PVD); } else { - up_disable_irq(STM32WB_IRQ_PVD); + up_disable_irq(STM32_IRQ_PVD); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_PVD), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_PVD), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_PVD) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_PVD), event ? EXTI_C1EMR1_EM(EXTI_EVT_PVD) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_PVD), func ? EXTI_C1IMR1_IM(EXTI_EVT_PVD) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index eae587fda8e..0e44b3f4dcc 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -71,7 +71,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) /* Clear the pending EXTI interrupt */ - putreg32(EXTI_RTC_WAKEUP, STM32WB_EXTI_PR1); + putreg32(EXTI_RTC_WAKEUP, STM32_EXTI_PR1); return ret; } @@ -107,29 +107,29 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32WB_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); - up_enable_irq(STM32WB_IRQ_RTC_WKUP); + irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + up_enable_irq(STM32_IRQ_RTC_WKUP); } else { - up_disable_irq(STM32WB_IRQ_RTC_WKUP); + up_disable_irq(STM32_IRQ_RTC_WKUP); } /* Configure rising/falling edges */ - modifyreg32(STM32WB_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP), risingedge ? EXTI_RTSR1_RT(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP), fallingedge ? EXTI_FTSR1_FT(EXTI_EVT_RTCWAKEUP) : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WB_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP), event ? EXTI_C1EMR1_EM(EXTI_EVT_RTCWAKEUP) : 0); - modifyreg32(STM32WB_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP), func ? EXTI_C1IMR1_IM(EXTI_EVT_RTCWAKEUP) : 0); diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 5d151d37c75..346a1355940 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -63,7 +63,7 @@ #define OPTBYTES_KEY1 0x08192a3b #define OPTBYTES_KEY2 0x4c5d6e7f -#define FLASH_PAGE_SIZE STM32WB_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (12) /* 2**12 = 4096B */ @@ -91,35 +91,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WB_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WB_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WB_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WB_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WB_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -136,17 +136,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", page); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_STRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -225,20 +225,20 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WB_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WB_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } @@ -251,42 +251,42 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WB_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WB_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WB_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WB_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WB_FLASH_PAGESIZE + STM32WB_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WB_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -298,7 +298,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WB_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -336,7 +336,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WB_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -369,12 +369,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WB_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WB_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WB_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -444,23 +444,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WB_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); for (i = 0; i < FLASH_PAGE_WORDS; i += 2) { *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WB_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wb_waste(); } /* Verify */ - if (getreg32(STM32WB_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EROFS; goto out; } @@ -468,13 +468,13 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) if (getreg32(dest - 1) != *(src - 1) || getreg32(dest - 2) != *(src - 2)) { - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); ret = -EIO; goto out; } } - modifyreg32(STM32WB_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); /* Adjust pointers and counts for the next time through the loop */ @@ -494,9 +494,9 @@ out: if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WB_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WB_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index a4168046aa4..bd56695e121 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -69,7 +69,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); return OK; } #endif /* CONFIG_CLOCK_TIMEKEEPING */ @@ -117,14 +117,14 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, return -EBUSY; } - STM32WB_TIM_SETCLOCK(freerun->tch, frequency); + STM32_TIM_SETCLOCK(freerun->tch, frequency); /* Initialize the remaining fields in the state structure and return * success. */ freerun->chan = chan; - freerun->width = STM32WB_TIM_GETWIDTH(freerun->tch); + freerun->width = STM32_TIM_GETWIDTH(freerun->tch); #ifdef CONFIG_CLOCK_TIMEKEEPING freerun->counter_mask = 0xffffffff; @@ -135,21 +135,21 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); #endif /* Set timer period */ - STM32WB_TIM_SETPERIOD(freerun->tch, + STM32_TIM_SETPERIOD(freerun->tch, (uint32_t)((1ull << freerun->width) - 1)); /* Start the counter */ - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); #ifndef CONFIG_CLOCK_TIMEKEEPING - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(freerun->tch, GTIM_DIER_UIE); #endif return OK; @@ -198,9 +198,9 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, flags = enter_critical_section(); overflow = freerun->overflow; - counter = STM32WB_TIM_GETCOUNTER(freerun->tch); - pending = STM32WB_TIM_CHECKINT(freerun->tch, 0); - verify = STM32WB_TIM_GETCOUNTER(freerun->tch); + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -208,7 +208,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, if (pending) { - STM32WB_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(freerun->tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -256,7 +256,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, uint64_t *counter) { - *counter = STM32WB_TIM_GETCOUNTER(freerun->tch); + *counter = STM32_TIM_GETCOUNTER(freerun->tch); return OK; } @@ -285,9 +285,9 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Now we can disable the timer interrupt and disable the timer. */ - STM32WB_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(freerun->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_SETISR(freerun->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(freerun->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, NULL, 0); /* Free the timer */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index d857d472a50..433df3cea15 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -52,14 +52,14 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WB_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { - STM32WB_GPIOA_BASE, - STM32WB_GPIOB_BASE, - STM32WB_GPIOC_BASE, - STM32WB_GPIOD_BASE, - STM32WB_GPIOE_BASE, - STM32WB_GPIOH_BASE + STM32_GPIOA_BASE, + STM32_GPIOB_BASE, + STM32_GPIOC_BASE, + STM32_GPIOD_BASE, + STM32_GPIOE_BASE, + STM32_GPIOH_BASE }; /**************************************************************************** @@ -119,7 +119,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WB_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -168,10 +168,10 @@ int stm32wb_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WB_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -194,10 +194,10 @@ int stm32wb_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WB_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -212,17 +212,17 @@ int stm32wb_configgpio(uint32_t cfgset) if (pin < 8) { - regval = getreg32(base + STM32WB_GPIO_AFRL_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRL_OFFSET); regval &= ~GPIO_AFRL_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRL_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRL_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRL_OFFSET); } else { - regval = getreg32(base + STM32WB_GPIO_AFRH_OFFSET); + regval = getreg32(base + STM32_GPIO_AFRH_OFFSET); regval &= ~GPIO_AFRH_AFSEL_MASK(pin); regval |= (setting << GPIO_AFRH_AFSEL_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_AFRH_OFFSET); + putreg32(regval, base + STM32_GPIO_AFRH_OFFSET); } /* Set speed (Only outputs and alternate function pins) */ @@ -254,14 +254,14 @@ int stm32wb_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WB_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WB_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WB_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -274,7 +274,7 @@ int stm32wb_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WB_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -291,7 +291,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WB_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -353,7 +353,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -374,7 +374,7 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WB_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -393,7 +393,7 @@ bool stm32wb_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WB_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -402,7 +402,7 @@ bool stm32wb_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WB_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index befb722c0ee..e407a28a564 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -45,11 +45,11 @@ ****************************************************************************/ #if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 6 +# define STM32_NPORTS 6 #elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) -# define STM32WB_NPORTS 5 +# define STM32_NPORTS 5 #else -# define STM32WB_NPORTS 4 +# define STM32_NPORTS 4 #endif /* Bit-encoded input to stm32wb_configgpio() */ @@ -250,7 +250,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WB_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 3d7d6b8db19..182d588027a 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -32,7 +32,7 @@ * Standard-mode (up to 100 kHz) * Fast-mode (up to 400 kHz) * Fast-mode+ (up to 1 MHz) - * Clock source selection is based on STM32WB_RCC_CCIPR register + * Clock source selection is based on STM32_RCC_CCIPR register * * - Multiple instances (shared bus) * - Interrupt based operation @@ -432,14 +432,14 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_STM32WB_I2C1 static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = { - .base = STM32WB_I2C1_BASE, + .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, .reset_bit = RCC_APB1RSTR1_I2C1RST, .scl_pin = GPIO_I2C1_SCL, .sda_pin = GPIO_I2C1_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C1EV, - .er_irq = STM32WB_IRQ_I2C1ER + .ev_irq = STM32_IRQ_I2C1EV, + .er_irq = STM32_IRQ_I2C1ER #endif }; @@ -468,14 +468,14 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = #ifdef CONFIG_STM32WB_I2C3 static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = { - .base = STM32WB_I2C3_BASE, + .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, .reset_bit = RCC_APB1RSTR1_I2C3RST, .scl_pin = GPIO_I2C3_SCL, .sda_pin = GPIO_I2C3_SDA, #ifndef CONFIG_I2C_POLLED - .ev_irq = STM32WB_IRQ_I2C3EV, - .er_irq = STM32WB_IRQ_I2C3ER + .ev_irq = STM32_IRQ_I2C3EV, + .er_irq = STM32_IRQ_I2C3ER #endif }; @@ -631,7 +631,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) static inline void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif @@ -663,7 +663,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -701,7 +701,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; @@ -769,7 +769,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } @@ -785,7 +785,7 @@ static inline void stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } @@ -799,7 +799,7 @@ stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, static inline void stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** @@ -812,7 +812,7 @@ stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } @@ -826,7 +826,7 @@ stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } @@ -840,7 +840,7 @@ stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -1076,14 +1076,14 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) switch (frequency) { case 100000ul: @@ -1104,7 +1104,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #else -#if STM32WB_PCLK1_FREQUENCY != 64000000ul +#if STM32_PCLK1_FREQUENCY != 64000000ul # error Unsupported I2C configuration. #endif @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32WB_I2C_TIMINGR_OFFSET, timingr); + stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1279,7 +1279,7 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** @@ -1300,7 +1300,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending STOP\n"); stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR2_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } @@ -1315,7 +1315,7 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) static inline uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) { - return getreg32(priv->config->base + STM32WB_I2C_ISR_OFFSET); + return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** @@ -1329,7 +1329,7 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) static inline void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } @@ -1357,7 +1357,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1526,7 +1526,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32WB_I2C_TXDR_OFFSET, *priv->ptr); + stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32WB_I2C_RXDR_OFFSET); + *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1622,7 +1622,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Unsupported state */ stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1866,7 +1866,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); @@ -1889,7 +1889,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_ICR_OFFSET, + stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,7 +1954,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32WB_I2C_ISR_OFFSET); + status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; @@ -1992,9 +1992,9 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable power and reset the peripheral */ - modifyreg32(STM32WB_RCC_APB1ENR1, 0, priv->config->clk_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, 0, priv->config->reset_bit); - modifyreg32(STM32WB_RCC_APB1RSTR1, priv->config->reset_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, 0, priv->config->clk_bit); + modifyreg32(STM32_RCC_APB1RSTR1, 0, priv->config->reset_bit); + modifyreg32(STM32_RCC_APB1RSTR1, priv->config->reset_bit, 0); /* Configure pins */ @@ -2030,7 +2030,7 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32WB_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } @@ -2047,7 +2047,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32WB_I2C_CR1_OFFSET, 0); + stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ @@ -2066,7 +2066,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) /* Disable clocking */ - modifyreg32(STM32WB_RCC_APB1ENR1, priv->config->clk_bit, 0); + modifyreg32(STM32_RCC_APB1ENR1, priv->config->clk_bit, 0); return OK; } @@ -2146,8 +2146,8 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, waitrc = stm32wb_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32WB_I2C_CR2_OFFSET); + cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index a9999bdcd12..795ec398c46 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -53,27 +53,27 @@ void stm32wb_ipccreset(void) /* Disable CPU1 IPCC interrupts */ - putreg32(0x00000000, STM32WB_IPCC_C1CR); + putreg32(0x00000000, STM32_IPCC_C1CR); /* Clear CPU1 IPCC receive channel status */ - putreg32(IPCC_C1SCR_CLR_MASK, STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_CLR_MASK, STM32_IPCC_C1SCR); /* Clear CPU2 IPCC receive channel status */ - putreg32(IPCC_C2SCR_CLR_MASK, STM32WB_IPCC_C2SCR); + putreg32(IPCC_C2SCR_CLR_MASK, STM32_IPCC_C2SCR); /* Disable CPU1 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C1MR); + regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_MASK | IPCC_C1MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); /* Disable CPU2 transmit/receive channels */ - regval = getreg32(STM32WB_IPCC_C2MR); + regval = getreg32(STM32_IPCC_C2MR); regval |= IPCC_C2MR_OM_MASK | IPCC_C2MR_FM_MASK; - putreg32(regval, STM32WB_IPCC_C2MR); + putreg32(regval, STM32_IPCC_C2MR); } /**************************************************************************** @@ -90,21 +90,21 @@ void stm32wb_ipccenable(void) /* CPU2 IPCC clock enable */ - regval = getreg32(STM32WB_RCC_C2AHB3ENR); + regval = getreg32(STM32_RCC_C2AHB3ENR); regval |= RCC_C2AHB3ENR_IPCCEN; - putreg32(regval, STM32WB_RCC_C2AHB3ENR); + putreg32(regval, STM32_RCC_C2AHB3ENR); /* Enable EXTI event request for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_C2EMR2); + regval = getreg32(STM32_EXTI_C2EMR2); regval |= EXTI_C2EMR2_EM(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_C2EMR2); + putreg32(regval, STM32_EXTI_C2EMR2); /* Enable EXTI rising edge trigger for C1SEV interrupt to CPU2 */ - regval = getreg32(STM32WB_EXTI_RTSR2); + regval = getreg32(STM32_EXTI_RTSR2); regval |= EXTI_RTSR2_RT(EXTI_EVT_C1SEV); - putreg32(regval, STM32WB_EXTI_RTSR2); + putreg32(regval, STM32_EXTI_RTSR2); /* Set the internal event flag and send an event to CPU2 */ @@ -116,7 +116,7 @@ void stm32wb_ipccenable(void) /* Boot CPU2 after reset or wakeup from stop or standby modes */ - regval = getreg32(STM32WB_PWR_CR4); + regval = getreg32(STM32_PWR_CR4); regval |= PWR_CR4_C2BOOT; - putreg32(regval, STM32WB_PWR_CR4); + putreg32(regval, STM32_PWR_CR4); } diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index 1d8ae70afa5..b130c899662 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -88,7 +88,7 @@ void stm32wb_ipccenable(void); static inline bool stm32wb_ipcc_rxactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** @@ -101,7 +101,7 @@ static inline bool stm32wb_ipcc_rxactive(uint8_t chan) static inline bool stm32wb_ipcc_txactive(uint8_t chan) { - return (getreg32(STM32WB_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; + return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** @@ -114,7 +114,7 @@ static inline bool stm32wb_ipcc_txactive(uint8_t chan) static inline void stm32wb_ipcc_settxactive(uint8_t chan) { - putreg32(IPCC_C1SCR_SET_BIT(chan), STM32WB_IPCC_C1SCR); + putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** @@ -127,9 +127,9 @@ static inline void stm32wb_ipcc_settxactive(uint8_t chan) static inline void stm32wb_ipcc_masktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -142,9 +142,9 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -157,9 +157,9 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) static inline void stm32wb_ipcc_maskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } /**************************************************************************** @@ -172,9 +172,9 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) { - uint32_t regval = getreg32(STM32WB_IPCC_C1MR); + uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); - putreg32(regval, STM32WB_IPCC_C1MR); + putreg32(regval, STM32_IPCC_C1MR); } #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index 9b06b2bd709..f87503a7802 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -203,13 +203,13 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WB_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WB_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -219,19 +219,19 @@ static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WB_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WB_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WB_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WB_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -261,7 +261,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WB_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -319,13 +319,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WB_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WB_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WB_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -335,23 +335,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WB_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WB_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WB_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WB_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WB_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WB_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WB_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WB_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); #endif stm32wb_dumpnvic("initial", NR_IRQS); @@ -387,7 +387,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -422,7 +422,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WB_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -465,10 +465,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WB_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WB_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -481,7 +481,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WB_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index 7d73b1afd13..c8807a1f5bf 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -45,51 +45,51 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_LPUART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK1_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB1ENR2 -# define STM32WB_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WB_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WB_CONSOLE_BASE STM32WB_USART1_BASE -# define STM32WB_APBCLOCK STM32WB_PCLK2_FREQUENCY -# define STM32WB_CONSOLE_APBREG STM32WB_RCC_APB2ENR -# define STM32WB_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WB_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WB_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WB_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WB_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WB_CONSOLE_TX GPIO_USART1_TX -# define STM32WB_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WB_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WB_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WB_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WB_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WB_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -97,9 +97,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WB_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WB_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -115,7 +115,7 @@ /* CR2 settings */ -# if STM32WB_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -157,19 +157,19 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WB_USARTDIV8 \ - (((STM32WB_APBCLOCK << 1) + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) -# define STM32WB_USARTDIV16 \ - ((STM32WB_APBCLOCK + (STM32WB_CONSOLE_BAUD >> 1)) / STM32WB_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ -# if STM32WB_USARTDIV8 > 100 -# define STM32WB_BRR_VALUE STM32WB_USARTDIV16 +# if STM32_USARTDIV8 > 100 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WB_BRR_VALUE \ - ((STM32WB_USARTDIV8 & 0xfff0) | ((STM32WB_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif #endif /* HAVE_CONSOLE */ @@ -211,22 +211,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WB_CONSOLE_BASE + STM32WB_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WB_CONSOLE_RS485_DIR - while ((getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -252,7 +252,7 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WB_CONSOLE_APBREG, 0, STM32WB_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -261,17 +261,17 @@ void stm32wb_lowsetup(void) * stm32wb_rcc.c */ -#ifdef STM32WB_CONSOLE_TX - stm32wb_configgpio(STM32WB_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wb_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WB_CONSOLE_RX - stm32wb_configgpio(STM32WB_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wb_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WB_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32WB_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32WB_CONSOLE_RS485_DIR, - !STM32WB_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -279,42 +279,42 @@ void stm32wb_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WB_BRR_VALUE, - STM32WB_CONSOLE_BASE + STM32WB_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WB_CONSOLE_BASE + STM32WB_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 86c2e298c68..232e03af6f7 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -44,12 +44,12 @@ * the beginning of SRAM2a. */ -#define STM32WB_MBOX_SHARED_BASE STM32WB_SRAM2A_BASE +#define STM32_MBOX_SHARED_BASE STM32_SRAM2A_BASE /* Mailbox shared buffer fields */ #define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32WB_MBOX_SHARED_BASE) + (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) #define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) #define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) @@ -59,12 +59,12 @@ /* Mailbox buffer sizes */ -#define STM32WB_MBOX_CS_BUF_SIZE 16 -#define STM32WB_MBOX_CMDPKT_BUF_SIZE 268 -#define STM32WB_MBOX_ACLPKT_BUF_SIZE 264 +#define STM32_MBOX_CS_BUF_SIZE 16 +#define STM32_MBOX_CMDPKT_BUF_SIZE 268 +#define STM32_MBOX_ACLPKT_BUF_SIZE 264 -#define STM32WB_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32WB_MBOX_CMDPKT_BUF_SIZE) +#define STM32_MBOX_RX_BUF_SIZE \ + (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -156,15 +156,15 @@ struct stm32wb_mbox_shared_buffer_s aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_cs_buffer[STM32WB_MBOX_CS_BUF_SIZE]; + aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif - aligned_data(4) uint8_t evtpool_buffer[STM32WB_MBOX_RX_BUF_SIZE]; - aligned_data(4) uint8_t sys_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t sys_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; + aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) uint8_t ble_spare_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_cmd_buffer[STM32WB_MBOX_CMDPKT_BUF_SIZE]; - aligned_data(4) uint8_t ble_acl_buffer[STM32WB_MBOX_ACLPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; + aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; #endif }; @@ -205,7 +205,7 @@ static struct work_s g_tx_cmd_work; static stm32wb_mbox_list_t g_rx_evt_queue; static stm32wb_mbox_list_t g_tx_evtfree_queue; static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] - [STM32WB_MBOX_CMDPKT_BUF_SIZE]; + [STM32_MBOX_CMDPKT_BUF_SIZE]; static stm32wb_mbox_list_t g_free_buffers_pool; static struct stm32wb_mbox_channel_s g_syscmd_channel; @@ -235,24 +235,24 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_SYSEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_SYSEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } #ifdef CONFIG_STM32WB_BLE /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32WB_MBOX_BLEEVT_CHANNEL)) + if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, &g_rx_evt_queue); - clrmask |= IPCC_C1SCR_CLR_BIT(STM32WB_MBOX_BLEEVT_CHANNEL); + clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); } #endif @@ -265,7 +265,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Clear active statuses */ - putreg32(clrmask, STM32WB_IPCC_C1SCR); + putreg32(clrmask, STM32_IPCC_C1SCR); } /**************************************************************************** @@ -279,7 +279,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { - uint32_t c1mr = getreg32(STM32WB_IPCC_C1MR); + uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; /* TXF interrupt can be triggered by not masked channels and active status @@ -287,12 +287,12 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) * channels and rise other C1MR bits to highlight needed channels. */ - txfsrc = ~(c1mr | (getreg32(STM32WB_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) + txfsrc = ~(c1mr | (getreg32(STM32_IPCC_C1TOC2SR) << IPCC_C1MR_FM_SHIFT)) & IPCC_C1MR_FM_MASK; /* Check if the release channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all released events (if any) into transmission mailbox */ @@ -303,17 +303,17 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } /* Check other channels, except the release channel */ - if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (txfsrc & ~IPCC_C1MR_FM_BIT(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Check if the system channel triggered the interrupt */ - if (txfsrc & IPCC_C1MR_FM_BIT(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (txfsrc & IPCC_C1MR_FM_BIT(STM32_MBOX_SYSCMD_CHANNEL)) { /* System channel works in 'half-duplex' mode and acks * immediately on each command before TXF, so it needs @@ -333,7 +333,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) /* Mask triggered channels */ - putreg32(c1mr | txfsrc, STM32WB_IPCC_C1MR); + putreg32(c1mr | txfsrc, STM32_IPCC_C1MR); } /**************************************************************************** @@ -350,7 +350,7 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_SYSCMD_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ @@ -364,12 +364,12 @@ static void stm32wb_mbox_txworker(void *arg) } #ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLECMD_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_BLEACL_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { handled |= stm32wb_mbox_txnext(&g_bleacl_channel); } @@ -467,7 +467,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, stm32wb_ipcc_settxactive(chan->ch_num); if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || - chan->ch_num == STM32WB_MBOX_SYSCMD_CHANNEL) + chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get * notified when channel gets ready to process a next one. @@ -512,7 +512,7 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) { chan->cmd_buf->type = pkt_buf->type; - if (chan->ch_num == STM32WB_MBOX_BLEACL_CHANNEL) + if (chan->ch_num == STM32_MBOX_BLEACL_CHANNEL) { memcpy(&chan->cmd_buf->acl_hdr, &pkt_buf->acl_hdr, sizeof(pkt_buf->acl_hdr) + pkt_buf->acl_hdr.len); @@ -562,7 +562,7 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ @@ -571,13 +571,13 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Start transmission */ - stm32wb_ipcc_settxactive(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32WB_MBOX_EVT_RELEASE_CHANNEL); + stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); @@ -600,7 +600,7 @@ static void stm32wb_mbox_acksyscmd(void) */ evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); - evt->type = STM32WB_MBOX_SYSACK; + evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); } @@ -662,7 +662,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) /* Init system channel data */ - g_syscmd_channel.ch_num = STM32WB_MBOX_SYSCMD_CHANNEL; + g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.sys_cmd_buffer; stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); @@ -670,14 +670,14 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) #ifdef CONFIG_STM32WB_BLE /* Init BLE command channel data */ - g_blecmd_channel.ch_num = STM32WB_MBOX_BLECMD_CHANNEL; + g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_cmd_buffer; stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ - g_bleacl_channel.ch_num = STM32WB_MBOX_BLEACL_CHANNEL; + g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) stm32wb_mbox_shared.ble_acl_buffer; stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); @@ -715,21 +715,21 @@ void stm32wb_mboxenable(void) /* Setup RXO and TXF interrupts */ - irq_attach(STM32WB_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCRX); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32WB_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); - up_enable_irq(STM32WB_IRQ_IPCCTX); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + up_enable_irq(STM32_IRQ_IPCCTX); - regval = getreg32(STM32WB_IPCC_C1CR); + regval = getreg32(STM32_IPCC_C1CR); regval |= IPCC_C1CR_RXOIE | IPCC_C1CR_TXFIE; - putreg32(regval, STM32WB_IPCC_C1CR); + putreg32(regval, STM32_IPCC_C1CR); /* Unmask system channel RXO interrupt. Once CPU2 started we expect * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_SYSEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ @@ -747,7 +747,7 @@ void stm32wb_mboxenable(void) int stm32wb_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32WB_MBOX_SYSCMD, + return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } @@ -763,7 +763,7 @@ int stm32wb_mbox_syscmd(void *data, size_t len) int stm32wb_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32WB_MBOX_HCICMD, + return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } @@ -778,7 +778,7 @@ int stm32wb_mbox_blecmd(void *data, size_t len) int stm32wb_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32WB_MBOX_HCIACL, + return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } @@ -800,7 +800,7 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Prepare command data */ - cmd->opcode = STM32WB_SHCI_BLE_INIT; + cmd->opcode = STM32_SHCI_BLE_INIT; cmd->param_len = sizeof(*cmd); memcpy(cmd + 1, params, sizeof(*params)); @@ -810,6 +810,6 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32WB_MBOX_BLEEVT_CHANNEL); + stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } #endif /* CONFIG_STM32WB_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index f67821fa5c5..6d5f9cc7932 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -42,34 +42,34 @@ /* Mailbox channels */ -#define STM32WB_MBOX_BLEEVT_CHANNEL 1 -#define STM32WB_MBOX_BLECMD_CHANNEL 1 -#define STM32WB_MBOX_SYSEVT_CHANNEL 2 -#define STM32WB_MBOX_SYSCMD_CHANNEL 2 -#define STM32WB_MBOX_EVT_RELEASE_CHANNEL 4 -#define STM32WB_MBOX_BLEACL_CHANNEL 6 +#define STM32_MBOX_BLEEVT_CHANNEL 1 +#define STM32_MBOX_BLECMD_CHANNEL 1 +#define STM32_MBOX_SYSEVT_CHANNEL 2 +#define STM32_MBOX_SYSCMD_CHANNEL 2 +#define STM32_MBOX_EVT_RELEASE_CHANNEL 4 +#define STM32_MBOX_BLEACL_CHANNEL 6 /* Mailbox packet types */ -#define STM32WB_MBOX_HCICMD 0x01 -#define STM32WB_MBOX_HCIACL 0x02 -#define STM32WB_MBOX_HCIEVT 0x04 -#define STM32WB_MBOX_SYSCMD 0x10 -#define STM32WB_MBOX_SYSEVT 0x12 -#define STM32WB_MBOX_SYSACK 0xe0 +#define STM32_MBOX_HCICMD 0x01 +#define STM32_MBOX_HCIACL 0x02 +#define STM32_MBOX_HCIEVT 0x04 +#define STM32_MBOX_SYSCMD 0x10 +#define STM32_MBOX_SYSEVT 0x12 +#define STM32_MBOX_SYSACK 0xe0 /* Mailbox configuration helpers */ -#define STM32WB_MBOX_BLE_ATT_DEFAULT_MTU 23 -#define STM32WB_MBOX_C2_MEM_BLOCK_SZ 32 +#define STM32_MBOX_BLE_ATT_DEFAULT_MTU 23 +#define STM32_MBOX_C2_MEM_BLOCK_SZ 32 #define DIV_UP(a, b) (((a) + (b) - 1) / (b)) -#define STM32WB_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ - (DIV_UP((max_mtu), STM32WB_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) +#define STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(max_mtu) \ + (DIV_UP((max_mtu), STM32_MBOX_BLE_ATT_DEFAULT_MTU - 5) * 2) -#define STM32WB_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ - ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32WB_MBOX_C2_MEM_BLOCK_SZ) + 2)) +#define STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(max_mtu, max_conn, pw) \ + ((pw) + ((max_conn) + 1) * (DIV_UP((max_mtu) + 4, STM32_MBOX_C2_MEM_BLOCK_SZ) + 2)) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 68536c3cfcb..442dee86f15 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -37,87 +37,87 @@ /* SHCI event types *********************************************************/ -#define STM32WB_SHCI_ASYNC_EVT 0xff +#define STM32_SHCI_ASYNC_EVT 0xff /* SHCI async event subtypes */ -#define STM32WB_SHCI_ASYNC_EVT_C2RDY 0x9200 +#define STM32_SHCI_ASYNC_EVT_C2RDY 0x9200 /* SHCI system command acknowledgement events */ -#define STM32WB_SHCI_ACK_EVT_C2RDY 0x05 +#define STM32_SHCI_ACK_EVT_C2RDY 0x05 /* SHCI command opcodes *****************************************************/ -#define STM32WB_SHCI_OGF 0x3f -#define STM32WB_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) +#define STM32_SHCI_OGF 0x3f +#define STM32_SHCI_OP(ogf, ocf) (((ogf) << 10) | (ocf)) -#define STM32WB_SHCI_FUS_GET_STATE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x52) -#define STM32WB_SHCI_FUS_FW_UPGRADE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x54) -#define STM32WB_SHCI_FUS_FW_DELETE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x55) -#define STM32WB_SHCI_FUS_UPDATE_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x56) -#define STM32WB_SHCI_FUS_LOCK_AUTH_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x57) -#define STM32WB_SHCI_FUS_STORE_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x58) -#define STM32WB_SHCI_FUS_LOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x59) -#define STM32WB_SHCI_FUS_START_WS STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5a) -#define STM32WB_SHCI_FUS_LOCK_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5d) -#define STM32WB_SHCI_FUS_UNLOAD_USR_KEY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5e) -#define STM32WB_SHCI_FUS_ANTIROLLBACK STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x5f) -#define STM32WB_SHCI_BLE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x66) -#define STM32WB_SHCI_THREAD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x67) -#define STM32WB_SHCI_DEBUG_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x68) -#define STM32WB_SHCI_FLASH_ERASE_ACTIVITY STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x69) -#define STM32WB_SHCI_CONCURRENT_SET_MODE STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6a) -#define STM32WB_SHCI_FLASH_STORE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6b) -#define STM32WB_SHCI_FLASH_ERASE_DATA STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6c) -#define STM32WB_SHCI_RADIO_ALLOW_LOW_POWER STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6d) -#define STM32WB_SHCI_MAC_802154_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6e) -#define STM32WB_SHCI_REINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x6f) -#define STM32WB_SHCI_ZIGBEE_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x70) -#define STM32WB_SHCI_LLD_TESTS_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x71) -#define STM32WB_SHCI_EXTPA_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x72) -#define STM32WB_SHCI_SET_FLASH_CONTROL STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x73) -#define STM32WB_SHCI_BLE_LLD_INIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x74) -#define STM32WB_SHCI_CONFIG STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x75) -#define STM32WB_SHCI_GET_NEXT_BLE_EVT_TIME STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x76) -#define STM32WB_SHCI_ENABLE_NEXT_802154_NF STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x77) -#define STM32WB_SHCI_802_15_4_DEINIT STM32WB_SHCI_OP(STM32WB_SHCI_OGF, 0x78) +#define STM32_SHCI_FUS_GET_STATE STM32_SHCI_OP(STM32_SHCI_OGF, 0x52) +#define STM32_SHCI_FUS_FW_UPGRADE STM32_SHCI_OP(STM32_SHCI_OGF, 0x54) +#define STM32_SHCI_FUS_FW_DELETE STM32_SHCI_OP(STM32_SHCI_OGF, 0x55) +#define STM32_SHCI_FUS_UPDATE_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x56) +#define STM32_SHCI_FUS_LOCK_AUTH_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x57) +#define STM32_SHCI_FUS_STORE_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x58) +#define STM32_SHCI_FUS_LOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x59) +#define STM32_SHCI_FUS_START_WS STM32_SHCI_OP(STM32_SHCI_OGF, 0x5a) +#define STM32_SHCI_FUS_LOCK_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5d) +#define STM32_SHCI_FUS_UNLOAD_USR_KEY STM32_SHCI_OP(STM32_SHCI_OGF, 0x5e) +#define STM32_SHCI_FUS_ANTIROLLBACK STM32_SHCI_OP(STM32_SHCI_OGF, 0x5f) +#define STM32_SHCI_BLE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x66) +#define STM32_SHCI_THREAD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x67) +#define STM32_SHCI_DEBUG_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x68) +#define STM32_SHCI_FLASH_ERASE_ACTIVITY STM32_SHCI_OP(STM32_SHCI_OGF, 0x69) +#define STM32_SHCI_CONCURRENT_SET_MODE STM32_SHCI_OP(STM32_SHCI_OGF, 0x6a) +#define STM32_SHCI_FLASH_STORE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6b) +#define STM32_SHCI_FLASH_ERASE_DATA STM32_SHCI_OP(STM32_SHCI_OGF, 0x6c) +#define STM32_SHCI_RADIO_ALLOW_LOW_POWER STM32_SHCI_OP(STM32_SHCI_OGF, 0x6d) +#define STM32_SHCI_MAC_802154_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6e) +#define STM32_SHCI_REINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x6f) +#define STM32_SHCI_ZIGBEE_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x70) +#define STM32_SHCI_LLD_TESTS_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x71) +#define STM32_SHCI_EXTPA_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x72) +#define STM32_SHCI_SET_FLASH_CONTROL STM32_SHCI_OP(STM32_SHCI_OGF, 0x73) +#define STM32_SHCI_BLE_LLD_INIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x74) +#define STM32_SHCI_CONFIG STM32_SHCI_OP(STM32_SHCI_OGF, 0x75) +#define STM32_SHCI_GET_NEXT_BLE_EVT_TIME STM32_SHCI_OP(STM32_SHCI_OGF, 0x76) +#define STM32_SHCI_ENABLE_NEXT_802154_NF STM32_SHCI_OP(STM32_SHCI_OGF, 0x77) +#define STM32_SHCI_802_15_4_DEINIT STM32_SHCI_OP(STM32_SHCI_OGF, 0x78) /* Command params bitfield definitions **************************************/ /* BLE init command option flags */ -#define STM32WB_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ -# define STM32WB_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ +#define STM32_SHCI_BLE_INIT_OPT_STACK_MASK (1 << 0) /* Bit 0: BLE stack select */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST (0 << 0) /* 0x0: Link Layer and Host */ +# define STM32_SHCI_BLE_INIT_OPT_STACK_LL (1 << 0) /* 0x1: Link Layer only */ -#define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ +#define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_MASK (1 << 1) /* Bit 1: Service Changed characteristic */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED (0 << 1) /* 0x0: Characteristic enabled */ +# define STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED (1 << 1) /* 0x1: Characteristic disabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ -# define STM32WB_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ +#define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_MASK (1 << 2) /* Bit 2: Device Name mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW (0 << 2) /* 0x0: Read-Write mode */ +# define STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO (1 << 2) /* 0x1: Read-Only mode */ -#define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ -# define STM32WB_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ +#define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_MASK (1 << 4) /* Bit 4: Channel selection algorithm 2 enabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED (0 << 4) /* 0x0: Algorithm 2 disabled */ +# define STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED (1 << 4) /* 0x1: Algorithm 2 enabled */ -#define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ -# define STM32WB_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ +#define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_MASK (1 << 7) /* Bit 7: Power class */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 (0 << 7) /* 0x0: Power Class 2-3 */ +# define STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 (1 << 7) /* 0x1: Power Class 1 */ /* BLE init command rx_model_config flags */ -#define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ -# define STM32WB_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ +#define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_MASK (1 << 0) /* Bit 0: AGC RSSI model */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY (0 << 0) /* 0x0: AGC RSSI Legacy */ +# define STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED (1 << 0) /* 0x1: AGC RSSI Improved */ /**************************************************************************** * Public Types ****************************************************************************/ -/* STM32WB_SHCI_BLE_INIT command params */ +/* STM32_SHCI_BLE_INIT command params */ begin_packed_struct struct stm32wb_shci_ble_init_cfg_s { diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index ed0d899531c..bd8ffa00d19 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -86,10 +86,10 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * Disable the TC now and disable any further interrupts. */ - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); /* The timer is no longer running */ @@ -200,7 +200,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, return -EBUSY; } - STM32WB_TIM_SETCLOCK(oneshot->tch, frequency); + STM32_TIM_SETCLOCK(oneshot->tch, frequency); /* Initialize the remaining fields in the state structure. */ @@ -301,19 +301,19 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32WB_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); /* Set timer period */ oneshot->period = (uint32_t)period; - STM32WB_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); /* Start the counter */ - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_PULSE); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); - STM32WB_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); - STM32WB_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(oneshot->tch, GTIM_SR_UIF); + STM32_TIM_ENABLEINT(oneshot->tch, GTIM_DIER_UIE); /* Enable interrupts. We should get the callback when the interrupt * occurs. @@ -388,14 +388,14 @@ int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, tmrinfo("Cancelling...\n"); - count = STM32WB_TIM_GETCOUNTER(oneshot->tch); + count = STM32_TIM_GETCOUNTER(oneshot->tch); period = oneshot->period; /* Now we can disable the interrupt and stop the timer. */ - STM32WB_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(oneshot->tch, NULL, NULL, 0); - STM32WB_TIM_SETMODE(oneshot->tch, STM32WB_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(oneshot->tch, GTIM_DIER_UIE); + STM32_TIM_SETISR(oneshot->tch, NULL, NULL, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); oneshot->running = false; oneshot->handler = NULL; diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index c81179f8c62..fa601b27961 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -60,34 +60,34 @@ int stm32wb_pmlpr(void) /* Enable MSI clock */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSION; /* Set MSI clock to 2 MHz */ regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_2M; /* 2 MHz */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Select MSI clock as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_MSI; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the MSI source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_MSI) { } /* Enable Low-Power Run */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval |= PWR_CR1_LPR; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index d1fd88ac03c..657f4bf6779 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -63,15 +63,15 @@ int stm32wb_pmstandby(void) regval = PWR_SCR_CWUF1 | PWR_SCR_CWUF2 | PWR_SCR_CWUF3 | PWR_SCR_CWUF4 | PWR_SCR_CWUF5; - putreg32(regval, STM32WB_PWR_SCR); + putreg32(regval, STM32_PWR_SCR); /* Select Standby mode */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STANDBY; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set SLEEPDEEP bit of Cortex System Control Register */ diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 683af0cd07a..1cbd80f0e23 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -98,7 +98,7 @@ int stm32wb_pmstop(bool lpds) * register CR1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; /* Select Stop 1 mode with low-power regulator if so requested */ @@ -108,7 +108,7 @@ int stm32wb_pmstop(bool lpds) regval |= PWR_CR1_LPMS_STOP1; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } @@ -135,10 +135,10 @@ int stm32wb_pmstop2(void) /* Select Stop 2 mode in power control register 1. */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_LPMS_MASK; regval |= PWR_CR1_LPMS_STOP2; - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); return do_stop(); } diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index c13ca0b1480..62fe1b7be84 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -41,18 +41,18 @@ static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WB_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WB_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WB_PWR_BASE + (uint32_t)offset, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -82,7 +82,7 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR1_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32WB_PWR_CR1_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -132,7 +132,7 @@ bool stm32wb_pwr_enableusv(bool set) /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32WB_PWR_CR2_OFFSET); + regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32WB_PWR_CR2_OFFSET, regval); + stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; @@ -183,7 +183,7 @@ void stm32_pwr_setvos(int vos) return; } - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; if (vos == 1) @@ -195,5 +195,5 @@ void stm32_pwr_setvos(int vos) regval |= PWR_CR1_VOS_RANGE2; } - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 9fd6f17b2a4..e731a9448e5 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,9 +61,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32WB_USE_CLK48) -# if STM32WB_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 -# define STM32WB_USE_HSI48 +#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32_USE_CLK48) +# if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 +# define STM32_USE_HSI48 # endif #endif @@ -89,47 +89,47 @@ static inline void rcc_reset(void) /* Enable the Multi-Speed Internal clock (MSI) @ 4MHz */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; regval |= RCC_CR_MSIRANGE_4M | RCC_CR_MSION; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset CFGR register */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= RCC_CFGR_RESET_MASK; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~(RCC_CR_PLLON | RCC_CR_PLLSAI1ON | RCC_CR_CSSON | RCC_CR_HSEON | RCC_CR_HSION | RCC_CR_MSIPLLEN); - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Reset LSI1 and LSI2 bits */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~(RCC_CSR_LSI1ON | RCC_CSR_LSI2ON); - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); /* Reset HSI48ON bit */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~(RCC_CRRCR_HSI48ON); - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Reset PLLCFGR register */ - putreg32(RCC_PLLCFG_RESET, STM32WB_RCC_PLLCFG); + putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG); /* Reset PLLSAI1CFG register */ - putreg32(RCC_PLLSAI1CFG_RESET, STM32WB_RCC_PLLSAI1CFG); + putreg32(RCC_PLLSAI1CFG_RESET, STM32_RCC_PLLSAI1CFG); /* Disable all interrupts */ - putreg32(0x00000000, STM32WB_RCC_CIER); + putreg32(0x00000000, STM32_RCC_CIER); } /**************************************************************************** @@ -148,7 +148,7 @@ static inline void rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32WB_DMA1 /* DMA 1 clock enable */ @@ -180,7 +180,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_TSCEN; #endif - putreg32(regval, STM32WB_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -199,7 +199,7 @@ static inline void rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIO ports A-E, H */ @@ -224,7 +224,7 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR_AES1EN; #endif - putreg32(regval, STM32WB_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -243,7 +243,7 @@ static inline void rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WB_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32WB_QSPI /* QuadSPI module clock enable */ @@ -287,7 +287,7 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_FLASHEN; #endif - putreg32(regval, STM32WB_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -306,7 +306,7 @@ static inline void rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WB_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32WB_TIM2 /* TIM2 clock enable */ @@ -350,8 +350,8 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef STM32WB_USE_HSI48 - if (STM32WB_HSI48_SYNCSRC != SYNCSRC_NONE) +#ifdef STM32_USE_HSI48 + if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE) { /* Clock Recovery System clock enable */ @@ -371,11 +371,11 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WB_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32WB_LPUART1 /* Low power uart clock enable */ @@ -389,7 +389,7 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM2EN; #endif - putreg32(regval, STM32WB_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -408,7 +408,7 @@ static inline void rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WB_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #ifdef CONFIG_STM32WB_TIM1 /* TIM1 clock enable */ @@ -446,7 +446,7 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SAI1EN; #endif - putreg32(regval, STM32WB_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -466,9 +466,9 @@ static inline void rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WB_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WB_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -481,11 +481,11 @@ static inline void rcc_enableccip(void) regval &= ~RCC_CCIPR_I2C3SEL_MASK; regval |= RCC_CCIPR_I2C3SEL_HSI16; #endif -#endif /* STM32WB_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WB_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WB_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ @@ -500,7 +500,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif - putreg32(regval, STM32WB_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); } /**************************************************************************** @@ -519,12 +519,12 @@ static void stm32wb_stdclockconfig(void) uint32_t regval; volatile int32_t timeout; -#if defined(STM32WB_BOARD_USEHSI) || defined(STM32WB_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready (or until a timeout elapsed) */ @@ -532,7 +532,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -541,17 +541,17 @@ static void stm32wb_stdclockconfig(void) } #endif -#if defined(STM32WB_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready (or until a timeout elapsed) */ for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--) { - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); if ((regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { @@ -563,10 +563,10 @@ static void stm32wb_stdclockconfig(void) /* Setting MSIRANGE */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval &= ~RCC_CR_MSIRANGE_MASK; - regval |= (STM32WB_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WB_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready (or until a timeout elapsed) */ @@ -574,7 +574,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -582,12 +582,12 @@ static void stm32wb_stdclockconfig(void) } } -#elif defined(STM32WB_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready (or until a timeout elapsed) */ @@ -595,7 +595,7 @@ static void stm32wb_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WB_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out with timeout > 0 */ @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32WB_BOARD_USEHSI, STM32WB_BOARD_USEMSI, STM32WB_BOARD_USEHSE defined +# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -617,144 +617,144 @@ static void stm32wb_stdclockconfig(void) { /* Setup regulator voltage according to clock frequency */ - regval = getreg32(STM32WB_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; -#if STM32WB_SYSCLK_FREQUENCY > 16000000 || \ +#if STM32_SYSCLK_FREQUENCY > 16000000 || \ (defined(BOARD_MAX_PLL_FREQUENCY) && BOARD_MAX_PLL_FREQUENCY > 16000000) regval |= PWR_CR1_VOS_RANGE1; #else regval |= PWR_CR1_VOS_RANGE2; #endif - putreg32(regval, STM32WB_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WB_RCC_CFGR_HPRE; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the CPU2 HCLK2 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_C2HPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_C2HPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_C2HPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the HCLK4 source/divider */ - regval = getreg32(STM32WB_RCC_EXTCFGR); + regval = getreg32(STM32_RCC_EXTCFGR); regval &= ~RCC_EXTCFGR_SHDHPRE_MASK; - regval |= STM32WB_RCC_EXTCFGR_SHDHPRE; - putreg32(regval, STM32WB_RCC_EXTCFGR); + regval |= STM32_RCC_EXTCFGR_SHDHPRE; + putreg32(regval, STM32_RCC_EXTCFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WB_RCC_CFGR_PPRE1; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WB_RCC_CFGR_PPRE2; - putreg32(regval, STM32WB_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Configure Main PLL */ - regval = getreg32(STM32WB_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); regval &= ~(RCC_PLLCFG_PLLM_MASK | RCC_PLLCFG_PLLN_MASK); - regval |= (STM32WB_PLLCFG_PLLM | STM32WB_PLLCFG_PLLN); + regval |= (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN); /* Set the PLL dividers and multipliers to configure the main PLL */ regval &= ~(RCC_PLLCFG_PLLPEN | RCC_PLLCFG_PLLQEN | RCC_PLLCFG_PLLREN); -#ifdef STM32WB_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval &= ~RCC_PLLCFG_PLLP_MASK; - regval |= (RCC_PLLCFG_PLLPEN | STM32WB_PLLCFG_PLLP); + regval |= (RCC_PLLCFG_PLLPEN | STM32_PLLCFG_PLLP); #endif -#ifdef STM32WB_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval &= ~RCC_PLLCFG_PLLQ_MASK; - regval |= (RCC_PLLCFG_PLLQEN | STM32WB_PLLCFG_PLLQ); + regval |= (RCC_PLLCFG_PLLQEN | STM32_PLLCFG_PLLQ); #endif -#ifdef STM32WB_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval &= ~RCC_PLLCFG_PLLR_MASK; - regval |= (RCC_PLLCFG_PLLREN | STM32WB_PLLCFG_PLLR); + regval |= (RCC_PLLCFG_PLLREN | STM32_PLLCFG_PLLR); #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WB_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ regval &= ~RCC_PLLCFG_PLLSRC_MASK; -#ifdef STM32WB_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WB_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WB_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WB_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } #ifdef CONFIG_STM32WB_SAI1PLL /* Configure SAI1 PLL */ - regval = getreg32(STM32WB_RCC_PLLSAI1CFG); + regval = getreg32(STM32_RCC_PLLSAI1CFG); regval &= ~RCC_PLLSAI1CFG_PLLN_MASK; - regval |= STM32WB_PLLSAI1CFG_PLLN; + regval |= STM32_PLLSAI1CFG_PLLN; /* Set the PLL dividers and multipliers to configure the SAI1 PLL */ regval &= ~(RCC_PLLSAI1CFG_PLLPEN | RCC_PLLSAI1CFG_PLLQEN | RCC_PLLSAI1CFG_PLLREN); -#ifdef STM32WB_PLLSAI1CFG_PLLP_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLP_MASK; - regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32WB_PLLSAI1CFG_PLLP); + regval |= (RCC_PLLSAI1CFG_PLLPEN | STM32_PLLSAI1CFG_PLLP); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLQ_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLQ_MASK; - regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32WB_PLLSAI1CFG_PLLQ); + regval |= (RCC_PLLSAI1CFG_PLLQEN | STM32_PLLSAI1CFG_PLLQ); #endif -#ifdef STM32WB_PLLSAI1CFG_PLLR_ENABLED +#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED regval &= ~RCC_PLLSAI1CFG_PLLR_MASK; - regval |= (RCC_PLLSAI1CFG_PLLREN | STM32WB_PLLSAI1CFG_PLLR); + regval |= (RCC_PLLSAI1CFG_PLLREN | STM32_PLLSAI1CFG_PLLR); #endif - putreg32(regval, STM32WB_RCC_PLLSAI1CFG); + putreg32(regval, STM32_RCC_PLLSAI1CFG); /* Enable the SAI1 PLL */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLSAI1ON; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WB_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0) { } #endif /* Configure FLASH wait states */ - regval = getreg32(STM32WB_FLASH_ACR); + regval = getreg32(STM32_FLASH_ACR); regval &= ~FLASH_ACR_LATENCY_MASK; #ifdef BOARD_FLASH_WAITSTATES regval |= FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); @@ -770,18 +770,18 @@ static void stm32wb_stdclockconfig(void) regval &= ~FLASH_ACR_PRFTEN; #endif regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); - putreg32(regval, STM32WB_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WB_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } @@ -792,7 +792,7 @@ static void stm32wb_stdclockconfig(void) stm32wb_rcc_enable_lsi(); #endif -#if defined(STM32WB_USE_LSE) +#if defined(STM32_USE_LSE) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -807,25 +807,25 @@ static void stm32wb_stdclockconfig(void) stm32wb_rcc_enable_lse(); -# if defined(STM32WB_BOARD_USEMSI) +# if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ - regval = getreg32(STM32WB_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_MSIPLLEN; - putreg32(regval, STM32WB_RCC_CR); + putreg32(regval, STM32_RCC_CR); # endif -#endif /* STM32WB_USE_LSE */ +#endif /* STM32_USE_LSE */ /* Select CPU2 RF wakeup clock source, no clock if not set */ - regval = getreg32(STM32WB_RCC_CSR); + regval = getreg32(STM32_RCC_CSR); regval &= ~RCC_CSR_RFWKPSEL_MASK; -#if defined(STM32WB_BOARD_RFWKP_USELSE) +#if defined(STM32_BOARD_RFWKP_USELSE) regval |= RCC_CSR_RFWKPSEL_LSE; -#elif defined(STM32WB_BOARD_RFWKP_USEHSE) +#elif defined(STM32_BOARD_RFWKP_USEHSE) regval |= RCC_CSR_RFWKPSEL_HSE; #endif - putreg32(regval, STM32WB_RCC_CSR); + putreg32(regval, STM32_RCC_CSR); } } #endif @@ -843,10 +843,10 @@ static inline void rcc_enableperipherals(void) rcc_enableapb1(); rcc_enableapb2(); -#ifdef STM32WB_USE_HSI48 +#ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32WB_HSI48_SYNCSRC); + stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -881,14 +881,14 @@ static inline void rcc_resetbkp(void) init_stat = stm32wb_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WB_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WB_RTC_BKPR(i)); + bkregs[i] = getreg32(STM32_RTC_BKPR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -901,16 +901,16 @@ static inline void rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WB_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG != STM32WB_RTC_BKPR(i)) + if (RTC_MAGIC_REG != STM32_RTC_BKPR(i)) { - putreg32(bkregs[i], STM32WB_RTC_BKPR(i)); + putreg32(bkregs[i], STM32_RTC_BKPR(i)); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index c770e462bd1..e6e675a3534 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -88,7 +88,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; - regval = getreg32(STM32WB_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); /* Set MCO source */ @@ -99,7 +99,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) regval &= ~(RCC_CFGR_MCOPRE_MASK); regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32WB_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index e8d12b2d352..abdb78b4b44 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -77,13 +77,13 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * enabled. */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval |= RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Wait for the HSI48 clock to stabilize */ - while ((getreg32(STM32WB_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); + while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0); /* Return if no synchronization */ @@ -97,7 +97,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * clock or the USB SOF signal. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; switch (syncsrc) @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) break; } - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); /* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic * hardware adjustment of TRIM bits according to the measured frequency @@ -124,9 +124,9 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * frequency error counter and SYNC events. */ - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } /**************************************************************************** @@ -149,18 +149,18 @@ void stm32wb_rcc_disable_hsi48(void) /* Disable the HSI48 clock */ - regval = getreg32(STM32WB_RCC_CRRCR); + regval = getreg32(STM32_RCC_CRRCR); regval &= ~RCC_CRRCR_HSI48ON; - putreg32(regval, STM32WB_RCC_CRRCR); + putreg32(regval, STM32_RCC_CRRCR); /* Set other registers to the default settings. */ - regval = getreg32(STM32WB_CRS_CFGR); + regval = getreg32(STM32_CRS_CFGR); regval &= ~CRS_CFGR_SYNCSRC_MASK; regval |= CRS_CFGR_SYNCSRC_USBSOF; - putreg32(regval, STM32WB_CRS_CFGR); + putreg32(regval, STM32_CRS_CFGR); - regval = getreg32(STM32WB_CRS_CR); + regval = getreg32(STM32_CRS_CR); regval &= ~CRS_CR_AUTOTRIMEN; - putreg32(regval, STM32WB_CRS_CR); + putreg32(regval, STM32_CRS_CR); } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 4927de6dec4..e032a1a1c6d 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -68,7 +68,7 @@ void stm32wb_rcc_enable_lse(void) /* Check if the External Low-Speed (LSE) oscillator is already running. */ - regval = getreg32(STM32WB_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) != (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) @@ -94,11 +94,11 @@ void stm32wb_rcc_enable_lse(void) RCC_BDCR_LSEDRV_SHIFT; #endif - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready */ - while (((regval = getreg32(STM32WB_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) + while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { stm32wb_waste(); } @@ -116,7 +116,7 @@ void stm32wb_rcc_enable_lse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WB_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 32597118fbf..9fa23cfc73a 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -47,11 +47,11 @@ void stm32wb_rcc_enable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, 0, RCC_CSR_LSI1ON); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSI1ON); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WB_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSI1RDY) == 0); } /**************************************************************************** @@ -68,7 +68,7 @@ void stm32wb_rcc_disable_lsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WB_RCC_CSR, RCC_CSR_LSI1ON, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSI1ON, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index f33974fdb4e..78c793ef038 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -139,23 +139,23 @@ static inline void rtc_enable_alarm(void); static void rtc_dumpregs(const char *msg) { rtcinfo("%s:\n", msg); - rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TR)); - rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_DR)); - rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CR)); - rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ISR)); - rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32WB_RTC_PRER)); - rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_WUTR)); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); - rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_SHIFTR)); - rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSTR)); - rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSDR)); - rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TSSSR)); - rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_CALR)); - rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_TAMPCR)); - rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMASSR)); - rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBSSR)); - rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_OR)); + rtcinfo(" TR: %08" PRIx32 "\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08" PRIx32 "\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08" PRIx32 "\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08" PRIx32 "\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08" PRIx32 "\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08" PRIx32 "\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08" PRIx32 "\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08" PRIx32 "\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAMPCR: %08" PRIx32 "\n", getreg32(STM32_RTC_TAMPCR)); + rtcinfo("ALRMASSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo(" OR: %08" PRIx32 "\n", getreg32(STM32_RTC_OR)); rtcinfo("MAGICREG: %08" PRIx32 "\n", getreg32(RTC_MAGIC_REG)); } #else @@ -211,8 +211,8 @@ static void rtc_wprunlock(void) * Writing a wrong key re-activates the write protection. */ - putreg32(RTC_WPR_KEY1, STM32WB_RTC_WPR); - putreg32(RTC_WPR_KEY2, STM32WB_RTC_WPR); + putreg32(RTC_WPR_KEY1, STM32_RTC_WPR); + putreg32(RTC_WPR_KEY2, STM32_RTC_WPR); } /**************************************************************************** @@ -233,7 +233,7 @@ static inline void rtc_wprlock(void) { /* Writing any wrong key re-activates the write protection. */ - putreg32(0xff, STM32WB_RTC_WPR); + putreg32(0xff, STM32_RTC_WPR); /* Disable write access to the backup domain. */ @@ -263,16 +263,16 @@ static int rtc_synchwait(void) /* Clear Registers synchronization flag (RSF) */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_RSF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Now wait the registers to become synchronised */ ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_RSF) != 0) { /* Synchronized */ @@ -307,21 +307,21 @@ static int rtc_enterinit(void) /* Check if the Initialization mode is already set */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); ret = OK; if ((regval & RTC_ISR_INITF) == 0) { /* Set the Initialization mode */ - putreg32(RTC_ISR_INIT, STM32WB_RTC_ISR); + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); /* Wait until the RTC is in the INIT state (or a timeout occurs) */ ret = -ETIMEDOUT; for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_INITF) != 0) { ret = OK; @@ -351,9 +351,9 @@ static void rtc_exitinit(void) { uint32_t regval; - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_INIT); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); } /**************************************************************************** @@ -425,13 +425,13 @@ static void rtc_resume(void) /* Clear the RTC alarm flags */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); /* Clear the EXTI Line 17 Pending bit (Connected internally to RTC Alarm) */ - putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32WB_EXTI_PR1); + putreg32(EXTI_PR1_PIF(EXTI_EVT_RTCALARM), STM32_EXTI_PR1); #endif } @@ -469,10 +469,10 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* Check for EXTI from Alarm A or B and handle according */ - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRAIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRAF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMA]; @@ -491,17 +491,17 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #if CONFIG_RTC_NALARMS > 1 - cr = getreg32(STM32WB_RTC_CR); + cr = getreg32(STM32_RTC_CR); if ((cr & RTC_CR_ALRBIE) != 0) { - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); if ((isr & RTC_ISR_ALRBF) != 0) { cbinfo = &g_alarmcb[RTC_ALARMB]; @@ -520,9 +520,9 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, /* note, bits 8-13 do /not/ require the write enable procedure */ - isr = getreg32(STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR); isr &= ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + putreg32(isr, STM32_RTC_ISR); } } #endif @@ -565,7 +565,7 @@ static int rtchw_check_alrawf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRAWF) != 0) { ret = OK; @@ -591,7 +591,7 @@ static int rtchw_check_alrbwf(void) for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_ALRBWF) != 0) { ret = OK; @@ -630,12 +630,12 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Disable RTC alarm A & Interrupt A */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); /* Ensure Alarm A flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm A to be writable */ @@ -647,13 +647,13 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm A register */ - putreg32(alarmreg, STM32WB_RTC_ALRMAR); - putreg32(0, STM32WB_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMAR)); + putreg32(alarmreg, STM32_RTC_ALRMAR); + putreg32(0, STM32_RTC_ALRMASSR); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); errout_with_wprunlock: rtc_wprlock(); @@ -673,12 +673,12 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Disable RTC alarm B & Interrupt B */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); /* Ensure Alarm B flag reset; this is edge triggered */ - isr = getreg32(STM32WB_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32WB_RTC_ISR); + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_ISR); /* Wait for Alarm B to be writable */ @@ -690,13 +690,13 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) /* Set the RTC Alarm B register */ - putreg32(alarmreg, STM32WB_RTC_ALRMBR); - putreg32(0, STM32WB_RTC_ALRMBSSR); - rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32WB_RTC_ALRMBR)); + putreg32(alarmreg, STM32_RTC_ALRMBR); + putreg32(0, STM32_RTC_ALRMBSSR); + rtcinfo(" ALRMBR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMBR)); /* Enable RTC alarm B */ - modifyreg32(STM32WB_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); rtchw_set_alrmbr_exit: rtc_wprlock(); @@ -861,13 +861,13 @@ int up_rtc_initialize(void) stm32wb_pwr_enablebkp(true); #if defined(CONFIG_STM32WB_RTC_HSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); #elif defined(CONFIG_STM32WB_RTC_LSICLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); #elif defined(CONFIG_STM32WB_RTC_LSECLOCK) - modifyreg32(STM32WB_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else # error "No clock for RTC!" @@ -875,7 +875,7 @@ int up_rtc_initialize(void) /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ - modifyreg32(STM32WB_RCC_BDCR, 0, RCC_BDCR_RTCEN); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); /* Disable the write protection for RTC registers */ @@ -903,9 +903,9 @@ int up_rtc_initialize(void) { /* Clear RTC_CR FMT, OSEL and POL Bits */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_FMT | RTC_CR_OSEL_MASK | RTC_CR_POL); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Configure RTC pre-scaler with the required values */ @@ -921,7 +921,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #elif defined(CONFIG_STM32WB_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) @@ -929,13 +929,13 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), - STM32WB_RTC_PRER); + STM32_RTC_PRER); #endif /* Exit Initialization mode */ @@ -1029,18 +1029,18 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, do { - dr = getreg32(STM32WB_RTC_DR); - tr = getreg32(STM32WB_RTC_TR); + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS - ssr = getreg32(STM32WB_RTC_SSR); - tmp = getreg32(STM32WB_RTC_TR); + ssr = getreg32(STM32_RTC_SSR); + tmp = getreg32(STM32_RTC_TR); if (tmp != tr) { continue; } #endif - tmp = getreg32(STM32WB_RTC_DR); + tmp = getreg32(STM32_RTC_DR); } while (tmp != dr); @@ -1095,7 +1095,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, uint32_t prediv_s; uint32_t usecs; - prediv_s = getreg32(STM32WB_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; ssr &= RTC_SSR_MASK; @@ -1242,8 +1242,8 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) { /* Set the RTC TR and DR registers */ - putreg32(tr, STM32WB_RTC_TR); - putreg32(dr, STM32WB_RTC_DR); + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); /* Exit Initialization mode and wait for the RTC Time and Date * registers to be synchronized with RTC APB clock. @@ -1439,7 +1439,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); ret = rtchw_check_alrawf(); if (ret < 0) @@ -1449,8 +1449,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMAR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRAF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMAR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRAF, 0); rtc_wprlock(); ret = OK; } @@ -1470,7 +1470,7 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Disable RTC alarm and interrupt */ - modifyreg32(STM32WB_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); ret = rtchw_check_alrbwf(); if (ret < 0) @@ -1480,8 +1480,8 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) /* Unset the alarm */ - putreg32(0xffffffff, STM32WB_RTC_ALRMBR); - modifyreg32(STM32WB_RTC_ISR, RTC_ISR_ALRBF, 0); + putreg32(0xffffffff, STM32_RTC_ALRMBR); + modifyreg32(STM32_RTC_ISR, RTC_ISR_ALRBF, 0); rtc_wprlock(); ret = OK; } @@ -1528,7 +1528,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { case RTC_ALARMA: { - alarmreg = STM32WB_RTC_ALRMAR; + alarmreg = STM32_RTC_ALRMAR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1537,7 +1537,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #if CONFIG_RTC_NALARMS > 1 case RTC_ALARMB: { - alarmreg = STM32WB_RTC_ALRMBR; + alarmreg = STM32_RTC_ALRMBR; ret = stm32wb_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } @@ -1574,9 +1574,9 @@ static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) stm32wb_pwr_enablebkp(true); - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); stm32wb_pwr_enablebkp(false); @@ -1622,10 +1622,10 @@ static inline void rtc_set_wcksel(unsigned int wucksel) { uint32_t regval = 0; - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUCKSEL_MASK; regval |= wucksel; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); } #endif @@ -1661,7 +1661,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" #elif defined(CONFIG_STM32WB_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / - STM32WB_LSE_FREQUENCY; + STM32_LSE_FREQUENCY; #else # error "No clock for RTC!" #endif @@ -1699,9 +1699,9 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Clear WUTE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1710,7 +1710,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1734,7 +1734,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, /* Get number of ticks. */ - ticks = millisecs * STM32WB_LSE_FREQUENCY / (16 * 1000); + ticks = millisecs * STM32_LSE_FREQUENCY / (16 * 1000); /* Wake-up is after WUT+1 ticks. */ @@ -1755,17 +1755,17 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * selection. */ - putreg32(wutr_val, STM32WB_RTC_WUTR); + putreg32(wutr_val, STM32_RTC_WUTR); - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval |= RTC_CR_WUTIE | RTC_CR_WUTE; - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Just in case resets the WUTF flag in RTC_ISR */ - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; - putreg32(regval, STM32WB_RTC_ISR); + putreg32(regval, STM32_RTC_ISR); rtc_wprlock(); @@ -1797,9 +1797,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clear WUTE and WUTIE in RTC_CR to disable the wakeup timer */ - regval = getreg32(STM32WB_RTC_CR); + regval = getreg32(STM32_RTC_CR); regval &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - putreg32(regval, STM32WB_RTC_CR); + putreg32(regval, STM32_RTC_CR); /* Poll WUTWF until it is set in RTC_ISR (takes around 2 RTCCLK * clock cycles) @@ -1808,7 +1808,7 @@ int stm32wb_rtc_cancelperiodic(void) ret = -ETIMEDOUT; for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) { - regval = getreg32(STM32WB_RTC_ISR); + regval = getreg32(STM32_RTC_ISR); if ((regval & RTC_ISR_WUTWF) != 0) { /* Synchronized */ @@ -1820,9 +1820,9 @@ int stm32wb_rtc_cancelperiodic(void) /* Clears RTC_WUTR register */ - regval = getreg32(STM32WB_RTC_WUTR); + regval = getreg32(STM32_RTC_WUTR); regval &= ~RTC_WUTR_MASK; - putreg32(regval, STM32WB_RTC_WUTR); + putreg32(regval, STM32_RTC_WUTR); rtc_wprlock(); diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 6868b14ddcf..b83811499da 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -38,9 +38,9 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_RTC_PRESCALER_SECOND 32767 /* Default prescaler +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler * to get a second base */ -#define STM32WB_RTC_PRESCALER_MIN 1 /* Maximum speed +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ #if !defined(CONFIG_STM32WB_RTC_MAGIC) @@ -57,7 +57,7 @@ #define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC #define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32WB_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 009ead5cea0..16fc6ea8558 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_NALARMS 2 +#define STM32_NALARMS 2 /**************************************************************************** * Private Types @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32WB_NALARMS]; + struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index e657d7435de..5289b289fa7 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -379,13 +379,13 @@ static struct stm32wb_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WB_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WB_PCLK1_FREQUENCY, - .usartbase = STM32WB_LPUART1_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -441,13 +441,13 @@ static struct stm32wb_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WB_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WB_PCLK2_FREQUENCY, - .usartbase = STM32WB_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, #if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -478,7 +478,7 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wb_serial_s * -const g_uart_devs[STM32WB_NLPUART + STM32WB_NUSART] = +const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -542,15 +542,15 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32WB_USART_BRR_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,8 +713,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif @@ -750,7 +750,7 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32WB_USART_BRR_OFFSET, brr); + stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif @@ -772,7 +772,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - if (priv->usartbase == STM32WB_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { stm32wb_serial_setbaud_lpuart(priv); } @@ -784,7 +784,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,11 +834,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -855,7 +855,7 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -900,7 +900,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -1008,7 +1008,7 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -1045,15 +1045,15 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER - case STM32WB_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WB_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32WB_USART1_SERIALDRIVER - case STM32WB_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WB_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif } @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,26 +1150,26 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1177,9 +1177,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1231,7 +1231,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1242,7 +1242,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1315,9 +1315,9 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, regval); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR3_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1667,11 +1667,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR3_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,11 +1718,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32WB_USART_CR2_OFFSET); + uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32WB_USART_CR2_OFFSET, cr); + stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32WB_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32WB_USART_CR1_OFFSET, + cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1970,7 +1970,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32WB_USART_RDR_OFFSET); + rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2058,7 +2058,7 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2219,7 +2219,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2230,7 +2230,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wb_dmasetup(priv->rxdma, - priv->usartbase + STM32WB_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2396,7 +2396,7 @@ static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wb_serial_putreg(priv, STM32WB_USART_TDR_OFFSET, (uint32_t)ch); + stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2482,7 +2482,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wb_serial_txready(struct uart_dev_s *dev) { struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET) & + return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32WB_USART_ISR_OFFSET); + priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32WB_USART_ICR_OFFSET, + stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2655,7 +2655,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WB_NLPUART + STM32WB_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wb_serial_s *priv = g_uart_devs[n]; @@ -2723,7 +2723,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2787,7 +2787,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WB_NLPUART + STM32WB_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 7666a72f780..67e1cf36b01 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -281,10 +281,10 @@ static struct stm32wb_spidev_s g_spi1dev = { .ops = &g_spi1ops, }, - .spibase = STM32WB_SPI1_BASE, - .spiclock = STM32WB_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32WB_SPI_DMA /* lines must be configured in board.h */ @@ -339,10 +339,10 @@ static struct stm32wb_spidev_s g_spi2dev = { .ops = &g_spi2ops, }, - .spibase = STM32WB_SPI2_BASE, - .spiclock = STM32WB_PCLK1_FREQUENCY, + .spibase = STM32_SPI2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32WB_SPI_INTERRUPTS - .spiirq = STM32WB_IRQ_SPI2, + .spiirq = STM32_IRQ_SPI2, #endif #ifdef CONFIG_STM32WB_SPI_DMA .rxch = DMACHAN_SPI2_RX, @@ -462,11 +462,11 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -487,11 +487,11 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0); /* Then return the received byte */ - return spi_getreg8(priv, STM32WB_SPI_DR_OFFSET); + return spi_getreg8(priv, STM32_SPI_DR_OFFSET); } /**************************************************************************** @@ -514,11 +514,11 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg(priv, STM32WB_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } /**************************************************************************** @@ -541,11 +541,11 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WB_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0); /* Then send the byte */ - spi_putreg8(priv, STM32WB_SPI_DR_OFFSET, byte); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, byte); } /**************************************************************************** @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32WB_SPI_DR_OFFSET, + stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -922,11 +922,11 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) uint16_t setbits; uint32_t actual; - /* Limit to max possible (if STM32WB_SPI_CLK_MAX is defined in board.h) */ + /* Limit to max possible (if STM32_SPI_CLK_MAX is defined in board.h) */ - if (frequency > STM32WB_SPI_CLK_MAX) + if (frequency > STM32_SPI_CLK_MAX) { - frequency = STM32WB_SPI_CLK_MAX; + frequency = STM32_SPI_CLK_MAX; } /* Has the frequency changed? */ @@ -992,9 +992,9 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) actual = priv->spiclock >> 8; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, SPI_CR1_BR_MASK); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the frequency selection so that subsequent reconfigurations * will be faster. @@ -1064,9 +1064,9 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) return; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the mode so that subsequent re-configurations will be * faster. @@ -1130,9 +1130,9 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) clrbits |= SPI_CR2_FRXTH; /* RX FIFO Threshold = 2 bytes */ } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); /* Save the selection so that subsequent re-configurations will be * faster. @@ -1184,9 +1184,9 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) clrbits = SPI_CR1_LSBFIRST; } - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, 0, SPI_CR1_SPE); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); features &= ~HWFEAT_LSBFIRST; #endif @@ -1252,7 +1252,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * flags). */ - regval = spi_getreg(priv, STM32WB_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); if (spi_16bitmode(priv)) { @@ -1670,11 +1670,11 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) SPI_CR1_LSBFIRST | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | SPI_CR1_BIDIMODE; setbits = SPI_CR1_MSTR | SPI_CR1_SSI | SPI_CR1_SSM; - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, setbits, clrbits); clrbits = SPI_CR2_DS_MASK; setbits = SPI_CR2_DS_8BIT | SPI_CR2_FRXTH; /* FRXTH must be high in 8-bit mode */ - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, setbits, clrbits); + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, setbits, clrbits); priv->frequency = 0; priv->nbits = 8; @@ -1686,7 +1686,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WB_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WB_SPI_DMA /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA @@ -1701,13 +1701,13 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) priv->txdma = stm32wb_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); - spi_modifycr(STM32WB_SPI_CR2_OFFSET, priv, + spi_modifycr(STM32_SPI_CR2_OFFSET, priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); #endif /* Enable spi */ - spi_modifycr(STM32WB_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); + spi_modifycr(STM32_SPI_CR1_OFFSET, priv, SPI_CR1_SPE, 0); #ifdef CONFIG_PM /* Register to receive power management callbacks */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 7ecd128a5c9..660cd4db3a6 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -64,12 +64,12 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) #ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32WB_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) # define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) #endif #ifdef CONFIG_STM32WB_SRAM2B_HEAP -# define SRAM2B_START STM32WB_SRAM2B_BASE +# define SRAM2B_START STM32_SRAM2B_BASE # define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) #endif diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index ef5e64b5f60..acefc6af5ab 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -89,7 +89,7 @@ # define HAVE_32BIT_TICKLESS 1 # endif #else -# error "STM32WB_TICKLESS_TIMER must be defined for tickless configuration" +# error "STM32_TICKLESS_TIMER must be defined for tickless configuration" #endif /**************************************************************************** @@ -166,7 +166,7 @@ static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, static inline void stm32wb_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 0, 1 << channel); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** @@ -175,7 +175,7 @@ static inline void stm32wb_tickless_enableint(int channel) static inline void stm32wb_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32WB_TIM_DIER_OFFSET, 1 << channel, 0); + stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** @@ -184,7 +184,7 @@ static inline void stm32wb_tickless_disableint(int channel) static inline void stm32wb_tickless_ackint(int channel) { - stm32wb_putreg16(STM32WB_TIM_SR_OFFSET, ~(1 << channel)); + stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** @@ -193,7 +193,7 @@ static inline void stm32wb_tickless_ackint(int channel) static inline uint16_t stm32wb_tickless_getint(void) { - return stm32wb_getreg16(STM32WB_TIM_SR_OFFSET); + return stm32wb_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** @@ -205,7 +205,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; /* Further we use range as 0..3; if channel=0 it will also overflow here */ @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -231,14 +231,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } @@ -294,7 +294,7 @@ static void stm32wb_timing_handler(void) { g_tickless.overflow++; - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); } /**************************************************************************** @@ -364,25 +364,25 @@ void up_timer_initialize(void) { #ifdef CONFIG_STM32WB_TIM1 case 1: - g_tickless.base = STM32WB_TIM1_BASE; + g_tickless.base = STM32_TIM1_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: - g_tickless.base = STM32WB_TIM2_BASE; + g_tickless.base = STM32_TIM2_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: - g_tickless.base = STM32WB_TIM16_BASE; + g_tickless.base = STM32_TIM16_BASE; break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: - g_tickless.base = STM32WB_TIM17_BASE; + g_tickless.base = STM32_TIM17_BASE; break; #endif @@ -409,15 +409,15 @@ void up_timer_initialize(void) DEBUGPANIC(); } - STM32WB_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); + STM32_TIM_SETCLOCK(g_tickless.tch, g_tickless.frequency); /* Set up to receive the callback when the counter overflow occurs */ - STM32WB_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); /* Initialize interval to zero */ - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, 0); /* Setup compare channel for the interval timing */ @@ -426,12 +426,12 @@ void up_timer_initialize(void) /* Set timer period */ #ifdef HAVE_32BIT_TICKLESS - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT32_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT32_MAX; #endif #else - STM32WB_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); + STM32_TIM_SETPERIOD(g_tickless.tch, UINT16_MAX); #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP g_oneshot_maxticks = UINT16_MAX; #endif @@ -439,12 +439,12 @@ void up_timer_initialize(void) /* Initialize the counter */ - STM32WB_TIM_SETMODE(g_tickless.tch, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(g_tickless.tch, STM32_TIM_MODE_UP); /* Start the timer */ - STM32WB_TIM_ACKINT(g_tickless.tch, ~0); - STM32WB_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); + STM32_TIM_ACKINT(g_tickless.tch, ~0); + STM32_TIM_ENABLEINT(g_tickless.tch, GTIM_DIER_UIE); } /**************************************************************************** @@ -501,9 +501,9 @@ int up_timer_gettime(struct timespec *ts) flags = enter_critical_section(); overflow = g_tickless.overflow; - counter = STM32WB_TIM_GETCOUNTER(g_tickless.tch); - pending = STM32WB_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); - verify = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + counter = STM32_TIM_GETCOUNTER(g_tickless.tch); + pending = STM32_TIM_CHECKINT(g_tickless.tch, GTIM_SR_UIF); + verify = STM32_TIM_GETCOUNTER(g_tickless.tch); /* If an interrupt was pending before we re-enabled interrupts, * then the overflow needs to be incremented. @@ -511,7 +511,7 @@ int up_timer_gettime(struct timespec *ts) if (pending) { - STM32WB_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); + STM32_TIM_ACKINT(g_tickless.tch, GTIM_SR_UIF); /* Increment the overflow count and use the value of the * guaranteed to be AFTER the overflow occurred. @@ -576,7 +576,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_gettick(clock_t *ticks) { - *ticks = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + *ticks = STM32_TIM_GETCOUNTER(g_tickless.tch); return OK; } @@ -681,7 +681,7 @@ int up_timer_cancel(struct timespec *ts) stm32wb_tickless_disableint(g_tickless.channel); - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; g_tickless.pending = false; @@ -807,7 +807,7 @@ int up_timer_start(const struct timespec *ts) */ period = (usec * (uint64_t)g_tickless.frequency) / USEC_PER_SEC; - count = STM32WB_TIM_GETCOUNTER(g_tickless.tch); + count = STM32_TIM_GETCOUNTER(g_tickless.tch); tmrinfo("usec=%llu period=%08llx\n", usec, period); @@ -822,7 +822,7 @@ int up_timer_start(const struct timespec *ts) g_tickless.period = (uint16_t)(period + count); #endif - STM32WB_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, + STM32_TIM_SETCOMPARE(g_tickless.tch, g_tickless.channel, g_tickless.period); /* Enable interrupts. We should get the callback when the interrupt diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 9bc6340317b..d784f103c2a 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -225,16 +225,16 @@ static const struct stm32wb_tim_ops_s stm32wb_tim_ops = struct stm32wb_tim_priv_s stm32wb_tim1_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM2 struct stm32wb_tim_priv_s stm32wb_tim2_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -242,8 +242,8 @@ struct stm32wb_tim_priv_s stm32wb_tim2_priv = struct stm32wb_tim_priv_s stm32wb_tim16_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -251,8 +251,8 @@ struct stm32wb_tim_priv_s stm32wb_tim16_priv = struct stm32wb_tim_priv_s stm32wb_tim17_priv = { .ops = &stm32wb_tim_ops, - .mode = STM32WB_TIM_MODE_UNUSED, - .base = STM32WB_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -340,9 +340,9 @@ static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_EGR_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32WB_TIM_EGR_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** @@ -351,11 +351,11 @@ static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -364,9 +364,9 @@ static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET); + uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** @@ -380,7 +380,7 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_DISABLED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wb_tim_disable(dev); } @@ -393,7 +393,7 @@ static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) static void stm32wb_tim_gpioconfig(uint32_t cfg, enum stm32wb_tim_channel_e mode) { - if (mode & STM32WB_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wb_configgpio(cfg); } @@ -413,42 +413,42 @@ static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DIER_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCMR2_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_ARR_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_CCR4_OFFSET) + stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); - if (priv->base == STM32WB_TIM1_BASE) + if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32WB_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32WB_TIM_DMAR_OFFSET)); + stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } @@ -466,17 +466,17 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ #if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) - if ((mode == STM32WB_TIM_MODE_DOWN || mode == STM32WB_TIM_MODE_UPDOWN)) + if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { #if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM16_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif #if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM17_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -486,22 +486,22 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WB_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WB_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WB_TIM_MODE_UP: + case STM32_TIM_MODE_UP: val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; #if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) - case STM32WB_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; - case STM32WB_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_CMS_CNTR1; /* Our default: @@ -511,7 +511,7 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, break; #endif - case STM32WB_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | GTIM_CR1_OPM; break; @@ -520,14 +520,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32WB_TIM_CR1_OFFSET, val); + stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); #ifdef CONFIG_STM32WB_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM1_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32WB_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -564,25 +564,25 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -647,8 +647,8 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32WB_TIM_ARR_OFFSET, reload); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } @@ -681,25 +681,25 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -730,7 +730,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32WB_TIM_PSC_OFFSET, prescaler); + stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } @@ -754,25 +754,25 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -782,7 +782,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32WB_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } @@ -794,7 +794,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32WB_TIM_ARR_OFFSET, period); + stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** @@ -804,7 +804,7 @@ static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32WB_TIM_ARR_OFFSET); + return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** @@ -814,12 +814,12 @@ static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32WB_TIM_CNT_OFFSET); + uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -837,7 +837,7 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) /* Only TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32WB_TIM2_BASE) + if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -859,7 +859,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WB_TIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_TIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -872,17 +872,17 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32WB_TIM_CCER_OFFSET); + ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ - switch (mode & STM32WB_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WB_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WB_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = GTIM_CCMR_OCXM_PWM1(channel) | GTIM_CCMR_OCXPE(channel); ccer_val |= GTIM_CCER_CCXE(channel); break; @@ -893,28 +893,28 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WB_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CCXP(channel); } if (channel > 1) { - ccmr_offset = STM32WB_TIM_CCMR2_OFFSET; + ccmr_offset = STM32_TIM_CCMR2_OFFSET; } ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32WB_TIM_CCER_OFFSET, ccer_val); + stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -947,7 +947,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -980,7 +980,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -995,7 +995,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32WB_TIM_CCR1_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32WB_TIM_CCR2_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32WB_TIM_CCR3_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32WB_TIM_CCR4_OFFSET, compare); + stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1063,16 +1063,16 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR1_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR2_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR3_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32WB_TIM_CCR4_OFFSET); + return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; @@ -1093,26 +1093,26 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - vectorno = STM32WB_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - vectorno = STM32WB_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - vectorno = STM32WB_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - vectorno = STM32WB_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1144,7 +1144,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, 0, source); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** @@ -1154,7 +1154,7 @@ static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32WB_TIM_DIER_OFFSET, source, 0); + stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** @@ -1163,7 +1163,7 @@ static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32WB_TIM_SR_OFFSET, ~source); + stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** @@ -1172,7 +1172,7 @@ static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32WB_TIM_SR_OFFSET); + uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1195,28 +1195,28 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) #ifdef CONFIG_STM32WB_TIM1 case 1: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; - modifyreg32(STM32WB_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; - modifyreg32(STM32WB_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,7 +1226,7 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32WB_TIM_MODE_UNUSED) + if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1252,26 +1252,26 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) switch (((struct stm32wb_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 - case STM32WB_TIM1_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM2 - case STM32WB_TIM2_BASE: - modifyreg32(STM32WB_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM16 - case STM32WB_TIM16_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32WB_TIM17 - case STM32WB_TIM17_BASE: - modifyreg32(STM32WB_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1281,7 +1281,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32WB_TIM_MODE_UNUSED; + ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index a1257fbee51..ead07f60195 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -64,25 +64,25 @@ /* Helpers ******************************************************************/ -#define STM32WB_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WB_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) -#define STM32WB_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WB_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WB_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WB_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WB_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WB_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) -#define STM32WB_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WB_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WB_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WB_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WB_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WB_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WB_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WB_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) -#define STM32WB_TIM_ENABLE(d) ((d)->ops->enable(d)) -#define STM32WB_TIM_DISABLE(d) ((d)->ops->disable(d)) -#define STM32WB_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETFREQ(d,freq) ((d)->ops->setfreq(d,freq)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) +#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) +#define STM32_TIM_DUMPREGS(d) ((d)->ops->dump_regs(d)) /**************************************************************************** * Public Types @@ -110,34 +110,34 @@ struct stm32wb_tim_dev_s enum stm32wb_tim_mode_e { - STM32WB_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WB_TIM_MODE_MASK = 0x0310, - STM32WB_TIM_MODE_DISABLED = 0x0000, - STM32WB_TIM_MODE_UP = 0x0100, - STM32WB_TIM_MODE_DOWN = 0x0110, - STM32WB_TIM_MODE_UPDOWN = 0x0200, - STM32WB_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WB_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WB_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WB_TIM_MODE_CK_EXT = 0x0800, - STM32WB_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WB_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WB_TIM_MODE_CK_CH1 = 0x0001, - STM32WB_TIM_MODE_CK_CH2 = 0x0002, - STM32WB_TIM_MODE_CK_CH3 = 0x0003, - STM32WB_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -147,32 +147,32 @@ enum stm32wb_tim_mode_e enum stm32wb_tim_channel_e { - STM32WB_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WB_TIM_CH_POLARITY_POS = 0x00, - STM32WB_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WB_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WB_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active * high when counter < compare */ #if 0 - STM32WB_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif /* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */ #if 0 - STM32WB_TIM_CH_INCAPTURE = 0x10, - STM32WB_TIM_CH_INPWM = 0x20 - STM32WB_TIM_CH_DRIVE_OC /* Open collector mode */ + STM32_TIM_CH_INCAPTURE = 0x10, + STM32_TIM_CH_INPWM = 0x20 + STM32_TIM_CH_DRIVE_OC /* Open collector mode */ #endif }; diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ef7af07926e..ced3f62d5f9 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -44,10 +44,10 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WB_TIM1_RES 16 -#define STM32WB_TIM2_RES 32 -#define STM32WB_TIM16_RES 16 -#define STM32WB_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -107,7 +107,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -115,7 +115,7 @@ static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -123,7 +123,7 @@ static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -131,7 +131,7 @@ static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WB_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -156,13 +156,13 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WB_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); + STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WB_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -194,12 +194,12 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } priv->started = true; @@ -232,9 +232,9 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WB_TIM_SETMODE(priv->tim, STM32WB_TIM_MODE_DISABLED); - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -288,8 +288,8 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WB_TIM_GETCLOCK(priv->tim); - period = STM32WB_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -305,7 +305,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = clock / 1000000; - status->timeleft = (timeout - STM32WB_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -341,13 +341,13 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WB_TIM_SETCLOCK(priv->tim, freq); - STM32WB_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WB_TIM_SETCLOCK(priv->tim, 1000000); - STM32WB_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -386,13 +386,13 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WB_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); - STM32WB_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else { - STM32WB_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); - STM32WB_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, GTIM_DIER_UIE); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index c9dc2cc4738..a01219c737b 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -59,9 +59,9 @@ #undef CONFIG_STM32WB_SYSTICK_HCLKd8 #ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WB_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32WB_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); /* Enable SysTick interrupts */ @@ -144,5 +144,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WB_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 22e781f8c6f..17a3808d363 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -29,7 +29,7 @@ #include "hardware/stm32wb_memorymap.h" #include "stm32wb_uid.h" -#ifdef STM32WB_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -41,8 +41,8 @@ void stm32wb_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WB_SYSMEM_UID) + i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID) + i); } } -#endif /* STM32WB_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index e00cf8ce7ae..bb948a3f3c6 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -84,13 +84,13 @@ /* LCD */ -#define STM32WB_LCD_SPINO 2 /* SPI2 */ +#define STM32_LCD_SPINO 2 /* SPI2 */ -#define STM32WB_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_CS (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN11) -#define STM32WB_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_RST (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0) -#define STM32WB_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ +#define STM32_LCD_A0 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_5MHz |\ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1) /**************************************************************************** diff --git a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h index ce6734fd5a6..cff810a1b03 100644 --- a/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h +++ b/boards/arm/stm32wb/flipperzero/include/flipperzero-clocking.h @@ -51,10 +51,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -71,145 +71,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -218,18 +218,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index ed22e8917b2..4eea343833d 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -83,23 +83,23 @@ static struct st7565_lcd_s g_st7565_dev = static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32WB_LCD_RST, !on); + stm32wb_gpiowrite(STM32_LCD_RST, !on); } static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 0); + stm32wb_gpiowrite(STM32_LCD_CS, 0); } static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32WB_LCD_CS, 1); + stm32wb_gpiowrite(STM32_LCD_CS, 1); } static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32WB_LCD_A0, !cmd); + stm32wb_gpiowrite(STM32_LCD_A0, !cmd); } static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, @@ -124,14 +124,14 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32WB_LCD_RST); - stm32wb_configgpio(STM32WB_LCD_A0); + stm32wb_configgpio(STM32_LCD_RST); + stm32wb_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32WB_LCD_SPINO); + g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { - lcderr("ERROR: Failed to initialize SPI port %d\n", STM32WB_LCD_SPINO); + lcderr("ERROR: Failed to initialize SPI port %d\n", STM32_LCD_SPINO); return -ENODEV; } @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32WB_LCD_RST, 0); + stm32wb_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32WB_LCD_RST, 1); + stm32wb_gpiowrite(STM32_LCD_RST, 1); return OK; } @@ -156,12 +156,12 @@ struct lcd_dev_s *board_lcd_getdev(int lcddev) if (!g_lcddev) { lcderr("ERROR: Failed to bind SPI port %d to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); } else { lcdinfo("SPI port %d bound to LCD %d\n", - STM32WB_LCD_SPINO, lcddev); + STM32_LCD_SPINO, lcddev); /* And turn the LCD on (CONFIG_LCD_MAXPOWER should be 1) */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index a655b0f4f62..cfb057dae1e 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -55,7 +55,7 @@ void weak_function stm32wb_spidev_initialize(void) */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32WB_LCD_CS); /* ST7565 chip select */ + stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } @@ -91,7 +91,7 @@ void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32WB_LCD_CS, !selected); + stm32wb_gpiowrite(STM32_LCD_CS, !selected); } #endif } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h index d48843b2736..a4f9d490a7b 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/nucleo-wb55rg.h @@ -52,10 +52,10 @@ * HSI48 - 48 MHz fine-granularity trimmable RC with CRS */ -#define STM32WB_HSI_FREQUENCY 16000000ul -#define STM32WB_LSI_FREQUENCY 32000 -#define STM32WB_LSE_FREQUENCY 32768 -#define STM32WB_HSE_FREQUENCY 32000000ul +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_LSE_FREQUENCY 32768 +#define STM32_HSE_FREQUENCY 32000000ul /* XXX there needs to be independent selections for the System Clock Mux and * the PLL Source Mux; currently System Clock Mux always is PLL, and PLL @@ -72,145 +72,145 @@ #endif #if 0 -# define STM32WB_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ +# define STM32_BOARD_RFWKP_USEHSE 1 /* CPU2 use HSE/1024 on RF wakeup */ #elif 1 -# define STM32WB_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ +# define STM32_BOARD_RFWKP_USELSE 1 /* CPU2 use LSE on RF wakeup */ #endif #if defined(HSI_CLOCK_CONFIG) -#define STM32WB_BOARD_USEHSI 1 +#define STM32_BOARD_USEHSI 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((16MHz / 1) * 8) / 2) = 64MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(8) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from HSI48 */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 -#define STM32WB_HSI48_SYNCSRC SYNCSRC_LSE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 +#define STM32_HSI48_SYNCSRC SYNCSRC_LSE /* Enable LSE oscillator, used automatically trim the HSI48, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(HSE_CLOCK_CONFIG) /* Use the HSE */ -#define STM32WB_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 2 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((32MHz / 2) * 12) / 3) = 64MHz * And the Q output is set as (((32MHz / 2) * 12) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(12) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable LSE (for the RTC) */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #elif defined(MSI_CLOCK_CONFIG) /* Use the MSI */ -#define STM32WB_BOARD_USEMSI 1 +#define STM32_BOARD_USEMSI 1 -#define STM32WB_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M +#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M -#define STM32WB_SYSCLK_FREQUENCY 64000000ul +#define STM32_SYSCLK_FREQUENCY 64000000ul /* Prescaler common to all PLL inputs; will be 1 */ -#define STM32WB_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as (((4MHz / 1) * 48) / 3) = 64MHz * And the Q output is set as (((4MHz / 1) * 48) / 4) = 48MHz */ -#define STM32WB_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) -#define STM32WB_PLLCFG_PLLR_ENABLED -#define STM32WB_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) -#define STM32WB_PLLCFG_PLLQ_ENABLED -#define STM32WB_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(48) +#define STM32_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(3) +#define STM32_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(4) /* 'SAIPLL1' is not used */ -#define STM32WB_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) +#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(8) /* CLK48 will come from the PLLMAIN via the Q output */ -#define STM32WB_USE_CLK48 1 -#define STM32WB_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN -#define STM32WB_HSI48_SYNCSRC SYNCSRC_NONE +#define STM32_USE_CLK48 1 +#define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLMAIN +#define STM32_HSI48_SYNCSRC SYNCSRC_NONE /* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */ -#define STM32WB_USE_LSE 1 +#define STM32_USE_LSE 1 #endif /* AHB clock (HCLK) is SYSCLK (64MHz) */ -#define BOARD_AHB_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define BOARD_AHB_FREQUENCY STM32_SYSCLK_FREQUENCY -#define STM32WB_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK -#define STM32WB_HCLK_FREQUENCY STM32WB_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* CPU2 clock (HCLK2) is SYSCLK/2 (32MHz) */ -#define STM32WB_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 +#define STM32_RCC_EXTCFGR_C2HPRE RCC_EXTCFGR_C2HPRE_2 /* AHB4 clock (HCLK4) is SYSCLK (64MHz) */ -#define STM32WB_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 +#define STM32_RCC_EXTCFGR_SHDHPRE RCC_EXTCFGR_SHDHPRE_1 /* APB1 clock (PCLK1) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 -#define STM32WB_PCLK1_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK1 +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* APB2 clock (PCLK2) is HCLK/1 (64MHz) */ -#define STM32WB_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 -#define STM32WB_PCLK2_FREQUENCY (STM32WB_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK1 +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* Timer Frequencies, if APB prescaler is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. @@ -219,18 +219,18 @@ /* Timers driven from APB1 will be the same frequency as PCLK1 */ -#define STM32WB_APB1_TIM2_CLKIN (1 * STM32WB_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (1 * STM32_PCLK1_FREQUENCY) /* Timers driven from APB2 will be the same frequency as PCLK2 */ -#define STM32WB_APB2_TIM1_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM16_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) -#define STM32WB_APB2_TIM17_CLKIN (1 * STM32WB_PCLK2_FREQUENCY) +#define STM32_APB2_TIM1_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (1 * STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (1 * STM32_PCLK2_FREQUENCY) -#define BOARD_TIM1_FREQUENCY STM32WB_APB2_TIM1_CLKIN -#define BOARD_TIM2_FREQUENCY STM32WB_APB1_TIM2_CLKIN -#define BOARD_TIM16_FREQUENCY STM32WB_APB2_TIM16_CLKIN -#define BOARD_TIM17_FREQUENCY STM32WB_APB2_TIM17_CLKIN +#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN +#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN +#define BOARD_TIM16_FREQUENCY STM32_APB2_TIM16_CLKIN +#define BOARD_TIM17_FREQUENCY STM32_APB2_TIM17_CLKIN /* Higher SYSCLK requires more flash wait states. */ From 28c02dea3e3fcff9334bff9612dfcaed964b3e13 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 055/268] !arch/stm32wl5: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32WL5 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32wl5/chip.h | 34 +- arch/arm/include/stm32wl5/irq.h | 30 +- .../include/stm32wl5/stm32wl5xxx_cpu1_irq.h | 140 ++++---- arch/arm/src/stm32wl5/chip.h | 2 +- .../arm/src/stm32wl5/hardware/stm32wl5_exti.h | 72 ++-- .../src/stm32wl5/hardware/stm32wl5_flash.h | 102 +++--- .../arm/src/stm32wl5/hardware/stm32wl5_gpio.h | 118 +++---- .../arm/src/stm32wl5/hardware/stm32wl5_ipcc.h | 44 +-- .../stm32wl5/hardware/stm32wl5_memorymap.h | 168 ++++----- arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h | 88 ++--- arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h | 172 ++++----- arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h | 96 ++--- .../src/stm32wl5/hardware/stm32wl5_syscfg.h | 64 ++-- arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h | 268 +++++++------- .../arm/src/stm32wl5/hardware/stm32wl5_uart.h | 92 ++--- arch/arm/src/stm32wl5/stm32wl5_allocateheap.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c | 28 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 78 ++-- arch/arm/src/stm32wl5/stm32wl5_gpio.c | 50 +-- arch/arm/src/stm32wl5/stm32wl5_gpio.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.c | 74 ++-- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_irq.c | 50 +-- arch/arm/src/stm32wl5/stm32wl5_lowputc.c | 166 ++++----- arch/arm/src/stm32wl5/stm32wl5_lse.c | 16 +- arch/arm/src/stm32wl5/stm32wl5_lsi.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_pwr.c | 14 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 182 +++++----- arch/arm/src/stm32wl5/stm32wl5_rcc.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 160 ++++----- arch/arm/src/stm32wl5/stm32wl5_spi.c | 44 +-- arch/arm/src/stm32wl5/stm32wl5_start.c | 4 +- arch/arm/src/stm32wl5/stm32wl5_tim.c | 332 +++++++++--------- arch/arm/src/stm32wl5/stm32wl5_tim.h | 72 ++-- .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 82 ++--- arch/arm/src/stm32wl5/stm32wl5_timerisr.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_uid.c | 6 +- .../stm32wl5/nucleo-wl55jc/include/board.h | 62 ++-- .../stm32wl5/nucleo-wl55jc/src/stm32_flash.c | 2 +- 39 files changed, 1471 insertions(+), 1471 deletions(-) diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index d7da1c8c45e..48c3f837a6b 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -34,28 +34,28 @@ ****************************************************************************/ #if defined(CONFIG_STM32WL5_STM32WL5XXX) -# define STM32WL5_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ -# define STM32WL5_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ +# define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ +# define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif #if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) -# define STM32WL5_NATIM 1 /* One advanced timer TIM1 */ -# define STM32WL5_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ -# define STM32WL5_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ -# define STM32WL5_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ -# define STM32WL5_NRNG 1 /* Random number generator (RNG) */ -# define STM32WL5_NUSART 2 /* USART 1-2 */ -# define STM32WL5_NLPUART 1 /* LPUART 1 */ -# define STM32WL5_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ -# define STM32WL5_NI2C 3 /* I2C1-3 */ -# define STM32WL5_NDMA 2 /* Two DMA channels DMA1-2 */ -# define STM32WL5_NPORTS 4 /* GPIO{A,B,C,H} */ -# define STM32WL5_NADC 1 /* ADC1 */ -# define STM32WL5_NDAC 1 /* DAC1 */ -# define STM32WL5_NCRC 1 /* CRC1 */ -# define STM32WL5_NCOMP 1 /* COMP1 */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ +# define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ +# define STM32_NLPTIM 3 /* Three low-power timer, LPTIM1-3 */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NUSART 2 /* USART 1-2 */ +# define STM32_NLPUART 1 /* LPUART 1 */ +# define STM32_NSPI 2 /* SPI1 and SPI2S2 (spi2 shared with i2s) */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NDMA 2 /* Two DMA channels DMA1-2 */ +# define STM32_NPORTS 4 /* GPIO{A,B,C,H} */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 1 /* DAC1 */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NCOMP 1 /* COMP1 */ #endif /* CONFIG_STM32WL5_STM32WL5XXX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wl5/irq.h b/arch/arm/include/stm32wl5/irq.h index a8941dbeed6..08bbc522c55 100644 --- a/arch/arm/include/stm32wl5/irq.h +++ b/arch/arm/include/stm32wl5/irq.h @@ -44,26 +44,26 @@ /* Processor Exceptions (vectors 0-15) */ -#define STM32WL5_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32WL5_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32WL5_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ -#define STM32WL5_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ -#define STM32WL5_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ -#define STM32WL5_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ - /* Vectors 7-10: Reserved */ -#define STM32WL5_IRQ_SVCALL (11) /* Vector 11: SVC call */ -#define STM32WL5_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ - /* Vector 13: Reserved */ -#define STM32WL5_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32WL5_IRQ_SYSTICK (15) /* Vector 15: System tick */ +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ /* External interrupts (vectors >= 16). These definitions are * chip-specific */ -#define STM32WL5_IRQ_FIRST (16) /* Vector number of the first external interrupt */ +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ /**************************************************************************** * Included Files diff --git a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h index 88ce31efc5a..a8c99354b21 100644 --- a/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h +++ b/arch/arm/include/stm32wl5/stm32wl5xxx_cpu1_irq.h @@ -48,80 +48,80 @@ * External interrupts (vectors >= 16) */ -#define STM32WL5_IRQ_WWDG (STM32WL5_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ -#define STM32WL5_IRQ_PVD (STM32WL5_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ -#define STM32WL5_IRQ_PVM (STM32WL5_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ -#define STM32WL5_IRQ_TAMPER (STM32WL5_IRQ_FIRST + 2) /* 2: Tamper */ -#define STM32WL5_IRQ_LSE_CSS (STM32WL5_IRQ_FIRST + 2) /* 2: LSECSS */ -#define STM32WL5_IRQ_RTC_STAMP (STM32WL5_IRQ_FIRST + 2) /* 2: timestamp */ -#define STM32WL5_IRQ_RTC_SSRU (STM32WL5_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ -#define STM32WL5_IRQ_RTC_WKUP (STM32WL5_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ -#define STM32WL5_IRQ_FLASH (STM32WL5_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ -#define STM32WL5_IRQ_RCC (STM32WL5_IRQ_FIRST + 5) /* 5: RCC global interrupt */ -#define STM32WL5_IRQ_EXTI0 (STM32WL5_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ -#define STM32WL5_IRQ_EXTI1 (STM32WL5_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ -#define STM32WL5_IRQ_EXTI2 (STM32WL5_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ -#define STM32WL5_IRQ_EXTI3 (STM32WL5_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ -#define STM32WL5_IRQ_EXTI4 (STM32WL5_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ -#define STM32WL5_IRQ_DMA1CH1 (STM32WL5_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH2 (STM32WL5_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH3 (STM32WL5_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH4 (STM32WL5_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH5 (STM32WL5_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH6 (STM32WL5_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA1CH7 (STM32WL5_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_ADC (STM32WL5_IRQ_FIRST + 18) /* 18: ADC global interrupt */ -#define STM32WL5_IRQ_DAC (STM32WL5_IRQ_FIRST + 19) /* 19: DAC global interrupt */ -#define STM32WL5_IRQ_C2SEV (STM32WL5_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ -#define STM32WL5_IRQ_PWRC2H (STM32WL5_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ -#define STM32WL5_IRQ_COMP (STM32WL5_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ -#define STM32WL5_IRQ_EXTI95 (STM32WL5_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ -#define STM32WL5_IRQ_TIM1BRK (STM32WL5_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ -#define STM32WL5_IRQ_TIM1UP (STM32WL5_IRQ_FIRST + 24) /* 24: Timer 1 Update */ -#define STM32WL5_IRQ_TIM1TRG_COM (STM32WL5_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ -#define STM32WL5_IRQ_TIM1CC (STM32WL5_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ -#define STM32WL5_IRQ_TIM2 (STM32WL5_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ -#define STM32WL5_IRQ_TIM16 (STM32WL5_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ -#define STM32WL5_IRQ_TIM17 (STM32WL5_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ -#define STM32WL5_IRQ_I2C1EV (STM32WL5_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ -#define STM32WL5_IRQ_I2C1ER (STM32WL5_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#define STM32WL5_IRQ_I2C2EV (STM32WL5_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ -#define STM32WL5_IRQ_I2C2ER (STM32WL5_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ -#define STM32WL5_IRQ_SPI1 (STM32WL5_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#define STM32WL5_IRQ_SPI2S2 (STM32WL5_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ -#define STM32WL5_IRQ_USART1 (STM32WL5_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#define STM32WL5_IRQ_USART2 (STM32WL5_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ -#define STM32WL5_IRQ_LPUART1 (STM32WL5_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ -#define STM32WL5_IRQ_LPTIM1 (STM32WL5_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ -#define STM32WL5_IRQ_LPTIM2 (STM32WL5_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ -#define STM32WL5_IRQ_EXTI1510 (STM32WL5_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ -#define STM32WL5_IRQ_RTCALRM (STM32WL5_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ -#define STM32WL5_IRQ_LPTIM3 (STM32WL5_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ - /* 44: Reserved */ -#define STM32WL5_IRQ_IPCC_C1_RX_IT (STM32WL5_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ -#define STM32WL5_IRQ_IPCC_C1_TX_IT (STM32WL5_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ -#define STM32WL5_IRQ_HSEM (STM32WL5_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ -#define STM32WL5_IRQ_I2C3EV (STM32WL5_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ -#define STM32WL5_IRQ_I2C3ER (STM32WL5_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ -#define STM32WL5_IRQ_RADIO (STM32WL5_IRQ_FIRST + 50) /* 50: Radio */ -#define STM32WL5_IRQ_RFBUSY (STM32WL5_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ -#define STM32WL5_IRQ_AES (STM32WL5_IRQ_FIRST + 51) /* 51: AES global interrupt */ -#define STM32WL5_IRQ_RNG (STM32WL5_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ -#define STM32WL5_IRQ_PKA (STM32WL5_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ -#define STM32WL5_IRQ_DMA2CH1 (STM32WL5_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH2 (STM32WL5_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH3 (STM32WL5_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH4 (STM32WL5_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH5 (STM32WL5_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH6 (STM32WL5_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ -#define STM32WL5_IRQ_DMA2CH7 (STM32WL5_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ -#define STM32WL5_IRQ_DMAMUX1_OVR (STM32WL5_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ +#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window watchdog early wakeup */ +#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] */ +#define STM32_IRQ_PVM (STM32_IRQ_FIRST + 1) /* 1: PVM through EXTI[34] */ +#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper */ +#define STM32_IRQ_LSE_CSS (STM32_IRQ_FIRST + 2) /* 2: LSECSS */ +#define STM32_IRQ_RTC_STAMP (STM32_IRQ_FIRST + 2) /* 2: timestamp */ +#define STM32_IRQ_RTC_SSRU (STM32_IRQ_FIRST + 2) /* 2: RTC SSR underflow */ +#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC wakeup interrupt */ +#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash memory global interrupt and Flash memory ECC single error interrupt */ +#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */ +#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI line 0 interrupt through EXTI[0] */ +#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI line 1 interrupt through EXTI[1] */ +#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI line 2 interrupt through EXTI[2] */ +#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI line 3 interrupt through EXTI[3] */ +#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI line 4 interrupt through EXTI[4] */ +#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST + 11) /* 11: DMA1 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST + 12) /* 12: DMA1 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST + 13) /* 13: DMA1 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST + 14) /* 14: DMA1 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST + 15) /* 15: DMA1 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST + 16) /* 16: DMA1 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 channel 7 non-secure interrupt */ +#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC global interrupt */ +#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 19) /* 19: DAC global interrupt */ +#define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 20) /* 20: CPU2 SEV through EXTI[40] */ +#define STM32_IRQ_PWRC2H (STM32_IRQ_FIRST + 20) /* 20: PWR CPU2 HOLD wakeup */ +#define STM32_IRQ_COMP (STM32_IRQ_FIRST + 21) /* 21: COMP2 and COMP1 interrupt through EXTI[22:21] */ +#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 22) /* 22: EXTI line [9:5] interrupt through EXTI[9:5] */ +#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 23) /* 23: Timer 1 break interrupt */ +#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 24) /* 24: Timer 1 Update */ +#define STM32_IRQ_TIM1TRG_COM (STM32_IRQ_FIRST + 25) /* 25: Timer 1 trigger and communication */ +#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 26) /* 26: Timer 1 capture compare interrupt */ +#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 27) /* 27: Timer 2 global interrupt */ +#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 28) /* 28: Timer 16 global interrupt */ +#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 29) /* 29: Timer 17 global interrupt */ +#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ +#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ +#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 32) /* 32: I2C2 event interrupt */ +#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 33) /* 33: I2C2 error interrupt */ +#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ +#define STM32_IRQ_SPI2S2 (STM32_IRQ_FIRST + 35) /* 35: SPI2S2 global interrupt */ +#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ +#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 37) /* 37: USART2 global interrupt */ +#define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 38) /* 38: LPUART1 global interrupt */ +#define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 39) /* 39: LP timer 1 global interrupt */ +#define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 40) /* 40: LP timer 2 global interrupt */ +#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 41) /* 41: EXTI line [15:10] interrupt through EXTI[15:10] (IMR1[31:26]) */ +#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 42) /* 42: RTC alarms A and B interrupt */ +#define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 43) /* 43: LP timer 3 global interrupt */ + /* 44: Reserved */ +#define STM32_IRQ_IPCC_C1_RX_IT (STM32_IRQ_FIRST + 45) /* 45: IPCC CPU1 RX occupied interrupt */ +#define STM32_IRQ_IPCC_C1_TX_IT (STM32_IRQ_FIRST + 46) /* 46: IPCC CPU1 TX free interrupt */ +#define STM32_IRQ_HSEM (STM32_IRQ_FIRST + 47) /* 47: Semaphore interrupt 0 to CPU1 */ +#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 48) /* 48: I2C3 event interrupt */ +#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 49) /* 49: I2C3 error interrupt */ +#define STM32_IRQ_RADIO (STM32_IRQ_FIRST + 50) /* 50: Radio */ +#define STM32_IRQ_RFBUSY (STM32_IRQ_FIRST + 50) /* 50: RFBUSY interrupt through EXTI[45] */ +#define STM32_IRQ_AES (STM32_IRQ_FIRST + 51) /* 51: AES global interrupt */ +#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 52) /* 52: True random number generator interrupt */ +#define STM32_IRQ_PKA (STM32_IRQ_FIRST + 53) /* 53: Private key accelerator interrupt */ +#define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 54) /* 54: DMA2 channel 1 non-secure interrupt */ +#define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 55) /* 55: DMA2 channel 2 non-secure interrupt */ +#define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 56) /* 56: DMA2 channel 3 non-secure interrupt */ +#define STM32_IRQ_DMA2CH4 (STM32_IRQ_FIRST + 57) /* 57: DMA2 channel 4 non-secure interrupt */ +#define STM32_IRQ_DMA2CH5 (STM32_IRQ_FIRST + 58) /* 58: DMA2 channel 5 non-secure interrupt */ +#define STM32_IRQ_DMA2CH6 (STM32_IRQ_FIRST + 59) /* 59: DMA2 channel 6 non-secure interrupt */ +#define STM32_IRQ_DMA2CH7 (STM32_IRQ_FIRST + 60) /* 60: DMA2 channel 7 non-secure interrupt */ +#define STM32_IRQ_DMAMUX1_OVR (STM32_IRQ_FIRST + 61) /* 61: DMAMUX1 overrun interrupt */ -#define STM32WL5_IRQ_NEXTINTS 62 +#define STM32_IRQ_NEXTINTS 62 /* (EXTI interrupts do not use IRQ numbers) */ -#define NR_IRQS (STM32WL5_IRQ_FIRST + STM32WL5_IRQ_NEXTINTS) +#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32wl5/chip.h b/arch/arm/src/stm32wl5/chip.h index b9f0208954f..cfb6d0903ed 100644 --- a/arch/arm/src/stm32wl5/chip.h +++ b/arch/arm/src/stm32wl5/chip.h @@ -49,7 +49,7 @@ * arch/stm32wl5/chip.h header file. */ -#define ARMV7M_PERIPHERAL_INTERRUPTS STM32WL5_IRQ_NEXTINTS +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS /* Cache line sizes (in bytes) for the STM32WL5 */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h index 3a3b11d974c..85a6160b917 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_exti.h @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_NEXTI1 31 -#define STM32WL5_EXTI1_MASK 0xffffffff -#define STM32WL5_NEXTI2 9 -#define STM32WL5_EXTI2_MASK 0x000001ff +#define STM32_NEXTI1 31 +#define STM32_EXTI1_MASK 0xffffffff +#define STM32_NEXTI2 9 +#define STM32_EXTI2_MASK 0x000001ff /* Register Offsets *********************************************************/ -#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ -#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ -#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ -#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ -#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ -#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ -#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ -#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ -#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ -#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ -#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ -#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ -#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ -#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ +#define STM32_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */ +#define STM32_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */ +#define STM32_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */ +#define STM32_EXTI_PR1_OFFSET 0x000c /* Pending 1 */ +#define STM32_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */ +#define STM32_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */ +#define STM32_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */ +#define STM32_EXTI_PR2_OFFSET 0x002c /* Pending 2 */ +#define STM32_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */ +#define STM32_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */ +#define STM32_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */ +#define STM32_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */ +#define STM32_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */ +#define STM32_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */ +#define STM32_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */ +#define STM32_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */ /* Register Addresses *******************************************************/ -#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET) -#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET) -#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET) -#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET) -#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET) -#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET) -#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET) -#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET) -#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET) -#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET) -#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET) -#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET) -#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET) -#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET) -#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET) -#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET) +#define STM32_EXTI_RTSR1 (STM32_EXTI_BASE+STM32_EXTI_RTSR1_OFFSET) +#define STM32_EXTI_FTSR1 (STM32_EXTI_BASE+STM32_EXTI_FTSR1_OFFSET) +#define STM32_EXTI_SWIER1 (STM32_EXTI_BASE+STM32_EXTI_SWIER1_OFFSET) +#define STM32_EXTI_PR1 (STM32_EXTI_BASE+STM32_EXTI_PR1_OFFSET) +#define STM32_EXTI_RTSR2 (STM32_EXTI_BASE+STM32_EXTI_RTSR2_OFFSET) +#define STM32_EXTI_FTSR2 (STM32_EXTI_BASE+STM32_EXTI_FTSR2_OFFSET) +#define STM32_EXTI_SWIER2 (STM32_EXTI_BASE+STM32_EXTI_SWIER2_OFFSET) +#define STM32_EXTI_PR2 (STM32_EXTI_BASE+STM32_EXTI_PR2_OFFSET) +#define STM32_EXTI_C1IMR1 (STM32_EXTI_BASE+STM32_EXTI_C1IMR1_OFFSET) +#define STM32_EXTI_C1EMR1 (STM32_EXTI_BASE+STM32_EXTI_C1EMR1_OFFSET) +#define STM32_EXTI_C1IMR2 (STM32_EXTI_BASE+STM32_EXTI_C1IMR2_OFFSET) +#define STM32_EXTI_C1EMR2 (STM32_EXTI_BASE+STM32_EXTI_C1EMR2_OFFSET) +#define STM32_EXTI_C2IMR1 (STM32_EXTI_BASE+STM32_EXTI_C2IMR1_OFFSET) +#define STM32_EXTI_C2EMR1 (STM32_EXTI_BASE+STM32_EXTI_C2EMR1_OFFSET) +#define STM32_EXTI_C2IMR2 (STM32_EXTI_BASE+STM32_EXTI_C2IMR2_OFFSET) +#define STM32_EXTI_C2EMR2 (STM32_EXTI_BASE+STM32_EXTI_C2EMR2_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index 0f14d1b02ae..e7d57753c2b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -86,71 +86,71 @@ /* Define the valid configuration */ #if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */ -# define STM32WL5_FLASH_NPAGES 32 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 32 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */ -# define STM32WL5_FLASH_NPAGES 64 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 64 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */ -# define STM32WL5_FLASH_NPAGES 128 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 128 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */ -# define STM32WL5_FLASH_NPAGES 256 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 256 +# define STM32_FLASH_PAGESIZE 2048 #elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */ -# define STM32WL5_FLASH_NPAGES 512 -# define STM32WL5_FLASH_PAGESIZE 2048 +# define STM32_FLASH_NPAGES 512 +# define STM32_FLASH_PAGESIZE 2048 #else # error "unknown flash configuration!" #endif -#define STM32WL5_FLASH_SIZE (STM32WL5_FLASH_NPAGES * STM32WL5_FLASH_PAGESIZE) +#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) /* Register Offsets *********************************************************/ -#define STM32WL5_FLASH_ACR_OFFSET 0x0000 -#define STM32WL5_FLASH_ACR2_OFFSET 0x0004 -#define STM32WL5_FLASH_KEYR_OFFSET 0x0008 -#define STM32WL5_FLASH_OPTKEYR_OFFSET 0x000c -#define STM32WL5_FLASH_SR_OFFSET 0x0010 -#define STM32WL5_FLASH_CR_OFFSET 0x0014 -#define STM32WL5_FLASH_ECCR_OFFSET 0x0018 -#define STM32WL5_FLASH_OPTR_OFFSET 0x0020 -#define STM32WL5_FLASH_PCROP1ASR_OFFSET 0x0024 -#define STM32WL5_FLASH_PCROP1AER_OFFSET 0x0028 -#define STM32WL5_FLASH_WRP1AR_OFFSET 0x002c -#define STM32WL5_FLASH_WRP1BR_OFFSET 0x0030 -#define STM32WL5_FLASH_PCROP1BSR_OFFSET 0x0034 -#define STM32WL5_FLASH_PCROP1BER_OFFSET 0x0038 -#define STM32WL5_FLASH_IPCCBR_OFFSET 0x003c -#define STM32WL5_FLASH_C2ACR_OFFSET 0x005c -#define STM32WL5_FLASH_C2SR_OFFSET 0x0060 -#define STM32WL5_FLASH_C2CR_OFFSET 0x0064 -#define STM32WL5_FLASH_SFR_OFFSET 0x0080 -#define STM32WL5_FLASH_SRRVR_OFFSET 0x0084 +#define STM32_FLASH_ACR_OFFSET 0x0000 +#define STM32_FLASH_ACR2_OFFSET 0x0004 +#define STM32_FLASH_KEYR_OFFSET 0x0008 +#define STM32_FLASH_OPTKEYR_OFFSET 0x000c +#define STM32_FLASH_SR_OFFSET 0x0010 +#define STM32_FLASH_CR_OFFSET 0x0014 +#define STM32_FLASH_ECCR_OFFSET 0x0018 +#define STM32_FLASH_OPTR_OFFSET 0x0020 +#define STM32_FLASH_PCROP1ASR_OFFSET 0x0024 +#define STM32_FLASH_PCROP1AER_OFFSET 0x0028 +#define STM32_FLASH_WRP1AR_OFFSET 0x002c +#define STM32_FLASH_WRP1BR_OFFSET 0x0030 +#define STM32_FLASH_PCROP1BSR_OFFSET 0x0034 +#define STM32_FLASH_PCROP1BER_OFFSET 0x0038 +#define STM32_FLASH_IPCCBR_OFFSET 0x003c +#define STM32_FLASH_C2ACR_OFFSET 0x005c +#define STM32_FLASH_C2SR_OFFSET 0x0060 +#define STM32_FLASH_C2CR_OFFSET 0x0064 +#define STM32_FLASH_SFR_OFFSET 0x0080 +#define STM32_FLASH_SRRVR_OFFSET 0x0084 /* Register Addresses *******************************************************/ -#define STM32WL5_FLASH_ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR_OFFSET) -#define STM32WL5_FLASH_ACR2 (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ACR2_OFFSET) -#define STM32WL5_FLASH_KEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_KEYR_OFFSET) -#define STM32WL5_FLASH_OPTKEYR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTKEYR_OFFSET) -#define STM32WL5_FLASH_SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SR_OFFSET) -#define STM32WL5_FLASH_CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_CR_OFFSET) -#define STM32WL5_FLASH_ECCR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_ECCR_OFFSET) -#define STM32WL5_FLASH_OPTR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_OPTR_OFFSET) -#define STM32WL5_FLASH_PCROP1ASR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1ASR_OFFSET) -#define STM32WL5_FLASH_PCROP1AER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1AER_OFFSET) -#define STM32WL5_FLASH_WRP1AR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1AR_OFFSET) -#define STM32WL5_FLASH_WRP1BR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_WRP1BR_OFFSET) -#define STM32WL5_FLASH_PCROP1BSR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BSR_OFFSET) -#define STM32WL5_FLASH_PCROP1BER (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_PCROP1BER_OFFSET) -#define STM32WL5_FLASH_IPCCBR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_IPCCBR_OFFSET) -#define STM32WL5_FLASH_C2ACR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2ACR_OFFSET) -#define STM32WL5_FLASH_C2SR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2SR_OFFSET) -#define STM32WL5_FLASH_C2CR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_C2CR_OFFSET) -#define STM32WL5_FLASH_SFR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SFR_OFFSET) -#define STM32WL5_FLASH_SRRVR (STM32WL5_FLASHIF_BASE+STM32WL5_FLASH_SRRVR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_ACR2 (STM32_FLASHIF_BASE+STM32_FLASH_ACR2_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_ECCR (STM32_FLASHIF_BASE+STM32_FLASH_ECCR_OFFSET) +#define STM32_FLASH_OPTR (STM32_FLASHIF_BASE+STM32_FLASH_OPTR_OFFSET) +#define STM32_FLASH_PCROP1ASR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ASR_OFFSET) +#define STM32_FLASH_PCROP1AER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1AER_OFFSET) +#define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) +#define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) +#define STM32_FLASH_PCROP1BSR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BSR_OFFSET) +#define STM32_FLASH_PCROP1BER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1BER_OFFSET) +#define STM32_FLASH_IPCCBR (STM32_FLASHIF_BASE+STM32_FLASH_IPCCBR_OFFSET) +#define STM32_FLASH_C2ACR (STM32_FLASHIF_BASE+STM32_FLASH_C2ACR_OFFSET) +#define STM32_FLASH_C2SR (STM32_FLASHIF_BASE+STM32_FLASH_C2SR_OFFSET) +#define STM32_FLASH_C2CR (STM32_FLASHIF_BASE+STM32_FLASH_C2CR_OFFSET) +#define STM32_FLASH_SFR (STM32_FLASHIF_BASE+STM32_FLASH_SFR_OFFSET) +#define STM32_FLASH_SRRVR (STM32_FLASHIF_BASE+STM32_FLASH_SRRVR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h index 9f76cb4efa0..3bd6a33c9fd 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_gpio.h @@ -36,71 +36,71 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ -#define STM32WL5_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ -#define STM32WL5_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ -#define STM32WL5_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ -#define STM32WL5_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ -#define STM32WL5_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ -#define STM32WL5_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ -#define STM32WL5_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ -#define STM32WL5_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ -#define STM32WL5_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ -#define STM32WL5_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ +#define STM32_GPIO_MODER_OFFSET 0x0000 /* GPIO port mode register */ +#define STM32_GPIO_OTYPER_OFFSET 0x0004 /* GPIO port output type register */ +#define STM32_GPIO_OSPEED_OFFSET 0x0008 /* GPIO port output speed register */ +#define STM32_GPIO_PUPDR_OFFSET 0x000c /* GPIO port pull-up/pull-down register */ +#define STM32_GPIO_IDR_OFFSET 0x0010 /* GPIO port input data register */ +#define STM32_GPIO_ODR_OFFSET 0x0014 /* GPIO port output data register */ +#define STM32_GPIO_BSRR_OFFSET 0x0018 /* GPIO port bit set/reset register */ +#define STM32_GPIO_LCKR_OFFSET 0x001c /* GPIO port configuration lock register */ +#define STM32_GPIO_AFRL_OFFSET 0x0020 /* GPIO alternate function low register */ +#define STM32_GPIO_AFRH_OFFSET 0x0024 /* GPIO alternate function high register */ +#define STM32_GPIO_BRR_OFFSET 0x0028 /* GPIO port bit reset register */ /* Register Addresses *******************************************************/ -#define STM32WL5_GPIOA_MODER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOA_OTYPER (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOA_OSPEED (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOA_PUPDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOA_IDR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOA_ODR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOA_BSRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOA_LCKR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOA_AFRL (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOA_AFRH (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOA_BRR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOA_ASCR (STM32WL5_GPIOA_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOA_MODER (STM32_GPIOA_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOA_PUPDR (STM32_GPIOA_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOA_AFRL (STM32_GPIOA_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOA_AFRH (STM32_GPIOA_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOA_ASCR (STM32_GPIOA_BASE+STM32_GPIO_ASCR_OFFSET) -#define STM32WL5_GPIOB_MODER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOB_OTYPER (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOB_OSPEED (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOB_PUPDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOB_IDR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOB_ODR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOB_BSRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOB_LCKR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOB_AFRL (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOB_AFRH (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOB_BRR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOB_ASCR (STM32WL5_GPIOB_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOB_MODER (STM32_GPIOB_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOB_PUPDR (STM32_GPIOB_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOB_AFRL (STM32_GPIOB_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOB_AFRH (STM32_GPIOB_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOB_ASCR (STM32_GPIOB_BASE+STM32_GPIO_ASCR_OFFSET) -#define STM32WL5_GPIOC_MODER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOC_OTYPER (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOC_OSPEED (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOC_PUPDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOC_IDR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOC_ODR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOC_BSRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOC_LCKR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOC_AFRL (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOC_AFRH (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOC_BRR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOC_ASCR (STM32WL5_GPIOC_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOC_MODER (STM32_GPIOC_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOC_PUPDR (STM32_GPIOC_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOC_AFRL (STM32_GPIOC_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOC_AFRH (STM32_GPIOC_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOC_ASCR (STM32_GPIOC_BASE+STM32_GPIO_ASCR_OFFSET) -#define STM32WL5_GPIOH_MODER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_MODER_OFFSET) -#define STM32WL5_GPIOH_OTYPER (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OTYPER_OFFSET) -#define STM32WL5_GPIOH_OSPEED (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_OSPEED_OFFSET) -#define STM32WL5_GPIOH_PUPDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_PUPDR_OFFSET) -#define STM32WL5_GPIOH_IDR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_IDR_OFFSET) -#define STM32WL5_GPIOH_ODR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ODR_OFFSET) -#define STM32WL5_GPIOH_BSRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BSRR_OFFSET) -#define STM32WL5_GPIOH_LCKR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_LCKR_OFFSET) -#define STM32WL5_GPIOH_AFRL (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRL_OFFSET) -#define STM32WL5_GPIOH_AFRH (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_AFRH_OFFSET) -#define STM32WL5_GPIOH_BRR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_BRR_OFFSET) -#define STM32WL5_GPIOH_ASCR (STM32WL5_GPIOH_BASE+STM32WL5_GPIO_ASCR_OFFSET) +#define STM32_GPIOH_MODER (STM32_GPIOH_BASE+STM32_GPIO_MODER_OFFSET) +#define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE+STM32_GPIO_OTYPER_OFFSET) +#define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE+STM32_GPIO_OSPEED_OFFSET) +#define STM32_GPIOH_PUPDR (STM32_GPIOH_BASE+STM32_GPIO_PUPDR_OFFSET) +#define STM32_GPIOH_IDR (STM32_GPIOH_BASE+STM32_GPIO_IDR_OFFSET) +#define STM32_GPIOH_ODR (STM32_GPIOH_BASE+STM32_GPIO_ODR_OFFSET) +#define STM32_GPIOH_BSRR (STM32_GPIOH_BASE+STM32_GPIO_BSRR_OFFSET) +#define STM32_GPIOH_LCKR (STM32_GPIOH_BASE+STM32_GPIO_LCKR_OFFSET) +#define STM32_GPIOH_AFRL (STM32_GPIOH_BASE+STM32_GPIO_AFRL_OFFSET) +#define STM32_GPIOH_AFRH (STM32_GPIOH_BASE+STM32_GPIO_AFRH_OFFSET) +#define STM32_GPIOH_BRR (STM32_GPIOH_BASE+STM32_GPIO_BRR_OFFSET) +#define STM32_GPIOH_ASCR (STM32_GPIOH_BASE+STM32_GPIO_ASCR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h index 56632c5a936..35acf09fc6e 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_ipcc.h @@ -34,48 +34,48 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_IPCC_CPU1_OFFSET 0x00 -#define STM32WL5_IPCC_CPU2_OFFSET 0x10 +#define STM32_IPCC_CPU1_OFFSET 0x00 +#define STM32_IPCC_CPU2_OFFSET 0x10 /* Register Offsets *********************************************************/ -#define STM32WL5_IPCC_CR_OFFSET 0x00 /* IPCC control register */ -#define STM32WL5_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ -#define STM32WL5_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ -#define STM32WL5_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ +#define STM32_IPCC_CR_OFFSET 0x00 /* IPCC control register */ +#define STM32_IPCC_MR_OFFSET 0x04 /* IPCC mask register */ +#define STM32_IPCC_SCR_OFFSET 0x08 /* IPCC status set clear register */ +#define STM32_IPCC_CTOCSR_OFFSET 0x0c /* IPCC processor to processor status register */ /* Register Addresses *******************************************************/ -#define STM32WL5_IPCC_C1CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C1TOC2SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU1_OFFSET) -#define STM32WL5_IPCC_C2CR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2MR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_MR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2SCR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_SCR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) -#define STM32WL5_IPCC_C2TOC1SR (STM32WL5_IPCC_BASE+STM32WL5_IPCC_CTOCSR_OFFSET+STM32WL5_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C1CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C1TOC2SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU1_OFFSET) +#define STM32_IPCC_C2CR (STM32_IPCC_BASE+STM32_IPCC_CR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2MR (STM32_IPCC_BASE+STM32_IPCC_MR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2SCR (STM32_IPCC_BASE+STM32_IPCC_SCR_OFFSET+STM32_IPCC_CPU2_OFFSET) +#define STM32_IPCC_C2TOC1SR (STM32_IPCC_BASE+STM32_IPCC_CTOCSR_OFFSET+STM32_IPCC_CPU2_OFFSET) /* Register Bitfield Definitions ********************************************/ -#define STM32WL5_IPCC_TX_SHIFT (16) /* TX shift for all registers */ +#define STM32_IPCC_TX_SHIFT (16) /* TX shift for all registers */ /* IPCC control register */ -#define STM32WL5_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ -#define STM32WL5_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ +#define STM32_IPCC_CR_RXOIE (1 << 0) /* Bit 0: Receive channel occupied interrupt enable */ +#define STM32_IPCC_CR_TXFIE (1 << 16) /* Bit 16: Transmit channel free interrupt enable */ /* IPCC mask register */ -#define STM32WL5_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ -#define STM32WL5_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNOM(n) (1 << (n)) /* Bit 0..5: Receive channel n occupied interrupt enable, Channels 0..5 */ +#define STM32_IPCC_MR_CHNFM(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n free interrupt enable, Channels 0..5 */ /* IPCC status set clear register */ -#define STM32WL5_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ -#define STM32WL5_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNC(n) (1 << (n)) /* Bit 0..5: Receive channel n status bit clear, Channels 0..5 */ +#define STM32_IPCC_SCR_CHNS(n) (1 << (16 + (n))) /* Bit 16..21: Transmit channel n status bit set, Channels 0..5 */ /* IPCC processor to processor status register */ -#define STM32WL5_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ +#define STM32_IPCC_CTOCSR_CHNF(n) (1 << (n)) /* Bit 0..5: Channel n occupied, Channels 0..5 */ #endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h index 89df326775b..a51e3624142 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_memorymap.h @@ -29,40 +29,40 @@ /* STM32WL5XXX Address Blocks ***********************************************/ -#define STM32WL5_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ -#define STM32WL5_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ -#define STM32WL5_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ - /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ -#define STM32WL5_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ +#define STM32_CODE_BASE 0x00000000 /* 0x0000 0000-0x1fff ffff: 512Mb code block */ +#define STM32_SRAM_BASE 0x20000000 /* 0x2000 0000-0x3fff ffff: 512Mb sram block (48k to 256k) */ +#define STM32_PERIPH_BASE 0x40000000 /* 0x4000 0000-0x5fff ffff: 512Mb peripheral block */ + /* 0x6000 0000-0xdfff ffff: 2048Mb (not used) */ +#define STM32_CORTEX_BASE 0xe0000000 /* 0xe000 0000-0xffff ffff: 512Mb Cortex-M4/M0 block */ -#define STM32WL5_REGION_MASK 0xf0000000 -#define STM32WL5_IS_SRAM(a) ((((uint32_t)(a)) & STM32WL5_REGION_MASK) == STM32WL5_SRAM_BASE) +#define STM32_REGION_MASK 0xf0000000 +#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE) /* Code Base Addresses ******************************************************/ -#define STM32WL5_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ - /* 0x0004 0000-0x07ff ffff: Reserved */ -#define STM32WL5_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ - /* 0x0804 0000-0x0fff ffff: Reserved */ -#define STM32WL5_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ - /* 0x1000 0000-0x1ffe 6fff: Reserved */ -#define STM32WL5_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ -#define STM32WL5_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ -#define STM32WL5_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ -#define STM32WL5_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ - /* 0x1fff 8000-0x1fff ffff: reserved */ -#define STM32WL5_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ +#define STM32_BOOT_BASE 0x00000000 /* 0x0000 0000-0x0003 ffff: Aliased boot memory */ + /* 0x0004 0000-0x07ff ffff: Reserved */ +#define STM32_FLASH_BASE 0x08000000 /* 0x0800 0000-0x0803 ffff: FLASH memory */ + /* 0x0804 0000-0x0fff ffff: Reserved */ +#define STM32_FLASH_MASK 0xf8000000 /* Test if addr in FLASH */ + /* 0x1000 0000-0x1ffe 6fff: Reserved */ +#define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff 0000-0x1fff 6fff: System memory */ +#define STM32_OTP_BASE 0x1fff7000 /* 0x1fff 7000-0x1fff 73ff: 1k otp memory */ +#define STM32_ENGI_BASE 0x1fff7400 /* 0x1fff 7400-0x1fff 77ff: 1k engi flash */ +#define STM32_OPTION_BASE 0x1fff7800 /* 0x1fff 7800-0x1fff 7fff: 2k flash user options */ + /* 0x1fff 8000-0x1fff ffff: reserved */ +#define STM32_SRAM2_BASE 0x20008000 /* 0x2000 8000-0x2000 ffff: 32k SRAM2 */ /* System Memory Addresses **************************************************/ -#define STM32WL5_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package +#define STM32_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package * type. * 0: UFBGA73 * 2: WLCSP59 * 10: UFQFPN48 */ -#define STM32WL5_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#define STM32WL5_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of +#define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ +#define STM32_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of * the device Flash memory expressed in * Kbytes. Example: 0x0400 corresponds * to 1024 Kbytes. @@ -70,92 +70,92 @@ /* SRAM Base Addresses ******************************************************/ -#define STM32WL5_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ +#define STM32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */ /* Peripheral Base Addresses ************************************************/ -#define STM32WL5_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ - /* 0x4000 B400-0x4000 ffff: Reserved */ -#define STM32WL5_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ - /* 0x4001 4c00-0x4001 ffff: Reserved */ -#define STM32WL5_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ - /* 0x4260 0000-0x47ff ffff: Reserved */ -#define STM32WL5_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ - /* 0x4800 2000-0x57ff ffff: Reserved */ -#define STM32WL5_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ - /* 0x5800 40c0-0x5800 ffff: Reserved */ +#define STM32_APB1_BASE 0x40000000 /* 0x4000 0000-0x4000 b3ff: APB1 */ + /* 0x4000 B400-0x4000 ffff: Reserved */ +#define STM32_APB2_BASE 0x40010000 /* 0x4001 0000-0x4001 4bff: APB2 */ + /* 0x4001 4c00-0x4001 ffff: Reserved */ +#define STM32_AHB1_BASE 0x40020000 /* 0x4002 0000-0x425f ffff: APB1 */ + /* 0x4260 0000-0x47ff ffff: Reserved */ +#define STM32_AHB2_BASE 0x48000000 /* 0x4800 0000-0x4800 1fff: AHB2 */ + /* 0x4800 2000-0x57ff ffff: Reserved */ +#define STM32_AHB3_BASE 0x58000000 /* 0x5800 0000-0x5800 4bff: AHB3 */ + /* 0x5800 40c0-0x5800 ffff: Reserved */ /* Radio Base Addresses *****************************************************/ -#define STM32WL5_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ - /* 0x5801 0400-0x5801 ffff: Reserved */ +#define STM32_APB3_BASE 0x58010000 /* 0x5801 0000-0x5801 03ff: APB3 */ + /* 0x5801 0400-0x5801 ffff: Reserved */ /* in datasheet order */ /* APB1 Base Addresses ******************************************************/ -#define STM32WL5_TAMP_BASE 0x4000B000 -#define STM32WL5_LPTIM3_BASE 0x40009800 -#define STM32WL5_LPTIM2_BASE 0x40009400 -#define STM32WL5_LPUART1_BASE 0x40008000 -#define STM32WL5_LPTIM1_BASE 0x40007C00 -#define STM32WL5_DAC_BASE 0x40007400 -#define STM32WL5_I2C3_BASE 0x40005C00 -#define STM32WL5_I2C2_BASE 0x40005800 -#define STM32WL5_I2C1_BASE 0x40005400 -#define STM32WL5_USART2_BASE 0x40004400 -#define STM32WL5_SPI2S2_BASE 0x40003800 -#define STM32WL5_IWDG_BASE 0x40003000 -#define STM32WL5_WWDG_BASE 0x40002C00 -#define STM32WL5_RTC_BASE 0x40002800 -#define STM32WL5_TIM2_BASE 0x40000000 +#define STM32_TAMP_BASE 0x4000B000 +#define STM32_LPTIM3_BASE 0x40009800 +#define STM32_LPTIM2_BASE 0x40009400 +#define STM32_LPUART1_BASE 0x40008000 +#define STM32_LPTIM1_BASE 0x40007C00 +#define STM32_DAC_BASE 0x40007400 +#define STM32_I2C3_BASE 0x40005C00 +#define STM32_I2C2_BASE 0x40005800 +#define STM32_I2C1_BASE 0x40005400 +#define STM32_USART2_BASE 0x40004400 +#define STM32_SPI2S2_BASE 0x40003800 +#define STM32_IWDG_BASE 0x40003000 +#define STM32_WWDG_BASE 0x40002C00 +#define STM32_RTC_BASE 0x40002800 +#define STM32_TIM2_BASE 0x40000000 /* APB2 Base Addresses ******************************************************/ -#define STM32WL5_TIM17_BASE 0x40014800 -#define STM32WL5_TIM16_BASE 0x40014400 -#define STM32WL5_USART1_BASE 0x40013800 -#define STM32WL5_SPI1_BASE 0x40013000 -#define STM32WL5_TIM1_BASE 0x40012C00 -#define STM32WL5_ADC_BASE 0x40012400 -#define STM32WL5_COMP_BASE 0x40010200 -#define STM32WL5_SYSCFG2_BASE 0x40010100 -#define STM32WL5_VREFBUF_BASE 0x40010030 -#define STM32WL5_SYSCFG_BASE 0x40010000 +#define STM32_TIM17_BASE 0x40014800 +#define STM32_TIM16_BASE 0x40014400 +#define STM32_USART1_BASE 0x40013800 +#define STM32_SPI1_BASE 0x40013000 +#define STM32_TIM1_BASE 0x40012C00 +#define STM32_ADC_BASE 0x40012400 +#define STM32_COMP_BASE 0x40010200 +#define STM32_SYSCFG2_BASE 0x40010100 +#define STM32_VREFBUF_BASE 0x40010030 +#define STM32_SYSCFG_BASE 0x40010000 /* AHB1 Base Addresses ******************************************************/ -#define STM32WL5_CRC_BASE 0x40023000 -#define STM32WL5_DMAMUX1_BASE 0x40200800 -#define STM32WL5_DMA2_BASE 0x40200400 -#define STM32WL5_DMA1_BASE 0x40020000 +#define STM32_CRC_BASE 0x40023000 +#define STM32_DMAMUX1_BASE 0x40200800 +#define STM32_DMA2_BASE 0x40200400 +#define STM32_DMA1_BASE 0x40020000 /* AHB2 Base Addresses ******************************************************/ -#define STM32WL5_GPIOH_BASE 0x48001C00 -#define STM32WL5_GPIOC_BASE 0x48000800 -#define STM32WL5_GPIOB_BASE 0x48000400 -#define STM32WL5_GPIOA_BASE 0x48000000 +#define STM32_GPIOH_BASE 0x48001C00 +#define STM32_GPIOC_BASE 0x48000800 +#define STM32_GPIOB_BASE 0x48000400 +#define STM32_GPIOA_BASE 0x48000000 /* AHB3 Base Addresses ******************************************************/ -#define STM32WL5_GTZC_TZIC_BASE 0x58004800 -#define STM32WL5_GTZC_TZSC_BASE 0x58004400 -#define STM32WL5_FLASHIF_BASE 0x58004000 -#define STM32WL5_PKA2_BASE 0x58003400 -#define STM32WL5_PKARAM_BASE 0x58002400 -#define STM32WL5_PKA_BASE 0x58002000 -#define STM32WL5_AES_BASE 0x58001800 -#define STM32WL5_HSEM_BASE 0x58001400 -#define STM32WL5_RNG_BASE 0x58001000 -#define STM32WL5_IPCC_BASE 0x58000C00 -#define STM32WL5_EXTI_BASE 0x58000800 -#define STM32WL5_PWR_BASE 0x58000400 -#define STM32WL5_RCC_BASE 0x58000000 +#define STM32_GTZC_TZIC_BASE 0x58004800 +#define STM32_GTZC_TZSC_BASE 0x58004400 +#define STM32_FLASHIF_BASE 0x58004000 +#define STM32_PKA2_BASE 0x58003400 +#define STM32_PKARAM_BASE 0x58002400 +#define STM32_PKA_BASE 0x58002000 +#define STM32_AES_BASE 0x58001800 +#define STM32_HSEM_BASE 0x58001400 +#define STM32_RNG_BASE 0x58001000 +#define STM32_IPCC_BASE 0x58000C00 +#define STM32_EXTI_BASE 0x58000800 +#define STM32_PWR_BASE 0x58000400 +#define STM32_RCC_BASE 0x58000000 /* APB3 Base Addresses ******************************************************/ -#define STM32WL5_SUBGHZSPI_BASE 0x58010000 +#define STM32_SUBGHZSPI_BASE 0x58010000 /* Cortex-M4 Base Addresses *************************************************/ @@ -163,7 +163,7 @@ * this address range */ -#define STM32WL5_SCS_BASE 0xe000e000 -#define STM32WL5_DEBUGMCU_BASE 0xe0042000 +#define STM32_SCS_BASE 0xe000e000 +#define STM32_DEBUGMCU_BASE 0xe0042000 #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h index 978e931a4d5..2d6e28db628 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_pwr.h @@ -36,53 +36,53 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ -#define STM32WL5_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ -#define STM32WL5_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ -#define STM32WL5_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ -#define STM32WL5_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ -#define STM32WL5_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ -#define STM32WL5_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ -#define STM32WL5_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ -#define STM32WL5_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ -#define STM32WL5_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ -#define STM32WL5_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ -#define STM32WL5_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ -#define STM32WL5_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ -#define STM32WL5_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ -#define STM32WL5_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ -#define STM32WL5_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ -#define STM32WL5_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ -#define STM32WL5_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ -#define STM32WL5_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ -#define STM32WL5_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ -#define STM32WL5_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ -#define STM32WL5_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0004 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x0008 /* Power control register 3 */ +#define STM32_PWR_CR4_OFFSET 0x000C /* Power control register 4 */ +#define STM32_PWR_SR1_OFFSET 0x0010 /* Power status register 1 */ +#define STM32_PWR_SR2_OFFSET 0x0014 /* Power status register 2 */ +#define STM32_PWR_SCR_OFFSET 0x0018 /* Power status clear register */ +#define STM32_PWR_CR5_OFFSET 0x001C /* Power control register 5 */ +#define STM32_PWR_PUCRA_OFFSET 0x0020 /* Power Port A pull-up control register */ +#define STM32_PWR_PDCRA_OFFSET 0x0024 /* Power Port A pull-down control register */ +#define STM32_PWR_PUCRB_OFFSET 0x0028 /* Power Port B pull-up control register */ +#define STM32_PWR_PDCRB_OFFSET 0x002C /* Power Port B pull-down control register */ +#define STM32_PWR_PUCRC_OFFSET 0x0030 /* Power Port C pull-up control register */ +#define STM32_PWR_PDCRC_OFFSET 0x0034 /* Power Port C pull-down control register */ +#define STM32_PWR_PUCRH_OFFSET 0x0058 /* Power Port H pull-up control register */ +#define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ +#define STM32_PWR_C2CR1_OFFSET 0x0080 /* Power control register 1 for cpu2 */ +#define STM32_PWR_C2CR3_OFFSET 0x0084 /* Power control register 3 for cpu2 */ +#define STM32_PWR_EXTSCR_OFFSET 0x0088 /* Power extended status */ +#define STM32_PWR_SECCFGR_OFFSET 0x0088 /* Power security configuration */ +#define STM32_PWR_SUBGHZSPICR_OFFSET 0x0088 /* Power sub-ghz spi radio control */ +#define STM32_PWR_RSSCMDR_OFFSET 0x0088 /* Power RSS command */ /* Register Addresses *******************************************************/ -#define STM32WL5_PWR_CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR1_OFFSET) -#define STM32WL5_PWR_CR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR2_OFFSET) -#define STM32WL5_PWR_CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR3_OFFSET) -#define STM32WL5_PWR_CR4 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR4_OFFSET) -#define STM32WL5_PWR_SR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR1_OFFSET) -#define STM32WL5_PWR_SR2 (STM32WL5_PWR_BASE+STM32WL5_PWR_SR2_OFFSET) -#define STM32WL5_PWR_SCR (STM32WL5_PWR_BASE+STM32WL5_PWR_SCR_OFFSET) -#define STM32WL5_PWR_CR5 (STM32WL5_PWR_BASE+STM32WL5_PWR_CR5_OFFSET) -#define STM32WL5_PWR_PUCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRA_OFFSET) -#define STM32WL5_PWR_PDCRA (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRA_OFFSET) -#define STM32WL5_PWR_PUCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRB_OFFSET) -#define STM32WL5_PWR_PDCRB (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRB_OFFSET) -#define STM32WL5_PWR_PUCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRC_OFFSET) -#define STM32WL5_PWR_PDCRC (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRC_OFFSET) -#define STM32WL5_PWR_PUCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PUCRH_OFFSET) -#define STM32WL5_PWR_PDCRH (STM32WL5_PWR_BASE+STM32WL5_PWR_PDCRH_OFFSET) -#define STM32WL5_PWR_C2CR1 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR1_OFFSET) -#define STM32WL5_PWR_C2CR3 (STM32WL5_PWR_BASE+STM32WL5_PWR_C2CR3_OFFSET) -#define STM32WL5_PWR_EXTSCR (STM32WL5_PWR_BASE+STM32WL5_PWR_EXTSCR_OFFSET) -#define STM32WL5_PWR_SECCFGR (STM32WL5_PWR_BASE+STM32WL5_PWR_SECCFGR_OFFSET) -#define STM32WL5_PWR_SUBGHZSPICR (STM32WL5_PWR_BASE+STM32WL5_PWR_SUBGHZSPICR_OFFSET) -#define STM32WL5_PWR_RSSCMDR (STM32WL5_PWR_BASE+STM32WL5_PWR_RSSCMDR_OFFSET) +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CR4 (STM32_PWR_BASE+STM32_PWR_CR4_OFFSET) +#define STM32_PWR_SR1 (STM32_PWR_BASE+STM32_PWR_SR1_OFFSET) +#define STM32_PWR_SR2 (STM32_PWR_BASE+STM32_PWR_SR2_OFFSET) +#define STM32_PWR_SCR (STM32_PWR_BASE+STM32_PWR_SCR_OFFSET) +#define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) +#define STM32_PWR_PUCRA (STM32_PWR_BASE+STM32_PWR_PUCRA_OFFSET) +#define STM32_PWR_PDCRA (STM32_PWR_BASE+STM32_PWR_PDCRA_OFFSET) +#define STM32_PWR_PUCRB (STM32_PWR_BASE+STM32_PWR_PUCRB_OFFSET) +#define STM32_PWR_PDCRB (STM32_PWR_BASE+STM32_PWR_PDCRB_OFFSET) +#define STM32_PWR_PUCRC (STM32_PWR_BASE+STM32_PWR_PUCRC_OFFSET) +#define STM32_PWR_PDCRC (STM32_PWR_BASE+STM32_PWR_PDCRC_OFFSET) +#define STM32_PWR_PUCRH (STM32_PWR_BASE+STM32_PWR_PUCRH_OFFSET) +#define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) +#define STM32_PWR_C2CR1 (STM32_PWR_BASE+STM32_PWR_C2CR1_OFFSET) +#define STM32_PWR_C2CR3 (STM32_PWR_BASE+STM32_PWR_C2CR3_OFFSET) +#define STM32_PWR_EXTSCR (STM32_PWR_BASE+STM32_PWR_EXTSCR_OFFSET) +#define STM32_PWR_SECCFGR (STM32_PWR_BASE+STM32_PWR_SECCFGR_OFFSET) +#define STM32_PWR_SUBGHZSPICR (STM32_PWR_BASE+STM32_PWR_SUBGHZSPICR_OFFSET) +#define STM32_PWR_RSSCMDR (STM32_PWR_BASE+STM32_PWR_RSSCMDR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h index 3f7309342f3..987fed3348f 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_rcc.h @@ -35,95 +35,95 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_RCC_CR_OFFSET 0x0000 /* Clock control register */ -#define STM32WL5_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ -#define STM32WL5_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ -#define STM32WL5_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ -#define STM32WL5_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ -#define STM32WL5_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ -#define STM32WL5_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ -#define STM32WL5_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ -#define STM32WL5_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ -#define STM32WL5_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ -#define STM32WL5_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ -#define STM32WL5_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ -#define STM32WL5_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ -#define STM32WL5_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ -#define STM32WL5_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ -#define STM32WL5_RCC_CSR_OFFSET 0x0094 /* Control/status register */ -#define STM32WL5_RCC_EXTCFGR_OFFSET 0x0108 -#define STM32WL5_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ -#define STM32WL5_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ -#define STM32WL5_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ -#define STM32WL5_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ -#define STM32WL5_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ -#define STM32WL5_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ -#define STM32WL5_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ +#define STM32_RCC_CR_OFFSET 0x0000 /* Clock control register */ +#define STM32_RCC_ICSCR_OFFSET 0x0004 /* Internal clock sources calibration register */ +#define STM32_RCC_CFGR_OFFSET 0x0008 /* Clock configuration register */ +#define STM32_RCC_PLLCFG_OFFSET 0x000c /* PLL configuration register */ +#define STM32_RCC_CIER_OFFSET 0x0018 /* Clock interrupt enable register */ +#define STM32_RCC_CIFR_OFFSET 0x001c /* Clock interrupt flag register */ +#define STM32_RCC_CICR_OFFSET 0x0020 /* Clock interrupt clear register */ +#define STM32_RCC_AHB1RSTR_OFFSET 0x0028 /* AHB1 peripheral reset register */ +#define STM32_RCC_AHB2RSTR_OFFSET 0x002c /* AHB2 peripheral reset register */ +#define STM32_RCC_AHB3RSTR_OFFSET 0x0030 /* AHB3 peripheral reset register */ +#define STM32_RCC_APB1RSTR1_OFFSET 0x0038 /* APB1 Peripheral reset register 1 */ +#define STM32_RCC_APB1RSTR2_OFFSET 0x003c /* APB1 Peripheral reset register 2 */ +#define STM32_RCC_APB2RSTR_OFFSET 0x0040 /* APB2 Peripheral reset register */ +#define STM32_RCC_AHB1ENR_OFFSET 0x0048 /* AHB1 Peripheral Clock enable register */ +#define STM32_RCC_AHB2ENR_OFFSET 0x004c /* AHB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB3ENR_OFFSET 0x0050 /* AHB3 Peripheral Clock enable register */ +#define STM32_RCC_APB1ENR1_OFFSET 0x0058 /* APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_APB1ENR2_OFFSET 0x005c /* APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_APB2ENR_OFFSET 0x0060 /* APB2 Peripheral Clock enable register */ +#define STM32_RCC_AHB1SMENR_OFFSET 0x0068 /* RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB2SMENR_OFFSET 0x006c /* RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_AHB3SMENR_OFFSET 0x0070 /* RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_APB1SMENR1_OFFSET 0x0078 /* RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_APB1SMENR2_OFFSET 0x007c /* RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_APB2SMENR_OFFSET 0x0080 /* RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_CCIPR_OFFSET 0x0088 /* Peripherals independent clock configuration register 1 */ +#define STM32_RCC_BDCR_OFFSET 0x0090 /* Backup domain control register */ +#define STM32_RCC_CSR_OFFSET 0x0094 /* Control/status register */ +#define STM32_RCC_EXTCFGR_OFFSET 0x0108 +#define STM32_RCC_C2AHB1ENR_OFFSET 0x0148 /* CPU2 AHB1 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB2ENR_OFFSET 0x014c /* CPU2 AHB2 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB3ENR_OFFSET 0x0150 /* CPU2 AHB3 Peripheral Clock enable register */ +#define STM32_RCC_C2APB1ENR1_OFFSET 0x0158 /* CPU2 APB1 Peripheral Clock enable register 1 */ +#define STM32_RCC_C2APB1ENR2_OFFSET 0x015c /* CPU2 APB1 Peripheral Clock enable register 2 */ +#define STM32_RCC_C2APB2ENR_OFFSET 0x0160 /* CPU2 APB2 Peripheral Clock enable register */ +#define STM32_RCC_C2APB3ENR_OFFSET 0x0164 /* CPU2 APB3 Peripheral Clock enable register */ +#define STM32_RCC_C2AHB1SMENR_OFFSET 0x0168 /* CPU2 RCC AHB1 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB2SMENR_OFFSET 0x016c /* CPU2 RCC AHB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2AHB3SMENR_OFFSET 0x0170 /* CPU2 RCC AHB3 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB1SMENR1_OFFSET 0x0178 /* CPU2 RCC APB1 low power mode peripheral clock enable register 1 */ +#define STM32_RCC_C2APB1SMENR2_OFFSET 0x017c /* CPU2 RCC APB1 low power mode peripheral clock enable register 2 */ +#define STM32_RCC_C2APB2SMENR_OFFSET 0x0180 /* CPU2 RCC APB2 low power mode peripheral clock enable register */ +#define STM32_RCC_C2APB3SMENR_OFFSET 0x0184 /* CPU2 RCC APB3 low power mode peripheral clock enable register */ /* Register Addresses *******************************************************/ -#define STM32WL5_RCC_CR (STM32WL5_RCC_BASE + STM32WL5_RCC_CR_OFFSET) -#define STM32WL5_RCC_ICSCR (STM32WL5_RCC_BASE + STM32WL5_RCC_ICSCR_OFFSET) -#define STM32WL5_RCC_CFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_CFGR_OFFSET) -#define STM32WL5_RCC_PLLCFG (STM32WL5_RCC_BASE + STM32WL5_RCC_PLLCFG_OFFSET) -#define STM32WL5_RCC_CIER (STM32WL5_RCC_BASE + STM32WL5_RCC_CIER_OFFSET) -#define STM32WL5_RCC_CIFR (STM32WL5_RCC_BASE + STM32WL5_RCC_CIFR_OFFSET) -#define STM32WL5_RCC_CICR (STM32WL5_RCC_BASE + STM32WL5_RCC_CICR_OFFSET) -#define STM32WL5_RCC_AHB1RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1RSTR_OFFSET) -#define STM32WL5_RCC_AHB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB3RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3RSTR_OFFSET) -#define STM32WL5_RCC_APB1RSTR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR1_OFFSET) -#define STM32WL5_RCC_APB1RSTR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1RSTR2_OFFSET) -#define STM32WL5_RCC_APB2RSTR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2RSTR_OFFSET) -#define STM32WL5_RCC_AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1ENR_OFFSET) -#define STM32WL5_RCC_AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2ENR_OFFSET) -#define STM32WL5_RCC_AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3ENR_OFFSET) -#define STM32WL5_RCC_APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR1_OFFSET) -#define STM32WL5_RCC_APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1ENR2_OFFSET) -#define STM32WL5_RCC_APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2ENR_OFFSET) -#define STM32WL5_RCC_AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB1SMENR_OFFSET) -#define STM32WL5_RCC_AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB2SMENR_OFFSET) -#define STM32WL5_RCC_AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_AHB3SMENR_OFFSET) -#define STM32WL5_RCC_APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR1_OFFSET) -#define STM32WL5_RCC_APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_APB1SMENR2_OFFSET) -#define STM32WL5_RCC_APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_APB2SMENR_OFFSET) -#define STM32WL5_RCC_CCIPR (STM32WL5_RCC_BASE + STM32WL5_RCC_CCIPR_OFFSET) -#define STM32WL5_RCC_BDCR (STM32WL5_RCC_BASE + STM32WL5_RCC_BDCR_OFFSET) -#define STM32WL5_RCC_CSR (STM32WL5_RCC_BASE + STM32WL5_RCC_CSR_OFFSET) -#define STM32WL5_RCC_EXTCFGR (STM32WL5_RCC_BASE + STM32WL5_RCC_EXTCFGR_OFFSET) -#define STM32WL5_RCC_C2AHB1ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1ENR_OFFSET) -#define STM32WL5_RCC_C2AHB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2ENR_OFFSET) -#define STM32WL5_RCC_C2AHB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3ENR_OFFSET) -#define STM32WL5_RCC_C2APB1ENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR1_OFFSET) -#define STM32WL5_RCC_C2APB1ENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1ENR2_OFFSET) -#define STM32WL5_RCC_C2APB2ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2ENR_OFFSET) -#define STM32WL5_RCC_C2APB3ENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3ENR_OFFSET) -#define STM32WL5_RCC_C2AHB1SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB1SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB2SMENR_OFFSET) -#define STM32WL5_RCC_C2AHB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2AHB3SMENR_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR1 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR1_OFFSET) -#define STM32WL5_RCC_C2APB1SMENR2 (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB1SMENR2_OFFSET) -#define STM32WL5_RCC_C2APB2SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB2SMENR_OFFSET) -#define STM32WL5_RCC_C2APB3SMENR (STM32WL5_RCC_BASE + STM32WL5_RCC_C2APB3SMENR_OFFSET) +#define STM32_RCC_CR (STM32_RCC_BASE + STM32_RCC_CR_OFFSET) +#define STM32_RCC_ICSCR (STM32_RCC_BASE + STM32_RCC_ICSCR_OFFSET) +#define STM32_RCC_CFGR (STM32_RCC_BASE + STM32_RCC_CFGR_OFFSET) +#define STM32_RCC_PLLCFG (STM32_RCC_BASE + STM32_RCC_PLLCFG_OFFSET) +#define STM32_RCC_CIER (STM32_RCC_BASE + STM32_RCC_CIER_OFFSET) +#define STM32_RCC_CIFR (STM32_RCC_BASE + STM32_RCC_CIFR_OFFSET) +#define STM32_RCC_CICR (STM32_RCC_BASE + STM32_RCC_CICR_OFFSET) +#define STM32_RCC_AHB1RSTR (STM32_RCC_BASE + STM32_RCC_AHB1RSTR_OFFSET) +#define STM32_RCC_AHB2RSTR (STM32_RCC_BASE + STM32_RCC_AHB2RSTR_OFFSET) +#define STM32_RCC_AHB3RSTR (STM32_RCC_BASE + STM32_RCC_AHB3RSTR_OFFSET) +#define STM32_RCC_APB1RSTR1 (STM32_RCC_BASE + STM32_RCC_APB1RSTR1_OFFSET) +#define STM32_RCC_APB1RSTR2 (STM32_RCC_BASE + STM32_RCC_APB1RSTR2_OFFSET) +#define STM32_RCC_APB2RSTR (STM32_RCC_BASE + STM32_RCC_APB2RSTR_OFFSET) +#define STM32_RCC_AHB1ENR (STM32_RCC_BASE + STM32_RCC_AHB1ENR_OFFSET) +#define STM32_RCC_AHB2ENR (STM32_RCC_BASE + STM32_RCC_AHB2ENR_OFFSET) +#define STM32_RCC_AHB3ENR (STM32_RCC_BASE + STM32_RCC_AHB3ENR_OFFSET) +#define STM32_RCC_APB1ENR1 (STM32_RCC_BASE + STM32_RCC_APB1ENR1_OFFSET) +#define STM32_RCC_APB1ENR2 (STM32_RCC_BASE + STM32_RCC_APB1ENR2_OFFSET) +#define STM32_RCC_APB2ENR (STM32_RCC_BASE + STM32_RCC_APB2ENR_OFFSET) +#define STM32_RCC_AHB1SMENR (STM32_RCC_BASE + STM32_RCC_AHB1SMENR_OFFSET) +#define STM32_RCC_AHB2SMENR (STM32_RCC_BASE + STM32_RCC_AHB2SMENR_OFFSET) +#define STM32_RCC_AHB3SMENR (STM32_RCC_BASE + STM32_RCC_AHB3SMENR_OFFSET) +#define STM32_RCC_APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_APB1SMENR1_OFFSET) +#define STM32_RCC_APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_APB1SMENR2_OFFSET) +#define STM32_RCC_APB2SMENR (STM32_RCC_BASE + STM32_RCC_APB2SMENR_OFFSET) +#define STM32_RCC_CCIPR (STM32_RCC_BASE + STM32_RCC_CCIPR_OFFSET) +#define STM32_RCC_BDCR (STM32_RCC_BASE + STM32_RCC_BDCR_OFFSET) +#define STM32_RCC_CSR (STM32_RCC_BASE + STM32_RCC_CSR_OFFSET) +#define STM32_RCC_EXTCFGR (STM32_RCC_BASE + STM32_RCC_EXTCFGR_OFFSET) +#define STM32_RCC_C2AHB1ENR (STM32_RCC_BASE + STM32_RCC_C2AHB1ENR_OFFSET) +#define STM32_RCC_C2AHB2ENR (STM32_RCC_BASE + STM32_RCC_C2AHB2ENR_OFFSET) +#define STM32_RCC_C2AHB3ENR (STM32_RCC_BASE + STM32_RCC_C2AHB3ENR_OFFSET) +#define STM32_RCC_C2APB1ENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR1_OFFSET) +#define STM32_RCC_C2APB1ENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1ENR2_OFFSET) +#define STM32_RCC_C2APB2ENR (STM32_RCC_BASE + STM32_RCC_C2APB2ENR_OFFSET) +#define STM32_RCC_C2APB3ENR (STM32_RCC_BASE + STM32_RCC_C2APB3ENR_OFFSET) +#define STM32_RCC_C2AHB1SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB1SMENR_OFFSET) +#define STM32_RCC_C2AHB2SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB2SMENR_OFFSET) +#define STM32_RCC_C2AHB3SMENR (STM32_RCC_BASE + STM32_RCC_C2AHB3SMENR_OFFSET) +#define STM32_RCC_C2APB1SMENR1 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR1_OFFSET) +#define STM32_RCC_C2APB1SMENR2 (STM32_RCC_BASE + STM32_RCC_C2APB1SMENR2_OFFSET) +#define STM32_RCC_C2APB2SMENR (STM32_RCC_BASE + STM32_RCC_C2APB2SMENR_OFFSET) +#define STM32_RCC_C2APB3SMENR (STM32_RCC_BASE + STM32_RCC_C2APB3SMENR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index 22c61af23ae..aaeac357315 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32WL5_HAVE_IP_SPI_V2) +#if defined(STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V3) +#if defined(STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32WL5_HAVE_IP_SPI_V4) +#if defined(STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -75,65 +75,65 @@ /* Maximum allowed speed as per specifications for all SPIs */ #if defined(CONFIG_STM32WL5_STM32F4XXX) -# define STM32WL5_SPI_CLK_MAX 37500000UL +# define STM32_SPI_CLK_MAX 37500000UL #else -# define STM32WL5_SPI_CLK_MAX 18000000UL +# define STM32_SPI_CLK_MAX 18000000UL #endif /* Register Offsets *********************************************************/ -#define STM32WL5_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ -#define STM32WL5_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ -#define STM32WL5_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ -#define STM32WL5_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ -#define STM32WL5_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ -#define STM32WL5_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ -#define STM32WL5_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ +#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */ +#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */ +#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */ +#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */ +#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */ +#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */ +#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */ #if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ -# define STM32WL5_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ +# define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */ +# define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */ #endif /* Register Addresses *******************************************************/ -#if STM32WL5_NSPI > 0 -# define STM32WL5_SPI1_CR1 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI1_CR2 \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI1_SR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI1_DR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI1_CRCPR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI1_RXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI1_TXCRCR \ - (STM32WL5_SPI1_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 0 +# define STM32_SPI1_CR1 \ + (STM32_SPI1_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI1_CR2 \ + (STM32_SPI1_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI1_SR \ + (STM32_SPI1_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI1_DR \ + (STM32_SPI1_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI1_CRCPR \ + (STM32_SPI1_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI1_RXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI1_TXCRCR \ + (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) #endif -#if STM32WL5_NSPI > 1 -# define STM32WL5_SPI2S2_CR1 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR1_OFFSET) -# define STM32WL5_SPI2S2_CR2 \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CR2_OFFSET) -# define STM32WL5_SPI2S2_SR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_SR_OFFSET) -# define STM32WL5_SPI2S2_DR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_DR_OFFSET) -# define STM32WL5_SPI2S2_CRCPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_CRCPR_OFFSET) -# define STM32WL5_SPI2S2_RXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_RXCRCR_OFFSET) -# define STM32WL5_SPI2S2_TXCRCR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_TXCRCR_OFFSET) +#if STM32_NSPI > 1 +# define STM32_SPI2S2_CR1 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR1_OFFSET) +# define STM32_SPI2S2_CR2 \ + (STM32_SPI2S2_BASE + STM32_SPI_CR2_OFFSET) +# define STM32_SPI2S2_SR \ + (STM32_SPI2S2_BASE + STM32_SPI_SR_OFFSET) +# define STM32_SPI2S2_DR \ + (STM32_SPI2S2_BASE + STM32_SPI_DR_OFFSET) +# define STM32_SPI2S2_CRCPR \ + (STM32_SPI2S2_BASE + STM32_SPI_CRCPR_OFFSET) +# define STM32_SPI2S2_RXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_RXCRCR_OFFSET) +# define STM32_SPI2S2_TXCRCR \ + (STM32_SPI2S2_BASE + STM32_SPI_TXCRCR_OFFSET) # if defined(HAVE_SPI_I2S) -# define STM32WL5_SPI2S2_I2SCFGR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SCFGR_OFFSET) -# define STM32WL5_SPI2S2_I2SPR \ - (STM32WL5_SPI2S2_BASE + STM32WL5_SPI_I2SPR_OFFSET) +# define STM32_SPI2S2_I2SCFGR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SCFGR_OFFSET) +# define STM32_SPI2S2_I2SPR \ + (STM32_SPI2S2_BASE + STM32_SPI_I2SPR_OFFSET) # endif #endif diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h index eaf17d3ad0d..34874962a4b 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_syscfg.h @@ -36,43 +36,43 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ -#define STM32WL5_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ +#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */ +#define STM32_SYSCFG_CFGR1_OFFSET 0x0004 /* SYSCFG configuration register 1 */ -#define STM32WL5_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ +#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */ -#define STM32WL5_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ -#define STM32WL5_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ -#define STM32WL5_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ -#define STM32WL5_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ -#define STM32WL5_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ -#define STM32WL5_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ -#define STM32WL5_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ -#define STM32WL5_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ -#define STM32WL5_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ -#define STM32WL5_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ -#define STM32WL5_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ +#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */ +#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */ +#define STM32_SYSCFG_EXTICR3_OFFSET 0x0010 /* SYSCFG external interrupt configuration register 3 */ +#define STM32_SYSCFG_EXTICR4_OFFSET 0x0014 /* SYSCFG external interrupt configuration register 4 */ +#define STM32_SYSCFG_SCSR_OFFSET 0x0018 /* SYSCFG SRAM2 control and status register */ +#define STM32_SYSCFG_CFGR2_OFFSET 0x001c /* SYSCFG configuration register 2 */ +#define STM32_SYSCFG_SWPR_OFFSET 0x0020 /* SYSCFG SRAM2 write protection register */ +#define STM32_SYSCFG_SKR_OFFSET 0x0024 /* SYSCFG SRAM2 key register */ +#define STM32_SYSCFG_IMR1_OFFSET 0x0100 /* SYSCFG cpu1 interrupt mask register 1 */ +#define STM32_SYSCFG_IMR2_OFFSET 0x0104 /* SYSCFG cpu1 interrupt mask register 2 */ +#define STM32_SYSCFG_C2IMR1_OFFSET 0x0108 /* SYSCFG cpu2 interrupt mask register 1 */ +#define STM32_SYSCFG_C2IMR2_OFFSET 0x010c /* SYSCFG cpu2 interrupt mask register 2 */ +#define STM32_SYSCFG_RFDCR_OFFSET 0x0208 /* SYSCFG radio debug control register */ /* Register Addresses *******************************************************/ -#define STM32WL5_SYSCFG_MEMRMP (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_MEMRMP_OFFSET) -#define STM32WL5_SYSCFG_CFGR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR1_OFFSET) -#define STM32WL5_SYSCFG_EXTICR(p) (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR_OFFSET(p)) -#define STM32WL5_SYSCFG_EXTICR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR1) -#define STM32WL5_SYSCFG_EXTICR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR2) -#define STM32WL5_SYSCFG_EXTICR3 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR3) -#define STM32WL5_SYSCFG_EXTICR4 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_EXTICR4) -#define STM32WL5_SYSCFG_SCSR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SCSR) -#define STM32WL5_SYSCFG_CFGR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_CFGR2) -#define STM32WL5_SYSCFG_SWPR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SWPR) -#define STM32WL5_SYSCFG_SKR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_SKR) -#define STM32WL5_SYSCFG_IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR1) -#define STM32WL5_SYSCFG_IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_IMR2) -#define STM32WL5_SYSCFG_C2IMR1 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR1) -#define STM32WL5_SYSCFG_C2IMR2 (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_C2IMR2) -#define STM32WL5_SYSCFG_RFDCR (STM32WL5_SYSCFG_BASE+STM32WL5_SYSCFG_RFDCR) +#define STM32_SYSCFG_MEMRMP (STM32_SYSCFG_BASE+STM32_SYSCFG_MEMRMP_OFFSET) +#define STM32_SYSCFG_CFGR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET) +#define STM32_SYSCFG_EXTICR(p) (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p)) +#define STM32_SYSCFG_EXTICR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1) +#define STM32_SYSCFG_EXTICR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2) +#define STM32_SYSCFG_EXTICR3 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3) +#define STM32_SYSCFG_EXTICR4 (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4) +#define STM32_SYSCFG_SCSR (STM32_SYSCFG_BASE+STM32_SYSCFG_SCSR) +#define STM32_SYSCFG_CFGR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2) +#define STM32_SYSCFG_SWPR (STM32_SYSCFG_BASE+STM32_SYSCFG_SWPR) +#define STM32_SYSCFG_SKR (STM32_SYSCFG_BASE+STM32_SYSCFG_SKR) +#define STM32_SYSCFG_IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR1) +#define STM32_SYSCFG_IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_IMR2) +#define STM32_SYSCFG_C2IMR1 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR1) +#define STM32_SYSCFG_C2IMR2 (STM32_SYSCFG_BASE+STM32_SYSCFG_C2IMR2) +#define STM32_SYSCFG_RFDCR (STM32_SYSCFG_BASE+STM32_SYSCFG_RFDCR) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h index 1ffe5b78038..f3bc9aa64c1 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_tim.h @@ -31,166 +31,166 @@ /* Basic Timers - TIM6 and TIM7 */ -#define STM32WL5_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ -#define STM32WL5_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ -#define STM32WL5_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_BTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_BTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_BTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_BTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_BTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_BTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode */ +#define STM32_BTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register */ +#define STM32_BTIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_BTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_BTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ /* 32-bit General Timers - TIM2 * TIM2 and 5 are 32-bit. * TIM15, 16 and 17 are 16-bit. */ -#define STM32WL5_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ -#define STM32WL5_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ -#define STM32WL5_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ -#define STM32WL5_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ -#define STM32WL5_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ -#define STM32WL5_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ -#define STM32WL5_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ -#define STM32WL5_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ -#define STM32WL5_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ +#define STM32_GTIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_GTIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit) */ +#define STM32_GTIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit, TIM2-5,15 only) */ +#define STM32_GTIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_GTIM_SR_OFFSET 0x0010 /* Status register (16-bit) */ +#define STM32_GTIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_GTIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (32-bit) */ +#define STM32_GTIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (32-bit, TIM2-5 only) */ +#define STM32_GTIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit) */ +#define STM32_GTIM_CNT_OFFSET 0x0024 /* Counter (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_GTIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit TIM2-5,15 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit TIM2-5 only or 32-bit TIM2/5) */ +#define STM32_GTIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_GTIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_GTIM_OR1_OFFSET 0x0050 /* Option register 1 */ +#define STM32_GTIM_OR2_OFFSET 0x0060 /* Option register 2 */ /* TIM15, 16, and 17 only. */ -#define STM32WL5_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ -#define STM32WL5_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ +#define STM32_GTIM_RCR_OFFSET 0x0030 /* Repetition counter register (TIM16/TIM17) */ +#define STM32_GTIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (TIM16/TIM17) */ /* Advanced Timers - TIM1 */ -#define STM32WL5_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ -#define STM32WL5_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ -#define STM32WL5_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ -#define STM32WL5_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ -#define STM32WL5_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ -#define STM32WL5_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ -#define STM32WL5_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ -#define STM32WL5_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ -#define STM32WL5_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ -#define STM32WL5_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ -#define STM32WL5_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ -#define STM32WL5_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ -#define STM32WL5_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ -#define STM32WL5_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ -#define STM32WL5_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ -#define STM32WL5_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ -#define STM32WL5_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ -#define STM32WL5_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ -#define STM32WL5_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ -#define STM32WL5_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ -#define STM32WL5_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ -#define STM32WL5_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ -#define STM32WL5_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ -#define STM32WL5_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ -#define STM32WL5_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ +#define STM32_ATIM_CR1_OFFSET 0x0000 /* Control register 1 (16-bit) */ +#define STM32_ATIM_CR2_OFFSET 0x0004 /* Control register 2 (16-bit*) */ +#define STM32_ATIM_SMCR_OFFSET 0x0008 /* Slave mode control register (16-bit) */ +#define STM32_ATIM_DIER_OFFSET 0x000c /* DMA/Interrupt enable register (16-bit) */ +#define STM32_ATIM_SR_OFFSET 0x0010 /* Status register (16-bit*) */ +#define STM32_ATIM_EGR_OFFSET 0x0014 /* Event generation register (16-bit) */ +#define STM32_ATIM_CCMR1_OFFSET 0x0018 /* Capture/compare mode register 1 (16-bit*) */ +#define STM32_ATIM_CCMR2_OFFSET 0x001c /* Capture/compare mode register 2 (16-bit*) */ +#define STM32_ATIM_CCER_OFFSET 0x0020 /* Capture/compare enable register (16-bit*) */ +#define STM32_ATIM_CNT_OFFSET 0x0024 /* Counter (16-bit) */ +#define STM32_ATIM_PSC_OFFSET 0x0028 /* Prescaler (16-bit) */ +#define STM32_ATIM_ARR_OFFSET 0x002c /* Auto-reload register (16-bit) */ +#define STM32_ATIM_RCR_OFFSET 0x0030 /* Repetition counter register (16-bit) */ +#define STM32_ATIM_CCR1_OFFSET 0x0034 /* Capture/compare register 1 (16-bit) */ +#define STM32_ATIM_CCR2_OFFSET 0x0038 /* Capture/compare register 2 (16-bit) */ +#define STM32_ATIM_CCR3_OFFSET 0x003c /* Capture/compare register 3 (16-bit) */ +#define STM32_ATIM_CCR4_OFFSET 0x0040 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_BDTR_OFFSET 0x0044 /* Break and dead-time register (16-bit*) */ +#define STM32_ATIM_DCR_OFFSET 0x0048 /* DMA control register (16-bit) */ +#define STM32_ATIM_DMAR_OFFSET 0x004c /* DMA address for burst mode (16-bit) */ +#define STM32_ATIM_OR1_OFFSET 0x0050 /* Timer option register 1 */ +#define STM32_ATIM_CCMR3_OFFSET 0x0054 /* Capture/compare mode register 3 (32-bit) */ +#define STM32_ATIM_CCR5_OFFSET 0x0058 /* Capture/compare register 4 (16-bit) */ +#define STM32_ATIM_CCR6_OFFSET 0x005c /* Capture/compare register 4 (32-bit) */ +#define STM32_ATIM_OR2_OFFSET 0x0050 /* Timer option register 2 */ +#define STM32_ATIM_OR3_OFFSET 0x0050 /* Timer option register 3 */ /* Register Addresses *******************************************************/ /* Advanced Timers - TIM1 and TIM8 */ -#define STM32WL5_TIM1_CR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR1_OFFSET) -#define STM32WL5_TIM1_CR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CR2_OFFSET) -#define STM32WL5_TIM1_SMCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SMCR_OFFSET) -#define STM32WL5_TIM1_DIER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DIER_OFFSET) -#define STM32WL5_TIM1_SR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_SR_OFFSET) -#define STM32WL5_TIM1_EGR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_EGR_OFFSET) -#define STM32WL5_TIM1_CCMR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR1_OFFSET) -#define STM32WL5_TIM1_CCMR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR2_OFFSET) -#define STM32WL5_TIM1_CCER (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCER_OFFSET) -#define STM32WL5_TIM1_CNT (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CNT_OFFSET) -#define STM32WL5_TIM1_PSC (STM32WL5_TIM1_BASE+STM32WL5_ATIM_PSC_OFFSET) -#define STM32WL5_TIM1_ARR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_ARR_OFFSET) -#define STM32WL5_TIM1_RCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_RCR_OFFSET) -#define STM32WL5_TIM1_CCR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR1_OFFSET) -#define STM32WL5_TIM1_CCR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR2_OFFSET) -#define STM32WL5_TIM1_CCR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR3_OFFSET) -#define STM32WL5_TIM1_CCR4 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR4_OFFSET) -#define STM32WL5_TIM1_BDTR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_BDTR_OFFSET) -#define STM32WL5_TIM1_DCR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DCR_OFFSET) -#define STM32WL5_TIM1_DMAR (STM32WL5_TIM1_BASE+STM32WL5_ATIM_DMAR_OFFSET) -#define STM32WL5_TIM1_OR1 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR1_OFFSET) -#define STM32WL5_TIM1_CCMR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCMR3_OFFSET) -#define STM32WL5_TIM1_CCR5 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR5_OFFSET) -#define STM32WL5_TIM1_CCR6 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_CCR6_OFFSET) -#define STM32WL5_TIM1_OR2 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR2_OFFSET) -#define STM32WL5_TIM1_OR3 (STM32WL5_TIM1_BASE+STM32WL5_ATIM_OR3_OFFSET) +#define STM32_TIM1_CR1 (STM32_TIM1_BASE+STM32_ATIM_CR1_OFFSET) +#define STM32_TIM1_CR2 (STM32_TIM1_BASE+STM32_ATIM_CR2_OFFSET) +#define STM32_TIM1_SMCR (STM32_TIM1_BASE+STM32_ATIM_SMCR_OFFSET) +#define STM32_TIM1_DIER (STM32_TIM1_BASE+STM32_ATIM_DIER_OFFSET) +#define STM32_TIM1_SR (STM32_TIM1_BASE+STM32_ATIM_SR_OFFSET) +#define STM32_TIM1_EGR (STM32_TIM1_BASE+STM32_ATIM_EGR_OFFSET) +#define STM32_TIM1_CCMR1 (STM32_TIM1_BASE+STM32_ATIM_CCMR1_OFFSET) +#define STM32_TIM1_CCMR2 (STM32_TIM1_BASE+STM32_ATIM_CCMR2_OFFSET) +#define STM32_TIM1_CCER (STM32_TIM1_BASE+STM32_ATIM_CCER_OFFSET) +#define STM32_TIM1_CNT (STM32_TIM1_BASE+STM32_ATIM_CNT_OFFSET) +#define STM32_TIM1_PSC (STM32_TIM1_BASE+STM32_ATIM_PSC_OFFSET) +#define STM32_TIM1_ARR (STM32_TIM1_BASE+STM32_ATIM_ARR_OFFSET) +#define STM32_TIM1_RCR (STM32_TIM1_BASE+STM32_ATIM_RCR_OFFSET) +#define STM32_TIM1_CCR1 (STM32_TIM1_BASE+STM32_ATIM_CCR1_OFFSET) +#define STM32_TIM1_CCR2 (STM32_TIM1_BASE+STM32_ATIM_CCR2_OFFSET) +#define STM32_TIM1_CCR3 (STM32_TIM1_BASE+STM32_ATIM_CCR3_OFFSET) +#define STM32_TIM1_CCR4 (STM32_TIM1_BASE+STM32_ATIM_CCR4_OFFSET) +#define STM32_TIM1_BDTR (STM32_TIM1_BASE+STM32_ATIM_BDTR_OFFSET) +#define STM32_TIM1_DCR (STM32_TIM1_BASE+STM32_ATIM_DCR_OFFSET) +#define STM32_TIM1_DMAR (STM32_TIM1_BASE+STM32_ATIM_DMAR_OFFSET) +#define STM32_TIM1_OR1 (STM32_TIM1_BASE+STM32_ATIM_OR1_OFFSET) +#define STM32_TIM1_CCMR3 (STM32_TIM1_BASE+STM32_ATIM_CCMR3_OFFSET) +#define STM32_TIM1_CCR5 (STM32_TIM1_BASE+STM32_ATIM_CCR5_OFFSET) +#define STM32_TIM1_CCR6 (STM32_TIM1_BASE+STM32_ATIM_CCR6_OFFSET) +#define STM32_TIM1_OR2 (STM32_TIM1_BASE+STM32_ATIM_OR2_OFFSET) +#define STM32_TIM1_OR3 (STM32_TIM1_BASE+STM32_ATIM_OR3_OFFSET) /* 16-/32-bit General Timers - TIM2, TIM16-17. * TIM2 is 32-bit. * TIM16 and 17 are 16-bit. */ -#define STM32WL5_TIM2_CR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM2_CR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM2_SMCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SMCR_OFFSET) -#define STM32WL5_TIM2_DIER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM2_SR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM2_EGR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM2_CCMR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM2_CCMR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCMR2_OFFSET) -#define STM32WL5_TIM2_CCER (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM2_CNT (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM2_PSC (STM32WL5_TIM2_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM2_ARR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM2_CCR1 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM2_CCR2 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR2_OFFSET) -#define STM32WL5_TIM2_CCR3 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR3_OFFSET) -#define STM32WL5_TIM2_CCR4 (STM32WL5_TIM2_BASE+STM32WL5_GTIM_CCR4_OFFSET) -#define STM32WL5_TIM2_DCR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM2_DMAR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM2_OR (STM32WL5_TIM2_BASE+STM32WL5_GTIM_OR_OFFSET) +#define STM32_TIM2_CR1 (STM32_TIM2_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM2_CR2 (STM32_TIM2_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM2_SMCR (STM32_TIM2_BASE+STM32_GTIM_SMCR_OFFSET) +#define STM32_TIM2_DIER (STM32_TIM2_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM2_SR (STM32_TIM2_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM2_EGR (STM32_TIM2_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM2_CCMR1 (STM32_TIM2_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM2_CCMR2 (STM32_TIM2_BASE+STM32_GTIM_CCMR2_OFFSET) +#define STM32_TIM2_CCER (STM32_TIM2_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM2_CNT (STM32_TIM2_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM2_PSC (STM32_TIM2_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM2_ARR (STM32_TIM2_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM2_CCR1 (STM32_TIM2_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM2_CCR2 (STM32_TIM2_BASE+STM32_GTIM_CCR2_OFFSET) +#define STM32_TIM2_CCR3 (STM32_TIM2_BASE+STM32_GTIM_CCR3_OFFSET) +#define STM32_TIM2_CCR4 (STM32_TIM2_BASE+STM32_GTIM_CCR4_OFFSET) +#define STM32_TIM2_DCR (STM32_TIM2_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM2_DMAR (STM32_TIM2_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM2_OR (STM32_TIM2_BASE+STM32_GTIM_OR_OFFSET) -#define STM32WL5_TIM16_CR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM16_CR2 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM16_DIER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM16_SR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM16_EGR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM16_CCMR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM16_CCER (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM16_CNT (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM16_PSC (STM32WL5_TIM16_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM16_ARR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM16_RCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM16_CCR1 (STM32WL5_TIM16_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM16_BDTR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM16_DCR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM16_DMAR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_DMAR_OFFSET) -#define STM32WL5_TIM16_OR (STM32WL5_TIM16_BASE+STM32WL5_GTIM_OR_OFFSET) +#define STM32_TIM16_CR1 (STM32_TIM16_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM16_CR2 (STM32_TIM16_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM16_DIER (STM32_TIM16_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM16_SR (STM32_TIM16_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM16_EGR (STM32_TIM16_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM16_CCMR1 (STM32_TIM16_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM16_CCER (STM32_TIM16_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM16_CNT (STM32_TIM16_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM16_PSC (STM32_TIM16_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM16_ARR (STM32_TIM16_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM16_RCR (STM32_TIM16_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM16_CCR1 (STM32_TIM16_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM16_BDTR (STM32_TIM16_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM16_DCR (STM32_TIM16_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM16_DMAR (STM32_TIM16_BASE+STM32_GTIM_DMAR_OFFSET) +#define STM32_TIM16_OR (STM32_TIM16_BASE+STM32_GTIM_OR_OFFSET) -#define STM32WL5_TIM17_CR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR1_OFFSET) -#define STM32WL5_TIM17_CR2 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CR2_OFFSET) -#define STM32WL5_TIM17_DIER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DIER_OFFSET) -#define STM32WL5_TIM17_SR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_SR_OFFSET) -#define STM32WL5_TIM17_EGR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_EGR_OFFSET) -#define STM32WL5_TIM17_CCMR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCMR1_OFFSET) -#define STM32WL5_TIM17_CCER (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCER_OFFSET) -#define STM32WL5_TIM17_CNT (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CNT_OFFSET) -#define STM32WL5_TIM17_PSC (STM32WL5_TIM17_BASE+STM32WL5_GTIM_PSC_OFFSET) -#define STM32WL5_TIM17_ARR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_ARR_OFFSET) -#define STM32WL5_TIM17_RCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_RCR_OFFSET) -#define STM32WL5_TIM17_CCR1 (STM32WL5_TIM17_BASE+STM32WL5_GTIM_CCR1_OFFSET) -#define STM32WL5_TIM17_BDTR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_BDTR_OFFSET) -#define STM32WL5_TIM17_DCR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DCR_OFFSET) -#define STM32WL5_TIM17_DMAR (STM32WL5_TIM17_BASE+STM32WL5_GTIM_DMAR_OFFSET) +#define STM32_TIM17_CR1 (STM32_TIM17_BASE+STM32_GTIM_CR1_OFFSET) +#define STM32_TIM17_CR2 (STM32_TIM17_BASE+STM32_GTIM_CR2_OFFSET) +#define STM32_TIM17_DIER (STM32_TIM17_BASE+STM32_GTIM_DIER_OFFSET) +#define STM32_TIM17_SR (STM32_TIM17_BASE+STM32_GTIM_SR_OFFSET) +#define STM32_TIM17_EGR (STM32_TIM17_BASE+STM32_GTIM_EGR_OFFSET) +#define STM32_TIM17_CCMR1 (STM32_TIM17_BASE+STM32_GTIM_CCMR1_OFFSET) +#define STM32_TIM17_CCER (STM32_TIM17_BASE+STM32_GTIM_CCER_OFFSET) +#define STM32_TIM17_CNT (STM32_TIM17_BASE+STM32_GTIM_CNT_OFFSET) +#define STM32_TIM17_PSC (STM32_TIM17_BASE+STM32_GTIM_PSC_OFFSET) +#define STM32_TIM17_ARR (STM32_TIM17_BASE+STM32_GTIM_ARR_OFFSET) +#define STM32_TIM17_RCR (STM32_TIM17_BASE+STM32_GTIM_RCR_OFFSET) +#define STM32_TIM17_CCR1 (STM32_TIM17_BASE+STM32_GTIM_CCR1_OFFSET) +#define STM32_TIM17_BDTR (STM32_TIM17_BASE+STM32_GTIM_BDTR_OFFSET) +#define STM32_TIM17_DCR (STM32_TIM17_BASE+STM32_GTIM_DCR_OFFSET) +#define STM32_TIM17_DMAR (STM32_TIM17_BASE+STM32_GTIM_DMAR_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h index 5eb2450e7a3..921ee283b4d 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_uart.h @@ -37,57 +37,57 @@ /* Register Offsets *********************************************************/ -#define STM32WL5_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32WL5_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32WL5_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32WL5_USART_BRR_OFFSET 0x000c /* Baud Rate register */ -#define STM32WL5_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32WL5_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32WL5_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32WL5_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ -#define STM32WL5_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32WL5_USART_RDR_OFFSET 0x0024 /* Receive Data register */ -#define STM32WL5_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ -#define STM32WL5_USART_PRESC_OFFSET 0x002c /* Prescaler */ +#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ +#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ +#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ +#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate register */ +#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ +#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ +#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ +#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and status register */ +#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ +#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data register */ +#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data register */ +#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler */ /* Register Addresses *******************************************************/ -#define STM32WL5_USART1_CR1 (STM32WL5_USART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART1_CR2 (STM32WL5_USART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART1_CR3 (STM32WL5_USART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART1_BRR (STM32WL5_USART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART1_GTPR (STM32WL5_USART1_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART1_RTOR (STM32WL5_USART1_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART1_RQR (STM32WL5_USART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART1_ISR (STM32WL5_USART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART1_ICR (STM32WL5_USART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART1_RDR (STM32WL5_USART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART1_TDR (STM32WL5_USART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART1_PRESC (STM32WL5_USART1_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART1_PRESC (STM32_USART1_BASE+STM32_USART_PRESC_OFFSET) -#define STM32WL5_USART2_CR1 (STM32WL5_USART2_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_USART2_CR2 (STM32WL5_USART2_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_USART2_CR3 (STM32WL5_USART2_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_USART2_BRR (STM32WL5_USART2_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_USART2_GTPR (STM32WL5_USART2_BASE+STM32WL5_USART_GTPR_OFFSET) -#define STM32WL5_USART2_RTOR (STM32WL5_USART2_BASE+STM32WL5_USART_RTOR_OFFSET) -#define STM32WL5_USART2_RQR (STM32WL5_USART2_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_USART2_ISR (STM32WL5_USART2_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_USART2_ICR (STM32WL5_USART2_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_USART2_RDR (STM32WL5_USART2_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_USART2_TDR (STM32WL5_USART2_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_USART2_PRESC (STM32WL5_USART2_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +#define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +#define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +#define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +#define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) +#define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) +#define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) +#define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) +#define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) +#define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) +#define STM32_USART2_PRESC (STM32_USART2_BASE+STM32_USART_PRESC_OFFSET) -#define STM32WL5_LPUART1_CR1 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR1_OFFSET) -#define STM32WL5_LPUART1_CR2 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR2_OFFSET) -#define STM32WL5_LPUART1_CR3 (STM32WL5_LPUART1_BASE+STM32WL5_USART_CR3_OFFSET) -#define STM32WL5_LPUART1_BRR (STM32WL5_LPUART1_BASE+STM32WL5_USART_BRR_OFFSET) -#define STM32WL5_LPUART1_RQR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RQR_OFFSET) -#define STM32WL5_LPUART1_ISR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ISR_OFFSET) -#define STM32WL5_LPUART1_ICR (STM32WL5_LPUART1_BASE+STM32WL5_USART_ICR_OFFSET) -#define STM32WL5_LPUART1_RDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_RDR_OFFSET) -#define STM32WL5_LPUART1_TDR (STM32WL5_LPUART1_BASE+STM32WL5_USART_TDR_OFFSET) -#define STM32WL5_LPUART1_PRESC (STM32WL5_LPUART1_BASE+STM32WL5_USART_PRESC_OFFSET) +#define STM32_LPUART1_CR1 (STM32_LPUART1_BASE+STM32_USART_CR1_OFFSET) +#define STM32_LPUART1_CR2 (STM32_LPUART1_BASE+STM32_USART_CR2_OFFSET) +#define STM32_LPUART1_CR3 (STM32_LPUART1_BASE+STM32_USART_CR3_OFFSET) +#define STM32_LPUART1_BRR (STM32_LPUART1_BASE+STM32_USART_BRR_OFFSET) +#define STM32_LPUART1_RQR (STM32_LPUART1_BASE+STM32_USART_RQR_OFFSET) +#define STM32_LPUART1_ISR (STM32_LPUART1_BASE+STM32_USART_ISR_OFFSET) +#define STM32_LPUART1_ICR (STM32_LPUART1_BASE+STM32_USART_ICR_OFFSET) +#define STM32_LPUART1_RDR (STM32_LPUART1_BASE+STM32_USART_RDR_OFFSET) +#define STM32_LPUART1_TDR (STM32_LPUART1_BASE+STM32_USART_TDR_OFFSET) +#define STM32_LPUART1_PRESC (STM32_LPUART1_BASE+STM32_USART_PRESC_OFFSET) /* Register Bitfield Definitions ********************************************/ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 61e9a51df81..7b8dc6081ba 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -66,17 +66,17 @@ /* Set the range of system SRAM */ -#define SRAM1_START STM32WL5_SRAM_BASE -#define SRAM1_END (SRAM1_START + STM32WL5_SRAM1_SIZE) +#define SRAM1_START STM32_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ #ifdef CONFIG_IPCC # define SRAM2_START IPCC_END #else -# define SRAM2_START STM32WL5_SRAM2_BASE +# define SRAM2_START STM32_SRAM2_BASE #endif -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) /* Some sanity checking. If multiple memory regions are defined, verify * that CONFIG_MM_REGIONS is set to match the number of memory regions diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index 6d6318f0238..f94f6f9bbda 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -72,7 +72,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0001, STM32WL5_EXTI_PR1); + putreg32(0x0001, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -93,7 +93,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0002, STM32WL5_EXTI_PR1); + putreg32(0x0002, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -114,7 +114,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0004, STM32WL5_EXTI_PR1); + putreg32(0x0004, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -135,7 +135,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0008, STM32WL5_EXTI_PR1); + putreg32(0x0008, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -156,7 +156,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) /* Clear the pending interrupt */ - putreg32(0x0010, STM32WL5_EXTI_PR1); + putreg32(0x0010, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -180,7 +180,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, /* Examine the state of each pin in the group */ - pr = getreg32(STM32WL5_EXTI_PR1); + pr = getreg32(STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -193,7 +193,7 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, { /* Clear the pending interrupt */ - putreg32(mask, STM32WL5_EXTI_PR1); + putreg32(mask, STM32_EXTI_PR1); /* And dispatch the interrupt to the handler */ @@ -267,7 +267,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (pin < 5) { - irq = pin + STM32WL5_IRQ_EXTI0; + irq = pin + STM32_IRQ_EXTI0; nshared = 1; shared_cbs = &g_gpio_handlers[pin]; switch (pin) @@ -295,14 +295,14 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, } else if (pin < 10) { - irq = STM32WL5_IRQ_EXTI95; + irq = STM32_IRQ_EXTI95; handler = stm32wl5_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { - irq = STM32WL5_IRQ_EXTI1510; + irq = STM32_IRQ_EXTI1510; handler = stm32wl5_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; @@ -353,19 +353,19 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, /* Configure rising/falling edges */ - modifyreg32(STM32WL5_EXTI_RTSR1, + modifyreg32(STM32_EXTI_RTSR1, risingedge ? 0 : exti, risingedge ? exti : 0); - modifyreg32(STM32WL5_EXTI_FTSR1, + modifyreg32(STM32_EXTI_FTSR1, fallingedge ? 0 : exti, fallingedge ? exti : 0); /* Enable Events and Interrupts */ - modifyreg32(STM32WL5_EXTI_C1EMR1, + modifyreg32(STM32_EXTI_C1EMR1, event ? 0 : exti, event ? exti : 0); - modifyreg32(STM32WL5_EXTI_C1IMR1, + modifyreg32(STM32_EXTI_C1IMR1, func ? 0 : exti, func ? exti : 0); diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index 054ca10b3ae..bb83f736a46 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -65,7 +65,7 @@ #define OPTBYTES_KEY1 0x08192A3B #define OPTBYTES_KEY2 0x4C5D6E7F -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE #define FLASH_PAGE_WORDS (FLASH_PAGE_SIZE / 4) #define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1) #define FLASH_PAGE_SHIFT (11) /* 2**11 = 2048B */ @@ -93,35 +93,35 @@ static uint32_t g_page_buffer[FLASH_PAGE_WORDS]; static void flash_unlock(void) { - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_LOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) { /* Unlock sequence */ - putreg32(FLASH_KEY1, STM32WL5_FLASH_KEYR); - putreg32(FLASH_KEY2, STM32WL5_FLASH_KEYR); + putreg32(FLASH_KEY1, STM32_FLASH_KEYR); + putreg32(FLASH_KEY2, STM32_FLASH_KEYR); } } static void flash_lock(void) { - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_LOCK); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK); } static void flash_optbytes_unlock(void) { flash_unlock(); - if (getreg32(STM32WL5_FLASH_CR) & FLASH_CR_OPTLOCK) + if (getreg32(STM32_FLASH_CR) & FLASH_CR_OPTLOCK) { /* Unlock Option Bytes sequence */ - putreg32(OPTBYTES_KEY1, STM32WL5_FLASH_OPTKEYR); - putreg32(OPTBYTES_KEY2, STM32WL5_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY1, STM32_FLASH_OPTKEYR); + putreg32(OPTBYTES_KEY2, STM32_FLASH_OPTKEYR); } } @@ -138,17 +138,17 @@ static inline void flash_erase(size_t page) { finfo("erase page %u\n", (unsigned int)page); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PNB_MASK, + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_START); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_START); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } /**************************************************************************** @@ -227,20 +227,20 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) /* Modify Option Bytes in register. */ - regval = getreg32(STM32WL5_FLASH_OPTR); + regval = getreg32(STM32_FLASH_OPTR); finfo("Flash option bytes before: 0x%" PRIx32 "\n", regval); regval = (regval & ~clrbits) | setbits; - putreg32(regval, STM32WL5_FLASH_OPTR); + putreg32(regval, STM32_FLASH_OPTR); finfo("Flash option bytes after: 0x%" PRIx32 "\n", regval); /* Start Option Bytes programming and wait for completion. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_OPTSTRT); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_OPTSTRT); - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } @@ -253,42 +253,42 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) size_t up_progmem_pagesize(size_t page) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } size_t up_progmem_erasesize(size_t block) { - return STM32WL5_FLASH_PAGESIZE; + return STM32_FLASH_PAGESIZE; } ssize_t up_progmem_getpage(size_t addr) { - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - addr -= STM32WL5_FLASH_BASE; + addr -= STM32_FLASH_BASE; } - if (addr >= STM32WL5_FLASH_SIZE) + if (addr >= STM32_FLASH_SIZE) { return -EFAULT; } - return addr / STM32WL5_FLASH_PAGESIZE; + return addr / STM32_FLASH_PAGESIZE; } size_t up_progmem_getaddress(size_t page) { - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return SIZE_MAX; } - return page * STM32WL5_FLASH_PAGESIZE + STM32WL5_FLASH_BASE; + return page * STM32_FLASH_PAGESIZE + STM32_FLASH_BASE; } size_t up_progmem_neraseblocks(void) { - return STM32WL5_FLASH_NPAGES; + return STM32_FLASH_NPAGES; } bool up_progmem_isuniform(void) @@ -300,7 +300,7 @@ ssize_t up_progmem_eraseblock(size_t block) { int ret; - if (block >= STM32WL5_FLASH_NPAGES) + if (block >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -338,7 +338,7 @@ ssize_t up_progmem_ispageerased(size_t page) size_t count; size_t bwritten = 0; - if (page >= STM32WL5_FLASH_NPAGES) + if (page >= STM32_FLASH_NPAGES) { return -EFAULT; } @@ -372,12 +372,12 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Check for valid address range. */ offset = addr; - if (addr >= STM32WL5_FLASH_BASE) + if (addr >= STM32_FLASH_BASE) { - offset -= STM32WL5_FLASH_BASE; + offset -= STM32_FLASH_BASE; } - if (offset + buflen > STM32WL5_FLASH_SIZE) + if (offset + buflen > STM32_FLASH_SIZE) { return -EFAULT; } @@ -447,7 +447,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ - modifyreg32(STM32WL5_FLASH_CR, 0, FLASH_CR_PG); + modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG); set_pg_bit = true; for (i = 0; i < FLASH_PAGE_WORDS; i += 2) @@ -455,14 +455,14 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) *dest++ = *src++; *dest++ = *src++; - while (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_BSY) + while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { stm32wl5_waste(); } /* Verify */ - if (getreg32(STM32WL5_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) + if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR) { ret = -EROFS; goto out; @@ -476,7 +476,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) } } - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; /* Adjust pointers and counts for the next time through the loop */ @@ -492,7 +492,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) out: if (set_pg_bit) { - modifyreg32(STM32WL5_FLASH_CR, FLASH_CR_PG, 0); + modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); } /* If there was an error, clear all error flags in status register (rc_w1 @@ -502,9 +502,9 @@ out: if (ret != OK) { ferr("flash write error: %d, status: 0x%" PRIx32 "\n", - ret, getreg32(STM32WL5_FLASH_SR)); + ret, getreg32(STM32_FLASH_SR)); - modifyreg32(STM32WL5_FLASH_SR, 0, FLASH_SR_ALLERRS); + modifyreg32(STM32_FLASH_SR, 0, FLASH_SR_ALLERRS); } flash_lock(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index 3b22db6f904..b3ec90cac4c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -55,19 +55,19 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; /* Base addresses for each GPIO block */ -const uint32_t g_gpiobase[STM32WL5_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { -#if STM32WL5_NPORTS > 0 - STM32WL5_GPIOA_BASE, +#if STM32_NPORTS > 0 + STM32_GPIOA_BASE, #endif -#if STM32WL5_NPORTS > 1 - STM32WL5_GPIOB_BASE, +#if STM32_NPORTS > 1 + STM32_GPIOB_BASE, #endif -#if STM32WL5_NPORTS > 2 - STM32WL5_GPIOC_BASE, +#if STM32_NPORTS > 2 + STM32_GPIOC_BASE, #endif -#if STM32WL5_NPORTS > 3 - STM32WL5_GPIOH_BASE, +#if STM32_NPORTS > 3 + STM32_GPIOH_BASE, #endif }; @@ -130,7 +130,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32WL5_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -179,10 +179,10 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Now apply the configuration to the mode register */ - regval = getreg32(base + STM32WL5_GPIO_MODER_OFFSET); + regval = getreg32(base + STM32_GPIO_MODER_OFFSET); regval &= ~GPIO_MODER_MASK(pin); regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_MODER_OFFSET); + putreg32(regval, base + STM32_GPIO_MODER_OFFSET); /* Set up the pull-up/pull-down configuration (all but analog pins) */ @@ -205,10 +205,10 @@ int stm32wl5_configgpio(uint32_t cfgset) } } - regval = getreg32(base + STM32WL5_GPIO_PUPDR_OFFSET); + regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET); regval &= ~GPIO_PUPDR_MASK(pin); regval |= (setting << GPIO_PUPDR_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_PUPDR_OFFSET); + putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET); /* Set the alternate function (Only alternate function pins) */ @@ -223,12 +223,12 @@ int stm32wl5_configgpio(uint32_t cfgset) if (pin < 8) { - regoffset = STM32WL5_GPIO_AFRL_OFFSET; + regoffset = STM32_GPIO_AFRL_OFFSET; pos = pin; } else { - regoffset = STM32WL5_GPIO_AFRH_OFFSET; + regoffset = STM32_GPIO_AFRH_OFFSET; pos = pin - 8; } @@ -266,14 +266,14 @@ int stm32wl5_configgpio(uint32_t cfgset) setting = 0; } - regval = getreg32(base + STM32WL5_GPIO_OSPEED_OFFSET); + regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET); regval &= ~GPIO_OSPEED_MASK(pin); regval |= (setting << GPIO_OSPEED_SHIFT(pin)); - putreg32(regval, base + STM32WL5_GPIO_OSPEED_OFFSET); + putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET); /* Set push-pull/open-drain (Only outputs and alternate function pins) */ - regval = getreg32(base + STM32WL5_GPIO_OTYPER_OFFSET); + regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET); setting = GPIO_OTYPER_OD(pin); if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) && @@ -286,7 +286,7 @@ int stm32wl5_configgpio(uint32_t cfgset) regval &= ~setting; } - putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET); + putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET); /* Otherwise, it is an input pin. Should it configured as an * EXTI interrupt? @@ -303,7 +303,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the bits in the SYSCFG EXTICR register */ - regaddr = STM32WL5_SYSCFG_EXTICR(pin); + regaddr = STM32_SYSCFG_EXTICR(pin); regval = getreg32(regaddr); shift = SYSCFG_EXTICR_EXTI_SHIFT(pin); regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift); @@ -365,7 +365,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -386,7 +386,7 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) bit = GPIO_BSRR_RESET(pin); } - putreg32(bit, base + STM32WL5_GPIO_BSRR_OFFSET); + putreg32(bit, base + STM32_GPIO_BSRR_OFFSET); } } @@ -405,7 +405,7 @@ bool stm32wl5_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32WL5_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -414,7 +414,7 @@ bool stm32wl5_gpioread(uint32_t pinset) /* Get the pin number and return the input state of that pin */ pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; - return ((getreg32(base + STM32WL5_GPIO_IDR_OFFSET) & (1 << pin)) != 0); + return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0); } return 0; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 86480eb193a..9e583c880e8 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -237,7 +237,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32WL5_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index 38a41c71803..d625e58f1e6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -225,8 +225,8 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR) >> STM32WL5_IPCC_TX_SHIFT; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + mr = getreg32(STM32_IPCC_C1MR) >> STM32_IPCC_TX_SHIFT; + sr = getreg32(STM32_IPCC_C1TOC2SR); /* Consider only channels that have tx memory free and are unmasked */ @@ -266,7 +266,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) /* Yes, tell another CPU that data is available to read */ txmem->len = nwritten; - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(chan)); } if (circbuf_used(&priv->ipcc->txbuf) == 0) @@ -276,7 +276,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * will be constantly interrupted by tx free irq. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); } #else /* CONFIG_IPCC_BUFFERED */ /* In unbuffered operations we never write anything to IPCC @@ -284,7 +284,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * or else we will constantly get TX interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNFM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNFM(chan)); #endif /* CONFIG_IPCC_BUFFERED */ /* Wake up all blocked writers that there is free space available * in IPCC memory (or txbuffer) to write. @@ -324,7 +324,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_chan_mem_s *txmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C1TOC2SR); + sr = getreg32(STM32_IPCC_C1TOC2SR); if ((sr & (1 << ipcc->chan))) { @@ -334,7 +334,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * so we are notified when we can write to memory. */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } @@ -343,7 +343,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Disable TX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Copy as much as we can into IPCC memory */ @@ -353,12 +353,12 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, /* Tell another CPU that data is available to read */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNS(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNS(ipcc->chan)); /* Re-enable interrupts */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); /* Return number of successfully copied bytes to IPCC memory */ @@ -404,8 +404,8 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) UNUSED(arg); UNUSED(irq); - mr = getreg32(STM32WL5_IPCC_C1MR); - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + mr = getreg32(STM32_IPCC_C1MR); + sr = getreg32(STM32_IPCC_C2TOC1SR); /* Consider only channels that have data in rx memory and are unmasked */ @@ -446,7 +446,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * we have to mask rxirq so we don't get that irq again. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); #endif } @@ -485,7 +485,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, struct stm32wl5_ipcc_s *priv; struct stm32wl5_ipcc_chan_mem_s *rxmem; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << ipcc->chan))) { @@ -502,7 +502,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* This function may be called multiple times to get only part * of data from IPCC memory, ie. There are 8 bytes of data in @@ -525,17 +525,17 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, - STM32WL5_IPCC_SCR_CHNC(ipcc->chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, + STM32_IPCC_SCR_CHNC(ipcc->chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(ipcc->chan), 0); } /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); return to_copy; } @@ -569,7 +569,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, struct stm32wl5_ipcc_chan_mem_s *rxmem; uint32_t sr; - sr = getreg32(STM32WL5_IPCC_C2TOC1SR); + sr = getreg32(STM32_IPCC_C2TOC1SR); if (!(sr & (1 << chan))) { @@ -609,7 +609,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, * this one. */ - modifyreg32(STM32WL5_IPCC_C1MR, 0, STM32WL5_IPCC_MR_CHNOM(chan)); + modifyreg32(STM32_IPCC_C1MR, 0, STM32_IPCC_MR_CHNOM(chan)); } /* Buffer data. This function cannot really fail us if we @@ -629,11 +629,11 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, /* Tell another CPU that IPCC rx buffer is free to be populated */ - modifyreg32(STM32WL5_IPCC_C1SCR, 0, STM32WL5_IPCC_SCR_CHNC(chan)); + modifyreg32(STM32_IPCC_C1SCR, 0, STM32_IPCC_SCR_CHNC(chan)); /* Unmask RX interrupt to know when second CPU sends us a message */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); } return to_copy; @@ -665,7 +665,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Disable RX interrupt since we will modify shared data */ - up_disable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_disable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Copy data to buffer */ @@ -673,7 +673,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Re-enable interrupt */ - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); /* Return number of bytes that were successfully buffered */ @@ -701,7 +701,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #ifdef CONFIG_IPCC_BUFFERED static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) { - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(ipcc->chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; } #endif @@ -728,8 +728,8 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) /* Mask interrupts for given channel */ - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNFM(ipcc->chan)); - modifyreg32(STM32WL5_IPCC_C1MR, 1, STM32WL5_IPCC_MR_CHNOM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNFM(ipcc->chan)); + modifyreg32(STM32_IPCC_C1MR, 1, STM32_IPCC_MR_CHNOM(ipcc->chan)); /* Free allocated ipcc memory */ @@ -798,8 +798,8 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) /* Unmask channel interrupt */ - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNFM(chan), 0); - modifyreg32(STM32WL5_IPCC_C1MR, STM32WL5_IPCC_MR_CHNOM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(chan), 0); + modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNOM(chan), 0); if (ipcc_fti) { @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32WL5_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); @@ -829,11 +829,11 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * - CPU2 has read message from us and TX memory is free to be used again */ - putreg32(STM32WL5_IPCC_CR_RXOIE | STM32WL5_IPCC_CR_TXFIE, - STM32WL5_IPCC_C1CR); + putreg32(STM32_IPCC_CR_RXOIE | STM32_IPCC_CR_TXFIE, + STM32_IPCC_C1CR); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_RX_IT); - up_enable_irq(STM32WL5_IRQ_IPCC_C1_TX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_RX_IT); + up_enable_irq(STM32_IRQ_IPCC_C1_TX_IT); ipcc_fti = 1; diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 14b68fdb151..1e632661c05 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -135,7 +135,7 @@ * of SRAM2. SRAM2 region will be right after IPCC reserved memory */ -#define IPCC_START STM32WL5_SRAM2_BASE +#define IPCC_START STM32_SRAM2_BASE #define IPCC_NCHAN (IPCC_CHAN1 + IPCC_CHAN2 + IPCC_CHAN3 + \ IPCC_CHAN4 + IPCC_CHAN5 + IPCC_CHAN6) #define IPCC_END (IPCC_START + IPCC_CHAN1_SIZE + IPCC_CHAN2_SIZE + \ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index 8e953adb250..b0b25e844bc 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -202,13 +202,13 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, { int n; - DEBUGASSERT(irq >= STM32WL5_IRQ_NMI && irq < NR_IRQS); + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { - n = irq - STM32WL5_IRQ_FIRST; + n = irq - STM32_IRQ_FIRST; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -218,19 +218,19 @@ static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, else { *regaddr = NVIC_SYSHCON; - if (irq == STM32WL5_IRQ_MEMFAULT) + if (irq == STM32_IRQ_MEMFAULT) { *bit = NVIC_SYSHCON_MEMFAULTENA; } - else if (irq == STM32WL5_IRQ_BUSFAULT) + else if (irq == STM32_IRQ_BUSFAULT) { *bit = NVIC_SYSHCON_BUSFAULTENA; } - else if (irq == STM32WL5_IRQ_USAGEFAULT) + else if (irq == STM32_IRQ_USAGEFAULT) { *bit = NVIC_SYSHCON_USGFAULTENA; } - else if (irq == STM32WL5_IRQ_SYSTICK) + else if (irq == STM32_IRQ_SYSTICK) { *regaddr = NVIC_SYSTICK_CTRL; *bit = NVIC_SYSTICK_CTRL_ENABLE; @@ -260,7 +260,7 @@ void up_irqinitialize(void) /* Disable all interrupts */ - for (i = 0; i < NR_IRQS - STM32WL5_IRQ_FIRST; i += 32) + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) { putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); } @@ -314,13 +314,13 @@ void up_irqinitialize(void) * under certain conditions. */ - irq_attach(STM32WL5_IRQ_SVCALL, arm_svcall, NULL); - irq_attach(STM32WL5_IRQ_HARDFAULT, arm_hardfault, NULL); + irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL); /* Set the priority of the SVCall interrupt */ #ifdef CONFIG_ARCH_IRQPRIO - /* up_prioritize_irq(STM32WL5_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); @@ -330,23 +330,23 @@ void up_irqinitialize(void) */ #ifdef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); - up_enable_irq(STM32WL5_IRQ_MEMFAULT); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(STM32_IRQ_MEMFAULT); #endif /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32WL5_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL); #ifndef CONFIG_ARM_MPU - irq_attach(STM32WL5_IRQ_MEMFAULT, arm_memfault, NULL); + irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif - irq_attach(STM32WL5_IRQ_BUSFAULT, arm_busfault, NULL); - irq_attach(STM32WL5_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32WL5_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL); arm_enable_dbgmonitor(); - irq_attach(STM32WL5_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32WL5_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL); #endif stm32wl5_dumpnvic("initial", NR_IRQS); @@ -382,7 +382,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -417,7 +417,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= STM32WL5_IRQ_FIRST) + if (irq >= STM32_IRQ_FIRST) { putreg32(bit, regaddr); } @@ -460,10 +460,10 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32WL5_IRQ_MEMFAULT && irq < NR_IRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < STM32WL5_IRQ_FIRST) + if (irq < STM32_IRQ_FIRST) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -476,7 +476,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= STM32WL5_IRQ_FIRST; + irq -= STM32_IRQ_FIRST; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 06a47209fc6..47431555928 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -47,70 +47,70 @@ #ifdef HAVE_CONSOLE # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_LPUART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR2 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_LPUART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_LPUART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_LPUART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_LPUART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_LPUART1_TX -# define STM32WL5_CONSOLE_RX GPIO_LPUART1_RX +# define STM32_CONSOLE_BASE STM32_LPUART1_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR2 +# define STM32_CONSOLE_APBEN RCC_APB1ENR2_LPUART1EN +# define STM32_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_LPUART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_LPUART1_2STOP +# define STM32_CONSOLE_TX GPIO_LPUART1_TX +# define STM32_CONSOLE_RX GPIO_LPUART1_RX # ifdef CONFIG_LPUART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_LPUART1_RS485_DIR # if (CONFIG_LPUART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART1_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART1_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK2_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB2ENR -# define STM32WL5_CONSOLE_APBEN RCC_APB2ENR_USART1EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART1_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART1_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART1_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART1_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART1_TX -# define STM32WL5_CONSOLE_RX GPIO_USART1_RX +# define STM32_CONSOLE_BASE STM32_USART1_BASE +# define STM32_APBCLOCK STM32_PCLK2_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB2ENR +# define STM32_CONSOLE_APBEN RCC_APB2ENR_USART1EN +# define STM32_CONSOLE_BAUD CONFIG_USART1_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART1_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART1_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART1_2STOP +# define STM32_CONSOLE_TX GPIO_USART1_TX +# define STM32_CONSOLE_RX GPIO_USART1_RX # ifdef CONFIG_USART1_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR # if (CONFIG_USART1_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # elif defined(CONFIG_USART2_SERIAL_CONSOLE) -# define STM32WL5_CONSOLE_BASE STM32WL5_USART2_BASE -# define STM32WL5_APBCLOCK STM32WL5_PCLK1_FREQUENCY -# define STM32WL5_CONSOLE_APBREG STM32WL5_RCC_APB1ENR1 -# define STM32WL5_CONSOLE_APBEN RCC_APB1ENR1_USART2EN -# define STM32WL5_CONSOLE_BAUD CONFIG_USART2_BAUD -# define STM32WL5_CONSOLE_BITS CONFIG_USART2_BITS -# define STM32WL5_CONSOLE_PARITY CONFIG_USART2_PARITY -# define STM32WL5_CONSOLE_2STOP CONFIG_USART2_2STOP -# define STM32WL5_CONSOLE_TX GPIO_USART2_TX -# define STM32WL5_CONSOLE_RX GPIO_USART2_RX +# define STM32_CONSOLE_BASE STM32_USART2_BASE +# define STM32_APBCLOCK STM32_PCLK1_FREQUENCY +# define STM32_CONSOLE_APBREG STM32_RCC_APB1ENR1 +# define STM32_CONSOLE_APBEN RCC_APB1ENR1_USART2EN +# define STM32_CONSOLE_BAUD CONFIG_USART2_BAUD +# define STM32_CONSOLE_BITS CONFIG_USART2_BITS +# define STM32_CONSOLE_PARITY CONFIG_USART2_PARITY +# define STM32_CONSOLE_2STOP CONFIG_USART2_2STOP +# define STM32_CONSOLE_TX GPIO_USART2_TX +# define STM32_CONSOLE_RX GPIO_USART2_RX # ifdef CONFIG_USART2_RS485 -# define STM32WL5_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR +# define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR # if (CONFIG_USART2_RS485_DIR_POLARITY == 0) -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY false +# define STM32_CONSOLE_RS485_DIR_POLARITY false # else -# define STM32WL5_CONSOLE_RS485_DIR_POLARITY true +# define STM32_CONSOLE_RS485_DIR_POLARITY true # endif # endif # endif /* CR1 settings */ -# if STM32WL5_CONSOLE_BITS == 9 +# if STM32_CONSOLE_BITS == 9 # define USART_CR1_M0_VALUE USART_CR1_M0 # define USART_CR1_M1_VALUE 0 -# elif STM32WL5_CONSOLE_BITS == 7 +# elif STM32_CONSOLE_BITS == 7 # define USART_CR1_M0_VALUE 0 # define USART_CR1_M1_VALUE USART_CR1_M1 # else /* 8 bits */ @@ -118,9 +118,9 @@ # define USART_CR1_M1_VALUE 0 # endif -# if STM32WL5_CONSOLE_PARITY == 1 /* odd parity */ +# if STM32_CONSOLE_PARITY == 1 /* odd parity */ # define USART_CR1_PARITY_VALUE (USART_CR1_PCE|USART_CR1_PS) -# elif STM32WL5_CONSOLE_PARITY == 2 /* even parity */ +# elif STM32_CONSOLE_PARITY == 2 /* even parity */ # define USART_CR1_PARITY_VALUE USART_CR1_PCE # else /* no parity */ # define USART_CR1_PARITY_VALUE 0 @@ -136,7 +136,7 @@ /* CR2 settings */ -# if STM32WL5_CONSOLE_2STOP != 0 +# if STM32_CONSOLE_2STOP != 0 # define USART_CR2_STOP2_VALUE USART_CR2_STOP2 # else # define USART_CR2_STOP2_VALUE 0 @@ -178,24 +178,24 @@ * UARTDIV = 2 * fCK / baud */ -# define STM32WL5_USARTDIV8 \ - (((STM32WL5_APBCLOCK << 1) + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) -# define STM32WL5_USARTDIV16 \ - ((STM32WL5_APBCLOCK + (STM32WL5_CONSOLE_BAUD >> 1)) / STM32WL5_CONSOLE_BAUD) +# define STM32_USARTDIV8 \ + (((STM32_APBCLOCK << 1) + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) +# define STM32_USARTDIV16 \ + ((STM32_APBCLOCK + (STM32_CONSOLE_BAUD >> 1)) / STM32_CONSOLE_BAUD) /* Use oversamply by 8 only if the divisor is small. But what is small? */ # if defined(CONFIG_LPUART1_SERIAL_CONSOLE) /* lpuart has different formula for baud rate than normal uart */ -# define STM32WL5_BRR_VALUE \ - (((256ull * STM32WL5_APBCLOCK) / STM32WL5_CONSOLE_BAUD) & LPUART_BRR_MASK) +# define STM32_BRR_VALUE \ + (((256ull * STM32_APBCLOCK) / STM32_CONSOLE_BAUD) & LPUART_BRR_MASK) # else /* CONFIG_LPUART1_SERIAL_CONSOLE */ -# if STM32WL5_USARTDIV8 > 2000 -# define STM32WL5_BRR_VALUE STM32WL5_USARTDIV16 +# if STM32_USARTDIV8 > 2000 +# define STM32_BRR_VALUE STM32_USARTDIV16 # else # define USE_OVER8 1 -# define STM32WL5_BRR_VALUE \ - ((STM32WL5_USARTDIV8 & 0xfff0) | ((STM32WL5_USARTDIV8 & 0x000f) >> 1)) +# define STM32_BRR_VALUE \ + ((STM32_USARTDIV8 & 0xfff0) | ((STM32_USARTDIV8 & 0x000f) >> 1)) # endif # endif /* CONFIG_LPUART1_SERIAL_CONSOLE */ @@ -238,22 +238,22 @@ void arm_lowputc(char ch) #ifdef HAVE_CONSOLE /* Wait until the TX data register is empty */ - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Then send the character */ - putreg32((uint32_t)ch, STM32WL5_CONSOLE_BASE + STM32WL5_USART_TDR_OFFSET); + putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET); -#ifdef STM32WL5_CONSOLE_RS485_DIR - while ((getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_ISR_OFFSET) & +#ifdef STM32_CONSOLE_RS485_DIR + while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif #endif /* HAVE_CONSOLE */ @@ -279,7 +279,7 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) /* Enable USART APB1/2 clock */ - modifyreg32(STM32WL5_CONSOLE_APBREG, 0, STM32WL5_CONSOLE_APBEN); + modifyreg32(STM32_CONSOLE_APBREG, 0, STM32_CONSOLE_APBEN); #endif /* Enable the console USART and configure GPIO pins needed for rx/tx. @@ -288,17 +288,17 @@ void stm32wl5_lowsetup(void) * stm32wl5_rcc.c */ -#ifdef STM32WL5_CONSOLE_TX - stm32wl5_configgpio(STM32WL5_CONSOLE_TX); +#ifdef STM32_CONSOLE_TX + stm32wl5_configgpio(STM32_CONSOLE_TX); #endif -#ifdef STM32WL5_CONSOLE_RX - stm32wl5_configgpio(STM32WL5_CONSOLE_RX); +#ifdef STM32_CONSOLE_RX + stm32wl5_configgpio(STM32_CONSOLE_RX); #endif -#ifdef STM32WL5_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32WL5_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32WL5_CONSOLE_RS485_DIR, - !STM32WL5_CONSOLE_RS485_DIR_POLARITY); +#ifdef STM32_CONSOLE_RS485_DIR + stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR); + stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + !STM32_CONSOLE_RS485_DIR_POLARITY); #endif /* Enable and configure the selected console device */ @@ -306,42 +306,42 @@ void stm32wl5_lowsetup(void) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) /* Configure CR2 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); cr &= ~USART_CR2_CLRBITS; cr |= USART_CR2_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR2_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR2_OFFSET); /* Configure CR1 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); cr &= ~USART_CR1_CLRBITS; cr |= USART_CR1_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); /* Configure CR3 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_CLRBITS; cr |= USART_CR3_SETBITS; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR3_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR3_OFFSET); /* Configure the USART Baud Rate */ - putreg32(STM32WL5_BRR_VALUE, - STM32WL5_CONSOLE_BASE + STM32WL5_USART_BRR_OFFSET); + putreg32(STM32_BRR_VALUE, + STM32_CONSOLE_BASE + STM32_USART_BRR_OFFSET); /* Select oversampling by 8 */ - cr = getreg32(STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + cr = getreg32(STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #ifdef USE_OVER8 cr |= USART_CR1_OVER8; - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* Enable Rx, Tx, and the USART */ cr |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - putreg32(cr, STM32WL5_CONSOLE_BASE + STM32WL5_USART_CR1_OFFSET); + putreg32(cr, STM32_CONSOLE_BASE + STM32_USART_CR1_OFFSET); #endif /* HAVE_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ #endif /* HAVE_UART */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 5abad5f93ab..fe1bcb5ff4d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -89,7 +89,7 @@ void stm32wl5_rcc_enablelse(void) * clock are already running. */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY | RCC_BDCR_LSESYSEN | RCC_BDCR_LSESYSEN)) != @@ -117,7 +117,7 @@ void stm32wl5_rcc_enablelse(void) regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif @@ -126,11 +126,11 @@ void stm32wl5_rcc_enablelse(void) { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); regval |= drives[drive++]; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE clock to be ready (or until a timeout elapsed) */ @@ -139,7 +139,7 @@ void stm32wl5_rcc_enablelse(void) { /* Check if the LSERDY flag is the set in the BDCR */ - regval = getreg32(STM32WL5_RCC_BDCR); + regval = getreg32(STM32_RCC_BDCR); if (regval & RCC_BDCR_LSERDY) { @@ -167,11 +167,11 @@ void stm32wl5_rcc_enablelse(void) regval |= RCC_BDCR_LSESYSEN; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); /* Wait for the LSE system clock to be ready */ - while (!((regval = getreg32(STM32WL5_RCC_BDCR)) & + while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { stm32wl5_waste(); @@ -184,7 +184,7 @@ void stm32wl5_rcc_enablelse(void) regval &= ~RCC_BDCR_LSEDRV_MASK; regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT; - putreg32(regval, STM32WL5_RCC_BDCR); + putreg32(regval, STM32_RCC_BDCR); #endif /* Disable backup domain access if it was disabled on entry */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index ea4495ddbd6..5b5b36395df 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -46,11 +46,11 @@ void stm32wl5_rcc_enablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, 0, RCC_CSR_LSION); + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); /* Wait for the internal LSI oscillator to be stable. */ - while ((getreg32(STM32WL5_RCC_CSR) & RCC_CSR_LSIRDY) == 0); + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); } /**************************************************************************** @@ -67,7 +67,7 @@ void stm32wl5_rcc_disablelsi(void) * bit the RCC CSR register. */ - modifyreg32(STM32WL5_RCC_CSR, RCC_CSR_LSION, 0); + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); /* LSIRDY should go low after 3 LSI clock cycles */ } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index e1a1644ed56..1e0fa171389 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -42,18 +42,18 @@ static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) { - return (uint16_t)getreg32(STM32WL5_PWR_BASE + (uint32_t)offset); + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) { - putreg32((uint32_t)value, STM32WL5_PWR_BASE + (uint32_t)offset); + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg32(STM32WL5_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); } @@ -83,7 +83,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32WL5_PWR_CR1_OFFSET); + regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32WL5_PWR_CR1_OFFSET, regval); + stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -121,5 +121,5 @@ bool stm32wl5_pwr_enablebkp(bool writable) void stm32wl5_pwr_boot_c2(void) { - modifyreg32(STM32WL5_PWR_CR4, 0, PWR_CR4_C2BOOT); + modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 571ea43fc7f..cbc5c60afc8 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -84,14 +84,14 @@ static inline void stm32wl5_rcc_resetbkp(void) init_stat = stm32wl5_rtc_is_initialized(); if (!init_stat) { - uint32_t bkregs[STM32WL5_RTC_BKCOUNT]; + uint32_t bkregs[STM32_RTC_BKCOUNT]; int i; /* Backup backup-registers before RTC reset. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - bkregs[i] = getreg32(STM32WL5_RTC_BKR(i)); + bkregs[i] = getreg32(STM32_RTC_BKR(i)); } /* Enable write access to the backup domain (RTC registers, RTC @@ -104,19 +104,19 @@ static inline void stm32wl5_rcc_resetbkp(void) * reset the backup domain (having backed up the RTC_MAGIC token) */ - modifyreg32(STM32WL5_RCC_BDCR, 0, RCC_BDCR_BDRST); - modifyreg32(STM32WL5_RCC_BDCR, RCC_BDCR_BDRST, 0); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); /* Restore backup-registers, except RTC related. */ - for (i = 0; i < STM32WL5_RTC_BKCOUNT; i++) + for (i = 0; i < STM32_RTC_BKCOUNT; i++) { - if (RTC_MAGIC_REG == STM32WL5_RTC_BKR(i)) + if (RTC_MAGIC_REG == STM32_RTC_BKR(i)) { continue; } - putreg32(bkregs[i], STM32WL5_RTC_BKR(i)); + putreg32(bkregs[i], STM32_RTC_BKR(i)); } (void)stm32wl5_pwr_enablebkp(false); @@ -199,7 +199,7 @@ static void stm32wl5_rcc_enableahb1(void) * selected AHB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB1ENR); + regval = getreg32(STM32_RCC_AHB1ENR); #ifdef CONFIG_STM32WL5_DMA1 /* DMA 1 clock enable */ @@ -219,7 +219,7 @@ static void stm32wl5_rcc_enableahb1(void) regval |= RCC_AHB1ENR_CRCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB1ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } /**************************************************************************** @@ -238,25 +238,25 @@ static inline void stm32wl5_rcc_enableahb2(void) * selected AHB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB2ENR); + regval = getreg32(STM32_RCC_AHB2ENR); /* Enable GPIOA, GPIOB, .... GPIOH */ -#if STM32WL5_NPORTS > 0 +#if STM32_NPORTS > 0 regval |= (RCC_AHB2ENR_GPIOAEN -#if STM32WL5_NPORTS > 1 +#if STM32_NPORTS > 1 | RCC_AHB2ENR_GPIOBEN #endif -#if STM32WL5_NPORTS > 2 +#if STM32_NPORTS > 2 | RCC_AHB2ENR_GPIOCEN #endif -#if STM32WL5_NPORTS > 3 +#if STM32_NPORTS > 3 | RCC_AHB2ENR_GPIOHEN #endif ); -#endif /* STM32WL5_NPORTS */ +#endif /* STM32_NPORTS */ - putreg32(regval, STM32WL5_RCC_AHB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -275,7 +275,7 @@ static inline void stm32wl5_rcc_enableahb3(void) * selected AHB3 peripherals. */ - regval = getreg32(STM32WL5_RCC_AHB3ENR); + regval = getreg32(STM32_RCC_AHB3ENR); #ifdef CONFIG_STM32WL5_AES /* Cryptographic modules clock enable */ @@ -301,7 +301,7 @@ static inline void stm32wl5_rcc_enableahb3(void) regval |= RCC_AHB3ENR_IPCCEN; #endif - putreg32(regval, STM32WL5_RCC_AHB3ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ } /**************************************************************************** @@ -320,7 +320,7 @@ static inline void stm32wl5_rcc_enableapb1(void) * selected APB1 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB1ENR1); + regval = getreg32(STM32_RCC_APB1ENR1); #ifdef CONFIG_STM32WL5_TIM2 /* TIM2 clock enable */ @@ -370,11 +370,11 @@ static inline void stm32wl5_rcc_enableapb1(void) regval |= RCC_APB1ENR1_LPTIM1EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR1); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR1); /* Enable peripherals */ /* Second APB1 register */ - regval = getreg32(STM32WL5_RCC_APB1ENR2); + regval = getreg32(STM32_RCC_APB1ENR2); #ifdef CONFIG_STM32WL5_LPUART1 /* Low power uart clock enable */ @@ -394,7 +394,7 @@ static inline void stm32wl5_rcc_enableapb1(void) regval |= RCC_APB1ENR2_LPTIM3EN; #endif - putreg32(regval, STM32WL5_RCC_APB1ENR2); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB1ENR2); /* Enable peripherals */ } /**************************************************************************** @@ -413,7 +413,7 @@ static inline void stm32wl5_rcc_enableapb2(void) * selected APB2 peripherals. */ - regval = getreg32(STM32WL5_RCC_APB2ENR); + regval = getreg32(STM32_RCC_APB2ENR); #if defined(CONFIG_STM32WL5_ADC1) /* ADC clock enable */ @@ -451,7 +451,7 @@ static inline void stm32wl5_rcc_enableapb2(void) regval |= RCC_APB2ENR_TIM17EN; #endif - putreg32(regval, STM32WL5_RCC_APB2ENR); /* Enable peripherals */ + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ } /**************************************************************************** @@ -471,9 +471,9 @@ static inline void stm32wl5_rcc_enableccip(void) * will at least have a clock. */ - regval = getreg32(STM32WL5_RCC_CCIPR); + regval = getreg32(STM32_RCC_CCIPR); -#if defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WL5_I2C1 /* Select HSI16 as I2C1 clock source. */ @@ -489,15 +489,15 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_I2C3SEL_HSI; #endif -#endif /* STM32WL5_I2C_USE_HSI16 */ +#endif /* STM32_I2C_USE_HSI16 */ -#if defined(STM32WL5_USE_CLK48) +#if defined(STM32_USE_CLK48) /* XXX sanity if sdmmc1 or usb or rng, then we need to set the clk48 source - * and then we can also do away with STM32WL5_USE_CLK48, and give better + * and then we can also do away with STM32_USE_CLK48, and give better * warning messages. */ - regval |= STM32WL5_CLK48_SEL; + regval |= STM32_CLK48_SEL; #endif #if defined(CONFIG_STM32WL5_ADC1) @@ -518,19 +518,19 @@ static inline void stm32wl5_rcc_enableccip(void) regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; #endif - putreg32(regval, STM32WL5_RCC_CCIPR); + putreg32(regval, STM32_RCC_CCIPR); /* I2C4 alone has their clock selection in CCIPR2 register. */ -#if defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_I2C_USE_HSI16) #ifdef CONFIG_STM32WL5_I2C4 - regval = getreg32(STM32WL5_RCC_CCIPR2); + regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ regval |= RCC_CCIPR_I2C4SEL_HSI; - putreg32(regval, STM32WL5_RCC_CCIPR2); + putreg32(regval, STM32_RCC_CCIPR2); #endif #endif } @@ -610,12 +610,12 @@ void stm32wl5_stdclockconfig(void) { uint32_t regval; -#if defined(STM32WL5_BOARD_USEHSI) || defined(STM32WL5_I2C_USE_HSI16) +#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16) /* Enable Internal High-Speed Clock (HSI) */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSION; /* Enable HSI */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSI is ready */ @@ -623,7 +623,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) { /* If so, then break-out */ @@ -632,17 +632,17 @@ void stm32wl5_stdclockconfig(void) } #endif -#if defined(STM32WL5_BOARD_USEHSI) +#if defined(STM32_BOARD_USEHSI) /* Already set above */ -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) /* Enable Internal Multi-Speed Clock (MSI) */ /* Wait until the MSI is either off or ready */ for (; ; ) { - if ((regval = getreg32(STM32WL5_RCC_CR)), + if ((regval = getreg32(STM32_RCC_CR)), (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION)) { /* If so, then break-out */ @@ -653,9 +653,9 @@ void stm32wl5_stdclockconfig(void) /* setting MSIRANGE */ - regval = getreg32(STM32WL5_RCC_CR); - regval |= (STM32WL5_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ - putreg32(regval, STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); + regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */ + putreg32(regval, STM32_RCC_CR); /* Wait until the MSI is ready */ @@ -663,7 +663,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the MSIRDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_MSIRDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0) { /* If so, then break-out */ @@ -671,23 +671,23 @@ void stm32wl5_stdclockconfig(void) } } -#elif defined(STM32WL5_BOARD_USEHSE) +#elif defined(STM32_BOARD_USEHSE) /* Enable External High-Speed Clock (HSE) */ -#if defined(STM32WL5_BOARD_USETCXO) +#if defined(STM32_BOARD_USETCXO) /* nucleo-wl55jc uses TCXO crystal, which needs to be first * powered up with PB0 pin - or more conveniently by setting * HSEBYPPWR register. This has to be done before HSE is enabled */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEBYPPWR; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); #endif - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_HSEON; /* Enable HSE */ - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the HSE is ready */ @@ -695,7 +695,7 @@ void stm32wl5_stdclockconfig(void) { /* Check if the HSERDY flag is the set in the CR */ - if ((getreg32(STM32WL5_RCC_CR) & RCC_CR_HSERDY) != 0) + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) { /* If so, then break-out */ @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32WL5_BOARD_USEHSI, STM32WL5_BOARD_USEMSI, STM32WL5_BOARD_USEHSE defined +# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -714,10 +714,10 @@ void stm32wl5_stdclockconfig(void) /* Select correct main regulator range */ - regval = getreg32(STM32WL5_PWR_CR1); + regval = getreg32(STM32_PWR_CR1); regval &= ~PWR_CR1_VOS_MASK; - if (STM32WL5_SYSCLK_FREQUENCY <= 16000000) + if (STM32_SYSCLK_FREQUENCY <= 16000000) { /* set low power range for frequencies <= 16MHz */ @@ -730,121 +730,121 @@ void stm32wl5_stdclockconfig(void) regval |= PWR_CR1_VOS_RANGE1; } - putreg32(regval, STM32WL5_PWR_CR1); + putreg32(regval, STM32_PWR_CR1); /* Wait for voltage regulator to stabilize */ - while (getreg32(STM32WL5_PWR_SR2) & PWR_SR2_VOSF) + while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF) { } /* Set the HCLK source/divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32WL5_RCC_CFGR_HPRE; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_HPRE; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK2 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE2; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE2; + putreg32(regval, STM32_RCC_CFGR); /* Set the PCLK1 divider */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32WL5_RCC_CFGR_PPRE1; - putreg32(regval, STM32WL5_RCC_CFGR); + regval |= STM32_RCC_CFGR_PPRE1; + putreg32(regval, STM32_RCC_CFGR); #ifdef CONFIG_STM32WL5_RTC_HSECLOCK /* Set the RTC clock divisor */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_RTCPRE_MASK; regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); #endif /* Set the PLL source and main divider */ - regval = getreg32(STM32WL5_RCC_PLLCFG); + regval = getreg32(STM32_RCC_PLLCFG); /* Configure Main PLL */ /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32WL5_PLLCFG_PLLM | STM32WL5_PLLCFG_PLLN | - STM32WL5_PLLCFG_PLLP | STM32WL5_PLLCFG_PLLQ | - STM32WL5_PLLCFG_PLLR); + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | + STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ | + STM32_PLLCFG_PLLR); -#ifdef STM32WL5_PLLCFG_PLLP_ENABLED +#ifdef STM32_PLLCFG_PLLP_ENABLED regval |= RCC_PLLCFG_PLLPEN; #endif -#ifdef STM32WL5_PLLCFG_PLLQ_ENABLED +#ifdef STM32_PLLCFG_PLLQ_ENABLED regval |= RCC_PLLCFG_PLLQEN; #endif -#ifdef STM32WL5_PLLCFG_PLLR_ENABLED +#ifdef STM32_PLLCFG_PLLR_ENABLED regval |= RCC_PLLCFG_PLLREN; #endif /* XXX The choice of clock source to PLL (all three) is independent - * of the sys clock source choice, review the STM32WL5_BOARD_USEHSI + * of the sys clock source choice, review the STM32_BOARD_USEHSI * name; probably split it into two, one for PLL source and one * for sys clock source. */ -#ifdef STM32WL5_BOARD_USEHSI +#ifdef STM32_BOARD_USEHSI regval |= RCC_PLLCFG_PLLSRC_HSI16; -#elif defined(STM32WL5_BOARD_USEMSI) +#elif defined(STM32_BOARD_USEMSI) regval |= RCC_PLLCFG_PLLSRC_MSI; -#else /* if STM32WL5_BOARD_USEHSE */ +#else /* if STM32_BOARD_USEHSE */ regval |= RCC_PLLCFG_PLLSRC_HSE; #endif - putreg32(regval, STM32WL5_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCFG); /* Enable the main PLL */ - regval = getreg32(STM32WL5_RCC_CR); + regval = getreg32(STM32_RCC_CR); regval |= RCC_CR_PLLON; - putreg32(regval, STM32WL5_RCC_CR); + putreg32(regval, STM32_RCC_CR); /* Wait until the PLL is ready */ - while ((getreg32(STM32WL5_RCC_CR) & RCC_CR_PLLRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) { } /* Configure flash wait states according to manual */ - if (STM32WL5_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) + if (STM32_HCLK3_FREQUENCY <= 18000000 /* 18MHz */) { regval = FLASH_ACR_LATENCY_0; } - else if (STM32WL5_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) + else if (STM32_HCLK3_FREQUENCY <= 36000000 /* 36MHz */) { regval = FLASH_ACR_LATENCY_1; } - else /* STM32WL5_HCLK3_FREQUENCY <= 48MHz */ + else /* STM32_HCLK3_FREQUENCY <= 48MHz */ { regval = FLASH_ACR_LATENCY_2; } - putreg32(regval, STM32WL5_FLASH_ACR); + putreg32(regval, STM32_FLASH_ACR); /* Select the main PLL as system clock source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; regval |= RCC_CFGR_SW_PLL; - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32WL5_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 1989f237afd..3d563c431c4 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -77,10 +77,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) /* Set MCO source */ - regval = getreg32(STM32WL5_RCC_CFGR); + regval = getreg32(STM32_RCC_CFGR); regval &= ~(RCC_CFGR_MCOSEL_MASK); regval |= (source & RCC_CFGR_MCOSEL_MASK); - putreg32(regval, STM32WL5_RCC_CFGR); + putreg32(regval, STM32_RCC_CFGR); } /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 524483ef5cb..462d9170324 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -418,13 +418,13 @@ static struct stm32wl5_serial_s g_lpuart1priv = .priv = &g_lpuart1priv, }, - .irq = STM32WL5_IRQ_LPUART1, + .irq = STM32_IRQ_LPUART1, .parity = CONFIG_LPUART1_PARITY, .bits = CONFIG_LPUART1_BITS, .stopbits2 = CONFIG_LPUART1_2STOP, .baud = CONFIG_LPUART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_LPUART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_LPUART1_BASE, .tx_gpio = GPIO_LPUART1_TX, .rx_gpio = GPIO_LPUART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) @@ -478,13 +478,13 @@ static struct stm32wl5_serial_s g_usart1priv = .priv = &g_usart1priv, }, - .irq = STM32WL5_IRQ_USART1, + .irq = STM32_IRQ_USART1, .parity = CONFIG_USART1_PARITY, .bits = CONFIG_USART1_BITS, .stopbits2 = CONFIG_USART1_2STOP, .baud = CONFIG_USART1_BAUD, - .apbclock = STM32WL5_PCLK2_FREQUENCY, - .usartbase = STM32WL5_USART1_BASE, + .apbclock = STM32_PCLK2_FREQUENCY, + .usartbase = STM32_USART1_BASE, .tx_gpio = GPIO_USART1_TX, .rx_gpio = GPIO_USART1_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART1_OFLOWCONTROL) @@ -540,13 +540,13 @@ static struct stm32wl5_serial_s g_usart2priv = .priv = &g_usart2priv, }, - .irq = STM32WL5_IRQ_USART2, + .irq = STM32_IRQ_USART2, .parity = CONFIG_USART2_PARITY, .bits = CONFIG_USART2_BITS, .stopbits2 = CONFIG_USART2_2STOP, .baud = CONFIG_USART2_BAUD, - .apbclock = STM32WL5_PCLK1_FREQUENCY, - .usartbase = STM32WL5_USART2_BASE, + .apbclock = STM32_PCLK1_FREQUENCY, + .usartbase = STM32_USART2_BASE, .tx_gpio = GPIO_USART2_TX, .rx_gpio = GPIO_USART2_RX, # if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART2_OFLOWCONTROL) @@ -577,7 +577,7 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ static struct stm32wl5_serial_s * const - g_uart_devs[STM32WL5_NLPUART + STM32WL5_NUSART] = + g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, @@ -647,15 +647,15 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * above) */ - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** @@ -710,8 +710,8 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - cr3 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -772,7 +772,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; - if (priv->usartbase == STM32WL5_LPUART1_BASE) + if (priv->usartbase == STM32_LPUART1_BASE) { /* lpuart has different calculations baudrate, and there is not * oversampling: @@ -804,7 +804,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * But what is small? */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); if (usartdiv8 > 2000) { /* Use usartdiv16 */ @@ -828,14 +828,14 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) cr1 |= USART_CR1_OVER8; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); } - stm32wl5serial_putreg(priv, STM32WL5_USART_BRR_OFFSET, brr); + stm32wl5serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); /* Configure parity mode */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -873,11 +873,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -885,11 +885,11 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) @@ -906,7 +906,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -951,7 +951,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Wait last Tx to complete. */ - while ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + while ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_DMA @@ -1057,7 +1057,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -1097,21 +1097,21 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) default: return; #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER - case STM32WL5_LPUART1_BASE: + case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; - regaddr = STM32WL5_RCC_APB1ENR2; + regaddr = STM32_RCC_APB1ENR2; break; #endif #ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER - case STM32WL5_USART1_BASE: + case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; - regaddr = STM32WL5_RCC_APB2ENR; + regaddr = STM32_RCC_APB2ENR; break; #endif #ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER - case STM32WL5_USART2_BASE: + case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; - regaddr = STM32WL5_RCC_APB1ENR1; + regaddr = STM32_RCC_APB1ENR1; break; #endif } @@ -1198,7 +1198,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1209,26 +1209,26 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ @@ -1236,9 +1236,9 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) /* Enable Rx, Tx, and the USART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1291,7 +1291,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -1302,7 +1302,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -1316,9 +1316,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1376,9 +1376,9 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) /* Disable Rx, Tx, and the UART */ - regval = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + regval = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, regval); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1544,7 +1544,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Get the masked USART status word. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1612,7 +1612,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, * interrupt clear register (ICR). */ - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1685,19 +1685,19 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR3_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1742,11 +1742,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR3_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1763,17 +1763,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1793,11 +1793,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1814,17 +1814,17 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wl5serial_getreg(priv, STM32WL5_USART_CR2_OFFSET); + uint32_t cr = stm32wl5serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1835,11 +1835,11 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wl5serial_putreg(priv, STM32WL5_USART_CR2_OFFSET, cr); + stm32wl5serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1996,8 +1996,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -2009,8 +2009,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wl5serial_getreg(priv, STM32WL5_USART_CR1_OFFSET); - stm32wl5serial_putreg(priv, STM32WL5_USART_CR1_OFFSET, + cr1 = stm32wl5serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32wl5serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -2046,7 +2046,7 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, /* Get the Rx byte */ - rdr = stm32wl5serial_getreg(priv, STM32WL5_USART_RDR_OFFSET); + rdr = stm32wl5serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -2133,7 +2133,7 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif @@ -2296,7 +2296,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for non-circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_IFLOW_CONTROL_WORD); @@ -2307,7 +2307,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) /* Configure for circular DMA reception into the RX FIFO */ stm32wl5_dmasetup(priv->rxdma, - priv->usartbase + STM32WL5_USART_RDR_OFFSET, + priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, SERIAL_DMA_CONTROL_WORD); @@ -2476,7 +2476,7 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) } #endif - stm32wl5serial_putreg(priv, STM32WL5_USART_TDR_OFFSET, (uint32_t)ch); + stm32wl5serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** @@ -2561,7 +2561,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; - return ((stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET) & + return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2603,11 +2603,11 @@ static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wl5serial_getreg(priv, STM32WL5_USART_ISR_OFFSET); + priv->sr = stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NF | USART_ISR_FE)) != 0) { - stm32wl5serial_putreg(priv, STM32WL5_USART_ICR_OFFSET, + stm32wl5serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2743,7 +2743,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32WL5_NLPUART + STM32WL5_NUSART; n++) + for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { struct stm32wl5_serial_s *priv = g_uart_devs[n]; @@ -2813,7 +2813,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -2882,7 +2882,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32WL5_NLPUART + STM32WL5_NUSART; i++) + for (i = 0; i < STM32_NLPUART + STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 3aa45fe20c4..55229b62434 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -316,10 +316,10 @@ static struct stm32wl5_spidev_s g_spi1dev = { .ops = &g_sp1iops, }, - .spibase = STM32WL5_SPI1_BASE, - .spiclock = STM32WL5_PCLK2_FREQUENCY, + .spibase = STM32_SPI1_BASE, + .spiclock = STM32_PCLK2_FREQUENCY, #ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI1, + .spiirq = STM32_IRQ_SPI1, #endif #ifdef CONFIG_STM32WL5_SPI_DMA # ifdef CONFIG_STM32WL5_SPI1_DMA @@ -386,10 +386,10 @@ static struct stm32wl5_spidev_s g_spi2s2dev = { &g_sp2iops }, - .spibase = STM32WL5_SPI2S2_BASE, - .spiclock = STM32WL5_PCLK1_FREQUENCY, + .spibase = STM32_SPI2S2_BASE, + .spiclock = STM32_PCLK1_FREQUENCY, #ifdef CONFIG_STM32WL5_SPI_INTERRUPTS - .spiirq = STM32WL5_IRQ_SPI2S2, + .spiirq = STM32_IRQ_SPI2S2, #endif #ifdef CONFIG_STM32WL5_SPI_DMA # ifdef CONFIG_STM32WL5_SPI2S2_DMA @@ -518,7 +518,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) { /* Wait until the receive buffer is not empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_RXNE) == 0) { } @@ -539,11 +539,11 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) if (priv->nbits < 9) { - return (uint16_t)spi_getreg8(priv, STM32WL5_SPI_DR_OFFSET); + return (uint16_t)spi_getreg8(priv, STM32_SPI_DR_OFFSET); } else { - return spi_getreg(priv, STM32WL5_SPI_DR_OFFSET); + return spi_getreg(priv, STM32_SPI_DR_OFFSET); } } @@ -568,7 +568,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, { /* Wait until the transmit buffer is empty */ - while ((spi_getreg(priv, STM32WL5_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) + while ((spi_getreg(priv, STM32_SPI_SR_OFFSET) & SPI_SR_TXE) == 0) { } @@ -576,11 +576,11 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, if (priv->nbits < 9) { - spi_putreg8(priv, STM32WL5_SPI_DR_OFFSET, (uint8_t)word); + spi_putreg8(priv, STM32_SPI_DR_OFFSET, (uint8_t)word); } else { - spi_putreg(priv, STM32WL5_SPI_DR_OFFSET, word); + spi_putreg(priv, STM32_SPI_DR_OFFSET, word); } } @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32WL5_SPI_DR_OFFSET, + stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -875,12 +875,12 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, uint16_t clrbits) { uint16_t cr1; - cr1 = spi_getreg(priv, STM32WL5_SPI_CR1_OFFSET); + cr1 = spi_getreg(priv, STM32_SPI_CR1_OFFSET); cr1 &= ~clrbits; cr1 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR1_OFFSET, cr1); + spi_putreg(priv, STM32_SPI_CR1_OFFSET, cr1); - spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR1_OFFSET, + spiinfo("CR1 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR1_OFFSET, cr1); } @@ -904,11 +904,11 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; - cr2 = spi_getreg(priv, STM32WL5_SPI_CR2_OFFSET); + cr2 = spi_getreg(priv, STM32_SPI_CR2_OFFSET); cr2 &= ~clrbits; cr2 |= setbits; - spi_putreg(priv, STM32WL5_SPI_CR2_OFFSET, cr2); - spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32WL5_SPI_CR2_OFFSET, + spi_putreg(priv, STM32_SPI_CR2_OFFSET, cr2); + spiinfo("CR2 (0x%lx) = 0x%04x\n", priv->spibase + STM32_SPI_CR2_OFFSET, cr2); } @@ -1314,7 +1314,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * (Reading from the SR clears the error flags) */ - regval = spi_getreg(priv, STM32WL5_SPI_SR_OFFSET); + regval = spi_getreg(priv, STM32_SPI_SR_OFFSET); spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", wd, ret, regval); @@ -1731,7 +1731,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) /* CRCPOLY configuration */ - spi_putreg(priv, STM32WL5_SPI_CRCPR_OFFSET, 7); + spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WL5_SPI_DMA if (priv->rxch && priv->txch) diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index e828fca974e..aedd8b76cbf 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -60,8 +60,8 @@ * 0x2000:8000 - Start of internal SRAM2 */ -#define SRAM2_START STM32WL5_SRAM2_BASE -#define SRAM2_END (SRAM2_START + STM32WL5_SRAM2_SIZE) +#define SRAM2_START STM32_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE) #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 7be699ed8f7..9ecd2811a6e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -306,16 +306,16 @@ static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM1_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM2 struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM2_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, }; #endif @@ -323,8 +323,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM3_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, }; #endif @@ -332,8 +332,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM4_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, }; #endif @@ -341,8 +341,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM5_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, }; #endif @@ -350,8 +350,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM6_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, }; #endif @@ -359,8 +359,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM7_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, }; #endif @@ -368,8 +368,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM8_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, }; #endif @@ -377,8 +377,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM15_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, }; #endif @@ -386,8 +386,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM16_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, }; #endif @@ -395,8 +395,8 @@ struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = { .ops = &stm32wl5_tim_ops, - .mode = STM32WL5_TIM_MODE_UNUSED, - .base = STM32WL5_TIM17_BASE, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, }; #endif @@ -484,9 +484,9 @@ static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_EGR_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32WL5_GTIM_EGR_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** @@ -495,10 +495,10 @@ static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -507,9 +507,9 @@ static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CR1_OFFSET); + uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** @@ -523,7 +523,7 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_DISABLED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; stm32wl5_tim_disable(dev); } @@ -541,7 +541,7 @@ static void stm32wl5_tim_gpioconfig(uint32_t cfg, { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ - if (mode & STM32WL5_TIM_CH_MODE_MASK) + if (mode & STM32_TIM_CH_MODE_MASK) { stm32wl5_configgpio(cfg); } @@ -567,13 +567,13 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -582,19 +582,19 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, /* Decode operational modes */ - switch (mode & STM32WL5_TIM_MODE_MASK) + switch (mode & STM32_TIM_MODE_MASK) { - case STM32WL5_TIM_MODE_DISABLED: + case STM32_TIM_MODE_DISABLED: val = 0; break; - case STM32WL5_TIM_MODE_DOWN: + case STM32_TIM_MODE_DOWN: val |= GTIM_CR1_DIR; - case STM32WL5_TIM_MODE_UP: + case STM32_TIM_MODE_UP: break; - case STM32WL5_TIM_MODE_UPDOWN: + case STM32_TIM_MODE_UPDOWN: val |= GTIM_CR1_CENTER1; /* Our default: Interrupts are generated on compare, when counting @@ -603,7 +603,7 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, break; - case STM32WL5_TIM_MODE_PULSE: + case STM32_TIM_MODE_PULSE: val |= GTIM_CR1_OPM; break; @@ -612,15 +612,15 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CR1_OFFSET, val); + stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); -#if STM32WL5_NATIM > 0 +#if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM8_BASE) + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32WL5_ATIM_BDTR_OFFSET, + stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -657,66 +657,66 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -747,7 +747,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32WL5_GTIM_PSC_OFFSET, prescaler); + stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); stm32wl5_tim_enable(dev); return prescaler; @@ -772,64 +772,64 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: + case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: + case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; #endif @@ -839,7 +839,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32WL5_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } @@ -851,7 +851,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32WL5_GTIM_ARR_OFFSET, period); + stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** @@ -861,7 +861,7 @@ static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32WL5_GTIM_ARR_OFFSET); + return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** @@ -871,7 +871,7 @@ static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32WL5_GTIM_CNT_OFFSET); + uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. @@ -881,10 +881,10 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: #endif return counter; @@ -908,7 +908,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, uint16_t ccmr_val = 0; uint16_t ccmr_mask = 0xff; uint16_t ccer_val; - uint8_t ccmr_offset = STM32WL5_GTIM_CCMR1_OFFSET; + uint8_t ccmr_offset = STM32_GTIM_CCMR1_OFFSET; DEBUGASSERT(dev != NULL); @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32WL5_GTIM_CCER_OFFSET); + ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -929,13 +929,13 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, * disable it, simply set its clock to valid frequency or zero. */ -#if STM32WL5_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM6_BASE +#if STM32_NBTIM > 0 + if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif -#if STM32WL5_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32WL5_TIM7_BASE +#if STM32_NBTIM > 1 + || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif -#if STM32WL5_NBTIM > 0 +#if STM32_NBTIM > 0 ) { return -EINVAL; @@ -944,12 +944,12 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Decode configuration */ - switch (mode & STM32WL5_TIM_CH_MODE_MASK) + switch (mode & STM32_TIM_CH_MODE_MASK) { - case STM32WL5_TIM_CH_DISABLED: + case STM32_TIM_CH_DISABLED: break; - case STM32WL5_TIM_CH_OUTPWM: + case STM32_TIM_CH_OUTPWM: ccmr_val = (GTIM_CCMR_MODE_PWM1 << GTIM_CCMR1_OC1M_SHIFT) + GTIM_CCMR1_OC1PE; ccer_val |= GTIM_CCER_CC1E << GTIM_CCER_CCXBASE(channel); @@ -961,7 +961,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Set polarity */ - if (mode & STM32WL5_TIM_CH_POLARITY_NEG) + if (mode & STM32_TIM_CH_POLARITY_NEG) { ccer_val |= GTIM_CCER_CC1P << GTIM_CCER_CCXBASE(channel); } @@ -976,21 +976,21 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, if (channel > 1) { - ccmr_offset = STM32WL5_GTIM_CCMR2_OFFSET; + ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32WL5_GTIM_CCER_OFFSET, ccer_val); + stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: + case STM32_TIM1_BASE: switch (channel) { #if defined(GPIO_TIM1_CH1OUT) @@ -1023,7 +1023,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: + case STM32_TIM2_BASE: switch (channel) { #if defined(GPIO_TIM2_CH1OUT) @@ -1056,7 +1056,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: + case STM32_TIM3_BASE: switch (channel) { #if defined(GPIO_TIM3_CH1OUT) @@ -1089,7 +1089,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: + case STM32_TIM4_BASE: switch (channel) { #if defined(GPIO_TIM4_CH1OUT) @@ -1121,7 +1121,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: + case STM32_TIM5_BASE: switch (channel) { #if defined(GPIO_TIM5_CH1OUT) @@ -1154,7 +1154,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: + case STM32_TIM8_BASE: switch (channel) { #if defined(GPIO_TIM8_CH1OUT) @@ -1187,7 +1187,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: + case STM32_TIM15_BASE: switch (channel) { #if defined(GPIO_TIM15_CH1OUT) @@ -1220,7 +1220,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: + case STM32_TIM16_BASE: switch (channel) { #if defined(GPIO_TIM16_CH1OUT) @@ -1253,7 +1253,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: + case STM32_TIM17_BASE: switch (channel) { #if defined(GPIO_TIM17_CH1OUT) @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR1_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR2_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR3_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32WL5_GTIM_CCR4_OFFSET, compare); + stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1339,16 +1339,16 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR1_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR2_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR3_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32WL5_GTIM_CCR4_OFFSET); + return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; @@ -1369,66 +1369,66 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - vectorno = STM32WL5_IRQ_TIM1UP; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - vectorno = STM32WL5_IRQ_TIM2; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - vectorno = STM32WL5_IRQ_TIM3; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - vectorno = STM32WL5_IRQ_TIM4; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - vectorno = STM32WL5_IRQ_TIM5; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - vectorno = STM32WL5_IRQ_TIM6; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - vectorno = STM32WL5_IRQ_TIM7; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - vectorno = STM32WL5_IRQ_TIM8UP; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - vectorno = STM32WL5_IRQ_TIM15; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - vectorno = STM32WL5_IRQ_TIM16; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - vectorno = STM32WL5_IRQ_TIM17; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; break; #endif @@ -1461,7 +1461,7 @@ static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** @@ -1472,7 +1472,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32WL5_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** @@ -1481,7 +1481,7 @@ static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32WL5_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** @@ -1491,7 +1491,7 @@ static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32WL5_GTIM_SR_OFFSET); + uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1514,76 +1514,76 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) #ifdef CONFIG_STM32WL5_TIM1 case 1: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WL5_TIM2 case 2: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WL5_TIM3 case 3: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32WL5_TIM4 case 4: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32WL5_TIM5 case 5: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32WL5_TIM6 case 6: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32WL5_TIM7 case 7: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; - modifyreg32(STM32WL5_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); + modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32WL5_TIM8 case 8: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32WL5_TIM15 case 15: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32WL5_TIM16 case 16: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WL5_TIM17 case 17: dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; - modifyreg32(STM32WL5_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,7 +1593,7 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32WL5_TIM_MODE_UNUSED) + if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } @@ -1619,67 +1619,67 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) switch (((struct stm32wl5_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 - case STM32WL5_TIM1_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM2 - case STM32WL5_TIM2_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM3 - case STM32WL5_TIM3_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM4 - case STM32WL5_TIM4_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM5 - case STM32WL5_TIM5_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM6 - case STM32WL5_TIM6_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); + case STM32_TIM6_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM7 - case STM32WL5_TIM7_BASE: - modifyreg32(STM32WL5_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); + case STM32_TIM7_BASE: + modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM8 - case STM32WL5_TIM8_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM15 - case STM32WL5_TIM15_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); + case STM32_TIM15_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM16 - case STM32WL5_TIM16_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); + case STM32_TIM16_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif #ifdef CONFIG_STM32WL5_TIM17 - case STM32WL5_TIM17_BASE: - modifyreg32(STM32WL5_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); + case STM32_TIM17_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; #endif @@ -1689,7 +1689,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32WL5_TIM_MODE_UNUSED; + ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 9826600b87a..53292055355 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -38,20 +38,20 @@ /* Helpers ******************************************************************/ -#define STM32WL5_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) -#define STM32WL5_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) -#define STM32WL5_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) -#define STM32WL5_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) -#define STM32WL5_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) -#define STM32WL5_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) -#define STM32WL5_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) -#define STM32WL5_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) -#define STM32WL5_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) -#define STM32WL5_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) -#define STM32WL5_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) -#define STM32WL5_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) -#define STM32WL5_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) -#define STM32WL5_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) +#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_GETCLOCK(d) ((d)->ops->getclock(d)) +#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s)) +#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) +#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) #define STM32_TIM_ENABLE(d) ((d)->ops->enable(d)) #define STM32_TIM_DISABLE(d) ((d)->ops->disable(d)) @@ -81,34 +81,34 @@ struct stm32wl5_tim_dev_s enum stm32wl5_tim_mode_e { - STM32WL5_TIM_MODE_UNUSED = -1, + STM32_TIM_MODE_UNUSED = -1, /* One of the following */ - STM32WL5_TIM_MODE_MASK = 0x0310, - STM32WL5_TIM_MODE_DISABLED = 0x0000, - STM32WL5_TIM_MODE_UP = 0x0100, - STM32WL5_TIM_MODE_DOWN = 0x0110, - STM32WL5_TIM_MODE_UPDOWN = 0x0200, - STM32WL5_TIM_MODE_PULSE = 0x0300, + STM32_TIM_MODE_MASK = 0x0310, + STM32_TIM_MODE_DISABLED = 0x0000, + STM32_TIM_MODE_UP = 0x0100, + STM32_TIM_MODE_DOWN = 0x0110, + STM32_TIM_MODE_UPDOWN = 0x0200, + STM32_TIM_MODE_PULSE = 0x0300, /* One of the following */ - STM32WL5_TIM_MODE_CK_INT = 0x0000, + STM32_TIM_MODE_CK_INT = 0x0000, #if 0 - STM32WL5_TIM_MODE_CK_INT_TRIG = 0x0400, - STM32WL5_TIM_MODE_CK_EXT = 0x0800, - STM32WL5_TIM_MODE_CK_EXT_TRIG = 0x0c00, + STM32_TIM_MODE_CK_INT_TRIG = 0x0400, + STM32_TIM_MODE_CK_EXT = 0x0800, + STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00, #endif /* Clock sources, OR'ed with CK_EXT */ #if 0 - STM32WL5_TIM_MODE_CK_CHINVALID = 0x0000, - STM32WL5_TIM_MODE_CK_CH1 = 0x0001, - STM32WL5_TIM_MODE_CK_CH2 = 0x0002, - STM32WL5_TIM_MODE_CK_CH3 = 0x0003, - STM32WL5_TIM_MODE_CK_CH4 = 0x0004 + STM32_TIM_MODE_CK_CHINVALID = 0x0000, + STM32_TIM_MODE_CK_CH1 = 0x0001, + STM32_TIM_MODE_CK_CH2 = 0x0002, + STM32_TIM_MODE_CK_CH3 = 0x0003, + STM32_TIM_MODE_CK_CH4 = 0x0004 #endif /* Todo: external trigger block */ @@ -118,22 +118,22 @@ enum stm32wl5_tim_mode_e enum stm32wl5_tim_channel_e { - STM32WL5_TIM_CH_DISABLED = 0x00, + STM32_TIM_CH_DISABLED = 0x00, /* Common configuration */ - STM32WL5_TIM_CH_POLARITY_POS = 0x00, - STM32WL5_TIM_CH_POLARITY_NEG = 0x01, + STM32_TIM_CH_POLARITY_POS = 0x00, + STM32_TIM_CH_POLARITY_NEG = 0x01, /* MODES: */ - STM32WL5_TIM_CH_MODE_MASK = 0x06, + STM32_TIM_CH_MODE_MASK = 0x06, /* Output Compare Modes */ - STM32WL5_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ + STM32_TIM_CH_OUTPWM = 0x04, /* Enable standard PWM mode, active high when counter < compare */ #if 0 - STM32WL5_TIM_CH_OUTCOMPARE = 0x06, + STM32_TIM_CH_OUTCOMPARE = 0x06, #endif }; diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 572c4c95c21..10c2a3c3243 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -52,17 +52,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32WL5_TIM1_RES 16 -#define STM32WL5_TIM2_RES 32 -#define STM32WL5_TIM3_RES 16 -#define STM32WL5_TIM4_RES 16 -#define STM32WL5_TIM5_RES 32 -#define STM32WL5_TIM6_RES 16 -#define STM32WL5_TIM7_RES 16 -#define STM32WL5_TIM8_RES 16 -#define STM32WL5_TIM15_RES 16 -#define STM32WL5_TIM16_RES 16 -#define STM32WL5_TIM17_RES 16 +#define STM32_TIM1_RES 16 +#define STM32_TIM2_RES 32 +#define STM32_TIM3_RES 16 +#define STM32_TIM4_RES 16 +#define STM32_TIM5_RES 32 +#define STM32_TIM6_RES 16 +#define STM32_TIM7_RES 16 +#define STM32_TIM8_RES 16 +#define STM32_TIM15_RES 16 +#define STM32_TIM16_RES 16 +#define STM32_TIM17_RES 16 /**************************************************************************** * Private Types @@ -122,7 +122,7 @@ static const struct timer_ops_s g_timer_ops = static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM1_RES, + .resolution = STM32_TIM1_RES, }; #endif @@ -130,7 +130,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM2_RES, + .resolution = STM32_TIM2_RES, }; #endif @@ -138,7 +138,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM3_RES, + .resolution = STM32_TIM3_RES, }; #endif @@ -146,7 +146,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM4_RES, + .resolution = STM32_TIM4_RES, }; #endif @@ -154,7 +154,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM5_RES, + .resolution = STM32_TIM5_RES, }; #endif @@ -162,7 +162,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM6_RES, + .resolution = STM32_TIM6_RES, }; #endif @@ -170,7 +170,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM7_RES, + .resolution = STM32_TIM7_RES, }; #endif @@ -178,7 +178,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM8_RES, + .resolution = STM32_TIM8_RES, }; #endif @@ -186,7 +186,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM15_RES, + .resolution = STM32_TIM15_RES, }; #endif @@ -194,7 +194,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM16_RES, + .resolution = STM32_TIM16_RES, }; #endif @@ -202,7 +202,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, - .resolution = STM32WL5_TIM17_RES, + .resolution = STM32_TIM17_RES, }; #endif @@ -228,13 +228,13 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) (struct stm32wl5_lowerhalf_s *)arg; uint32_t next_interval_us = 0; - STM32WL5_TIM_ACKINT(lower->tim, 0); + STM32_TIM_ACKINT(lower->tim, 0); if (lower->callback(&next_interval_us, lower->arg)) { if (next_interval_us > 0) { - STM32WL5_TIM_SETPERIOD(lower->tim, next_interval_us); + STM32_TIM_SETPERIOD(lower->tim, next_interval_us); } } else @@ -267,12 +267,12 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) if (!priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_UP); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_UP); if (priv->callback != NULL) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } priv->started = true; @@ -306,9 +306,9 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) if (priv->started) { - STM32WL5_TIM_SETMODE(priv->tim, STM32WL5_TIM_MODE_DISABLED); - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_SETMODE(priv->tim, STM32_TIM_MODE_DISABLED); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); priv->started = false; return OK; } @@ -363,8 +363,8 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get timeout */ maxtimeout = (1 << priv->resolution) - 1; - clock = STM32WL5_TIM_GETCLOCK(priv->tim); - period = STM32WL5_TIM_GETPERIOD(priv->tim); + clock = STM32_TIM_GETCLOCK(priv->tim); + period = STM32_TIM_GETPERIOD(priv->tim); if (clock == 1000000) { @@ -380,7 +380,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, /* Get the time remaining until the timer expires (in microseconds) */ clock_factor = (clock == 1000000)? 1: (clock / 1000000); - status->timeleft = (timeout - STM32WL5_TIM_GETCOUNTER(priv->tim)) * + status->timeleft = (timeout - STM32_TIM_GETCOUNTER(priv->tim)) * clock_factor; return OK; } @@ -417,13 +417,13 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, if (timeout > maxtimeout) { uint64_t freq = (maxtimeout * 1000000) / timeout; - STM32WL5_TIM_SETCLOCK(priv->tim, freq); - STM32WL5_TIM_SETPERIOD(priv->tim, maxtimeout); + STM32_TIM_SETCLOCK(priv->tim, freq); + STM32_TIM_SETPERIOD(priv->tim, maxtimeout); } else { - STM32WL5_TIM_SETCLOCK(priv->tim, 1000000); - STM32WL5_TIM_SETPERIOD(priv->tim, timeout); + STM32_TIM_SETCLOCK(priv->tim, 1000000); + STM32_TIM_SETPERIOD(priv->tim, timeout); } return OK; @@ -463,13 +463,13 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32WL5_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); - STM32WL5_TIM_ENABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_ENABLEINT(priv->tim, 0); } else { - STM32WL5_TIM_DISABLEINT(priv->tim, 0); - STM32WL5_TIM_SETISR(priv->tim, NULL, NULL, 0); + STM32_TIM_DISABLEINT(priv->tim, 0); + STM32_TIM_SETISR(priv->tim, NULL, NULL, 0); } leave_critical_section(flags); diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index c4238fbf268..070fbc8b745 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -62,9 +62,9 @@ #undef CONFIG_STM32WL5_SYSTICK_HCLKd8 #ifdef CONFIG_STM32WL5_SYSTICK_HCLKd8 -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else -# define SYSTICK_RELOAD ((STM32WL5_HCLK_FREQUENCY / CLK_TCK) - 1) +# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) #endif /* The size of the reload field is 24 bits. Verify that the reload value @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32WL5_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); /* Enable SysTick interrupts */ @@ -147,5 +147,5 @@ void up_timer_initialize(void) /* And enable the timer interrupt */ - up_enable_irq(STM32WL5_IRQ_SYSTICK); + up_enable_irq(STM32_IRQ_SYSTICK); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c index b8fa93730bf..311458d7adb 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.c @@ -44,7 +44,7 @@ #include "hardware/stm32wl5_memorymap.h" #include "stm32wl5_uid.h" -#ifdef STM32WL5_SYSMEM_UID +#ifdef STM32_SYSMEM_UID /**************************************************************************** * Public Functions @@ -56,8 +56,8 @@ void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) for (i = 0; i < 12; i++) { - uniqueid[i] = *((uint8_t *)(STM32WL5_SYSMEM_UID)+i); + uniqueid[i] = *((uint8_t *)(STM32_SYSMEM_UID)+i); } } -#endif /* STM32WL5_SYSMEM_UID */ +#endif /* STM32_SYSMEM_UID */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index 673b0232ecb..b00acf8b0d2 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -36,72 +36,72 @@ /* nucleo-wl55jc has installed 32Mhz HSE oscillator */ -#define STM32WL5_XTAL_FREQ 32000000ul +#define STM32_XTAL_FREQ 32000000ul /* Use the HSE */ -#define STM32WL5_BOARD_USEHSE 1 +#define STM32_BOARD_USEHSE 1 /* HSE source is a TCXO crystal which needs to be first powered on */ -#define STM32WL5_BOARD_USETCXO +#define STM32_BOARD_USETCXO /* Prescaler common to all PLL inputs */ -#define STM32WL5_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(2) /* 32MHz / 2 = 16MHz */ /* 'main' PLL config; we use this to generate our system clock */ /* disable unused pll clocks */ -#define STM32WL5_PLLCFG_PLLP 0 -#undef STM32WL5_PLLCFG_PLLP_ENABLED -#define STM32WL5_PLLCFG_PLLQ 0 -#undef STM32WL5_PLLCFG_PLLQ_ENABLED +#define STM32_PLLCFG_PLLP 0 +#undef STM32_PLLCFG_PLLP_ENABLED +#define STM32_PLLCFG_PLLQ 0 +#undef STM32_PLLCFG_PLLQ_ENABLED /* further multiplicate source for system clock */ -#define STM32WL5_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ -#define STM32WL5_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ -#define STM32WL5_PLLCFG_PLLR_ENABLED +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(6) /* 16MHz * 6 = 96MHz */ +#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2) /* 96MHz / 2 = 48MHz */ +#define STM32_PLLCFG_PLLR_ENABLED /* Resulting system clock is 48MHz */ -#define STM32WL5_SYSCLK_FREQUENCY 48000000ul +#define STM32_SYSCLK_FREQUENCY 48000000ul /* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ -#define STM32WL5_HCLK_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the HCLK3 divisor (for flash and sram2) */ -#define STM32WL5_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ -#define STM32WL5_HCLK3_FREQUENCY STM32WL5_SYSCLK_FREQUENCY +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK3 = SYSCLK / 1 */ +#define STM32_HCLK3_FREQUENCY STM32_SYSCLK_FREQUENCY /* Configure the APB1 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32WL5_PCLK1_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB1_TIM2_CLKIN (STM32WL5_PCLK1_FREQUENCY) +#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY) /* Configure the APB2 prescaler */ -#define STM32WL5_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ -#define STM32WL5_PCLK2_FREQUENCY (STM32WL5_HCLK_FREQUENCY / 1) +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1) /* The timer clock frequencies are automatically defined by hardware. * If the APB prescaler equals 1, the timer clock frequencies are set to the * same frequency as that of the APB domain. Otherwise they are set to twice. */ -#define STM32WL5_APB2_TIM1_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM16_CLKIN STM32WL5_PCLK2_FREQUENCY -#define STM32WL5_APB2_TIM17_CLKIN STM32WL5_PCLK2_FREQUENCY +#define STM32_APB2_TIM1_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM16_CLKIN STM32_PCLK2_FREQUENCY +#define STM32_APB2_TIM17_CLKIN STM32_PCLK2_FREQUENCY /* The timer clock frequencies are automatically defined by hardware. If the * APB prescaler equals 1, the timer clock frequencies are set to the same @@ -109,13 +109,13 @@ * Note: TIM1,15,16 are on APB2, others on APB1 */ -#define BOARD_TIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM16_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_TIM17_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM1_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM2_FREQUENCY STM32WL5_HCLK_FREQUENCY -#define BOARD_LPTIM3_FREQUENCY STM32WL5_HCLK_FREQUENCY +#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_TIM17_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY +#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index ec04c1555a6..16b17248230 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -91,7 +91,7 @@ # warning "There is unused space on flash" #endif -#define FLASH_PAGE_SIZE STM32WL5_FLASH_PAGESIZE +#define FLASH_PAGE_SIZE STM32_FLASH_PAGESIZE /**************************************************************************** * Private Definitions From a788e3d436fbcb1e6eb58985fbf723c1f1d041b8 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 14:46:55 +0200 Subject: [PATCH 056/268] !arch/stm32n6: unify non-standard hardware definition prefixes BREAKING CHANGE: STM32N6 non-standard hardware definition macros (IRQ, peripheral-count, SRAM and related) were renamed to the common STM32_* prefix. Out-of-tree code must update the affected references. Signed-off-by: raiden00pl --- arch/arm/include/stm32n6/chip.h | 6 +++--- arch/arm/src/stm32n6/stm32_gpio.c | 8 ++++---- arch/arm/src/stm32n6/stm32_gpio.h | 2 +- arch/arm/src/stm32n6/stm32_serial.c | 10 +++++----- 4 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/arm/include/stm32n6/chip.h b/arch/arm/include/stm32n6/chip.h index 72f643ba3b6..9c50b19c7c7 100644 --- a/arch/arm/include/stm32n6/chip.h +++ b/arch/arm/include/stm32n6/chip.h @@ -52,10 +52,10 @@ * Each bank requires its RCC MEMENR clock enable bit to be set. */ -#define STM32N6_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ +#define STM32_SRAM_SIZE (4 * 1024 * 1024) /* 4194304 bytes (4 MiB) */ -#define STM32N6_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ -#define STM32N6_NUSART (1) /* USART1 */ +#define STM32_NPORTS (12) /* GPIO ports A-H (8) + N, O, P, Q (4) */ +#define STM32_NUSART (1) /* USART1 */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/src/stm32n6/stm32_gpio.c b/arch/arm/src/stm32n6/stm32_gpio.c index 41275453032..c22839ad781 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.c +++ b/arch/arm/src/stm32n6/stm32_gpio.c @@ -55,7 +55,7 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED; * 8-11). Note that there is no GPIOI-M on this chip. */ -const uint32_t g_gpiobase[STM32N6_NPORTS] = +const uint32_t g_gpiobase[STM32_NPORTS] = { STM32_GPIOA_BASE, /* Port A - index 0 */ STM32_GPIOB_BASE, /* Port B - index 1 */ @@ -110,7 +110,7 @@ int stm32_configgpio(uint32_t cfgset) /* Verify that this hardware supports the select GPIO port */ port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port >= STM32N6_NPORTS) + if (port >= STM32_NPORTS) { return -EINVAL; } @@ -318,7 +318,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ @@ -358,7 +358,7 @@ bool stm32_gpioread(uint32_t pinset) unsigned int pin; port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; - if (port < STM32N6_NPORTS) + if (port < STM32_NPORTS) { /* Get the port base address */ diff --git a/arch/arm/src/stm32n6/stm32_gpio.h b/arch/arm/src/stm32n6/stm32_gpio.h index 4c32f43d43c..64ad271b3f1 100644 --- a/arch/arm/src/stm32n6/stm32_gpio.h +++ b/arch/arm/src/stm32n6/stm32_gpio.h @@ -243,7 +243,7 @@ extern "C" /* Base addresses for each GPIO block */ -EXTERN const uint32_t g_gpiobase[STM32N6_NPORTS]; +EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; /**************************************************************************** * Public Function Prototypes diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 220a34dc3ac..75dc8c8c857 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -274,7 +274,7 @@ static struct stm32_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ static struct stm32_serial_s * const - g_uart_devs[STM32N6_NUSART] = + g_uart_devs[STM32_NUSART] = { #ifdef CONFIG_STM32N6_USART1_SERIALDRIVER [0] = &g_usart1priv, @@ -639,7 +639,7 @@ static void stm32serial_pm_setsuspend(bool suspend) g_serialpm.serial_suspended = suspend; - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1559,7 +1559,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - for (n = 0; n < STM32N6_NUSART; n++) + for (n = 0; n < STM32_NUSART; n++) { struct stm32_serial_s *priv = g_uart_devs[n]; @@ -1629,7 +1629,7 @@ void arm_earlyserialinit(void) /* Disable all USART interrupts */ - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { if (g_uart_devs[i]) { @@ -1694,7 +1694,7 @@ void arm_serialinit(void) strlcpy(devname, "/dev/ttySx", sizeof(devname)); - for (i = 0; i < STM32N6_NUSART; i++) + for (i = 0; i < STM32_NUSART; i++) { /* Don't create a device for non-configured ports. */ From f6bb93c3795eec898d86b64adb60c62ecdfa7399 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 19:19:52 +0800 Subject: [PATCH 057/268] Documentation/applications/system/conntrack: add conntrack man page Add documentation for the conntrack command including usage, options, output format, and examples for listing and monitoring connection tracking entries. Signed-off-by: hanzhijian --- .../applications/system/conntrack/index.rst | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/applications/system/conntrack/index.rst diff --git a/Documentation/applications/system/conntrack/index.rst b/Documentation/applications/system/conntrack/index.rst new file mode 100644 index 00000000000..5d1511d826c --- /dev/null +++ b/Documentation/applications/system/conntrack/index.rst @@ -0,0 +1,107 @@ +============================ +``conntrack`` connection tracking +============================ + +The ``conntrack`` command is used to list and monitor connection tracking +entries in the NuttX kernel, similar to the Linux conntrack tool. It +communicates with the kernel via Netlink (``NETLINK_NETFILTER``). + +Configuration +============= + +- ``CONFIG_SYSTEM_CONNTRACK`` +- ``CONFIG_NETLINK_NETFILTER`` + +The following additional options are available: + +- ``CONFIG_SYSTEM_CONNTRACK_PRIORITY`` - Task priority + (default: 100) +- ``CONFIG_SYSTEM_CONNTRACK_STACKSIZE`` - Stack size + (default: ``DEFAULT_TASK_STACKSIZE``) + +Usage +===== + +.. code-block:: text + + conntrack -L [-f family] + conntrack -E + +Options +======= + +``-L, --dump`` + List all connection tracking entries. For each entry, the protocol, + original tuple (source, destination, ports), and reply tuple are + displayed. + +``-E, --event`` + Display a real-time event log of connection tracking changes. New + connections are shown with ``[NEW]`` and destroyed connections with + ``[DESTROY]``. Press Ctrl+C to stop monitoring. + +``-f, --family PROTO`` + Specify the L3 protocol family for the ``-L`` (dump) option. Valid + values are ``ipv4`` (default) and ``ipv6``. This option is only + valid with ``-L``. + +Output Format +============= + +Each connection tracking entry is displayed in the following format: + +.. code-block:: text + + proto orig reply + +Where: + +- ``proto``: Protocol name (``tcp``, ``udp``, ``icmp``, or ``icmp6``) +- ``orig``: Original direction tuple (``src=``, ``dst=``, ``sport=``/``type=``, + ``dport=``/``code=``/``id=``) +- ``reply``: Reply direction tuple (same format as orig) + +For TCP/UDP entries, the port numbers are shown. For ICMP/ICMPv6 entries, +the type, code, and id are shown instead. + +Examples +======== + +List all IPv4 connection tracking entries: + +.. code-block:: text + + nsh> conntrack -L + +List all IPv6 connection tracking entries: + +.. code-block:: text + + nsh> conntrack -L -f ipv6 + +Monitor connection tracking events in real-time: + +.. code-block:: text + + nsh> conntrack -E + +Sample output for ``conntrack -L``: + +.. code-block:: text + + tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 + udp src=10.0.0.1 dst=10.0.0.2 sport=54321 dport=53 src=10.0.0.2 dst=10.0.0.1 sport=53 dport=54321 + conntrack: 2 flow entries have been shown. + +Sample output for ``conntrack -E``: + +.. code-block:: text + + [NEW] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 + [DESTROY] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 + +See Also +======== + +- :doc:`../iptables/index` +- :doc:`../ip6tables/index` From d866153a25f1eca36c2403e7fbc64ea8e3224ad5 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Wed, 10 Jun 2026 23:21:27 +0800 Subject: [PATCH 058/268] Documentation/applications/system/conntrack: add conntrack man page Add comprehensive documentation for the conntrack command including dump and event monitoring options. Signed-off-by: hanzhijian --- .../applications/system/conntrack/index.rst | 75 ++++++++----------- 1 file changed, 33 insertions(+), 42 deletions(-) diff --git a/Documentation/applications/system/conntrack/index.rst b/Documentation/applications/system/conntrack/index.rst index 5d1511d826c..8e125370321 100644 --- a/Documentation/applications/system/conntrack/index.rst +++ b/Documentation/applications/system/conntrack/index.rst @@ -1,10 +1,9 @@ -============================ -``conntrack`` connection tracking -============================ +============================== +``conntrack`` connection track +============================== -The ``conntrack`` command is used to list and monitor connection tracking -entries in the NuttX kernel, similar to the Linux conntrack tool. It -communicates with the kernel via Netlink (``NETLINK_NETFILTER``). +The ``conntrack`` command is used to display and monitor connection tracking +entries in the NuttX kernel. It is similar to Linux's ``conntrack`` tool. Configuration ============= @@ -27,23 +26,26 @@ Usage conntrack -L [-f family] conntrack -E +Commands +======== + +``-L, --dump`` + List all connection tracking entries. + +``-E, --event`` + Display a real-time event log of connection tracking changes. + Press Ctrl+C to stop monitoring. + Options ======= -``-L, --dump`` - List all connection tracking entries. For each entry, the protocol, - original tuple (source, destination, ports), and reply tuple are - displayed. - -``-E, --event`` - Display a real-time event log of connection tracking changes. New - connections are shown with ``[NEW]`` and destroyed connections with - ``[DESTROY]``. Press Ctrl+C to stop monitoring. - ``-f, --family PROTO`` - Specify the L3 protocol family for the ``-L`` (dump) option. Valid - values are ``ipv4`` (default) and ``ipv6``. This option is only - valid with ``-L``. + Specify the L3 protocol family. Only valid with ``-L``. + + Supported values: + + - ``ipv4`` (default): Show IPv4 connection tracking entries. + - ``ipv6``: Show IPv6 connection tracking entries. Output Format ============= @@ -52,17 +54,19 @@ Each connection tracking entry is displayed in the following format: .. code-block:: text - proto orig reply + PROTO src=SRC_ADDR dst=DST_ADDR sport=SPORT dport=DPORT src=REPLY_SRC dst=REPLY_DST sport=REPLY_SPORT dport=REPLY_DPORT -Where: +For ICMP/ICMPv6 entries, the format uses ``type``, ``code``, and ``id`` +instead of ``sport`` and ``dport``: -- ``proto``: Protocol name (``tcp``, ``udp``, ``icmp``, or ``icmp6``) -- ``orig``: Original direction tuple (``src=``, ``dst=``, ``sport=``/``type=``, - ``dport=``/``code=``/``id=``) -- ``reply``: Reply direction tuple (same format as orig) +.. code-block:: text -For TCP/UDP entries, the port numbers are shown. For ICMP/ICMPv6 entries, -the type, code, and id are shown instead. + icmp src=SRC_ADDR dst=DST_ADDR type=TYPE code=CODE id=ID src=REPLY_SRC dst=REPLY_DST type=REPLY_TYPE code=REPLY_CODE id=REPLY_ID + +Event mode prefixes each entry with an event type: + +- ``[NEW]``: A new connection tracking entry was created. +- ``[DESTROY]``: A connection tracking entry was removed. Examples ======== @@ -84,21 +88,8 @@ Monitor connection tracking events in real-time: .. code-block:: text nsh> conntrack -E - -Sample output for ``conntrack -L``: - -.. code-block:: text - - tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 - udp src=10.0.0.1 dst=10.0.0.2 sport=54321 dport=53 src=10.0.0.2 dst=10.0.0.1 sport=53 dport=54321 - conntrack: 2 flow entries have been shown. - -Sample output for ``conntrack -E``: - -.. code-block:: text - - [NEW] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 - [DESTROY] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 + [NEW] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 + [DESTROY] tcp src=10.0.0.1 dst=10.0.0.2 sport=12345 dport=80 src=10.0.0.2 dst=10.0.0.1 sport=80 dport=12345 See Also ======== From ce0e715254f906ba334374bc15cd7f3a8a267cc5 Mon Sep 17 00:00:00 2001 From: Kerogit Date: Wed, 3 Jun 2026 01:50:53 +0200 Subject: [PATCH 059/268] boards/avr/avrdx/breadxavr: provide board_late_initialize This patch amends commit f077c0321de which is a part of series that changed (in commit 48db502daf9) default value of BOARD_LATE_INITIALIZE to yes. With this change, the boards are required to provide board_late_initialize function. Commit f077c0321de added this function to many AVR boards but not to this one, making the build with default configuration fail. This patch rectifies that and provides an empty function. With this patch applied, the build no longer fails. Signed-off-by: Kerogit --- boards/avr/avrdx/breadxavr/src/Makefile | 6 +---- boards/avr/avrdx/breadxavr/src/avrdx_init.c | 29 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 5 deletions(-) diff --git a/boards/avr/avrdx/breadxavr/src/Makefile b/boards/avr/avrdx/breadxavr/src/Makefile index f5ef01580aa..da62b5457ca 100644 --- a/boards/avr/avrdx/breadxavr/src/Makefile +++ b/boards/avr/avrdx/breadxavr/src/Makefile @@ -22,16 +22,12 @@ include $(TOPDIR)/Make.defs -CSRCS = avrdx_boot.c +CSRCS = avrdx_boot.c avrdx_init.c ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += avr_leds.c endif -ifeq ($(CONFIG_BOARD_EARLY_INITIALIZE),y) -CSRCS += avrdx_init.c -endif - ifeq ($(CONFIG_BREADXAVR_BUTTONS_DRIVER),y) CSRCS += avrdx_buttons.c endif diff --git a/boards/avr/avrdx/breadxavr/src/avrdx_init.c b/boards/avr/avrdx/breadxavr/src/avrdx_init.c index 6e09599e38f..096c1f9730b 100644 --- a/boards/avr/avrdx/breadxavr/src/avrdx_init.c +++ b/boards/avr/avrdx/breadxavr/src/avrdx_init.c @@ -89,3 +89,32 @@ void board_early_initialize(void) } #endif /* CONFIG_BOARD_EARLY_INITIALIZE */ + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * Excerpt from Kconfig: + * + * If CONFIG_BOARD_LATE_INITIALIZE is set, board_late_initialize() is + * called after up_initialize() just before the main application is + * started. It can be used to initialize more complex, board-specific + * device drivers. + * + * Function runs on a temporary, internal kernel thread and can therefore + * wait for events. + * + * Currently, the board has no need for this function but the Kconfig + * option is enabled by default so the function either needs to be defined, + * or default configuration needs to be changed. This is why this function + * exists but is empty. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE + +void board_late_initialize(void) +{ +} + +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ From a7352902aeaf9775dec2aa541ab8273d3abd2b44 Mon Sep 17 00:00:00 2001 From: Kerogit Date: Thu, 19 Feb 2026 12:15:16 +0100 Subject: [PATCH 060/268] arch/avr/src/avrdx: fix Make.defs when CONFIG_ENABLE_ALL_SIGNALS unset This patch amends commit dfd3426aa59 which added support for running with some signals disabled to AVR architecture. AVR DA/DB architecture was not covered by the commit and failed to build with CONFIG_ENABLE_ALL_SIGNALS unset (which includes building with CONFIG_ENABLE_PARTIAL_SIGNALS, the default value.) Change is replicated from the commit and tested by a custom stress application which spawns some always-busy threads and uses preemptive multitasking to switch between them. Additionally, ability to sleep in the application was tested by a simple LED blinking application. Signed-off-by: Kerogit --- arch/avr/src/avrdx/Make.defs | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/avr/src/avrdx/Make.defs b/arch/avr/src/avrdx/Make.defs index 1b92a37994b..4978f92b3a4 100644 --- a/arch/avr/src/avrdx/Make.defs +++ b/arch/avr/src/avrdx/Make.defs @@ -31,11 +31,15 @@ CMN_CSRCS = avr_allocateheap.c avr_copystate.c avr_createstack.c CMN_CSRCS += avr_doirq.c avr_exit.c avr_idle.c avr_initialize.c CMN_CSRCS += avr_initialstate.c avr_irq.c avr_lowputs.c CMN_CSRCS += avr_nputs.c avr_releasestack.c avr_registerdump.c -CMN_CSRCS += avr_schedulesigaction.c avr_sigdeliver.c avr_getintstack.c +CMN_CSRCS += avr_getintstack.c CMN_CSRCS += avr_stackframe.c avr_switchcontext.c avr_usestack.c # Configuration-dependent common files +ifeq ($(CONFIG_ENABLE_ALL_SIGNALS),y) +CMN_CSRCS += avr_schedulesigaction.c avr_sigdeliver.c +endif + ifeq ($(CONFIG_AVR_SPI),y) CMN_CSRCS += avr_spi.c endif From 689ed188c617a124b8f53baf102d521bcc9ac438 Mon Sep 17 00:00:00 2001 From: Kerogit Date: Thu, 5 Mar 2026 08:52:22 +0100 Subject: [PATCH 061/268] sched/clock/clock_delay: added config flag to remove weak up_udelay While attempting to create architecture-specific implementation of up_udelay, it was discovered that the overriding function is not included in the final binary, the weak implementation was used instead. Further investigation and experimentation showed that the linker only overrides the weak implementation with the custom one if the custom one is present in a .c source file that contains at least one other function that is called from somewhere. Some additional testing revealed that at least one other already present up_udelay override (rv32m1-vega:nsh) is affected by this. In a short mailing list discussion it was determined that this is a likely result of using static libraries during the build process and it was suggested to introduce configuration option that will exclude weak implementations of the function from the build altogether. This patch does that. This patch does not enable this configuration option for any existing board/chip because doing so would change its behaviour and needs to be tested by users of the hardware. Also changed is the static assertion in sched/clock/clock_delay.c to not prevent building the code when architecture declares that it does not use BOARD_LOOPSPERMSEC to determine required loop count. BOARD_LOOPSPERMSEC is made undefined in such case. Patch was tested by building breadxavr:nsh (identical binary by SHA256), rv32m1-vega:nsh (identical text section) and rv-virt:nsh (text section differs because of different ordering of functions in the binary, ostest passed though.) Signed-off-by: Kerogit --- arch/Kconfig | 31 ++++++++++++++++++++++++++ drivers/timers/arch_alarm.c | 16 ++++++++++++++ drivers/timers/arch_timer.c | 42 ++++++++++++++++++++++++++++++------ sched/clock/clock_delay.c | 43 ++++++++++++++++++++++++++++++++++--- 4 files changed, 122 insertions(+), 10 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index 7cd6ec4f10d..0085b50d1ad 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -560,6 +560,36 @@ config ARCH_LDST_16BIT_NOT_ATOMIC (The same applies for non-interrupt context write and interrupt context read.) +config ARCH_HAVE_UDELAY + bool + default n + ---help--- + This configuration option is set for architectures that define + their own version of up_udelay. That function is defined as weak + but due to linker behaviour with regards to static libraries, + it was found that the overriding definition is not included + in the resulting binary, the default (weak) one is still used. + + (Found with GCC 14.2 on AVR and Risc-V but likely present + elsewhere too. Manifests when up_udelay override is the only + function in the source file.) + + If set, the default up_udelay function is excluded from build. + +config ARCH_HAVE_DYNAMIC_UDELAY + bool + default n + depends on ARCH_HAVE_UDELAY + ---help--- + This configuration option is set if architecture-specific up_udelay + function does not use CONFIG_BOARD_LOOPSPERMSEC. This should be used + for architectures/boards where the user has the option to choose + clock frequency of the CPU. + + (Keep in mind that up_udelay function may also be used in situations + after a failure - the implementation should always re-read current + hardware settings as anything stored in memory may be corrupted.) + config ARCH_HAVE_TESTSET bool default n @@ -1366,6 +1396,7 @@ comment "Board Settings" config BOARD_LOOPSPERMSEC int "Delay loops per millisecond" + depends on !ARCH_HAVE_DYNAMIC_UDELAY default -1 ---help--- Simple delay loops are used by some logic, especially during boot-up, diff --git a/drivers/timers/arch_alarm.c b/drivers/timers/arch_alarm.c index 557a326f36e..b8eb29bf8af 100644 --- a/drivers/timers/arch_alarm.c +++ b/drivers/timers/arch_alarm.c @@ -39,8 +39,16 @@ /* If no value is given, we proceed with 0 since a one-shot timer is used for * accurate delays. A runtime DEBUGASSERT catches the case where the one-shot * timer lower-half isn't registered in time. + * + * If ARCH_HAVE_DYNAMIC_UDELAY is set, BOARD_LOOPSPERMSEC is unset. + * Considering the above, it should not be used. Set a default value of -1, + * turning this case into an already handled one. */ +#ifndef CONFIG_BOARD_LOOPSPERMSEC +# define CONFIG_BOARD_LOOPSPERMSEC -1 +#endif + #if CONFIG_BOARD_LOOPSPERMSEC == -1 # undef CONFIG_BOARD_LOOPSPERMSEC # define CONFIG_BOARD_LOOPSPERMSEC 0 @@ -181,13 +189,21 @@ void weak_function up_mdelay(unsigned int milliseconds) * Delay inline for the requested number of microseconds. * WARNING: NOT multi-tasking friendly * + * This function is both compiled optionally based on ARCH_HAVE_UDELAY + * and declared with weak attribute. See comment of up_udelay + * implementation in sched/clock/clock_delay.c for explanation. + * ****************************************************************************/ +#ifndef CONFIG_ARCH_HAVE_UDELAY + void weak_function up_udelay(useconds_t microseconds) { up_ndelay(NSEC_PER_USEC * microseconds); } +#endif + /**************************************************************************** * Name: up_ndelay * diff --git a/drivers/timers/arch_timer.c b/drivers/timers/arch_timer.c index c0cb09fd9d6..5e3b0f988cd 100644 --- a/drivers/timers/arch_timer.c +++ b/drivers/timers/arch_timer.c @@ -39,16 +39,22 @@ /* If no value is given, we proceed with 0 since a timer is used for accurate * delays. A runtime DEBUGASSERT catches the case where the timer lower-half * isn't registered in time. + * + * Value is unset if ARCH_HAVE_DYNAMIC_UDELAY is set. In that case, + * ARCH_HAVE_UDELAY is also set and the only user of these values + * (udelay_coarse) is excluded from the build. */ -#if CONFIG_BOARD_LOOPSPERMSEC == -1 -# undef CONFIG_BOARD_LOOPSPERMSEC -# define CONFIG_BOARD_LOOPSPERMSEC 0 -#endif +#ifndef CONFIG_ARCH_HAVE_UDELAY +# if CONFIG_BOARD_LOOPSPERMSEC == -1 +# undef CONFIG_BOARD_LOOPSPERMSEC +# define CONFIG_BOARD_LOOPSPERMSEC 0 +# endif -#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) -#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) -#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) +# define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +# define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +# define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) +#endif /**************************************************************************** * Private Types @@ -127,6 +133,18 @@ static void udelay_accurate(useconds_t microseconds) } } +#ifndef CONFIG_ARCH_HAVE_UDELAY + +/**************************************************************************** + * Name: udelay_coarse + * + * Description: + * Wait loop called (only) by up_udelay if udelay_accurate + * is not available. (Excluded from the build if up_udelay is also + * excluded from the build.) + * + ****************************************************************************/ + static void udelay_coarse(useconds_t microseconds) { volatile int i; @@ -176,6 +194,8 @@ static void udelay_coarse(useconds_t microseconds) } } +#endif /* ifndef CONFIG_ARCH_HAVE_UDELAY */ + static bool timer_callback(FAR uint32_t *next_interval, FAR void *arg) { #ifdef CONFIG_SCHED_TICKLESS @@ -464,8 +484,14 @@ void weak_function up_mdelay(unsigned int milliseconds) * * *** NOT multi-tasking friendly *** * + * This function is both compiled optionally based on ARCH_HAVE_UDELAY + * and declared with weak attribute. See comment of up_udelay + * implementation in sched/clock/clock_delay.c for explanation. + * ****************************************************************************/ +#ifndef CONFIG_ARCH_HAVE_UDELAY + void weak_function up_udelay(useconds_t microseconds) { if (g_timer.lower != NULL) @@ -478,6 +504,8 @@ void weak_function up_udelay(useconds_t microseconds) } } +#endif + /**************************************************************************** * Name: up_ndelay * diff --git a/sched/clock/clock_delay.c b/sched/clock/clock_delay.c index cf3e2f0c902..f217477505a 100644 --- a/sched/clock/clock_delay.c +++ b/sched/clock/clock_delay.c @@ -67,17 +67,27 @@ "new value to apache/nuttx." #endif +#ifndef CONFIG_ARCH_HAVE_DYNAMIC_UDELAY static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, "Configure BOARD_LOOPSPERMSEC to non-default value."); -#define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) -#define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) -#define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) +/* If ARCH_HAVE_DYNAMIC_UDELAY is set, BOARD_LOOPSPERMSEC is unset, + * calculate these optionally. (Only used in udelay_coarse and + * that function is excluded from the build if these end up undefined.) + */ + +# define CONFIG_BOARD_LOOPSPER100USEC ((CONFIG_BOARD_LOOPSPERMSEC+5)/10) +# define CONFIG_BOARD_LOOPSPER10USEC ((CONFIG_BOARD_LOOPSPERMSEC+50)/100) +# define CONFIG_BOARD_LOOPSPERUSEC ((CONFIG_BOARD_LOOPSPERMSEC+500)/1000) + +#endif /**************************************************************************** * Private Functions ****************************************************************************/ +#ifndef CONFIG_ARCH_HAVE_UDELAY + static void udelay_coarse(useconds_t microseconds) { volatile int i; @@ -125,6 +135,8 @@ static void udelay_coarse(useconds_t microseconds) } } +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -151,13 +163,38 @@ void weak_function up_mdelay(unsigned int milliseconds) * * *** NOT multi-tasking friendly *** * + * Note that this method is both marked weak and compiled optionally + * based on ARCH_HAVE_UDELAY option. This is redundant but kept + * as a temporary measure. + * + * It was discovered that sometimes the weak attribute is not enough + * to have the method replaced with other, non-weak implementation. + * (Described in more detail in help text for the ARCH_HAVE_UDELAY + * Kconfig option.) The ARCH_HAVE_UDELAY option is meant to remedy + * this but the author of the change does not own all the hardware + * that implements its own up_udelay and is affected by this problem. + * + * Enabling ARCH_HAVE_UDELAY for every such chip is therefore impossible, + * the change would be untested. Instead, the weak attribute is kept, + * preserving previous behaviour of current code. If, at some future + * time, the change is tested for other chips that implement up_udelay, + * the weak attribute and this comment can be removed. + * + * The same also applies to up_udelay implementations + * in drivers/timers/arch_alarm.c and drivers/timers/arch_timer.c + * and this comment is referenced there. + * ****************************************************************************/ +#ifndef CONFIG_ARCH_HAVE_UDELAY + void weak_function up_udelay(useconds_t microseconds) { udelay_coarse(microseconds); } +#endif + /**************************************************************************** * Name: up_ndelay * From 10dea61e2320b0b1ddfb3ea386de1be205e71994 Mon Sep 17 00:00:00 2001 From: Kerogit Date: Thu, 5 Mar 2026 11:04:36 +0100 Subject: [PATCH 062/268] arch/avr/src/avrdx: add support for reading CPU clock from other sources This patch adds support for reading CPU clock frequency when the MCU is driven by clock source other than high frequency oscillator. Signed-off-by: Kerogit --- arch/avr/src/avrdx/avrdx.h | 24 +++++- arch/avr/src/avrdx/avrdx_peripherals.c | 111 ++++++++++++++++++++----- arch/avr/src/avrdx/iodefs/avr128da28.h | 10 +++ arch/avr/src/avrdx/iodefs/avr128da64.h | 10 +++ arch/avr/src/avrdx/iodefs/avr128db64.h | 10 +++ 5 files changed, 143 insertions(+), 22 deletions(-) diff --git a/arch/avr/src/avrdx/avrdx.h b/arch/avr/src/avrdx/avrdx.h index 84efae45da9..88a2c413454 100644 --- a/arch/avr/src/avrdx/avrdx.h +++ b/arch/avr/src/avrdx/avrdx.h @@ -94,15 +94,33 @@ void up_clkinitialize(void); * Name: avrdx_current_freq_per * * Description: - * Calculate and return current f_per + * Calculate and return current f_per (peripheral clock frequency) * - * Assumptions: - * Main clock source is internal oscillator + * Returned Value: frequency in Hz. + * + * Assumptions/Limitations: + * Main clock must not be driven by external clock. * ****************************************************************************/ uint32_t avrdx_current_freq_per(void); +/**************************************************************************** + * Name: avrdx_current_freq_cpu + * + * Description: + * Calculate and return current f_cpu (CPU frequency). Returns value + * of avrdx_current_freq_per because both clocks are identical. + * + * Returned Value: frequency in Hz + * + * Assumptions/Limitations: + * Main clock must not be driven by external clock. + * + ****************************************************************************/ + +uint32_t avrdx_current_freq_cpu(void); + /**************************************************************************** * Name: up_consoleinit * diff --git a/arch/avr/src/avrdx/avrdx_peripherals.c b/arch/avr/src/avrdx/avrdx_peripherals.c index a7442280f39..7de37e38fd6 100644 --- a/arch/avr/src/avrdx/avrdx_peripherals.c +++ b/arch/avr/src/avrdx/avrdx_peripherals.c @@ -301,11 +301,36 @@ const IOBJ uint8_t avrdx_usart_portmux_masks[] = ****************************************************************************/ /**************************************************************************** - * Public Functions - ****************************************************************************/ + * Name: avrdx_current_freq_main_prescaler + * + * Description: + * Reduces given frequency by main clock prescaler. + * + * Input Parameters: + * frequency - input frequency + * + * Return value: output frequency in Hz + */ + +uint32_t avrdx_current_freq_main_prescaler(uint32_t frequency) +{ + uint8_t mclkctrlb; + uint8_t pdiv; + + /* Read this once, no point in re-reading */ + + mclkctrlb = CLKCTRL.MCLKCTRLB; + if (mclkctrlb & CLKCTRL_PEN_bm) + { + pdiv = (mclkctrlb & CLKCTRL_PDIV_GM) >> CLKCTRL_PDIV_GP; + frequency /= avrdx_main_pdiv[pdiv]; + } + + return frequency; +} /**************************************************************************** - * Name: avrdx_current_freq_per + * Name: avrdx_current_freq_per_oschf * * Description: * Calculate and return current f_per (peripheral clock frequency) @@ -315,15 +340,13 @@ const IOBJ uint8_t avrdx_usart_portmux_masks[] = * ****************************************************************************/ -uint32_t avrdx_current_freq_per() +uint32_t avrdx_current_freq_per_oschf(void) { uint32_t f_per; /* Shortcut variables */ uint8_t frqsel; - uint8_t pdiv; - uint8_t mclkctrlb; /* Calculate frequency in MHz, then divide it by main prescaler, * if set. @@ -332,23 +355,73 @@ uint32_t avrdx_current_freq_per() frqsel = (CLKCTRL.OSCHFCTRLA & CLKCTRL_FRQSEL_GM) >> CLKCTRL_FRQSEL_GP; f_per = 1000000UL * avrdx_frqsel_mhz[frqsel]; - /* Read this once, no point in re-reading */ + return avrdx_current_freq_main_prescaler(f_per); +} - mclkctrlb = CLKCTRL.MCLKCTRLB; - if (mclkctrlb & CLKCTRL_PEN_bm) +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: avrdx_current_freq_per + * + * Description: + * Calculate and return current f_per (peripheral clock frequency) + * + * Returned Value: frequency in Hz. + * + * Assumptions/Limitations: + * Main clock must not be driven by external clock. + * + ****************************************************************************/ + +uint32_t avrdx_current_freq_per(void) +{ + uint8_t mclkctrla; + + mclkctrla = CLKCTRL.MCLKCTRLA & CLKCTRL_CLKSEL_GM; + + /* Using if - else to deal with the most likely case first */ + + if (mclkctrla == CLKCTRL_CLKSEL_OSCHF_GC) { - pdiv = (mclkctrlb & CLKCTRL_PDIV_GM) >> CLKCTRL_PDIV_GP; - f_per /= avrdx_main_pdiv[pdiv]; + /* Internal high frequency oscillator */ + + return avrdx_current_freq_per_oschf(); + } + else if ((mclkctrla == CLKCTRL_CLKSEL_OSC32K_GC) || \ + (mclkctrla == CLKCTRL_CLKSEL_XOSC32K_GC)) + { + /* 32768 oscillator or external oscillator/crystal. + * Only apply the prescaler. + */ + + return avrdx_current_freq_main_prescaler(32768); } - /* Currently, rest of the code only supports internal oscillator - * and its frequency is pre-set using Kconfig. Nevertheless, that - * can change at some point and this function accounts for some - * of that. - * - * It doesn't account for the chip being clocked by external source - * though, that's to be done. + /* External clock. This is not supported and we can not determine + * the frequency. This will likely cause a failure (unless the caller + * has this case handled using other means.) */ - return f_per; + return 0; +} + +/**************************************************************************** + * Name: avrdx_current_freq_cpu + * + * Description: + * Calculate and return current f_cpu (CPU frequency). Returns value + * of avrdx_current_freq_per because both clocks are identical. + * + * Returned Value: frequency in Hz + * + * Assumptions/Limitations: + * Main clock must not be driven by external clock. + * + ****************************************************************************/ + +uint32_t avrdx_current_freq_cpu(void) +{ + return avrdx_current_freq_per(); } diff --git a/arch/avr/src/avrdx/iodefs/avr128da28.h b/arch/avr/src/avrdx/iodefs/avr128da28.h index 6dbc143bc35..abb16bcd5ce 100644 --- a/arch/avr/src/avrdx/iodefs/avr128da28.h +++ b/arch/avr/src/avrdx/iodefs/avr128da28.h @@ -64,6 +64,16 @@ #define PORT_ISC_BOTHEDGES_GC ( PORT_ISC_0_bm ) +/* CLKCTRL.MCLKCTRLA */ + +#define CLKCTRL_CLKSEL_GM ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm | \ + CLKCTRL_CLKSEL_2_bm ) + +#define CLKCTRL_CLKSEL_OSCHF_GC (0) +#define CLKCTRL_CLKSEL_OSC32K_GC ( CLKCTRL_CLKSEL_0_bm ) +#define CLKCTRL_CLKSEL_XOSC32K_GC ( CLKCTRL_CLKSEL_1_bm ) +#define CLKCTRL_CLKSEL_EXTCLK_GC ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm ) + /* CLKCTRL.MCLKCTRLB */ #define CLKCTRL_PDIV_GM ( CLKCTRL_PDIV_0_bm | CLKCTRL_PDIV_1_bm | \ diff --git a/arch/avr/src/avrdx/iodefs/avr128da64.h b/arch/avr/src/avrdx/iodefs/avr128da64.h index f00fef5bbce..8ce2e251e07 100644 --- a/arch/avr/src/avrdx/iodefs/avr128da64.h +++ b/arch/avr/src/avrdx/iodefs/avr128da64.h @@ -89,6 +89,16 @@ #define PORT_ISC_BOTHEDGES_GC ( PORT_ISC_0_bm ) +/* CLKCTRL.MCLKCTRLA */ + +#define CLKCTRL_CLKSEL_gm ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm | \ + CLKCTRL_CLKSEL_2_bm ) + +#define CLKCTRL_CLKSEL_OSCHF_GC (0) +#define CLKCTRL_CLKSEL_OSC32K_GC ( CLKCTRL_CLKSEL_0_bm ) +#define CLKCTRL_CLKSEL_XOSC32K_GC ( CLKCTRL_CLKSEL_1_bm ) +#define CLKCTRL_CLKSEL_EXTCLK_GC ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm ) + /* CLKCTRL.MCLKCTRLB */ #define CLKCTRL_PDIV_GM ( CLKCTRL_PDIV_0_bm | CLKCTRL_PDIV_1_bm | \ diff --git a/arch/avr/src/avrdx/iodefs/avr128db64.h b/arch/avr/src/avrdx/iodefs/avr128db64.h index 6bd0456f6ca..7fa48d80050 100644 --- a/arch/avr/src/avrdx/iodefs/avr128db64.h +++ b/arch/avr/src/avrdx/iodefs/avr128db64.h @@ -89,6 +89,16 @@ #define PORT_ISC_BOTHEDGES_GC ( PORT_ISC_0_bm ) +/* CLKCTRL.MCLKCTRLA */ + +#define CLKCTRL_CLKSEL_gm ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm | \ + CLKCTRL_CLKSEL_2_bm ) + +#define CLKCTRL_CLKSEL_OSCHF_GC (0) +#define CLKCTRL_CLKSEL_OSC32K_GC ( CLKCTRL_CLKSEL_0_bm ) +#define CLKCTRL_CLKSEL_XOSC32K_GC ( CLKCTRL_CLKSEL_1_bm ) +#define CLKCTRL_CLKSEL_EXTCLK_GC ( CLKCTRL_CLKSEL_0_bm | CLKCTRL_CLKSEL_1_bm ) + /* CLKCTRL.MCLKCTRLB */ #define CLKCTRL_PDIV_GM ( CLKCTRL_PDIV_0_bm | CLKCTRL_PDIV_1_bm | \ From 0b5bf6c2c59579b83d0e93356b1977620f227170 Mon Sep 17 00:00:00 2001 From: Kerogit Date: Thu, 5 Mar 2026 17:43:39 +0100 Subject: [PATCH 063/268] arch/avr/src/avrdx/avrdx_delay: add custom up_udelay function NuttX builtin up_udelay function uses BOARD_LOOPSPERMSEC configuration value to determine how many loops need to be done to cause requested delay. This does not match well with AVR DA/DB microcontrollers because the CPU clock frequency is configurable. A board configuration could therefore provide BOARD_LOOPSPERMSEC valid for one frequency but for other frequencies, the user would be required to calibrate the value and would still get incorrect result when changing the clock speed during runtime. This patch therefore implements dynamic architecture-specific up_udelay function which determines current clock settings and infers required loop count from that. New function was tested by simple application that used up_udelay to put delays between printf calls. Signed-off-by: Kerogit --- .../platforms/avr/avrdx/docs/up_udelay.rst | 69 ++++ Documentation/platforms/avr/avrdx/index.rst | 3 + Documentation/reference/os/sleep.rst | 3 +- arch/avr/src/avrdx/Kconfig | 61 ++- arch/avr/src/avrdx/Make.defs | 2 + arch/avr/src/avrdx/avrdx.h | 16 + arch/avr/src/avrdx/avrdx_delay.c | 350 ++++++++++++++++++ arch/avr/src/avrdx/avrdx_delay_loop.S | 81 ++++ arch/avr/src/avrdx/avrdx_delay_loop.h | 92 +++++ arch/avr/src/avrdx/avrdx_peripherals.c | 70 ++-- 10 files changed, 711 insertions(+), 36 deletions(-) create mode 100644 Documentation/platforms/avr/avrdx/docs/up_udelay.rst create mode 100644 arch/avr/src/avrdx/avrdx_delay.c create mode 100644 arch/avr/src/avrdx/avrdx_delay_loop.S create mode 100644 arch/avr/src/avrdx/avrdx_delay_loop.h diff --git a/Documentation/platforms/avr/avrdx/docs/up_udelay.rst b/Documentation/platforms/avr/avrdx/docs/up_udelay.rst new file mode 100644 index 00000000000..a89f954ff00 --- /dev/null +++ b/Documentation/platforms/avr/avrdx/docs/up_udelay.rst @@ -0,0 +1,69 @@ +============================================= +AVR DA/DB family ``up_udelay`` implementation +============================================= + +NuttX provides functions for busy sleep, these are documented +:doc:`here `. These functions +use ``BOARD_LOOPSPERMSEC`` configuration value to determine how many loops need +to be done to cause requested delay. Creator of a the board code is supposed +to calibrate this value to make the delay as precise as possible. + +This does not match well with AVR DA/DB microcontrollers because the CPU clock +frequency is configurable and unless the user chooses one and sticks with it, +any value in ``BOARD_LOOPSPERMSEC`` is going to be incorrect. + +Instead of using the default ``up_udelay`` function, custom one is provided. +When called, it determines current clock settings and infers required loop count +from that. + +Configuration +============= + +This implementation is enabled automatically and can be turned off using +:menuselection:`System Type --> Use AVR DA/DB implementation of up_udelay` +configuration option. If enabled, there are two additional options: + +:menuselection:`External clock is not supported in up_udelay` and +:menuselection:`32.768kHz oscillator is not supported in up_udelay`. + +The latter simply excludes the code that checks if any 32.768kHz clock source +is in use. + +The former does the same thing for external clock but also has an additional +effect: when not selected, it does not set ``ARCH_HAVE_DYNAMIC_UDELAY`` +configuration option. This in turn means that ``BOARD_LOOPSPERMSEC`` will +need to be configured +in :menuselection:`System Type --> Delay loops per millisecond` + +The reason for this is that with the external clock, there is no way of knowing +what the current CPU clock frequency is and it is therefore impossible +to calculate the loop count. It needs to be provided by board code's author +to match the external clock the board is using. If the main clock prescaler is +active, the loop value is recalculated to take that into consideration. + +Note that ``BOARD_LOOPSPERMSEC`` also needs to be specified if this ``up_udelay`` +implementation is disabled altogether. + +The other functions - ``up_mdelay`` and ``up_ndelay`` - are unchanged. These +simply multiply or divide their time parameter by 1000 and pass the result +to ``up_udelay``. + +Precision +========= + +The loop count calculation takes time and that time depends on current settings +and requested wait time. For example, calculation for wait time below +180 microseconds when using high frequency oscillator can be done using 16bit +arithmetic and without expensive division - unless the compiler is set +to optimize for code size. + +On the other hand - whenever the main clock prescaler is in effect, +division is unavoidable. + +The function attempts to account for this by guessing how much time all +the processing took and reduce the loop count accordingly. Nevertheless, +the wait may be considerably longer than requested for shorter delays +and lower clock speeds. + +(For example - 32.768kHz clock with prescaler of 2 needs to do two +divisions, taking 42 milliseconds total.) diff --git a/Documentation/platforms/avr/avrdx/index.rst b/Documentation/platforms/avr/avrdx/index.rst index 059413978ca..96b528b17e9 100644 --- a/Documentation/platforms/avr/avrdx/index.rst +++ b/Documentation/platforms/avr/avrdx/index.rst @@ -46,6 +46,9 @@ in :menuselection:`RTOS Features --> Clocks and Timers --> Support tick-less OS` changed to value of at least 300. Higher value is recommended though, 300us is not going to be precise at all. +Architecture code for this CPU family provides custom ``up_udelay`` function. +More information can be found in :doc:`docs/up_udelay` document + Peripheral Support ================== diff --git a/Documentation/reference/os/sleep.rst b/Documentation/reference/os/sleep.rst index ce7f06ff5eb..393cee5fe00 100644 --- a/Documentation/reference/os/sleep.rst +++ b/Documentation/reference/os/sleep.rst @@ -100,7 +100,8 @@ Busy Sleep Interfaces --------------------- Spin in a loop for the requested duration and never yield the CPU. The delay accuracy depends on -``CONFIG_BOARD_LOOPSPERMSEC``. +``CONFIG_BOARD_LOOPSPERMSEC`` (unless the architecture/board code replaces these +function(s) with an implementation that does not use the value.) .. c:function:: void up_mdelay(unsigned int milliseconds) diff --git a/arch/avr/src/avrdx/Kconfig b/arch/avr/src/avrdx/Kconfig index 3025f919cf6..dcfe1e674d8 100644 --- a/arch/avr/src/avrdx/Kconfig +++ b/arch/avr/src/avrdx/Kconfig @@ -583,4 +583,63 @@ config AVRDX_HFO_CLOCK_FREQ default 20000000 if AVRDX_HFO_CLOCK_20MHZ default 24000000 if AVRDX_HFO_CLOCK_24MHZ -endif +config AVRDX_ARCH_UDELAY + bool "Use AVR DA/DB implementation of up_udelay" + default y + select ARCH_HAVE_UDELAY + ---help--- + This option enables architecture-specific implementation + of up_udelay. + + The implementation is still a busy wait that runs a loop + as many times as needed for requested delay period. It is + "dynamic" meaning that it calculates number of loops needed + from current CPU frequency. + + If disabled, BOARD_LOOPSPERMSEC needs to be configured. + +config AVRDX_ARCH_UDELAY_NO_EXTCLK + bool "External clock is not supported in up_udelay" + default y + depends on AVRDX_ARCH_UDELAY + select ARCH_HAVE_DYNAMIC_UDELAY + ---help--- + Selecting this option indicates that the board does not use + external clock source (EXTCLK setting in CLKCTRL.MCLKCTRLA.) + + The implementation of up_udelay is able to determine CPU + clock frequency of the other sources but not this one. + If external clock is in use, the implementation needs to fall + back to the value of BOARD_LOOPSPERMSEC which must + be specified. + + If external clock is not in use (and this option is set), + BOARD_LOOPSPERMSEC must be set to its default value of -1. + + Note that this option does not apply to the XOSC32K setting. + We are able to determine CPU clock frequency rather easily + when driven by external 32.768 kHz crystal oscillator. + + Also note that if this option is enabled and the board uses + external clock (EXTCLK), up_udelay will fail and wait for + maximum amount of time. + + Say Y if your board does not use external clock. + +config AVRDX_ARCH_UDELAY_NO_OSC32K + bool "32.768kHz oscillator is not supported in up_udelay" + default y + depends on AVRDX_ARCH_UDELAY + ---help--- + Selecting this option indicates that the board does not use + either of OSC32K and XOSC32K settings in CLKCTRL.MCLKCTRLA. + In other words - neither source of 32.768kHz clock is used. + + If this is set, the implementation of up_udelay will skip + support for these frequencies to save flash space. Note that + if one of these clock sources is used anyway, up_udelay + will fail and wait for maximum amount of time. + + Say Y if your board does not use 32.768kHz clock. + +endif # if ARCH_CHIP_AVRDX diff --git a/arch/avr/src/avrdx/Make.defs b/arch/avr/src/avrdx/Make.defs index 4978f92b3a4..203390efb4e 100644 --- a/arch/avr/src/avrdx/Make.defs +++ b/arch/avr/src/avrdx/Make.defs @@ -59,6 +59,8 @@ CHIP_CSRCS = avrdx_lowconsole.c avrdx_lowinit.c avrdx_init.c CHIP_CSRCS += avrdx_serial.c avrdx_serial_early.c CHIP_CSRCS += avrdx_peripherals.c CHIP_CSRCS += avrdx_twi.c +CHIP_ASRCS += avrdx_delay_loop.S +CHIP_CSRCS += avrdx_delay.c # Configuration-dependent files diff --git a/arch/avr/src/avrdx/avrdx.h b/arch/avr/src/avrdx/avrdx.h index 88a2c413454..5b53c33337b 100644 --- a/arch/avr/src/avrdx/avrdx.h +++ b/arch/avr/src/avrdx/avrdx.h @@ -90,6 +90,22 @@ extern "C" void up_clkinitialize(void); +/**************************************************************************** + * Name: avrdx_current_freq_main_prescaler + * + * Description: + * Reduces given frequency by main clock prescaler. (Note - this is also + * used for non-frequency values. Implementation of up_udelay uses this + * function to reduce number of needed loops when external clock is used.) + * + * Input Parameters: + * frequency - input frequency + * + * Return value: output frequency in Hz + */ + +uint32_t avrdx_current_freq_main_prescaler(uint32_t frequency); + /**************************************************************************** * Name: avrdx_current_freq_per * diff --git a/arch/avr/src/avrdx/avrdx_delay.c b/arch/avr/src/avrdx/avrdx_delay.c new file mode 100644 index 00000000000..836276ee8da --- /dev/null +++ b/arch/avr/src/avrdx/avrdx_delay.c @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/avr/src/avrdx/avrdx_delay.c + * Custom implementation of up_udelay + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "avrdx.h" +#include "avrdx_delay_loop.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Division takes some 350 clock cycles and the delay loop needs 6 cycles + * per loop. Each division therefore takes as much time as this number + * of loops. + */ + +#define DIVISION_LOOP_INCREMENT 55 + +/* Multiplication is not that difficult */ + +#define MULTIPLICATION_LOOP_INCREMENT 5 + +/* Detect if divisions are optimized for size - that means the program + * will actually call the division function even when dividing by constant + * (which can be done without the actual division.) + */ + +#if (defined(CONFIG_ARCH_TOOLCHAIN_GCC) && defined(__OPTIMIZE_SIZE__)) +# define DIVISION_OPTIMIZED_FOR_SIZE +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_udelay + * + * Description: + * Delay execution for requested number of microseconds. + * + * This is a replacement for core implementation (which is defined + * as weak) specific for AVR DA/DB (AVRxt) cores. The main difference + * is the means used to calculate the number of cycles. The core function + * uses CONFIG_BOARD_LOOPSPERMSEC, a value configured by either the user, + * or the author of board code. + * + * AVRxt chips can run with various clock sources and those can be further + * configured and prescaled during runtime. As such, there is no single + * universal value of CONFIG_BOARD_LOOPSPERMSEC (unless the board uses + * external clock source.) + * + * This implementation therefore attempts to determine current running + * frequency of the MCU and calculate needed loop count from that. + * + * Note - same as core implementation of up_udelay, the function waits + * in a busy-wait loop. As such: + * + * * It is *** NOT multi-tasking friendly *** + * * If interrupted (by interrupt handler or preempted by another task), + * the total wait time is increased by the duration of the outside code. + * + * Input Parameters: + * microseconds - requested wait time + * + * Returned Value: none + * + * Assumptions/Limitations: + * Conversion from microseconds is done in run-time and can take + * a lot of cycles itself. + * + ****************************************************************************/ + +void up_udelay(useconds_t microseconds) +{ + /* Determined frequency of the CPU. 16bit variable is used + * to force math with smaller data types. + */ + + uint32_t f_cpu; + uint16_t f_cpu_shifted; + + /* Variable for determined loop count. The counter accumulates + * number of loops that were already "done" by computations + * in this function. + */ + + uint32_t loops; + uint16_t loop_like_counter = 0; + + /* This is added to loop_like_counter whenever this function + * does something that divides clock frequency by main prescaler + * if the main prescaler is enabled. + */ + + uint8_t main_clock_prescaler = 0; + + /* Other helper variables. */ + +#ifndef DIVISION_OPTIMIZED_FOR_SIZE + uint8_t microseconds_u8; +#endif + uint8_t mclkctrla; + + if (microseconds == 0) + { + return; + } + + if (CLKCTRL.MCLKCTRLB & CLKCTRL_PEN_bm) + { + /* Main prescaler is enabled. Frequency is divided + * by prescaling ratio, loop count calculation is slowed + * by that. + */ + + main_clock_prescaler = DIVISION_LOOP_INCREMENT; + } + + /* We need to convert duration in microseconds to loop count. + * + * - one clock cycle takes 1/f seconds (where f is CPU frequency.) + * - one loop of avrdx_delay_loop takes 6 clock cycles. Duration + * of one loop pass is therefore 6/f seconds. + * - we receive microseconds as a parameter, duration of one loop + * pass is 6e6/f microseconds + * - total number of required loops is therefore: + * usec/(6e6/f) == (f * usec) / 6e6 + */ + + f_cpu = avrdx_current_freq_cpu(); + + /* Increment the counter if the main clock prescaler is enabled, + * ie. if the frequency obtained from the hardware got divided. + */ + + loop_like_counter += main_clock_prescaler; + + mclkctrla = CLKCTRL.MCLKCTRLA & CLKCTRL_CLKSEL_GM; + if (mclkctrla == CLKCTRL_CLKSEL_OSCHF_GC) + { + /* All of this works with 32 bit operands and the calculation + * will involve some divisions and those are expensive. We can + * attempt to alleviate that by forcing 16 bit operation instead. + * That is possible but some conditions need to be met: + * + * 1. f_cpu is more than 1MHz (that's minimum for high frequency + * oscillator but it can be prescaled + * 2. microseconds is less than 180 + * 3. compiler is not optimizing for size + * + * The first condition allows us to bitshift the frequency by 16 + * without losing too much accuracy. + * + * The second condition makes sure that the result fits into 16 bit + * value even with maximum f_cpu (24MHz) + * + * The third condition accounts for the fact that the compiler + * is able to avoid division when dividing by a compile-time + * constant but will not do it if optimizing for size. + */ + +#ifndef DIVISION_OPTIMIZED_FOR_SIZE + if ((microseconds < 180) && (f_cpu >= 1000000)) + { + /* Condition above allows us to bitshift the frequency 16 bits + * to the right, we will bitshift the denominator as well + * to compensate + */ + + f_cpu_shifted = f_cpu >> 16; + microseconds_u8 = microseconds; + loops = microseconds_u8 * f_cpu_shifted / (6000000 >> 16); + } + else +#endif + { + /* Cannot do 16 bit math above for some reason. We still need + * to bitshift the inputs to the multiplication though, + * otherwise any delay (value of microseconds) greater than 178 + * overflows even 32 bit math. + */ + + if (f_cpu >= 1000000) + { + f_cpu_shifted = f_cpu >> 16; + } + else + { + /* This is safe to do - f_cpu is at least 41666, which + * is 1MHz / 24 from prescaler. + */ + + f_cpu_shifted = f_cpu >> 8; + + /* Still need to shift something by 8 to the right. Can't do + * microseconds blindly though - the compiler may know + * (from the test above) that the value is less than 180 + * and use that knowledge here to determine that bitshifted + * value is 0. Calculated value of loops will be 0 too and + * the function terminates because value of 0 will always + * be less than loop_like_counter which is non-zero. + * + * However - since we know frequency is less than 1MHz, + * we also know that the prescaler is applied. Reading f_cpu + * therefore did a division for 350 clock cycles. Highest + * value of f_cpu can therefore be 833333Hz (20MHz oscillator + * divided by 24 prescaler.) That is 1.2us per cycle. + * + * The division therefore took 420us. If the requested delay + * value is less than 256us, we already achieved that. + * + * So in the end - we CAN do the bitshift blindly. + */ + + microseconds = microseconds >> 8; + } + + /* This compiles into 2x16bit to 32bit multiplication, followed + * by division. Some 350 cycles for the division, + * 40 for multiplication, this function takes some, let's say + * 420 clock cycles total. This means that this function already + * did 70 loops by itself, without entering the actual loop. + */ + + loops = microseconds * f_cpu_shifted / (6000000 >> 16); + loop_like_counter += (DIVISION_LOOP_INCREMENT + \ + MULTIPLICATION_LOOP_INCREMENT); + } + } + +#ifndef CONFIG_AVRDX_ARCH_UDELAY_NO_OSC32K + else if ((mclkctrla == CLKCTRL_CLKSEL_OSC32K_GC) || \ + (mclkctrla == CLKCTRL_CLKSEL_XOSC32K_GC)) + { + /* Unlike with the high frequency oscillator, we can't bitshift + * the CPU frequency by 16 bits, that would erase it to zero. + * We can only do bitshift by 8 bits (and we have to because + * otherwise the multiplication between f_cpu and microseconds + * overflows for 2^17 (131072) microseconds or more. + * + * Also cannot assume it's actually 32.768k - main clock prescaler + * may be in effect. We will check for that one though, that could + * save us a lot of time. + */ + + if (main_clock_prescaler) + { + /* Main prescaler in use, we are out of luck and need + * to do the computation. Considering that the CPU clock + * is slow and we need to divide (and that obtaining + * f_cpu also did a division), the accuracy of this + * function will most likely be way off.) + */ + + f_cpu_shifted = f_cpu >> 8; + loops = f_cpu_shifted * microseconds / (6000000 >> 8); + loop_like_counter += DIVISION_LOOP_INCREMENT; + } + else + { + /* Main prescaler not in use, frequency is a known constant. + * + */ + + loops = (32768 >> 8) * microseconds / (6000000 >> 8); + + /* Does no division unless optimizing for size */ + +# ifdef DIVISION_OPTIMIZED_FOR_SIZE + loop_like_counter += DIVISION_LOOP_INCREMENT; +# endif + } + } +#endif + +#ifndef CONFIG_AVRDX_ARCH_UDELAY_NO_EXTCLK + else if (mclkctrla == CLKCTRL_CLKSEL_EXTCLK_GC) + { + loops = (USEC_PER_MSEC * microseconds) * CONFIG_BOARD_LOOPSPERMSEC; + avrdx_current_freq_main_prescaler(loops); + loop_like_counter += main_clock_prescaler; + } +#endif + + else + { + /* Unsupported clock, wait as long as possible */ + + loops = UINT32_MAX; + } + + if (loops < loop_like_counter) + { + /* This function already took more time that it was supposed to. + * Note - must not pass 0 to avrdx_delay_loop. + */ + + return; + } + + avrdx_delay_loop(loops - loop_like_counter); +} diff --git a/arch/avr/src/avrdx/avrdx_delay_loop.S b/arch/avr/src/avrdx/avrdx_delay_loop.S new file mode 100644 index 00000000000..0883075e466 --- /dev/null +++ b/arch/avr/src/avrdx/avrdx_delay_loop.S @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/avr/src/avrdx/avrdx_delay_loop.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * External Symbols + ****************************************************************************/ + + .file "avrdx_delay_loop.S" + +/**************************************************************************** + * Name: avrdx_delay_loop + * + * Description: + * Spins in a loop to cause a delay. On chips with AVRxt cores, it takes: + * (3 + count * 6 + call) cycles where count is the parameter and call + * is the number of cycles needed for instruction that jumps into this + * function (2 cycles for RCALL or 3 cycles for CALL, depends on what + * the compiler/linker does.) + * + * Input Parameters: + * Loop count - uint32_t (registers r22:r25) + * + * Return value: none + * + * Assumptions/Limitations: + * - only called from avrdx_udelay + * - count is not zero + * + ****************************************************************************/ + + .global avrdx_delay_loop + +avrdx_delay_loop: + + ; Because: + ; - all of the registers that contain loop count are call-clobbered. + ; - avrdx_udelay does not call this function with count set to zero + ; we can start counting right away + + ; Note - r22 cannot be used with SBIW. SBIW takes two clock cycles + ; though so we can achieve the same timing with with SUBI/SBC + +1: + subi r22, 1 ; subtract immediate, 1 cycle + sbc r23, r1 ; subtract zero register from r26 with carry + ; 1 cycle + sbc r24, r1 ; 1 cycle + sbc r25, r1 ; 1 cycle + brne 1b ; 2 cycles if the condition is true (ie. if branching) + ; 1 cycle otherwise + + ; 1 pass through the loop takes 6 cycles total (except for last pass + ; which takes 5 cycles) + +2: + ret ; 4 cycles diff --git a/arch/avr/src/avrdx/avrdx_delay_loop.h b/arch/avr/src/avrdx/avrdx_delay_loop.h new file mode 100644 index 00000000000..bc894323a59 --- /dev/null +++ b/arch/avr/src/avrdx/avrdx_delay_loop.h @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/avr/src/avrdx/avrdx_delay_loop.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_AVR_ETC_ETC_H +#define __ARCH_AVR_ETC_ETC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: avrdx_delay_loop + * + * Description: + * Spins in a loop to cause a delay. On chips with AVRxt cores, it takes: + * (3 + count * 6 + call) cycles where count is the parameter and call + * is the number of cycles needed for instruction that jumps into this + * function (2 cycles for RCALL or 3 cycles for CALL, depends on what + * the compiler/linker does.) + * + * Input Parameters: + * Loop count - uint32_t (registers r22:r25) + * + * Return value: none + * + * Assumptions/Limitations: + * - only called from avrdx_udelay + * - count is not zero + * + ****************************************************************************/ + +void avrdx_delay_loop(uint32_t count); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/arch/avr/src/avrdx/avrdx_peripherals.c b/arch/avr/src/avrdx/avrdx_peripherals.c index 7de37e38fd6..2cc260b9440 100644 --- a/arch/avr/src/avrdx/avrdx_peripherals.c +++ b/arch/avr/src/avrdx/avrdx_peripherals.c @@ -300,11 +300,46 @@ const IOBJ uint8_t avrdx_usart_portmux_masks[] = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: avrdx_current_freq_per_oschf + * + * Description: + * Calculate and return current f_per (peripheral clock frequency) + * + * Assumptions: + * Main clock source is internal oscillator + * + ****************************************************************************/ + +static uint32_t avrdx_current_freq_per_oschf(void) +{ + uint32_t f_per; + + /* Shortcut variables */ + + uint8_t frqsel; + + /* Calculate frequency in MHz, then divide it by main prescaler, + * if set. + */ + + frqsel = (CLKCTRL.OSCHFCTRLA & CLKCTRL_FRQSEL_GM) >> CLKCTRL_FRQSEL_GP; + f_per = 1000000UL * avrdx_frqsel_mhz[frqsel]; + + return avrdx_current_freq_main_prescaler(f_per); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: avrdx_current_freq_main_prescaler * * Description: - * Reduces given frequency by main clock prescaler. + * Reduces given frequency by main clock prescaler. (Note - this is also + * used for non-frequency values. Implementation of up_udelay uses this + * function to reduce number of needed loops when external clock is used.) * * Input Parameters: * frequency - input frequency @@ -329,39 +364,6 @@ uint32_t avrdx_current_freq_main_prescaler(uint32_t frequency) return frequency; } -/**************************************************************************** - * Name: avrdx_current_freq_per_oschf - * - * Description: - * Calculate and return current f_per (peripheral clock frequency) - * - * Assumptions: - * Main clock source is internal oscillator - * - ****************************************************************************/ - -uint32_t avrdx_current_freq_per_oschf(void) -{ - uint32_t f_per; - - /* Shortcut variables */ - - uint8_t frqsel; - - /* Calculate frequency in MHz, then divide it by main prescaler, - * if set. - */ - - frqsel = (CLKCTRL.OSCHFCTRLA & CLKCTRL_FRQSEL_GM) >> CLKCTRL_FRQSEL_GP; - f_per = 1000000UL * avrdx_frqsel_mhz[frqsel]; - - return avrdx_current_freq_main_prescaler(f_per); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - /**************************************************************************** * Name: avrdx_current_freq_per * From 3490eec26dfc24e034410687468d05df9ab7670e Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:21:36 +0200 Subject: [PATCH 064/268] !arm/stm32f7: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32F7 APIs were renamed from stm32f7_* and stm32f7x9_* forms to canonical stm32_* names. Signed-off-by: raiden00pl --- arch/arm/src/stm32f7/stm32_qspi.c | 16 ++++++++-------- arch/arm/src/stm32f7/stm32_qspi.h | 10 +++++----- arch/arm/src/stm32f7/stm32_rcc.h | 8 ++++---- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 8 ++++---- .../stm32f7/stm32f746g-disco/src/stm32_n25q.c | 2 +- .../stm32f777zit6-meadow/src/stm32_boot.c | 6 +++--- 6 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index c9f30d3155a..65e52304863 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -2489,7 +2489,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2502,7 +2502,7 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32f7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32f7_qspidev_s *priv; uint32_t regval; @@ -2625,7 +2625,7 @@ errout_with_dmach: } /**************************************************************************** - * Name: stm32f7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2639,9 +2639,9 @@ errout_with_dmach: * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, - const struct qspi_meminfo_s *meminfo, - uint32_t lpto) +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, + const struct qspi_meminfo_s *meminfo, + uint32_t lpto) { struct stm32f7_qspidev_s *priv = (struct stm32f7_qspidev_s *)dev; uint32_t regval; @@ -2717,7 +2717,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32f7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2730,7 +2730,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32f7_qspidev_s *priv = (struct stm32f7_qspidev_s *)dev; diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index ae919405ef5..a82c3296e06 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,9 +101,9 @@ struct qspi_dev_s *stm32f7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, - const struct qspi_meminfo_s *meminfo, - uint32_t lpto); +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, + const struct qspi_meminfo_s *meminfo, + uint32_t lpto); /**************************************************************************** * Name: stm32l4_qspi_exit_memorymapped @@ -119,7 +119,7 @@ void stm32f7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32f7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index b1c7aaefe37..9a1d166e96d 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -218,24 +218,24 @@ void stm32_rcc_disablelsi(void); #if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void); +void stm32_rcc_dsisrcphy(void); /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void); +void stm32_rcc_dsisrcpllr(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index d59a5729de6..070060097d5 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -1040,14 +1040,14 @@ static inline void rcc_enableperipherals(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcphy + * Name: stm32_rcc_dsisrcphy * * Description: * Set DSI clock source to DSI PHY * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcphy(void) +void stm32_rcc_dsisrcphy(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); @@ -1058,14 +1058,14 @@ void stm32f7x9_rcc_dsisrcphy(void) } /**************************************************************************** - * Name: stm32f7x9_rcc_dsisrcpllr + * Name: stm32_rcc_dsisrcpllr * * Description: * Set DSI clock source to PLLR * ****************************************************************************/ -void stm32f7x9_rcc_dsisrcpllr(void) +void stm32_rcc_dsisrcpllr(void) { uint32_t regval; regval = getreg32(STM32_RCC_DCKCFGR2); diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c index 6524920c680..3249fb4ac01 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_n25q.c @@ -81,7 +81,7 @@ int stm32_n25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32f7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index 5966f0315b8..adae2fb2067 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -46,7 +46,7 @@ /* MEADOW FIXME: header clash? */ -extern struct qspi_dev_s *stm32f7_qspi_initialize(int intf); +extern struct qspi_dev_s *stm32_qspi_initialize(int intf); #endif /**************************************************************************** @@ -132,7 +132,7 @@ void board_late_initialize(void) int ret; - qspi = stm32f7_qspi_initialize(0); + qspi = stm32_qspi_initialize(0); if (!qspi) { syslog(LOG_ERR, "ERROR: sam_qspi_initialize failed\n"); @@ -159,7 +159,7 @@ void board_late_initialize(void) meminfo.buflen = 0; meminfo.buffer = NULL; - stm32f7_qspi_enter_memorymapped(qspi, &meminfo, 80000000); + stm32_qspi_enter_memorymapped(qspi, &meminfo, 80000000); /* FIXME: stm32_mpu_uheap depends on PROTECTED && MPU * From 8ece56ff11fb2cd1e1f3680de54d03bb10ebdc39 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:22:18 +0200 Subject: [PATCH 065/268] !arm/stm32h5: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32H5 APIs were renamed from stm32h5_* forms to canonical stm32_* forms. Signed-off-by: raiden00pl --- arch/arm/src/stm32h5/stm32_adc.c | 7 +++--- arch/arm/src/stm32h5/stm32_adc.h | 7 +++--- arch/arm/src/stm32h5/stm32_dts.c | 2 +- arch/arm/src/stm32h5/stm32_dts.h | 2 +- arch/arm/src/stm32h5/stm32_flash.h | 12 +++++----- arch/arm/src/stm32h5/stm32_hsi48.c | 8 +++---- arch/arm/src/stm32h5/stm32_hsi48.h | 8 +++---- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 10 ++++----- arch/arm/src/stm32h5/stm32_usbdrdhost.h | 10 ++++----- arch/arm/src/stm32h5/stm32h563xx_flash.c | 22 +++++++++---------- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_adc.c | 4 ++-- .../arm/stm32h5/nucleo-h563zi/src/stm32_dts.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_usb.c | 6 ++--- 14 files changed, 50 insertions(+), 52 deletions(-) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index a503d233a94..c6bee5ce1fc 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -2585,12 +2585,11 @@ static int adc_timinit(struct stm32_dev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize ****************************************************************************/ -struct adc_dev_s *stm32h5_adc_initialize(int intf, - const uint8_t *chanlist, - int cchannels) +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int cchannels) { struct adc_dev_s *dev; struct stm32_dev_s *priv; diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index 7777d539376..cc4dff62400 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -500,7 +500,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h5_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -516,9 +516,8 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h5_adc_initialize(int intf, - const uint8_t *chanlist, - int nchannels); +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int nchannels); #undef EXTERN #ifdef __cplusplus } diff --git a/arch/arm/src/stm32h5/stm32_dts.c b/arch/arm/src/stm32h5/stm32_dts.c index efcf5da4795..4719c59ce1c 100644 --- a/arch/arm/src/stm32h5/stm32_dts.c +++ b/arch/arm/src/stm32h5/stm32_dts.c @@ -538,7 +538,7 @@ static int stm32_dts_isr(int irq, void *context, void *arg) * Name: stm32_dts_register ****************************************************************************/ -int stm32h5_dts_register(int devno) +int stm32_dts_register(int devno) { int ret; diff --git a/arch/arm/src/stm32h5/stm32_dts.h b/arch/arm/src/stm32h5/stm32_dts.h index 67e796699a9..560ef39cfdb 100644 --- a/arch/arm/src/stm32h5/stm32_dts.h +++ b/arch/arm/src/stm32h5/stm32_dts.h @@ -65,7 +65,7 @@ extern "C" #define EXTERN extern #endif -int stm32h5_dts_register(int devno); +int stm32_dts_register(int devno); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_flash.h b/arch/arm/src/stm32h5/stm32_flash.h index bb0220a9215..3dd4f10fd4e 100644 --- a/arch/arm/src/stm32h5/stm32_flash.h +++ b/arch/arm/src/stm32h5/stm32_flash.h @@ -45,16 +45,16 @@ extern "C" #define EXTERN extern #endif -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2); +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2); -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, - uint32_t clear2, uint32_t set2); +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, + uint32_t clear2, uint32_t set2); -int stm32h5_flash_swapbanks(void); +int stm32_flash_swapbanks(void); -void stm32h5_flash_lock(void); +void stm32_flash_lock(void); -void stm32h5_flash_unlock(void); +void stm32_flash_unlock(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index 7ad06b84912..1cf72a2e56f 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -39,7 +39,7 @@ #ifdef CONFIG_STM32H5_HAVE_HSI48 /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * The HSI48 @@ -65,7 +65,7 @@ * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -134,7 +134,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) } /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -147,7 +147,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32h5_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index 458a27f6aaa..a27e5458320 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32H5X3, STM32H596xx/4A6xx and STM32H5XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32h5_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32h5_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32h5_disable_hsi48(void); +void stm32_disable_hsi48(void); #endif /* CONFIG_STM32H5_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index 11d20e68e67..a9b9332eb21 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -2829,7 +2829,7 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) /* Enable VBUS drive */ - stm32h5_usbhost_vbusdrive(0, true); + stm32_usbdrdhost_vbusdrive(0, true); uinfo("USB Host initialized\n"); @@ -2841,14 +2841,14 @@ static int stm32_hw_initialize(struct stm32_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void) +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void) { struct stm32_usbhost_s *priv = &g_usbhost; int ret; @@ -2872,7 +2872,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) } /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Control VBUS power @@ -2881,7 +2881,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void) ****************************************************************************/ __attribute__((weak)) -void stm32_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* Default implementation - do nothing. * Board-specific code should override this to control VBUS power. diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.h b/arch/arm/src/stm32h5/stm32_usbdrdhost.h index f96b56e0cb7..1cccbd78e31 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.h +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.h @@ -63,7 +63,7 @@ * to the board-level USB host logic. */ -struct stm32h5_usbhost_connection_s +struct stm32_usbhost_connection_s { /* Wait for device connection/disconnection */ @@ -90,7 +90,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_usbhost_initialize + * Name: stm32_usbdrdhost_initialize * * Description: * Initialize USB host controller hardware. @@ -108,10 +108,10 @@ extern "C" * ****************************************************************************/ -struct usbhost_connection_s *stm32h5_usbhost_initialize(void); +struct usbhost_connection_s *stm32_usbdrdhost_initialize(void); /**************************************************************************** - * Name: stm32h5_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable VBUS power to the connected USB device. @@ -133,7 +133,7 @@ struct usbhost_connection_s *stm32h5_usbhost_initialize(void); * ****************************************************************************/ -void stm32h5_usbhost_vbusdrive(int port, bool enable); +void stm32_usbdrdhost_vbusdrive(int port, bool enable); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 199cc59b9d9..11656e1212b 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -344,14 +344,14 @@ static void flash_lock_opt(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32h5_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock_nscr(); @@ -359,14 +359,14 @@ void stm32h5_flash_unlock(void) } /**************************************************************************** - * Name: stm32h5_flash_lock + * Name: stm32_flash_lock * * Description: * Lock non-secure flash control * ****************************************************************************/ -void stm32h5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock_nscr(); @@ -374,7 +374,7 @@ void stm32h5_flash_lock(void) } /**************************************************************************** - * Name: stm32h5_flash_getopt + * Name: stm32_flash_getopt * * Description: * Read the current flash option bytes from FLASH_OPTSR_CUR and @@ -386,14 +386,14 @@ void stm32h5_flash_lock(void) * ****************************************************************************/ -void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) +void stm32_flash_getopt(uint32_t *opt1, uint32_t *opt2) { *opt1 = getreg32(STM32_FLASH_OPTSR_CUR); *opt2 = getreg32(STM32_FLASH_OPTSR2_CUR); } /**************************************************************************** - * Name: stm32h5_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. @@ -412,8 +412,8 @@ void stm32h5_flash_getopt(uint32_t *opt1, uint32_t *opt2) * ****************************************************************************/ -int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, - uint32_t clear2, uint32_t set2) +int stm32_flash_optmodify(uint32_t clear1, uint32_t set1, + uint32_t clear2, uint32_t set2) { int ret; uint32_t reg; @@ -451,7 +451,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, } /**************************************************************************** - * Name: stm32h5_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -464,7 +464,7 @@ int stm32h5_flash_optmodify(uint32_t clear1, uint32_t set1, * ****************************************************************************/ -int stm32h5_flash_swapbanks(void) +int stm32_flash_swapbanks(void) { uint32_t reg; bool was_locked; diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index 87b12f55e92..c26278872f2 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -845,7 +845,7 @@ void stm32_rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c index ff662f03c1f..9061382e463 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c @@ -122,7 +122,7 @@ int stm32_adc_setup(void) stm32_configgpio(g_pinlist1[i]); } - adc1 = stm32h5_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); + adc1 = stm32_adc_initialize(1, g_chanlist1, ADC1_NCHANNELS); if (adc1 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); @@ -145,7 +145,7 @@ int stm32_adc_setup(void) stm32_configgpio(g_pinlist2[i]); } - adc2 = stm32h5_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); + adc2 = stm32_adc_initialize(2, g_chanlist2, ADC2_NCHANNELS); if (adc2 == NULL) { aerr("ERROR: Failed to get ADC interface 1\n"); diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c index 4b1fbd9a713..8a0e6d61858 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c @@ -75,7 +75,7 @@ int stm32_dts_setup(int devno) { /* Register the DTS driver at "/dev/sensor_temp0" */ - ret = stm32h5_dts_register(0); + ret = stm32_dts_register(0); if (ret < 0) { aerr("ERROR: dts_register /dev/dts0 failed: %d\n", ret); diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c index cb293dd7f6e..dcf5bae1cbd 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c @@ -185,7 +185,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32h5_usbhost_initialize(); + g_usbconn = stm32_usbdrdhost_initialize(); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -203,7 +203,7 @@ int stm32_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32_usbhost_vbusdrive + * Name: stm32_usbdrdhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -232,7 +232,7 @@ int stm32_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32h5_usbhost_vbusdrive(int port, bool enable) +void stm32_usbdrdhost_vbusdrive(int port, bool enable) { /* The Nucleo-h563zi doesn't have hardware for a vbus drive. * Instead to get host working, you need to put an extra jumper From fe42e755a11b5db9e4e24869c82ad4860f6600a9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:23:50 +0200 Subject: [PATCH 066/268] !arm/stm32h7: standardize public API prefix to stm32_ BREAKING CHANGE: Public STM32H7 APIs were renamed from stm32h7_* forms to canonical stm32_* forms. Signed-off-by: raiden00pl --- arch/arm/src/stm32h7/stm32_adc.c | 7 ++--- arch/arm/src/stm32h7/stm32_adc.h | 7 ++--- arch/arm/src/stm32h7/stm32_dualcore.c | 8 ++--- arch/arm/src/stm32h7/stm32_dualcore.h | 8 ++--- arch/arm/src/stm32h7/stm32_flash.h | 24 +++++++-------- arch/arm/src/stm32h7/stm32_qspi.c | 16 +++++----- arch/arm/src/stm32h7/stm32_qspi.h | 10 +++---- arch/arm/src/stm32h7/stm32_start.c | 4 +-- arch/arm/src/stm32h7/stm32h743xx_flash.c | 30 +++++++++---------- arch/arm/src/stm32h7/stm32h7b3xx_flash.c | 30 +++++++++---------- .../linum-stm32h753bi/src/stm32_w25q.c | 2 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_adc.c | 6 ++-- .../arm/stm32h7/nucleo-h743zi/src/stm32_adc.c | 6 ++-- .../stm32h7/nucleo-h743zi2/src/stm32_adc.c | 4 +-- .../arm/stm32h7/nucleo-h745zi/src/stm32_adc.c | 4 +-- .../arm/stm32h7/nucleo-h753zi/src/stm32_adc.c | 4 +-- .../stm32h7/stm32h747i-disco/src/stm32_adc.c | 4 +-- 17 files changed, 86 insertions(+), 88 deletions(-) diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index af06b0b83bf..1db742bb688 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -2277,7 +2277,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2302,9 +2302,8 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, * ****************************************************************************/ -struct adc_dev_s *stm32h7_adc_initialize(int intf, - const uint8_t *chanlist, - int cchannels) +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int cchannels) { struct adc_dev_s *dev; struct stm32_dev_s *priv; diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index df7e5132e05..ce6a460ca92 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -785,7 +785,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -801,9 +801,8 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32h7_adc_initialize(int intf, - const uint8_t *chanlist, - int nchannels); +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int nchannels); #undef EXTERN #ifdef __cplusplus } diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 5288a3f2206..85ab5e0ba3c 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -137,14 +137,14 @@ static void stm32_cpu2sem_take(void) defined(CONFIG_STM32H7_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void) +void stm32_start_cm4(void) { uint32_t regval = 0; @@ -177,14 +177,14 @@ void stm32h7_start_cm4(void) #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void) +void stm32_waitfor_cm7(void) { if (stm32_cm4_boot() == true) { diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index ab0524de3bf..64f42ade6b3 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -54,26 +54,26 @@ extern "C" defined(CONFIG_STM32H7_CORTEXM4_ENABLED) /**************************************************************************** - * Name: stm32h7_start_cm4 + * Name: stm32_start_cm4 * * Description: * Start CM4 core * ****************************************************************************/ -void stm32h7_start_cm4(void); +void stm32_start_cm4(void); #endif #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /**************************************************************************** - * Name: stm32h7_waitfor_cm7 + * Name: stm32_waitfor_cm7 * * Description: * Wait for CM7 core initialization * ****************************************************************************/ -void stm32h7_waitfor_cm7(void); +void stm32_waitfor_cm7(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32h7/stm32_flash.h b/arch/arm/src/stm32h7/stm32_flash.h index 39481210dda..cdd73d3b31d 100644 --- a/arch/arm/src/stm32h7/stm32_flash.h +++ b/arch/arm/src/stm32h7/stm32_flash.h @@ -48,27 +48,27 @@ extern "C" #endif /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void); +uint32_t stm32_flash_getopt(void); /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); +void stm32_flash_optmodify(uint32_t clear, uint32_t set); /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -76,37 +76,37 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set); * ****************************************************************************/ -void stm32h7_flash_swapbanks(void); +void stm32_flash_swapbanks(void); /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(void); +int stm32_flash_lock(void); /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t page, bool enabled); +int stm32_flash_writeprotect(size_t page, bool enabled); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index c346fa55125..c6f72058489 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -2543,7 +2543,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2556,7 +2556,7 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32h7_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { struct stm32h7_qspidev_s *priv; uint32_t regval; @@ -2683,7 +2683,7 @@ errout_with_dmach: } /**************************************************************************** - * Name: stm32h7_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2697,9 +2697,9 @@ errout_with_dmach: * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, - const struct qspi_meminfo_s *meminfo, - uint32_t lpto) +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, + const struct qspi_meminfo_s *meminfo, + uint32_t lpto) { struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev; uint32_t regval; @@ -2775,7 +2775,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32h7_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2788,7 +2788,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { struct stm32h7_qspidev_s *priv = (struct stm32h7_qspidev_s *)dev; diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index 36724b2538e..dd2c257584c 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32h7_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** * Name: stm32l4_qspi_enter_memorymapped @@ -101,9 +101,9 @@ struct qspi_dev_s *stm32h7_qspi_initialize(int intf); * ****************************************************************************/ -void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, - const struct qspi_meminfo_s *meminfo, - uint32_t lpto); +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, + const struct qspi_meminfo_s *meminfo, + uint32_t lpto); /**************************************************************************** * Name: stm32l4_qspi_exit_memorymapped @@ -119,7 +119,7 @@ void stm32h7_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32h7_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 88d53cf8bb7..70c7d4ade3f 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -195,7 +195,7 @@ void __start(void) #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 /* Wait for CM7 initialization done */ - stm32h7_waitfor_cm7(); + stm32_waitfor_cm7(); #endif /* If enabled reset the MPU */ @@ -309,7 +309,7 @@ void __start(void) /* Start CM4 core after clock configuration is done */ - stm32h7_start_cm4(); + stm32_start_cm4(); #endif nx_start(); diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index 1d68c42c786..ddf3c13a5b8 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -508,14 +508,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -536,14 +536,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -564,14 +564,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -605,14 +605,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -625,14 +625,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -652,7 +652,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -660,16 +660,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index c76b4e307a3..278d0d2171d 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -478,14 +478,14 @@ static void stm32h7_save_flashopt(struct stm32h7_flash_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32h7_flash_unlock + * Name: stm32_flash_unlock * * Description: * Unlocks a bank * ****************************************************************************/ -int stm32h7_flash_unlock(size_t addr) +int stm32_flash_unlock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -506,14 +506,14 @@ int stm32h7_flash_unlock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_lock + * Name: stm32_flash_lock * * Description: * Locks a bank * ****************************************************************************/ -int stm32h7_flash_lock(size_t addr) +int stm32_flash_lock(size_t addr) { int ret = -ENODEV; struct stm32h7_flash_priv_s *priv = stm32h7_flash_bank(addr); @@ -534,14 +534,14 @@ int stm32h7_flash_lock(size_t addr) } /**************************************************************************** - * Name: stm32h7_flash_writeprotect + * Name: stm32_flash_writeprotect * * Description: * Enable or disable the write protection of a flash sector. * ****************************************************************************/ -int stm32h7_flash_writeprotect(size_t block, bool enabled) +int stm32_flash_writeprotect(size_t block, bool enabled) { struct stm32h7_flash_priv_s *priv; uint32_t setbits = 0; @@ -575,14 +575,14 @@ int stm32h7_flash_writeprotect(size_t block, bool enabled) } /**************************************************************************** - * Name: stm32h7_flash_getopt + * Name: stm32_flash_getopt * * Description: * Returns the current flash option bytes from the FLASH_OPTSR_CR register. * ****************************************************************************/ -uint32_t stm32h7_flash_getopt(void) +uint32_t stm32_flash_getopt(void) { struct stm32h7_flash_priv_s *priv; priv = stm32h7_flash_bank(STM32_FLASH_BANK1); @@ -595,14 +595,14 @@ uint32_t stm32h7_flash_getopt(void) } /**************************************************************************** - * Name: stm32h7_flash_optmodify + * Name: stm32_flash_optmodify * * Description: * Modifies the current flash option bytes, given bits to set and clear. * ****************************************************************************/ -void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) +void stm32_flash_optmodify(uint32_t clear, uint32_t set) { struct stm32h7_flash_priv_s *priv; bool was_locked; @@ -622,7 +622,7 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) } /**************************************************************************** - * Name: stm32h7_flash_swapbanks + * Name: stm32_flash_swapbanks * * Description: * Swaps banks 1 and 2 in the processor's memory map. Takes effect @@ -630,16 +630,16 @@ void stm32h7_flash_optmodify(uint32_t clear, uint32_t set) * ****************************************************************************/ -void stm32h7_flash_swapbanks(void) +void stm32_flash_swapbanks(void) { - uint32_t opts = stm32h7_flash_getopt(); + uint32_t opts = stm32_flash_getopt(); if (opts & FLASH_OPTCR_SWAPBANK) { - stm32h7_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); + stm32_flash_optmodify(FLASH_OPTCR_SWAPBANK, 0); } else { - stm32h7_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); + stm32_flash_optmodify(0, FLASH_OPTCR_SWAPBANK); } } diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c index 26a494c7619..98c8454c49c 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c @@ -79,7 +79,7 @@ int stm32_w25qxxx_setup(void) struct mtd_dev_s *mtd_dev; int ret = -1; - qspi_dev = stm32h7_qspi_initialize(0); + qspi_dev = stm32_qspi_initialize(0); if (!qspi_dev) { _err("ERROR: Failed to initialize W25 minor %d: %d\n", diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index 8170b1decc7..60de3707aae 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index 46744e439de..a4ac81103a6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -171,7 +171,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -203,7 +203,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_adc2_chanlist, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -235,7 +235,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index 04a0ef65f5d..c11ea35b3f3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index 731b1421e93..7ab6b8a0331 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -160,7 +160,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -191,7 +191,7 @@ int stm32_adc_setup(int adcno) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 3bd182ef382..8bc9ba8841a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -157,7 +157,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -188,7 +188,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index 43d90ea1c58..89c9a723d69 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -149,7 +149,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -180,7 +180,7 @@ int stm32_adc_setup(void) /* Call stm32_adcinitialize() to get an instance of the ADC interface */ - adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); From bc41d984cc523bf7d0c2337e2f7849cdfe54f6a6 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:33 +0200 Subject: [PATCH 067/268] !arm/stm32l4: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32L4 interfaces were renamed from stm32l4_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names were normalized to stm32_* equivalents (including timer/lptimer/dma/freerun API-facing types), and stm32l4can_initialize() was renamed to stm32_caninitialize(). The STM32L4 root family header was renamed from stm32l4.h to stm32.h; all STM32L4 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32l4/{stm32l4.h => stm32.h} | 2 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 14 +- arch/arm/src/stm32l4/stm32l4_1wire.h | 10 +- arch/arm/src/stm32l4/stm32l4_adc.c | 39 +- arch/arm/src/stm32l4/stm32l4_adc.h | 17 +- arch/arm/src/stm32l4/stm32l4_allocateheap.c | 8 +- arch/arm/src/stm32l4/stm32l4_can.c | 110 +- arch/arm/src/stm32l4/stm32l4_can.h | 4 +- arch/arm/src/stm32l4/stm32l4_comp.c | 73 +- arch/arm/src/stm32l4/stm32l4_comp.h | 33 +- arch/arm/src/stm32l4/stm32l4_dac.c | 62 +- arch/arm/src/stm32l4/stm32l4_dac.h | 8 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 17 +- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 7 +- arch/arm/src/stm32l4/stm32l4_dfumode.c | 4 +- arch/arm/src/stm32l4/stm32l4_dfumode.h | 4 +- arch/arm/src/stm32l4/stm32l4_dma.h | 72 +- arch/arm/src/stm32l4/stm32l4_dumpgpio.c | 4 +- arch/arm/src/stm32l4/stm32l4_exti.h | 16 +- arch/arm/src/stm32l4/stm32l4_exti_alarm.c | 10 +- arch/arm/src/stm32l4/stm32l4_exti_comp.c | 8 +- arch/arm/src/stm32l4/stm32l4_exti_gpio.c | 40 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.c | 10 +- arch/arm/src/stm32l4/stm32l4_exti_pwr.h | 4 +- arch/arm/src/stm32l4/stm32l4_exti_wakeup.c | 10 +- arch/arm/src/stm32l4/stm32l4_firewall.c | 2 +- arch/arm/src/stm32l4/stm32l4_firewall.h | 6 +- arch/arm/src/stm32l4/stm32l4_flash.c | 16 +- arch/arm/src/stm32l4/stm32l4_flash.h | 8 +- arch/arm/src/stm32l4/stm32l4_freerun.c | 32 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 22 +- arch/arm/src/stm32l4/stm32l4_gpio.c | 28 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 36 +- arch/arm/src/stm32l4/stm32l4_hsi48.c | 8 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 8 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 532 +++---- arch/arm/src/stm32l4/stm32l4_i2c.h | 10 +- arch/arm/src/stm32l4/stm32l4_idle.c | 6 +- arch/arm/src/stm32l4/stm32l4_irq.c | 40 +- arch/arm/src/stm32l4/stm32l4_iwdg.c | 112 +- arch/arm/src/stm32l4/stm32l4_lowputc.c | 20 +- arch/arm/src/stm32l4/stm32l4_lowputc.h | 4 +- arch/arm/src/stm32l4/stm32l4_lptim.c | 238 +-- arch/arm/src/stm32l4/stm32l4_lptim.h | 48 +- arch/arm/src/stm32l4/stm32l4_lse.c | 10 +- arch/arm/src/stm32l4/stm32l4_lsi.c | 8 +- arch/arm/src/stm32l4/stm32l4_mpuinit.c | 8 +- arch/arm/src/stm32l4/stm32l4_mpuinit.h | 12 +- arch/arm/src/stm32l4/stm32l4_oneshot.c | 42 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 28 +- .../src/stm32l4/stm32l4_oneshot_lowerhalf.c | 78 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 12 +- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 1318 ++++++++--------- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 1136 +++++++------- arch/arm/src/stm32l4/stm32l4_pm.h | 20 +- arch/arm/src/stm32l4/stm32l4_pmlpr.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmsleep.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmstandby.c | 4 +- arch/arm/src/stm32l4/stm32l4_pmstop.c | 8 +- arch/arm/src/stm32l4/stm32l4_pulsecount.c | 102 +- arch/arm/src/stm32l4/stm32l4_pulsecount.h | 2 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 160 +- arch/arm/src/stm32l4/stm32l4_pwm.h | 28 +- arch/arm/src/stm32l4/stm32l4_pwr.c | 68 +- arch/arm/src/stm32l4/stm32l4_pwr.h | 22 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 304 ++-- arch/arm/src/stm32l4/stm32l4_qencoder.h | 4 +- arch/arm/src/stm32l4/stm32l4_qspi.c | 122 +- arch/arm/src/stm32l4/stm32l4_qspi.h | 12 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 30 +- arch/arm/src/stm32l4/stm32l4_rcc.h | 34 +- arch/arm/src/stm32l4/stm32l4_rng.c | 34 +- arch/arm/src/stm32l4/stm32l4_rtc.c | 90 +- arch/arm/src/stm32l4/stm32l4_rtc.h | 42 +- arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c | 152 +- arch/arm/src/stm32l4/stm32l4_sai.c | 104 +- arch/arm/src/stm32l4/stm32l4_sai.h | 4 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 28 +- arch/arm/src/stm32l4/stm32l4_serial.c | 208 +-- arch/arm/src/stm32l4/stm32l4_spi.c | 182 +-- arch/arm/src/stm32l4/stm32l4_spi.h | 48 +- arch/arm/src/stm32l4/stm32l4_start.c | 12 +- arch/arm/src/stm32l4/stm32l4_start.h | 4 +- arch/arm/src/stm32l4/stm32l4_tickless.c | 32 +- arch/arm/src/stm32l4/stm32l4_tim.c | 526 +++---- arch/arm/src/stm32l4/stm32l4_tim.h | 58 +- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 110 +- arch/arm/src/stm32l4/stm32l4_timerisr.c | 8 +- arch/arm/src/stm32l4/stm32l4_uart.h | 4 +- arch/arm/src/stm32l4/stm32l4_uid.c | 2 +- arch/arm/src/stm32l4/stm32l4_uid.h | 2 +- arch/arm/src/stm32l4/stm32l4_usbdev.c | 1036 ++++++------- arch/arm/src/stm32l4/stm32l4_usbdev.h | 6 +- arch/arm/src/stm32l4/stm32l4_usbhost.h | 4 +- arch/arm/src/stm32l4/stm32l4_usbhost_trace.c | 6 +- arch/arm/src/stm32l4/stm32l4_userspace.c | 6 +- arch/arm/src/stm32l4/stm32l4_userspace.h | 4 +- arch/arm/src/stm32l4/stm32l4_waste.c | 2 +- arch/arm/src/stm32l4/stm32l4_waste.h | 4 +- arch/arm/src/stm32l4/stm32l4_wdg.h | 8 +- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 14 +- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 12 +- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 110 +- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 18 +- arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 196 +-- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 12 +- .../b-l475e-iot01a/src/b-l475e-iot01a.h | 14 +- .../b-l475e-iot01a/src/stm32_autoleds.c | 6 +- .../stm32l4/b-l475e-iot01a/src/stm32_boot.c | 12 +- .../b-l475e-iot01a/src/stm32_bringup.c | 14 +- .../stm32l4/b-l475e-iot01a/src/stm32_spi.c | 44 +- .../stm32l4/b-l475e-iot01a/src/stm32_spirit.c | 64 +- .../stm32l4/b-l475e-iot01a/src/stm32_timer.c | 24 +- .../b-l475e-iot01a/src/stm32_userleds.c | 12 +- .../arm/stm32l4/nucleo-l432kc/include/board.h | 4 +- .../stm32l4/nucleo-l432kc/src/nucleo-l432kc.h | 32 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_adc.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_at45db.c | 2 +- .../nucleo-l432kc/src/stm32_autoleds.c | 8 +- .../stm32l4/nucleo-l432kc/src/stm32_boot.c | 12 +- .../stm32l4/nucleo-l432kc/src/stm32_bringup.c | 36 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_dac.c | 6 +- .../stm32l4/nucleo-l432kc/src/stm32_dac7571.c | 10 +- .../nucleo-l432kc/src/stm32_dac_wgen.c | 4 +- .../stm32l4/nucleo-l432kc/src/stm32_gpio.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_ina219.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_ina226.c | 10 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c | 18 +- .../nucleo-l432kc/src/stm32_qencoder.c | 6 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 40 +- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_timer.c | 2 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_uid.c | 2 +- .../nucleo-l432kc/src/stm32_userleds.c | 8 +- .../nucleo-l432kc/src/stm32_zerocross.c | 8 +- .../arm/stm32l4/nucleo-l452re/include/board.h | 4 +- .../stm32l4/nucleo-l452re/src/nucleo-l452re.h | 12 +- .../arm/stm32l4/nucleo-l452re/src/stm32_adc.c | 14 +- .../nucleo-l452re/src/stm32_autoleds.c | 6 +- .../stm32l4/nucleo-l452re/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l452re/src/stm32_bringup.c | 6 +- .../stm32l4/nucleo-l452re/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l452re/src/stm32_dac.c | 6 +- .../arm/stm32l4/nucleo-l452re/src/stm32_spi.c | 44 +- .../nucleo-l452re/src/stm32_userleds.c | 10 +- .../stm32l4/nucleo-l476rg/src/nucleo-l476rg.h | 36 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_adc.c | 10 +- .../nucleo-l476rg/src/stm32_ajoystick.c | 10 +- .../stm32l4/nucleo-l476rg/src/stm32_as726x.c | 4 +- .../nucleo-l476rg/src/stm32_autoleds.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_bmp180.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_bmp280.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_boot.c | 12 +- .../stm32l4/nucleo-l476rg/src/stm32_bringup.c | 46 +- .../stm32l4/nucleo-l476rg/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_can.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_cc1101.c | 14 +- .../stm32l4/nucleo-l476rg/src/stm32_gpio.c | 28 +- .../nucleo-l476rg/src/stm32_lsm303agr.c | 8 +- .../stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c | 10 +- .../stm32l4/nucleo-l476rg/src/stm32_mpu9250.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_pcd8544.c | 14 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c | 28 +- .../nucleo-l476rg/src/stm32_qencoder.c | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 58 +- .../nucleo-l476rg/src/stm32_spimmcsd.c | 12 +- .../stm32l4/nucleo-l476rg/src/stm32_timer.c | 2 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_uid.c | 2 +- .../nucleo-l476rg/src/stm32_userleds.c | 12 +- .../arm/stm32l4/nucleo-l496zg/include/board.h | 4 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 14 +- .../nucleo-l496zg/src/stm32_autoleds.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_bringup.c | 10 +- .../stm32l4/nucleo-l496zg/src/stm32_buttons.c | 6 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_dac.c | 4 +- .../stm32l4/nucleo-l496zg/src/stm32_dfsdm.c | 8 +- .../stm32l4/nucleo-l496zg/src/stm32_sdio.c | 14 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_spi.c | 16 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_uid.c | 2 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 14 +- .../nucleo-l496zg/src/stm32_userleds.c | 6 +- .../steval-stlcs01v1/src/steval-stlcs01v1.h | 8 +- .../steval-stlcs01v1/src/stm32_autoleds.c | 8 +- .../stm32l4/steval-stlcs01v1/src/stm32_boot.c | 16 +- .../steval-stlcs01v1/src/stm32_bringup.c | 4 +- .../stm32l4/steval-stlcs01v1/src/stm32_usb.c | 14 +- .../arm/stm32l4/stm32l476-mdk/include/board.h | 4 +- .../stm32l476-mdk/src/stm32_autoleds.c | 10 +- .../stm32l4/stm32l476-mdk/src/stm32_boot.c | 12 +- .../stm32l4/stm32l476-mdk/src/stm32_buttons.c | 6 +- .../stm32l476-mdk/src/stm32_clockconfig.c | 8 +- .../arm/stm32l4/stm32l476-mdk/src/stm32_spi.c | 2 +- .../stm32l476-mdk/src/stm32_userleds.c | 18 +- .../stm32l4/stm32l476vg-disco/include/board.h | 4 +- .../stm32l476vg-disco/src/stm32_autoleds.c | 26 +- .../stm32l476vg-disco/src/stm32_boot.c | 8 +- .../stm32l476vg-disco/src/stm32_bringup.c | 12 +- .../stm32l476vg-disco/src/stm32_buttons.c | 6 +- .../stm32l476vg-disco/src/stm32_clockconfig.c | 8 +- .../stm32l4/stm32l476vg-disco/src/stm32_spi.c | 2 +- .../stm32l4/stm32l476vg-disco/src/stm32_uid.c | 2 +- .../stm32l4/stm32l476vg-disco/src/stm32_usb.c | 40 +- .../stm32l476vg-disco/src/stm32_userleds.c | 30 +- .../stm32l476vg-disco/src/stm32l476vg-disco.h | 4 +- .../stm32l4/stm32l4r9ai-disco/include/board.h | 4 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_adc.c | 14 +- .../stm32l4r9ai-disco/src/stm32_autoleds.c | 26 +- .../stm32l4r9ai-disco/src/stm32_boot.c | 6 +- .../stm32l4r9ai-disco/src/stm32_bringup.c | 16 +- .../stm32l4r9ai-disco/src/stm32_buttons.c | 6 +- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 8 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_dac.c | 6 +- .../stm32l4r9ai-disco/src/stm32_dfsdm.c | 8 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_spi.c | 40 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_uid.c | 2 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_usb.c | 40 +- .../stm32l4r9ai-disco/src/stm32_userleds.c | 30 +- .../stm32l4r9ai-disco/src/stm32l4r9ai-disco.h | 16 +- include/nuttx/analog/ioctl.h | 6 +- 220 files changed, 4966 insertions(+), 4974 deletions(-) rename arch/arm/src/stm32l4/{stm32l4.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32l4/stm32l4.h b/arch/arm/src/stm32l4/stm32.h similarity index 98% rename from arch/arm/src/stm32l4/stm32l4.h rename to arch/arm/src/stm32l4/stm32.h index 8aeee5c6861..30d93ed49fd 100644 --- a/arch/arm/src/stm32l4/stm32l4.h +++ b/arch/arm/src/stm32l4/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l4/stm32l4.h + * arch/arm/src/stm32l4/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index 2a4ff88f8f5..c316fb57fb4 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -575,7 +575,7 @@ static int stm32_1wire_init(struct stm32_1wire_priv_s *priv) /* Configure pins for USART use */ - stm32l4_configgpio(config->data_pin); + stm32_configgpio(config->data_pin); ret = irq_attach(config->irq, stm32_1wire_isr, priv); if (ret == OK) @@ -604,7 +604,7 @@ static int stm32_1wire_deinit(struct stm32_1wire_priv_s *priv) /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(config->data_pin); + stm32_unconfiggpio(config->data_pin); /* Disable RXNEIE, Rx, Tx, and the USART */ @@ -1125,7 +1125,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -1141,7 +1141,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port) +struct onewire_dev_s *stm32_1wireinitialize(int port) { struct stm32_1wire_priv_s *priv = NULL; /* Private data of device with multiple instances */ struct stm32_1wire_inst_s *inst = NULL; /* Device, single instance */ @@ -1218,13 +1218,13 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) } /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -1232,7 +1232,7 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port) * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev) +int stm32_1wireuninitialize(struct onewire_dev_s *dev) { struct stm32_1wire_priv_s *priv = ((struct stm32_1wire_inst_s *)dev)->priv; diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.h b/arch/arm/src/stm32l4/stm32l4_1wire.h index b196230e655..f76918de269 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.h +++ b/arch/arm/src/stm32l4/stm32l4_1wire.h @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_1wireinitialize + * Name: stm32_1wireinitialize * * Description: * Initialize the selected 1-Wire port. And return a unique instance of @@ -52,16 +52,16 @@ * ****************************************************************************/ -struct onewire_dev_s *stm32l4_1wireinitialize(int port); +struct onewire_dev_s *stm32_1wireinitialize(int port); /**************************************************************************** - * Name: stm32l4_1wireuninitialize + * Name: stm32_1wireuninitialize * * Description: * De-initialize the selected 1-Wire port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_1wireinitialize() + * Device structure as returned by the stm32_1wireinitialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -69,6 +69,6 @@ struct onewire_dev_s *stm32l4_1wireinitialize(int port); * ****************************************************************************/ -int stm32l4_1wireuninitialize(struct onewire_dev_s *dev); +int stm32_1wireuninitialize(struct onewire_dev_s *dev); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_1WIRE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index 52d7977f353..347b5837903 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -2074,7 +2074,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) } break; - case ANIOC_STM32L4_TRIGGER_REG: + case ANIOC_STM32_TRIGGER_REG: /* Start regular conversion if regular channels configured */ @@ -2086,7 +2086,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) break; #ifdef ADC_HAVE_INJECTED - case ANIOC_STM32L4_TRIGGER_INJ: + case ANIOC_STM32_TRIGGER_INJ: /* Start injected conversion if injected channels configured */ @@ -2354,20 +2354,20 @@ static void adc_dma_start(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); #ifndef CONFIG_STM32L4_ADC_NOIRQ - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, priv->rnchannels * priv->dmabatch, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, adc_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, adc_dmaconvcallback, dev, false); #endif } @@ -2544,7 +2544,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, @@ -2552,7 +2552,7 @@ static int adc_regbufregister(struct stm32_adc_dev_s *dev, /* No DMA callback */ - stm32l4_dmastart(priv->dma, NULL, dev, false); + stm32_dmastart(priv->dma, NULL, dev, false); return OK; } @@ -2571,19 +2571,19 @@ static void adc_llops_dma_start(struct stm32_adc_dev_s *adc, if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } - dev->dma = stm32l4_dmachannel(dev->dmachan); + dev->dma = stm32_dmachannel(dev->dmachan); - stm32l4_dmasetup(dev->dma, + stm32_dmasetup(dev->dma, dev->base + STM32_ADC_DR_OFFSET, (uint32_t)buffer, len, ADC_DMA_CONTROL_WORD); - stm32l4_dmastart(dev->dma, callback, dev, false); + stm32_dmastart(dev->dma, callback, dev, false); } /**************************************************************************** @@ -2598,8 +2598,8 @@ static void adc_llops_dma_stop(struct stm32_adc_dev_s *adc) if (dev->dma != NULL) { - stm32l4_dmastop(dev->dma); - stm32l4_dmafree(dev->dma); + stm32_dmastop(dev->dma); + stm32_dmafree(dev->dma); } } @@ -2678,7 +2678,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -2725,9 +2725,8 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) * ****************************************************************************/ -struct adc_dev_s *stm32l4_adc_initialize(int intf, - const uint8_t *chanlist, - int cchannels) +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int cchannels) { struct adc_dev_s *dev; struct stm32_dev_s *priv; diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index 34980e8ccb8..ee261533e98 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -483,13 +483,13 @@ /* IOCTL Commands *********************************************************** * - * Cmd: ANIOC_STM32L4_TRIGGER_REG Arg: - * Cmd: ANIOC_STM32L4_TRIGGER_INJ Arg: + * Cmd: ANIOC_STM32_TRIGGER_REG Arg: + * Cmd: ANIOC_STM32_TRIGGER_INJ Arg: * */ -#define ANIOC_STM32L4_TRIGGER_REG _ANIOC(AN_STM32L4_FIRST + 0) -#define ANIOC_STM32L4_TRIGGER_INJ _ANIOC(AN_STM32L4_FIRST + 1) +#define ANIOC_STM32_TRIGGER_REG _ANIOC(AN_STM32_FIRST + 0) +#define ANIOC_STM32_TRIGGER_INJ _ANIOC(AN_STM32_FIRST + 1) /**************************************************************************** * Public Types @@ -600,7 +600,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_adc_initialize + * Name: stm32_adc_initialize * * Description: * Initialize the ADC. @@ -616,9 +616,8 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_adc_initialize(int intf, - const uint8_t *chanlist, - int nchannels); +struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, + int nchannels); #undef EXTERN #ifdef __cplusplus } @@ -626,4 +625,4 @@ struct adc_dev_s *stm32l4_adc_initialize(int intf, #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ -#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 3669cf0233a..8dce482c8ec 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -241,7 +241,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l4_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -319,7 +319,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ @@ -338,7 +338,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM3 heap */ - stm32l4_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -357,7 +357,7 @@ void arm_addregion(void) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l4_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 2d53c1edba8..1dd36db8d07 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -41,7 +41,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_can.h" #if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) @@ -72,7 +72,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_can_s +struct stm32_can_s { uint8_t port; /* CAN port number (1 or 2) */ uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ @@ -89,20 +89,20 @@ struct stm32l4_can_s /* CAN Register access */ -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset); -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset); -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); #ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg); -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg); #else # define stm32l4can_dumpctrlregs(priv,msg) @@ -113,14 +113,14 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, /* Filtering (todo) */ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg); -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg); #endif -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg); -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg); /* CAN driver methods */ @@ -151,11 +151,11 @@ static int stm32l4can_txinterrupt(int irq, void *context, /* Initialization */ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv); -static int stm32l4can_bittiming(struct stm32l4_can_s *priv); -static int stm32l4can_cellinit(struct stm32l4_can_s *priv); -static int stm32l4can_filterinit(struct stm32l4_can_s *priv); +static int stm32l4can_enterinitmode(struct stm32_can_s *priv); +static int stm32l4can_exitinitmode(struct stm32_can_s *priv); +static int stm32l4can_bittiming(struct stm32_can_s *priv); +static int stm32l4can_cellinit(struct stm32_can_s *priv); +static int stm32l4can_filterinit(struct stm32_can_s *priv); /**************************************************************************** * Private Data @@ -176,7 +176,7 @@ static const struct can_ops_s g_canops = }; #ifdef CONFIG_STM32L4_CAN1 -static struct stm32l4_can_s g_can1priv = +static struct stm32_can_s g_can1priv = { .port = 1, .canrx = @@ -271,24 +271,24 @@ static uint32_t stm32l4can_vgetreg(uint32_t addr) return val; } -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return stm32l4can_vgetreg(priv->fbase + offset); } #else -static uint32_t stm32l4can_getreg(struct stm32l4_can_s *priv, int offset) +static uint32_t stm32l4can_getreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->base + offset); } -static uint32_t stm32l4can_getfreg(struct stm32l4_can_s *priv, +static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, int offset) { return getreg32(priv->fbase + offset); @@ -325,26 +325,26 @@ static void stm32l4can_vputreg(uint32_t addr, uint32_t value) putreg32(value, addr); } -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->base + offset, value); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { stm32l4can_vputreg(priv->fbase + offset, value); } #else -static void stm32l4can_putreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->base + offset); } -static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, +static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value) { putreg32(value, priv->fbase + offset); @@ -366,7 +366,7 @@ static void stm32l4can_putfreg(struct stm32l4_can_s *priv, int offset, ****************************************************************************/ #ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -411,7 +411,7 @@ static void stm32l4can_dumpctrlregs(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { if (msg) @@ -477,7 +477,7 @@ static void stm32l4can_dumpmbregs(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L4_CAN_REGDEBUG -static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, +static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { int i; @@ -526,7 +526,7 @@ static void stm32l4can_dumpfiltregs(struct stm32l4_can_s *priv, static void stm32l4can_reset(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; uint32_t regbit = 0; irqstate_t flags; @@ -583,7 +583,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) static int stm32l4can_setup(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; int ret; caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", @@ -670,7 +670,7 @@ static int stm32l4can_setup(struct can_dev_s *dev) static void stm32l4can_shutdown(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; caninfo("CAN%d\n", priv->port); @@ -707,7 +707,7 @@ static void stm32l4can_shutdown(struct can_dev_s *dev) static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); @@ -743,7 +743,7 @@ static void stm32l4can_rxint(struct can_dev_s *dev, bool enable) static void stm32l4can_txint(struct can_dev_s *dev, bool enable) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; caninfo("CAN%d enable: %d\n", priv->port, enable); @@ -775,7 +775,7 @@ static void stm32l4can_txint(struct can_dev_s *dev, bool enable) static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) { - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; int ret = -ENOTTY; caninfo("cmd=%04x arg=%lu\n", cmd, arg); @@ -1173,7 +1173,7 @@ static int stm32l4can_remoterequest(struct can_dev_s *dev, uint16_t id) static int stm32l4can_send(struct can_dev_s *dev, struct can_msg_s *msg) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint8_t *ptr; uint32_t regval; uint32_t tmp; @@ -1333,7 +1333,7 @@ static int stm32l4can_send(struct can_dev_s *dev, static bool stm32l4can_txready(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if any mailbox is available */ @@ -1364,7 +1364,7 @@ static bool stm32l4can_txready(struct can_dev_s *dev) static bool stm32l4can_txempty(struct can_dev_s *dev) { - struct stm32l4_can_s *priv = dev->cd_priv; + struct stm32_can_s *priv = dev->cd_priv; uint32_t regval; /* Return true if all mailboxes are available */ @@ -1394,7 +1394,7 @@ static bool stm32l4can_txempty(struct can_dev_s *dev) static int stm32l4can_rxinterrupt(int irq, void *context, int rxmb) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; struct can_hdr_s hdr; uint8_t data[CAN_MAXDATALEN]; uint32_t regval; @@ -1552,7 +1552,7 @@ static int stm32l4can_rx1interrupt(int irq, void *context, void *arg) static int stm32l4can_txinterrupt(int irq, void *context, void *arg) { struct can_dev_s *dev = NULL; - struct stm32l4_can_s *priv; + struct stm32_can_s *priv; uint32_t regval; dev = &g_can1dev; @@ -1682,7 +1682,7 @@ static int stm32l4can_txinterrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4can_bittiming(struct stm32l4_can_s *priv) +static int stm32l4can_bittiming(struct stm32_can_s *priv) { uint32_t tmp; uint32_t brp; @@ -1782,7 +1782,7 @@ static int stm32l4can_bittiming(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_enterinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; @@ -1833,7 +1833,7 @@ static int stm32l4can_enterinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) +static int stm32l4can_exitinitmode(struct stm32_can_s *priv) { uint32_t regval; volatile uint32_t timeout; @@ -1884,7 +1884,7 @@ static int stm32l4can_exitinitmode(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_cellinit(struct stm32l4_can_s *priv) +static int stm32l4can_cellinit(struct stm32_can_s *priv) { uint32_t regval; int ret; @@ -1962,7 +1962,7 @@ static int stm32l4can_cellinit(struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_filterinit(struct stm32l4_can_s *priv) +static int stm32l4can_filterinit(struct stm32_can_s *priv) { uint32_t regval; uint32_t bitmask; @@ -2042,7 +2042,7 @@ static int stm32l4can_filterinit(struct stm32l4_can_s *priv) ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addextfilter(struct stm32_can_s *priv, struct canioc_extfilter_s *arg) { return -ENOTTY; @@ -2068,7 +2068,7 @@ static int stm32l4can_addextfilter(struct stm32l4_can_s *priv, ****************************************************************************/ #ifdef CONFIG_CAN_EXTID -static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delextfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2091,7 +2091,7 @@ static int stm32l4can_delextfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, +static int stm32l4can_addstdfilter(struct stm32_can_s *priv, struct canioc_stdfilter_s *arg) { return -ENOTTY; @@ -2115,7 +2115,7 @@ static int stm32l4can_addstdfilter(struct stm32l4_can_s *priv, * ****************************************************************************/ -static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delstdfilter(struct stm32_can_s *priv, int arg) { return -ENOTTY; } @@ -2125,7 +2125,7 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -2138,14 +2138,14 @@ static int stm32l4can_delstdfilter(struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -struct can_dev_s *stm32l4can_initialize(int port) +struct can_dev_s *stm32_caninitialize(int port) { struct can_dev_s *dev = NULL; caninfo("CAN%d\n", port); /* NOTE: Peripherical clocking for CAN1 and/or CAN2 was already provided - * by stm32l4_clockconfig() early in the reset sequence. + * by stm32_clockconfig() early in the reset sequence. */ #ifdef CONFIG_STM32L4_CAN1 @@ -2159,8 +2159,8 @@ struct can_dev_s *stm32l4can_initialize(int port) * file must have been disambiguated in the board.h file. */ - stm32l4_configgpio(GPIO_CAN1_RX); - stm32l4_configgpio(GPIO_CAN1_TX); + stm32_configgpio(GPIO_CAN1_RX); + stm32_configgpio(GPIO_CAN1_TX); } else #endif diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 2a33a504bf3..11174fd1a24 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -101,7 +101,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4can_initialize + * Name: stm32_caninitialize * * Description: * Initialize the selected CAN port @@ -115,7 +115,7 @@ extern "C" ****************************************************************************/ struct can_dev_s; -struct can_dev_s *stm32l4can_initialize(int port); +struct can_dev_s *stm32_caninitialize(int port); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index a2af78f8421..6271db60ac6 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -66,12 +66,11 @@ /* COMP Register access */ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits); -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg); -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, - bool en); -static int stm32l4_compconfig(const struct comp_dev_s *dev); +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg); +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en); +static int stm32_compconfig(const struct comp_dev_s *dev); /* COMP Driver Methods */ @@ -96,7 +95,7 @@ static const struct comp_ops_s g_compops = .ao_bind = comp_bind, }; -static struct stm32l4_comp_config_s g_comp1priv = +static struct stm32_comp_config_s g_comp1priv = { .interrupt = { @@ -118,7 +117,7 @@ static struct comp_dev_s g_comp1dev = .ad_priv = &g_comp1priv, }; -static struct stm32l4_comp_config_s g_comp2priv = +static struct stm32_comp_config_s g_comp2priv = { .interrupt = { @@ -148,7 +147,7 @@ static struct comp_dev_s g_comp2dev = * Name: modify_csr ****************************************************************************/ -static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, +static inline void modify_csr(const struct stm32_comp_config_s *cfg, uint32_t clearbits, uint32_t setbits) { modifyreg32(cfg->csr, clearbits, setbits); @@ -158,7 +157,7 @@ static inline void modify_csr(const struct stm32l4_comp_config_s *cfg, * Name: get_csr ****************************************************************************/ -static inline uint32_t get_csr(const struct stm32l4_comp_config_s *cfg) +static inline uint32_t get_csr(const struct stm32_comp_config_s *cfg) { return getreg32(cfg->csr); } @@ -184,7 +183,7 @@ static int comp_setup(struct comp_dev_s *dev) /* Configure selected comparator */ - ret = stm32l4_compconfig(dev); + ret = stm32_compconfig(dev); if (ret < 0) { aerr("ERROR: Failed to initialize COMP: %d\n", ret); @@ -212,10 +211,10 @@ static int comp_setup(struct comp_dev_s *dev) static void comp_shutdown(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; cfg = dev->ad_priv; - stm32l4_compenable(cfg, false); + stm32_compenable(cfg, false); } /**************************************************************************** @@ -235,7 +234,7 @@ static void comp_shutdown(struct comp_dev_s *dev) static int comp_read(struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval; cfg = dev->ad_priv; @@ -283,8 +282,8 @@ static int comp_ioctl(struct comp_dev_s *dev, int cmd, unsigned long arg) static int comp_bind(struct comp_dev_s *dev, const struct comp_callback_s *callback) { - struct stm32l4_comp_config_s *priv = - (struct stm32l4_comp_config_s *)dev->ad_priv; + struct stm32_comp_config_s *priv = + (struct stm32_comp_config_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); priv->interrupt.cb = callback; @@ -296,7 +295,7 @@ static int comp_bind(struct comp_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_compenable + * Name: stm32_compenable * * Description: * Enable/disable comparator @@ -307,8 +306,7 @@ static int comp_bind(struct comp_dev_s *dev, * ****************************************************************************/ -static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, - bool en) +static void stm32_compenable(struct stm32_comp_config_s *cfg, bool en) { uint32_t clearbits = en ? 0 : COMP_CSR_EN; uint32_t setbits = en ? COMP_CSR_EN : 0; @@ -316,10 +314,10 @@ static void stm32l4_compenable(struct stm32l4_comp_config_s *cfg, modify_csr(cfg, clearbits, setbits); } -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { struct comp_dev_s *dev = (struct comp_dev_s *)arg; - struct stm32l4_comp_config_s *cfg = dev->ad_priv; + struct stm32_comp_config_s *cfg = dev->ad_priv; DEBUGASSERT(cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)); @@ -332,7 +330,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_compconfig + * Name: stm32_compconfig * * Description: * Configure comparator and I/Os used as comparators inputs @@ -345,9 +343,9 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_compconfig(const struct comp_dev_s *dev) +static int stm32_compconfig(const struct comp_dev_s *dev) { - struct stm32l4_comp_config_s *cfg; + struct stm32_comp_config_s *cfg; uint32_t regval = 0; uint32_t mask = 0; uint32_t clearbits; @@ -364,20 +362,20 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) switch (cfg->inp) { case STM32_COMP_INP_PIN_1: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_1 : GPIO_COMP2_INP_1); regval |= COMP_CSR_INPSEL_PIN1; break; case STM32_COMP_INP_PIN_2: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_2 : GPIO_COMP2_INP_2); regval |= COMP_CSR_INPSEL_PIN2; break; #if defined(CONFIG_STM32L4_STM32L4X3) case STM32_COMP_INP_PIN_3: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); regval |= COMP_CSR_INPSEL_PIN3; break; @@ -425,13 +423,13 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_1: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_1 : GPIO_COMP2_INM_1); regval |= COMP_CSR_INMSEL_PIN1; break; case STM32_COMP_INM_PIN_2: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); #if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ defined(CONFIG_STM32L4_STM32L4XR) @@ -445,7 +443,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) #if defined(CONFIG_STM32L4_STM32L4X3) case STM32_COMP_INM_PIN_3: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -453,7 +451,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_4: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_4 : GPIO_COMP2_INM_4); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -461,7 +459,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) break; case STM32_COMP_INM_PIN_5: - stm32l4_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : + stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_5 : GPIO_COMP2_INM_5); regval |= COMP_CSR_INMSEL_INMESEL; mask |= COMP_CSR_INMESEL_MASK; @@ -539,18 +537,18 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) /* Enable */ - stm32l4_compenable(cfg, true); + stm32_compenable(cfg, true); /* Enable interrupt */ if (cfg->interrupt.cb && (cfg->interrupt.rising || cfg->interrupt.falling)) { - ret = stm32l4_exti_comp(cmp, cfg->interrupt.rising, + ret = stm32_exti_comp(cmp, cfg->interrupt.rising, cfg->interrupt.falling, 0, - stm32l4_exti_comp_isr, (void *)dev); + stm32_exti_comp_isr, (void *)dev); if (ret < 0) { - aerr("stm32l4_exti_comp failed ret = %d\n", ret); + aerr("stm32_exti_comp failed ret = %d\n", ret); return ERROR; } } @@ -561,7 +559,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -579,8 +577,7 @@ static int stm32l4_compconfig(const struct comp_dev_s *dev) ****************************************************************************/ struct comp_dev_s * - stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg) +stm32_compinitialize(int intf, const struct stm32_comp_config_s *cfg) { struct comp_dev_s *dev; diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index 0414ed9f774..02f92d4c9c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -54,7 +54,7 @@ /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { STM32_COMP1, STM32_COMP2, @@ -63,7 +63,7 @@ enum stm32l4_comp_e /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ STM32_COMP_INP_PIN_2, /* COMP1: PB2, COMP2: PB6 */ @@ -72,7 +72,7 @@ enum stm32l4_comp_inp_e /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { STM32_COMP_INM_1_4_VREF, STM32_COMP_INM_1_2_VREF, @@ -91,7 +91,7 @@ enum stm32l4_comp_inm_e /* Comparators */ -enum stm32l4_comp_e +enum stm32_comp_e { STM32_COMP1, STM32_COMP2, @@ -100,7 +100,7 @@ enum stm32l4_comp_e /* Plus input */ -enum stm32l4_comp_inp_e +enum stm32_comp_inp_e { STM32_COMP_INP_PIN_1, /* COMP1: PC5, COMP2: PB4 */ STM32_COMP_INP_PIN_2 /* COMP1: PB2, COMP2: PB6 */ @@ -108,7 +108,7 @@ enum stm32l4_comp_inp_e /* Minus input */ -enum stm32l4_comp_inm_e +enum stm32_comp_inm_e { STM32_COMP_INM_1_4_VREF, STM32_COMP_INM_1_2_VREF, @@ -123,7 +123,7 @@ enum stm32l4_comp_inm_e /* Hysteresis */ -enum stm32l4_comp_hyst_e +enum stm32_comp_hyst_e { STM32_COMP_HYST_NONE, STM32_COMP_HYST_LOW, @@ -133,7 +133,7 @@ enum stm32l4_comp_hyst_e /* Power/Speed Modes */ -enum stm32l4_comp_speed_e +enum stm32_comp_speed_e { STM32_COMP_SPEED_HIGH, STM32_COMP_SPEED_MEDIUM, @@ -142,7 +142,7 @@ enum stm32l4_comp_speed_e /* Comparator configuration *************************************************/ -struct stm32l4_comp_config_s +struct stm32_comp_config_s { struct { @@ -151,10 +151,10 @@ struct stm32l4_comp_config_s bool falling; } interrupt; - uint8_t inp; /* Plus input pin (see enum stm32l4_comp_inp_e) */ - uint8_t inm; /* Minus input pin (see enum stm32l4_comp_inm_e) */ - uint8_t hyst; /* Hysteresis (see enum stm32l4_comp_hyst_e) */ - uint8_t speed; /* Speed (see stm32l4_comp_speed_e) */ + uint8_t inp; /* Plus input pin (see enum stm32_comp_inp_e) */ + uint8_t inm; /* Minus input pin (see enum stm32_comp_inm_e) */ + uint8_t hyst; /* Hysteresis (see enum stm32_comp_hyst_e) */ + uint8_t speed; /* Speed (see stm32_comp_speed_e) */ bool inverted; /* Invert output? */ uint32_t csr; /* Control and status register */ }; @@ -173,7 +173,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_compinitialize + * Name: stm32_compinitialize * * Description: * Initialize the COMP. @@ -191,9 +191,8 @@ extern "C" * ****************************************************************************/ -struct -comp_dev_s *stm32l4_compinitialize(int intf, - const struct stm32l4_comp_config_s *cfg); +struct comp_dev_s * +stm32_compinitialize(int intf, const struct stm32_comp_config_s *cfg); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index a529515e70e..7b1bd5b0e0a 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -40,7 +40,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_dac.h" #include "stm32l4_rcc.h" #include "stm32l4_dma.h" @@ -408,7 +408,7 @@ static const struct stm32_dac_ops_s g_dac_llops = /* Channel 1 */ #ifdef CONFIG_STM32L4_DAC1_DMA -uint16_t stm32l4_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE]; +uint16_t stm32_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac1priv = @@ -428,7 +428,7 @@ static struct stm32_chan_s g_dac1priv = .hasdma = 1, .dmachan = DAC1_DMA_CHAN, .buffer_len = CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac1_dmabuffer, + .dmabuffer = stm32_dac1_dmabuffer, .timer = CONFIG_STM32L4_DAC1_TIMER, .tsel = DAC1_TSEL_VALUE, .tbase = DAC1_TIMER_BASE, @@ -448,7 +448,7 @@ static struct dac_dev_s g_dac1dev = /* Channel 2 */ #ifdef CONFIG_STM32L4_DAC2_DMA -uint16_t stm32l4_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE]; +uint16_t stm32_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac2priv = @@ -468,7 +468,7 @@ static struct stm32_chan_s g_dac2priv = .hasdma = 1, .dmachan = DAC2_DMA_CHAN, .buffer_len = CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE, - .dmabuffer = stm32l4_dac2_dmabuffer, + .dmabuffer = stm32_dac2_dmabuffer, .timer = CONFIG_STM32L4_DAC2_TIMER, .tsel = DAC2_TSEL_VALUE, .tbase = DAC2_TIMER_BASE, @@ -511,7 +511,7 @@ static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) } /**************************************************************************** - * Name: stm32l4_dac_modify_cr + * Name: stm32_dac_modify_cr * * Description: * Modify the contents of the DAC control register. @@ -526,7 +526,7 @@ static uint32_t dac_getreg(struct stm32_chan_s *priv, int offset) * ****************************************************************************/ -static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, +static inline void stm32_dac_modify_cr(struct stm32_chan_s *chan, uint32_t clearbits, uint32_t setbits) { @@ -546,7 +546,7 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, } /**************************************************************************** - * Name: stm32l4_dac_modify_mcr + * Name: stm32_dac_modify_mcr * * Description: * Modify the contents of the DAC mode register. @@ -561,9 +561,9 @@ static inline void stm32l4_dac_modify_cr(struct stm32_chan_s *chan, * ****************************************************************************/ -static inline void stm32l4_dac_modify_mcr(struct stm32_chan_s *chan, - uint32_t clearbits, - uint32_t setbits) +static inline void stm32_dac_modify_mcr(struct stm32_chan_s *chan, + uint32_t clearbits, + uint32_t setbits) { unsigned int shift; @@ -807,7 +807,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Enable DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_EN); + stm32_dac_modify_cr(chan, 0, DAC_CR_EN); #ifdef HAVE_DMA if (chan->hasdma) @@ -843,17 +843,17 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) * - Peripheral Burst: single */ - stm32l4_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, + stm32_dmasetup(chan->dma, chan->dro, (uint32_t)chan->dmabuffer, chan->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ chan->result = -EBUSY; - stm32l4_dmastart(chan->dma, dac_dmatxcallback, chan, false); + stm32_dmastart(chan->dma, dac_dmatxcallback, chan, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_DMAEN); } else #endif @@ -1098,7 +1098,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (chan->pin != 0xffffffffu) { - stm32l4_configgpio(chan->pin); + stm32_configgpio(chan->pin); } /* DAC channel configuration: @@ -1110,7 +1110,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Disable before change */ - stm32l4_dac_modify_cr(chan, DAC_CR_EN, 0); + stm32_dac_modify_cr(chan, DAC_CR_EN, 0); clearbits = DAC_CR_TSEL_MASK | DAC_CR_MAMP_MASK | @@ -1119,7 +1119,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) chan->tsel | /* Set trigger source (SW or timer TRGO event) */ DAC_CR_MAMP_AMP1 | /* Set waveform characteristics */ DAC_CR_WAVE_DISABLED; /* Set no noise */ - stm32l4_dac_modify_cr(chan, clearbits, setbits); + stm32_dac_modify_cr(chan, clearbits, setbits); /* Enable output buffer or route DAC output to on-chip peripherals (ADC) */ @@ -1133,7 +1133,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) setbits = DAC_MCR_MODE_IN; } - stm32l4_dac_modify_mcr(chan, clearbits, setbits); + stm32_dac_modify_mcr(chan, clearbits, setbits); #ifdef HAVE_DMA /* Determine if DMA is supported by this channel */ @@ -1144,11 +1144,11 @@ static int dac_chaninit(struct stm32_chan_s *chan) /* Yes.. DAC trigger enable */ - stm32l4_dac_modify_cr(chan, 0, DAC_CR_TEN); + stm32_dac_modify_cr(chan, 0, DAC_CR_TEN); /* Allocate a DMA channel */ - chan->dma = stm32l4_dmachannel(chan->dmachan); + chan->dma = stm32_dmachannel(chan->dmachan); if (!chan->dma) { aerr("ERROR: Failed to allocate a DMA channel\n"); @@ -1161,7 +1161,7 @@ static int dac_chaninit(struct stm32_chan_s *chan) if (ret < 0) { aerr("ERROR: Failed to initialize the DMA timer: %d\n", ret); - stm32l4_dmafree(chan->dma); + stm32_dmafree(chan->dma); return ret; } } @@ -1229,11 +1229,11 @@ static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled) if (enabled) { - stm32l4_dac_modify_cr(priv, 0, DAC_CR_EN); + stm32_dac_modify_cr(priv, 0, DAC_CR_EN); } else { - stm32l4_dac_modify_cr(priv, DAC_CR_EN, 0); + stm32_dac_modify_cr(priv, DAC_CR_EN, 0); } } @@ -1272,17 +1272,17 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev) * - Peripheral Burst: single */ - stm32l4_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, + stm32_dmasetup(priv->dma, priv->dro, (uint32_t)priv->dmabuffer, priv->buffer_len, DAC_DMA_CONTROL_WORD); /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dma, dac_dmatxcallback, priv, false); + stm32_dmastart(priv->dma, dac_dmatxcallback, priv, false); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); /* Reset counters (generate an update) */ @@ -1300,11 +1300,11 @@ static void dac_llops_stopdma(struct stm32_dac_dev_s *dev) /* Stop the DMA */ priv->result = -EBUSY; - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); /* Enable DMA for DAC Channel */ - stm32l4_dac_modify_cr(priv, 0, DAC_CR_DMAEN); + stm32_dac_modify_cr(priv, 0, DAC_CR_DMAEN); } #endif @@ -1326,7 +1326,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC. @@ -1343,7 +1343,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) * ****************************************************************************/ -struct dac_dev_s *stm32l4_dacinitialize(int intf) +struct dac_dev_s *stm32_dacinitialize(int intf) { struct dac_dev_s *dev; struct stm32_chan_s *chan; diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h index 6bf30f75ab4..144edea439a 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/stm32l4_dac.h @@ -144,10 +144,10 @@ struct stm32_dac_ops_s ****************************************************************************/ #ifdef CONFIG_STM32L4_DAC1_DMA -extern uint16_t stm32l4_dac1_dmabuffer[]; +extern uint16_t stm32_dac1_dmabuffer[]; #endif #ifdef CONFIG_STM32L4_DAC2_DMA -extern uint16_t stm32l4_dac2_dmabuffer[]; +extern uint16_t stm32_dac2_dmabuffer[]; #endif /**************************************************************************** @@ -164,7 +164,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dacinitialize + * Name: stm32_dacinitialize * * Description: * Initialize the DAC @@ -178,7 +178,7 @@ extern "C" ****************************************************************************/ struct dac_dev_s; -struct dac_dev_s *stm32l4_dacinitialize(int intf); +struct dac_dev_s *stm32_dacinitialize(int intf); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index 451f8050480..ef79acc58da 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -1204,19 +1204,19 @@ static int dfsdm_setup(struct adc_dev_s *dev) if (priv->dma != NULL) { - stm32l4_dmastop(priv->dma); - stm32l4_dmafree(priv->dma); + stm32_dmastop(priv->dma); + stm32_dmafree(priv->dma); } - priv->dma = stm32l4_dmachannel(priv->dmachan); + priv->dma = stm32_dmachannel(priv->dmachan); - stm32l4_dmasetup(priv->dma, + stm32_dmasetup(priv->dma, priv->base + FLTRDATAR_OFFSET(priv), (uint32_t)priv->dmabuffer, priv->nchannels, DFSDM_DMA_CONTROL_WORD); - stm32l4_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); + stm32_dmastart(priv->dma, dfsdm_dmaconvcallback, dev, false); } #endif @@ -1735,7 +1735,7 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -1750,9 +1750,8 @@ static void dfsdm_dmaconvcallback(DMA_HANDLE handle, * ****************************************************************************/ -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, - const uint8_t *chanlist, - int cchannels) +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, + int cchannels) { struct adc_dev_s *dev; struct stm32_dev_s *priv; diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 5e763736b20..82395d4c767 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -306,7 +306,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_dfsdm_initialize + * Name: stm32_dfsdm_initialize * * Description: * Initialize the DFSDM. @@ -322,9 +322,8 @@ extern "C" ****************************************************************************/ struct adc_dev_s; -struct adc_dev_s *stm32l4_dfsdm_initialize(int intf, - const uint8_t *chanlist, - int nchannels); +struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, + int nchannels); #undef EXTERN #ifdef __cplusplus } diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 19c87426f6c..8f2db0fba1b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -120,7 +120,7 @@ static inline void apb_reset(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode (GCC only). @@ -128,7 +128,7 @@ static inline void apb_reset(void) ****************************************************************************/ #if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) -void stm32l4_dfumode(void) +void stm32_dfumode(void) { uint32_t regval; boot_call_t boot; diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.h b/arch/arm/src/stm32l4/stm32l4_dfumode.h index 67cd03b0db0..c27e1887717 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.h +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dfumode + * Name: stm32_dfumode * * Description: * Reboot the part in DFU mode. @@ -42,7 +42,7 @@ ****************************************************************************/ #if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) -void stm32l4_dfumode(void) noreturn_function; +void stm32_dfumode(void) noreturn_function; #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFUMODE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 5044edb200b..2d7a3aa548c 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -77,13 +77,13 @@ typedef void *DMA_HANDLE; * status - A bit encoded value that provides the completion status. See * the DMASTATUS_* definitions above. * arg - A user-provided value that was provided when - * stm32l4_dmastart() was called. + * stm32_dmastart() was called. */ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32l4_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ @@ -130,7 +130,7 @@ extern "C" defined(CONFIG_STM32L4_STM32L4X6) /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -139,11 +139,11 @@ extern "C" * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will + * If the DMA channel is not available, then stm32_dmachannel() will * wait until the holder of the channel relinquishes the channel by - * calling stm32l4_dmafree(). WARNING: If you have two devices sharing a + * calling stm32_dmafree(). WARNING: If you have two devices sharing a * DMA channel and the code never releases the channel, the - * stm32l4_dmachannel call for the other will hang forever in this + * stm32_dmachannel call for the other will hang forever in this * function! Don't let your design do that! * * Hmm.. I suppose this interface could be extended to make a non-blocking @@ -166,7 +166,7 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chan); +DMA_HANDLE stm32_dmachannel(unsigned int chan); #elif defined(CONFIG_STM32L4_STM32L4XR) @@ -195,20 +195,20 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chan); * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); #endif /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32l4_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -220,64 +220,64 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -292,44 +292,44 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32l4_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32l4_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32l4_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c index 48d4cace763..96b483ff201 100644 --- a/arch/arm/src/stm32l4/stm32l4_dumpgpio.c +++ b/arch/arm/src/stm32l4/stm32l4_dumpgpio.c @@ -86,14 +86,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l4_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 212fab58d31..3b660bafe10 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32L4_COMP -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c index 2ad3d44cde5..34f26326050 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_alarm.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_alarm.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -83,7 +83,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -109,7 +109,7 @@ int stm32l4_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32l4_exti_alarm_isr, NULL); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index 35fd4128668..f7508e387fd 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -83,7 +83,7 @@ static const uint32_t g_comp_lines[STM32_COMP_NUM] = * Private Functions ****************************************************************************/ -static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) +static int stm32_exti_comp_isr(int irq, void *context, void *arg) { uint32_t pr; uint32_t ln; @@ -118,7 +118,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -136,7 +136,7 @@ static int stm32l4_exti_comp_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { irqstate_t flags; @@ -152,7 +152,7 @@ int stm32l4_exti_comp(int cmp, bool risingedge, bool fallingedge, if (func != NULL) { - irq_attach(STM32_IRQ_COMP, stm32l4_exti_comp_isr, NULL); + irq_attach(STM32_IRQ_COMP, stm32_exti_comp_isr, NULL); up_enable_irq(STM32_IRQ_COMP); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c index 767bffb83ca..1418d7c75d6 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_gpio.c @@ -66,7 +66,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32l4_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -87,7 +87,7 @@ static int stm32l4_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -108,7 +108,7 @@ static int stm32l4_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -129,7 +129,7 @@ static int stm32l4_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -150,7 +150,7 @@ static int stm32l4_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -171,7 +171,7 @@ static int stm32l4_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32l4_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -215,14 +215,14 @@ static int stm32l4_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32l4_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32l4_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32l4_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,7 +252,7 @@ static int stm32l4_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -273,37 +273,37 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32l4_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32l4_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32l4_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32l4_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32l4_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32l4_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32l4_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,7 +349,7 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l4_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c index 854df35b913..01a6dd882f8 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.c @@ -58,14 +58,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -88,7 +88,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -104,7 +104,7 @@ static int stm32l4_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -116,7 +116,7 @@ int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_PVD, stm32l4_exti_pvd_isr, NULL); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h index a9d6b3f0ec0..72607feec2c 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_exti_pwr.h @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -52,7 +52,7 @@ * ****************************************************************************/ -int stm32l4_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /* STM32L4_EXTI_PWR_H_ */ diff --git a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c index 2bcf7b22ef3..dd0c8b7d440 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_wakeup.c @@ -53,14 +53,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -83,7 +83,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -99,7 +99,7 @@ static int stm32l4_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -109,7 +109,7 @@ int stm32l4_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTC_WKUP, stm32l4_exti_wakeup_isr, NULL); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); } else diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.c b/arch/arm/src/stm32l4/stm32l4_firewall.c index c4597da0e98..2a427efb118 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.c +++ b/arch/arm/src/stm32l4/stm32l4_firewall.c @@ -39,7 +39,7 @@ * Public Functions ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup) +int stm32_firewallsetup(struct stm32_firewall_t *setup) { uint32_t reg; diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 6e69bddca2e..48eb504d41b 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -52,7 +52,7 @@ * Public Types ****************************************************************************/ -struct stm32l4_firewall_t +struct stm32_firewall_t { uintptr_t codestart; size_t codelen; @@ -84,7 +84,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_firewallsetup + * Name: stm32_firewallsetup * * Description: * Configure the STM32L4 firewall. After this, protected code will only @@ -95,7 +95,7 @@ extern "C" * ****************************************************************************/ -int stm32l4_firewallsetup(struct stm32l4_firewall_t *setup); +int stm32_firewallsetup(struct stm32_firewall_t *setup); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index 914e213005a..46736f121a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -106,7 +106,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -174,7 +174,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -202,7 +202,7 @@ static void data_cache_enable(void) * Public Functions ****************************************************************************/ -int stm32l4_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -218,7 +218,7 @@ int stm32l4_flash_unlock(void) return ret; } -int stm32l4_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -235,7 +235,7 @@ int stm32l4_flash_lock(void) } /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -251,7 +251,7 @@ int stm32l4_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -289,7 +289,7 @@ uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -508,7 +508,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32l4_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32l4/stm32l4_flash.h b/arch/arm/src/stm32l4/stm32l4_flash.h index 89cf22190fa..3acc0d160b5 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/stm32l4_flash.h @@ -34,11 +34,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32l4_flash_lock(void); -int stm32l4_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l4_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ int stm32l4_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l4_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 37f2a2b8c9f..29aedb4864c 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -44,7 +44,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -61,10 +61,10 @@ * ****************************************************************************/ -static int stm32l4_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32l4_freerun_s *freerun = - (struct stm32l4_freerun_s *)arg; + struct stm32_freerun_s *freerun = + (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; @@ -78,7 +78,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -96,7 +96,7 @@ static int stm32l4_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { @@ -110,7 +110,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32l4_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -128,7 +128,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(freerun->tch, stm32l4_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); /* Set timer period */ @@ -144,7 +144,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, } /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -152,7 +152,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -162,7 +162,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -176,7 +176,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32l4_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -238,7 +238,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, } /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -246,7 +246,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -254,7 +254,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); @@ -266,7 +266,7 @@ int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun) /* Free the timer */ - stm32l4_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index 21ce87d2628..4f99980e27d 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -42,16 +42,16 @@ ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32l4_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since the * contents are subject to change. */ -struct stm32l4_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint32_t overflow; /* Timer counter overflow */ - struct stm32l4_tim_dev_s *tch; /* Handle returned by stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ uint32_t frequency; }; @@ -73,7 +73,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -91,11 +91,11 @@ extern "C" * ****************************************************************************/ -int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -103,7 +103,7 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -113,11 +113,11 @@ int stm32l4_freerun_initialize(struct stm32l4_freerun_s *freerun, int chan, * ****************************************************************************/ -int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); /**************************************************************************** - * Name: stm32l4_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -125,7 +125,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32l4_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -133,7 +133,7 @@ int stm32l4_freerun_counter(struct stm32l4_freerun_s *freerun, * ****************************************************************************/ -int stm32l4_freerun_uninitialize(struct stm32l4_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 228dec79877..cfe12286031 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -94,13 +94,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -108,17 +108,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32l4_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -129,7 +129,7 @@ void stm32l4_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -177,7 +177,7 @@ int stm32l4_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l4_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -364,7 +364,7 @@ int stm32l4_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -384,7 +384,7 @@ int stm32l4_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -393,18 +393,18 @@ int stm32l4_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l4_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -438,14 +438,14 @@ void stm32l4_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 4969756362b..13e321fc0d4 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -50,7 +50,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l4_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -251,12 +251,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l4_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative * function. * @@ -266,10 +266,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32l4_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -288,30 +288,30 @@ int stm32l4_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l4_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l4_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l4_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l4_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l4_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l4_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -330,11 +330,11 @@ bool stm32l4_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l4_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -342,23 +342,23 @@ int stm32l4_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l4_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l4_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l4_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l4_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l4_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.c b/arch/arm/src/stm32l4/stm32l4_hsi48.c index e34c588f6a1..65716843cb1 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.c +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -64,7 +64,7 @@ * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) +void stm32_enable_hsi48(enum syncsrc_e syncsrc) { uint32_t regval; @@ -133,7 +133,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) } /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -146,7 +146,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc) * ****************************************************************************/ -void stm32l4_disable_hsi48(void) +void stm32_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index 4028f5a2bbc..f9636dce34d 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -48,7 +48,7 @@ enum syncsrc_e ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enable_hsi48 + * Name: stm32_enable_hsi48 * * Description: * On STM32L4X3, STM32L496xx/4A6xx and STM32L4XR devices only, the HSI48 @@ -74,10 +74,10 @@ enum syncsrc_e * ****************************************************************************/ -void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); +void stm32_enable_hsi48(enum syncsrc_e syncsrc); /**************************************************************************** - * Name: stm32l4_disable_hsi48 + * Name: stm32_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -90,7 +90,7 @@ void stm32l4_enable_hsi48(enum syncsrc_e syncsrc); * ****************************************************************************/ -void stm32l4_disable_hsi48(void); +void stm32_disable_hsi48(void); #endif /* CONFIG_STM32L4_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 4e42d3beb51..91a1ca0bc41 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -328,10 +328,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32l4_i2c_tracereset(p) -# define stm32l4_i2c_tracenew(p,s) -# define stm32l4_i2c_traceevent(p,e,a) -# define stm32l4_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -344,7 +344,7 @@ /* Interrupt state */ -enum stm32l4_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -353,7 +353,7 @@ enum stm32l4_intstate_e /* Trace events */ -enum stm32l4_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -381,18 +381,18 @@ enum stm32l4_trace_e /* Trace data */ -struct stm32l4_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32l4_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32l4_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -407,18 +407,18 @@ struct stm32l4_i2c_config_s /* I2C Device Private Data */ -struct stm32l4_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32l4_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32l4_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -436,7 +436,7 @@ struct stm32l4_i2c_priv_s /* The actual trace data */ - struct stm32l4_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -448,10 +448,10 @@ struct stm32l4_i2c_priv_s /* I2C Device, Instance */ -struct stm32l4_i2c_inst_s +struct stm32_i2c_inst_s { const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32l4_i2c_priv_s *priv; /* Common driver private data structure */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -459,57 +459,57 @@ struct stm32l4_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_STM32L4_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); #endif /* CONFIG_STM32L4_I2C_DYNTIMEO */ static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv); -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm); -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv); -static inline void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv); -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -518,7 +518,7 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_STM32L4_I2C1 -static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = +static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, @@ -531,9 +531,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c1_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32l4_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -548,13 +548,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32L4_I2C2 -static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = +static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, .clk_bit = RCC_APB1ENR1_I2C2EN, @@ -567,9 +567,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c2_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = +static struct stm32_i2c_priv_s stm32_i2c2_priv = { - .config = &stm32l4_i2c2_config, + .config = &stm32_i2c2_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -584,13 +584,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c2_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32L4_I2C3 -static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = +static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, @@ -603,9 +603,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c3_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32l4_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -620,13 +620,13 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32L4_I2C4 -static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = +static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, .clk_bit = RCC_APB1ENR2_I2C4EN, @@ -639,9 +639,9 @@ static const struct stm32l4_i2c_config_s stm32l4_i2c4_config = #endif }; -static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = +static struct stm32_i2c_priv_s stm32_i2c4_priv = { - .config = &stm32l4_i2c4_config, + .config = &stm32_i2c4_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -656,18 +656,18 @@ static struct stm32l4_i2c_priv_s stm32l4_i2c4_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32l4_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32l4_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32l4_i2c_transfer + .transfer = stm32_i2c_transfer #ifdef CONFIG_I2C_RESET - , .reset = stm32l4_i2c_reset + , .reset = stm32_i2c_reset #endif }; @@ -676,7 +676,7 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -684,14 +684,14 @@ static const struct i2c_ops_s stm32l4_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -699,42 +699,42 @@ uint16_t stm32l4_i2c_getreg(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getreg32(struct stm32l4_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -742,7 +742,7 @@ static inline void stm32l4_i2c_putreg32(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -750,7 +750,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -759,7 +759,7 @@ void stm32l4_i2c_modifyreg32(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L4_I2C_DYNTIMEO -static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -780,7 +780,7 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #endif /**************************************************************************** - * Name: stm32l4_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -789,15 +789,15 @@ static uint32_t stm32l4_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32l4_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -809,7 +809,7 @@ void stm32l4_i2c_enableinterrupts(struct stm32l4_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -819,11 +819,11 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32l4_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -835,7 +835,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) #ifdef CONFIG_STM32L4_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32l4_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, CONFIG_STM32L4_I2CTIMEOTICKS); @@ -861,14 +861,14 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -878,7 +878,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) /* Get the timeout value */ #ifdef CONFIG_STM32L4_I2C_DYNTIMEO - timeout = stm32l4_i2c_toticks(priv->msgc, priv->msgv); + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else timeout = CONFIG_STM32L4_I2CTIMEOTICKS; #endif @@ -901,7 +901,7 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) * reports that it is done. */ - stm32l4_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -921,91 +921,91 @@ int stm32l4_i2c_sem_waitdone(struct stm32l4_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32l4_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_7bit_address(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, ((priv->msgv->addr & 0x7f) << I2C_CR2_SADD7_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_bytes_to_transfer(struct stm32l4_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32l4_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_write_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32l4_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_set_read_transfer_dir(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32l4_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_enable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32l4_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32l4_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -1013,7 +1013,7 @@ stm32l4_i2c_disable_reload(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -1040,7 +1040,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -1048,7 +1048,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { return; @@ -1067,7 +1067,7 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32l4_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -1075,9 +1075,9 @@ void stm32l4_i2c_sem_waitstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -1086,19 +1086,19 @@ static void stm32l4_i2c_traceclear(struct stm32l4_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32l4_i2c_tracereset(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32l4_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -1124,7 +1124,7 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -1137,10 +1137,10 @@ static void stm32l4_i2c_tracenew(struct stm32l4_i2c_priv_s *priv, } } -static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, - enum stm32l4_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1160,13 +1160,13 @@ static void stm32l4_i2c_traceevent(struct stm32l4_i2c_priv_s *priv, } priv->tndx++; - stm32l4_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32l4_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1185,7 +1185,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32l4_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1237,7 +1237,7 @@ static void stm32l4_i2c_tracedump(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { int i2cclk_mhz; @@ -1252,11 +1252,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = (stm32l4_i2c_getreg32(priv, + pe = (stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } @@ -1454,11 +1454,11 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, (scl_h_period << I2C_TIMINGR_SCLH_SHIFT) | (scl_l_period << I2C_TIMINGR_SCLL_SHIFT); - stm32l4_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1467,7 +1467,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32l4_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1494,7 +1494,7 @@ static void stm32l4_i2c_setclock(struct stm32l4_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1556,13 +1556,13 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1572,18 +1572,18 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32l4_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1591,11 +1591,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32l4_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32l4_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1605,11 +1605,11 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32l4_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1621,17 +1621,17 @@ void stm32l4_i2c_sendstart(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32l4_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1639,13 +1639,13 @@ void stm32l4_i2c_sendstop(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32l4_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1653,14 +1653,14 @@ uint32_t stm32l4_i2c_getstatus(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32l4_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1669,22 +1669,22 @@ void stm32l4_i2c_clearinterrupts(struct stm32l4_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32l4_i2c_process + * stm32_i2c_process * and - * stm32l4_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1694,8 +1694,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32l4_i2c_tracenew(priv, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1737,7 +1737,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1747,7 +1747,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1801,7 +1801,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1814,7 +1814,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1825,7 +1825,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1847,13 +1847,13 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32l4_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1866,7 +1866,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32l4_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1909,7 +1909,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1917,7 +1917,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32l4_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1928,7 +1928,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32l4_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1948,8 +1948,8 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { /* Unsupported state */ - stm32l4_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -2015,7 +2015,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -2029,7 +2029,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->msgv++; - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -2042,9 +2042,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32l4_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -2123,7 +2123,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -2131,7 +2131,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -2156,9 +2156,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) * the transfer. */ - stm32l4_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -2175,9 +2175,9 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32l4_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32l4_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -2193,10 +2193,10 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -2212,11 +2212,11 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32l4_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32l4_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -2225,7 +2225,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32l4_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -2234,7 +2234,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32l4_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -2242,7 +2242,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32l4_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* clear pointer to message content to reflect we are done * with the current transaction. @@ -2254,7 +2254,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -2268,7 +2268,7 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) /* Clear all interrupts */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -2281,14 +2281,14 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) #endif } - status = stm32l4_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -2296,24 +2296,24 @@ static int stm32l4_i2c_isr_process(struct stm32l4_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32l4_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32l4_i2c_priv_s *priv = (struct stm32l4_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32l4_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32l4_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ @@ -2336,22 +2336,22 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Configure pins */ - if (stm32l4_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32l4_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32l4_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32l4_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32l4_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2364,33 +2364,33 @@ static int stm32l4_i2c_init(struct stm32l4_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32l4_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32l4_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32l4_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32l4_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32l4_unconfiggpio(priv->config->scl_pin); - stm32l4_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2419,7 +2419,7 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32l4_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2429,11 +2429,11 @@ static int stm32l4_i2c_deinit(struct stm32l4_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32l4_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_inst_s *inst = (struct stm32l4_i2c_inst_s *)dev; - struct stm32l4_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2444,11 +2444,11 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32l4_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32l4_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2457,14 +2457,14 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32l4_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32l4_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32l4_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2473,17 +2473,17 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32l4_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32l4_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32l4_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2491,10 +2491,10 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32l4_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32l4_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2508,7 +2508,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2613,7 +2613,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2623,7 +2623,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32l4_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2631,7 +2631,7 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2642,49 +2642,49 @@ static int stm32l4_i2c_process(struct i2c_master_s *dev, break; } - status = stm32l4_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32l4_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32l4_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32l4_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; int ret; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Ensure that address or flags don't change meanwhile */ ret = nxmutex_lock(&priv->lock); if (ret >= 0) { - ret = stm32l4_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32l4_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2692,9 +2692,9 @@ static int stm32l4_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32l4_i2c_reset(struct i2c_master_s *dev) +static int stm32_i2c_reset(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2706,7 +2706,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Get I2C private structure */ - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2728,7 +2728,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* De-init the port */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ @@ -2737,12 +2737,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Let SDA go high */ - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32l4_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2757,7 +2757,7 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) */ stretch_count = 0; - while (!stm32l4_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2771,12 +2771,12 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) /* Drive SCL low */ - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2784,27 +2784,27 @@ static int stm32l4_i2c_reset(struct i2c_master_s *dev) * state machines. */ - stm32l4_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32l4_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32l4_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32l4_unconfiggpio(sda_gpio); - stm32l4_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32l4_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2817,7 +2817,7 @@ out: #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32l4_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2846,12 +2846,12 @@ out: ****************************************************************************/ #ifdef CONFIG_PM -static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_i2c_priv_s *priv = - (struct stm32l4_i2c_priv_s *)((char *)cb - - offsetof(struct stm32l4_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2893,17 +2893,17 @@ static int stm32l4_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32l4_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32l4_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ @@ -2911,22 +2911,22 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) { #ifdef CONFIG_STM32L4_I2C1 case 1: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif #ifdef CONFIG_STM32L4_I2C2 case 2: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c2_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif #ifdef CONFIG_STM32L4_I2C3 case 3: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif #ifdef CONFIG_STM32L4_I2C4 case 4: - priv = (struct stm32l4_i2c_priv_s *)&stm32l4_i2c4_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; #endif default: @@ -2935,14 +2935,14 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32l4_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32l4_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2952,7 +2952,7 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32l4_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2966,19 +2966,19 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32l4_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32l4_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -3003,7 +3003,7 @@ int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32l4_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h index 9381a169230..5cf6b3b0dbc 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/stm32l4_i2c.h @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32l4_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32l4_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32l4_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32l4_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32l4_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_I2C_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 9ab0ccdf059..0a156b2512e 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32l4_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32l4_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32l4_pmstandby(); + stm32_pmstandby(); break; default: diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 77c20d24e4a..53ec98f34f6 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l4_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32l4_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l4_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l4_nmi, stm32l4_pendsv, stm32l4_pendsv, stm32l4_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32l4_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l4_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32l4_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l4_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { #ifndef CONFIG_ARCH_HIPRI_INTERRUPT up_irq_save(); @@ -160,7 +160,7 @@ static int stm32l4_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l4_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -170,7 +170,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -178,7 +178,7 @@ static int stm32l4_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l4_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -191,7 +191,7 @@ static inline void stm32l4_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l4_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -199,7 +199,7 @@ static inline void stm32l4_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -325,7 +325,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32l4_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -339,19 +339,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32l4_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32l4_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32l4_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l4_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -376,7 +376,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -411,7 +411,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l4_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -488,7 +488,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l4_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index 05f19076f09..fcc02723cc1 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -87,7 +87,7 @@ * well-known watchdog_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct watchdog_ops_s *ops; /* Lower half operations */ uint32_t lsifreq; /* The calibrated frequency of the LSI oscillator */ @@ -105,24 +105,24 @@ struct stm32l4_lowerhalf_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) #endif static inline void -stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv); +stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower); -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower); -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status); -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout); /**************************************************************************** @@ -133,25 +133,25 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, static const struct watchdog_ops_s g_wdgops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .keepalive = stm32l4_keepalive, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, + .start = stm32_start, + .stop = stm32_stop, + .keepalive = stm32_keepalive, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, .capture = NULL, .ioctl = NULL, }; /* "Lower half" driver state */ -static struct stm32l4_lowerhalf_s g_wdgdev; +static struct stm32_lowerhalf_s g_wdgdev; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 IWDG register @@ -159,7 +159,7 @@ static struct stm32l4_lowerhalf_s g_wdgdev; ****************************************************************************/ #ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t count = 0; @@ -214,7 +214,7 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -222,7 +222,7 @@ static uint16_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #ifdef CONFIG_STM32L4_IWDG_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -235,7 +235,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_setprescaler + * Name: stm32_setprescaler * * Description: * Set up the prescaler and reload values. @@ -246,7 +246,7 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) * ****************************************************************************/ -static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) +static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { irqstate_t flags; @@ -254,26 +254,26 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) /* Enable write access to IWDG_PR and IWDG_RLR registers */ - stm32l4_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. These bits * were set the last time that the PR register was written and may not * yet be cleared. */ - while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); /* Set the prescaler */ - stm32l4_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + stm32_putreg(priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - stm32l4_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset by hardware. This is * to wait for the change to take effect before exiting critical section, @@ -289,14 +289,14 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) if (priv->started) { - while (stm32l4_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); + while (stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the watchdog timer, resetting the time to the current timeout, @@ -310,10 +310,10 @@ static inline void stm32l4_setprescaler(struct stm32l4_lowerhalf_s *priv) * ****************************************************************************/ -static int stm32l4_start(struct watchdog_lowerhalf_s *lower) +static int stm32_start(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry: started\n"); @@ -327,7 +327,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * starting the watchdog timer. */ - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); /* Enable IWDG (the LSI oscillator will be enabled by hardware). NOTE: * If the "Hardware watchdog" feature is enabled through the device @@ -335,7 +335,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -345,7 +345,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the watchdog timer @@ -359,7 +359,7 @@ static int stm32l4_start(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) +static int stm32_stop(struct watchdog_lowerhalf_s *lower) { /* There is no way to disable the IDWG timer once it has been started */ @@ -368,7 +368,7 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_keepalive + * Name: stm32_keepalive * * Description: * Reset the watchdog timer to the current timeout value, prevent any @@ -384,10 +384,10 @@ static int stm32l4_stop(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; wdinfo("Entry\n"); @@ -395,7 +395,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - stm32l4_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -403,7 +403,7 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * Get the current watchdog timer status @@ -418,11 +418,11 @@ static int stm32l4_keepalive(struct watchdog_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, struct watchdog_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t ticks; uint32_t elapsed; @@ -463,7 +463,7 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the watchdog timer) @@ -478,11 +478,11 @@ static int stm32l4_getstatus(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint32_t fiwdg; uint64_t reload; int prescaler; @@ -574,7 +574,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, if (priv->started) { - stm32l4_setprescaler(priv); + stm32_setprescaler(priv); } wdinfo("prescaler=%d fiwdg=%" PRId32 " reload=%" PRId64 "\n", @@ -588,7 +588,7 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog timer. The watchdog timer is initialized @@ -605,9 +605,9 @@ static int stm32l4_settimeout(struct watchdog_lowerhalf_s *lower, * ****************************************************************************/ -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) { - struct stm32l4_lowerhalf_s *priv = &g_wdgdev; + struct stm32_lowerhalf_s *priv = &g_wdgdev; wdinfo("Entry: devpath=%s lsifreq=%" PRId32 "\n", devpath, lsifreq); @@ -628,7 +628,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * LSI controls outside of this file. */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); /* Select an arbitrary initial timeout value. But don't start the watchdog @@ -636,7 +636,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq) * device option bits, the watchdog is automatically enabled at power-on. */ - stm32l4_settimeout((struct watchdog_lowerhalf_s *)priv, + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, CONFIG_STM32L4_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.c b/arch/arm/src/stm32l4/stm32l4_lowputc.c index 440c185a92c..d94d25eacc5 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.c +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_rcc.h" #include "stm32l4_gpio.h" #include "stm32l4_uart.h" @@ -291,7 +291,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -302,7 +302,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -310,7 +310,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -319,7 +319,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l4_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -335,19 +335,19 @@ void stm32l4_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l4_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32l4_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32l4_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32l4_configgpio(STM32_CONSOLE_RS485_DIR); - stm32l4_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_lowputc.h b/arch/arm/src/stm32l4/stm32l4_lowputc.h index b28b6d97579..c7441af8c67 100644 --- a/arch/arm/src/stm32l4/stm32l4_lowputc.h +++ b/arch/arm/src/stm32l4/stm32l4_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index f376a1fd169..2b1c4845aa5 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -79,7 +79,7 @@ #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_lptim.h" #include "stm32l4_rcc.h" @@ -92,10 +92,10 @@ /* TIM Device Structure */ -struct stm32l4_lptim_priv_s +struct stm32_lptim_priv_s { - const struct stm32l4_lptim_ops_s *ops; - stm32l4_lptim_mode_t mode; + const struct stm32_lptim_ops_s *ops; + stm32_lptim_mode_t mode; uint32_t base; /* LPTIMn base address */ uint32_t freq; /* Clocking for the LPTIM module */ }; @@ -104,56 +104,56 @@ struct stm32l4_lptim_priv_s * Private Function Prototypes ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer); -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer); +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits); -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg); -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq); -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); static -uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev); -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev); +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev); +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_lptim_ops_s stm32l4_lptim_ops = +static const struct stm32_lptim_ops_s stm32_lptim_ops = { - .setmode = &stm32l4_lptim_setmode, - .setclock = &stm32l4_lptim_setclock, - .setchannel = &stm32l4_lptim_setchannel, - .setclocksource = &stm32l4_lptim_setclocksource, - .setpolarity = &stm32l4_lptim_setpolarity, - .getcounter = &stm32l4_lptim_getcounter, - .setcountmode = &stm32l4_lptim_setcountmode, - .setperiod = &stm32l4_lptim_setperiod, - .getperiod = &stm32l4_lptim_getperiod + .setmode = &stm32_lptim_setmode, + .setclock = &stm32_lptim_setclock, + .setchannel = &stm32_lptim_setchannel, + .setclocksource = &stm32_lptim_setclocksource, + .setpolarity = &stm32_lptim_setpolarity, + .getcounter = &stm32_lptim_getcounter, + .setcountmode = &stm32_lptim_setcountmode, + .setperiod = &stm32_lptim_setperiod, + .getperiod = &stm32_lptim_getperiod }; #if defined(CONFIG_STM32L4_LPTIM1) -static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = +static struct stm32_lptim_priv_s stm32_lptim1_priv = { - .ops = &stm32l4_lptim_ops, + .ops = &stm32_lptim_ops, .mode = STM32_LPTIM_MODE_UNUSED, .base = STM32_LPTIM1_BASE, .freq = STM32_LPTIM1_FREQUENCY, /* Must be defined in board.h */ @@ -161,9 +161,9 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim1_priv = #endif #if defined(CONFIG_STM32L4_LPTIM2) -static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = +static struct stm32_lptim_priv_s stm32_lptim2_priv = { - .ops = &stm32l4_lptim_ops, + .ops = &stm32_lptim_ops, .mode = STM32_LPTIM_MODE_UNUSED, .base = STM32_LPTIM2_BASE, .freq = STM32_LPTIM2_FREQUENCY, /* Must be defined in board.h */ @@ -175,20 +175,20 @@ static struct stm32l4_lptim_priv_s stm32l4_lptim2_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_getstruct + * Name: stm32_lptim_getstruct ****************************************************************************/ -static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) +static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer) { switch (timer) { #if defined(CONFIG_STM32L4_LPTIM1) case 1: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim1_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim1_priv; #endif #if defined(CONFIG_STM32L4_LPTIM2) case 2: - return (struct stm32l4_lptim_dev_s *)&stm32l4_lptim2_priv; + return (struct stm32_lptim_dev_s *)&stm32_lptim2_priv; #endif default: return NULL; @@ -196,26 +196,26 @@ static struct stm32l4_lptim_dev_s *stm32l4_lptim_getstruct(int timer) } /**************************************************************************** - * Name: stm32l4_modifyreg32 + * Name: stm32_modifyreg32 ****************************************************************************/ -static inline void stm32l4_modifyreg32(struct stm32l4_lptim_dev_s *dev, +static inline void stm32_modifyreg32(struct stm32_lptim_dev_s *dev, uint8_t offset, uint32_t clearbits, uint32_t setbits) { - modifyreg32(((struct stm32l4_lptim_priv_s *)dev)->base + offset, + modifyreg32(((struct stm32_lptim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_lptim_enable + * Name: stm32_lptim_enable ****************************************************************************/ -static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) case STM32_LPTIM1_BASE: @@ -236,14 +236,14 @@ static int stm32l4_lptim_enable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_disable + * Name: stm32_lptim_disable ****************************************************************************/ -static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) case STM32_LPTIM1_BASE: @@ -264,14 +264,14 @@ static int stm32l4_lptim_disable(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_reset + * Name: stm32_lptim_reset ****************************************************************************/ -static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) +static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev) { DEBUGASSERT(dev != NULL); - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) case STM32_LPTIM1_BASE: @@ -291,18 +291,18 @@ static int stm32l4_lptim_reset(struct stm32l4_lptim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_lptim_get_gpioconfig + * Name: stm32_lptim_get_gpioconfig ****************************************************************************/ -static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, uint32_t *cfg) { DEBUGASSERT(dev != NULL && cfg != NULL); channel &= STM32_LPTIM_CH_MASK; - switch (((struct stm32l4_lptim_priv_s *)dev)->base) + switch (((struct stm32_lptim_priv_s *)dev)->base) { #if defined(CONFIG_STM32L4_LPTIM1) case STM32_LPTIM1_BASE: @@ -362,13 +362,13 @@ static int stm32l4_lptim_get_gpioconfig(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setmode + * Name: stm32_lptim_setmode ****************************************************************************/ -static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode) +static int stm32_lptim_setmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode) { - const uint32_t addr = ((struct stm32l4_lptim_priv_s *)dev)->base + + const uint32_t addr = ((struct stm32_lptim_priv_s *)dev)->base + STM32_LPTIM_CR_OFFSET; DEBUGASSERT(dev != NULL); @@ -397,20 +397,20 @@ static int stm32l4_lptim_setmode(struct stm32l4_lptim_dev_s *dev, /* Save mode */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = mode; + ((struct stm32_lptim_priv_s *)dev)->mode = mode; return OK; } /**************************************************************************** - * Name: stm32l4_lptim_setclock + * Name: stm32_lptim_setclock ****************************************************************************/ -static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, +static int stm32_lptim_setclock(struct stm32_lptim_dev_s *dev, uint32_t freq) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; uint32_t setbits; uint32_t actual; @@ -420,7 +420,7 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, if (freq == 0) { - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); return 0; } @@ -469,19 +469,19 @@ static int stm32l4_lptim_setclock(struct stm32l4_lptim_dev_s *dev, actual = priv->freq >> 7; } - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_PRESC_MASK, setbits); - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); return actual; } /**************************************************************************** - * Name: stm32l4_lptim_setchannel + * Name: stm32_lptim_setchannel ****************************************************************************/ -static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, +static int stm32_lptim_setchannel(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable) { int ret = OK; @@ -491,16 +491,16 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, /* Configure GPIOs */ - ret = stm32l4_lptim_get_gpioconfig(dev, channel, &cfg); + ret = stm32_lptim_get_gpioconfig(dev, channel, &cfg); if (!ret) { if (enable) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } @@ -508,20 +508,20 @@ static int stm32l4_lptim_setchannel(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setclocksource + * Name: stm32_lptim_setclocksource ****************************************************************************/ -static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc) +static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); if (clksrc == STM32_LPTIM_CLK_EXT) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_EXTCLK); } @@ -613,7 +613,7 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, modifyreg32(STM32_RCC_CCIPR, ccr_mask, ccr_bits); - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKSEL_MASK, LPTIM_CFGR_CKSEL_INTCLK); } @@ -622,49 +622,49 @@ static int stm32l4_lptim_setclocksource(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setperiod + * Name: stm32_lptim_setperiod ****************************************************************************/ -static void stm32l4_lptim_setperiod(struct stm32l4_lptim_dev_s *dev, +static void stm32_lptim_setperiod(struct stm32_lptim_dev_s *dev, uint32_t period) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); putreg32(period, (uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_lptim_getperiod(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getperiod(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); return getreg32((uintptr_t)(priv->base + STM32_LPTIM_ARR_OFFSET)); } /**************************************************************************** - * Name: stm32l4_lptim_setcountmode + * Name: stm32_lptim_setcountmode ****************************************************************************/ -static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode) +static int stm32_lptim_setcountmode(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode) { DEBUGASSERT(dev != NULL); if (cntmode == STM32_LPTIM_COUNT_CLOCK) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_COUNTMODE, 0); } else if (cntmode == STM32_LPTIM_COUNT_EXTTRIG) { - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, 0, LPTIM_CFGR_COUNTMODE); } else @@ -676,30 +676,30 @@ static int stm32l4_lptim_setcountmode(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity) +static int stm32_lptim_setpolarity(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity) { DEBUGASSERT(dev != NULL); switch (polarity) { case STM32_LPTIM_CLKPOL_RISING: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_RISING); break; case STM32_LPTIM_CLKPOL_FALLING: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_FALLING); break; case STM32_LPTIM_CLKPOL_BOTH: - stm32l4_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, + stm32_modifyreg32(dev, STM32_LPTIM_CFGR_OFFSET, LPTIM_CFGR_CKPOL_MASK, LPTIM_CFGR_CKPOL_BOTH); break; @@ -709,13 +709,13 @@ static int stm32l4_lptim_setpolarity(struct stm32l4_lptim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_lptim_setpolarity + * Name: stm32_lptim_setpolarity ****************************************************************************/ -static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) +static uint32_t stm32_lptim_getcounter(struct stm32_lptim_dev_s *dev) { - struct stm32l4_lptim_priv_s *priv = - (struct stm32l4_lptim_priv_s *)dev; + struct stm32_lptim_priv_s *priv = + (struct stm32_lptim_priv_s *)dev; DEBUGASSERT(dev != NULL); @@ -739,16 +739,16 @@ static uint32_t stm32l4_lptim_getcounter(struct stm32l4_lptim_dev_s *dev) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lptim_init + * Name: stm32_lptim_init ****************************************************************************/ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) +struct stm32_lptim_dev_s *stm32_lptim_init(int timer) { - struct stm32l4_lptim_dev_s *dev = NULL; + struct stm32_lptim_dev_s *dev = NULL; /* Get structure and enable power */ - dev = stm32l4_lptim_getstruct(timer); + dev = stm32_lptim_getstruct(timer); if (!dev) { return NULL; @@ -756,7 +756,7 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_lptim_priv_s *)dev)->mode != + if (((struct stm32_lptim_priv_s *)dev)->mode != STM32_LPTIM_MODE_UNUSED) { return NULL; @@ -764,34 +764,34 @@ struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer) /* Enable power */ - stm32l4_lptim_enable(dev); + stm32_lptim_enable(dev); /* Reset timer */ - stm32l4_lptim_reset(dev); + stm32_lptim_reset(dev); /* Mark it as used */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_DISABLED; return dev; } /**************************************************************************** - * Name: stm32l4_lptim_deinit + * Name: stm32_lptim_deinit ****************************************************************************/ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s * dev) +int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) { DEBUGASSERT(dev); /* Disable power */ - stm32l4_lptim_disable(dev); + stm32_lptim_disable(dev); /* Mark it as free */ - ((struct stm32l4_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; + ((struct stm32_lptim_priv_s *)dev)->mode = STM32_LPTIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.h b/arch/arm/src/stm32l4/stm32l4_lptim.h index db940b524c3..eec2fc06c84 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.h +++ b/arch/arm/src/stm32l4/stm32l4_lptim.h @@ -112,9 +112,9 @@ extern "C" /* LPTIM Device Structure */ -struct stm32l4_lptim_dev_s +struct stm32_lptim_dev_s { - struct stm32l4_lptim_ops_s *ops; + struct stm32_lptim_ops_s *ops; }; /* LPTIM Modes of Operation */ @@ -129,7 +129,7 @@ typedef enum STM32_LPTIM_MODE_SINGLE = 0x0001, STM32_LPTIM_MODE_CONTINUOUS = 0x0002, STM32_LPTIM_MODE_MASK = 0x000f, -} stm32l4_lptim_mode_t; +} stm32_lptim_mode_t; /* LPTIM Clock Source */ @@ -142,7 +142,7 @@ typedef enum STM32_LPTIM_CLK_HSI = 0x0002, STM32_LPTIM_CLK_LSE = 0x0003, STM32_LPTIM_CLK_EXT = 0x0004, -} stm32l4_lptim_clksrc_t; +} stm32_lptim_clksrc_t; /* LPTIM Counter Modes */ @@ -152,7 +152,7 @@ typedef enum STM32_LPTIM_COUNT_CLOCK = 0x0000, STM32_LPTIM_COUNT_EXTTRIG = 0x0001, -} stm32l4_lptim_cntmode_t; +} stm32_lptim_cntmode_t; /* LPTIM Clock Polarity */ @@ -163,7 +163,7 @@ typedef enum STM32_LPTIM_CLKPOL_RISING = 0x0000, STM32_LPTIM_CLKPOL_FALLING = 0x0001, STM32_LPTIM_CLKPOL_BOTH = 0x0002, -} stm32l4_lptim_clkpol_t; +} stm32_lptim_clkpol_t; /* LPTIM Channel Modes */ @@ -178,26 +178,26 @@ typedef enum STM32_LPTIM_CH_CH2 = 0x0002, STM32_LPTIM_CH_CH3 = 0x0003, STM32_LPTIM_CH_MASK = 0x000f, -} stm32l4_lptim_channel_t; +} stm32_lptim_channel_t; /* LPTIM Operations */ -struct stm32l4_lptim_ops_s +struct stm32_lptim_ops_s { - int (*setmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_mode_t mode); - int (*setclock)(struct stm32l4_lptim_dev_s *dev, uint32_t freq); - int (*setchannel)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_channel_t channel, int enable); - int (*setclocksource)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clksrc_t clksrc); - int (*setpolarity)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_clkpol_t polarity); - uint32_t (*getcounter)(struct stm32l4_lptim_dev_s *dev); - int (*setcountmode)(struct stm32l4_lptim_dev_s *dev, - stm32l4_lptim_cntmode_t cntmode); - void (*setperiod)(struct stm32l4_lptim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_lptim_dev_s *dev); + int (*setmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_mode_t mode); + int (*setclock)(struct stm32_lptim_dev_s *dev, uint32_t freq); + int (*setchannel)(struct stm32_lptim_dev_s *dev, + stm32_lptim_channel_t channel, int enable); + int (*setclocksource)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clksrc_t clksrc); + int (*setpolarity)(struct stm32_lptim_dev_s *dev, + stm32_lptim_clkpol_t polarity); + uint32_t (*getcounter)(struct stm32_lptim_dev_s *dev); + int (*setcountmode)(struct stm32_lptim_dev_s *dev, + stm32_lptim_cntmode_t cntmode); + void (*setperiod)(struct stm32_lptim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_lptim_dev_s *dev); }; /**************************************************************************** @@ -206,11 +206,11 @@ struct stm32l4_lptim_ops_s /* Get timer structure, power-up, reset, and mark it as used */ -struct stm32l4_lptim_dev_s *stm32l4_lptim_init(int timer); +struct stm32_lptim_dev_s *stm32_lptim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_lptim_deinit(struct stm32l4_lptim_dev_s *dev); +int stm32_lptim_deinit(struct stm32_lptim_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 6859cfec064..0a36765f326 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -54,14 +54,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; @@ -78,7 +78,7 @@ void stm32l4_rcc_enablelse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32l4_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -100,7 +100,7 @@ void stm32l4_rcc_enablelse(void) while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32l4_waste(); + stm32_waste(); } #if defined(CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ @@ -121,6 +121,6 @@ void stm32l4_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - stm32l4_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l4/stm32l4_lsi.c b/arch/arm/src/stm32l4/stm32l4_lsi.c index 2897d3646ba..ae42b876ca2 100644 --- a/arch/arm/src/stm32l4/stm32l4_lsi.c +++ b/arch/arm/src/stm32l4/stm32l4_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32l4_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.c b/arch/arm/src/stm32l4/stm32l4_mpuinit.c index fe22ca17d48..1deb74cdf96 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.c +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l4_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l4_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l4_mpuinitialize(void) * ****************************************************************************/ -void stm32l4_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l4/stm32l4_mpuinit.h b/arch/arm/src/stm32l4/stm32l4_mpuinit.h index 986554b2ba8..8851634ea3b 100644 --- a/arch/arm/src/stm32l4/stm32l4_mpuinit.h +++ b/arch/arm/src/stm32l4/stm32l4_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l4_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l4_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l4_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l4_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_MPUINIT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index 68ff5860cf2..dbcdb372253 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -45,20 +45,20 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32l4_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32l4_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32l4_oneshot_s *oneshot = (struct stm32l4_oneshot_s *) arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *) arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -107,7 +107,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -121,7 +121,7 @@ static int stm32l4_oneshot_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { #if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; @@ -162,7 +162,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32l4_allocate_handler(struct stm32l4_oneshot_s *oneshot) * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,7 +193,7 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32l4_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -211,18 +211,18 @@ int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32l4_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32l4_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -302,7 +302,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32_TIM_SETISR(oneshot->tch, stm32l4_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ @@ -326,7 +326,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -337,7 +337,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -350,7 +350,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index 0a7d2ff34d5..d8dc54996ed 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32l4_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32l4_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ #if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32l4_tim_dev_s *tch; /* Pointer returned by - * stm32l4_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32l4_oneshot_initialize(struct stm32l4_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32l4_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32l4_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32l4_oneshot_max_delay(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32l4_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32l4_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32l4_oneshot_start(struct stm32l4_oneshot_s *oneshot, * ****************************************************************************/ -int stm32l4_oneshot_cancel(struct stm32l4_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c index 7dd0b0cd73f..12474e60807 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32l4_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32l4_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32l4_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32l4_max_delay, - .start = stm32l4_start, - .cancel = stm32l4_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32l4_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32l4_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32l4_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32l4_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32l4_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32l4_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_start(&priv->oneshot, - stm32l4_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32l4_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32l4_oneshot_lowerhalf_s *priv = - (struct stm32l4_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32l4_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -278,13 +278,13 @@ static int stm32l4_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32l4_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32l4_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32l4_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -298,10 +298,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, /* Initialize the contained STM32 oneshot timer */ - ret = stm32l4_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index 00fb8ba0b30..9b6991c9904 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -31,7 +31,7 @@ #include -#include "stm32l4.h" +#include "stm32.h" #if defined(CONFIG_STM32L4_OTGFS) @@ -67,7 +67,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -94,21 +94,21 @@ extern "C" #ifdef CONFIG_USBHOST struct usbhost_connection_s; struct -usbhost_connection_s *stm32l4_otgfshost_initialize(int controller); +usbhost_connection_s *stm32_otgfshost_initialize(int controller); #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the OTG FS + * Board logic must provide the stm32_usbsuspend logic if the OTG FS * device driver is used. This function is called whenever the USB enters * or leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index ef8f20ba9da..a7c8ef95eef 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -349,8 +349,8 @@ /* Request queue operations *************************************************/ -#define stm32l4_rqempty(ep) ((ep)->head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /**************************************************************************** * Private Types @@ -358,7 +358,7 @@ /* Overall device state */ -enum stm32l4_devstate_e +enum stm32_devstate_e { DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply * means that the device is not yet been given an @@ -385,11 +385,11 @@ enum stm32l4_devstate_e /* Endpoint 0 states */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or * epsubmit: - * SET: In stm32l4_epin() and stm32l4_epout() when + * SET: In stm32_epin() and stm32_epout() when * we revert from request processing to * SETUP processing. * TESTED: Never @@ -397,51 +397,51 @@ enum stm32l4_ep0state_e EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA * OUT phase of SETUP Packet to complete before * processing a SETUP command (without a USB request): - * SET: Set in stm32l4_rxinterrupt() when SETUP OUT + * SET: Set in stm32_rxinterrupt() when SETUP OUT * packet is received. - * TESTED: In stm32l4_ep0out_receive() + * TESTED: In stm32_ep0out_receive() */ EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and * accompanying data have been received. Processing * of SETUP command will happen soon. - * SET: (1) stm32l4_ep0out_receive() when the OUT + * SET: (1) stm32_ep0out_receive() when the OUT * SETUP data phase completes, or (2) - * stm32l4_rxinterrupt() when an IN SETUP is + * stm32_rxinterrupt() when an IN SETUP is * packet received. - * TESTED: Tested in stm32l4_epout_interrupt() when + * TESTED: Tested in stm32_epout_interrupt() when * SETUP phase is done to see if the SETUP * command is ready to be processed. Also - * tested in stm32l4_ep0out_setup() just to + * tested in stm32_ep0out_setup() just to * double-check that we have a SETUP request * and any accompanying data. */ - EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32l4_ep0out_setup(): + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): * SET: When SETUP packet received in EP0 OUT * TESTED: Never */ EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): * SET: When SETUP response is sent by - * stm32l4_ep0in_setupresponse() + * stm32_ep0in_setupresponse() * TESTED: Never */ EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): - * SET: In stm32l4_epin_request() when a write + * SET: In stm32_epin_request() when a write * request is processed on EP0. - * TESTED: In stm32l4_epin() to see if we should + * TESTED: In stm32_epin() to see if we should * revert to SETUP processing. */ EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a * USB request) - * SET: In stm32l4_epout_request() when a read + * SET: In stm32_epout_request() when a read * request is processed on EP0. - * TESTED: In stm32l4_epout() to see if we should + * TESTED: In stm32_epout() to see if we should * revert to SETUP processing */ }; /* Parsed control request */ -struct stm32l4_ctrlreq_s +struct stm32_ctrlreq_s { uint8_t type; uint8_t req; @@ -452,28 +452,28 @@ struct stm32l4_ctrlreq_s /* A container for a request so that the request may be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t epphy; /* Physical EP address */ uint8_t eptype:2; /* Endpoint type */ uint8_t active:1; /* 1: A request is being processed */ @@ -485,11 +485,11 @@ struct stm32l4_ep_s /* This structure retains the state of the USB device controller */ -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s - * to struct stm32l4_usbdev_s. + * to struct stm32_usbdev_s. */ struct usbdev_s usbdev; @@ -507,8 +507,8 @@ struct stm32l4_usbdev_s uint8_t wakeup:1; /* 1: Device remote wake-up */ uint8_t dotest:1; /* 1: Test mode selected */ - uint8_t devstate:4; /* See enum stm32l4_devstate_e */ - uint8_t ep0state:4; /* See enum stm32l4_ep0state_e */ + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ uint8_t testmode:4; /* Selected test mode */ uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ @@ -538,8 +538,8 @@ struct stm32l4_usbdev_s /* The endpoint lists */ - struct stm32l4_ep_s epin[STM32_NENDPOINTS]; - struct stm32l4_ep_s epout[STM32_NENDPOINTS]; + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -549,203 +549,203 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ #if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t val, uint32_t addr); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(val,addr) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) #endif /* Request queue operations *************************************************/ static struct -stm32l4_req_s *stm32l4_req_remfirst(struct stm32l4_ep_s *privep); -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +stm32_req_s *stm32_req_remfirst(struct stm32_ep_s *privep); +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req); /* Low level data transfers and request operations **************************/ /* Special endpoint 0 data transfer logic */ static -void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *data, uint32_t nbytes); static inline -void stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in_activate(void); +void stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); static -void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv); +void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv); /* IN request and TxFIFO handling */ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes); -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* OUT request and RxFIFO handling */ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len); -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len); -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt); -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt); -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* General request handling */ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep); -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_ep_flush(struct stm32_ep_s *privep); +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status); /* Interrupt handling *******************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog); -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl); -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv); +static void stm32_usbreset(struct stm32_usbdev_s *priv); /* Second level OUT endpoint interrupt processing */ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index); -static inline void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq); -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv); +void stm32_epout_interrupt(struct stm32_usbdev_s *priv); /* Second level IN endpoint interrupt processing */ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv); +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv); static inline -void stm32l4_epin(struct stm32l4_usbdev_s *priv, uint8_t epno); +void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno); static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno); -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv); +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv); /* Other second level interrupt processing */ static inline -void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_resumeinterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv); +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv); #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocininterrupt(struct stm32_usbdev_s *priv); static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv); +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv); #endif #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv); -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv); +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv); #endif /* First level interrupt processing */ -static int stm32l4_usbinterrupt(int irq, void *context, +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint operations ******************************************************/ /* Global OUT NAK controls */ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep); -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep); +static void stm32_enablegonak(struct stm32_ep_s *privep); +static void stm32_disablegonak(struct stm32_ep_s *privep); /* Endpoint configuration */ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket); -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv); +static void stm32_ep0_configure(struct stm32_usbdev_s *priv); /* Endpoint disable */ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep); -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep); -static int stm32l4_ep_disable(struct usbdev_ep_s *ep); +static void stm32_epout_disable(struct stm32_ep_s *privep); +static void stm32_epin_disable(struct stm32_ep_s *privep); +static int stm32_ep_disable(struct usbdev_ep_s *ep); /* Endpoint request management */ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep); -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep); +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); /* Endpoint buffer management */ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes); -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf); #endif /* Endpoint request submission */ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Endpoint request cancellation */ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); /* Stall handling */ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep); -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume); -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv); +static int stm32_epout_setstall(struct stm32_ep_s *privep); +static int stm32_epin_setstall(struct stm32_ep_s *privep); +static int stm32_ep_setstall(struct stm32_ep_s *privep); +static int stm32_ep_clrstall(struct stm32_ep_s *privep); +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(struct stm32_usbdev_s *priv); /* Endpoint allocation */ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep); /* USB device controller operations *****************************************/ -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address); -static int stm32l4_txfifo_flush(uint32_t txfnum); -static int stm32l4_rxfifo_flush(void); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); /* Initialization ***********************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); +static void stm32_swinitialize(struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -755,31 +755,31 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_otgfsdev; +static struct stm32_usbdev_s g_otgfsdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_ep_configure, - .disable = stm32l4_ep_disable, - .allocreq = stm32l4_ep_allocreq, - .freereq = stm32l4_ep_freereq, + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, #ifdef CONFIG_USBDEV_DMA - .allocbuffer = stm32l4_ep_allocbuffer, - .freebuffer = stm32l4_ep_freebuffer, + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, #endif - .submit = stm32l4_ep_submit, - .cancel = stm32l4_ep_cancel, - .stall = stm32l4_ep_stall, + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_ep_alloc, - .freeep = stm32l4_ep_free, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /* Device error strings that may be enabled for more descriptive USB trace @@ -886,7 +886,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register @@ -894,7 +894,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = ****************************************************************************/ #if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static uint32_t stm32l4_getreg(uint32_t addr) +static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -949,7 +949,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -957,7 +957,7 @@ static uint32_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) -static void stm32l4_putreg(uint32_t val, uint32_t addr) +static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -970,17 +970,17 @@ static void stm32l4_putreg(uint32_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_req_remfirst + * Name: stm32_req_remfirst * * Description: * Remove a request from the head of an endpoint request queue * ****************************************************************************/ -static struct stm32l4_req_s * -stm32l4_req_remfirst(struct stm32l4_ep_s *privep) +static struct stm32_req_s * +stm32_req_remfirst(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -997,15 +997,15 @@ stm32l4_req_remfirst(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_req_addlast + * Name: stm32_req_addlast * * Description: * Add a request to the end of an endpoint request queue * ****************************************************************************/ -static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static bool stm32_req_addlast(struct stm32_ep_s *privep, + struct stm32_req_s *req) { bool is_empty = !privep->head; @@ -1025,23 +1025,23 @@ static bool stm32l4_req_addlast(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_ep0in_setupresponse + * Name: stm32_ep0in_setupresponse * * Description: * Schedule a short transfer on Endpoint 0 (IN or OUT) * ****************************************************************************/ -static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, +static void stm32_ep0in_setupresponse(struct stm32_usbdev_s *priv, uint8_t *buf, uint32_t nbytes) { - stm32l4_epin_transfer(&priv->epin[EP0], buf, nbytes); + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); priv->ep0state = EP0STATE_SETUPRESPONSE; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0in_transmitzlp + * Name: stm32_ep0in_transmitzlp * * Description: * Send a zero length packet (ZLP) on endpoint 0 IN @@ -1049,26 +1049,26 @@ static void stm32l4_ep0in_setupresponse(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline void -stm32l4_ep0in_transmitzlp(struct stm32l4_usbdev_s *priv) +stm32_ep0in_transmitzlp(struct stm32_usbdev_s *priv) { - stm32l4_ep0in_setupresponse(priv, NULL, 0); + stm32_ep0in_setupresponse(priv, NULL, 0); } /**************************************************************************** - * Name: stm32l4_ep0in_activate + * Name: stm32_ep0in_activate * * Description: * Activate the endpoint 0 IN endpoint. * ****************************************************************************/ -static void stm32l4_ep0in_activate(void) +static void stm32_ep0in_activate(void) { uint32_t regval; /* Set the max packet size of the IN EP. */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(0)); regval &= ~OTGFS_DIEPCTL0_MPSIZ_MASK; #if CONFIG_USBDEV_EP0_MAXSIZE == 8 @@ -1083,24 +1083,24 @@ static void stm32l4_ep0in_activate(void) # error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" #endif - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(0)); /* Clear global IN NAK */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGINAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_ep0out_ctrlsetup + * Name: stm32_ep0out_ctrlsetup * * Description: * Setup to receive a SETUP packet. * ****************************************************************************/ -static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out_ctrlsetup(struct stm32_usbdev_s *priv) { uint32_t regval; @@ -1109,24 +1109,24 @@ static void stm32l4_ep0out_ctrlsetup(struct stm32l4_usbdev_s *priv) regval = (USB_SIZEOF_CTRLREQ * 3 << OTGFS_DOEPTSIZ0_XFRSIZ_SHIFT) | (OTGFS_DOEPTSIZ0_PKTCNT) | (3 << OTGFS_DOEPTSIZ0_STUPCNT_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPTSIZ(0)); /* Then clear NAKing and enable the transfer */ - regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(0)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(0)); regval |= (OTGFS_DOEPCTL0_CNAK | OTGFS_DOEPCTL0_EPENA); - stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(0)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(0)); } /**************************************************************************** - * Name: stm32l4_txfifo_write + * Name: stm32_txfifo_write * * Description: * Send data to the endpoint's TxFIFO. * ****************************************************************************/ -static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, +static void stm32_txfifo_write(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t regaddr; @@ -1157,19 +1157,19 @@ static void stm32l4_txfifo_write(struct stm32l4_ep_s *privep, /* Then write the packet data to the TxFIFO */ - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); } } /**************************************************************************** - * Name: stm32l4_epin_transfer + * Name: stm32_epin_transfer * * Description: * Start the Tx data transfer * ****************************************************************************/ -static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, +static void stm32_epin_transfer(struct stm32_ep_s *privep, uint8_t *buf, int nbytes) { uint32_t pktcnt; @@ -1177,7 +1177,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Read the DIEPSIZx register */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ @@ -1223,11 +1223,11 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, /* Save DIEPSIZx register value */ - stm32l4_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPTSIZ(privep->epphy)); /* Read the DIEPCTLx register */ - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(privep->epphy)); /* If this is an isochronous endpoint, then set the even/odd frame bit * the DIEPCTLx register. @@ -1239,7 +1239,7 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, * even/odd frame to match. */ - uint32_t status = stm32l4_getreg(STM32_OTGFS_DSTS); + uint32_t status = stm32_getreg(STM32_OTGFS_DSTS); if ((status & OTGFS_DSTS_SOFFN0) == OTGFS_DSTS_SOFFN_EVEN) { regval |= OTGFS_DIEPCTL_SEVNFRM; @@ -1254,28 +1254,28 @@ static void stm32l4_epin_transfer(struct stm32l4_ep_s *privep, regval &= ~OTGFS_DIEPCTL_EPDIS; regval |= (OTGFS_DIEPCTL_CNAK | OTGFS_DIEPCTL_EPENA); - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(privep->epphy)); /* Transfer the data to the TxFIFO. At this point, the caller has already * assured that there is sufficient space in the TxFIFO to hold the * transfer we can just blindly continue. */ - stm32l4_txfifo_write(privep, buf, nbytes); + stm32_txfifo_write(privep, buf, nbytes); } /**************************************************************************** - * Name: stm32l4_epin_request + * Name: stm32_epin_request * * Description: * Begin or continue write request processing. * ****************************************************************************/ -static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epin_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint8_t *buf; @@ -1286,12 +1286,12 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* We get here in one of four possible ways. From three interrupting * events: * - * 1. From stm32l4_epin as part of the transfer complete interrupt + * 1. From stm32_epin as part of the transfer complete interrupt * processing This interrupt indicates that the last transfer has * completed. * 2. As part of the ITTXFE interrupt processing. That interrupt indicates * that an IN token was received when the associated TxFIFO was empty. - * 3. From stm32l4_epin_txfifoempty as part of the TXFE interrupt + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt * processing. The TXFE interrupt is only enabled when the TxFIFO is * full and the software must wait for space to become available in the * TxFIFO. @@ -1299,13 +1299,13 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * And this function may be called immediately when the write request is * queue to start up the next transaction. * - * 4. From stm32l4_ep_submit when a new write request is received WHILE the + * 4. From stm32_ep_submit when a new write request is received WHILE the * endpoint is not active (privep->active == false). */ /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); @@ -1317,9 +1317,9 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DIEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer active */ @@ -1426,7 +1426,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * the TxFIFO is empty. */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((int)(regval & OTGFS_DTXFSTS_MASK) < nwords) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), @@ -1436,16 +1436,16 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * empty interrupt and try again. */ - uint32_t empmsk = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); + uint32_t empmsk = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); empmsk |= OTGFS_DIEPEMPMSK(privep->epphy); - stm32l4_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(empmsk, STM32_OTGFS_DIEPEMPMSK); #ifdef CONFIG_DEBUG_FEATURES /* Check if the configured TXFIFO size is sufficient for a given * request. If not, raise an assertion here. */ - regval = stm32l4_getreg(STM32_OTG_DIEPTXF(privep->epphy)); + regval = stm32_getreg(STM32_OTG_DIEPTXF(privep->epphy)); regval &= OTGFS_DIEPTXF_INEPTXFD_MASK; regval >>= OTGFS_DIEPTXF_INEPTXFD_SHIFT; uerr("EP%" PRId8 " TXLEN=%" PRId32 " nwords=%d\n", @@ -1463,7 +1463,7 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, /* Transfer data to the TxFIFO */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epin_transfer(privep, buf, nbytes); + stm32_epin_transfer(privep, buf, nbytes); /* If it was not before, the OUT endpoint is now actively transferring * data. @@ -1497,19 +1497,19 @@ static void stm32l4_epin_request(struct stm32l4_usbdev_s *priv, * yet completed). */ - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); } } /**************************************************************************** - * Name: stm32l4_rxfifo_read + * Name: stm32_rxfifo_read * * Description: * Read packet from the RxFIFO into a read request. * ****************************************************************************/ -static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, +static void stm32_rxfifo_read(struct stm32_ep_s *privep, uint8_t *dest, uint16_t len) { uint32_t regaddr; @@ -1535,7 +1535,7 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, /* Read 1 x 32-bits of EP0 packet data */ - data.w = stm32l4_getreg(regaddr); + data.w = stm32_getreg(regaddr); /* Write 4 x 8-bits of EP0 packet data */ @@ -1547,14 +1547,14 @@ static void stm32l4_rxfifo_read(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_rxfifo_discard + * Name: stm32_rxfifo_discard * * Description: * Discard packet data from the RxFIFO. * ****************************************************************************/ -static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) +static void stm32_rxfifo_discard(struct stm32_ep_s *privep, int len) { if (len > 0) { @@ -1571,7 +1571,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) for (i = 0; i < len; i += 4) { - volatile uint32_t data = stm32l4_getreg(regaddr); + volatile uint32_t data = stm32_getreg(regaddr); UNUSED(data); } @@ -1580,7 +1580,7 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) } /**************************************************************************** - * Name: stm32l4_epout_complete + * Name: stm32_epout_complete * * Description: * This function is called when an OUT transfer complete interrupt is @@ -1589,16 +1589,16 @@ static void stm32l4_rxfifo_discard(struct stm32l4_ep_s *privep, int len) * ****************************************************************************/ -static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_complete(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Since a transfer just completed, there must be a read request at the * head of the endpoint request queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); DEBUGASSERT(privreq); if (!privreq) @@ -1620,16 +1620,16 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, */ usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); privep->active = false; /* Now set up the next read request (if any) */ - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_ep0out_receive + * Name: stm32_ep0out_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1638,15 +1638,15 @@ static void stm32l4_epout_complete(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, +static inline void stm32_ep0out_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_usbdev_s *priv; + struct stm32_usbdev_s *priv; /* Sanity Checking */ DEBUGASSERT(privep && privep->dev); - priv = (struct stm32l4_usbdev_s *)privep->dev; + priv = (struct stm32_usbdev_s *)privep->dev; uinfo("EP0: bcnt=%d\n", bcnt); usbtrace(TRACE_READ(EP0), bcnt); @@ -1660,11 +1660,11 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, /* Read the data into our special buffer for SETUP data */ int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); - stm32l4_rxfifo_read(privep, priv->ep0data, readlen); + stm32_rxfifo_read(privep, priv->ep0data, readlen); /* Do we have to discard any excess bytes? */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Now we can process the setup command */ @@ -1672,7 +1672,7 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, priv->ep0state = EP0STATE_SETUP_READY; priv->ep0datlen = readlen; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } else { @@ -1682,13 +1682,13 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, */ usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); - stm32l4_rxfifo_discard(privep, bcnt); + stm32_rxfifo_discard(privep, bcnt); privep->active = false; } } /**************************************************************************** - * Name: stm32l4_epout_receive + * Name: stm32_epout_receive * * Description: * This function is called from the RXFLVL interrupt handler when new @@ -1697,10 +1697,10 @@ static inline void stm32l4_ep0out_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, +static inline void stm32_epout_receive(struct stm32_ep_s *privep, int bcnt) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *dest; int buflen; int readlen; @@ -1709,7 +1709,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * queue. */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data is available in the RxFIFO, but there is no read setup @@ -1724,7 +1724,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, if (privep->epphy == 0) { - stm32l4_ep0out_receive(privep, bcnt); + stm32_ep0out_receive(privep, bcnt); } else { @@ -1737,7 +1737,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, /* Discard the data in the RxFIFO */ - stm32l4_rxfifo_discard(privep, bcnt); + stm32_rxfifo_discard(privep, bcnt); } privep->active = false; @@ -1760,13 +1760,13 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, /* Transfer the data from the RxFIFO to the request's data buffer */ - stm32l4_rxfifo_read(privep, dest, readlen); + stm32_rxfifo_read(privep, dest, readlen); /* If there were more bytes in the RxFIFO than could be held in the read * request, then we will have to discard those. */ - stm32l4_rxfifo_discard(privep, bcnt - readlen); + stm32_rxfifo_discard(privep, bcnt - readlen); /* Update the number of bytes transferred */ @@ -1774,7 +1774,7 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_epout_request + * Name: stm32_epout_request * * Description: * This function is called when either @@ -1784,10 +1784,10 @@ static inline void stm32l4_epout_receive(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static void stm32_epout_request(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t regval; uint32_t xfrsize; @@ -1811,7 +1811,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, * request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), @@ -1824,9 +1824,9 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_SNAK; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* This endpoint is no longer actively transferring */ @@ -1843,7 +1843,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, if (privreq->req.len <= 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_req_complete(privep, OK); + stm32_req_complete(privep, OK); } /* Otherwise, we have a usable read request... @@ -1871,16 +1871,16 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Then setup the hardware to perform this transfer */ regaddr = STM32_OTGFS_DOEPTSIZ(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~(OTGFS_DOEPTSIZ_XFRSIZ_MASK | OTGFS_DOEPTSIZ_PKTCNT_MASK); regval |= (xfrsize << OTGFS_DOEPTSIZ_XFRSIZ_SHIFT); regval |= (pktcnt << OTGFS_DOEPTSIZ_PKTCNT_SHIFT); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Then enable the transfer */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); /* When an isochronous transfer is enabled the Even/Odd frame bit must * also be set appropriately. @@ -1903,7 +1903,7 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, /* Clearing NAKing and enable the transfer. */ regval |= (OTGFS_DOEPCTL_CNAK | OTGFS_DOEPCTL_EPENA); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* A transfer is now active on this endpoint */ @@ -1921,27 +1921,27 @@ static void stm32l4_epout_request(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep_flush + * Name: stm32_ep_flush * * Description: * Flush any primed descriptors from this ep * ****************************************************************************/ -static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) +static void stm32_ep_flush(struct stm32_ep_s *privep) { if (privep->isin) { - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); } else { - stm32l4_rxfifo_flush(); + stm32_rxfifo_flush(); } } /**************************************************************************** - * Name: stm32l4_req_complete + * Name: stm32_req_complete * * Description: * Handle termination of the request at the head of the endpoint request @@ -1949,14 +1949,14 @@ static void stm32l4_ep_flush(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static void stm32l4_req_complete(struct stm32l4_ep_s *privep, +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; /* Remove the request at the head of the request list */ - privreq = stm32l4_req_remfirst(privep); + privreq = stm32_req_remfirst(privep); DEBUGASSERT(privreq != NULL); /* If endpoint 0, temporarily reflect the state of protocol stalled @@ -1983,30 +1983,30 @@ static void stm32l4_req_complete(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_req_cancel + * Name: stm32_req_cancel * * Description: * Cancel all pending requests for an endpoint * ****************************************************************************/ -static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) { - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { - stm32l4_ep_flush(privep); + stm32_ep_flush(privep); } - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(privep->epphy), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_req_complete(privep, status); + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); } } /**************************************************************************** - * Name: stm32l4_ep_findbyaddr + * Name: stm32_ep_findbyaddr * * Description: * Find the physical endpoint structure corresponding to a logic endpoint @@ -2015,10 +2015,10 @@ static void stm32l4_req_cancel(struct stm32l4_ep_s *privep, int16_t status) ****************************************************************************/ static -struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, +struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, uint16_t eplog) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint8_t epphy = USB_EPNO(eplog); if (epphy >= STM32_NENDPOINTS) @@ -2044,7 +2044,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_req_dispatch + * Name: stm32_req_dispatch * * Description: * Provide unhandled setup actions to the class driver. This is logically @@ -2052,7 +2052,7 @@ struct stm32l4_ep_s *stm32l4_ep_findbyaddr(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, const struct usb_ctrlreq_s *ctrl) { int ret = -EIO; @@ -2078,28 +2078,28 @@ static int stm32l4_req_dispatch(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_usbreset + * Name: stm32_usbreset * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) +static void stm32_usbreset(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int i; /* Clear the Remote Wake-up Signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Flush the EP0 Tx FIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(EP0)); /* Tell the class driver that we are disconnected. The class * driver should then accept any new configurations. @@ -2121,13 +2121,13 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) { /* Disable endpoint interrupts */ - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); /* Return write requests to the class implementation */ privep = &priv->epin[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset IN endpoint status */ @@ -2136,54 +2136,54 @@ static void stm32l4_usbreset(struct stm32l4_usbdev_s *priv) /* Return read requests to the class implementation */ privep = &priv->epout[i]; - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); /* Reset endpoint status */ privep->stalled = false; } - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Mask all device endpoint interrupts except EP0 */ regval = (OTGFS_DAINT_IEP(EP0) | OTGFS_DAINT_OEP(EP0)); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Unmask OUT interrupts */ regval = (OTGFS_DOEPMSK_XFRCM | OTGFS_DOEPMSK_STUPM | OTGFS_DOEPMSK_EPDM); - stm32l4_putreg(regval, STM32_OTGFS_DOEPMSK); + stm32_putreg(regval, STM32_OTGFS_DOEPMSK); /* Unmask IN interrupts */ regval = (OTGFS_DIEPMSK_XFRCM | OTGFS_DIEPMSK_EPDM | OTGFS_DIEPMSK_TOM); - stm32l4_putreg(regval, STM32_OTGFS_DIEPMSK); + stm32_putreg(regval, STM32_OTGFS_DIEPMSK); /* Reset device address to 0 */ - stm32l4_setaddress(priv, 0); + stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; priv->usbdev.speed = USB_SPEED_FULL; /* Re-configure EP0 */ - stm32l4_ep0_configure(priv); + stm32_ep0_configure(priv); /* Setup EP0 to receive SETUP packets */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_testmode + * Name: stm32_ep0out_testmode * * Description: * Select test mode * ****************************************************************************/ -static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0out_testmode(struct stm32_usbdev_s *priv, uint16_t index) { uint8_t testmode; @@ -2219,11 +2219,11 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, } priv->dotest = true; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } /**************************************************************************** - * Name: stm32l4_ep0out_stdrequest + * Name: stm32_ep0out_stdrequest * * Description: * Handle a standard request on EP0. Pick off the things of interest to @@ -2232,10 +2232,10 @@ static inline void stm32l4_ep0out_testmode(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ctrlreq_s *ctrlreq) +void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + struct stm32_ctrlreq_s *ctrlreq) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Handle standard request */ @@ -2265,7 +2265,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { usbtrace(TRACE_INTDECODE( STM32_TRACEINTID_EPGETSTATUS), 0); - privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); if (!privep) { usbtrace(TRACE_DEVERROR( @@ -2284,7 +2284,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } } break; @@ -2304,7 +2304,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, USB_FEATURE_REMOTEWAKEUP); priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } else { @@ -2322,7 +2322,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, priv->ep0data[0] = 0; priv->ep0data[1] = 0; - stm32l4_ep0in_setupresponse(priv, priv->ep0data, 2); + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); } break; @@ -2352,23 +2352,23 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_clrstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 0; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } } else @@ -2393,29 +2393,29 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; if (recipient == USB_REQ_RECIPIENT_ENDPOINT && ctrlreq->value == USB_FEATURE_ENDPOINTHALT && - (privep = stm32l4_ep_findbyaddr(priv, ctrlreq->index)) != + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) { - stm32l4_ep_setstall(privep); - stm32l4_ep0in_transmitzlp(priv); + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) { priv->wakeup = 1; - stm32l4_ep0in_transmitzlp(priv); + stm32_ep0in_transmitzlp(priv); } else if (recipient == USB_REQ_RECIPIENT_DEVICE && ctrlreq->value == USB_FEATURE_TESTMODE && ((ctrlreq->index & 0xff) == 0)) { - stm32l4_ep0out_testmode(priv, ctrlreq->index); + stm32_ep0out_testmode(priv, ctrlreq->index); } else if (priv->configured) { /* Actually, I think we could just stall here. */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2452,8 +2452,8 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * address until the completion of the status phase. */ - stm32l4_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); - stm32l4_ep0in_transmitzlp(priv); + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); } else { @@ -2482,7 +2482,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2508,7 +2508,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, ctrlreq->index == 0 && ctrlreq->len == 1) { - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { @@ -2535,7 +2535,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { /* Give the configuration to the class driver */ - int ret = stm32l4_req_dispatch(priv, &priv->ctrlreq); + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); /* If the class driver accepted the configuration, then mark the * device state as configured (or not, depending on the @@ -2581,7 +2581,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } break; @@ -2607,7 +2607,7 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_ep0out_setup + * Name: stm32_ep0out_setup * * Description: * USB Ctrl EP Setup Event. This is logically part of the USB interrupt @@ -2615,9 +2615,9 @@ void stm32l4_ep0out_stdrequest(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ctrlreq_s ctrlreq; + struct stm32_ctrlreq_s ctrlreq; /* Verify that a SETUP was received */ @@ -2629,8 +2629,8 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) /* Terminate any pending requests */ - stm32l4_req_cancel(&priv->epout[EP0], -EPROTO); - stm32l4_req_cancel(&priv->epin[EP0], -EPROTO); + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); /* Assume NOT stalled */ @@ -2660,13 +2660,13 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) { /* Dispatch any non-standard requests */ - stm32l4_req_dispatch(priv, &priv->ctrlreq); + stm32_req_dispatch(priv, &priv->ctrlreq); } else { /* Handle standard requests. */ - stm32l4_ep0out_stdrequest(priv, &ctrlreq); + stm32_ep0out_stdrequest(priv, &ctrlreq); } /* Check if the setup processing resulted in a STALL */ @@ -2675,7 +2675,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); - stm32l4_ep0_stall(priv); + stm32_ep0_stall(priv); } /* Reset state/data associated with the SETUP request */ @@ -2684,7 +2684,7 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epout + * Name: stm32_epout * * Description: * This is part of the OUT endpoint interrupt processing. This function @@ -2692,10 +2692,10 @@ static inline void stm32l4_ep0out_setup(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, +static inline void stm32_epout(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; /* Endpoint 0 is a special case. */ @@ -2712,7 +2712,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epout_complete(priv, privep); + stm32_epout_complete(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2720,7 +2720,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2732,12 +2732,12 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, else if (priv->devstate == DEVSTATE_CONFIGURED) { - stm32l4_epout_complete(priv, &priv->epout[epno]); + stm32_epout_complete(priv, &priv->epout[epno]); } } /**************************************************************************** - * Name: stm32l4_epout_interrupt + * Name: stm32_epout_interrupt * * Description: * USB OUT endpoint interrupt handler. @@ -2750,7 +2750,7 @@ static inline void stm32l4_epout(struct stm32l4_usbdev_s *priv, * ****************************************************************************/ -static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epout_interrupt(struct stm32_usbdev_s *priv) { uint32_t daint; uint32_t regval; @@ -2761,8 +2761,8 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - regval = stm32l4_getreg(STM32_OTGFS_DAINT); - regval &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINT); + regval &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; if (daint == 0) @@ -2777,7 +2777,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - regval = stm32l4_getreg(STM32_OTGFS_DAINT); + regval = stm32_getreg(STM32_OTGFS_DAINT); daint = (regval & OTGFS_DAINT_OEP_MASK) >> OTGFS_DAINT_OEP_SHIFT; usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), @@ -2788,9 +2788,9 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { if ((daint & 1) != 0) { - regval = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); + regval = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); uinfo("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(epno)); } epno++; @@ -2811,11 +2811,11 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) { /* Yes.. get the OUT endpoint interrupt status */ - doepint = stm32l4_getreg(STM32_OTGFS_DOEPINT(epno)); - doepint &= stm32l4_getreg(STM32_OTGFS_DOEPMSK); + doepint = stm32_getreg(STM32_OTGFS_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTGFS_DOEPMSK); /* Transfer completed interrupt. - * This interrupt is triggered when stm32l4_rxinterrupt() removes + * This interrupt is triggered when stm32_rxinterrupt() removes * the last packet data from the RxFIFO. * In this case, core internally sets the NAK bit for this endpoint * to prevent it from receiving any more packets. @@ -2828,12 +2828,12 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_XFRC, + stm32_putreg(OTGFS_DOEPINT_XFRC, STM32_OTGFS_DOEPINT(epno)); /* Handle the RX transfer data ready event */ - stm32l4_epout(priv, epno); + stm32_epout(priv, epno); } /* Endpoint disabled interrupt (ignored because this interrupt is @@ -2849,7 +2849,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) /* Clear the bit in DOEPINTn for this interrupt */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(epno)); } #endif @@ -2868,10 +2868,10 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_SETUP_READY) { - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } - stm32l4_putreg(OTGFS_DOEPINT_SETUP, + stm32_putreg(OTGFS_DOEPINT_SETUP, STM32_OTGFS_DOEPINT(epno)); } } @@ -2882,7 +2882,7 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epin_runtestmode + * Name: stm32_epin_runtestmode * * Description: * Execute the test mode setup by the SET FEATURE request @@ -2890,19 +2890,19 @@ static inline void stm32l4_epout_interrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) +void stm32_epin_runtestmode(struct stm32_usbdev_s *priv) { - uint32_t regval = stm32l4_getreg(STM32_OTGFS_DCTL); + uint32_t regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= OTGFS_DCTL_TCTL_MASK; regval |= (uint32_t)priv->testmode << OTGFS_DCTL_TCTL_SHIFT; - stm32l4_putreg(regval , STM32_OTGFS_DCTL); + stm32_putreg(regval , STM32_OTGFS_DCTL); priv->dotest = 0; priv->testmode = OTGFS_TESTMODE_DISABLED; } /**************************************************************************** - * Name: stm32l4_epin + * Name: stm32_epin * * Description: * This is part of the IN endpoint interrupt processing. This function @@ -2910,10 +2910,10 @@ void stm32l4_epin_runtestmode(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, +static inline void stm32_epin(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Endpoint 0 is a special case. */ @@ -2927,7 +2927,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the EP0 OUT request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); /* If we are not actively processing an OUT request, then we * need to setup to receive the next control request. @@ -2935,7 +2935,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (!privep->active) { - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); priv->ep0state = EP0STATE_IDLE; } } @@ -2944,7 +2944,7 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, if (priv->dotest) { - stm32l4_epin_runtestmode(priv); + stm32_epin_runtestmode(priv); } } @@ -2956,12 +2956,12 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, { /* Continue processing data from the endpoint write request queue */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } /**************************************************************************** - * Name: stm32l4_epin_txfifoempty + * Name: stm32_epin_txfifoempty * * Description: * TxFIFO empty interrupt handling @@ -2969,20 +2969,20 @@ static inline void stm32l4_epin(struct stm32l4_usbdev_s *priv, ****************************************************************************/ static inline -void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) +void stm32_epin_txfifoempty(struct stm32_usbdev_s *priv, int epno) { - struct stm32l4_ep_s *privep = &priv->epin[epno]; + struct stm32_ep_s *privep = &priv->epin[epno]; /* Continue processing the write request queue. This may mean sending * more data from the existing request or terminating the current requests * and (perhaps) starting the IN transfer from the next write request. */ - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } /**************************************************************************** - * Name: stm32l4_epin_interrupt + * Name: stm32_epin_interrupt * * Description: * USB IN endpoint interrupt handler. The core generates this interrupt @@ -2994,7 +2994,7 @@ void stm32l4_epin_txfifoempty(struct stm32l4_usbdev_s *priv, int epno) * ****************************************************************************/ -static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_epin_interrupt(struct stm32_usbdev_s *priv) { uint32_t diepint; uint32_t daint; @@ -3006,8 +3006,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * endpoint interrupt status register. */ - daint = stm32l4_getreg(STM32_OTGFS_DAINT); - daint &= stm32l4_getreg(STM32_OTGFS_DAINTMSK); + daint = stm32_getreg(STM32_OTGFS_DAINT); + daint &= stm32_getreg(STM32_OTGFS_DAINTMSK); daint &= OTGFS_DAINT_IEP_MASK; if (daint == 0) @@ -3022,7 +3022,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * It works by clearing each endpoint flags, masked or not. */ - daint = stm32l4_getreg(STM32_OTGFS_DAINT); + daint = stm32_getreg(STM32_OTGFS_DAINT); usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), (uint16_t)daint); @@ -3034,8 +3034,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) if ((daint & 1) != 0) { uerr("DIEPINT(%d) = %08" PRIx32 "\n", - epno, stm32l4_getreg(STM32_OTGFS_DIEPINT(epno))); - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); + epno, stm32_getreg(STM32_OTGFS_DIEPINT(epno))); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(epno)); } epno++; @@ -3059,7 +3059,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * register. */ - mask = stm32l4_getreg(STM32_OTGFS_DIEPMSK); + mask = stm32_getreg(STM32_OTGFS_DIEPMSK); /* Check if the TxFIFO not empty interrupt is enabled for this * endpoint in the DIEPMSK register. Bits n corresponds to @@ -3068,7 +3068,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * no TXFE bit in the mask register, so we fake one here. */ - empty = stm32l4_getreg(STM32_OTGFS_DIEPEMPMSK); + empty = stm32_getreg(STM32_OTGFS_DIEPEMPMSK); if ((empty & OTGFS_DIEPEMPMSK(epno)) != 0) { mask |= OTGFS_DIEPINT_TXFE; @@ -3078,7 +3078,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) * interrupts. */ - diepint = stm32l4_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; + diepint = stm32_getreg(STM32_OTGFS_DIEPINT(epno)) & mask; /* Decode and process the enabled, pending interrupts */ @@ -3096,13 +3096,13 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(OTGFS_DIEPINT_XFRC, + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(OTGFS_DIEPINT_XFRC, STM32_OTGFS_DIEPINT(epno)); /* IN transfer complete */ - stm32l4_epin(priv, epno); + stm32_epin(priv, epno); } /* Timeout condition */ @@ -3111,7 +3111,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); + stm32_putreg(OTGFS_DIEPINT_TOC, STM32_OTGFS_DIEPINT(epno)); } /* IN token received when TxFIFO is empty. Applies to non-periodic @@ -3125,8 +3125,8 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); - stm32l4_epin_request(priv, &priv->epin[epno]); - stm32l4_putreg(OTGFS_DIEPINT_ITTXFE, + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTGFS_DIEPINT_ITTXFE, STM32_OTGFS_DIEPINT(epno)); } @@ -3138,7 +3138,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3151,7 +3151,7 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, + stm32_putreg(OTGFS_DIEPINT_EPDISD, STM32_OTGFS_DIEPINT(epno)); } #endif @@ -3176,16 +3176,16 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) */ empty &= ~OTGFS_DIEPEMPMSK(epno); - stm32l4_putreg(empty, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(empty, STM32_OTGFS_DIEPEMPMSK); /* Handle TxFIFO empty */ - stm32l4_epin_txfifoempty(priv, epno); + stm32_epin_txfifoempty(priv, epno); } /* Clear the pending TxFIFO empty interrupt */ - stm32l4_putreg(OTGFS_DIEPINT_TXFE, + stm32_putreg(OTGFS_DIEPINT_TXFE, STM32_OTGFS_DIEPINT(epno)); } } @@ -3196,34 +3196,34 @@ static inline void stm32l4_epin_interrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_resumeinterrupt + * Name: stm32_resumeinterrupt * * Description: * Resume/remote wakeup detected interrupt * ****************************************************************************/ -static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_resumeinterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Restart the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Clear remote wake-up signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Notify the class driver of the resume event */ @@ -3234,7 +3234,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_suspendinterrupt + * Name: stm32_suspendinterrupt * * Description: * USB suspend interrupt @@ -3242,7 +3242,7 @@ static inline void stm32l4_resumeinterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ static inline -void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_suspendinterrupt(struct stm32_usbdev_s *priv) { #ifdef CONFIG_USBDEV_LOWPOWER uint32_t regval; @@ -3261,7 +3261,7 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * connected to the host, and that we have been configured. */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) { @@ -3269,16 +3269,16 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * PHY clock. */ - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval |= OTGFS_PCGCCTL_STPPCLK; - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); /* Setting OTGFS_PCGCCTL_GATEHCLK gate HCLK to modules other than * the AHB Slave and Master and wakeup logic. */ regval |= OTGFS_PCGCCTL_GATEHCLK; - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); } #endif @@ -3286,11 +3286,11 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_rxinterrupt + * Name: stm32_rxinterrupt * * Description: * RxFIFO non-empty interrupt. This interrupt indicates that there is at @@ -3298,18 +3298,18 @@ void stm32l4_suspendinterrupt(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_rxinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint32_t regval; int bcnt; int epphy; - while (0 != (stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) + while (0 != (stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_RXFLVL)) { /* Get the status from the top of the FIFO */ - regval = stm32l4_getreg(STM32_OTGFS_GRXSTSP); + regval = stm32_getreg(STM32_OTGFS_GRXSTSP); /* Decode status fields */ @@ -3357,7 +3357,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) OTGFS_GRXSTSD_BCNT_SHIFT; if (bcnt > 0) { - stm32l4_epout_receive(privep, bcnt); + stm32_epout_receive(privep, bcnt); } } break; @@ -3420,7 +3420,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) * packets and only that last SETUP packet will be processed. */ - stm32l4_rxfifo_read(&priv->epout[EP0], + stm32_rxfifo_read(&priv->epout[EP0], (uint8_t *)&priv->ctrlreq, USB_SIZEOF_CTRLREQ); @@ -3439,7 +3439,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) { /* Reset the endpoint and Stop NAK-ing */ - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); /* Wait for the data phase. */ @@ -3452,7 +3452,7 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) */ priv->ep0state = EP0STATE_SETUP_READY; - stm32l4_ep0out_setup(priv); + stm32_ep0out_setup(priv); } } break; @@ -3470,33 +3470,33 @@ static inline void stm32l4_rxinterrupt(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_enuminterrupt + * Name: stm32_enuminterrupt * * Description: * Enumeration done interrupt * ****************************************************************************/ -static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Activate EP0 */ - stm32l4_ep0in_activate(); + stm32_ep0in_activate(); /* Set USB turn-around time for the full speed device with internal * PHY interface. */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_TRDT_MASK; regval |= OTGFS_GUSBCFG_TRDT(6); - stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); } /**************************************************************************** - * Name: stm32l4_isocininterrupt + * Name: stm32_isocininterrupt * * Description: * Incomplete isochronous IN transfer interrupt. Assertion of the @@ -3506,7 +3506,7 @@ static inline void stm32l4_enuminterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_ISOCHRONOUS -static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_isocininterrupt(struct stm32_usbdev_s *priv) { int i; @@ -3539,8 +3539,8 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32_OTGFS_DSTS); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3561,16 +3561,16 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DIEPCTL_USBAEP too" - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_isocoutinterrupt + * Name: stm32_isocoutinterrupt * * Description: * Incomplete periodic transfer interrupt @@ -3579,10 +3579,10 @@ static inline void stm32l4_isocininterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_ISOCHRONOUS static inline -void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) +void stm32_isocoutinterrupt(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; - struct stm32l4_req_s *privreq; + struct stm32_ep_s *privep; + struct stm32_req_s *privreq; uint32_t regaddr; uint32_t doepctl; uint32_t dsts; @@ -3623,8 +3623,8 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) /* Check if this is the endpoint that had the incomplete transfer */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - doepctl = stm32l4_getreg(regaddr); - dsts = stm32l4_getreg(STM32_OTGFS_DSTS); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTGFS_DSTS); /* EONUM = 0:even frame, 1:odd frame * SOFFN = Frame number of the received SOF @@ -3645,16 +3645,16 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) * disable the endpoint. */ - stm32l4_req_complete(privep, -EIO); + stm32_req_complete(privep, -EIO); #warning "Will clear OTGFS_DOEPCTL_USBAEP too" - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); break; } } #endif /**************************************************************************** - * Name: stm32l4_sessioninterrupt + * Name: stm32_sessioninterrupt * * Description: * Session request/new session detected interrupt @@ -3663,14 +3663,14 @@ void stm32l4_isocoutinterrupt(struct stm32l4_usbdev_s *priv) #ifdef CONFIG_USBDEV_VBUSSENSING static inline -void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) +void stm32_sessioninterrupt(struct stm32_usbdev_s *priv) { #warning "Missing logic" } #endif /**************************************************************************** - * Name: stm32l4_otginterrupt + * Name: stm32_otginterrupt * * Description: * OTG interrupt @@ -3678,13 +3678,13 @@ void stm32l4_sessioninterrupt(struct stm32l4_usbdev_s *priv) ****************************************************************************/ #ifdef CONFIG_USBDEV_VBUSSENSING -static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) +static inline void stm32_otginterrupt(struct stm32_usbdev_s *priv) { uint32_t regval; /* Check for session end detected */ - regval = stm32l4_getreg(STM32_OTGFS_GOTGINT); + regval = stm32_getreg(STM32_OTGFS_GOTGINT); if ((regval & OTGFS_GOTGINT_SEDET) != 0) { #warning "Missing logic" @@ -3692,19 +3692,19 @@ static inline void stm32l4_otginterrupt(struct stm32l4_usbdev_s *priv) /* Clear OTG interrupt */ - stm32l4_putreg(regval, STM32_OTGFS_GOTGINT); + stm32_putreg(regval, STM32_OTGFS_GOTGINT); } #endif /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt * * Description: * USB interrupt handler * ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* At present, there is only a single OTG FS device support. Hence it is * pre-allocated as g_otgfsdev. However, in most code, the private data @@ -3713,7 +3713,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; uint32_t regval; uint32_t reserved; @@ -3721,7 +3721,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Assure that we are in device mode */ - DEBUGASSERT((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == + DEBUGASSERT((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINTSTS_CMOD) == OTGFS_GINTSTS_DEVMODE); /* Get the state of all enabled interrupts. We will do this repeatedly @@ -3733,15 +3733,15 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Get the set of pending, un-masked interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); reserved = (regval & OTGFS_GINT_RESERVED); - regval &= stm32l4_getreg(STM32_OTGFS_GINTMSK); + regval &= stm32_getreg(STM32_OTGFS_GINTMSK); /* With out modifying the reserved bits, acknowledge all * **Writable** pending irqs we will service below */ - stm32l4_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), + stm32_putreg(((regval | reserved) & OTGFS_GINT_RC_W1), STM32_OTGFS_GINTSTS); /* Break out of the loop when there are no further pending (and @@ -3764,7 +3764,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); - stm32l4_epout_interrupt(priv); + stm32_epout_interrupt(priv); } /* IN endpoint interrupt. The core sets this bit to indicate that @@ -3775,7 +3775,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); - stm32l4_epin_interrupt(priv); + stm32_epin_interrupt(priv); } /* Host/device mode mismatch error interrupt */ @@ -3794,7 +3794,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); - stm32l4_resumeinterrupt(priv); + stm32_resumeinterrupt(priv); } /* USB suspend interrupt */ @@ -3803,7 +3803,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); - stm32l4_suspendinterrupt(priv); + stm32_suspendinterrupt(priv); } /* Start of frame interrupt */ @@ -3813,7 +3813,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); - usbdev_sof_irq(&priv->usbdev, stm32l4_getframe(&priv->usbdev)); + usbdev_sof_irq(&priv->usbdev, stm32_getframe(&priv->usbdev)); } #endif @@ -3825,7 +3825,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); - stm32l4_rxinterrupt(priv); + stm32_rxinterrupt(priv); } /* USB reset interrupt */ @@ -3837,7 +3837,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Perform the device reset */ - stm32l4_usbreset(priv); + stm32_usbreset(priv); usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), priv->ep0state); return OK; } @@ -3848,7 +3848,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); - stm32l4_enuminterrupt(priv); + stm32_enuminterrupt(priv); } /* Incomplete isochronous IN transfer interrupt. When the core finds @@ -3862,7 +3862,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); - stm32l4_isocininterrupt(priv); + stm32_isocininterrupt(priv); } /* Incomplete isochronous OUT transfer. For isochronous OUT @@ -3879,7 +3879,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); - stm32l4_isocoutinterrupt(priv); + stm32_isocoutinterrupt(priv); } #endif @@ -3890,7 +3890,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); - stm32l4_sessioninterrupt(priv); + stm32_sessioninterrupt(priv); } /* OTG interrupt */ @@ -3899,7 +3899,7 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); - stm32l4_otginterrupt(priv); + stm32_otginterrupt(priv); } #endif } @@ -3913,28 +3913,28 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_enablegonak + * Name: stm32_enablegonak * * Description: * Enable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) +static void stm32_enablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* First, make sure that there is no GNOAKEFF interrupt pending. */ #if 0 - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #endif /* Enable Global OUT NAK mode in the core. */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_SGONAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); #if 0 /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK @@ -3942,8 +3942,8 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * from the RxFIFO, the core sets the GONAKEFF interrupt. */ - while ((stm32l4_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); - stm32l4_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); + while ((stm32_getreg(STM32_OTGFS_GINTSTS) & OTGFS_GINT_GONAKEFF) == 0); + stm32_putreg(OTGFS_GINT_GONAKEFF, STM32_OTGFS_GINTSTS); #else /* Since we are in the interrupt handler, we cannot wait inline for the @@ -3954,31 +3954,31 @@ static void stm32l4_enablegonak(struct stm32l4_ep_s *privep) * reported in OTGFS DCTL register? */ - while ((stm32l4_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); + while ((stm32_getreg(STM32_OTGFS_DCTL) & OTGFS_DCTL_GONSTS) == 0); #endif } /**************************************************************************** - * Name: stm32l4_disablegonak + * Name: stm32_disablegonak * * Description: * Disable global OUT NAK mode * ****************************************************************************/ -static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) +static void stm32_disablegonak(struct stm32_ep_s *privep) { uint32_t regval; /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_CGONAK; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } /**************************************************************************** - * Name: stm32l4_epout_configure + * Name: stm32_epout_configure * * Description: * Configure an OUT endpoint, making it usable @@ -3990,7 +3990,7 @@ static void stm32l4_disablegonak(struct stm32l4_ep_s *privep) * ****************************************************************************/ -static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, +static int stm32_epout_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { uint32_t mpsiz; @@ -4043,7 +4043,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DOEPCTL_USBAEP) == 0) { if (regval & OTGFS_DOEPCTL_NAKSTS) @@ -4055,7 +4055,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, regval |= mpsiz; regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT); regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4066,14 +4066,14 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_epin_configure + * Name: stm32_epin_configure * * Description: * Configure an IN endpoint, making it usable @@ -4085,7 +4085,7 @@ static int stm32l4_epout_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, +static int stm32_epin_configure(struct stm32_ep_s *privep, uint8_t eptype, uint16_t maxpacket) { @@ -4139,7 +4139,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { if (regval & OTGFS_DIEPCTL_NAKSTS) @@ -4153,7 +4153,7 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT); regval |= (privep->epphy << OTGFS_DIEPCTL_TXFNUM_SHIFT); regval |= (OTGFS_DIEPCTL_SD0PID | OTGFS_DIEPCTL_USBAEP); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Save the endpoint configuration */ @@ -4164,15 +4164,15 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, /* Enable the interrupt for this endpoint */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval |= OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); return OK; } /**************************************************************************** - * Name: stm32l4_ep_configure + * Name: stm32_ep_configure * * Description: * Configure endpoint, making it usable @@ -4186,11 +4186,11 @@ static int stm32l4_epin_configure(struct stm32l4_ep_s *privep, * ****************************************************************************/ -static int stm32l4_ep_configure(struct usbdev_ep_s *ep, +static int stm32_ep_configure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t maxpacket; uint8_t eptype; int ret; @@ -4207,43 +4207,43 @@ static int stm32l4_ep_configure(struct usbdev_ep_s *ep, if (privep->isin) { - ret = stm32l4_epin_configure(privep, eptype, maxpacket); + ret = stm32_epin_configure(privep, eptype, maxpacket); } else { - ret = stm32l4_epout_configure(privep, eptype, maxpacket); + ret = stm32_epout_configure(privep, eptype, maxpacket); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0_configure + * Name: stm32_ep0_configure * * Description: * Reset Usb engine * ****************************************************************************/ -static void stm32l4_ep0_configure(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_configure(struct stm32_usbdev_s *priv) { /* Enable EP0 IN and OUT */ - stm32l4_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); - stm32l4_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, CONFIG_USBDEV_EP0_MAXSIZE); } /**************************************************************************** - * Name: stm32l4_epout_disable + * Name: stm32_epout_disable * * Description: * Disable an OUT endpoint will no longer be used * ****************************************************************************/ -static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) +static void stm32_epout_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4258,17 +4258,17 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) */ flags = enter_critical_section(); - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits * int DOECPTL register. */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DOEPCTL_USBAEP; regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. @@ -4276,7 +4276,7 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) #if 0 /* Doesn't happen */ regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4285,36 +4285,36 @@ static void stm32l4_epout_disable(struct stm32l4_ep_s *privep) /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); + stm32_putreg(OTGFS_DOEPINT_EPDISD, STM32_OTGFS_DOEPINT(privep->epphy)); /* Then disable the Global OUT NAK mode to continue receiving data * from other non-disabled OUT endpoints. */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_OEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued read requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_epin_disable + * Name: stm32_epin_disable * * Description: * Disable an IN endpoint when it will no longer be used * ****************************************************************************/ -static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) +static void stm32_epin_disable(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4327,7 +4327,7 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); if ((regval & OTGFS_DIEPCTL_USBAEP) == 0) { return; @@ -4342,26 +4342,26 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) * to poll this bit below). */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); + stm32_putreg(OTGFS_DIEPINT_INEPNE, STM32_OTGFS_DIEPINT(privep->epphy)); /* Set the endpoint in NAK mode */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the INEPNE interrupt that indicates that we are now in * NAK mode */ regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_INEPNE) == 0); /* Clear the INEPNE interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_INEPNE, regaddr); + stm32_putreg(OTGFS_DIEPINT_INEPNE, regaddr); #endif /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits @@ -4370,49 +4370,49 @@ static void stm32l4_epin_disable(struct stm32l4_ep_s *privep) flags = enter_critical_section(); regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~OTGFS_DIEPCTL_USBAEP; regval |= (OTGFS_DIEPCTL_EPDIS | OTGFS_DIEPCTL_SNAK); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the IN * endpoint is completely disabled. */ regaddr = STM32_OTGFS_DIEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DIEPINT_EPDISD) == 0); /* Clear the EPDISD interrupt indication */ - stm32l4_putreg(OTGFS_DIEPINT_EPDISD, stm32l4_getreg(regaddr)); + stm32_putreg(OTGFS_DIEPINT_EPDISD, stm32_getreg(regaddr)); /* Flush any data remaining in the TxFIFO */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_D(privep->epphy)); /* Disable endpoint interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_DAINTMSK); + regval = stm32_getreg(STM32_OTGFS_DAINTMSK); regval &= ~OTGFS_DAINT_IEP(privep->epphy); - stm32l4_putreg(regval, STM32_OTGFS_DAINTMSK); + stm32_putreg(regval, STM32_OTGFS_DAINTMSK); /* Cancel any queued write requests */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); } /**************************************************************************** - * Name: stm32l4_ep_disable + * Name: stm32_ep_disable * * Description: * The endpoint will no longer be used * ****************************************************************************/ -static int stm32l4_ep_disable(struct usbdev_ep_s *ep) +static int stm32_ep_disable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -4430,29 +4430,29 @@ static int stm32l4_ep_disable(struct usbdev_ep_s *ep) { /* Disable the IN endpoint */ - stm32l4_epin_disable(privep); + stm32_epin_disable(privep); } else { /* Disable the OUT endpoint */ - stm32l4_epout_disable(privep); + stm32_epout_disable(privep); } return OK; } /**************************************************************************** - * Name: stm32l4_ep_allocreq + * Name: stm32_ep_allocreq * * Description: * Allocate an I/O request * ****************************************************************************/ -static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_ep_allocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -4462,32 +4462,32 @@ static struct usbdev_req_s *stm32l4_ep_allocreq(struct usbdev_ep_s *ep) } #endif - usbtrace(TRACE_EPALLOCREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCREQ, ((struct stm32_ep_s *)ep)->epphy); - privreq = (struct stm32l4_req_s *) - kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = (struct stm32_req_s *) + kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_ep_freereq + * Name: stm32_ep_freereq * * Description: * Free an I/O request * ****************************************************************************/ -static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, +static void stm32_ep_freereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) @@ -4497,12 +4497,12 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, } #endif - usbtrace(TRACE_EPFREEREQ, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEREQ, ((struct stm32_ep_s *)ep)->epphy); kmm_free(privreq); } /**************************************************************************** - * Name: stm32l4_ep_allocbuffer + * Name: stm32_ep_allocbuffer * * Description: * Allocate an I/O buffer @@ -4510,10 +4510,10 @@ static void stm32l4_ep_freereq(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, +static void *stm32_ep_allocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) { - usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPALLOCBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY return usbdev_dma_alloc(bytes); @@ -4524,7 +4524,7 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, #endif /**************************************************************************** - * Name: stm32l4_ep_freebuffer + * Name: stm32_ep_freebuffer * * Description: * Free an I/O buffer @@ -4532,9 +4532,9 @@ static void *stm32l4_ep_allocbuffer(struct usbdev_ep_s *ep, ****************************************************************************/ #ifdef CONFIG_USBDEV_DMA -static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) +static void stm32_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) { - usbtrace(TRACE_EPFREEBUFFER, ((struct stm32l4_ep_s *)ep)->epphy); + usbtrace(TRACE_EPFREEBUFFER, ((struct stm32_ep_s *)ep)->epphy); #ifdef CONFIG_USBDEV_DMAMEMORY usbdev_dma_free(buf); @@ -4545,19 +4545,19 @@ static void stm32l4_ep_freebuffer(struct usbdev_ep_s *ep, void *buf) #endif /**************************************************************************** - * Name: stm32l4_ep_submit + * Name: stm32_ep_submit * * Description: * Submit an I/O request to the endpoint * ****************************************************************************/ -static int stm32l4_ep_submit(struct usbdev_ep_s *ep, +static int stm32_ep_submit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; int ret = OK; @@ -4604,7 +4604,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, { /* Add the new request to the request queue for the endpoint. */ - if (stm32l4_req_addlast(privep, privreq) && !privep->active) + if (stm32_req_addlast(privep, privreq) && !privep->active) { /* If a request was added to an IN endpoint, then attempt to send * the request data buffer now. @@ -4620,7 +4620,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, if (!privep->active) { - stm32l4_epin_request(priv, privep); + stm32_epin_request(priv, privep); } } @@ -4632,7 +4632,7 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, else { usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); - stm32l4_epout_request(priv, privep); + stm32_epout_request(priv, privep); } } } @@ -4642,17 +4642,17 @@ static int stm32l4_ep_submit(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_ep_cancel + * Name: stm32_ep_cancel * * Description: * Cancel an I/O request previously sent to an endpoint * ****************************************************************************/ -static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, +static int stm32_ep_cancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_FEATURES @@ -4673,20 +4673,20 @@ static int stm32l4_ep_cancel(struct usbdev_ep_s *ep, * but ... all other implementations cancel all requests ... */ - stm32l4_req_cancel(privep, -ESHUTDOWN); + stm32_req_cancel(privep, -ESHUTDOWN); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epout_setstall + * Name: stm32_epout_setstall * * Description: * Stall an OUT endpoint * ****************************************************************************/ -static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) +static int stm32_epout_setstall(struct stm32_ep_s *privep) { #if 1 /* This implementation follows the requirements from the STM32 F4 reference @@ -4698,16 +4698,16 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Put the core in the Global OUT NAK mode */ - stm32l4_enablegonak(privep); + stm32_enablegonak(privep); /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits * in the DOECPTL register. */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= (OTGFS_DOEPCTL_EPDIS | OTGFS_DOEPCTL_STALL); - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* Wait for the EPDISD interrupt which indicates that the OUT * endpoint is completely disabled. @@ -4715,7 +4715,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) #if 0 /* Doesn't happen */ regaddr = STM32_OTGFS_DOEPINT(privep->epphy); - while ((stm32l4_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); + while ((stm32_getreg(regaddr) & OTGFS_DOEPINT_EPDISD) == 0); #else /* REVISIT: */ @@ -4724,7 +4724,7 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) /* Disable Global OUT NAK mode */ - stm32l4_disablegonak(privep); + stm32_disablegonak(privep); /* The endpoint is now stalled */ @@ -4743,9 +4743,9 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) */ regaddr = STM32_OTGFS_DOEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval |= OTGFS_DOEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4755,14 +4755,14 @@ static int stm32l4_epout_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_epin_setstall + * Name: stm32_epin_setstall * * Description: * Stall an IN endpoint * ****************************************************************************/ -static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) +static int stm32_epin_setstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4770,12 +4770,12 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) /* Get the IN endpoint device control register */ regaddr = STM32_OTGFS_DIEPCTL(privep->epphy); - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); /* Then stall the endpoint */ regval |= OTGFS_DIEPCTL_STALL; - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is now stalled */ @@ -4784,14 +4784,14 @@ static int stm32l4_epin_setstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_setstall + * Name: stm32_ep_setstall * * Description: * Stall an endpoint * ****************************************************************************/ -static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) +static int stm32_ep_setstall(struct stm32_ep_s *privep) { usbtrace(TRACE_EPSTALL, privep->epphy); @@ -4799,23 +4799,23 @@ static int stm32l4_ep_setstall(struct stm32l4_ep_s *privep) if (privep->isin == 1) { - return stm32l4_epin_setstall(privep); + return stm32_epin_setstall(privep); } else { - return stm32l4_epout_setstall(privep); + return stm32_epout_setstall(privep); } } /**************************************************************************** - * Name: stm32l4_ep_clrstall + * Name: stm32_ep_clrstall * * Description: * Resume a stalled endpoint * ****************************************************************************/ -static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) +static int stm32_ep_clrstall(struct stm32_ep_s *privep) { uint32_t regaddr; uint32_t regval; @@ -4845,7 +4845,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) /* Clear the stall bit */ - regval = stm32l4_getreg(regaddr); + regval = stm32_getreg(regaddr); regval &= ~stallbit; /* Set the DATA0 pid for interrupt and bulk endpoints */ @@ -4858,7 +4858,7 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) regval |= data0bit; } - stm32l4_putreg(regval, regaddr); + stm32_putreg(regval, regaddr); /* The endpoint is no longer stalled */ @@ -4867,16 +4867,16 @@ static int stm32l4_ep_clrstall(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_ep_stall + * Name: stm32_ep_stall * * Description: * Stall or resume an endpoint * ****************************************************************************/ -static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) +static int stm32_ep_stall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; int ret; @@ -4885,11 +4885,11 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) flags = enter_critical_section(); if (resume) { - ret = stm32l4_ep_clrstall(privep); + ret = stm32_ep_clrstall(privep); } else { - ret = stm32l4_ep_setstall(privep); + ret = stm32_ep_setstall(privep); } leave_critical_section(flags); @@ -4898,19 +4898,19 @@ static int stm32l4_ep_stall(struct usbdev_ep_s *ep, bool resume) } /**************************************************************************** - * Name: stm32l4_ep0_stall + * Name: stm32_ep0_stall * * Description: * Stall endpoint 0 * ****************************************************************************/ -static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) +static void stm32_ep0_stall(struct stm32_usbdev_s *priv) { - stm32l4_epin_setstall(&priv->epin[EP0]); - stm32l4_epout_setstall(&priv->epout[EP0]); + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); priv->stalled = true; - stm32l4_ep0out_ctrlsetup(priv); + stm32_ep0out_ctrlsetup(priv); } /**************************************************************************** @@ -4918,7 +4918,7 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_ep_alloc + * Name: stm32_ep_alloc * * Description: * Allocate an endpoint matching the parameters. @@ -4933,11 +4933,11 @@ static void stm32l4_ep0_stall(struct stm32l4_usbdev_s *priv) * ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_ep_alloc(struct usbdev_s *dev, uint8_t eplog, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint8_t epavail; irqstate_t flags; int epphy; @@ -5013,18 +5013,18 @@ static struct usbdev_ep_s *stm32l4_ep_alloc(struct usbdev_s *dev, } /**************************************************************************** - * Name: stm32l4_ep_free + * Name: stm32_ep_free * * Description: * Free the previously allocated endpoint * ****************************************************************************/ -static void stm32l4_ep_free(struct usbdev_s *dev, +static void stm32_ep_free(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); @@ -5040,14 +5040,14 @@ static void stm32l4_ep_free(struct usbdev_s *dev, } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Returns the current frame number * ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint32_t regval; @@ -5055,21 +5055,21 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number of the last SOF detected by the hardware */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); return (int)((regval & OTGFS_DSTS_SOFFN_MASK) >> OTGFS_DSTS_SOFFN_SHIFT); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup * * Description: * Exit suspend mode. * ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; uint32_t regval; irqstate_t flags; @@ -5082,24 +5082,24 @@ static int stm32l4_wakeup(struct usbdev_s *dev) { /* Yes... is the core suspended? */ - regval = stm32l4_getreg(STM32_OTGFS_DSTS); + regval = stm32_getreg(STM32_OTGFS_DSTS); if ((regval & OTGFS_DSTS_SUSPSTS) != 0) { /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ #ifdef CONFIG_USBDEV_LOWPOWER - regval = stm32l4_getreg(STM32_OTGFS_PCGCCTL); + regval = stm32_getreg(STM32_OTGFS_PCGCCTL); regval &= ~(OTGFS_PCGCCTL_STPPCLK | OTGFS_PCGCCTL_GATEHCLK); - stm32l4_putreg(regval, STM32_OTGFS_PCGCCTL); + stm32_putreg(regval, STM32_OTGFS_PCGCCTL); #endif /* Activate Remote wakeup signaling */ - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); regval |= OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); up_mdelay(5); regval &= ~OTGFS_DCTL_RWUSIG; - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); } } @@ -5108,16 +5108,16 @@ static int stm32l4_wakeup(struct usbdev_s *dev) } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered * * Description: * Sets/clears the device self-powered feature * ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); @@ -5134,21 +5134,21 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup * * Description: * Software-controlled connect to/disconnect from USB host * ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = stm32l4_getreg(STM32_OTGFS_DCTL); + regval = stm32_getreg(STM32_OTGFS_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL @@ -5166,30 +5166,30 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval |= OTGFS_DCTL_SDIS; } - stm32l4_putreg(regval, STM32_OTGFS_DCTL); + stm32_putreg(regval, STM32_OTGFS_DCTL); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_setaddress + * Name: stm32_setaddress * * Description: * Set the devices USB address * ****************************************************************************/ -static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) { uint32_t regval; /* Set the device address in the DCFG register */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DAD_MASK; regval |= ((uint32_t)address << OTGFS_DCFG_DAD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Are we now addressed? (i.e., do we have a non-NULL device * address?) @@ -5208,14 +5208,14 @@ static void stm32l4_setaddress(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_txfifo_flush + * Name: stm32_txfifo_flush * * Description: * Flush the specific TX fifo. * ****************************************************************************/ -static int stm32l4_txfifo_flush(uint32_t txfnum) +static int stm32_txfifo_flush(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5223,13 +5223,13 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(regval, STM32_OTGFS_GRSTCTL); + stm32_putreg(regval, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5243,27 +5243,27 @@ static int stm32l4_txfifo_flush(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_rxfifo_flush + * Name: stm32_rxfifo_flush * * Description: * Flush the RX fifo. * ****************************************************************************/ -static int stm32l4_rxfifo_flush(void) +static int stm32_rxfifo_flush(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); + stm32_putreg(OTGFS_GRSTCTL_RXFFLSH, STM32_OTGFS_GRSTCTL); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5277,21 +5277,21 @@ static int stm32l4_rxfifo_flush(void) } /**************************************************************************** - * Name: stm32l4_swinitialize + * Name: stm32_swinitialize * * Description: * Initialize all driver data structures. * ****************************************************************************/ -static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_swinitialize(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; int i; /* Initialize the device state structure */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->epin[EP0].ep; @@ -5356,14 +5356,14 @@ static void stm32l4_swinitialize(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_hwinitialize + * Name: stm32_hwinitialize * * Description: * Configure the OTG FS core for operation. * ****************************************************************************/ -static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) +static void stm32_hwinitialize(struct stm32_usbdev_s *priv) { uint32_t regval; uint32_t timeout; @@ -5372,7 +5372,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* At start-up the core is in FS mode. */ @@ -5382,7 +5382,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); + stm32_putreg(OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); /* Common USB OTG core initialization */ @@ -5393,7 +5393,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5402,10 +5402,10 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); + stm32_putreg(OTGFS_GRSTCTL_CSRST, STM32_OTGFS_GRSTCTL); for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5426,48 +5426,48 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GCCFG_VBDEN; #endif - stm32l4_putreg(regval, STM32_OTGFS_GCCFG); + stm32_putreg(regval, STM32_OTGFS_GCCFG); up_mdelay(20); /* When VBUS sensing is not used we need to force the B session valid */ #ifndef CONFIG_USBDEV_VBUSSENSING - regval = stm32l4_getreg(STM32_OTGFS_GOTGCTL); + regval = stm32_getreg(STM32_OTGFS_GOTGCTL); regval |= (OTGFS_GOTGCTL_BVALOEN | OTGFS_GOTGCTL_BVALOVAL); - stm32l4_putreg(regval, STM32_OTGFS_GOTGCTL); + stm32_putreg(regval, STM32_OTGFS_GOTGCTL); #endif /* Force Device Mode */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FHMOD; regval |= OTGFS_GUSBCFG_FDMOD; - stm32l4_putreg(regval, STM32_OTGFS_GUSBCFG); + stm32_putreg(regval, STM32_OTGFS_GUSBCFG); up_mdelay(50); /* Initialize device mode */ /* Restart the PHY Clock */ - stm32l4_putreg(0, STM32_OTGFS_PCGCCTL); + stm32_putreg(0, STM32_OTGFS_PCGCCTL); /* Device configuration register */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_PFIVL_MASK; regval |= OTGFS_DCFG_PFIVL_80PCT; - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set full speed PHY */ - regval = stm32l4_getreg(STM32_OTGFS_DCFG); + regval = stm32_getreg(STM32_OTGFS_DCFG); regval &= ~OTGFS_DCFG_DSPD_MASK; regval |= OTGFS_DCFG_DSPD_FS; - stm32l4_putreg(regval, STM32_OTGFS_DCFG); + stm32_putreg(regval, STM32_OTGFS_DCFG); /* Set Rx FIFO size */ - stm32l4_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTGFS_GRXFSIZ); #if STM32_NENDPOINTS > 0 /* EP0 TX */ @@ -5475,7 +5475,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address = STM32_RXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF0_TX0FD_SHIFT) | (STM32_EP0_TXFIFO_WORDS << OTGFS_DIEPTXF0_TX0FSA_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF0); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF0); #endif #if STM32_NENDPOINTS > 1 @@ -5484,7 +5484,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP0_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP1_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(1)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(1)); #endif #if STM32_NENDPOINTS > 2 @@ -5493,7 +5493,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP1_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP2_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(2)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(2)); #endif #if STM32_NENDPOINTS > 3 @@ -5502,7 +5502,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP2_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP3_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(3)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(3)); #endif #if STM32_NENDPOINTS > 4 @@ -5511,7 +5511,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP3_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP4_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(4)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(4)); #endif #if STM32_NENDPOINTS > 5 @@ -5520,27 +5520,27 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) address += STM32_EP4_TXFIFO_WORDS; regval = (address << OTGFS_DIEPTXF_INEPTXSA_SHIFT) | (STM32_EP5_TXFIFO_WORDS << OTGFS_DIEPTXF_INEPTXFD_SHIFT); - stm32l4_putreg(regval, STM32_OTGFS_DIEPTXF(5)); + stm32_putreg(regval, STM32_OTGFS_DIEPTXF(5)); #endif /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* Clear all pending Device Interrupts */ - stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); - stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); /* Configure all IN endpoints */ for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32_OTGFS_DIEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DIEPCTL(i)); if ((regval & OTGFS_DIEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5552,16 +5552,16 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32_OTGFS_DIEPCTL(i)); - stm32l4_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DIEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); } /* Configure all OUT endpoints */ for (i = 0; i < STM32_NENDPOINTS; i++) { - regval = stm32l4_getreg(STM32_OTGFS_DOEPCTL(i)); + regval = stm32_getreg(STM32_OTGFS_DOEPCTL(i)); if ((regval & OTGFS_DOEPCTL_EPENA) != 0) { /* The endpoint is already enabled */ @@ -5573,24 +5573,24 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval = 0; } - stm32l4_putreg(regval, STM32_OTGFS_DOEPCTL(i)); - stm32l4_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(regval, STM32_OTGFS_DOEPCTL(i)); + stm32_putreg(0, STM32_OTGFS_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } /* Disable all interrupts. */ - stm32l4_putreg(0, STM32_OTGFS_GINTMSK); + stm32_putreg(0, STM32_OTGFS_GINTMSK); /* Clear any pending USB_OTG Interrupts */ - stm32l4_putreg(0xffffffff, STM32_OTGFS_GOTGINT); + stm32_putreg(0xffffffff, STM32_OTGFS_GOTGINT); /* Clear any pending interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTSTS); + regval = stm32_getreg(STM32_OTGFS_GINTSTS); regval &= OTGFS_GINT_RESERVED; - stm32l4_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); + stm32_putreg(regval | OTGFS_GINT_RC_W1, STM32_OTGFS_GINTSTS); /* Enable the interrupts in the INTMSK */ @@ -5613,7 +5613,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) regval |= OTGFS_GINT_MMIS; #endif - stm32l4_putreg(regval, STM32_OTGFS_GINTMSK); + stm32_putreg(regval, STM32_OTGFS_GINTMSK); /* Enable the USB global interrupt by setting GINTMSK in the global OTG * FS AHB configuration register; Set the TXFELVL bit in the GAHBCFG @@ -5621,7 +5621,7 @@ static void stm32l4_hwinitialize(struct stm32l4_usbdev_s *priv) * empty (not just half full). */ - stm32l4_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, + stm32_putreg(OTGFS_GAHBCFG_GINTMSK | OTGFS_GAHBCFG_TXFELVL, STM32_OTGFS_GAHBCFG); } @@ -5653,7 +5653,7 @@ void arm_usbinitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVINIT, 0); @@ -5681,14 +5681,14 @@ void arm_usbinitialize(void) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable. */ #ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Uninitialize the hardware so that we know that we are starting from a @@ -5699,11 +5699,11 @@ void arm_usbinitialize(void) /* Initialize the driver data structure */ - stm32l4_swinitialize(priv); + stm32_swinitialize(priv); /* Attach the OTG FS interrupt handler */ - ret = irq_attach(STM32_IRQ_OTGFS, stm32l4_usbinterrupt, NULL); + ret = irq_attach(STM32_IRQ_OTGFS, stm32_usbinterrupt, NULL); if (ret < 0) { uerr("ERROR: irq_attach failed: %d\n", ret); @@ -5712,15 +5712,15 @@ void arm_usbinitialize(void) /* Initialize the USB OTG core */ - stm32l4_hwinitialize(priv); + stm32_hwinitialize(priv); /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Reset/Re-initialize the USB hardware */ - stm32l4_usbreset(priv); + stm32_usbreset(priv); /* Enable USB controller interrupts at the NVIC */ @@ -5744,7 +5744,7 @@ void arm_usbuninitialize(void) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; int i; @@ -5759,7 +5759,7 @@ void arm_usbuninitialize(void) /* Disconnect device */ flags = enter_critical_section(); - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable and detach IRQs */ @@ -5771,20 +5771,20 @@ void arm_usbuninitialize(void) for (i = 0; i < STM32_NENDPOINTS; i++) { - stm32l4_putreg(0xff, STM32_OTGFS_DIEPINT(i)); - stm32l4_putreg(0xff, STM32_OTGFS_DOEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTGFS_DOEPINT(i)); } - stm32l4_putreg(0, STM32_OTGFS_DIEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DOEPMSK); - stm32l4_putreg(0, STM32_OTGFS_DIEPEMPMSK); - stm32l4_putreg(0, STM32_OTGFS_DAINTMSK); - stm32l4_putreg(0xffffffff, STM32_OTGFS_DAINT); + stm32_putreg(0, STM32_OTGFS_DIEPMSK); + stm32_putreg(0, STM32_OTGFS_DOEPMSK); + stm32_putreg(0, STM32_OTGFS_DIEPEMPMSK); + stm32_putreg(0, STM32_OTGFS_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTGFS_DAINT); /* Flush the FIFOs */ - stm32l4_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); - stm32l4_rxfifo_flush(); + stm32_txfifo_flush(OTGFS_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); /* TODO: Turn off USB power and clocking */ @@ -5810,7 +5810,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -5856,7 +5856,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * that logic to the class drivers but left this logic here. */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -5883,7 +5883,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * devices. */ - struct stm32l4_usbdev_s *priv = &g_otgfsdev; + struct stm32_usbdev_s *priv = &g_otgfsdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -5901,7 +5901,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_usbreset(priv); + stm32_usbreset(priv); leave_critical_section(flags); /* Unbind the class driver */ @@ -5915,7 +5915,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) /* Disconnect device */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Unhook the driver */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index 955e9d78d80..41d83c9592f 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -154,7 +154,7 @@ * state machine (for debug purposes only) */ -enum stm32l4_smstate_e +enum stm32_smstate_e { SMSTATE_DETACHED = 0, /* Not attached to a device */ SMSTATE_ATTACHED, /* Attached to a device */ @@ -164,7 +164,7 @@ enum stm32l4_smstate_e /* This enumeration provides the reason for the channel halt. */ -enum stm32l4_chreason_e +enum stm32_chreason_e { CHREASON_IDLE = 0, /* Inactive (initial state) */ CHREASON_FREED, /* Channel is no longer in use */ @@ -180,15 +180,15 @@ enum stm32l4_chreason_e /* This structure retains the state of one host channel. NOTE: Since there * is only one channel operation active at a time, some of the fields in - * in the structure could be moved in struct stm32l4_ubhost_s to achieve + * in the structure could be moved in struct stm32_ubhost_s to achieve * some memory savings. */ -struct stm32l4_chan_s +struct stm32_chan_s { sem_t waitsem; /* Channel wait semaphore */ volatile uint8_t result; /* The result of the transfer */ - volatile uint8_t chreason; /* Channel halt reason. See enum stm32l4_chreason_e */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ uint8_t chidx; /* Channel index */ uint8_t epno; /* Device endpoint number (0-127) */ uint8_t eptype; /* See OTGFS_EPTYPE_* definitions */ @@ -218,7 +218,7 @@ struct stm32l4_chan_s * the endpoint. */ -struct stm32l4_ctrlinfo_s +struct stm32_ctrlinfo_s { uint8_t inndx; /* EP0 IN control channel index */ uint8_t outndx; /* EP0 OUT control channel index */ @@ -226,7 +226,7 @@ struct stm32l4_ctrlinfo_s /* This structure retains the state of the USB host controller */ -struct stm32l4_usbhost_s +struct stm32_usbhost_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbhost_s @@ -248,7 +248,7 @@ struct stm32l4_usbhost_s volatile bool pscwait; /* True: Thread is waiting for a port event */ mutex_t lock; /* Support mutually exclusive access */ sem_t pscsem; /* Semaphore to wait for a port event */ - struct stm32l4_ctrlinfo_s ep0; /* Root hub port EP0 description */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ #ifdef CONFIG_USBHOST_HUB /* Used to pass external hub port events */ @@ -260,7 +260,7 @@ struct stm32l4_usbhost_s /* The state of each host channel */ - struct stm32l4_chan_s chan[STM32_MAX_TX_FIFOS]; + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; }; /**************************************************************************** @@ -270,96 +270,96 @@ struct stm32l4_usbhost_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite); -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite); -static uint32_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint32_t addr, uint32_t value); +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); #else -# define stm32l4_getreg(addr) getreg32(addr) -# define stm32l4_putreg(addr,val) putreg32(val,addr) +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) #endif -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); #ifdef CONFIG_STM32L4_USBHOST_PKTDUMP -# define stm32l4_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else -# define stm32l4_pktdump(m,b,n) +# define stm32_pktdump(m,b,n) #endif /* Byte stream access helper functions **************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val); +static inline uint16_t stm32_getle16(const uint8_t *val); /* Channel management *******************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, +static int stm32_chan_alloc(struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv); -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv); +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, - int chidx, enum stm32l4_chreason_e chreason); -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); +static void stm32_chan_halt(struct stm32_usbhost_s *priv, + int chidx, enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep); -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, + struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); /* Control/data transfer logic **********************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx); #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void); +static inline uint16_t stm32_getframe(void); #endif -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req); -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen); -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx); -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan); -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan); +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif @@ -368,106 +368,106 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, /* Lower level interrupt handlers */ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen); -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx); -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx); -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv); -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv); +static void stm32_gint_connected(struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ #ifdef CONFIG_STM32L4_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv); +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void -stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv); +stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv); static inline void -stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv); -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv); +stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv); /* First level, global interrupt handler */ -static int stm32l4_gint_isr(int irq, void *context, void *arg); +static int stm32_gint_isr(int irq, void *context, void *arg); /* Interrupt controls */ -static void stm32l4_gint_enable(void); -static void stm32l4_gint_disable(void); -static inline void stm32l4_hostinit_enable(void); -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx); /* USB host controller operations *******************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport); -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport); -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize); -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep); -static int stm32l4_epfree(struct usbhost_driver_s *drvr, +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep); -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen); -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen); -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer); -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer); -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer); -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen); #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg); #endif -static int stm32l4_cancel(struct usbhost_driver_s *drvr, +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep); #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected); #endif -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport); /* Initialization ***********************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv); -static void stm32l4_flush_txfifos(uint32_t txfnum); -static void stm32l4_flush_rxfifo(void); -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, +static void stm32_portreset(struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state); -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv); +static void stm32_host_initialize(struct stm32_usbhost_s *priv); -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv); -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv); /**************************************************************************** * Private Data @@ -478,7 +478,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv); * single global instance. */ -static struct stm32l4_usbhost_s g_usbhost = +static struct stm32_usbhost_s g_usbhost = { .lock = NXMUTEX_INITIALIZER, .pscsem = SEM_INITIALIZER(0), @@ -488,8 +488,8 @@ static struct stm32l4_usbhost_s g_usbhost = static struct usbhost_connection_s g_usbconn = { - .wait = stm32l4_wait, - .enumerate = stm32l4_enumerate, + .wait = stm32_wait, + .enumerate = stm32_enumerate, }; /**************************************************************************** @@ -497,7 +497,7 @@ static struct usbhost_connection_s g_usbconn = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_printreg + * Name: stm32_printreg * * Description: * Print the contents of an STM32xx register operation @@ -505,14 +505,14 @@ static struct usbhost_connection_s g_usbconn = ****************************************************************************/ #ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { lldbg("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); } #endif /**************************************************************************** - * Name: stm32l4_checkreg + * Name: stm32_checkreg * * Description: * Get the contents of an STM32 register @@ -520,7 +520,7 @@ static void stm32l4_printreg(uint32_t addr, uint32_t val, bool iswrite) ****************************************************************************/ #ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; static uint32_t preval = 0; @@ -551,7 +551,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* Yes.. Just one */ - stm32l4_printreg(prevaddr, preval, prevwrite); + stm32_printreg(prevaddr, preval, prevwrite); } else { @@ -570,13 +570,13 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) /* Show the new regisgter access */ - stm32l4_printreg(addr, val, iswrite); + stm32_printreg(addr, val, iswrite); } } #endif /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg * * Description: * Get the contents of an STM32 register @@ -584,7 +584,7 @@ static void stm32l4_checkreg(uint32_t addr, uint32_t val, bool iswrite) ****************************************************************************/ #ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static uint32_t stm32l4_getreg(uint32_t addr) +static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -592,13 +592,13 @@ static uint32_t stm32l4_getreg(uint32_t addr) /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, false); + stm32_checkreg(addr, val, false); return val; } #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg * * Description: * Set the contents of an STM32 register to a value @@ -606,11 +606,11 @@ static uint32_t stm32l4_getreg(uint32_t addr) ****************************************************************************/ #ifdef CONFIG_STM32L4_USBHOST_REGDEBUG -static void stm32l4_putreg(uint32_t addr, uint32_t val) +static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ - stm32l4_checkreg(addr, val, true); + stm32_checkreg(addr, val, true); /* Write the value */ @@ -619,41 +619,41 @@ static void stm32l4_putreg(uint32_t addr, uint32_t val) #endif /**************************************************************************** - * Name: stm32l4_modifyreg + * Name: stm32_modifyreg * * Description: * Modify selected bits of an STM32 register. * ****************************************************************************/ -static inline void stm32l4_modifyreg(uint32_t addr, uint32_t clrbits, +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits) { - stm32l4_putreg(addr, (((stm32l4_getreg(addr)) & ~clrbits) | setbits)); + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); } /**************************************************************************** - * Name: stm32l4_getle16 + * Name: stm32_getle16 * * Description: * Get a (possibly unaligned) 16-bit little endian value. * ****************************************************************************/ -static inline uint16_t stm32l4_getle16(const uint8_t *val) +static inline uint16_t stm32_getle16(const uint8_t *val) { return (uint16_t)val[1] << 8 | (uint16_t)val[0]; } /**************************************************************************** - * Name: stm32l4_chan_alloc + * Name: stm32_chan_alloc * * Description: * Allocate a channel. * ****************************************************************************/ -static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) +static int stm32_chan_alloc(struct stm32_usbhost_s *priv) { int chidx; @@ -678,20 +678,20 @@ static int stm32l4_chan_alloc(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_chan_free + * Name: stm32_chan_free * * Description: * Free a previoiusly allocated channel. * ****************************************************************************/ -static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) +static void stm32_chan_free(struct stm32_usbhost_s *priv, int chidx) { DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_FREED); + stm32_chan_halt(priv, chidx, CHREASON_FREED); /* Mark the channel available */ @@ -699,14 +699,14 @@ static void stm32l4_chan_free(struct stm32l4_usbhost_s *priv, int chidx) } /**************************************************************************** - * Name: stm32l4_chan_freeall + * Name: stm32_chan_freeall * * Description: * Free all channels. * ****************************************************************************/ -static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) +static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv) { uint8_t chidx; @@ -714,12 +714,12 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx++) { - stm32l4_chan_free(priv, chidx); + stm32_chan_free(priv, chidx); } } /**************************************************************************** - * Name: stm32l4_chan_configure + * Name: stm32_chan_configure * * Description: * Configure or re-configure a host channel. Host channels are configured @@ -728,15 +728,15 @@ static inline void stm32l4_chan_freeall(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, +static void stm32_chan_configure(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; /* Clear any old pending interrupts for this host channel. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINT(chidx), 0xffffffff); /* Enable channel interrupts required for transfers on this channel. */ @@ -836,15 +836,15 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, break; } - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Enable the top level host channel interrupt. */ - stm32l4_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); + stm32_modifyreg(STM32_OTGFS_HAINTMSK, 0, OTGFS_HAINT(chidx)); /* Make sure host channel interrupts are enabled. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); + stm32_modifyreg(STM32_OTGFS_GINTMSK, 0, OTGFS_GINT_HC); /* Program the HCCHAR register */ @@ -876,11 +876,11 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, /* Write the channel configuration */ - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } /**************************************************************************** - * Name: stm32l4_chan_halt + * Name: stm32_chan_halt * * Description: * Halt the channel associated with 'chidx' by setting the CHannel DISable @@ -888,8 +888,8 @@ static void stm32l4_chan_configure(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, - enum stm32l4_chreason_e chreason) +static void stm32_chan_halt(struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) { uint32_t hcchar; uint32_t intmsk; @@ -913,7 +913,7 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * transaction that has already been started on the USB." */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); hcchar |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); /* Get the endpoint type from the HCCHAR register */ @@ -935,14 +935,14 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32_OTGFS_HNPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HNPTXSTS) & OTGFS_HNPTXSTS_NPTXFSAV_MASK; } else { /* Get the number of words available in the non-periodic Tx FIFO. */ - avail = stm32l4_getreg(STM32_OTGFS_HPTXSTS) & + avail = stm32_getreg(STM32_OTGFS_HPTXSTS) & OTGFS_HPTXSTS_PTXFSAVL_MASK; } @@ -957,17 +957,17 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, /* Unmask the CHannel Halted (CHH) interrupt */ - intmsk = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + intmsk = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); intmsk |= OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), intmsk); /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } /**************************************************************************** - * Name: stm32l4_chan_waitsetup + * Name: stm32_chan_waitsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -982,8 +982,8 @@ static void stm32l4_chan_halt(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_waitsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags = enter_critical_section(); int ret = -ENODEV; @@ -1010,7 +1010,7 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_asynchsetup + * Name: stm32_chan_asynchsetup * * Description: * Set the request for the transfer complete event well BEFORE enabling @@ -1025,8 +1025,8 @@ static int stm32l4_chan_waitsetup(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan, +static int stm32_chan_asynchsetup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan, usbhost_asynch_t callback, void *arg) { irqstate_t flags = enter_critical_section(); @@ -1053,7 +1053,7 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_chan_wait + * Name: stm32_chan_wait * * Description: * Wait for a transfer on a channel to complete. @@ -1063,8 +1063,8 @@ static int stm32l4_chan_asynchsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static int stm32_chan_wait(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { irqstate_t flags; int ret; @@ -1102,7 +1102,7 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_chan_wakeup + * Name: stm32_chan_wakeup * * Description: * A channel transfer has completed... wakeup any threads waiting for the @@ -1114,8 +1114,8 @@ static int stm32l4_chan_wait(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_chan_wakeup(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { /* Is the transfer complete? */ @@ -1151,11 +1151,11 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, if (chan->in) { - stm32l4_in_next(priv, chan); + stm32_in_next(priv, chan); } else { - stm32l4_out_next(priv, chan); + stm32_out_next(priv, chan); } } #endif @@ -1163,23 +1163,23 @@ static void stm32l4_chan_wakeup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_ctrlchan_alloc + * Name: stm32_ctrlchan_alloc * * Description: * Allocate and configured channels for a control pipe. * ****************************************************************************/ -static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv, uint8_t epno, uint8_t funcaddr, uint8_t speed, - struct stm32l4_ctrlinfo_s *ctrlep) + struct stm32_ctrlinfo_s *ctrlep) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int inndx; int outndx; - outndx = stm32l4_chan_alloc(priv); + outndx = stm32_chan_alloc(priv); if (outndx < 0) { return -ENOMEM; @@ -1199,14 +1199,14 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, /* Configure control OUT channels */ - stm32l4_chan_configure(priv, outndx); + stm32_chan_configure(priv, outndx); /* Allocate and initialize the control IN channel */ - inndx = stm32l4_chan_alloc(priv); + inndx = stm32_chan_alloc(priv); if (inndx < 0) { - stm32l4_chan_free(priv, outndx); + stm32_chan_free(priv, outndx); return -ENOMEM; } @@ -1224,12 +1224,12 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, /* Configure control IN channels */ - stm32l4_chan_configure(priv, inndx); + stm32_chan_configure(priv, inndx); return OK; } /**************************************************************************** - * Name: stm32l4_ctrlep_alloc + * Name: stm32_ctrlep_alloc * * Description: * Allocate a container and channels for control pipe. @@ -1249,12 +1249,12 @@ static int stm32l4_ctrlchan_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_ctrlep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_ctrlinfo_s *ctrlep; + struct stm32_ctrlinfo_s *ctrlep; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -1266,8 +1266,8 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a container for the control endpoint */ - ctrlep = (struct stm32l4_ctrlinfo_s *) - kmm_malloc(sizeof(struct stm32l4_ctrlinfo_s)); + ctrlep = (struct stm32_ctrlinfo_s *) + kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); if (ctrlep == NULL) { uerr("ERROR: Failed to allocate control endpoint container\n"); @@ -1276,11 +1276,11 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, /* Then allocate and configure the IN/OUT channels */ - ret = stm32l4_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, hport->funcaddr, hport->speed, ctrlep); if (ret < 0) { - uerr("ERROR: stm32l4_ctrlchan_alloc failed: %d\n", ret); + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); kmm_free(ctrlep); return ret; } @@ -1292,7 +1292,7 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_xfrep_alloc + * Name: stm32_xfrep_alloc * * Description: * Allocate and configure one unidirectional endpoint. @@ -1312,12 +1312,12 @@ static int stm32l4_ctrlep_alloc(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, +static int stm32_xfrep_alloc(struct stm32_usbhost_s *priv, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { struct usbhost_hubport_s *hport; - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int chidx; /* Sanity check. NOTE that this method should only be called if a device @@ -1329,7 +1329,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Allocate a host channel for the endpoint */ - chidx = stm32l4_chan_alloc(priv); + chidx = stm32_chan_alloc(priv); if (chidx < 0) { uerr("ERROR: Failed to allocate a host channel\n"); @@ -1355,7 +1355,7 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, /* Then configure the endpoint */ - stm32l4_chan_configure(priv, chidx); + stm32_chan_configure(priv, chidx); /* Return the index to the allocated channel as the endpoint "handle" */ @@ -1364,17 +1364,17 @@ static int stm32l4_xfrep_alloc(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_transfer_start + * Name: stm32_transfer_start * * Description: * Start at transfer on the select IN or OUT channel. * ****************************************************************************/ -static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, +static void stm32_transfer_start(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int npackets; unsigned int maxpacket; @@ -1453,18 +1453,18 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval = ((uint32_t)chan->buflen << OTGFS_HCTSIZ_XFRSIZ_SHIFT) | ((uint32_t)npackets << OTGFS_HCTSIZ_PKTCNT_SHIFT) | ((uint32_t)chan->pid << OTGFS_HCTSIZ_DPID_SHIFT); - stm32l4_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); + stm32_putreg(STM32_OTGFS_HCTSIZ(chidx), regval); /* Setup the HCCHAR register: Frame oddness and host channel enable */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd * Frame. This field is applicable for only periodic (isochronous and * interrupt) channels. */ - if ((stm32l4_getreg(STM32_OTGFS_HFNUM) & 1) == 0) + if ((stm32_getreg(STM32_OTGFS_HFNUM) & 1) == 0) { regval |= OTGFS_HCCHAR_ODDFRM; } @@ -1475,7 +1475,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, regval &= ~OTGFS_HCCHAR_CHDIS; regval |= OTGFS_HCCHAR_CHENA; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* If this is an out transfer, then we need to do more.. we need to copy * the outgoing data into the correct TxFIFO. @@ -1496,7 +1496,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); avail = ((regval & OTGFS_HNPTXSTS_NPTXFSAV_MASK) >> OTGFS_HNPTXSTS_NPTXFSAV_SHIFT) << 2; } @@ -1509,7 +1509,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, { /* Read the Non-periodic Tx FIFO status register */ - regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); avail = ((regval & OTGFS_HPTXSTS_PTXFSAVL_MASK) >> OTGFS_HPTXSTS_PTXFSAVL_SHIFT) << 2; } @@ -1541,7 +1541,7 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, /* Write packet into the Tx FIFO. */ - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /* Did we put the entire buffer into the Tx FIFO? */ @@ -1553,13 +1553,13 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, * FIFO becomes empty. */ - stm32l4_txfe_enable(priv, chidx); + stm32_txfe_enable(priv, chidx); } } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe * * Description: * Get the current frame number. The frame number (FRNUM) field increments @@ -1569,26 +1569,26 @@ static void stm32l4_transfer_start(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #if 0 /* Not used */ -static inline uint16_t stm32l4_getframe(void) +static inline uint16_t stm32_getframe(void) { return (uint16_t) - (stm32l4_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); + (stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK); } #endif /**************************************************************************** - * Name: stm32l4_ctrl_sendsetup + * Name: stm32_ctrl_sendsetup * * Description: * Send an IN/OUT SETUP packet. * ****************************************************************************/ -static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_sendsetup(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, const struct usb_ctrlreq_s *req) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; int ret; @@ -1609,7 +1609,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1618,11 +1618,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Return on success and for all failures other than EAGAIN. EAGAIN * means that the device NAKed the SETUP command and that we should @@ -1653,7 +1653,7 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_ctrl_senddata + * Name: stm32_ctrl_senddata * * Description: * Send data in the data phase of an OUT control transfer. Or send status @@ -1661,11 +1661,11 @@ static int stm32l4_ctrl_sendsetup(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_senddata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->outndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; int ret; /* Save buffer information */ @@ -1689,7 +1689,7 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1698,15 +1698,15 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->outndx); + stm32_transfer_start(priv, ep0->outndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_ctrl_recvdata + * Name: stm32_ctrl_recvdata * * Description: * Receive data in the data phase of an IN control transfer. Or receive @@ -1714,11 +1714,11 @@ static int stm32l4_ctrl_senddata(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, - struct stm32l4_ctrlinfo_s *ep0, +static int stm32_ctrl_recvdata(struct stm32_usbhost_s *priv, + struct stm32_ctrlinfo_s *ep0, uint8_t *buffer, unsigned int buflen) { - struct stm32l4_chan_s *chan = &priv->chan[ep0->inndx]; + struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; int ret; /* Save buffer information */ @@ -1730,7 +1730,7 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1739,24 +1739,24 @@ static int stm32l4_ctrl_recvdata(struct stm32l4_usbhost_s *priv, /* Start the transfer */ - stm32l4_transfer_start(priv, ep0->inndx); + stm32_transfer_start(priv, ep0->inndx); /* Wait for the transfer to complete and return the result */ - return stm32l4_chan_wait(priv, chan); + return stm32_chan_wait(priv, chan); } /**************************************************************************** - * Name: stm32l4_in_setup + * Name: stm32_in_setup * * Description: * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_in_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -1803,23 +1803,23 @@ static int stm32l4_in_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_in_transfer + * Name: stm32_in_transfer * * Description: * Transfer 'buflen' bytes into 'buffer' from an IN channel. * ****************************************************************************/ -static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_in_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; ssize_t xfrd; int ret; @@ -1840,7 +1840,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, { /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -1849,16 +1849,16 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* EAGAIN indicates that the device NAKed the transfer. */ @@ -1973,7 +1973,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } } @@ -1993,7 +1993,7 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_in_next + * Name: stm32_in_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2004,8 +2004,8 @@ static ssize_t stm32l4_in_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_in_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2022,13 +2022,13 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_in_setup(priv, chan->chidx); + ret = stm32_in_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); result = ret; } @@ -2058,7 +2058,7 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_in_asynch + * Name: stm32_in_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2069,11 +2069,11 @@ static void stm32l4_in_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_in_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2083,19 +2083,19 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_in_setup(priv, chidx); + ret = stm32_in_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_in_setup failed: %d\n", ret); + uerr("ERROR: stm32_in_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2105,16 +2105,16 @@ static int stm32l4_in_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_out_setup + * Name: stm32_out_setup * * Description: * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. * ****************************************************************************/ -static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) +static int stm32_out_setup(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; /* Set up for the transfer based on the direction and the endpoint type */ @@ -2165,23 +2165,23 @@ static int stm32l4_out_setup(struct stm32l4_usbhost_s *priv, int chidx) /* Start the transfer */ - stm32l4_transfer_start(priv, chidx); + stm32_transfer_start(priv, chidx); return OK; } /**************************************************************************** - * Name: stm32l4_out_transfer + * Name: stm32_out_transfer * * Description: * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. * ****************************************************************************/ -static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, +static ssize_t stm32_out_transfer(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; clock_t start; clock_t elapsed; size_t xfrlen; @@ -2212,7 +2212,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the wait BEFORE starting the transfer */ - ret = stm32l4_chan_waitsetup(priv, chan); + ret = stm32_chan_waitsetup(priv, chan); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_DEVDISCONN, 0); @@ -2221,16 +2221,16 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, /* Set up for the transfer based on the direction and the endpoint */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); return (ssize_t)ret; } /* Wait for the transfer to complete and get the result */ - ret = stm32l4_chan_wait(priv, chan); + ret = stm32_chan_wait(priv, chan); /* Handle transfer failures */ @@ -2253,7 +2253,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, { /* Break out and return the error */ - uerr("ERROR: stm32l4_chan_wait failed: %d\n", ret); + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); return (ssize_t)ret; } @@ -2261,7 +2261,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, * the data in the FIFO when the NAK occurs? Does it discard it? */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); /* Get the device a little time to catch up. Then retry the * transfer using the same buffer pointer and length. @@ -2284,7 +2284,7 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_out_next + * Name: stm32_out_next * * Description: * Initiate the next of a sequence of asynchronous transfers. @@ -2295,8 +2295,8 @@ static ssize_t stm32l4_out_transfer(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, - struct stm32l4_chan_s *chan) +static void stm32_out_next(struct stm32_usbhost_s *priv, + struct stm32_chan_s *chan) { usbhost_asynch_t callback; void *arg; @@ -2313,13 +2313,13 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, * endpoint type */ - ret = stm32l4_out_setup(priv, chan->chidx); + ret = stm32_out_setup(priv, chan->chidx); if (ret >= 0) { return; } - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); result = ret; } @@ -2349,7 +2349,7 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, #endif /**************************************************************************** - * Name: stm32l4_out_asynch + * Name: stm32_out_asynch * * Description: * Initiate the first of a sequence of asynchronous transfers. @@ -2360,11 +2360,11 @@ static void stm32l4_out_next(struct stm32l4_usbhost_s *priv, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, +static int stm32_out_asynch(struct stm32_usbhost_s *priv, int chidx, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; int ret; /* Set up for the transfer BEFORE starting the first transfer */ @@ -2374,19 +2374,19 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, chan->buflen = buflen; chan->xfrd = 0; - ret = stm32l4_chan_asynchsetup(priv, chan, callback, arg); + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); if (ret < 0) { - uerr("ERROR: stm32l4_chan_asynchsetup failed: %d\n", ret); + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); return ret; } /* Set up for the transfer based on the direction and the endpoint type */ - ret = stm32l4_out_setup(priv, chidx); + ret = stm32_out_setup(priv, chidx); if (ret < 0) { - uerr("ERROR: stm32l4_out_setup failed: %d\n", ret); + uerr("ERROR: stm32_out_setup failed: %d\n", ret); } /* And return with the transfer pending */ @@ -2396,7 +2396,7 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, #endif /**************************************************************************** - * Name: stm32l4_gint_wrpacket + * Name: stm32_gint_wrpacket * * Description: * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with @@ -2404,14 +2404,14 @@ static int stm32l4_out_asynch(struct stm32l4_usbhost_s *priv, int chidx, * ****************************************************************************/ -static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, +static void stm32_gint_wrpacket(struct stm32_usbhost_s *priv, uint8_t *buffer, int chidx, int buflen) { uint32_t *src; uint32_t fifo; int buflen32; - stm32l4_pktdump("Sending", buffer, buflen); + stm32_pktdump("Sending", buffer, buflen); /* Get the number of 32-byte words associated with this byte size */ @@ -2427,7 +2427,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, for (; buflen32 > 0; buflen32--) { uint32_t data = *src++; - stm32l4_putreg(fifo, data); + stm32_putreg(fifo, data); } /* Increment the count of bytes "in-flight" in the Tx FIFO */ @@ -2436,7 +2436,7 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, } /**************************************************************************** - * Name: stm32l4_gint_hcinisr + * Name: stm32_gint_hcinisr * * Description: * USB OTG FS host IN channels interrupt handler @@ -2454,10 +2454,10 @@ static void stm32l4_gint_wrpacket(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcinisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2465,8 +2465,8 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2480,7 +2480,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2489,14 +2489,14 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the NAK and STALL Conditions. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_STALL)); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); /* When there is a STALL, clear any pending NAK so that it is not * processed below. @@ -2513,11 +2513,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the NAK and data toggle error conditions */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_NAK | OTGFS_HCINT_DTERR)); } @@ -2527,11 +2527,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the FRaMe OverRun (FRMOR) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2540,7 +2540,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Clear the TransFeR Completed (XFRC) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); /* Then handle the transfer completion event based on the endpoint */ @@ -2549,22 +2549,22 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear any pending NAK condition. The 'indata1' data toggle * should have been appropriately updated by the RxFIFO * logic as each packet was received. */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } else if (chan->eptype == OTGFS_EPTYPE_INTR) { /* Force the next transfer on an ODD frame */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_ODDFRM; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); /* Set the request done state */ @@ -2578,9 +2578,9 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); /* Update the request state based on the host state machine state */ @@ -2618,7 +2618,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, /* Clear the CHannel Halted (CHH) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2629,11 +2629,11 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the Transaction ERror (TXERR) condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2654,7 +2654,7 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); } /* Re-activate CTRL and BULK channels. @@ -2671,30 +2671,30 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * TODO: set channel reason to NACK? */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); regval |= OTGFS_HCCHAR_CHENA; regval &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), regval); } #else /* Halt all transfers on the NAK -- CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); #endif /* Clear the NAK condition */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_hcoutisr + * Name: stm32_gint_hcoutisr * * Description: * USB OTG FS host OUT channels interrupt handler @@ -2712,10 +2712,10 @@ static inline void stm32l4_gint_hcinisr(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, +static inline void stm32_gint_hcoutisr(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; uint32_t regval; uint32_t pending; @@ -2723,8 +2723,8 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * HCINTMSK register to get the set of enabled HC interrupts. */ - pending = stm32l4_getreg(STM32_OTGFS_HCINT(chidx)); - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + pending = stm32_getreg(STM32_OTGFS_HCINT(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); /* AND the two to get the set of enabled, pending HC interrupts */ @@ -2738,7 +2738,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending the ACK response received/transmitted interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_ACK); } /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ @@ -2747,11 +2747,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel (probably not necessary for FRMOR) */ - stm32l4_chan_halt(priv, chidx, CHREASON_FRMOR); + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_FRMOR); } /* Check for a pending TransFeR Completed (XFRC) interrupt */ @@ -2768,11 +2768,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_XFRC); + stm32_chan_halt(priv, chidx, CHREASON_XFRC); /* Clear the pending the TransFeR Completed (XFRC) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_XFRC); } /* Check for a pending STALL response receive (STALL) interrupt */ @@ -2781,13 +2781,13 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Clear the pending STALL response receive (STALL) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_STALL); /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_STALL); + stm32_chan_halt(priv, chidx, CHREASON_STALL); } /* Check for a pending NAK response received (NAK) interrupt */ @@ -2796,11 +2796,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel -- the CHH interrupt is expected next */ - stm32l4_chan_halt(priv, chidx, CHREASON_NAK); + stm32_chan_halt(priv, chidx, CHREASON_NAK); /* Clear the pending the NAK response received (NAK) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NAK); } /* Check for a pending Transaction ERror (TXERR) interrupt */ @@ -2811,11 +2811,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_TXERR); + stm32_chan_halt(priv, chidx, CHREASON_TXERR); /* Clear the pending the Transaction ERror (TXERR) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_TXERR); } /* Check for a NYET interrupt */ @@ -2825,11 +2825,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_NYET); + stm32_chan_halt(priv, chidx, CHREASON_NYET); /* Clear the pending the NYET interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_NYET); } #endif @@ -2841,11 +2841,11 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * received on the channel. */ - stm32l4_chan_halt(priv, chidx, CHREASON_DTERR); + stm32_chan_halt(priv, chidx, CHREASON_DTERR); /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), + stm32_putreg(STM32_OTGFS_HCINT(chidx), (OTGFS_HCINT_DTERR | OTGFS_HCINT_NAK)); } @@ -2855,9 +2855,9 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, { /* Mask the CHannel Halted (CHH) interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_HCINTMSK(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCINTMSK(chidx)); regval &= ~OTGFS_HCINT_CHH; - stm32l4_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); + stm32_putreg(STM32_OTGFS_HCINTMSK(chidx), regval); if (chan->chreason == CHREASON_XFRC) { @@ -2869,7 +2869,7 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, * the endpoint type. */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Is it a bulk endpoint? Were an odd number of packets * transferred? @@ -2913,23 +2913,23 @@ static inline void stm32l4_gint_hcoutisr(struct stm32l4_usbhost_s *priv, /* Clear the pending the CHannel Halted (CHH) interrupt */ - stm32l4_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); + stm32_putreg(STM32_OTGFS_HCINT(chidx), OTGFS_HCINT_CHH); } /* Check for a transfer complete event */ - stm32l4_chan_wakeup(priv, chan); + stm32_chan_wakeup(priv, chan); } /**************************************************************************** - * Name: stm32l4_gint_connected + * Name: stm32_gint_connected * * Description: * Handle a connection event. * ****************************************************************************/ -static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_connected(struct stm32_usbhost_s *priv) { /* We we previously disconnected? */ @@ -2954,14 +2954,14 @@ static void stm32l4_gint_connected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_disconnected + * Name: stm32_gint_disconnected * * Description: * Handle a disconnection event. * ****************************************************************************/ -static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) +static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) { /* Were we previously connected? */ @@ -2986,7 +2986,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) priv->smstate = SMSTATE_DETACHED; priv->connected = false; priv->change = true; - stm32l4_chan_freeall(priv); + stm32_chan_freeall(priv); priv->rhport.hport.speed = USB_SPEED_FULL; priv->rhport.hport.funcaddr = 0; @@ -3002,7 +3002,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_gint_sofisr + * Name: stm32_gint_sofisr * * Description: * USB OTG FS start-of-frame interrupt handler @@ -3010,7 +3010,7 @@ static void stm32l4_gint_disconnected(struct stm32l4_usbhost_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_OTGFS_SOFINTR -static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3018,19 +3018,19 @@ static inline void stm32l4_gint_sofisr(struct stm32l4_usbhost_s *priv) /* Clear pending SOF interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_SOF); } #endif /**************************************************************************** - * Name: stm32l4_gint_rxflvlisr + * Name: stm32_gint_rxflvlisr * * Description: * USB OTG FS RxFIFO non-empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_rxflvlisr(struct stm32_usbhost_s *priv) { uint32_t *dest; uint32_t grxsts; @@ -3045,13 +3045,13 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Disable the RxFIFO non-empty interrupt */ - intmsk = stm32l4_getreg(STM32_OTGFS_GINTMSK); + intmsk = stm32_getreg(STM32_OTGFS_GINTMSK); intmsk &= ~OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); /* Read and pop the next status from the Rx FIFO */ - grxsts = stm32l4_getreg(STM32_OTGFS_GRXSTSP); + grxsts = stm32_getreg(STM32_OTGFS_GRXSTSP); uinfo("GRXSTS: %08" PRIx32 "\n", grxsts); /* Isolate the channel number/index in the status word */ @@ -3060,7 +3060,7 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Get the host channel characteristics register (HCCHAR) */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(chidx)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(chidx)); /* Then process the interrupt according to the packet status */ @@ -3082,10 +3082,10 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) for (i = 0; i < bcnt32; i++) { - *dest++ = stm32l4_getreg(fifo); + *dest++ = stm32_getreg(fifo); } - stm32l4_pktdump("Received", priv->chan[chidx].buffer, bcnt); + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); /* Toggle the IN data pid (Used by Bulk and INTR only) */ @@ -3098,14 +3098,14 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Check if more packets are expected */ - hctsiz = stm32l4_getreg(STM32_OTGFS_HCTSIZ(chidx)); + hctsiz = stm32_getreg(STM32_OTGFS_HCTSIZ(chidx)); if ((hctsiz & OTGFS_HCTSIZ_PKTCNT_MASK) != 0) { /* Re-activate the channel when more packets are expected */ hcchar |= OTGFS_HCCHAR_CHENA; hcchar &= ~OTGFS_HCCHAR_CHDIS; - stm32l4_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); + stm32_putreg(STM32_OTGFS_HCCHAR(chidx), hcchar); } } } @@ -3121,20 +3121,20 @@ static inline void stm32l4_gint_rxflvlisr(struct stm32l4_usbhost_s *priv) /* Re-enable the RxFIFO non-empty interrupt */ intmsk |= OTGFS_GINT_RXFLVL; - stm32l4_putreg(STM32_OTGFS_GINTMSK, intmsk); + stm32_putreg(STM32_OTGFS_GINTMSK, intmsk); } /**************************************************************************** - * Name: stm32l4_gint_nptxfeisr + * Name: stm32_gint_nptxfeisr * * Description: * USB OTG FS non-periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_nptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3164,13 +3164,13 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); return; } /* Read the status from the top of the non-periodic TxFIFO */ - regval = stm32l4_getreg(STM32_OTGFS_HNPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HNPTXSTS); /* Extract the number of bytes available in the non-periodic Tx FIFO. */ @@ -3202,7 +3202,7 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_NPTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3211,20 +3211,20 @@ static inline void stm32l4_gint_nptxfeisr(struct stm32l4_usbhost_s *priv) "wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_ptxfeisr + * Name: stm32_gint_ptxfeisr * * Description: * USB OTG FS periodic TxFIFO empty interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ptxfeisr(struct stm32_usbhost_s *priv) { - struct stm32l4_chan_s *chan; + struct stm32_chan_s *chan; uint32_t regval; unsigned int wrsize; unsigned int avail; @@ -3254,13 +3254,13 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) { /* Disable further Tx FIFO empty interrupts and bail. */ - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); return; } /* Read the status from the top of the periodic TxFIFO */ - regval = stm32l4_getreg(STM32_OTGFS_HPTXSTS); + regval = stm32_getreg(STM32_OTGFS_HPTXSTS); /* Extract the number of bytes available in the periodic Tx FIFO. */ @@ -3292,7 +3292,7 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) else { - stm32l4_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); + stm32_modifyreg(STM32_OTGFS_GINTMSK, OTGFS_GINT_PTXFE, 0); } /* Write the next group of packets into the Tx FIFO */ @@ -3301,18 +3301,18 @@ static inline void stm32l4_gint_ptxfeisr(struct stm32l4_usbhost_s *priv) " buflen: %d xfrd: %d wrsize: %d\n", regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); - stm32l4_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); } /**************************************************************************** - * Name: stm32l4_gint_hcisr + * Name: stm32_gint_hcisr * * Description: * USB OTG FS host channels interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hcisr(struct stm32_usbhost_s *priv) { uint32_t haint; uint32_t hcchar; @@ -3323,7 +3323,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) * a pending interrupt on channel i. */ - haint = stm32l4_getreg(STM32_OTGFS_HAINT); + haint = stm32_getreg(STM32_OTGFS_HAINT); for (i = 0; i < STM32_NHOST_CHANNELS; i++) { /* Is an interrupt pending on this channel? */ @@ -3332,7 +3332,7 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Yes... read the HCCHAR register to get the direction bit */ - hcchar = stm32l4_getreg(STM32_OTGFS_HCCHAR(i)); + hcchar = stm32_getreg(STM32_OTGFS_HCCHAR(i)); /* Was this an interrupt on an IN or an OUT channel? */ @@ -3340,27 +3340,27 @@ static inline void stm32l4_gint_hcisr(struct stm32l4_usbhost_s *priv) { /* Handle the HC IN channel interrupt */ - stm32l4_gint_hcinisr(priv, i); + stm32_gint_hcinisr(priv, i); } else { /* Handle the HC OUT channel interrupt */ - stm32l4_gint_hcoutisr(priv, i); + stm32_gint_hcoutisr(priv, i); } } } } /**************************************************************************** - * Name: stm32l4_gint_hprtisr + * Name: stm32_gint_hprtisr * * Description: * USB OTG FS host port interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_hprtisr(struct stm32_usbhost_s *priv) { uint32_t hprt; uint32_t newhprt; @@ -3370,7 +3370,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Read the port status and control register (HPRT) */ - hprt = stm32l4_getreg(STM32_OTGFS_HPRT); + hprt = stm32_getreg(STM32_OTGFS_HPRT); /* Setup to clear the interrupt bits in GINTSTS by setting the * corresponding bits in the HPRT. The HCINT interrupt bit is cleared @@ -3402,8 +3402,8 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_PCDET, 0); newhprt |= OTGFS_HPRT_PCDET; - stm32l4_portreset(priv); - stm32l4_gint_connected(priv); + stm32_portreset(priv); + stm32_gint_connected(priv); } /* Check for Port Enable CHaNGed (PENCHNG) */ @@ -3421,11 +3421,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) { /* Yes.. handle the new connection event */ - stm32l4_gint_connected(priv); + stm32_gint_connected(priv); /* Check the Host ConFiGuration register (HCFG) */ - hcfg = stm32l4_getreg(STM32_OTGFS_HCFG); + hcfg = stm32_getreg(STM32_OTGFS_HCFG); /* Is this a low speed or full speed connection (OTG FS does not * support high speed) @@ -3436,7 +3436,7 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Set the Host Frame Interval Register for the 6KHz speed */ usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_LSDEV, 0); - stm32l4_putreg(STM32_OTGFS_HFIR, 6000); + stm32_putreg(STM32_OTGFS_HFIR, 6000); /* Are we switching from FS to LS? */ @@ -3449,17 +3449,17 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_LS6MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } else /* if ((hprt & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_FS) */ { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HPRT_FSDEV, 0); - stm32l4_putreg(STM32_OTGFS_HFIR, 48000); + stm32_putreg(STM32_OTGFS_HFIR, 48000); /* Are we switching from LS to FS? */ @@ -3472,11 +3472,11 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) hcfg &= ~OTGFS_HCFG_FSLSPCS_MASK; hcfg |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, hcfg); + stm32_putreg(STM32_OTGFS_HCFG, hcfg); /* And reset the port */ - stm32l4_portreset(priv); + stm32_portreset(priv); } } } @@ -3484,37 +3484,37 @@ static inline void stm32l4_gint_hprtisr(struct stm32l4_usbhost_s *priv) /* Clear port interrupts by setting bits in the HPRT */ - stm32l4_putreg(STM32_OTGFS_HPRT, newhprt); + stm32_putreg(STM32_OTGFS_HPRT, newhprt); } /**************************************************************************** - * Name: stm32l4_gint_discisr + * Name: stm32_gint_discisr * * Description: * USB OTG FS disconnect detected interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_discisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_discisr(struct stm32_usbhost_s *priv) { /* Handle the disconnection event */ - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); /* Clear the dicsonnect interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_DISC); } /**************************************************************************** - * Name: stm32l4_gint_ipxfrisr + * Name: stm32_gint_ipxfrisr * * Description: * USB OTG FS incomplete periodic interrupt handler * ****************************************************************************/ -static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) +static inline void stm32_gint_ipxfrisr(struct stm32_usbhost_s *priv) { uint32_t regval; @@ -3522,24 +3522,24 @@ static inline void stm32l4_gint_ipxfrisr(struct stm32l4_usbhost_s *priv) * CHDIS : Set to stop transmitting/receiving data on a channel */ - regval = stm32l4_getreg(STM32_OTGFS_HCCHAR(0)); + regval = stm32_getreg(STM32_OTGFS_HCCHAR(0)); regval |= (OTGFS_HCCHAR_CHDIS | OTGFS_HCCHAR_CHENA); - stm32l4_putreg(STM32_OTGFS_HCCHAR(0), regval); + stm32_putreg(STM32_OTGFS_HCCHAR(0), regval); /* Clear the incomplete isochronous OUT interrupt */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); + stm32_putreg(STM32_OTGFS_GINTSTS, OTGFS_GINT_IPXFR); } /**************************************************************************** - * Name: stm32l4_gint_isr + * Name: stm32_gint_isr * * Description: * USB OTG FS global interrupt handler * ****************************************************************************/ -static int stm32l4_gint_isr(int irq, void *context, void *arg) +static int stm32_gint_isr(int irq, void *context, void *arg) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -3548,7 +3548,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; uint32_t pending; /* If OTG were supported, we would need to check if we are in host or @@ -3564,8 +3564,8 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) { /* Get the unmasked bits in the GINT status */ - pending = stm32l4_getreg(STM32_OTGFS_GINTSTS); - pending &= stm32l4_getreg(STM32_OTGFS_GINTMSK); + pending = stm32_getreg(STM32_OTGFS_GINTSTS); + pending &= stm32_getreg(STM32_OTGFS_GINTMSK); /* Return from the interrupt when there are no further pending * interrupts. @@ -3584,7 +3584,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_SOF) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); - stm32l4_gint_sofisr(priv); + stm32_gint_sofisr(priv); } #endif @@ -3593,7 +3593,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_RXFLVL) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_RXFLVL, 0); - stm32l4_gint_rxflvlisr(priv); + stm32_gint_rxflvlisr(priv); } /* Handle the non-periodic TxFIFO empty interrupt */ @@ -3601,7 +3601,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_NPTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_NPTXFE, 0); - stm32l4_gint_nptxfeisr(priv); + stm32_gint_nptxfeisr(priv); } /* Handle the periodic TxFIFO empty interrupt */ @@ -3609,7 +3609,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_PTXFE) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_PTXFE, 0); - stm32l4_gint_ptxfeisr(priv); + stm32_gint_ptxfeisr(priv); } /* Handle the host channels interrupt */ @@ -3617,14 +3617,14 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_HC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_HC, 0); - stm32l4_gint_hcisr(priv); + stm32_gint_hcisr(priv); } /* Handle the host port interrupt */ if ((pending & OTGFS_GINT_HPRT) != 0) { - stm32l4_gint_hprtisr(priv); + stm32_gint_hprtisr(priv); } /* Handle the disconnect detected interrupt */ @@ -3632,7 +3632,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_DISC) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_DISC, 0); - stm32l4_gint_discisr(priv); + stm32_gint_discisr(priv); } /* Handle the incomplete periodic transfer */ @@ -3640,7 +3640,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) if ((pending & OTGFS_GINT_IPXFR) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_IPXFR, 0); - stm32l4_gint_ipxfrisr(priv); + stm32_gint_ipxfrisr(priv); } } @@ -3650,7 +3650,7 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_gint_enable and stm32l4_gint_disable + * Name: stm32_gint_enable and stm32_gint_disable * * Description: * Respectively enable or disable the global OTG FS interrupt. @@ -3663,30 +3663,30 @@ static int stm32l4_gint_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static void stm32l4_gint_enable(void) +static void stm32_gint_enable(void) { uint32_t regval; /* Set the GINTMSK bit to unmask the interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval |= OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } -static void stm32l4_gint_disable(void) +static void stm32_gint_disable(void) { uint32_t regval; /* Clear the GINTMSK bit to mask the interrupt */ - regval = stm32l4_getreg(STM32_OTGFS_GAHBCFG); + regval = stm32_getreg(STM32_OTGFS_GAHBCFG); regval &= ~OTGFS_GAHBCFG_GINTMSK; - stm32l4_putreg(STM32_OTGFS_GAHBCFG, regval); + stm32_putreg(STM32_OTGFS_GAHBCFG, regval); } /**************************************************************************** - * Name: stm32l4_hostinit_enable + * Name: stm32_hostinit_enable * * Description: * Enable host interrupts. @@ -3699,25 +3699,25 @@ static void stm32l4_gint_disable(void) * ****************************************************************************/ -static inline void stm32l4_hostinit_enable(void) +static inline void stm32_hostinit_enable(void) { uint32_t regval; /* Disable all interrupts. */ - stm32l4_putreg(STM32_OTGFS_GINTMSK, 0); + stm32_putreg(STM32_OTGFS_GINTMSK, 0); /* Clear any pending interrupts. */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xffffffff); /* Clear any pending USB OTG Interrupts */ - stm32l4_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); + stm32_putreg(STM32_OTGFS_GOTGINT, 0xffffffff); /* Clear any pending USB OTG interrupts */ - stm32l4_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); + stm32_putreg(STM32_OTGFS_GINTSTS, 0xbfffffff); /* Enable the host interrupts */ @@ -3753,11 +3753,11 @@ static inline void stm32l4_hostinit_enable(void) regval |= (OTGFS_GINT_RXFLVL | OTGFS_GINT_IPXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #endif - stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); } /**************************************************************************** - * Name: stm32l4_txfe_enable + * Name: stm32_txfe_enable * * Description: * Enable Tx FIFO empty interrupts. This is necessary when the entire @@ -3778,10 +3778,10 @@ static inline void stm32l4_hostinit_enable(void) * ****************************************************************************/ -static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, +static void stm32_txfe_enable(struct stm32_usbhost_s *priv, int chidx) { - struct stm32l4_chan_s *chan = &priv->chan[chidx]; + struct stm32_chan_s *chan = &priv->chan[chidx]; irqstate_t flags; uint32_t regval; @@ -3793,7 +3793,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ - regval = stm32l4_getreg(STM32_OTGFS_GINTMSK); + regval = stm32_getreg(STM32_OTGFS_GINTMSK); switch (chan->eptype) { default: @@ -3810,7 +3810,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, /* Enable interrupts */ - stm32l4_putreg(STM32_OTGFS_GINTMSK, regval); + stm32_putreg(STM32_OTGFS_GINTMSK, regval); leave_critical_section(flags); } @@ -3819,7 +3819,7 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_wait + * Name: stm32_wait * * Description: * Wait for a device to be connected or disconnected to/from a hub port. @@ -3843,10 +3843,10 @@ static void stm32l4_txfe_enable(struct stm32l4_usbhost_s *priv, * ****************************************************************************/ -static int stm32l4_wait(struct usbhost_connection_s *conn, +static int stm32_wait(struct usbhost_connection_s *conn, struct usbhost_hubport_s **hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; struct usbhost_hubport_s *connport; irqstate_t flags; int ret; @@ -3910,7 +3910,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, } /**************************************************************************** - * Name: stm32l4_enumerate + * Name: stm32_enumerate * * Description: * Enumerate the connected device. As part of this enumeration process, @@ -3937,7 +3937,7 @@ static int stm32l4_wait(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, +static int stm32_rh_enumerate(struct stm32_usbhost_s *priv, struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { @@ -3968,11 +3968,11 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Get the current device speed */ - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); if ((regval & OTGFS_HPRT_PSPD_MASK) == OTGFS_HPRT_PSPD_LS) { priv->rhport.hport.speed = USB_SPEED_LOW; @@ -3984,7 +3984,7 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, /* Allocate and initialize the root hub port EP0 channels */ - ret = stm32l4_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0); if (ret < 0) { @@ -3994,10 +3994,10 @@ static int stm32l4_rh_enumerate(struct stm32l4_usbhost_s *priv, return ret; } -static int stm32l4_enumerate(struct usbhost_connection_s *conn, +static int stm32_enumerate(struct usbhost_connection_s *conn, struct usbhost_hubport_s *hport) { - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; int ret; DEBUGASSERT(hport); @@ -4011,7 +4011,7 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, if (ROOTHUB(hport)) #endif { - ret = stm32l4_rh_enumerate(priv, conn, hport); + ret = stm32_rh_enumerate(priv, conn, hport); if (ret < 0) { return ret; @@ -4035,14 +4035,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, /* Return to the disconnected state */ uerr("ERROR: Enumeration failed: %d\n", ret); - stm32l4_gint_disconnected(priv); + stm32_gint_disconnected(priv); } return ret; } /**************************************************************************** - * Name: stm32l4_ep0configure + * Name: stm32_ep0configure * * Description: * Configure endpoint 0. This method is normally used internally by the @@ -4068,14 +4068,14 @@ static int stm32l4_enumerate(struct usbhost_connection_s *conn, * ****************************************************************************/ -static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, +static int stm32_ep0configure(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, uint16_t maxpacketsize) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; + struct stm32_chan_s *chan; int ret; DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && @@ -4096,7 +4096,7 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->outndx); + stm32_chan_configure(priv, ep0info->outndx); /* Configure the EP0 IN channel */ @@ -4105,14 +4105,14 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, chan->speed = speed; chan->maxpacket = maxpacketsize; - stm32l4_chan_configure(priv, ep0info->inndx); + stm32_chan_configure(priv, ep0info->inndx); nxmutex_unlock(&priv->lock); return OK; } /**************************************************************************** - * Name: stm32l4_epalloc + * Name: stm32_epalloc * * Description: * Allocate and configure one endpoint. @@ -4133,11 +4133,11 @@ static int stm32l4_ep0configure(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epalloc(struct usbhost_driver_s *drvr, +static int stm32_epalloc(struct usbhost_driver_s *drvr, const struct usbhost_epdesc_s *epdesc, usbhost_ep_t *ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; /* Sanity check. NOTE that this method should only be called if a device @@ -4162,11 +4162,11 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, if (epdesc->xfrtype == OTGFS_EPTYPE_CTRL) { - ret = stm32l4_ctrlep_alloc(priv, epdesc, ep); + ret = stm32_ctrlep_alloc(priv, epdesc, ep); } else { - ret = stm32l4_xfrep_alloc(priv, epdesc, ep); + ret = stm32_xfrep_alloc(priv, epdesc, ep); } nxmutex_unlock(&priv->lock); @@ -4174,7 +4174,7 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_epfree + * Name: stm32_epfree * * Description: * Free and endpoint previously allocated by DRVR_EPALLOC. @@ -4193,9 +4193,9 @@ static int stm32l4_epalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; int ret; DEBUGASSERT(priv); @@ -4213,17 +4213,17 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { /* Halt the channel and mark the channel available */ - stm32l4_chan_free(priv, (int)ep); + stm32_chan_free(priv, (int)ep); } else { /* Halt both control channel and mark the channels available */ - struct stm32l4_ctrlinfo_s *ctrlep = - (struct stm32l4_ctrlinfo_s *)ep; + struct stm32_ctrlinfo_s *ctrlep = + (struct stm32_ctrlinfo_s *)ep; - stm32l4_chan_free(priv, ctrlep->inndx); - stm32l4_chan_free(priv, ctrlep->outndx); + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); /* And free the control endpoint container */ @@ -4235,7 +4235,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_alloc + * Name: stm32_alloc * * Description: * Some hardware supports special memory in which request and descriptor @@ -4268,7 +4268,7 @@ static int stm32l4_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #warning this function name is too generic -static int stm32l4_alloc(struct usbhost_driver_s *drvr, +static int stm32_alloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t *maxlen) { uint8_t *alloc; @@ -4291,7 +4291,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_free + * Name: stm32_free * * Description: * Some hardware supports special memory in which request and descriptor @@ -4315,7 +4315,7 @@ static int stm32l4_alloc(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_free(struct usbhost_driver_s *drvr, +static int stm32_free(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4326,7 +4326,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ioalloc + * Name: stm32_ioalloc * * Description: * Some hardware supports special memory in which larger IO buffers can @@ -4355,7 +4355,7 @@ static int stm32l4_free(struct usbhost_driver_s *drvr, ****************************************************************************/ #warning this function name is too generic -static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, +static int stm32_ioalloc(struct usbhost_driver_s *drvr, uint8_t **buffer, size_t buflen) { uint8_t *alloc; @@ -4377,7 +4377,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_iofree + * Name: stm32_iofree * * Description: * Some hardware supports special memory in which IO data can be accessed @@ -4399,7 +4399,7 @@ static int stm32l4_ioalloc(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_iofree(struct usbhost_driver_s *drvr, +static int stm32_iofree(struct usbhost_driver_s *drvr, uint8_t *buffer) { /* There is no special memory requirement */ @@ -4410,7 +4410,7 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_ctrlin and stm32l4_ctrlout + * Name: stm32_ctrlin and stm32_ctrlout * * Description: * Process a IN or OUT request on the control endpoint. These methods @@ -4446,14 +4446,14 @@ static int stm32l4_iofree(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, +static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4468,7 +4468,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4484,7 +4484,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4495,7 +4495,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, if (buflen > 0) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, buffer, buflen); + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_RECVDATA, -ret); @@ -4511,7 +4511,7 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, /* Handle the status OUT phase */ priv->chan[ep0info->outndx].outdata1 ^= true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactions exit here */ @@ -4535,14 +4535,14 @@ static int stm32l4_ctrlin(struct usbhost_driver_s *drvr, return -ETIMEDOUT; } -static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, +static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0, const struct usb_ctrlreq_s *req, const uint8_t *buffer) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_ctrlinfo_s *ep0info = - (struct stm32l4_ctrlinfo_s *)ep0; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_ctrlinfo_s *ep0info = + (struct stm32_ctrlinfo_s *)ep0; uint16_t buflen; clock_t start; clock_t elapsed; @@ -4557,7 +4557,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Extract values from the request */ - buflen = stm32l4_getle16(req->len); + buflen = stm32_getle16(req->len); /* We must have exclusive access to the USB host hardware and structures */ @@ -4573,7 +4573,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, { /* Send the SETUP request */ - ret = stm32l4_ctrl_sendsetup(priv, ep0info, req); + ret = stm32_ctrl_sendsetup(priv, ep0info, req); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDSETUP, -ret); @@ -4592,7 +4592,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, /* Start DATA out transfer (only one DATA packet) */ priv->chan[ep0info->outndx].outdata1 = true; - ret = stm32l4_ctrl_senddata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); if (ret < 0) { usbhost_trace1(OTGFS_TRACE1_SENDDATA, -ret); @@ -4603,7 +4603,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, if (ret == OK) { - ret = stm32l4_ctrl_recvdata(priv, ep0info, NULL, 0); + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); if (ret == OK) { /* All success transactins exit here */ @@ -4629,7 +4629,7 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_transfer + * Name: stm32_transfer * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4667,11 +4667,11 @@ static int stm32l4_ctrlout(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, +static ssize_t stm32_transfer(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; ssize_t nbytes; int ret; @@ -4692,11 +4692,11 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, if (priv->chan[chidx].in) { - nbytes = stm32l4_in_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); } else { - nbytes = stm32l4_out_transfer(priv, chidx, buffer, buflen); + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); } nxmutex_unlock(&priv->lock); @@ -4704,7 +4704,7 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, } /**************************************************************************** - * Name: stm32l4_asynch + * Name: stm32_asynch * * Description: * Process a request to handle a transfer descriptor. This method will @@ -4740,11 +4740,11 @@ static ssize_t stm32l4_transfer(struct usbhost_driver_s *drvr, ****************************************************************************/ #ifdef CONFIG_USBHOST_ASYNCH -static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, +static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, uint8_t *buffer, size_t buflen, usbhost_asynch_t callback, void *arg) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; unsigned int chidx = (unsigned int)ep; int ret; @@ -4764,11 +4764,11 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, if (priv->chan[chidx].in) { - ret = stm32l4_in_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); } else { - ret = stm32l4_out_asynch(priv, chidx, buffer, buflen, callback, arg); + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); } nxmutex_unlock(&priv->lock); @@ -4777,7 +4777,7 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, #endif /* CONFIG_USBHOST_ASYNCH */ /**************************************************************************** - * Name: stm32l4_cancel + * Name: stm32_cancel * * Description: * Cancel a pending transfer on an endpoint. Cancelled synchronous or @@ -4795,10 +4795,10 @@ static int stm32l4_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep, * ****************************************************************************/ -static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) +static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; - struct stm32l4_chan_s *chan; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; + struct stm32_chan_s *chan; unsigned int chidx = (unsigned int)ep; irqstate_t flags; @@ -4815,7 +4815,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) /* Halt the channel */ - stm32l4_chan_halt(priv, chidx, CHREASON_CANCELLED); + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); chan->result = -ESHUTDOWN; /* Is there a thread waiting for this transfer to complete? */ @@ -4864,7 +4864,7 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) } /**************************************************************************** - * Name: stm32l4_connect + * Name: stm32_connect * * Description: * New connections may be detected by an attached hub. This method is @@ -4885,11 +4885,11 @@ static int stm32l4_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) ****************************************************************************/ #ifdef CONFIG_USBHOST_HUB -static int stm32l4_connect(struct usbhost_driver_s *drvr, +static int stm32_connect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport, bool connected) { - struct stm32l4_usbhost_s *priv = (struct stm32l4_usbhost_s *)drvr; + struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr; irqstate_t flags; DEBUGASSERT(priv != NULL && hport != NULL); @@ -4916,7 +4916,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, #endif /**************************************************************************** - * Name: stm32l4_disconnect + * Name: stm32_disconnect * * Description: * Called by the class when an error occurs and driver has been @@ -4941,7 +4941,7 @@ static int stm32l4_connect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_disconnect(struct usbhost_driver_s *drvr, +static void stm32_disconnect(struct usbhost_driver_s *drvr, struct usbhost_hubport_s *hport) { DEBUGASSERT(hport != NULL); @@ -4953,7 +4953,7 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_portreset + * Name: stm32_portreset * * Description: * Reset the USB host port. @@ -4972,26 +4972,26 @@ static void stm32l4_disconnect(struct usbhost_driver_s *drvr, * ****************************************************************************/ -static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) +static void stm32_portreset(struct stm32_usbhost_s *priv) { uint32_t regval; - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); regval |= OTGFS_HPRT_PRST; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); regval &= ~OTGFS_HPRT_PRST; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); up_mdelay(20); } /**************************************************************************** - * Name: stm32l4_flush_txfifos + * Name: stm32_flush_txfifos * * Description: * Flush the selected Tx FIFO. @@ -5004,7 +5004,7 @@ static void stm32l4_portreset(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static void stm32l4_flush_txfifos(uint32_t txfnum) +static void stm32_flush_txfifos(uint32_t txfnum) { uint32_t regval; uint32_t timeout; @@ -5012,13 +5012,13 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) /* Initiate the TX FIFO flush operation */ regval = OTGFS_GRSTCTL_TXFFLSH | txfnum; - stm32l4_putreg(STM32_OTGFS_GRSTCTL, regval); + stm32_putreg(STM32_OTGFS_GRSTCTL, regval); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_TXFFLSH) == 0) { break; @@ -5031,7 +5031,7 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) } /**************************************************************************** - * Name: stm32l4_flush_rxfifo + * Name: stm32_flush_rxfifo * * Description: * Flush the Rx FIFO. @@ -5044,20 +5044,20 @@ static void stm32l4_flush_txfifos(uint32_t txfnum) * ****************************************************************************/ -static void stm32l4_flush_rxfifo(void) +static void stm32_flush_rxfifo(void) { uint32_t regval; uint32_t timeout; /* Initiate the RX FIFO flush operation */ - stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_RXFFLSH); /* Wait for the FLUSH to complete */ for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_RXFFLSH) == 0) { break; @@ -5070,7 +5070,7 @@ static void stm32l4_flush_rxfifo(void) } /**************************************************************************** - * Name: stm32l4_vbusdrive + * Name: stm32_vbusdrive * * Description: * Drive the Vbus +5V. @@ -5084,41 +5084,41 @@ static void stm32l4_flush_rxfifo(void) * ****************************************************************************/ -static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) +static void stm32_vbusdrive(struct stm32_usbhost_s *priv, bool state) { uint32_t regval; /* Enable/disable the external charge pump */ - stm32l4_usbhost_vbusdrive(0, state); + stm32_usbhost_vbusdrive(0, state); /* Turn on the Host port power. */ - regval = stm32l4_getreg(STM32_OTGFS_HPRT); + regval = stm32_getreg(STM32_OTGFS_HPRT); regval &= ~(OTGFS_HPRT_PENA | OTGFS_HPRT_PCDET | OTGFS_HPRT_PENCHNG | OTGFS_HPRT_POCCHNG); if (((regval & OTGFS_HPRT_PPWR) == 0) && state) { regval |= OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } if (((regval & OTGFS_HPRT_PPWR) != 0) && !state) { regval &= ~OTGFS_HPRT_PPWR; - stm32l4_putreg(STM32_OTGFS_HPRT, regval); + stm32_putreg(STM32_OTGFS_HPRT, regval); } up_mdelay(200); } /**************************************************************************** - * Name: stm32l4_host_initialize + * Name: stm32_host_initialize * * Description: * Initialize/re-initialize hardware for host mode operation. At present, - * this function is called only from stm32l4_hw_initialize(). But if OTG + * this function is called only from stm32_hw_initialize(). But if OTG * mode were supported, this function would also be called to switch * between host and device modes on a connector ID change interrupt. * @@ -5130,7 +5130,7 @@ static void stm32l4_vbusdrive(struct stm32l4_usbhost_s *priv, bool state) * ****************************************************************************/ -static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) +static void stm32_host_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; uint32_t offset; @@ -5138,24 +5138,24 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Restart the PHY Clock */ - stm32l4_putreg(STM32_OTGFS_PCGCCTL, 0); + stm32_putreg(STM32_OTGFS_PCGCCTL, 0); /* Initialize Host Configuration (HCFG) register */ - regval = stm32l4_getreg(STM32_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSPCS_MASK; regval |= OTGFS_HCFG_FSLSPCS_FS48MHz; - stm32l4_putreg(STM32_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Reset the host port */ - stm32l4_portreset(priv); + stm32_portreset(priv); /* Clear the FS-/LS-only support bit in the HCFG register */ - regval = stm32l4_getreg(STM32_OTGFS_HCFG); + regval = stm32_getreg(STM32_OTGFS_HCFG); regval &= ~OTGFS_HCFG_FSLSS; - stm32l4_putreg(STM32_OTGFS_HCFG, regval); + stm32_putreg(STM32_OTGFS_HCFG, regval); /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic * Tx FIFOs @@ -5163,7 +5163,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32l4_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); + stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ @@ -5171,7 +5171,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); - stm32l4_putreg(STM32_OTGFS_HNPTXFSIZ, regval); + stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ @@ -5179,7 +5179,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) regval = (offset | (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); - stm32l4_putreg(STM32_OTGFS_HPTXFSIZ, regval); + stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); /* If OTG were supported, we should need to clear HNP enable bit in the * USB_OTG control register about here. @@ -5187,30 +5187,30 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) /* Flush all FIFOs */ - stm32l4_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); - stm32l4_flush_rxfifo(); + stm32_flush_txfifos(OTGFS_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); /* Clear all pending HC Interrupts */ for (i = 0; i < STM32_NHOST_CHANNELS; i++) { - stm32l4_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); - stm32l4_putreg(STM32_OTGFS_HCINTMSK(i), 0); + stm32_putreg(STM32_OTGFS_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTGFS_HCINTMSK(i), 0); } /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG * mode. */ - stm32l4_vbusdrive(priv, true); + stm32_vbusdrive(priv, true); /* Enable host interrupts */ - stm32l4_hostinit_enable(); + stm32_hostinit_enable(); } /**************************************************************************** - * Name: stm32l4_sw_initialize + * Name: stm32_sw_initialize * * Description: * One-time setup of the host driver state structure. @@ -5223,7 +5223,7 @@ static void stm32l4_host_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) +static inline void stm32_sw_initialize(struct stm32_usbhost_s *priv) { struct usbhost_driver_s *drvr; struct usbhost_hubport_s *hport; @@ -5232,24 +5232,24 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Initialize the device operations */ drvr = &priv->drvr; - drvr->ep0configure = stm32l4_ep0configure; - drvr->epalloc = stm32l4_epalloc; - drvr->epfree = stm32l4_epfree; - drvr->alloc = stm32l4_alloc; - drvr->free = stm32l4_free; - drvr->ioalloc = stm32l4_ioalloc; - drvr->iofree = stm32l4_iofree; - drvr->ctrlin = stm32l4_ctrlin; - drvr->ctrlout = stm32l4_ctrlout; - drvr->transfer = stm32l4_transfer; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; #ifdef CONFIG_USBHOST_ASYNCH - drvr->asynch = stm32l4_asynch; + drvr->asynch = stm32_asynch; #endif - drvr->cancel = stm32l4_cancel; + drvr->cancel = stm32_cancel; #ifdef CONFIG_USBHOST_HUB - drvr->connect = stm32l4_connect; + drvr->connect = stm32_connect; #endif - drvr->disconnect = stm32l4_disconnect; + drvr->disconnect = stm32_disconnect; /* Initialize the public port representation */ @@ -5275,13 +5275,13 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) /* Put all of the channels back in their initial, allocated state */ memset(priv->chan, 0, - STM32_MAX_TX_FIFOS * sizeof(struct stm32l4_chan_s)); + STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); /* Initialize each channel */ for (i = 0; i < STM32_MAX_TX_FIFOS; i++) { - struct stm32l4_chan_s *chan = &priv->chan[i]; + struct stm32_chan_s *chan = &priv->chan[i]; chan->chidx = i; nxsem_init(&chan->waitsem, 0, 0); @@ -5289,7 +5289,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) } /**************************************************************************** - * Name: stm32l4_hw_initialize + * Name: stm32_hw_initialize * * Description: * One-time setup of the host controller hardware for normal operations. @@ -5302,7 +5302,7 @@ static inline void stm32l4_sw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) +static inline int stm32_hw_initialize(struct stm32_usbhost_s *priv) { uint32_t regval; unsigned long timeout; @@ -5311,9 +5311,9 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * transceiver: "This bit is always 1 with write-only access" */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval |= OTGFS_GUSBCFG_PHYSEL; - stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); /* Reset after a PHY select and set Host mode. First, wait for AHB master * IDLE state. @@ -5322,7 +5322,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { up_udelay(3); - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_AHBIDL) != 0) { break; @@ -5331,10 +5331,10 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Then perform the core soft reset. */ - stm32l4_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); + stm32_putreg(STM32_OTGFS_GRSTCTL, OTGFS_GRSTCTL_CSRST); for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) { - regval = stm32l4_getreg(STM32_OTGFS_GRSTCTL); + regval = stm32_getreg(STM32_OTGFS_GRSTCTL); if ((regval & OTGFS_GRSTCTL_CSRST) == 0) { break; @@ -5355,7 +5355,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) #ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT regval |= OTGFS_GCCFG_SOFOUTEN; #endif - stm32l4_putreg(STM32_OTGFS_GCCFG, regval); + stm32_putreg(STM32_OTGFS_GCCFG, regval); up_mdelay(20); /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP @@ -5364,15 +5364,15 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) /* Force Host Mode */ - regval = stm32l4_getreg(STM32_OTGFS_GUSBCFG); + regval = stm32_getreg(STM32_OTGFS_GUSBCFG); regval &= ~OTGFS_GUSBCFG_FDMOD; regval |= OTGFS_GUSBCFG_FHMOD; - stm32l4_putreg(STM32_OTGFS_GUSBCFG, regval); + stm32_putreg(STM32_OTGFS_GUSBCFG, regval); up_mdelay(50); /* Initialize host mode and return success */ - stm32l4_host_initialize(priv); + stm32_host_initialize(priv); return OK; } @@ -5381,7 +5381,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_otgfshost_initialize + * Name: stm32_otgfshost_initialize * * Description: * Initialize USB host device controller hardware. @@ -5405,7 +5405,7 @@ static inline int stm32l4_hw_initialize(struct stm32l4_usbhost_s *priv) * ****************************************************************************/ -struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) +struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) { /* At present, there is only support for a single OTG FS host. Hence it is * pre-allocated as g_usbhost. However, in most code, the private data @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * devices. */ - struct stm32l4_usbhost_s *priv = &g_usbhost; + struct stm32_usbhost_s *priv = &g_usbhost; /* Sanity checks */ @@ -5422,11 +5422,11 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Make sure that interrupts from the OTG FS core are disabled */ - stm32l4_gint_disable(); + stm32_gint_disable(); /* Reset the state of the host driver */ - stm32l4_sw_initialize(priv); + stm32_sw_initialize(priv); /* Alternate function pin configuration. Here we assume that: * @@ -5451,23 +5451,23 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) * *Pins may vary from device-to-device. */ - stm32l4_configgpio(GPIO_OTGFS_DM); - stm32l4_configgpio(GPIO_OTGFS_DP); - stm32l4_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ + stm32_configgpio(GPIO_OTGFS_DM); + stm32_configgpio(GPIO_OTGFS_DP); + stm32_configgpio(GPIO_OTGFS_ID); /* Only needed for OTG */ /* SOF output pin configuration is configurable */ #ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT - stm32l4_configgpio(GPIO_OTGFS_SOF); + stm32_configgpio(GPIO_OTGFS_SOF); #endif /* Initialize the USB OTG FS core */ - stm32l4_hw_initialize(priv); + stm32_hw_initialize(priv); /* Attach USB host controller interrupt handler */ - if (irq_attach(STM32_IRQ_OTGFS, stm32l4_gint_isr, NULL) != 0) + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr, NULL) != 0) { usbhost_trace1(OTGFS_TRACE1_IRQATTACH, 0); return NULL; @@ -5475,7 +5475,7 @@ struct usbhost_connection_s *stm32l4_otgfshost_initialize(int controller) /* Enable USB OTG FS global interrupts */ - stm32l4_gint_enable(); + stm32_gint_enable(); /* Enable interrupts at the interrupt controller */ diff --git a/arch/arm/src/stm32l4/stm32l4_pm.h b/arch/arm/src/stm32l4/stm32l4_pm.h index d8f276e282a..36c8f0a335e 100644 --- a/arch/arm/src/stm32l4/stm32l4_pm.h +++ b/arch/arm/src/stm32l4/stm32l4_pm.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32l4_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32l4_pmstop(bool lpds); * ****************************************************************************/ -int stm32l4_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32l4_pmstop2(void); * ****************************************************************************/ -int stm32l4_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32l4_pmstandby(void); * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32l4_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32l4_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_pmlpr.c b/arch/arm/src/stm32l4/stm32l4_pmlpr.c index d43ae86f66f..ae7a525c5eb 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmlpr.c +++ b/arch/arm/src/stm32l4/stm32l4_pmlpr.c @@ -54,7 +54,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -69,7 +69,7 @@ * ****************************************************************************/ -int stm32l4_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmsleep.c b/arch/arm/src/stm32l4/stm32l4_pmsleep.c index 24e4170a62a..24dd4659231 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmsleep.c +++ b/arch/arm/src/stm32l4/stm32l4_pmsleep.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -void stm32l4_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmstandby.c b/arch/arm/src/stm32l4/stm32l4_pmstandby.c index 0866f7a2f5a..759ef841e9b 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstandby.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstandby.c @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -69,7 +69,7 @@ * ****************************************************************************/ -int stm32l4_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index c67a19a27aa..3b07546af4b 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -88,7 +88,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -106,7 +106,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32l4_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -130,7 +130,7 @@ int stm32l4_pmstop(bool lpds) } /**************************************************************************** - * Name: stm32l4_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -145,7 +145,7 @@ int stm32l4_pmstop(bool lpds) * ****************************************************************************/ -int stm32l4_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 866af2489de..54bfd8d5dd1 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pulsecount.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_tim.h" /* This module then only compiles if there is at least one enabled timer @@ -66,7 +66,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_TIMER_INFO -# define pulsecount_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pulsecount_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pulsecount_dumpgpio(p,m) #endif @@ -77,7 +77,7 @@ /* Pulsecount output configuration */ -struct stm32l4_out_s +struct stm32_out_s { uint8_t in_use:1; uint8_t pol:1; @@ -88,17 +88,17 @@ struct stm32l4_out_s /* Pulsecount channel configuration */ -struct stm32l4_chan_s +struct stm32_chan_s { uint8_t channel; - struct stm32l4_out_s out1; + struct stm32_out_s out1; }; /* This structure represents the state of one pulsecount timer */ -struct stm32l4_tim_s +struct stm32_tim_s { - struct stm32l4_chan_s channel; + struct stm32_chan_s channel; uint8_t timid:5; uint8_t timtype:3; uint8_t t_dts:3; @@ -113,10 +113,10 @@ struct stm32l4_tim_s void *handle; }; -struct stm32l4_pulsecount_s +struct stm32_pulsecount_s { const struct pulsecount_ops_s *ops; - struct stm32l4_tim_s *timer; + struct stm32_tim_s *timer; }; /**************************************************************************** @@ -125,10 +125,10 @@ struct stm32l4_pulsecount_s /* Register access */ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset); -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset); +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value); -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_TIMER_INFO @@ -146,11 +146,11 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty); static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency); -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv); +static int pulsecount_timer_configure(struct stm32_tim_s *priv); static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel); -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, - struct stm32l4_chan_s *chan); +static int pulsecount_output_configure(struct stm32_tim_s *priv, + struct stm32_chan_s *chan); static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state); static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, @@ -191,7 +191,7 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount1dev = +static struct stm32_tim_s g_pulsecount1dev = { .channel = { @@ -242,7 +242,7 @@ static struct stm32l4_tim_s g_pulsecount1dev = #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT -static struct stm32l4_tim_s g_pulsecount8dev = +static struct stm32_tim_s g_pulsecount8dev = { .channel = { @@ -301,7 +301,7 @@ static const struct pulsecount_ops_s g_pulsecountops = }; #ifdef CONFIG_STM32L4_TIM1_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount1lower = +static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount1dev, @@ -309,7 +309,7 @@ static struct stm32l4_pulsecount_s g_pulsecount1lower = #endif #ifdef CONFIG_STM32L4_TIM8_PULSECOUNT -static struct stm32l4_pulsecount_s g_pulsecount8lower = +static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, .timer = &g_pulsecount8dev, @@ -335,7 +335,7 @@ static struct stm32l4_pulsecount_s g_pulsecount8lower = * ****************************************************************************/ -static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) +static uint16_t pulsecount_getreg(struct stm32_tim_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -355,7 +355,7 @@ static uint16_t pulsecount_getreg(struct stm32l4_tim_s *priv, int offset) * ****************************************************************************/ -static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, +static void pulsecount_putreg(struct stm32_tim_s *priv, int offset, uint16_t value) { putreg16(value, priv->base + offset); @@ -378,7 +378,7 @@ static void pulsecount_putreg(struct stm32l4_tim_s *priv, int offset, * ****************************************************************************/ -static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, +static void pulsecount_modifyreg(struct stm32_tim_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { modifyreg16(priv->base + offset, (uint16_t)clearbits, @@ -403,7 +403,7 @@ static void pulsecount_modifyreg(struct stm32l4_tim_s *priv, uint32_t offset, static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, const char *msg) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; _info("%s:\n", msg); _info(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", @@ -441,7 +441,7 @@ static void pulsecount_dumpregs(struct pulsecount_lowerhalf_s *dev, static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t offset = 0; /* CCR channel indices are one-based to match timer channel numbers. */ @@ -505,7 +505,7 @@ static int pulsecount_ccr_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -547,7 +547,7 @@ static int pulsecount_duty_update(struct pulsecount_lowerhalf_s *dev, static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -632,7 +632,7 @@ static int pulsecount_frequency_update(struct pulsecount_lowerhalf_s *dev, * ****************************************************************************/ -static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) +static int pulsecount_timer_configure(struct stm32_tim_s *priv) { uint16_t cr1 = 0; @@ -669,7 +669,7 @@ static int pulsecount_timer_configure(struct stm32l4_tim_s *priv) static int pulsecount_channel_configure(struct pulsecount_lowerhalf_s *dev, uint8_t channel) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -765,7 +765,7 @@ errout: * ****************************************************************************/ -static int pulsecount_output_configure(struct stm32l4_tim_s *priv, +static int pulsecount_output_configure(struct stm32_tim_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -824,7 +824,7 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, * * Input Parameters: * dev - A reference to the lower half driver state structure - * outputs - outputs to set (look at enum stm32l4_pulsecount_chan_e) + * outputs - outputs to set (look at enum stm32_pulsecount_chan_e) * state - Enable/disable operation * ****************************************************************************/ @@ -832,7 +832,7 @@ static int pulsecount_output_configure(struct stm32l4_tim_s *priv, static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; @@ -877,7 +877,7 @@ static int pulsecount_outputs_enable(struct pulsecount_lowerhalf_s *dev, static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, bool enable) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; if (enable) { @@ -898,7 +898,7 @@ static void pulsecount_moe_enable(struct pulsecount_lowerhalf_s *dev, ****************************************************************************/ static uint16_t -pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, +pulsecount_outputs_from_channels(struct stm32_tim_s *priv, uint8_t selected) { uint16_t outputs = 0; @@ -925,7 +925,7 @@ pulsecount_outputs_from_channels(struct stm32l4_tim_s *priv, static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t outputs = 0; int ret = OK; @@ -991,7 +991,7 @@ errout: static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; ub16_t duty = 0; uint8_t channel = 0; uint16_t outputs = 0; @@ -1139,7 +1139,7 @@ errout: static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint16_t regval; /* Verify that this is an update interrupt. Nothing else is expected. */ @@ -1297,7 +1297,7 @@ static uint8_t pulsecount_count(uint32_t count) * ****************************************************************************/ -static int pulsecount_setapbclock(struct stm32l4_tim_s *priv, +static int pulsecount_setapbclock(struct stm32_tim_s *priv, bool on) { uint32_t en_bit; @@ -1371,7 +1371,7 @@ errout: static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg; _info("TIM%u\n", priv->timid); @@ -1389,7 +1389,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) pincfg = priv->channel.out1.pincfg; _info("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pulsecount_dumpgpio(pincfg, "pulsecount setup"); } @@ -1414,7 +1414,7 @@ static int pulsecount_ll_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t pincfg = 0; int ret = OK; @@ -1442,7 +1442,7 @@ static int pulsecount_ll_shutdown(struct pulsecount_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } errout: @@ -1470,7 +1470,7 @@ errout: static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -1547,7 +1547,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_TIMER_INFO - struct stm32l4_tim_s *priv = (struct stm32l4_tim_s *)dev; + struct stm32_tim_s *priv = (struct stm32_tim_s *)dev; /* There are no platform-specific ioctl commands */ @@ -1558,7 +1558,7 @@ static int pulsecount_ll_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; int ret; ret = pulsecount_ll_setup((struct pulsecount_lowerhalf_s *)pulse->timer); @@ -1572,7 +1572,7 @@ static int pulsecount_setup(struct pulsecount_lowerhalf_s *dev) static int pulsecount_shutdown(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_shutdown((struct pulsecount_lowerhalf_s *) pulse->timer); } @@ -1581,8 +1581,8 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info, void *handle) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; - struct stm32l4_tim_s *priv = pulse->timer; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; + struct stm32_tim_s *priv = pulse->timer; if (info->count > 0) { @@ -1600,14 +1600,14 @@ static int pulsecount_start(struct pulsecount_lowerhalf_s *dev, static int pulsecount_stop(struct pulsecount_lowerhalf_s *dev) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_stop((struct pulsecount_lowerhalf_s *)pulse->timer); } static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, int cmd, unsigned long arg) { - struct stm32l4_pulsecount_s *pulse = (struct stm32l4_pulsecount_s *)dev; + struct stm32_pulsecount_s *pulse = (struct stm32_pulsecount_s *)dev; return pulsecount_ll_ioctl((struct pulsecount_lowerhalf_s *)pulse->timer, cmd, arg); } @@ -1616,9 +1616,9 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Public Functions ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer) +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) { - struct stm32l4_pulsecount_s *lower = NULL; + struct stm32_pulsecount_s *lower = NULL; _info("TIM%u\n", timer); diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.h b/arch/arm/src/stm32l4/stm32l4_pulsecount.h index 8d1a95c595b..fc4ee3ed929 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.h +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.h @@ -34,6 +34,6 @@ * Public Function Prototypes ****************************************************************************/ -struct pulsecount_lowerhalf_s *stm32l4_pulsecountinitialize(int timer); +struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index edb4452d0a2..679112ed21a 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -40,7 +40,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32l4_pwm.h" -#include "stm32l4.h" +#include "stm32.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. @@ -125,7 +125,7 @@ /* Debug ********************************************************************/ #ifdef CONFIG_DEBUG_PWM_INFO -# define pwm_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m) #else # define pwm_dumpgpio(p,m) #endif @@ -136,7 +136,7 @@ /* PWM output configuration */ -struct stm32l4_pwm_out_s +struct stm32_pwm_out_s { uint8_t in_use:1; /* Output in use */ uint8_t pol:1; /* Polarity. Default: positive */ @@ -147,33 +147,33 @@ struct stm32l4_pwm_out_s /* PWM channel configuration */ -struct stm32l4_pwmchan_s +struct stm32_pwmchan_s { uint8_t channel:4; /* Timer output channel: {1,..4} */ - uint8_t mode:4; /* PWM channel mode (see stm32l4_pwm_chanmode_e) */ - struct stm32l4_pwm_out_s out1; /* PWM output configuration */ + uint8_t mode:4; /* PWM channel mode (see stm32_pwm_chanmode_e) */ + struct stm32_pwm_out_s out1; /* PWM output configuration */ #ifdef HAVE_BREAK - struct stm32l4_pwm_break_s brk; /* PWM break configuration */ + struct stm32_pwm_break_s brk; /* PWM break configuration */ #endif #ifdef HAVE_PWM_COMPLEMENTARY - struct stm32l4_pwm_out_s out2; /* PWM complementary output configuration */ + struct stm32_pwm_out_s out2; /* PWM complementary output configuration */ #endif }; /* This structure represents the state of one PWM timer */ -struct stm32l4_pwmtimer_s +struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ #ifdef CONFIG_STM32L4_PWM_LL_OPS - const struct stm32l4_pwm_ops_s *llops; /* Low-level PWM ops */ + const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif - struct stm32l4_pwmchan_s *channels; /* Channels configuration */ + struct stm32_pwmchan_s *channels; /* Channels configuration */ uint8_t timid:5; /* Timer ID {1,...,17} */ uint8_t chan_num:3; /* Number of configured channels */ uint8_t timtype:3; /* See the TIMTYPE_* definitions */ - uint8_t mode:3; /* Timer mode (see stm32l4_pwm_tim_mode_e) */ + uint8_t mode:3; /* Timer mode (see stm32_pwm_tim_mode_e) */ uint8_t lock:2; /* TODO: Lock configuration */ uint8_t t_dts:3; /* Clock division for t_DTS */ uint8_t _res:5; /* Reserved */ @@ -197,10 +197,10 @@ struct stm32l4_pwmtimer_s /* Register access */ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset); -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset); +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value); -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_DEBUG_PWM_INFO @@ -274,7 +274,7 @@ static const struct pwm_ops_s g_pwmops = }; #ifdef CONFIG_STM32L4_PWM_LL_OPS -static const struct stm32l4_pwm_ops_s g_llpwmops = +static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, .soft_break = pwm_soft_break, @@ -298,7 +298,7 @@ static const struct stm32l4_pwm_ops_s g_llpwmops = #ifdef CONFIG_STM32L4_TIM1_PWM -static struct stm32l4_pwmchan_s g_pwm1channels[] = +static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ @@ -435,7 +435,7 @@ static struct stm32l4_pwmchan_s g_pwm1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm1dev = +static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -461,7 +461,7 @@ static struct stm32l4_pwmtimer_s g_pwm1dev = #ifdef CONFIG_STM32L4_TIM2_PWM -static struct stm32l4_pwmchan_s g_pwm2channels[] = +static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ @@ -531,7 +531,7 @@ static struct stm32l4_pwmchan_s g_pwm2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm2dev = +static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -558,7 +558,7 @@ static struct stm32l4_pwmtimer_s g_pwm2dev = #ifdef CONFIG_STM32L4_TIM3_PWM -static struct stm32l4_pwmchan_s g_pwm3channels[] = +static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ @@ -628,7 +628,7 @@ static struct stm32l4_pwmchan_s g_pwm3channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm3dev = +static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -654,7 +654,7 @@ static struct stm32l4_pwmtimer_s g_pwm3dev = #ifdef CONFIG_STM32L4_TIM4_PWM -static struct stm32l4_pwmchan_s g_pwm4channels[] = +static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ @@ -724,7 +724,7 @@ static struct stm32l4_pwmchan_s g_pwm4channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm4dev = +static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -750,7 +750,7 @@ static struct stm32l4_pwmtimer_s g_pwm4dev = #ifdef CONFIG_STM32L4_TIM5_PWM -static struct stm32l4_pwmchan_s g_pwm5channels[] = +static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ @@ -818,7 +818,7 @@ static struct stm32l4_pwmchan_s g_pwm5channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm5dev = +static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -844,7 +844,7 @@ static struct stm32l4_pwmtimer_s g_pwm5dev = #ifdef CONFIG_STM32L4_TIM8_PWM -static struct stm32l4_pwmchan_s g_pwm8channels[] = +static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ @@ -981,7 +981,7 @@ static struct stm32l4_pwmchan_s g_pwm8channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm8dev = +static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1007,7 +1007,7 @@ static struct stm32l4_pwmtimer_s g_pwm8dev = #ifdef CONFIG_STM32L4_TIM15_PWM -static struct stm32l4_pwmchan_s g_pwm15channels[] = +static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ @@ -1063,7 +1063,7 @@ static struct stm32l4_pwmchan_s g_pwm15channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm15dev = +static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1089,7 +1089,7 @@ static struct stm32l4_pwmtimer_s g_pwm15dev = #ifdef CONFIG_STM32L4_TIM16_PWM -static struct stm32l4_pwmchan_s g_pwm16channels[] = +static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ @@ -1129,7 +1129,7 @@ static struct stm32l4_pwmchan_s g_pwm16channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm16dev = +static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1155,7 +1155,7 @@ static struct stm32l4_pwmtimer_s g_pwm16dev = #ifdef CONFIG_STM32L4_TIM17_PWM -static struct stm32l4_pwmchan_s g_pwm17channels[] = +static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ @@ -1195,7 +1195,7 @@ static struct stm32l4_pwmchan_s g_pwm17channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwm17dev = +static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1221,7 +1221,7 @@ static struct stm32l4_pwmtimer_s g_pwm17dev = #ifdef CONFIG_STM32L4_LPTIM1_PWM -static struct stm32l4_pwmchan_s g_pwmlp1channels[] = +static struct stm32_pwmchan_s g_pwmlp1channels[] = { /* LPTIM1 has 1 channel */ @@ -1243,7 +1243,7 @@ static struct stm32l4_pwmchan_s g_pwmlp1channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp1dev = +static struct stm32_pwmtimer_s g_pwmlp1dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1277,7 +1277,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp1dev = #ifdef CONFIG_STM32L4_LPTIM2_PWM -static struct stm32l4_pwmchan_s g_pwmlp2channels[] = +static struct stm32_pwmchan_s g_pwmlp2channels[] = { /* LPTIM2 has 1 channel */ @@ -1299,7 +1299,7 @@ static struct stm32l4_pwmchan_s g_pwmlp2channels[] = #endif }; -static struct stm32l4_pwmtimer_s g_pwmlp2dev = +static struct stm32_pwmtimer_s g_pwmlp2dev = { .ops = &g_pwmops, #ifdef CONFIG_STM32L4_PWM_LL_OPS @@ -1350,7 +1350,7 @@ static struct stm32l4_pwmtimer_s g_pwmlp2dev = * ****************************************************************************/ -static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) +static uint16_t pwm_getreg(struct stm32_pwmtimer_s *priv, int offset) { return getreg16(priv->base + offset); } @@ -1370,7 +1370,7 @@ static uint16_t pwm_getreg(struct stm32l4_pwmtimer_s *priv, int offset) * ****************************************************************************/ -static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, +static void pwm_putreg(struct stm32_pwmtimer_s *priv, int offset, uint16_t value) { if (priv->timtype == TIMTYPE_GENERAL32 && @@ -1412,7 +1412,7 @@ static void pwm_putreg(struct stm32l4_pwmtimer_s *priv, int offset, * ****************************************************************************/ -static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, +static void pwm_modifyreg(struct stm32_pwmtimer_s *priv, uint32_t offset, uint32_t clearbits, uint32_t setbits) { if (priv->timtype == TIMTYPE_GENERAL32 && @@ -1456,7 +1456,7 @@ static void pwm_modifyreg(struct stm32l4_pwmtimer_s *priv, uint32_t offset, static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, const char *msg) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { @@ -1520,7 +1520,7 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; #ifdef HAVE_LPTIM @@ -1604,7 +1604,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, #ifdef CONFIG_STM32L4_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t offset = 0; switch (index) @@ -1664,7 +1664,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Update ARR register */ @@ -1686,7 +1686,7 @@ static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr) static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (priv->timtype == TIMTYPE_LOWPOWER) { @@ -1717,7 +1717,7 @@ static uint32_t pwm_arr_get(struct pwm_lowerhalf_s *dev) static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, ub16_t duty) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t ccr = 0; @@ -1756,7 +1756,7 @@ static int pwm_duty_update(struct pwm_lowerhalf_s *dev, uint8_t channel, static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; #ifdef HAVE_LPTIM if (priv->timtype != TIMTYPE_LOWPOWER) @@ -1807,7 +1807,7 @@ static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state) static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t reload = 0; uint32_t timclk = 0; uint32_t prescaler = 0; @@ -1906,7 +1906,7 @@ static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* Calculated values */ @@ -1980,7 +1980,7 @@ static int pwm_lp_frequency_update(struct pwm_lowerhalf_s *dev, * ****************************************************************************/ -static int pwm_timer_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_timer_configure(struct stm32_pwmtimer_s *priv) { uint16_t cr1 = 0; int ret = OK; @@ -2081,7 +2081,7 @@ errout: static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t chanmode = 0; uint32_t ocmode = 0; uint32_t ccmr = 0; @@ -2326,7 +2326,7 @@ errout: * ****************************************************************************/ -static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, +static int pwm_output_configure(struct stm32_pwmtimer_s *priv, uint8_t channel) { uint32_t cr2 = 0; @@ -2434,7 +2434,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, * * Input Parameters: * dev - A reference to the lower half PWM driver state structure - * outputs - outputs to set (look at enum stm32l4_chan_e in stm32l4_pwm.h) + * outputs - outputs to set (look at enum stm32_chan_e in stm32l4_pwm.h) * state - Enable/disable operation * ****************************************************************************/ @@ -2442,7 +2442,7 @@ static int pwm_output_configure(struct stm32l4_pwmtimer_s *priv, static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, uint16_t outputs, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t ccer = 0; uint32_t regval = 0; @@ -2494,7 +2494,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t bdtr = 0; int ret = OK; @@ -2536,7 +2536,7 @@ errout: static int pwm_soft_update(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; pwm_putreg(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); @@ -2559,7 +2559,7 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev) static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; if (state == true) { @@ -2586,7 +2586,7 @@ static int pwm_soft_break(struct pwm_lowerhalf_s *dev, bool state) ****************************************************************************/ static uint16_t -pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) +pwm_outputs_from_channels(struct stm32_pwmtimer_s *priv) { uint16_t outputs = 0; uint8_t channel = 0; @@ -2636,7 +2636,7 @@ pwm_outputs_from_channels(struct stm32l4_pwmtimer_s *priv) * ****************************************************************************/ -static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) +static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv) { uint32_t bdtr = 0; @@ -2716,7 +2716,7 @@ static int pwm_break_dt_configure(struct stm32l4_pwmtimer_s *priv) static int pwm_configure(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; uint8_t j = 0; int ret = OK; @@ -2840,7 +2840,7 @@ errout: static int pwm_duty_channels_update(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint8_t channel = 0; ub16_t duty = 0; int ret = OK; @@ -2914,7 +2914,7 @@ errout: static int pwm_timer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t outputs = 0; int ret = OK; @@ -3012,7 +3012,7 @@ errout: static int pwm_lptimer(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint16_t cr; int ret = OK; @@ -3070,7 +3070,7 @@ errout: * ****************************************************************************/ -static int pwm_setapbclock(struct stm32l4_pwmtimer_s *priv, +static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) { uint32_t en_bit; @@ -3292,7 +3292,7 @@ errout: static int pwm_setup(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg; int ret; int i; @@ -3321,7 +3321,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out1.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } @@ -3331,7 +3331,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pincfg = priv->channels[i].out2.pincfg; pwminfo("pincfg: %08" PRIx32 "\n", pincfg); - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); pwm_dumpgpio(pincfg, "PWM setup"); } #endif @@ -3371,7 +3371,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) static int pwm_shutdown(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t pincfg = 0; int i = 0; int ret = OK; @@ -3409,7 +3409,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #ifdef HAVE_PWM_COMPLEMENTARY @@ -3421,7 +3421,7 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) pincfg &= (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= GPIO_INPUT | GPIO_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); } #endif } @@ -3449,7 +3449,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { int ret = OK; - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* if frequency has not changed we just update duty */ @@ -3520,7 +3520,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, static int pwm_stop(struct pwm_lowerhalf_s *dev) { - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; uint32_t resetbit = 0; uint32_t regaddr; uint32_t regval; @@ -3667,7 +3667,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg) { #ifdef CONFIG_DEBUG_PWM_INFO - struct stm32l4_pwmtimer_s *priv = (struct stm32l4_pwmtimer_s *)dev; + struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; /* There are no platform-specific ioctl commands */ @@ -3681,7 +3681,7 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -3697,9 +3697,9 @@ static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("TIM%u\n", timer); @@ -3774,7 +3774,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) } /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -3791,9 +3791,9 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer) ****************************************************************************/ #ifdef HAVE_LPTIM -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer) +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer) { - struct stm32l4_pwmtimer_s *lower; + struct stm32_pwmtimer_s *lower; pwminfo("LPTIM%u\n", timer); diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 08b8e021a4f..66d75febf09 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -797,7 +797,7 @@ #ifdef CONFIG_STM32L4_PWM_LL_OPS /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops - * access can be found in stm32l4_pwm_dev_s + * access can be found in stm32_pwm_dev_s */ #define PWM_SETUP(dev) \ @@ -842,7 +842,7 @@ /* Timer mode */ -enum stm32l4_timmode_e +enum stm32_timmode_e { STM32_TIMMODE_COUNTUP = 0, STM32_TIMMODE_COUNTDOWN = 1, @@ -853,7 +853,7 @@ enum stm32l4_timmode_e /* Timer output polarity */ -enum stm32l4_pwm_pol_e +enum stm32_pwm_pol_e { STM32_POL_POS = 0, STM32_POL_NEG = 1, @@ -861,7 +861,7 @@ enum stm32l4_pwm_pol_e /* Timer output IDLE state */ -enum stm32l4_pwm_idle_e +enum stm32_pwm_idle_e { STM32_IDLE_INACTIVE = 0, STM32_IDLE_ACTIVE = 1 @@ -869,7 +869,7 @@ enum stm32l4_pwm_idle_e /* PWM channel mode */ -enum stm32l4_chanmode_e +enum stm32_chanmode_e { STM32_CHANMODE_FRZN = 0, /* CCRx matches has no effects on outputs */ STM32_CHANMODE_CHACT = 1, /* OCxREF active on match */ @@ -887,7 +887,7 @@ enum stm32l4_chanmode_e /* PWM timer channel */ -enum stm32l4_pwm_chan_e +enum stm32_pwm_chan_e { STM32_PWM_CHAN1 = 1, STM32_PWM_CHAN2 = 2, @@ -899,7 +899,7 @@ enum stm32l4_pwm_chan_e /* PWM timer channel output */ -enum stm32l4_pwm_output_e +enum stm32_pwm_output_e { STM32_PWM_OUT1 = (1 << 0), STM32_PWM_OUT1N = (1 << 1), @@ -928,7 +928,7 @@ enum stm32l4_pwm_output_e * "lower-half" PWM driver structure. */ -struct stm32l4_pwm_dev_s +struct stm32_pwm_dev_s { /* The first field of this state structure must be a pointer to the PWM * callback structure to be consistent with upper-half PWM driver. @@ -938,7 +938,7 @@ struct stm32l4_pwm_dev_s /* Publicly visible portion of the "lower-half" PWM driver structure */ - const struct stm32l4_pwm_ops_s *llops; + const struct stm32_pwm_ops_s *llops; /* Require cast-compatibility with private "lower-half" PWM structure */ }; @@ -946,7 +946,7 @@ struct stm32l4_pwm_dev_s /* Low-level operations for PWM */ struct pwm_lowerhalf_s; -struct stm32l4_pwm_ops_s +struct stm32_pwm_ops_s { /* Update CCR register */ @@ -1030,7 +1030,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwminitialize + * Name: stm32_pwminitialize * * Description: * Initialize one timer for use with the upper_level PWM driver. @@ -1046,10 +1046,10 @@ extern "C" * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); /**************************************************************************** - * Name: stm32l4_lp_pwminitialize + * Name: stm32_lp_pwminitialize * * Description: * Initialize one low-power timer for use with the upper_level PWM driver. @@ -1065,7 +1065,7 @@ struct pwm_lowerhalf_s *stm32l4_pwminitialize(int timer); * ****************************************************************************/ -struct pwm_lowerhalf_s *stm32l4_lp_pwminitialize(int timer); +struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index 1da59b2797a..088c66dfe4f 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -39,12 +39,12 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l4_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } @@ -70,7 +70,7 @@ static inline void stm32l4_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; @@ -99,7 +99,7 @@ bool stm32l4_pwr_enableclk(bool enable) } /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l4_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L4 PWR control register 1 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l4_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l4_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l4_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,7 +163,7 @@ bool stm32l4_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; @@ -174,12 +174,12 @@ bool stm32l4_pwr_enableusv(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l4_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -222,7 +222,7 @@ bool stm32l4_pwr_enableusv(bool set) ****************************************************************************/ #if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set) +bool stm32_pwr_enable_pvme2(bool set) { uint32_t regval; bool was_set; @@ -233,12 +233,12 @@ bool stm32l4_pwr_enable_pvme2(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_PVME2) != 0); /* Enable or disable the ability to write */ @@ -248,26 +248,26 @@ bool stm32l4_pwr_enable_pvme2(bool set) /* Disable the Vddio2 monitoring */ regval &= ~PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddio2 monitoring */ regval |= PWR_CR2_PVME2; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -278,7 +278,7 @@ bool stm32l4_pwr_enable_pvme2(bool set) * ****************************************************************************/ -bool stm32l4_pwr_get_pvmo2(void) +bool stm32_pwr_get_pvmo2(void) { uint32_t regval; bool was_clk_enabled; @@ -288,23 +288,23 @@ bool stm32l4_pwr_get_pvmo2(void) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 SR2 control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_SR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_SR2_OFFSET); if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return !!(regval & PWR_SR2_PVMO2); } /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -319,7 +319,7 @@ bool stm32l4_pwr_get_pvmo2(void) * ****************************************************************************/ -bool stm32l4_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; @@ -330,12 +330,12 @@ bool stm32l4_pwr_vddio2_valid(bool set) if (!was_clk_enabled) { - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L4 PWR control register 2 */ - regval = stm32l4_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -345,19 +345,19 @@ bool stm32l4_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l4_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l4_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 0208128cae8..2de90b4f585 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l4_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l4_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l4_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l4_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l4_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l4_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l4_pwr_enable_pvme2 + * Name: stm32_pwr_enable_pvme2 * * Description: * Enables or disables the peripheral voltage monitoring for Vddio2. @@ -122,11 +122,11 @@ bool stm32l4_pwr_enableusv(bool set); ****************************************************************************/ #if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_enable_pvme2(bool set); +bool stm32_pwr_enable_pvme2(bool set); #endif /**************************************************************************** - * Name: stm32l4_pwr_get_pvmo2 + * Name: stm32_pwr_get_pvmo2 * * Description: * Get value of peripheral voltage monitor output 2 (Vddio2). @@ -138,11 +138,11 @@ bool stm32l4_pwr_enable_pvme2(bool set); ****************************************************************************/ #if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_get_pvmo2(void); +bool stm32_pwr_get_pvmo2(void); #endif /**************************************************************************** - * Name: stm32l4_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -157,7 +157,7 @@ bool stm32l4_pwr_get_pvmo2(void); ****************************************************************************/ #if !defined(CONFIG_STM32L4_STM32L4X3) -bool stm32l4_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #endif /**************************************************************************** diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index d3e065ba9c4..b7ce3145b32 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" #include "stm32l4_qencoder.h" @@ -163,7 +163,7 @@ #ifdef CONFIG_DEBUG_SENSORS # ifdef CONFIG_DEBUG_INFO -# define qe_dumpgpio(p,m) stm32l4_dumpgpio(p,m) +# define qe_dumpgpio(p,m) stm32_dumpgpio(p,m) # else # define qe_dumpgpio(p,m) # endif @@ -177,7 +177,7 @@ /* Constant configuration structure that is retained in FLASH */ -struct stm32l4_qeconfig_s +struct stm32_qeconfig_s { uint8_t timid; /* Timer ID {1,2,3,4,5,8} */ uint8_t irq; /* Timer update IRQ */ @@ -192,7 +192,7 @@ struct stm32l4_qeconfig_s /* Overall, RAM-based state structure */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* The first field of this state structure must be a pointer to the lower- * half callback structure: @@ -202,7 +202,7 @@ struct stm32l4_lowerhalf_s /* STM32 driver-specific fields: */ - const struct stm32l4_qeconfig_s *config; /* static onfiguration */ + const struct stm32_qeconfig_s *config; /* static onfiguration */ bool inuse; /* True: The lower-half driver is in-use */ @@ -218,38 +218,38 @@ struct stm32l4_lowerhalf_s /* Helper functions */ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value); -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset); -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value); #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg); #else -# define stm32l4_dumpregs(priv,msg) +# define stm32_dumpregs(priv,msg) #endif -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ -static int stm32l4_setup(struct qe_lowerhalf_s *lower); -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower); -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_setup(struct qe_lowerhalf_s *lower); +static int stm32_shutdown(struct qe_lowerhalf_s *lower); +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos); -static int stm32l4_reset(struct qe_lowerhalf_s *lower); -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, +static int stm32_reset(struct qe_lowerhalf_s *lower); +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg); /**************************************************************************** @@ -260,19 +260,19 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, int cmd, static const struct qe_ops_s g_qecallbacks = { - .setup = stm32l4_setup, - .shutdown = stm32l4_shutdown, - .position = stm32l4_position, + .setup = stm32_setup, + .shutdown = stm32_shutdown, + .position = stm32_position, .setposmax = NULL, /* not supported yet */ - .reset = stm32l4_reset, + .reset = stm32_reset, .setindex = NULL, /* not supported yet */ - .ioctl = stm32l4_ioctl, + .ioctl = stm32_ioctl, }; /* Per-timer state structures */ #ifdef CONFIG_STM32L4_TIM1_QE -static const struct stm32l4_qeconfig_s g_tim1config = +static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, .irq = STM32_IRQ_TIM1UP, @@ -285,7 +285,7 @@ static const struct stm32l4_qeconfig_s g_tim1config = .ti2cfg = GPIO_TIM1_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim1lower = +static struct stm32_lowerhalf_s g_tim1lower = { .ops = &g_qecallbacks, .config = &g_tim1config, @@ -296,7 +296,7 @@ static struct stm32l4_lowerhalf_s g_tim1lower = #endif #ifdef CONFIG_STM32L4_TIM2_QE -static const struct stm32l4_qeconfig_s g_tim2config = +static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, .irq = STM32_IRQ_TIM2, @@ -309,7 +309,7 @@ static const struct stm32l4_qeconfig_s g_tim2config = .ti2cfg = GPIO_TIM2_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim2lower = +static struct stm32_lowerhalf_s g_tim2lower = { .ops = &g_qecallbacks, .config = &g_tim2config, @@ -320,7 +320,7 @@ static struct stm32l4_lowerhalf_s g_tim2lower = #endif #ifdef CONFIG_STM32L4_TIM3_QE -static const struct stm32l4_qeconfig_s g_tim3config = +static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, .irq = STM32_IRQ_TIM3, @@ -333,7 +333,7 @@ static const struct stm32l4_qeconfig_s g_tim3config = .ti2cfg = GPIO_TIM3_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim3lower = +static struct stm32_lowerhalf_s g_tim3lower = { .ops = &g_qecallbacks, .config = &g_tim3config, @@ -344,7 +344,7 @@ static struct stm32l4_lowerhalf_s g_tim3lower = #endif #ifdef CONFIG_STM32L4_TIM4_QE -static const struct stm32l4_qeconfig_s g_tim4config = +static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, .irq = STM32_IRQ_TIM4, @@ -357,7 +357,7 @@ static const struct stm32l4_qeconfig_s g_tim4config = .ti2cfg = GPIO_TIM4_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim4lower = +static struct stm32_lowerhalf_s g_tim4lower = { .ops = &g_qecallbacks, .config = &g_tim4config, @@ -368,7 +368,7 @@ static struct stm32l4_lowerhalf_s g_tim4lower = #endif #ifdef CONFIG_STM32L4_TIM5_QE -static const struct stm32l4_qeconfig_s g_tim5config = +static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, .irq = STM32_IRQ_TIM5, @@ -381,7 +381,7 @@ static const struct stm32l4_qeconfig_s g_tim5config = .ti2cfg = GPIO_TIM5_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim5lower = +static struct stm32_lowerhalf_s g_tim5lower = { .ops = &g_qecallbacks, .config = &g_tim5config, @@ -392,7 +392,7 @@ static struct stm32l4_lowerhalf_s g_tim5lower = #endif #ifdef CONFIG_STM32L4_TIM8_QE -static const struct stm32l4_qeconfig_s g_tim8config = +static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, .irq = STM32_IRQ_TIM8UP, @@ -405,7 +405,7 @@ static const struct stm32l4_qeconfig_s g_tim8config = .ti2cfg = GPIO_TIM8_CH2IN, }; -static struct stm32l4_lowerhalf_s g_tim8lower = +static struct stm32_lowerhalf_s g_tim8lower = { .ops = &g_qecallbacks, .config = &g_tim8config, @@ -420,7 +420,7 @@ static struct stm32l4_lowerhalf_s g_tim8lower = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Read the value of a 16-bit timer register. @@ -434,14 +434,14 @@ static struct stm32l4_lowerhalf_s g_tim8lower = * ****************************************************************************/ -static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, +static uint16_t stm32_getreg16(struct stm32_lowerhalf_s *priv, int offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 16-bit timer register. @@ -455,7 +455,7 @@ static uint16_t stm32l4_getreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg16(struct stm32_lowerhalf_s *priv, int offset, uint16_t value) { @@ -463,7 +463,7 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Read the value of a 32-bit timer register. @@ -480,14 +480,14 @@ static void stm32l4_putreg16(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, +static uint32_t stm32_getreg32(struct stm32_lowerhalf_s *priv, int offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Write a value to a 32-bit timer register. @@ -504,7 +504,7 @@ static uint32_t stm32l4_getreg32(struct stm32l4_lowerhalf_s *priv, * ****************************************************************************/ -static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, +static void stm32_putreg32(struct stm32_lowerhalf_s *priv, int offset, uint32_t value) { @@ -512,7 +512,7 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, } /**************************************************************************** - * Name: stm32l4_dumpregs + * Name: stm32_dumpregs * * Description: * Dump all timer registers. @@ -526,61 +526,61 @@ static void stm32l4_putreg32(struct stm32l4_lowerhalf_s *priv, ****************************************************************************/ #if defined(CONFIG_DEBUG_SENSORS) && defined(CONFIG_DEBUG_INFO) -static void stm32l4_dumpregs(struct stm32l4_lowerhalf_s *priv, +static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, const char *msg) { sninfo("%s:\n", msg); sninfo(" CR1: %04x CR2: %04x SMCR: %08" PRIx32 " DIER: %04x\n", - stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_CR2_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(priv, STM32_GTIM_CR2_OFFSET), + stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET)); sninfo(" SR: %04x EGR: %04x CCMR1: %08" PRIx32 " CCMR2: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_EGR_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_SR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_EGR_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCMR2_OFFSET)); sninfo(" CCER: %04x CNT: %08" PRIx32 " PSC: %04x" " ARR: %08" PRIx32 "\n", - stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_PSC_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_ARR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(priv, STM32_GTIM_PSC_OFFSET), + stm32_getreg32(priv, STM32_GTIM_ARR_OFFSET)); sninfo(" CCR1: %08" PRIx32 " CCR2: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32_GTIM_CCR1_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); + stm32_getreg32(priv, STM32_GTIM_CCR1_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR2_OFFSET)); sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", - stm32l4_getreg32(priv, STM32_GTIM_CCR3_OFFSET), - stm32l4_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); + stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), + stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32_ATIM_RCR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_BDTR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_ATIM_DMAR_OFFSET)); } else #endif { sninfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(priv, STM32_GTIM_DCR_OFFSET), - stm32l4_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); + stm32_getreg16(priv, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(priv, STM32_GTIM_DMAR_OFFSET)); } } #endif /**************************************************************************** - * Name: stm32l4_tim2lower + * Name: stm32_tim2lower * * Description: * Map a timer number to a device structure * ****************************************************************************/ -static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) +static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { @@ -614,7 +614,7 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) } /**************************************************************************** - * Name: stm32l4_interrupt + * Name: stm32_interrupt * * Description: * Common timer interrupt handling. NOTE: Only 16-bit timers require timer @@ -623,10 +623,10 @@ static struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) ****************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(int irq, void *context, void *arg) +static int stm32_interrupt(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)arg; uint16_t regval; DEBUGASSERT(priv != NULL); @@ -635,18 +635,18 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * Nothing else is expected. */ - regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); DEBUGASSERT((regval & ATIM_SR_UIF) != 0); /* Clear the UIF interrupt bit */ - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Check the direction bit in the CR1 register and add or subtract the * maximum value, as appropriate. */ - regval = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + regval = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); if ((regval & ATIM_CR1_DIR) != 0) { priv->position -= (int32_t)0x0000ffff; @@ -661,7 +661,7 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l4_setup + * Name: stm32_setup * * Description: * This method is called when the driver is opened. The lower half driver @@ -670,10 +670,10 @@ static int stm32l4_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_setup(struct qe_lowerhalf_s *lower) +static int stm32_setup(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint16_t dier; uint32_t smcr; uint32_t ccmr1; @@ -690,7 +690,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Timer base configuration */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); /* Clear the direction bit (0=count up) and select the Counter Mode * (0=Edge aligned) @@ -698,23 +698,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) */ cr1 &= ~(GTIM_CR1_DIR | GTIM_CR1_CMS_MASK); - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Set the Autoreload value */ #if defined(HAVE_MIXEDWIDTH_TIMERS) if (priv->config->width == 32) { - stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); } else { - stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); } #elif defined(HAVE_32BIT_TIMERS) - stm32l4_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); + stm32_putreg32(priv, STM32_GTIM_ARR_OFFSET, 0xffffffff); #else - stm32l4_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); + stm32_putreg16(priv, STM32_GTIM_ARR_OFFSET, 0xffff); #endif /* Set the timer prescaler value. @@ -736,7 +736,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * on the encoder resolution. */ - stm32l4_putreg16(priv, + stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); #if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) @@ -744,7 +744,7 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear the Repetition Counter value */ - stm32l4_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); + stm32_putreg16(priv, STM32_ATIM_RCR_OFFSET, 0); } #endif @@ -752,30 +752,30 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * and the repetition counter (only for TIM1 and TIM8) value immediately */ - stm32l4_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); + stm32_putreg16(priv, STM32_GTIM_EGR_OFFSET, GTIM_EGR_UG); /* GPIO pin configuration */ - stm32l4_configgpio(priv->config->ti1cfg); - stm32l4_configgpio(priv->config->ti2cfg); + stm32_configgpio(priv->config->ti1cfg); + stm32_configgpio(priv->config->ti2cfg); /* Set the encoder Mode 3 */ - smcr = stm32l4_getreg32(priv, STM32_GTIM_SMCR_OFFSET); + smcr = stm32_getreg32(priv, STM32_GTIM_SMCR_OFFSET); smcr &= ~GTIM_SMCR_SMS_MASK; smcr |= GTIM_SMCR_ENCMD3; - stm32l4_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); + stm32_putreg32(priv, STM32_GTIM_SMCR_OFFSET, smcr); /* TI1 Channel Configuration */ /* Disable the Channel 1: Reset the CC1E Bit */ - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC1E; - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC1=TI1 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -790,28 +790,28 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC1PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC1PSC_SHIFT); - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* TI2 Channel Configuration */ /* Disable the Channel 2: Reset the CC2E Bit */ - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); ccer &= ~GTIM_CCER_CC2E; - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); - ccer = stm32l4_getreg16(priv, STM32_GTIM_CCER_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccer = stm32_getreg16(priv, STM32_GTIM_CCER_OFFSET); /* Select the Input IC2=TI2 and set the filter fSAMPLING=fDTS/4, N=6 */ @@ -826,23 +826,23 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Write to TIM CCMR1 and CCER registers */ - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); - stm32l4_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg16(priv, STM32_GTIM_CCER_OFFSET, ccer); /* Set the Input Capture Prescaler value: Capture performed each time an * edge is detected on the capture input. */ - ccmr1 = stm32l4_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); + ccmr1 = stm32_getreg32(priv, STM32_GTIM_CCMR1_OFFSET); ccmr1 &= ~GTIM_CCMR1_IC2PSC_MASK; ccmr1 |= (GTIM_CCMR_ICPSC_NOPSC << GTIM_CCMR1_IC2PSC_SHIFT); - stm32l4_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); + stm32_putreg32(priv, STM32_GTIM_CCMR1_OFFSET, ccmr1); /* Disable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier &= ~GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); /* There is no need for interrupts with 32-bit timers */ @@ -853,10 +853,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, stm32l4_interrupt, priv); + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); if (ret < 0) { - stm32l4_shutdown(lower); + stm32_shutdown(lower); return ret; } @@ -868,14 +868,14 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) /* Reset the Update Disable Bit */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 &= ~GTIM_CR1_UDIS; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* Reset the URS Bit */ cr1 &= ~GTIM_CR1_URS; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); /* There is no need for interrupts with 32-bit timers */ @@ -886,30 +886,30 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) { /* Clear any pending update interrupts */ - regval = stm32l4_getreg16(priv, STM32_GTIM_SR_OFFSET); - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); + regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, regval & ~GTIM_SR_UIF); /* Then enable the update interrupt */ - dier = stm32l4_getreg16(priv, STM32_GTIM_DIER_OFFSET); + dier = stm32_getreg16(priv, STM32_GTIM_DIER_OFFSET); dier |= GTIM_DIER_UIE; - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, dier); } #endif /* Enable the TIM Counter */ - cr1 = stm32l4_getreg16(priv, STM32_GTIM_CR1_OFFSET); + cr1 = stm32_getreg16(priv, STM32_GTIM_CR1_OFFSET); cr1 |= GTIM_CR1_CEN; - stm32l4_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); + stm32_putreg16(priv, STM32_GTIM_CR1_OFFSET, cr1); - stm32l4_dumpregs(priv, "After setup"); + stm32_dumpregs(priv, "After setup"); return OK; } /**************************************************************************** - * Name: stm32l4_shutdown + * Name: stm32_shutdown * * Description: * This method is called when the driver is closed. The lower half driver @@ -918,10 +918,10 @@ static int stm32l4_setup(struct qe_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) +static int stm32_shutdown(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags; uint32_t regaddr; uint32_t regval; @@ -943,8 +943,8 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) /* Disable further interrupts and stop the timer */ - stm32l4_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); - stm32l4_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_DIER_OFFSET, 0); + stm32_putreg16(priv, STM32_GTIM_SR_OFFSET, 0); /* Determine which timer to reset */ @@ -992,7 +992,7 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) } /* Reset the timer - stopping the output and putting the timer back - * into a state where stm32l4_start() can be called. + * into a state where stm32_start() can be called. */ regval = getreg32(regaddr); @@ -1005,37 +1005,37 @@ static int stm32l4_shutdown(struct qe_lowerhalf_s *lower) sninfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", regaddr, resetbit); - stm32l4_dumpregs(priv, "After stop"); + stm32_dumpregs(priv, "After stop"); /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); pincfg |= STM32_GPIO_INPUT_FLOAT; - stm32l4_configgpio(pincfg); + stm32_configgpio(pincfg); return OK; } /**************************************************************************** - * Name: stm32l4_position + * Name: stm32_position * * Description: * Return the current position measurement. * ****************************************************************************/ -static int stm32l4_position(struct qe_lowerhalf_s *lower, +static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; int32_t position; @@ -1050,7 +1050,7 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, do { position = priv->position; - count = stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); + count = stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); verify = priv->position; } while (position != verify); @@ -1062,23 +1062,23 @@ static int stm32l4_position(struct qe_lowerhalf_s *lower, #else /* Return the counter value */ - *pos = (int32_t)stm32l4_getreg32(priv, STM32_GTIM_CNT_OFFSET); + *pos = (int32_t)stm32_getreg32(priv, STM32_GTIM_CNT_OFFSET); #endif return OK; } /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset * * Description: * Reset the position measurement to zero. * ****************************************************************************/ -static int stm32l4_reset(struct qe_lowerhalf_s *lower) +static int stm32_reset(struct qe_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; #ifdef HAVE_16BIT_TIMERS irqstate_t flags; @@ -1090,7 +1090,7 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) */ flags = spin_lock_irqsave(&priv->lock); - stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); priv->position = 0; spin_unlock_irqrestore(&priv->lock, flags); #else @@ -1099,20 +1099,20 @@ static int stm32l4_reset(struct qe_lowerhalf_s *lower) /* Reset the counter to zero */ - stm32l4_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); + stm32_putreg32(priv, STM32_GTIM_CNT_OFFSET, 0); #endif return OK; } /**************************************************************************** - * Name: stm32l4_ioctl + * Name: stm32_ioctl * * Description: * Lower-half logic may support platform-specific ioctl commands * ****************************************************************************/ -static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, +static int stm32_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg) { /* No ioctl commands supported */ @@ -1127,7 +1127,7 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -1143,16 +1143,16 @@ static int stm32l4_ioctl(struct qe_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim) +int stm32_qeinitialize(const char *devpath, int tim) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; /* Find the pre-allocated timer state structure corresponding to this * timer */ - priv = stm32l4_tim2lower(tim); + priv = stm32_tim2lower(tim); if (!priv) { snerr("ERROR: TIM%d support not configured\n", tim); @@ -1178,7 +1178,7 @@ int stm32l4_qeinitialize(const char *devpath, int tim) /* Make sure that the timer is in the shutdown state */ - stm32l4_shutdown((struct qe_lowerhalf_s *)priv); + stm32_shutdown((struct qe_lowerhalf_s *)priv); /* The driver is now in-use */ diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h index 9d88bdb8323..fefe8c0d9e9 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qeinitialize + * Name: stm32_qeinitialize * * Description: * Initialize a quadrature encoder interface. @@ -95,7 +95,7 @@ * ****************************************************************************/ -int stm32l4_qeinitialize(const char *devpath, int tim); +int stm32_qeinitialize(const char *devpath, int tim); #endif /* CONFIG_SENSORS_QENCODER */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QENCODER_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index f3d3bc994a3..85c80431636 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -149,7 +149,7 @@ * designed to support multiple QSPI peripherals. */ -struct stm32l4_qspidev_s +struct stm32_qspidev_s { struct qspi_dev_s qspi; /* Externally visible part of the QSPI interface */ uint32_t base; /* QSPI controller register base address */ @@ -180,7 +180,7 @@ struct stm32l4_qspidev_s /* Debug stuff */ #ifdef CONFIG_STM32L4_QSPI_DMADEBUG - struct stm32l4_dmaregs_s dmaregs[DMA_NSAMPLES]; + struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif #ifdef CONFIG_STM32L4_QSPI_REGDEBUG @@ -234,19 +234,19 @@ struct qspi_xctnspec_s /* Helpers */ #ifdef CONFIG_STM32L4_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else # define qspi_checkreg(priv,wr,value,address) (false) #endif -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset); -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset); #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg); #else # define qspi_dumpregs(priv,msg) @@ -270,9 +270,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg); #ifdef CONFIG_STM32L4_QSPI_DMA # ifdef CONFIG_STM32L4_QSPI_DMADEBUG -# define qspi_dma_sample(s,i) stm32l4_dmasample((s)->dmach, &(s)->dmaregs[i]) -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv); -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv); +# define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # else # define qspi_dma_sample(s,i) # define qspi_dma_sampleinit(s) @@ -301,7 +301,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer); /* Initialization */ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv); +static int qspi_hw_initialize(struct stm32_qspidev_s *priv); /**************************************************************************** * Private Data @@ -326,7 +326,7 @@ static const struct qspi_ops_s g_qspi0ops = /* This is the overall state of the QSPI0 controller */ -static struct stm32l4_qspidev_s g_qspi0dev = +static struct stm32_qspidev_s g_qspi0dev = { .qspi = { @@ -367,7 +367,7 @@ static struct stm32l4_qspidev_s g_qspi0dev = ****************************************************************************/ #ifdef CONFIG_STM32L4_QSPI_REGDEBUG -static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, +static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { if (wr == priv->wrlast && /* Same kind of access? */ @@ -412,7 +412,7 @@ static bool qspi_checkreg(struct stm32l4_qspidev_s *priv, bool wr, * ****************************************************************************/ -static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, +static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, unsigned int offset) { uint32_t address = priv->base + offset; @@ -436,7 +436,7 @@ static inline uint32_t qspi_getreg(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, +static inline void qspi_putreg(struct stm32_qspidev_s *priv, uint32_t value, unsigned int offset) { uint32_t address = priv->base + offset; @@ -467,7 +467,7 @@ static inline void qspi_putreg(struct stm32l4_qspidev_s *priv, ****************************************************************************/ #ifdef CONFIG_DEBUG_SPI_INFO -static void qspi_dumpregs(struct stm32l4_qspidev_s *priv, const char *msg) +static void qspi_dumpregs(struct stm32_qspidev_s *priv, const char *msg) { uint32_t regval; spiinfo("%s:\n", msg); @@ -596,16 +596,16 @@ static void qspi_dumpgpioconfig(const char *msg) * ****************************************************************************/ -static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv) { /* Put contents of register samples into a known state */ memset(priv->dmaregs, 0xff, - DMA_NSAMPLES * sizeof(struct stm32l4_dmaregs_s)); + DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); /* Then get the initial samples */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_INITIAL]); } /**************************************************************************** @@ -622,27 +622,27 @@ static void qspi_dma_sampleinit(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) +static void qspi_dma_sampledone(struct stm32_qspidev_s *priv) { /* Sample the final registers */ - stm32l4_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); + stm32_dmasample(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER]); /* Then dump the sampled DMA registers */ /* Initial register values */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_INITIAL], "Initial Registers"); /* Register values after DMA setup */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_SETUP], "After DMA Setup"); /* Register values after DMA start */ - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_AFTER_START], "After DMA Start"); /* Register values at the time of the TX and RX DMA callbacks @@ -655,16 +655,16 @@ static void qspi_dma_sampledone(struct stm32l4_qspidev_s *priv) if (priv->result == -ETIMEDOUT) { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_TIMEOUT], "At DMA timeout"); } else { - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_CALLBACK], "At DMA callback"); } - stm32l4_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], + stm32_dmadump(priv->dmach, &priv->dmaregs[DMA_END_TRANSFER], "At End-of-Transfer"); } #endif @@ -944,7 +944,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, * ****************************************************************************/ -static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, +static void qspi_waitstatusflags(struct stm32_qspidev_s *priv, uint32_t mask, int polarity) { uint32_t regval; @@ -975,7 +975,7 @@ static void qspi_waitstatusflags(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static void qspi_abort(struct stm32l4_qspidev_s *priv) +static void qspi_abort(struct stm32_qspidev_s *priv) { uint32_t regval; @@ -1000,7 +1000,7 @@ static void qspi_abort(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -static void qspi_ccrconfig(struct stm32l4_qspidev_s *priv, +static void qspi_ccrconfig(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn, uint8_t fctn) { @@ -1290,7 +1290,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) static void qspi_dma_timeout(wdparm_t arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Sample DMA registers at the time of the timeout */ @@ -1326,7 +1326,7 @@ static void qspi_dma_timeout(wdparm_t arg) static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)arg; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)arg; DEBUGASSERT(priv != NULL); /* Cancel the watchdog timeout */ @@ -1374,7 +1374,7 @@ static void qspi_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, +static inline uintptr_t qspi_regaddr(struct stm32_qspidev_s *priv, unsigned int offset) { return priv->base + offset; @@ -1396,7 +1396,7 @@ static inline uintptr_t qspi_regaddr(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, +static int qspi_memory_dma(struct stm32_qspidev_s *priv, struct qspi_meminfo_s *meminfo, struct qspi_xctnspec_s *xctn) { @@ -1425,7 +1425,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, DMA_CCR_MINC); } - stm32l4_dmasetup(priv->dmach, qspi_regaddr(priv, + stm32_dmasetup(priv->dmach, qspi_regaddr(priv, STM32_QUADSPI_DR_OFFSET), (uint32_t)meminfo->buffer, meminfo->buflen, dmaflags); @@ -1446,7 +1446,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, /* Start the DMA */ priv->result = -EBUSY; - stm32l4_dmastart(priv->dmach, qspi_dma_callback, priv, false); + stm32_dmastart(priv->dmach, qspi_dma_callback, priv, false); qspi_dma_sample(priv, DMA_AFTER_START); @@ -1510,7 +1510,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * on an error condition). */ - stm32l4_dmastop(priv->dmach); + stm32_dmastop(priv->dmach); regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); regval &= ~QSPI_CR_DMAEN; @@ -1543,7 +1543,7 @@ static int qspi_memory_dma(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_receive_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; @@ -1621,7 +1621,7 @@ static int qspi_receive_blocking(struct stm32l4_qspidev_s *priv, * ****************************************************************************/ -static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, +static int qspi_transmit_blocking(struct stm32_qspidev_s *priv, struct qspi_xctnspec_s *xctn) { int ret = OK; @@ -1692,7 +1692,7 @@ static int qspi_transmit_blocking(struct stm32l4_qspidev_s *priv, static int qspi_lock(struct qspi_dev_s *dev, bool lock) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; int ret; spiinfo("lock=%d\n", lock); @@ -1725,7 +1725,7 @@ static int qspi_lock(struct qspi_dev_s *dev, bool lock) static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t actual; uint32_t prescaler; uint32_t regval; @@ -1822,7 +1822,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; if (priv->memmap) @@ -1924,7 +1924,7 @@ static void qspi_setbits(struct qspi_dev_s *dev, int nbits) static int qspi_command(struct qspi_dev_s *dev, struct qspi_cmdinfo_s *cmdinfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -2106,7 +2106,7 @@ static int qspi_command(struct qspi_dev_s *dev, static int qspi_memory(struct qspi_dev_s *dev, struct qspi_meminfo_s *meminfo) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; struct qspi_xctnspec_s xctn; int ret; @@ -2346,7 +2346,7 @@ static void qspi_free(struct qspi_dev_s *dev, void *buffer) * ****************************************************************************/ -static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) +static int qspi_hw_initialize(struct stm32_qspidev_s *priv) { uint32_t regval; @@ -2429,7 +2429,7 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -2442,9 +2442,9 @@ static int qspi_hw_initialize(struct stm32l4_qspidev_s *priv) * ****************************************************************************/ -struct qspi_dev_s *stm32l4_qspi_initialize(int intf) +struct qspi_dev_s *stm32_qspi_initialize(int intf) { - struct stm32l4_qspidev_s *priv; + struct stm32_qspidev_s *priv; uint32_t regval; int ret; @@ -2482,12 +2482,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) /* Configure multiplexed pins as connected on the board. */ - stm32l4_configgpio(GPIO_QSPI_CS); - stm32l4_configgpio(GPIO_QSPI_IO0); - stm32l4_configgpio(GPIO_QSPI_IO1); - stm32l4_configgpio(GPIO_QSPI_IO2); - stm32l4_configgpio(GPIO_QSPI_IO3); - stm32l4_configgpio(GPIO_QSPI_SCK); + stm32_configgpio(GPIO_QSPI_CS); + stm32_configgpio(GPIO_QSPI_IO0); + stm32_configgpio(GPIO_QSPI_IO1); + stm32_configgpio(GPIO_QSPI_IO2); + stm32_configgpio(GPIO_QSPI_IO3); + stm32_configgpio(GPIO_QSPI_SCK); } else { @@ -2506,7 +2506,7 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf) if (priv->candma) { - priv->dmach = stm32l4_dmachannel(DMACHAN_QUADSPI); + priv->dmach = stm32_dmachannel(DMACHAN_QUADSPI); if (!priv->dmach) { spierr("ERROR: Failed to allocate the DMA channel\n"); @@ -2557,7 +2557,7 @@ errout_with_dmach: #ifdef CONFIG_STM32L4_QSPI_DMA if (priv->dmach) { - stm32l4_dmafree(priv->dmach); + stm32_dmafree(priv->dmach); priv->dmach = NULL; } #endif @@ -2566,7 +2566,7 @@ errout_with_dmach: } /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -2580,11 +2580,11 @@ errout_with_dmach: * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; uint32_t regval; struct qspi_xctnspec_s xctn; @@ -2658,7 +2658,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -2671,9 +2671,9 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev) +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) { - struct stm32l4_qspidev_s *priv = (struct stm32l4_qspidev_s *)dev; + struct stm32_qspidev_s *priv = (struct stm32_qspidev_s *)dev; qspi_lock(dev, true); diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index f2e7fd119a9..e4f9c9cec22 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -68,7 +68,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_qspi_initialize + * Name: stm32_qspi_initialize * * Description: * Initialize the selected QSPI port in master mode @@ -82,10 +82,10 @@ extern "C" ****************************************************************************/ struct qspi_dev_s; -struct qspi_dev_s *stm32l4_qspi_initialize(int intf); +struct qspi_dev_s *stm32_qspi_initialize(int intf); /**************************************************************************** - * Name: stm32l4_qspi_enter_memorymapped + * Name: stm32_qspi_enter_memorymapped * * Description: * Put the QSPI device into memory mapped mode @@ -100,12 +100,12 @@ struct qspi_dev_s *stm32l4_qspi_initialize(int intf); * ****************************************************************************/ -void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, +void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, const struct qspi_meminfo_s *meminfo, uint32_t lpto); /**************************************************************************** - * Name: stm32l4_qspi_exit_memorymapped + * Name: stm32_qspi_exit_memorymapped * * Description: * Take the QSPI device out of memory mapped mode @@ -118,7 +118,7 @@ void stm32l4_qspi_enter_memorymapped(struct qspi_dev_s *dev, * ****************************************************************************/ -void stm32l4_qspi_exit_memorymapped(struct qspi_dev_s *dev); +void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 04af2e8fcfe..a397f68af72 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -37,7 +37,7 @@ #include "chip.h" #include "stm32l4_rcc.h" #include "stm32l4_flash.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_waste.h" #include "stm32l4_rtc.h" @@ -105,7 +105,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -122,7 +122,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -143,7 +143,7 @@ static inline void rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -155,7 +155,7 @@ static inline void rcc_resetbkp(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -165,7 +165,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -175,7 +175,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l4_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -189,7 +189,7 @@ void stm32l4_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -197,7 +197,7 @@ void stm32l4_clockconfig(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -207,7 +207,7 @@ void stm32l4_clockconfig(void) } /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -217,12 +217,12 @@ void stm32l4_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -233,13 +233,13 @@ void stm32l4_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l4_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -247,7 +247,7 @@ void stm32l4_clockenable(void) * board.h */ - stm32l4_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index e17ed34b7b1..a4287889351 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -64,7 +64,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. @@ -82,7 +82,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32l4_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -99,7 +99,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -109,7 +109,7 @@ static inline void stm32l4_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -119,10 +119,10 @@ static inline void stm32l4_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l4_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l4_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L4 board may replace the "standard" board clock configuration @@ -131,11 +131,11 @@ void stm32l4_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -void stm32l4_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l4_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -144,12 +144,12 @@ void stm32l4_board_clockconfig(void); * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32l4_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l4_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -160,11 +160,11 @@ void stm32l4_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l4_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -177,27 +177,27 @@ void stm32l4_clockenable(void); * ****************************************************************************/ -void stm32l4_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l4_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l4_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l4_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index c5480f1af84..4447ffcf6eb 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -48,11 +48,11 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32l4_rng_initialize(void); -static int stm32l4_rnginterrupt(int irq, void *context, void *arg); -static void stm32l4_rngenable(void); -static void stm32l4_rngdisable(void); -static ssize_t stm32l4_rngread(struct file *filep, char *buffer, size_t); +static int stm32_rng_initialize(void); +static int stm32_rnginterrupt(int irq, void *context, void *arg); +static void stm32_rngenable(void); +static void stm32_rngdisable(void); +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t); /**************************************************************************** * Private Types @@ -82,18 +82,18 @@ static const struct file_operations g_rngops = { NULL, /* open */ NULL, /* close */ - stm32l4_rngread, /* read */ + stm32_rngread, /* read */ }; /**************************************************************************** * Private functions ****************************************************************************/ -static int stm32l4_rng_initialize(void) +static int stm32_rng_initialize(void) { _info("Initializing RNG\n"); - if (irq_attach(STM32_IRQ_RNG, stm32l4_rnginterrupt, NULL)) + if (irq_attach(STM32_IRQ_RNG, stm32_rnginterrupt, NULL)) { /* We could not attach the ISR to the interrupt */ @@ -105,7 +105,7 @@ static int stm32l4_rng_initialize(void) return OK; } -static void stm32l4_rngenable(void) +static void stm32_rngenable(void) { uint32_t regval; @@ -121,7 +121,7 @@ static void stm32l4_rngenable(void) up_enable_irq(STM32_IRQ_RNG); } -static void stm32l4_rngdisable(void) +static void stm32_rngdisable(void) { uint32_t regval; @@ -133,7 +133,7 @@ static void stm32l4_rngdisable(void) putreg32(regval, STM32_RNG_CR); } -static int stm32l4_rnginterrupt(int irq, void *context, void *arg) +static int stm32_rnginterrupt(int irq, void *context, void *arg) { uint32_t rngsr; uint32_t data; @@ -216,7 +216,7 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) { /* Buffer filled, stop further interrupts. */ - stm32l4_rngdisable(); + stm32_rngdisable(); nxsem_post(&g_rngdev.rd_readsem); } @@ -224,10 +224,10 @@ static int stm32l4_rnginterrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_rngread + * Name: stm32_rngread ****************************************************************************/ -static ssize_t stm32l4_rngread(struct file *filep, +static ssize_t stm32_rngread(struct file *filep, char *buffer, size_t buflen) { int ret; @@ -251,7 +251,7 @@ static ssize_t stm32l4_rngread(struct file *filep, /* Enable RNG with interrupts */ - stm32l4_rngenable(); + stm32_rngenable(); /* Wait until the buffer is filled */ @@ -285,7 +285,7 @@ static ssize_t stm32l4_rngread(struct file *filep, #ifdef CONFIG_DEV_RANDOM void devrandom_register(void) { - stm32l4_rng_initialize(); + stm32_rng_initialize(); register_driver("/dev/random", &g_rngops, 0444, NULL); } #endif @@ -308,7 +308,7 @@ void devrandom_register(void) void devurandom_register(void) { #ifndef CONFIG_DEV_RANDOM - stm32l4_rng_initialize(); + stm32_rng_initialize(); #endif register_driver("/dev/urandom", &g_rngops, 0444, NULL); } diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index bc554c7564b..7292d5eb79a 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -208,7 +208,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -246,7 +246,7 @@ static inline void rtc_wprlock(void) /* Disable write access to the backup domain. */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -445,7 +445,7 @@ static void rtc_resume(void) } /**************************************************************************** - * Name: stm32l4_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -460,7 +460,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -474,7 +474,7 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ @@ -540,7 +540,7 @@ static int stm32l4_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -746,14 +746,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32l4_exti_alarm(true, false, true, stm32l4_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32l4_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -768,7 +768,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -809,7 +809,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -825,7 +825,7 @@ static int stm32l4_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -860,14 +860,14 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32l4_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); #if defined(CONFIG_STM32L4_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, @@ -902,7 +902,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -978,7 +978,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -988,7 +988,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -998,7 +998,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1018,7 +1018,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { #ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS @@ -1153,7 +1153,7 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1187,12 +1187,12 @@ int up_rtc_getdatetime(struct tm *tp) # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32l4_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32l4_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1270,9 +1270,9 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1283,7 +1283,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1293,7 +1293,7 @@ int stm32l4_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1322,11 +1322,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32l4_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1340,7 +1340,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1415,7 +1415,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1429,7 +1429,7 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1515,7 +1515,7 @@ errout_with_wprunlock: #endif /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1529,7 +1529,7 @@ errout_with_wprunlock: ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1542,7 +1542,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMA: { alarmreg = STM32_RTC_ALRMAR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1551,7 +1551,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMB: { alarmreg = STM32_RTC_ALRMBR; - ret = stm32l4_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1567,7 +1567,7 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32l4_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1581,18 +1581,18 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_rtc_wakeup_handler(int irq, void *context, +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32l4_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; putreg32(regval, STM32_RTC_ISR); - stm32l4_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1616,7 +1616,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32l4_exti_wakeup(true, false, true, stm32l4_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1644,7 +1644,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) #endif /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1659,7 +1659,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1788,7 +1788,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1801,7 +1801,7 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l4_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index 7a202e90d22..ebb8d093f81 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -118,7 +118,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -133,10 +133,10 @@ extern "C" * ****************************************************************************/ -bool stm32l4_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32l4_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -157,12 +157,12 @@ bool stm32l4_rtc_is_initialized(void); ****************************************************************************/ #ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS -int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32l4_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -179,11 +179,11 @@ int stm32l4_rtc_getdatetime_with_subseconds(struct tm *tp, #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32l4_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32l4_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -193,11 +193,11 @@ int stm32l4_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32l4_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32l4_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -210,10 +210,10 @@ bool stm32l4_rtc_havesettime(void); * ****************************************************************************/ -int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -226,10 +226,10 @@ int stm32l4_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32l4_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -242,13 +242,13 @@ int stm32l4_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32l4_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -262,11 +262,11 @@ int stm32l4_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32l4_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32l4_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -278,11 +278,11 @@ int stm32l4_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32l4_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32L4. General usage: @@ -291,7 +291,7 @@ int stm32l4_rtc_cancelperiodic(void); * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -305,7 +305,7 @@ int stm32l4_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c index 27e3aaabfc0..0d87286eb68 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc_lowerhalf.c @@ -52,7 +52,7 @@ ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32l4_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument to accompany callback */ @@ -64,7 +64,7 @@ struct stm32l4_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32l4_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32l4_cbinfo_s cbinfo[STM32_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,30 +97,30 @@ struct stm32l4_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -131,24 +131,24 @@ stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32l4_rdtime, - .settime = stm32l4_settime, - .havesettime = stm32l4_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32l4_setalarm, - .setrelative = stm32l4_setrelative, - .cancelalarm = stm32l4_cancelalarm, - .rdalarm = stm32l4_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32l4_setperiodic, - .cancelperiodic = stm32l4_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32L4 RTC device state */ -static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -159,7 +159,7 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -174,17 +174,17 @@ static struct stm32l4_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32l4_lowerhalf_s *lower; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32l4_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -207,7 +207,7 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32l4_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -222,13 +222,13 @@ static void stm32l4_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -247,7 +247,7 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -262,13 +262,13 @@ static int stm32l4_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -280,14 +280,14 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32l4_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32l4_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -300,13 +300,13 @@ static int stm32l4_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32l4_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32l4_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -323,11 +323,11 @@ static bool stm32l4_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -335,7 +335,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -356,13 +356,13 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32l4_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32l4_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -376,7 +376,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -394,7 +394,7 @@ static int stm32l4_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32l4_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -440,7 +440,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32l4_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -451,7 +451,7 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -468,16 +468,16 @@ stm32l4_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32l4_lowerhalf_s *priv; - struct stm32l4_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -498,7 +498,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, /* Then cancel the alarm */ - ret = stm32l4_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -507,7 +507,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -523,7 +523,7 @@ static int stm32l4_cancelalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -544,7 +544,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32l4_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -554,7 +554,7 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -570,14 +570,14 @@ static int stm32l4_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32l4_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -595,7 +595,7 @@ static int stm32l4_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32l4_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -614,14 +614,14 @@ static int stm32l4_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -630,8 +630,8 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32l4_rtc_setperiodic(&alarminfo->period, - stm32l4_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -639,7 +639,7 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32l4_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -655,13 +655,13 @@ stm32l4_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32l4_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32l4_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -671,7 +671,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32l4_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -683,7 +683,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -692,7 +692,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32l4_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32l4_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -704,7 +704,7 @@ static int stm32l4_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32l4_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index f30d0564e79..550b5a5b00e 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -142,7 +142,7 @@ struct sai_buffer_s /* The state of the one SAI peripheral */ -struct stm32l4_sai_s +struct stm32_sai_s { struct i2s_dev_s dev; /* Externally visible I2S interface */ uintptr_t base; /* SAI block register base address */ @@ -176,7 +176,7 @@ struct stm32l4_sai_s ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg); #else # define sai_dump_regs(s,m) #endif @@ -184,15 +184,15 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg); /* Buffer container helpers */ static struct sai_buffer_s * - sai_buf_allocate(struct stm32l4_sai_s *priv); -static void sai_buf_free(struct stm32l4_sai_s *priv, + sai_buf_allocate(struct stm32_sai_s *priv); +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer); -static void sai_buf_initialize(struct stm32l4_sai_s *priv); +static void sai_buf_initialize(struct stm32_sai_s *priv); /* DMA support */ #ifdef CONFIG_STM32L4_SAI_DMA -static void sai_schedule(struct stm32l4_sai_s *priv, int result); +static void sai_schedule(struct stm32_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -230,7 +230,7 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ #ifdef CONFIG_STM32L4_SAI1_A -static struct stm32l4_sai_s g_sai1a_priv = +static struct stm32_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_A_BASE, @@ -251,7 +251,7 @@ static struct stm32l4_sai_s g_sai1a_priv = #endif #ifdef CONFIG_STM32L4_SAI1_B -static struct stm32l4_sai_s g_sai1b_priv = +static struct stm32_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_B_BASE, @@ -274,7 +274,7 @@ static struct stm32l4_sai_s g_sai1b_priv = /* SAI2 state */ #ifdef CONFIG_STM32L4_SAI2_A -static struct stm32l4_sai_s g_sai2a_priv = +static struct stm32_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_A_BASE, @@ -295,7 +295,7 @@ static struct stm32l4_sai_s g_sai2a_priv = #endif #ifdef CONFIG_STM32L4_SAI2_B -static struct stm32l4_sai_s g_sai2b_priv = +static struct stm32_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_B_BASE, @@ -333,7 +333,7 @@ static struct stm32l4_sai_s g_sai2b_priv = * ****************************************************************************/ -static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) +static inline uint32_t sai_getbitrate(struct stm32_sai_s *priv) { /* Calculate the bitrate in Hz */ @@ -355,7 +355,7 @@ static inline uint32_t sai_getbitrate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) +static inline uint32_t sai_getreg(struct stm32_sai_s *priv, uint8_t offset) { return getreg32(priv->base + offset); } @@ -376,7 +376,7 @@ static inline uint32_t sai_getreg(struct stm32l4_sai_s *priv, uint8_t offset) * ****************************************************************************/ -static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, +static inline void sai_putreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->base + offset); @@ -399,7 +399,7 @@ static inline void sai_putreg(struct stm32l4_sai_s *priv, uint8_t offset, * ****************************************************************************/ -static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, +static void sai_modifyreg(struct stm32_sai_s *priv, uint8_t offset, uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -426,7 +426,7 @@ static void sai_modifyreg(struct stm32l4_sai_s *priv, uint8_t offset, ****************************************************************************/ #ifdef CONFIG_DEBUG_I2S_INFO -static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) +static void sai_dump_regs(struct stm32_sai_s *priv, const char *msg) { if (msg) i2sinfo("%s\n", msg); @@ -460,7 +460,7 @@ static void sai_dump_regs(struct stm32l4_sai_s *priv, const char *msg) * ****************************************************************************/ -static void sai_mckdivider(struct stm32l4_sai_s *priv) +static void sai_mckdivider(struct stm32_sai_s *priv) { uint32_t mckdiv; @@ -497,13 +497,13 @@ static void sai_mckdivider(struct stm32l4_sai_s *priv) static void sai_timeout(wdparm_t arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv != NULL); #ifdef CONFIG_STM32L4_SAI_DMA /* Cancel the DMA */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); #endif /* Then schedule completion of the transfer to occur on the worker @@ -531,7 +531,7 @@ static void sai_timeout(wdparm_t arg) ****************************************************************************/ #ifdef CONFIG_STM32L4_SAI_DMA -static int sai_dma_setup(struct stm32l4_sai_s *priv) +static int sai_dma_setup(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; struct ap_buffer_s *apb; @@ -621,7 +621,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) DEBUGASSERT(ntransfers > 0); - stm32l4_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SAI_DR_OFFSET, samp, ntransfers, priv->dma_ccr); /* Add the container to the list of active DMAs */ @@ -630,7 +630,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) /* Start the DMA, saving the container as the current active transfer */ - stm32l4_dmastart(priv->dma, sai_dma_callback, priv, false); + stm32_dmastart(priv->dma, sai_dma_callback, priv, false); /* Enable the transmitter */ @@ -675,7 +675,7 @@ static int sai_dma_setup(struct stm32l4_sai_s *priv) static void sai_worker(void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -759,7 +759,7 @@ static void sai_worker(void *arg) * ****************************************************************************/ -static void sai_schedule(struct stm32l4_sai_s *priv, int result) +static void sai_schedule(struct stm32_sai_s *priv, int result) { struct sai_buffer_s *bfcontainer; int ret; @@ -817,7 +817,7 @@ static void sai_schedule(struct stm32l4_sai_s *priv, int result) #ifdef CONFIG_STM32L4_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)arg; + struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv); /* Cancel the watchdog timeout */ @@ -847,7 +847,7 @@ static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; DEBUGASSERT(priv && rate > 0); @@ -877,7 +877,7 @@ static uint32_t sai_samplerate(struct i2s_dev_s *dev, uint32_t rate) static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; uint32_t setbits; DEBUGASSERT(priv && bits >= 8); @@ -947,7 +947,7 @@ static uint32_t sai_datawidth(struct i2s_dev_s *dev, int bits) static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -1052,7 +1052,7 @@ errout_with_lock: static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout) { - struct stm32l4_sai_s *priv = (struct stm32l4_sai_s *)dev; + struct stm32_sai_s *priv = (struct stm32_sai_s *)dev; struct sai_buffer_s *bfcontainer; uint32_t mode; irqstate_t flags; @@ -1144,7 +1144,7 @@ errout_with_lock: * ****************************************************************************/ -static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) +static struct sai_buffer_s *sai_buf_allocate(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; irqstate_t flags; @@ -1191,7 +1191,7 @@ static struct sai_buffer_s *sai_buf_allocate(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_buf_free(struct stm32l4_sai_s *priv, +static void sai_buf_free(struct stm32_sai_s *priv, struct sai_buffer_s *bfcontainer) { irqstate_t flags; @@ -1227,7 +1227,7 @@ static void sai_buf_free(struct stm32l4_sai_s *priv, * ****************************************************************************/ -static void sai_buf_initialize(struct stm32l4_sai_s *priv) +static void sai_buf_initialize(struct stm32_sai_s *priv) { int i; @@ -1252,7 +1252,7 @@ static void sai_buf_initialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -static void sai_portinitialize(struct stm32l4_sai_s *priv) +static void sai_portinitialize(struct stm32_sai_s *priv) { sai_dump_regs(priv, "Before initialization"); @@ -1272,7 +1272,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) #ifdef CONFIG_STM32L4_SAI_DMA /* Get DMA channel */ - priv->dma = stm32l4_dmachannel(priv->dma_ch); + priv->dma = stm32_dmachannel(priv->dma_ch); DEBUGASSERT(priv->dma); sai_modifyreg(priv, STM32_SAI_CR1_OFFSET, 0, SAI_CR1_DMAEN); @@ -1302,7 +1302,7 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -1315,9 +1315,9 @@ static void sai_portinitialize(struct stm32l4_sai_s *priv) * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf) +struct i2s_dev_s *stm32_sai_initialize(int intf) { - struct stm32l4_sai_s *priv; + struct stm32_sai_s *priv; irqstate_t flags; flags = enter_critical_section(); @@ -1330,11 +1330,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI1 Block A Selected\n"); priv = &g_sai1a_priv; - stm32l4_configgpio(GPIO_SAI1_SD_A); + stm32_configgpio(GPIO_SAI1_SD_A); # ifndef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI1_FS_A); - stm32l4_configgpio(GPIO_SAI1_SCK_A); - stm32l4_configgpio(GPIO_SAI1_MCLK_A); + stm32_configgpio(GPIO_SAI1_FS_A); + stm32_configgpio(GPIO_SAI1_SCK_A); + stm32_configgpio(GPIO_SAI1_MCLK_A); # endif break; } @@ -1346,11 +1346,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI1 Block B Selected\n"); priv = &g_sai1b_priv; - stm32l4_configgpio(GPIO_SAI1_SD_B); + stm32_configgpio(GPIO_SAI1_SD_B); # ifndef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI1_FS_B); - stm32l4_configgpio(GPIO_SAI1_SCK_B); - stm32l4_configgpio(GPIO_SAI1_MCLK_B); + stm32_configgpio(GPIO_SAI1_FS_B); + stm32_configgpio(GPIO_SAI1_SCK_B); + stm32_configgpio(GPIO_SAI1_MCLK_B); # endif break; } @@ -1362,11 +1362,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI2 Block A Selected\n"); priv = &g_sai2a_priv; - stm32l4_configgpio(GPIO_SAI2_SD_A); + stm32_configgpio(GPIO_SAI2_SD_A); # ifndef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B - stm32l4_configgpio(GPIO_SAI2_FS_A); - stm32l4_configgpio(GPIO_SAI2_SCK_A); - stm32l4_configgpio(GPIO_SAI2_MCLK_A); + stm32_configgpio(GPIO_SAI2_FS_A); + stm32_configgpio(GPIO_SAI2_SCK_A); + stm32_configgpio(GPIO_SAI2_MCLK_A); # endif break; } @@ -1378,11 +1378,11 @@ struct i2s_dev_s *stm32l4_sai_initialize(int intf) i2sinfo("SAI2 Block B Selected\n"); priv = &g_sai2b_priv; - stm32l4_configgpio(GPIO_SAI2_SD_B); + stm32_configgpio(GPIO_SAI2_SD_B); # ifndef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A - stm32l4_configgpio(GPIO_SAI2_FS_B); - stm32l4_configgpio(GPIO_SAI2_SCK_B); - stm32l4_configgpio(GPIO_SAI2_MCLK_B); + stm32_configgpio(GPIO_SAI2_FS_B); + stm32_configgpio(GPIO_SAI2_SCK_B); + stm32_configgpio(GPIO_SAI2_MCLK_B); # endif break; } diff --git a/arch/arm/src/stm32l4/stm32l4_sai.h b/arch/arm/src/stm32l4/stm32l4_sai.h index 69c305ba8b1..6f98ce3e3b5 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.h +++ b/arch/arm/src/stm32l4/stm32l4_sai.h @@ -71,7 +71,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_sai_initialize + * Name: stm32_sai_initialize * * Description: * Initialize the selected SAI block @@ -84,7 +84,7 @@ extern "C" * ****************************************************************************/ -struct i2s_dev_s *stm32l4_sai_initialize(int intf); +struct i2s_dev_s *stm32_sai_initialize(int intf); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index c1a1de20f1b..f33087ecc8d 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -1373,7 +1373,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * terminates on an error condition). */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -2127,7 +2127,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) * terminates on an error condition. */ - stm32l4_dmastop(priv->dma); + stm32_dmastop(priv->dma); } #endif @@ -2751,7 +2751,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* DMA must be possible to the buffer */ - if (!stm32l4_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri)) { return -EFAULT; @@ -2818,14 +2818,14 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN); - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_RXDMA32_CONFIG | priv->dmapri); /* Start the DMA */ stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; @@ -2883,7 +2883,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Configure the TX DMA */ - stm32l4_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, (buflen + 3) >> 2, SDMMC_TXDMA32_CONFIG | priv->dmapri); @@ -2893,7 +2893,7 @@ static int stm32_dmasendsetup(struct sdio_dev_s *dev, /* Start the DMA */ - stm32l4_dmastart(priv->dma, stm32_dmacallback, priv, false); + stm32_dmastart(priv->dma, stm32_dmacallback, priv, false); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); /* Enable TX interrupts */ @@ -3056,14 +3056,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) * utility in the scope of the board support package. */ #ifndef CONFIG_SDIO_MUXBUS - stm32l4_configgpio(GPIO_SDMMC1_D0); + stm32_configgpio(GPIO_SDMMC1_D0); #ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY - stm32l4_configgpio(GPIO_SDMMC1_D1); - stm32l4_configgpio(GPIO_SDMMC1_D2); - stm32l4_configgpio(GPIO_SDMMC1_D3); + stm32_configgpio(GPIO_SDMMC1_D1); + stm32_configgpio(GPIO_SDMMC1_D2); + stm32_configgpio(GPIO_SDMMC1_D3); #endif - stm32l4_configgpio(GPIO_SDMMC1_CK); - stm32l4_configgpio(GPIO_SDMMC1_CMD); + stm32_configgpio(GPIO_SDMMC1_CK); + stm32_configgpio(GPIO_SDMMC1_CMD); #endif } else @@ -3113,7 +3113,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) #ifdef CONFIG_STM32L4_SDMMC_DMA /* Allocate a DMA channel */ - priv->dma = stm32l4_dmachannel(dmachan); + priv->dma = stm32_dmachannel(dmachan); DEBUGASSERT(priv->dma); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index 084ae78ac50..f286b0cdf67 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -209,7 +209,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -323,9 +323,9 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev); static void stm32l4serial_dmashutdown(struct uart_dev_s *dev); static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv); +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv); +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev); @@ -442,7 +442,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 LPUART1 port. */ #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER -static struct stm32l4_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -504,7 +504,7 @@ static struct stm32l4_serial_s g_lpuart1priv = /* This describes the state of the STM32 USART1 port. */ #ifdef CONFIG_STM32L4_USART1_SERIALDRIVER -static struct stm32l4_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -566,7 +566,7 @@ static struct stm32l4_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32L4_USART2_SERIALDRIVER -static struct stm32l4_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -628,7 +628,7 @@ static struct stm32l4_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ #ifdef CONFIG_STM32L4_USART3_SERIALDRIVER -static struct stm32l4_serial_s g_usart3priv = +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -690,7 +690,7 @@ static struct stm32l4_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ #ifdef CONFIG_STM32L4_UART4_SERIALDRIVER -static struct stm32l4_serial_s g_uart4priv = +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -752,7 +752,7 @@ static struct stm32l4_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ #ifdef CONFIG_STM32L4_UART5_SERIALDRIVER -static struct stm32l4_serial_s g_uart5priv = +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -813,7 +813,7 @@ static struct stm32l4_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l4_serial_s * +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER @@ -858,7 +858,7 @@ static struct ****************************************************************************/ static inline -uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) +uint32_t stm32l4serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -867,7 +867,7 @@ uint32_t stm32l4serial_getreg(struct stm32l4_serial_s *priv, int offset) * Name: stm32l4serial_putreg ****************************************************************************/ -static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, +static inline void stm32l4serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -878,7 +878,7 @@ static inline void stm32l4serial_putreg(struct stm32l4_serial_s *priv, ****************************************************************************/ static inline -void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, +void stm32l4serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -906,7 +906,7 @@ void stm32l4serial_setusartint(struct stm32l4_serial_s *priv, * Name: up_restoreusartint ****************************************************************************/ -static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -922,7 +922,7 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, * Name: stm32l4serial_disableusartint ****************************************************************************/ -static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, +static void stm32l4serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -988,11 +988,11 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) +static int stm32l4serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l4_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1007,7 +1007,7 @@ static int stm32l4serial_dmanextrx(struct stm32l4_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) +static void stm32l4serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -1077,7 +1077,7 @@ static void stm32l4serial_setbaud_usart(struct stm32l4_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG #ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER -static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) +static void stm32l4serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -1115,8 +1115,8 @@ static void stm32l4serial_setbaud_lpuart(struct stm32l4_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l4serial_setformat(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ @@ -1220,7 +1220,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -1239,7 +1239,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l4_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1268,7 +1268,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1309,7 +1309,7 @@ static void stm32l4serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l4_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1358,7 +1358,7 @@ static void stm32l4serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1384,8 +1384,8 @@ static void stm32l4serial_pm_setsuspend(bool suspend) static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1456,14 +1456,14 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l4serial_setup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l4_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1474,18 +1474,18 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1499,15 +1499,15 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l4_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_configgpio(priv->rs485_dir_gpio); - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1582,8 +1582,8 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1600,14 +1600,14 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l4_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1618,7 +1618,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1645,7 +1645,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -1656,7 +1656,7 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -1675,8 +1675,8 @@ static int stm32l4serial_dmasetup(struct uart_dev_s *dev) static void stm32l4serial_shutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1707,32 +1707,32 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l4_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l4_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l4_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l4_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1749,8 +1749,8 @@ static void stm32l4serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1758,11 +1758,11 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l4_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l4_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1785,8 +1785,8 @@ static void stm32l4serial_dmashutdown(struct uart_dev_s *dev) static int stm32l4serial_attach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1816,8 +1816,8 @@ static int stm32l4serial_attach(struct uart_dev_s *dev) static void stm32l4serial_detach(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1836,7 +1836,7 @@ static void stm32l4serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1901,7 +1901,7 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l4serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1967,8 +1967,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1977,15 +1977,15 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l4_serial_s *user = - (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *user = + (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32l4_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -2031,7 +2031,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -2042,7 +2042,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l4_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2268,7 +2268,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l4_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2285,7 +2285,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l4_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2348,8 +2348,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, static int stm32l4serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2378,8 +2378,8 @@ static int stm32l4serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2441,8 +2441,8 @@ static void stm32l4serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2476,8 +2476,8 @@ static bool stm32l4serial_rxavailable(struct uart_dev_s *dev) static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) @@ -2485,7 +2485,7 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l4_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2560,8 +2560,8 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l4serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l4serial_dmanextrx(priv) != priv->rxdmanext) @@ -2599,14 +2599,14 @@ static int stm32l4serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) +static void stm32l4serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2617,7 +2617,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l4_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2638,7 +2638,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, false); } else @@ -2649,7 +2649,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l4_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l4serial_dmarxcallback, (void *)priv, true); } @@ -2670,7 +2670,7 @@ static void stm32l4serial_dmareenable(struct stm32l4_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) +static bool stm32l4serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2721,8 +2721,8 @@ static bool stm32l4serial_dmaiflowrestart(struct stm32l4_serial_s *priv) #ifdef SERIAL_HAVE_RXDMA static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2756,8 +2756,8 @@ static void stm32l4serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_RXDMA static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2777,13 +2777,13 @@ static bool stm32l4serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l4serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l4_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2800,8 +2800,8 @@ static void stm32l4serial_send(struct uart_dev_s *dev, int ch) static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2873,8 +2873,8 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l4serial_txready(struct uart_dev_s *dev) { - struct stm32l4_serial_s *priv = - (struct stm32l4_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l4serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } @@ -2892,7 +2892,7 @@ static bool stm32l4serial_txready(struct uart_dev_s *dev) static void stm32l4serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l4_serial_s *priv = (struct stm32l4_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l4serial_dmarxavailable(&priv->dev)) { @@ -3051,7 +3051,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l4_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -3060,7 +3060,7 @@ static int stm32l4serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l4_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3224,7 +3224,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3235,7 +3235,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3298,7 +3298,7 @@ void stm32l4_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l4_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l4serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index c2864c40c2c..b69995cb042 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l4_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,7 +73,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_dma.h" #include "stm32l4_spi.h" @@ -132,7 +132,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -173,37 +173,37 @@ struct stm32l4_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv); -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv); -static int spi_dmatxwait(struct stm32l4_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -251,16 +251,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l4_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -309,16 +309,16 @@ static struct stm32l4_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l4_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,13 +331,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -365,16 +365,16 @@ static struct stm32l4_spidev_s g_spi2dev = static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l4_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l4_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l4_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,13 +387,13 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l4_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l4_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { @@ -436,7 +436,7 @@ static struct stm32l4_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l4_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l4_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,7 +518,7 @@ static inline void spi_putreg8(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -543,7 +543,7 @@ static inline uint16_t spi_readword(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -569,7 +569,7 @@ static inline uint8_t spi_readbyte(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l4_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -596,7 +596,7 @@ static inline void spi_writeword(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l4_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l4_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -636,7 +636,7 @@ static inline bool spi_16bitmode(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmarxwait(struct stm32l4_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -669,7 +669,7 @@ static int spi_dmarxwait(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static int spi_dmatxwait(struct stm32l4_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -702,7 +702,7 @@ static int spi_dmatxwait(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -717,7 +717,7 @@ static inline void spi_dmarxwakeup(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -734,7 +734,7 @@ static inline void spi_dmatxwakeup(struct stm32l4_spidev_s *priv) #ifdef CONFIG_STM32L4_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -754,7 +754,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32L4_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -772,7 +772,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -809,7 +809,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, /* Configure the RX DMA */ - stm32l4_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -823,7 +823,7 @@ static void spi_dmarxsetup(struct stm32l4_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -861,7 +861,7 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, /* Setup the TX DMA */ - stm32l4_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -875,10 +875,10 @@ static void spi_dmatxsetup(struct stm32l4_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l4_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -891,10 +891,10 @@ static inline void spi_dmarxstart(struct stm32l4_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI_DMA -static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l4_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -914,7 +914,7 @@ static inline void spi_dmatxstart(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -948,7 +948,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l4_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -981,7 +981,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1089,7 +1089,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1157,7 +1157,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1290,7 +1290,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1364,7 +1364,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1465,14 +1465,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; #ifdef CONFIG_STM32L4_DMACAPABLE if ((txbuffer && - !stm32l4_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l4_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1662,8 +1662,8 @@ static void spi_recvblock(struct spi_dev_s *dev, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l4_spidev_s *priv = (struct stm32l4_spidev_s *)((char *)cb - - offsetof(struct stm32l4_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1715,7 +1715,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l4_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1757,16 +1757,16 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32L4_SPI_DMA - /* Get DMA channels. NOTE: stm32l4_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32l4_dmachannel() + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32l4_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32l4_dmachannel(priv->rxch); - priv->txdma = stm32l4_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1791,7 +1791,7 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1804,9 +1804,9 @@ static void spi_bus_initialize(struct stm32l4_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l4_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1823,9 +1823,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI1_SCK); - stm32l4_configgpio(GPIO_SPI1_MISO); - stm32l4_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1848,9 +1848,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI2_SCK); - stm32l4_configgpio(GPIO_SPI2_MISO); - stm32l4_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1873,9 +1873,9 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l4_configgpio(GPIO_SPI3_SCK); - stm32l4_configgpio(GPIO_SPI3_MISO); - stm32l4_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h index b946487353f..e71e9c67e46 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/stm32l4_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l4_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l4_spi1/2/...select and stm32l4_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l4_spi1/2/...select, - * stm32l4_spi1/2/...status, and stm32l4_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/...select() and stm32l4_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l4_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l4_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l4_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,28 +105,28 @@ struct spi_dev_s *stm32l4_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l4_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -147,19 +147,19 @@ int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1register(struct spi_dev_s *dev, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2register(struct spi_dev_s *dev, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3register(struct spi_dev_s *dev, +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index cda08e167a4..561447051ad 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_userspace.h" #include "stm32l4_start.h" @@ -149,10 +149,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l4_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l4_lowsetup(); - stm32l4_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -203,13 +203,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l4_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l4_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l4/stm32l4_start.h b/arch/arm/src/stm32l4/stm32l4_start.h index 60f19e7a16a..09fb1a5a1e5 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.h +++ b/arch/arm/src/stm32l4/stm32l4_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_START_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index dba5a51fd3f..164b1b62f41 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -107,24 +107,24 @@ * Private Types ****************************************************************************/ -struct stm32l4_tickless_s +struct stm32_tickless_s { - struct stm32l4_oneshot_s oneshot; - struct stm32l4_freerun_s freerun; + struct stm32_oneshot_s oneshot; + struct stm32_freerun_s freerun; }; /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32l4_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Called when the one shot timer expires @@ -141,7 +141,7 @@ static struct stm32l4_tickless_s g_tickless; * ****************************************************************************/ -static void stm32l4_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { tmrinfo("Expired...\n"); nxsched_process_timer(); @@ -185,22 +185,22 @@ void up_timer_initialize(void) /* Initialize the one-shot timer */ - ret = stm32l4_oneshot_initialize(&g_tickless.oneshot, + ret = stm32_oneshot_initialize(&g_tickless.oneshot, CONFIG_STM32L4_TICKLESS_ONESHOT, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_initialize failed\n"); + tmrerr("ERROR: stm32_oneshot_initialize failed\n"); DEBUGPANIC(); } #ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP /* Get the maximum delay of the one-shot timer in microseconds */ - ret = stm32l4_oneshot_max_delay(&g_tickless.oneshot, &max_delay); + ret = stm32_oneshot_max_delay(&g_tickless.oneshot, &max_delay); if (ret < 0) { - tmrerr("ERROR: stm32l4_oneshot_max_delay failed\n"); + tmrerr("ERROR: stm32_oneshot_max_delay failed\n"); DEBUGPANIC(); } @@ -219,12 +219,12 @@ void up_timer_initialize(void) /* Initialize the free-running timer */ - ret = stm32l4_freerun_initialize(&g_tickless.freerun, + ret = stm32_freerun_initialize(&g_tickless.freerun, CONFIG_STM32L4_TICKLESS_FREERUN, CONFIG_USEC_PER_TICK); if (ret < 0) { - tmrerr("ERROR: stm32l4_freerun_initialize failed\n"); + tmrerr("ERROR: stm32_freerun_initialize failed\n"); DEBUGPANIC(); } } @@ -264,7 +264,7 @@ void up_timer_initialize(void) int up_timer_gettime(struct timespec *ts) { - return stm32l4_freerun_counter(&g_tickless.freerun, ts); + return stm32_freerun_counter(&g_tickless.freerun, ts); } /**************************************************************************** @@ -305,7 +305,7 @@ int up_timer_gettime(struct timespec *ts) int up_timer_cancel(struct timespec *ts) { - return stm32l4_oneshot_cancel(&g_tickless.oneshot, ts); + return stm32_oneshot_cancel(&g_tickless.oneshot, ts); } /**************************************************************************** @@ -335,7 +335,7 @@ int up_timer_cancel(struct timespec *ts) int up_timer_start(const struct timespec *ts) { - return stm32l4_oneshot_start(&g_tickless.oneshot, - stm32l4_oneshot_handler, NULL, ts); + return stm32_oneshot_start(&g_tickless.oneshot, + stm32_oneshot_handler, NULL, ts); } #endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index 24776426fab..d6b08e28659 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -39,7 +39,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_tim.h" @@ -207,10 +207,10 @@ /* TIM Device Structure */ -struct stm32l4_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l4_tim_ops_s *ops; - enum stm32l4_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -220,184 +220,184 @@ struct stm32l4_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev); -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l4_tim_getperiod(struct stm32l4_tim_dev_s *dev); -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev); -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l4_tim_ops_s stm32l4_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l4_tim_enable, - .disable = stm32l4_tim_disable, - .setmode = stm32l4_tim_setmode, - .setfreq = stm32l4_tim_setfreq, - .setclock = stm32l4_tim_setclock, - .getclock = stm32l4_tim_getclock, - .setperiod = stm32l4_tim_setperiod, - .getperiod = stm32l4_tim_getperiod, - .getcounter = stm32l4_tim_getcounter, - .setchannel = stm32l4_tim_setchannel, - .setcompare = stm32l4_tim_setcompare, - .getcapture = stm32l4_tim_getcapture, - .setisr = stm32l4_tim_setisr, - .enableint = stm32l4_tim_enableint, - .disableint = stm32l4_tim_disableint, - .ackint = stm32l4_tim_ackint, - .checkint = stm32l4_tim_checkint, - .dump_regs = stm32l4_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32L4_TIM1 -struct stm32l4_tim_priv_s stm32l4_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM2 -struct stm32l4_tim_priv_s stm32l4_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM3 -struct stm32l4_tim_priv_s stm32l4_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM4 -struct stm32l4_tim_priv_s stm32l4_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM5 -struct stm32l4_tim_priv_s stm32l4_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM6 -struct stm32l4_tim_priv_s stm32l4_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM7 -struct stm32l4_tim_priv_s stm32l4_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM8 -struct stm32l4_tim_priv_s stm32l4_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM15 -struct stm32l4_tim_priv_s stm32l4_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM16 -struct stm32l4_tim_priv_s stm32l4_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32L4_TIM17 -struct stm32l4_tim_priv_s stm32l4_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l4_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -408,51 +408,51 @@ struct stm32l4_tim_priv_s stm32l4_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l4_getreg16(struct stm32l4_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_putreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l4_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l4_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32 @@ -460,14 +460,14 @@ static inline void stm32l4_modifyreg16(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l4_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32 @@ -475,49 +475,49 @@ static inline uint32_t stm32l4_getreg32(struct stm32l4_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l4_putreg32(struct stm32l4_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l4_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l4_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l4_tim_reload_counter(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l4_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l4_tim_enable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l4_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -525,14 +525,14 @@ static void stm32l4_tim_disable(struct stm32l4_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32l4_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l4_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -540,8 +540,8 @@ static void stm32l4_tim_reset(struct stm32l4_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l4_tim_gpioconfig(uint32_t cfg, - enum stm32l4_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: * Add support for input capture and bipolar dual outputs for TIM8 @@ -549,69 +549,69 @@ static void stm32l4_tim_gpioconfig(uint32_t cfg, if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l4_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l4_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l4_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32l4_tim_dumpregs(struct stm32l4_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32l4_tim_priv_s *priv = (struct stm32l4_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CR2_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_SMCR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_GTIM_SR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CNT_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_GTIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_CCR1_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR2_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR3_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_GTIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_GTIM_CCR4_OFFSET) ); if (priv->base == STM32_TIM1_BASE || priv->base == STM32_TIM8_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32_ATIM_RCR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_BDTR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_ATIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_ATIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32l4_getreg16(dev, STM32_GTIM_DCR_OFFSET), - stm32l4_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_GTIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_GTIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32l4_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -622,10 +622,10 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -667,16 +667,16 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, return -EINVAL; } - stm32l4_tim_reload_counter(dev); - stm32l4_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l4_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -684,10 +684,10 @@ static int stm32l4_tim_setmode(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -701,7 +701,7 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -711,7 +711,7 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -838,17 +838,17 @@ static int stm32l4_tim_setfreq(struct stm32l4_tim_dev_s *dev, /* Set the reload and prescaler values */ - stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); - stm32l4_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_GTIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32l4_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -860,7 +860,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, if (freq == 0) { - stm32l4_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -870,7 +870,7 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -963,16 +963,16 @@ static int stm32l4_tim_setclock(struct stm32l4_tim_dev_s *dev, prescaler = 0xffff; } - stm32l4_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32l4_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -984,7 +984,7 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -1054,46 +1054,46 @@ static uint32_t stm32l4_tim_getclock(struct stm32l4_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l4_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l4_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l4_tim_setperiod(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l4_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l4_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l4_tim_getperiod (struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l4_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l4_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l4_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32L4_TIM2) || defined(CONFIG_STM32L4_TIM5) - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM2 case STM32_TIM2_BASE: @@ -1112,12 +1112,12 @@ static uint32_t stm32l4_tim_getcounter(struct stm32l4_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l4_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -1136,7 +1136,7 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l4_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -1145,10 +1145,10 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l4_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -1194,15 +1194,15 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l4_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l4_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l4_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -1210,25 +1210,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1243,25 +1243,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1276,25 +1276,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1309,24 +1309,24 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1341,25 +1341,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1374,25 +1374,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1407,25 +1407,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1440,25 +1440,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1473,25 +1473,25 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l4_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1509,10 +1509,10 @@ static int stm32l4_tim_setchannel(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1520,19 +1520,19 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - stm32l4_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l4_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l4_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l4_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1543,10 +1543,10 @@ static int stm32l4_tim_setcompare(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1554,26 +1554,26 @@ static int stm32l4_tim_getcapture(struct stm32l4_tim_dev_s *dev, switch (channel) { case 1: - return stm32l4_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l4_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l4_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l4_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l4_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1581,7 +1581,7 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -1669,44 +1669,44 @@ static int stm32l4_tim_setisr(struct stm32l4_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l4_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l4_tim_enableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l4_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l4_tim_disableint(struct stm32l4_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l4_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l4_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l4_tim_ackint(struct stm32l4_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l4_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l4_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l4_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1715,12 +1715,12 @@ static int stm32l4_tim_checkint(struct stm32l4_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l4_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1728,76 +1728,76 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) { #ifdef CONFIG_STM32L4_TIM1 case 1: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L4_TIM2 case 2: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L4_TIM3 case 3: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L4_TIM4 case 4: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L4_TIM5 case 5: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L4_TIM6 case 6: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L4_TIM7 case 7: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L4_TIM8 case 8: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L4_TIM15 case 15: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L4_TIM16 case 16: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L4_TIM17 case 17: - dev = (struct stm32l4_tim_dev_s *)&stm32l4_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1808,30 +1808,30 @@ struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l4_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l4_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l4_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l4_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L4_TIM1 case STM32_TIM1_BASE: @@ -1904,7 +1904,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l4_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l4/stm32l4_tim.h b/arch/arm/src/stm32l4/stm32l4_tim.h index 338ca644aa2..dbb4ffe1096 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.h +++ b/arch/arm/src/stm32l4/stm32l4_tim.h @@ -74,14 +74,14 @@ extern "C" /* TIM Device Structure */ -struct stm32l4_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l4_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l4_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -118,7 +118,7 @@ enum stm32l4_tim_mode_e /* TIM Channel Modes */ -enum stm32l4_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -151,41 +151,41 @@ enum stm32l4_tim_channel_e /* TIM Operations */ -struct stm32l4_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l4_tim_dev_s *dev); - void (*disable)(struct stm32l4_tim_dev_s *dev); - int (*setmode)(struct stm32l4_tim_dev_s *dev, - enum stm32l4_tim_mode_e mode); - int (*setfreq)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32l4_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l4_tim_dev_s *dev); - void (*setperiod)(struct stm32l4_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l4_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l4_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l4_tim_dev_s *dev, uint8_t channel, - enum stm32l4_tim_channel_e mode); - int (*setcompare)(struct stm32l4_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l4_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l4_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l4_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l4_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l4_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32l4_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -194,14 +194,14 @@ struct stm32l4_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l4_tim_dev_s *stm32l4_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -219,7 +219,7 @@ int stm32l4_tim_deinit(struct stm32l4_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index 35f42694a4a..c01128d68c3 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -92,10 +92,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l4_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l4_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -108,17 +108,17 @@ struct stm32l4_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower); -static int stm32l4_stop(struct timer_lowerhalf_s *lower); -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -129,16 +129,16 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l4_start, - .stop = stm32l4_stop, - .getstatus = stm32l4_getstatus, - .settimeout = stm32l4_settimeout, - .setcallback = stm32l4_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32L4_TIM1 -static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -146,7 +146,7 @@ static struct stm32l4_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM2 -static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -154,7 +154,7 @@ static struct stm32l4_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM3 -static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -162,7 +162,7 @@ static struct stm32l4_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM4 -static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -170,7 +170,7 @@ static struct stm32l4_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM5 -static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -178,7 +178,7 @@ static struct stm32l4_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM6 -static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -186,7 +186,7 @@ static struct stm32l4_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM7 -static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -194,7 +194,7 @@ static struct stm32l4_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM8 -static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -202,7 +202,7 @@ static struct stm32l4_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM15 -static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -210,7 +210,7 @@ static struct stm32l4_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM16 -static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -218,7 +218,7 @@ static struct stm32l4_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32L4_TIM17 -static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -230,7 +230,7 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -241,10 +241,10 @@ static struct stm32l4_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l4_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l4_lowerhalf_s *lower = - (struct stm32l4_lowerhalf_s *) arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *) arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -258,14 +258,14 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) } else { - stm32l4_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l4_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -279,10 +279,10 @@ static int stm32l4_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l4_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -290,7 +290,7 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -304,7 +304,7 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -318,10 +318,10 @@ static int stm32l4_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -338,7 +338,7 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l4_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -353,11 +353,11 @@ static int stm32l4_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -405,7 +405,7 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -420,11 +420,11 @@ static int stm32l4_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -449,7 +449,7 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l4_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -468,11 +468,11 @@ static int stm32l4_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l4_lowerhalf_s *priv = - (struct stm32l4_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -482,7 +482,7 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32l4_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -499,7 +499,7 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -516,9 +516,9 @@ static void stm32l4_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l4_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l4_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -595,7 +595,7 @@ int stm32l4_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l4_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l4/stm32l4_timerisr.c b/arch/arm/src/stm32l4/stm32l4_timerisr.c index d943d75bb3d..6f0b332f960 100644 --- a/arch/arm/src/stm32l4/stm32l4_timerisr.c +++ b/arch/arm/src/stm32l4/stm32l4_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l4_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -84,7 +84,7 @@ * ****************************************************************************/ -static int stm32l4_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -134,7 +134,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l4_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 4aa94686346..8af667ad4a0 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -282,7 +282,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -295,7 +295,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32l4_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4_uid.c b/arch/arm/src/stm32l4/stm32l4_uid.c index eb955770cb6..df2b64233e4 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.c +++ b/arch/arm/src/stm32l4/stm32l4_uid.c @@ -50,7 +50,7 @@ * Public Functions ****************************************************************************/ -void stm32l4_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32l4/stm32l4_uid.h b/arch/arm/src/stm32l4/stm32l4_uid.h index a9b1cf4027f..239c83ed96f 100644 --- a/arch/arm/src/stm32l4/stm32l4_uid.h +++ b/arch/arm/src/stm32l4/stm32l4_uid.h @@ -48,6 +48,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l4_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_UID_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index 2df8f8bd83f..017b8f18a20 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -45,7 +45,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_gpio.h" #include "stm32l4_usbdev.h" @@ -150,8 +150,8 @@ /* Request queue operations *************************************************/ -#define stm32l4_rqempty(ep) ((ep)->head == NULL) -#define stm32l4_rqpeek(ep) ((ep)->head) +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) /* USB trace ****************************************************************/ @@ -236,7 +236,7 @@ /* The various states of a control pipe */ -enum stm32l4_ep0state_e +enum stm32_ep0state_e { EP0STATE_IDLE = 0, /* No request in progress */ EP0STATE_SETUP_OUT, /* Set up received with data for device OUT in progress */ @@ -249,7 +249,7 @@ enum stm32l4_ep0state_e /* Resume states */ -enum stm32l4_rsmstate_e +enum stm32_rsmstate_e { RSMSTATE_IDLE = 0, /* Device is either fully suspended or running */ RSMSTATE_STARTED, /* Resume sequence has been started */ @@ -264,28 +264,28 @@ union wb_u /* A container for a request so that the request make be retained in a list */ -struct stm32l4_req_s +struct stm32_req_s { struct usbdev_req_s req; /* Standard USB request */ - struct stm32l4_req_s *flink; /* Supports a singly linked list */ + struct stm32_req_s *flink; /* Supports a singly linked list */ }; /* This is the internal representation of an endpoint */ -struct stm32l4_ep_s +struct stm32_ep_s { /* Common endpoint fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_ep_s - * to struct stm32l4_ep_s. + * to struct stm32_ep_s. */ struct usbdev_ep_s ep; /* Standard endpoint structure */ /* STM32-specific fields */ - struct stm32l4_usbdev_s *dev; /* Reference to private driver data */ - struct stm32l4_req_s *head; /* Request list for this endpoint */ - struct stm32l4_req_s *tail; + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; uint8_t bufno; /* Allocated buffer number */ uint8_t stalled:1; /* true: Endpoint is stalled */ uint8_t halted:1; /* true: Endpoint feature halted */ @@ -293,7 +293,7 @@ struct stm32l4_ep_s uint8_t txnullpkt:1; /* Null packet needed at end of transfer */ }; -struct stm32l4_usbdev_s +struct stm32_usbdev_s { /* Common device fields. This must be the first thing defined in the * structure so that it is possible to simply cast from struct usbdev_s @@ -308,8 +308,8 @@ struct stm32l4_usbdev_s /* STM32-specific fields */ - uint8_t ep0state; /* State of EP0 (see enum stm32l4_ep0state_e) */ - uint8_t rsmstate; /* Resume state (see enum stm32l4_rsmstate_e) */ + uint8_t ep0state; /* State of EP0 (see enum stm32_ep0state_e) */ + uint8_t rsmstate; /* Resume state (see enum stm32_rsmstate_e) */ uint8_t nesofs; /* ESOF counter (for resume support) */ uint8_t rxpending:1; /* 1: OUT data in PMA, but no read requests */ uint8_t selfpowered:1; /* 1: Device is self powered */ @@ -328,7 +328,7 @@ struct stm32l4_usbdev_s * ep0data * For OUT SETUP requests, the SETUP data phase must also complete before * the SETUP command can be processed. The ep0 packet receipt logic - * stm32l4_ep0_rdrequest will save the accompanying EP0 OUT data in + * stm32_ep0_rdrequest will save the accompanying EP0 OUT data in * ep0data[] before the SETUP command is re-processed. * * ep0datlen @@ -342,7 +342,7 @@ struct stm32l4_usbdev_s /* The endpoint list */ - struct stm32l4_ep_s eplist[STM32_NENDPOINTS]; + struct stm32_ep_s eplist[STM32_NENDPOINTS]; }; /**************************************************************************** @@ -352,156 +352,156 @@ struct stm32l4_usbdev_s /* Register operations ******************************************************/ #ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr); -static void stm32l4_putreg(uint16_t val, uint32_t addr); -static void stm32l4_checksetup(void); -static void stm32l4_dumpep(int epno); +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +static void stm32_checksetup(void); +static void stm32_dumpep(int epno); #else -# define stm32l4_getreg(addr) getreg16(addr) -# define stm32l4_putreg(val,addr) putreg16(val,addr) -# define stm32l4_checksetup() -# define stm32l4_dumpep(epno) +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +# define stm32_checksetup() +# define stm32_dumpep(epno) #endif /* Low-Level Helpers ********************************************************/ static inline void - stm32l4_seteptxcount(uint8_t epno, uint16_t count); + stm32_seteptxcount(uint8_t epno, uint16_t count); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteptxaddr(uint8_t epno); -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count); + stm32_geteptxaddr(uint8_t epno); +static void stm32_seteprxcount(uint8_t epno, uint16_t count); static inline uint16_t - stm32l4_geteprxcount(uint8_t epno); + stm32_geteprxcount(uint8_t epno); static inline void - stm32l4_seteprxaddr(uint8_t epno, uint16_t addr); + stm32_seteprxaddr(uint8_t epno, uint16_t addr); static inline uint16_t - stm32l4_geteprxaddr(uint8_t epno); + stm32_geteprxaddr(uint8_t epno); static inline void - stm32l4_setepaddress(uint8_t epno, uint16_t addr); + stm32_setepaddress(uint8_t epno, uint16_t addr); static inline void - stm32l4_seteptype(uint8_t epno, uint16_t type); + stm32_seteptype(uint8_t epno, uint16_t type); static inline void - stm32l4_seteptxaddr(uint8_t epno, uint16_t addr); + stm32_seteptxaddr(uint8_t epno, uint16_t addr); static inline void - stm32l4_setstatusout(uint8_t epno); + stm32_setstatusout(uint8_t epno); static inline void - stm32l4_clrstatusout(uint8_t epno); -static void stm32l4_clrrxdtog(uint8_t epno); -static void stm32l4_clrtxdtog(uint8_t epno); -static void stm32l4_clrepctrrx(uint8_t epno); -static void stm32l4_clrepctrtx(uint8_t epno); -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state); -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state); + stm32_clrstatusout(uint8_t epno); +static void stm32_clrrxdtog(uint8_t epno); +static void stm32_clrtxdtog(uint8_t epno); +static void stm32_clrepctrrx(uint8_t epno); +static void stm32_clrepctrtx(uint8_t epno); +static void stm32_seteptxstatus(uint8_t epno, uint16_t state); +static void stm32_seteprxstatus(uint8_t epno, uint16_t state); static inline uint16_t - stm32l4_geteptxstatus(uint8_t epno); + stm32_geteptxstatus(uint8_t epno); static inline uint16_t - stm32l4_geteprxstatus(uint8_t epno); -static bool stm32l4_eptxstalled(uint8_t epno); -static bool stm32l4_eprxstalled(uint8_t epno); -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, + stm32_geteprxstatus(uint8_t epno); +static bool stm32_eptxstalled(uint8_t epno); +static bool stm32_eprxstalled(uint8_t epno); +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits); /* Suspend/Resume Helpers ***************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv); -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv); -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ; +static void stm32_suspend(struct stm32_usbdev_s *priv); +static void stm32_initresume(struct stm32_usbdev_s *priv); +static void stm32_esofpoll(struct stm32_usbdev_s *priv) ; /* Request Helpers **********************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes); static inline void - stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, + stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes); -static struct stm32l4_req_s * - stm32l4_rqdequeue(struct stm32l4_ep_s *privep); -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req); +static struct stm32_req_s * + stm32_rqdequeue(struct stm32_ep_s *privep); +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req); static inline void - stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, + stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result); -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result); -static void stm32l4_epwrite(struct stm32l4_usbdev_s *buf, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *buf, + struct stm32_ep_s *privep, const uint8_t *data, uint32_t nbytes); -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); inline static int - stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline int - stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv); -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep); + stm32_ep0_rdrequest(struct stm32_usbdev_s *priv); +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); +static void stm32_cancelrequests(struct stm32_ep_s *privep); /* Interrupt level processing ***********************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv); -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno); -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv); +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno); +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value); -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv); -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv); +static void stm32_ep0setup(struct stm32_usbdev_s *priv); +static void stm32_ep0out(struct stm32_usbdev_s *priv); +static void stm32_ep0in(struct stm32_usbdev_s *priv); static inline void - stm32l4_ep0done(struct stm32l4_usbdev_s *priv, uint16_t istr); -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv); -static int stm32l4_usbinterrupt(int irq, void *context, void *arg); + stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr); +static void stm32_lptransfer(struct stm32_usbdev_s *priv); +static int stm32_usbinterrupt(int irq, void *context, void *arg); /* Endpoint helpers *********************************************************/ -static inline struct stm32l4_ep_s * - stm32l4_epreserve(struct stm32l4_usbdev_s *priv, +static inline struct stm32_ep_s * + stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset); static inline void - stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); static inline bool - stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno); -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv); + stm32_epreserved(struct stm32_usbdev_s *priv, int epno); +static int stm32_epallocpma(struct stm32_usbdev_s *priv); static inline void - stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep); + stm32_epfreepma(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep); /* Endpoint operations ******************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last); -static int stm32l4_epdisable(struct usbdev_ep_s *ep); +static int stm32_epdisable(struct usbdev_ep_s *ep); static struct usbdev_req_s * - stm32l4_epallocreq(struct usbdev_ep_s *ep); -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, + stm32_epallocreq(struct usbdev_ep_s *ep); +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *); -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epcancel(struct usbdev_ep_s *ep, +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req); -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume); +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume); /* USB device controller operations *****************************************/ static struct usbdev_ep_s * - stm32l4_allocep(struct usbdev_s *dev, uint8_t epno, bool in, + stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype); -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); -static int stm32l4_getframe(struct usbdev_s *dev); -static int stm32l4_wakeup(struct usbdev_s *dev); -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered); -static int stm32l4_pullup(struct usbdev_s *dev, bool enable); +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep); +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); /* Initialization/Reset *****************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv); -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); +static void stm32_reset(struct stm32_usbdev_s *priv); +static void stm32_hwreset(struct stm32_usbdev_s *priv); +static void stm32_hwsetup(struct stm32_usbdev_s *priv); +static void stm32_hwshutdown(struct stm32_usbdev_s *priv); /**************************************************************************** * Private Data @@ -511,27 +511,27 @@ static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv); * be simply retained in a single global instance. */ -static struct stm32l4_usbdev_s g_usbdev; +static struct stm32_usbdev_s g_usbdev; static const struct usbdev_epops_s g_epops = { - .configure = stm32l4_epconfigure, - .disable = stm32l4_epdisable, - .allocreq = stm32l4_epallocreq, - .freereq = stm32l4_epfreereq, - .submit = stm32l4_epsubmit, - .cancel = stm32l4_epcancel, - .stall = stm32l4_epstall, + .configure = stm32_epconfigure, + .disable = stm32_epdisable, + .allocreq = stm32_epallocreq, + .freereq = stm32_epfreereq, + .submit = stm32_epsubmit, + .cancel = stm32_epcancel, + .stall = stm32_epstall, }; static const struct usbdev_ops_s g_devops = { - .allocep = stm32l4_allocep, - .freeep = stm32l4_freeep, - .getframe = stm32l4_getframe, - .wakeup = stm32l4_wakeup, - .selfpowered = stm32l4_selfpowered, - .pullup = stm32l4_pullup, + .allocep = stm32_allocep, + .freeep = stm32_freeep, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, }; /**************************************************************************** @@ -615,11 +615,11 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_getreg + * Name: stm32_getreg ****************************************************************************/ #ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static uint16_t stm32l4_getreg(uint32_t addr) +static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; static uint16_t preval = 0; @@ -674,11 +674,11 @@ static uint16_t stm32l4_getreg(uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_putreg + * Name: stm32_putreg ****************************************************************************/ #ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_putreg(uint16_t val, uint32_t addr) +static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -691,11 +691,11 @@ static void stm32l4_putreg(uint16_t val, uint32_t addr) #endif /**************************************************************************** - * Name: stm32l4_dumpep + * Name: stm32_dumpep ****************************************************************************/ #ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_dumpep(int epno) +static void stm32_dumpep(int epno) { uint32_t addr; @@ -734,11 +734,11 @@ static void stm32l4_dumpep(int epno) #endif /**************************************************************************** - * Name: stm32l4_checksetup + * Name: stm32_checksetup ****************************************************************************/ #ifdef CONFIG_STM32L4_USBDEV_REGDEBUG -static void stm32l4_checksetup(void) +static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); uint32_t apb1rstr = getreg32(STM32_RCC_APB1RSTR1); @@ -757,40 +757,40 @@ static void stm32l4_checksetup(void) #endif /**************************************************************************** - * Name: stm32l4_seteptxcount + * Name: stm32_seteptxcount ****************************************************************************/ -static inline void stm32l4_seteptxcount(uint8_t epno, uint16_t count) +static inline void stm32_seteptxcount(uint8_t epno, uint16_t count) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_TX(epno); *epaddr = count; } /**************************************************************************** - * Name: stm32l4_seteptxaddr + * Name: stm32_seteptxaddr ****************************************************************************/ -static inline void stm32l4_seteptxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteptxaddr(uint8_t epno, uint16_t addr) { volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); *txaddr = addr; } /**************************************************************************** - * Name: stm32l4_geteptxaddr + * Name: stm32_geteptxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteptxaddr(uint8_t epno) +static inline uint16_t stm32_geteptxaddr(uint8_t epno) { volatile uint16_t *txaddr = (uint16_t *)STM32_USB_ADDR_TX(epno); return (uint16_t)*txaddr; } /**************************************************************************** - * Name: stm32l4_seteprxcount + * Name: stm32_seteprxcount ****************************************************************************/ -static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) +static void stm32_seteprxcount(uint8_t epno, uint16_t count) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); uint32_t rxcount = 0; @@ -836,72 +836,72 @@ static void stm32l4_seteprxcount(uint8_t epno, uint16_t count) } /**************************************************************************** - * Name: stm32l4_geteprxcount + * Name: stm32_geteprxcount ****************************************************************************/ -static inline uint16_t stm32l4_geteprxcount(uint8_t epno) +static inline uint16_t stm32_geteprxcount(uint8_t epno) { volatile uint16_t *epaddr = (uint16_t *)STM32_USB_COUNT_RX(epno); return (*epaddr) & USB_COUNT_RX_MASK; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline void stm32l4_seteprxaddr(uint8_t epno, uint16_t addr) +static inline void stm32_seteprxaddr(uint8_t epno, uint16_t addr) { volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); *rxaddr = addr; } /**************************************************************************** - * Name: stm32l4_seteprxaddr + * Name: stm32_seteprxaddr ****************************************************************************/ -static inline uint16_t stm32l4_geteprxaddr(uint8_t epno) +static inline uint16_t stm32_geteprxaddr(uint8_t epno) { volatile uint16_t *rxaddr = (uint16_t *)STM32_USB_ADDR_RX(epno); return (uint16_t)*rxaddr; } /**************************************************************************** - * Name: stm32l4_setepaddress + * Name: stm32_setepaddress ****************************************************************************/ -static inline void stm32l4_setepaddress(uint8_t epno, uint16_t addr) +static inline void stm32_setepaddress(uint8_t epno, uint16_t addr) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EA_MASK; regval |= (addr << USB_EPR_EA_SHIFT); - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteptype + * Name: stm32_seteptype ****************************************************************************/ -static inline void stm32l4_seteptype(uint8_t epno, uint16_t type) +static inline void stm32_seteptype(uint8_t epno, uint16_t type) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EPTYPE_MASK; regval |= type; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_setstatusout + * Name: stm32_setstatusout ****************************************************************************/ -static inline void stm32l4_setstatusout(uint8_t epno) +static inline void stm32_setstatusout(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -911,17 +911,17 @@ static inline void stm32l4_setstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval |= USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrstatusout + * Name: stm32_clrstatusout ****************************************************************************/ -static inline void stm32l4_clrstatusout(uint8_t epno) +static inline void stm32_clrstatusout(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -931,102 +931,102 @@ static inline void stm32l4_clrstatusout(uint8_t epno) * transaction is expected. The bit is not used with out endpoint types. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_EP_KIND; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrrxdtog + * Name: stm32_clrrxdtog ****************************************************************************/ -static void stm32l4_clrrxdtog(uint8_t epno) +static void stm32_clrrxdtog(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_RX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrtxdtog + * Name: stm32_clrtxdtog ****************************************************************************/ -static void stm32l4_clrtxdtog(uint8_t epno) +static void stm32_clrtxdtog(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); if ((regval & USB_EPR_DTOG_TX) != 0) { regval &= EPR_NOTOG_MASK; regval |= USB_EPR_DTOG_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } } /**************************************************************************** - * Name: stm32l4_clrepctrrx + * Name: stm32_clrepctrrx ****************************************************************************/ -static void stm32l4_clrepctrrx(uint8_t epno) +static void stm32_clrepctrrx(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_RX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_clrepctrtx + * Name: stm32_clrepctrtx ****************************************************************************/ -static void stm32l4_clrepctrtx(uint8_t epno) +static void stm32_clrepctrtx(uint8_t epno) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); regval &= EPR_NOTOG_MASK; regval &= ~USB_EPR_CTR_TX; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_geteptxstatus + * Name: stm32_geteptxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteptxstatus(uint8_t epno) +static inline uint16_t stm32_geteptxstatus(uint8_t epno) { - return (uint16_t)(stm32l4_getreg(STM32_USB_EPR(epno)) & + return (uint16_t)(stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATTX_MASK); } /**************************************************************************** - * Name: stm32l4_geteprxstatus + * Name: stm32_geteprxstatus ****************************************************************************/ -static inline uint16_t stm32l4_geteprxstatus(uint8_t epno) +static inline uint16_t stm32_geteprxstatus(uint8_t epno) { - return (stm32l4_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); + return (stm32_getreg(STM32_USB_EPR(epno)) & USB_EPR_STATRX_MASK); } /**************************************************************************** - * Name: stm32l4_seteptxstatus + * Name: stm32_seteptxstatus ****************************************************************************/ -static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) +static void stm32_seteptxstatus(uint8_t epno, uint16_t state) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -1036,7 +1036,7 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_TX bits to 1 if there value is different * from the bits requested in 'state' @@ -1044,14 +1044,14 @@ static void stm32l4_seteptxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_TXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_seteprxstatus + * Name: stm32_seteprxstatus ****************************************************************************/ -static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) +static void stm32_seteprxstatus(uint8_t epno, uint16_t state) { uint32_t epaddr = STM32_USB_EPR(epno); uint16_t regval; @@ -1061,7 +1061,7 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) * value toggles. */ - regval = stm32l4_getreg(epaddr); + regval = stm32_getreg(epaddr); /* The exclusive OR will set STAT_RX bits to 1 if there value is different * from the bits requested in 'state' @@ -1069,32 +1069,32 @@ static void stm32l4_seteprxstatus(uint8_t epno, uint16_t state) regval ^= state; regval &= EPR_RXDTOG_MASK; - stm32l4_putreg(regval, epaddr); + stm32_putreg(regval, epaddr); } /**************************************************************************** - * Name: stm32l4_eptxstalled + * Name: stm32_eptxstalled ****************************************************************************/ -static inline bool stm32l4_eptxstalled(uint8_t epno) +static inline bool stm32_eptxstalled(uint8_t epno) { - return (stm32l4_geteptxstatus(epno) == USB_EPR_STATTX_STALL); + return (stm32_geteptxstatus(epno) == USB_EPR_STATTX_STALL); } /**************************************************************************** - * Name: stm32l4_eprxstalled + * Name: stm32_eprxstalled ****************************************************************************/ -static inline bool stm32l4_eprxstalled(uint8_t epno) +static inline bool stm32_eprxstalled(uint8_t epno) { - return (stm32l4_geteprxstatus(epno) == USB_EPR_STATRX_STALL); + return (stm32_geteprxstatus(epno) == USB_EPR_STATRX_STALL); } /**************************************************************************** - * Name: stm32l4_copytopma + * Name: stm32_copytopma ****************************************************************************/ -static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, +static void stm32_copytopma(const uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *dest; @@ -1123,11 +1123,11 @@ static void stm32l4_copytopma(const uint8_t *buffer, uint16_t pma, } /**************************************************************************** - * Name: stm32l4_copyfrompma + * Name: stm32_copyfrompma ****************************************************************************/ static inline void -stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) +stm32_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) { volatile uint16_t *src; int nwords = (nbytes + 1) >> 1; @@ -1151,12 +1151,12 @@ stm32l4_copyfrompma(uint8_t *buffer, uint16_t pma, uint16_t nbytes) } /**************************************************************************** - * Name: stm32l4_rqdequeue + * Name: stm32_rqdequeue ****************************************************************************/ -static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) +static struct stm32_req_s *stm32_rqdequeue(struct stm32_ep_s *privep) { - struct stm32l4_req_s *ret = privep->head; + struct stm32_req_s *ret = privep->head; if (ret) { @@ -1173,11 +1173,11 @@ static struct stm32l4_req_s *stm32l4_rqdequeue(struct stm32l4_ep_s *privep) } /**************************************************************************** - * Name: stm32l4_rqenqueue + * Name: stm32_rqenqueue ****************************************************************************/ -static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *req) +static void stm32_rqenqueue(struct stm32_ep_s *privep, + struct stm32_req_s *req) { req->flink = NULL; if (!privep->head) @@ -1193,12 +1193,12 @@ static void stm32l4_rqenqueue(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_abortrequest + * Name: stm32_abortrequest ****************************************************************************/ static inline void -stm32l4_abortrequest(struct stm32l4_ep_s *privep, - struct stm32l4_req_s *privreq, int16_t result) +stm32_abortrequest(struct stm32_ep_s *privep, + struct stm32_req_s *privreq, int16_t result) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_REQABORTED), (uint16_t)USB_EPNO(privep->ep.eplog)); @@ -1213,18 +1213,18 @@ stm32l4_abortrequest(struct stm32l4_ep_s *privep, } /**************************************************************************** - * Name: stm32l4_reqcomplete + * Name: stm32_reqcomplete ****************************************************************************/ -static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) +static void stm32_reqcomplete(struct stm32_ep_s *privep, int16_t result) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ flags = enter_critical_section(); - privreq = stm32l4_rqdequeue(privep); + privreq = stm32_rqdequeue(privep); leave_critical_section(flags); if (privreq) @@ -1258,8 +1258,8 @@ static void stm32l4_reqcomplete(struct stm32l4_ep_s *privep, int16_t result) * Name: tm32_epwrite ****************************************************************************/ -static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep, +static void stm32_epwrite(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep, const uint8_t *buf, uint32_t nbytes) { uint8_t epno = USB_EPNO(privep->ep.eplog); @@ -1273,12 +1273,12 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, * endpoint */ - stm32l4_copytopma(buf, stm32l4_geteptxaddr(epno), nbytes); + stm32_copytopma(buf, stm32_geteptxaddr(epno), nbytes); } /* Send the packet (might be a null packet nbytes == 0) */ - stm32l4_seteptxcount(epno, nbytes); + stm32_seteptxcount(epno, nbytes); priv->txstatus = USB_EPR_STATTX_VALID; /* Indicate that there is data in the TX packet memory. This will be @@ -1289,30 +1289,30 @@ static void stm32l4_epwrite(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_wrrequest_ep0 + * Name: stm32_wrrequest_ep0 * * Description: * Handle the ep0 state on writes. * ****************************************************************************/ -inline static int stm32l4_wrrequest_ep0(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +inline static int stm32_wrrequest_ep0(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { int ret; - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_WRREQUEST : EP0STATE_IDLE); return ret; } /**************************************************************************** - * Name: stm32l4_wrrequest + * Name: stm32_wrrequest ****************************************************************************/ -static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_wrrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint8_t *buf; uint8_t epno; int nbytes; @@ -1326,7 +1326,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* There is no TX transfer in progress and no new pending TX @@ -1388,7 +1388,7 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, /* Send the packet (might be a null packet nbytes == 0) */ buf = privreq->req.buf + privreq->req.xfrd; - stm32l4_epwrite(priv, privep, buf, nbytes); + stm32_epwrite(priv, privep, buf, nbytes); /* Update for the next data IN interrupt */ @@ -1406,24 +1406,24 @@ static int stm32l4_wrrequest(struct stm32l4_usbdev_s *priv, usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), privreq->req.xfrd); privep->txnullpkt = 0; - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_ep0_rdrequest + * Name: stm32_ep0_rdrequest * * Description: - * This function is called from the stm32l4_ep0out handler when the + * This function is called from the stm32_ep0out handler when the * ep0state is EP0STATE_SETUP_OUT and upon new incoming data is available * in the endpoint 0's buffer. This function will simply copy the OUT data * into ep0data. * ****************************************************************************/ -static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) +static inline int stm32_ep0_rdrequest(struct stm32_usbdev_s *priv) { uint32_t src; int pmalen; @@ -1431,7 +1431,7 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(EP0); + pmalen = stm32_geteprxcount(EP0); uinfo("EP0: pmalen=%d\n", pmalen); usbtrace(TRACE_READ(EP0), pmalen); @@ -1439,11 +1439,11 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) /* Read the data into our special buffer for SETUP data */ readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, pmalen); - src = stm32l4_geteprxaddr(EP0); + src = stm32_geteprxaddr(EP0); /* Receive the next packet */ - stm32l4_copyfrompma(&priv->ep0data[0], src, readlen); + stm32_copyfrompma(&priv->ep0data[0], src, readlen); /* Now we can process the setup command */ @@ -1451,20 +1451,20 @@ static inline int stm32l4_ep0_rdrequest(struct stm32l4_usbdev_s *priv) priv->ep0datlen = readlen; usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPOUTDATA), readlen); - stm32l4_ep0setup(priv); + stm32_ep0setup(priv); priv->ep0datlen = 0; /* mark the date consumed */ return OK; } /**************************************************************************** - * Name: stm32l4_rdrequest + * Name: stm32_rdrequest ****************************************************************************/ -static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +static int stm32_rdrequest(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; uint32_t src; uint8_t *dest; uint8_t epno; @@ -1474,7 +1474,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Check the request from the head of the endpoint request queue */ epno = USB_EPNO(privep->ep.eplog); - privreq = stm32l4_rqpeek(privep); + privreq = stm32_rqpeek(privep); if (!privreq) { /* Incoming data available in PMA, but no packet to receive the data. @@ -1494,7 +1494,7 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, if (privreq->req.len == 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); return OK; } @@ -1503,16 +1503,16 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Get the source and destination transfer addresses */ dest = privreq->req.buf + privreq->req.xfrd; - src = stm32l4_geteprxaddr(epno); + src = stm32_geteprxaddr(epno); /* Get the number of bytes to read from packet memory */ - pmalen = stm32l4_geteprxcount(epno); + pmalen = stm32_geteprxcount(epno); readlen = MIN(privreq->req.len, pmalen); /* Receive the next packet */ - stm32l4_copyfrompma(dest, src, readlen); + stm32_copyfrompma(dest, src, readlen); /* If the receive buffer is full or this is a partial packet, * then we are finished with the request buffer). @@ -1524,23 +1524,23 @@ static int stm32l4_rdrequest(struct stm32l4_usbdev_s *priv, /* Return the read request to the class driver. */ usbtrace(TRACE_COMPLETE(epno), privreq->req.xfrd); - stm32l4_reqcomplete(privep, OK); + stm32_reqcomplete(privep, OK); } return OK; } /**************************************************************************** - * Name: stm32l4_cancelrequests + * Name: stm32_cancelrequests ****************************************************************************/ -static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) +static void stm32_cancelrequests(struct stm32_ep_s *privep) { - while (!stm32l4_rqempty(privep)) + while (!stm32_rqempty(privep)) { usbtrace(TRACE_COMPLETE(USB_EPNO(privep->ep.eplog)), - (stm32l4_rqpeek(privep))->req.xfrd); - stm32l4_reqcomplete(privep, -ESHUTDOWN); + (stm32_rqpeek(privep))->req.xfrd); + stm32_reqcomplete(privep, -ESHUTDOWN); } } @@ -1549,10 +1549,10 @@ static void stm32l4_cancelrequests(struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dispatchrequest + * Name: stm32_dispatchrequest ****************************************************************************/ -static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) +static void stm32_dispatchrequest(struct stm32_usbdev_s *priv) { int ret; @@ -1574,17 +1574,17 @@ static void stm32l4_dispatchrequest(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epdone + * Name: stm32_epdone ****************************************************************************/ -static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) +static void stm32_epdone(struct stm32_usbdev_s *priv, uint8_t epno) { - struct stm32l4_ep_s *privep; + struct stm32_ep_s *privep; uint16_t epr; /* Decode and service non control endpoints interrupt */ - epr = stm32l4_getreg(STM32_USB_EPR(epno)); + epr = stm32_getreg(STM32_USB_EPR(epno)); privep = &priv->eplist[epno]; /* OUT: host-to-device @@ -1600,11 +1600,11 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) * accept the host data. */ - if (!stm32l4_rqempty(privep)) + if (!stm32_rqempty(privep)) { /* Read host data into the current read request */ - stm32l4_rdrequest(priv, privep); + stm32_rdrequest(priv, privep); /* "After the received data is processed, the application software * should set the STAT_RX bits to '11' (Valid) in the USB_EPnR, @@ -1616,7 +1616,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* NAK further OUT packets if there there no more read requests */ - if (stm32l4_rqempty(privep)) + if (stm32_rqempty(privep)) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUTPENDING), (uint16_t)epno); @@ -1634,8 +1634,8 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) /* Clear the interrupt status and set the new RX status */ - stm32l4_clrepctrrx(epno); - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_clrepctrrx(epno); + stm32_seteprxstatus(epno, priv->rxstatus); } /* IN: device-to-host @@ -1647,7 +1647,7 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) { /* Clear interrupt status */ - stm32l4_clrepctrtx(epno); + stm32_clrepctrtx(epno); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPINDONE), epr); /* Handle write requests */ @@ -1655,24 +1655,24 @@ static void stm32l4_epdone(struct stm32l4_usbdev_s *priv, uint8_t epno) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } /**************************************************************************** - * Name: stm32l4_setdevaddr + * Name: stm32_setdevaddr ****************************************************************************/ -static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) +static void stm32_setdevaddr(struct stm32_usbdev_s *priv, uint8_t value) { int epno; @@ -1680,26 +1680,26 @@ static void stm32l4_setdevaddr(struct stm32l4_usbdev_s *priv, uint8_t value) for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - if (stm32l4_epreserved(priv, epno)) + if (stm32_epreserved(priv, epno)) { - stm32l4_setepaddress((uint8_t)epno, (uint8_t)epno); + stm32_setepaddress((uint8_t)epno, (uint8_t)epno); } } /* Set the device address and enable function */ - stm32l4_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); + stm32_putreg(value | USB_DADDR_EF, STM32_USB_DADDR); } /**************************************************************************** - * Name: stm32l4_ep0setup + * Name: stm32_ep0setup ****************************************************************************/ -static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) +static void stm32_ep0setup(struct stm32_usbdev_s *priv) { - struct stm32l4_ep_s *ep0 = &priv->eplist[EP0]; - struct stm32l4_req_s *privreq = stm32l4_rqpeek(ep0); - struct stm32l4_ep_s *privep; + struct stm32_ep_s *ep0 = &priv->eplist[EP0]; + struct stm32_req_s *privreq = stm32_rqpeek(ep0); + struct stm32_ep_s *privep; union wb_u value; union wb_u index; union wb_u len; @@ -1712,7 +1712,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * was a zero-length transfer!) */ - while (!stm32l4_rqempty(ep0)) + while (!stm32_rqempty(ep0)) { int16_t result = OK; if (privreq->req.xfrd != privreq->req.len) @@ -1721,7 +1721,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) } usbtrace(TRACE_COMPLETE(ep0->ep.eplog), privreq->req.xfrd); - stm32l4_reqcomplete(ep0, result); + stm32_reqcomplete(ep0, result); } /* Assume NOT stalled; no TX in progress */ @@ -1739,7 +1739,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * request */ - stm32l4_copyfrompma((uint8_t *)&priv->ctrl, stm32l4_geteprxaddr(EP0), + stm32_copyfrompma((uint8_t *)&priv->ctrl, stm32_geteprxaddr(EP0), USB_SIZEOF_CTRLREQ); /* And extract the little-endian 16-bit values to host order */ @@ -1777,7 +1777,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Let the class implementation handle all non-standar requests */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); return; } @@ -1828,7 +1828,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { /* IN Endpoint stalled */ @@ -1839,7 +1839,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { /* OUT Endpoint stalled */ @@ -1913,7 +1913,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * the endpoint recipient) */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1926,7 +1926,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 0; - stm32l4_epstall(&privep->ep, true); + stm32_epstall(&privep->ep, true); } else { @@ -1962,7 +1962,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * endpoint */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -1975,7 +1975,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) { privep = &priv->eplist[epno]; privep->halted = 1; - stm32l4_epstall(&privep->ep, false); + stm32_epstall(&privep->ep, false); } else { @@ -2033,7 +2033,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2056,7 +2056,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -2084,7 +2084,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) * let the class implementation handle it */ - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } else @@ -2114,7 +2114,7 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), priv->ctrl.type); - stm32l4_dispatchrequest(priv); + stm32_dispatchrequest(priv); handled = true; } break; @@ -2171,16 +2171,16 @@ static void stm32l4_ep0setup(struct stm32l4_usbdev_s *priv) /* Send the response (might be a zero-length packet) */ - stm32l4_epwrite(priv, ep0, response.b, nbytes); + stm32_epwrite(priv, ep0, response.b, nbytes); priv->ep0state = EP0STATE_IDLE; } } /**************************************************************************** - * Name: stm32l4_ep0in + * Name: stm32_ep0in ****************************************************************************/ -static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) +static void stm32_ep0in(struct stm32_usbdev_s *priv) { /* There is no longer anything in the EP0 TX packet memory */ @@ -2192,7 +2192,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) if (priv->ep0state == EP0STATE_WRREQUEST) { - stm32l4_wrrequest_ep0(priv, &priv->eplist[EP0]); + stm32_wrrequest_ep0(priv, &priv->eplist[EP0]); } /* No.. Are we processing the completion of a status response? */ @@ -2209,7 +2209,7 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) { union wb_u value; value.w = GETUINT16(priv->ctrl.value); - stm32l4_setdevaddr(priv, value.b[LSB]); + stm32_setdevaddr(priv, value.b[LSB]); } } else @@ -2219,24 +2219,24 @@ static void stm32l4_ep0in(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0out + * Name: stm32_ep0out ****************************************************************************/ -static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) +static void stm32_ep0out(struct stm32_usbdev_s *priv) { int ret; - struct stm32l4_ep_s *privep = &priv->eplist[EP0]; + struct stm32_ep_s *privep = &priv->eplist[EP0]; switch (priv->ep0state) { case EP0STATE_RDREQUEST: /* Read request in progress */ case EP0STATE_IDLE: /* No transfer in progress */ - ret = stm32l4_rdrequest(priv, privep); + ret = stm32_rdrequest(priv, privep); priv->ep0state = ((ret == OK) ? EP0STATE_RDREQUEST : EP0STATE_IDLE); break; case EP0STATE_SETUP_OUT: /* SETUP was waiting for data */ - ret = stm32l4_ep0_rdrequest(priv); /* Off load the data and run the + ret = stm32_ep0_rdrequest(priv); /* Off load the data and run the * last set up command with the * OUT data */ @@ -2259,10 +2259,10 @@ static void stm32l4_ep0out(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_ep0done + * Name: stm32_ep0done ****************************************************************************/ -static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, +static inline void stm32_ep0done(struct stm32_usbdev_s *priv, uint16_t istr) { uint16_t epr; @@ -2277,8 +2277,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Set both RX and TX status to NAK */ - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_NAK); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_NAK); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); /* Check the direction bit to determine if this the completion of an EP0 * packet sent to or received from the host PC. @@ -2289,14 +2289,14 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* EP0 IN: device-to-host (DIR=0) */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0IN), istr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } else { /* EP0 OUT: host-to-device (DIR=1) */ - epr = stm32l4_getreg(STM32_USB_EPR(EP0)); + epr = stm32_getreg(STM32_USB_EPR(EP0)); /* CTR_TX is set when an IN transaction successfully * completes on an endpoint @@ -2305,8 +2305,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, if ((epr & USB_EPR_CTR_TX) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0INDONE), epr); - stm32l4_clrepctrtx(EP0); - stm32l4_ep0in(priv); + stm32_clrepctrtx(EP0); + stm32_ep0in(priv); } /* SETUP is set by the hardware when the last completed @@ -2316,8 +2316,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_SETUP) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0SETUPDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0setup(priv); + stm32_clrepctrrx(EP0); + stm32_ep0setup(priv); } /* Set by the hardware when an OUT/SETUP transaction successfully @@ -2327,8 +2327,8 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, else if ((epr & USB_EPR_CTR_RX) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EP0OUTDONE), epr); - stm32l4_clrepctrrx(EP0); - stm32l4_ep0out(priv); + stm32_clrepctrrx(EP0); + stm32_ep0out(priv); } /* None of the above */ @@ -2342,7 +2342,7 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Make sure that the EP0 packet size is still OK (superstitious?) */ - stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); /* Now figure out the new RX/TX status. Here are all possible * consequences of the above EP0 operations: @@ -2379,24 +2379,24 @@ static inline void stm32l4_ep0done(struct stm32l4_usbdev_s *priv, /* Now set the new TX and RX status */ - stm32l4_seteprxstatus(EP0, priv->rxstatus); - stm32l4_seteptxstatus(EP0, priv->txstatus); + stm32_seteprxstatus(EP0, priv->rxstatus); + stm32_seteptxstatus(EP0, priv->txstatus); } /**************************************************************************** - * Name: stm32l4_lptransfer + * Name: stm32_lptransfer ****************************************************************************/ -static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) +static void stm32_lptransfer(struct stm32_usbdev_s *priv) { uint8_t epno; uint16_t istr; /* Stay in loop while LP interrupts are pending */ - while (((istr = stm32l4_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) + while (((istr = stm32_getreg(STM32_USB_ISTR)) & USB_ISTR_CTR) != 0) { - stm32l4_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); + stm32_putreg((uint16_t)~USB_ISTR_CTR, STM32_USB_ISTR); /* Extract highest priority endpoint number */ @@ -2406,31 +2406,31 @@ static void stm32l4_lptransfer(struct stm32l4_usbdev_s *priv) if (epno == 0) { - stm32l4_ep0done(priv, istr); + stm32_ep0done(priv, istr); } /* Handle other endpoint completion events */ else { - stm32l4_epdone(priv, epno); + stm32_epdone(priv, epno); } } } /**************************************************************************** - * Name: stm32l4_usbinterrupt + * Name: stm32_usbinterrupt ****************************************************************************/ -static int stm32l4_usbinterrupt(int irq, void *context, void *arg) +static int stm32_usbinterrupt(int irq, void *context, void *arg) { /* For now there is only one USB controller, but we will always refer to * it using a pointer to make any future ports to multiple USB controllers * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; - uint16_t istr = stm32l4_getreg(STM32_USB_ISTR); + struct stm32_usbdev_s *priv = &g_usbdev; + uint16_t istr = stm32_getreg(STM32_USB_ISTR); usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USBINTERRUPT), istr); @@ -2443,14 +2443,14 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) { /* Reset interrupt received. Clear the RESET interrupt status. */ - stm32l4_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_RESET, STM32_USB_ISTR); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RESET), istr); /* Restore our power-up state and exit now because istr is no longer * valid. */ - stm32l4_reset(priv); + stm32_reset(priv); goto out; } @@ -2464,13 +2464,13 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * cause of the resume is indicated in the FNR register */ - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WKUP), - stm32l4_getreg(STM32_USB_FNR)); + stm32_getreg(STM32_USB_FNR)); /* Perform the wakeup action */ - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the wakeup interrupt, and @@ -2478,31 +2478,31 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) * interrupts. */ - stm32l4_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_SUSPM, USB_CNTR_ESOFM | USB_CNTR_WKUPM); - stm32l4_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); + stm32_putreg(~USB_CNTR_SUSPM, STM32_USB_ISTR); } if ((istr & USB_ISTR_SUSP & priv->imask) != 0) { usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSP), 0); - stm32l4_suspend(priv); + stm32_suspend(priv); /* Clear of the ISTR bit must be done after setting of * USB_CNTR_FSUSP */ - stm32l4_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_SUSP, STM32_USB_ISTR); } if ((istr & USB_ISTR_ESOF & priv->imask) != 0) { - stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); /* Resume handling timing is made with ESOFs */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ESOF), 0); - stm32l4_esofpoll(priv); + stm32_esofpoll(priv); } if ((istr & USB_ISTR_CTR & priv->imask) != 0) @@ -2510,20 +2510,20 @@ static int stm32l4_usbinterrupt(int irq, void *context, void *arg) /* Low priority endpoint correct transfer interrupt */ usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_USBCTR), istr); - stm32l4_lptransfer(priv); + stm32_lptransfer(priv); } out: usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USBINTERRUPT), - stm32l4_getreg(STM32_USB_EP0R)); + stm32_getreg(STM32_USB_EP0R)); return OK; } /**************************************************************************** - * Name: stm32l4_setimask + * Name: stm32_setimask ****************************************************************************/ -static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, +static void stm32_setimask(struct stm32_usbdev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t regval; @@ -2537,10 +2537,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, * register (Hmmm... who is shadowing whom?) */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= ~USB_CNTR_ALLINTS; regval |= priv->imask; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /**************************************************************************** @@ -2548,10 +2548,10 @@ static void stm32l4_setimask(struct stm32l4_usbdev_s *priv, ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_suspend + * Name: stm32_suspend ****************************************************************************/ -static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) +static void stm32_suspend(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2566,16 +2566,16 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); /* Set the FSUSP bit in the CNTR register. This activates suspend mode * within the USB peripheral and disables further SUSP interrupts. */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_FSUSP; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* If we are not a self-powered device, the got to low-power mode */ @@ -2586,23 +2586,23 @@ static void stm32l4_suspend(struct stm32l4_usbdev_s *priv) * able to detect resume activity */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_LPMODE; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); } /* Let the board-specific logic know that we have entered the suspend * state */ - stm32l4_usbsuspend((struct usbdev_s *)priv, false); + stm32_usbsuspend((struct usbdev_s *)priv, false); } /**************************************************************************** - * Name: stm32l4_initresume + * Name: stm32_initresume ****************************************************************************/ -static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) +static void stm32_initresume(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2616,17 +2616,17 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) * hardware when a WKUP interrupt event occurs). */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_LPMODE); - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); /* Restore full power -- whatever that means for this particular board */ - stm32l4_usbsuspend((struct usbdev_s *)priv, true); + stm32_usbsuspend((struct usbdev_s *)priv, true); /* Reset FSUSP bit and enable normal interrupt handling */ - stm32l4_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); + stm32_putreg(STM32_CNTR_SETUP, STM32_USB_CNTR); /* Notify the class driver of the resume event */ @@ -2637,10 +2637,10 @@ static void stm32l4_initresume(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_esofpoll + * Name: stm32_esofpoll ****************************************************************************/ -static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) +static void stm32_esofpoll(struct stm32_usbdev_s *priv) { uint16_t regval; @@ -2651,9 +2651,9 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) /* One ESOF after internal resume requested */ case RSMSTATE_STARTED: - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval |= USB_CNTR_RESUME; - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_WAITING; priv->nesofs = 10; break; @@ -2666,18 +2666,18 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) { /* Okay.. we are ready to resume normal operation */ - regval = stm32l4_getreg(STM32_USB_CNTR); + regval = stm32_getreg(STM32_USB_CNTR); regval &= (~USB_CNTR_RESUME); - stm32l4_putreg(regval, STM32_USB_CNTR); + stm32_putreg(regval, STM32_USB_CNTR); priv->rsmstate = RSMSTATE_IDLE; /* Disable ESOF polling, disable the SUSP interrupt, and enable * the WKUP interrupt. Clear any pending WKUP interrupt. */ - stm32l4_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | + stm32_setimask(priv, USB_CNTR_WKUPM, USB_CNTR_ESOFM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); + stm32_putreg(~USB_ISTR_WKUP, STM32_USB_ISTR); } break; @@ -2693,13 +2693,13 @@ static void stm32l4_esofpoll(struct stm32l4_usbdev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epreserve + * Name: stm32_epreserve ****************************************************************************/ -static inline struct stm32l4_ep_s * -stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) +static inline struct stm32_ep_s * +stm32_epreserve(struct stm32_usbdev_s *priv, uint8_t epset) { - struct stm32l4_ep_s *privep = NULL; + struct stm32_ep_s *privep = NULL; irqstate_t flags; int epndx = 0; @@ -2733,12 +2733,12 @@ stm32l4_epreserve(struct stm32l4_usbdev_s *priv, uint8_t epset) } /**************************************************************************** - * Name: stm32l4_epunreserve + * Name: stm32_epunreserve ****************************************************************************/ static inline void -stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, - struct stm32l4_ep_s *privep) +stm32_epunreserve(struct stm32_usbdev_s *priv, + struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); priv->epavail |= STM32_ENDP_BIT(USB_EPNO(privep->ep.eplog)); @@ -2746,20 +2746,20 @@ stm32l4_epunreserve(struct stm32l4_usbdev_s *priv, } /**************************************************************************** - * Name: stm32l4_epreserved + * Name: stm32_epreserved ****************************************************************************/ static inline bool -stm32l4_epreserved(struct stm32l4_usbdev_s *priv, int epno) +stm32_epreserved(struct stm32_usbdev_s *priv, int epno) { return ((priv->epavail & STM32_ENDP_BIT(epno)) == 0); } /**************************************************************************** - * Name: stm32l4_epallocpma + * Name: stm32_epallocpma ****************************************************************************/ -static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) +static int stm32_epallocpma(struct stm32_usbdev_s *priv) { irqstate_t flags; int bufno = ERROR; @@ -2789,11 +2789,11 @@ static int stm32l4_epallocpma(struct stm32l4_usbdev_s *priv) } /**************************************************************************** - * Name: stm32l4_epfreepma + * Name: stm32_epfreepma ****************************************************************************/ static inline void -stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) +stm32_epfreepma(struct stm32_usbdev_s *priv, struct stm32_ep_s *privep) { irqstate_t flags = enter_critical_section(); priv->epavail |= STM32_ENDP_BIT(privep->bufno); @@ -2805,14 +2805,14 @@ stm32l4_epfreepma(struct stm32l4_usbdev_s *priv, struct stm32l4_ep_s *privep) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_epconfigure + * Name: stm32_epconfigure ****************************************************************************/ -static int stm32l4_epconfigure(struct usbdev_ep_s *ep, +static int stm32_epconfigure(struct usbdev_ep_s *ep, const struct usb_epdesc_s *desc, bool last) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; uint16_t pma; uint16_t setting; uint16_t maxpacket; @@ -2860,7 +2860,7 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, return -EINVAL; } - stm32l4_seteptype(epno, setting); + stm32_seteptype(epno, setting); /* Get the address of the PMA buffer allocated for this endpoint */ @@ -2883,9 +2883,9 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up TX; disable RX */ - stm32l4_seteptxaddr(epno, pma); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_NAK); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxaddr(epno, pma); + stm32_seteptxstatus(epno, USB_EPR_STATTX_NAK); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); } else { @@ -2895,23 +2895,23 @@ static int stm32l4_epconfigure(struct usbdev_ep_s *ep, /* Set up RX; disable TX */ - stm32l4_seteprxaddr(epno, pma); - stm32l4_seteprxcount(epno, maxpacket); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxaddr(epno, pma); + stm32_seteprxcount(epno, maxpacket); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); } - stm32l4_dumpep(epno); + stm32_dumpep(epno); return OK; } /**************************************************************************** - * Name: stm32l4_epdisable + * Name: stm32_epdisable ****************************************************************************/ -static int stm32l4_epdisable(struct usbdev_ep_s *ep) +static int stm32_epdisable(struct usbdev_ep_s *ep) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; uint8_t epno; @@ -2930,25 +2930,25 @@ static int stm32l4_epdisable(struct usbdev_ep_s *ep) /* Cancel any ongoing activity */ flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Disable TX; disable RX */ - stm32l4_seteprxcount(epno, 0); - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_DIS); - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_DIS); + stm32_seteprxcount(epno, 0); + stm32_seteprxstatus(epno, USB_EPR_STATRX_DIS); + stm32_seteptxstatus(epno, USB_EPR_STATTX_DIS); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epallocreq + * Name: stm32_epallocreq ****************************************************************************/ -static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) +static struct usbdev_req_s *stm32_epallocreq(struct usbdev_ep_s *ep) { - struct stm32l4_req_s *privreq; + struct stm32_req_s *privreq; #ifdef CONFIG_DEBUG_FEATURES if (!ep) @@ -2960,25 +2960,25 @@ static struct usbdev_req_s *stm32l4_epallocreq(struct usbdev_ep_s *ep) usbtrace(TRACE_EPALLOCREQ, USB_EPNO(ep->eplog)); - privreq = kmm_malloc(sizeof(struct stm32l4_req_s)); + privreq = kmm_malloc(sizeof(struct stm32_req_s)); if (!privreq) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); return NULL; } - memset(privreq, 0, sizeof(struct stm32l4_req_s)); + memset(privreq, 0, sizeof(struct stm32_req_s)); return &privreq->req; } /**************************************************************************** - * Name: stm32l4_epfreereq + * Name: stm32_epfreereq ****************************************************************************/ -static void stm32l4_epfreereq(struct usbdev_ep_s *ep, +static void stm32_epfreereq(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; #ifdef CONFIG_DEBUG_FEATURES if (!ep || !req) @@ -2994,14 +2994,14 @@ static void stm32l4_epfreereq(struct usbdev_ep_s *ep, } /**************************************************************************** - * Name: stm32l4_epsubmit + * Name: stm32_epsubmit ****************************************************************************/ -static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_req_s *privreq = (struct stm32l4_req_s *)req; - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; - struct stm32l4_usbdev_s *priv; + struct stm32_req_s *privreq = (struct stm32_req_s *)req; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; + struct stm32_usbdev_s *priv; irqstate_t flags; uint8_t epno; int ret = OK; @@ -3040,7 +3040,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (privep->stalled) { - stm32l4_abortrequest(privep, privreq, -EBUSY); + stm32_abortrequest(privep, privreq, -EBUSY); uerr("ERROR: stalled\n"); ret = -EBUSY; } @@ -3054,7 +3054,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { /* Add the new request to the request queue for the IN endpoint */ - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_INREQQUEUED(epno), req->len); /* If the IN endpoint FIFO is available, then transfer the data now */ @@ -3064,16 +3064,16 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - ret = stm32l4_wrrequest_ep0(priv, privep); + ret = stm32_wrrequest_ep0(priv, privep); } else { - ret = stm32l4_wrrequest(priv, privep); + ret = stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } @@ -3084,7 +3084,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) /* Add the new request to the request queue for the OUT endpoint */ privep->txnullpkt = 0; - stm32l4_rqenqueue(privep, privreq); + stm32_rqenqueue(privep, privreq); usbtrace(TRACE_OUTREQQUEUED(epno), req->len); /* This there a incoming data pending the availability of a request? */ @@ -3099,7 +3099,7 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) */ priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, priv->rxstatus); + stm32_seteprxstatus(epno, priv->rxstatus); /* Data is no longer pending */ @@ -3112,12 +3112,12 @@ static int stm32l4_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) } /**************************************************************************** - * Name: stm32l4_epcancel + * Name: stm32_epcancel ****************************************************************************/ -static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) +static int stm32_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { - struct stm32l4_ep_s *privep = (struct stm32l4_ep_s *)ep; + struct stm32_ep_s *privep = (struct stm32_ep_s *)ep; irqstate_t flags; #ifdef CONFIG_DEBUG_USB @@ -3131,19 +3131,19 @@ static int stm32l4_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) usbtrace(TRACE_EPCANCEL, USB_EPNO(ep->eplog)); flags = enter_critical_section(); - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_epstall + * Name: stm32_epstall ****************************************************************************/ -static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) +static int stm32_epstall(struct usbdev_ep_s *ep, bool resume) { - struct stm32l4_ep_s *privep; - struct stm32l4_usbdev_s *priv; + struct stm32_ep_s *privep; + struct stm32_usbdev_s *priv; uint8_t epno; uint16_t status; irqstate_t flags; @@ -3156,8 +3156,8 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) } #endif - privep = (struct stm32l4_ep_s *)ep; - priv = (struct stm32l4_usbdev_s *)privep->dev; + privep = (struct stm32_ep_s *)ep; + priv = (struct stm32_usbdev_s *)privep->dev; epno = USB_EPNO(ep->eplog); /* STALL or RESUME the endpoint */ @@ -3171,11 +3171,11 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) if (USB_ISEPIN(ep->eplog)) { - status = stm32l4_geteptxstatus(epno); + status = stm32_geteptxstatus(epno); } else { - status = stm32l4_geteprxstatus(epno); + status = stm32_geteprxstatus(epno); } if (status == 0) @@ -3204,32 +3204,32 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) { /* IN endpoint */ - if (stm32l4_eptxstalled(epno)) + if (stm32_eptxstalled(epno)) { - stm32l4_clrtxdtog(epno); + stm32_clrtxdtog(epno); /* Restart any queued write requests */ priv->txstatus = USB_EPR_STATTX_NAK; if (epno == EP0) { - stm32l4_wrrequest_ep0(priv, privep); + stm32_wrrequest_ep0(priv, privep); } else { - stm32l4_wrrequest(priv, privep); + stm32_wrrequest(priv, privep); } /* Set the new TX status */ - stm32l4_seteptxstatus(epno, priv->txstatus); + stm32_seteptxstatus(epno, priv->txstatus); } } else { /* OUT endpoint */ - if (stm32l4_eprxstalled(epno)) + if (stm32_eprxstalled(epno)) { if (epno == EP0) { @@ -3237,15 +3237,15 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) * enable the default endpoint receiver */ - stm32l4_seteprxcount(epno, ep->maxpacket); + stm32_seteprxcount(epno, ep->maxpacket); } else { - stm32l4_clrrxdtog(epno); + stm32_clrrxdtog(epno); } priv->rxstatus = USB_EPR_STATRX_VALID; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_VALID); + stm32_seteprxstatus(epno, USB_EPR_STATRX_VALID); } } } @@ -3262,14 +3262,14 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) /* IN endpoint */ priv->txstatus = USB_EPR_STATTX_STALL; - stm32l4_seteptxstatus(epno, USB_EPR_STATTX_STALL); + stm32_seteptxstatus(epno, USB_EPR_STATTX_STALL); } else { /* OUT endpoint */ priv->rxstatus = USB_EPR_STATRX_STALL; - stm32l4_seteprxstatus(epno, USB_EPR_STATRX_STALL); + stm32_seteprxstatus(epno, USB_EPR_STATRX_STALL); } } @@ -3282,15 +3282,15 @@ static int stm32l4_epstall(struct usbdev_ep_s *ep, bool resume) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_allocep + * Name: stm32_allocep ****************************************************************************/ -static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, +static struct usbdev_ep_s *stm32_allocep(struct usbdev_s *dev, uint8_t epno, bool in, uint8_t eptype) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; - struct stm32l4_ep_s *privep = NULL; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; + struct stm32_ep_s *privep = NULL; uint8_t epset = STM32_ENDP_ALLSET; int bufno; @@ -3335,7 +3335,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, /* Check if the selected endpoint number is available */ - privep = stm32l4_epreserve(priv, epset); + privep = stm32_epreserve(priv, epset); if (!privep) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPRESERVE), (uint16_t)epset); @@ -3345,7 +3345,7 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, /* Allocate a PMA buffer for this endpoint */ #warning "REVISIT: Should configure BULK EPs using double buffer feature" - bufno = stm32l4_epallocpma(priv); + bufno = stm32_epallocpma(priv); if (bufno < 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPBUFFER), 0); @@ -3356,19 +3356,19 @@ static struct usbdev_ep_s *stm32l4_allocep(struct usbdev_s *dev, return &privep->ep; errout_with_ep: - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); errout: return NULL; } /**************************************************************************** - * Name: stm32l4_freeep + * Name: stm32_freeep ****************************************************************************/ -static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) +static void stm32_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) { - struct stm32l4_usbdev_s *priv; - struct stm32l4_ep_s *privep; + struct stm32_usbdev_s *priv; + struct stm32_ep_s *privep; #ifdef CONFIG_DEBUG_USB if (!dev || !ep) @@ -3378,27 +3378,27 @@ static void stm32l4_freeep(struct usbdev_s *dev, struct usbdev_ep_s *ep) } #endif - priv = (struct stm32l4_usbdev_s *)dev; - privep = (struct stm32l4_ep_s *)ep; + priv = (struct stm32_usbdev_s *)dev; + privep = (struct stm32_ep_s *)ep; usbtrace(TRACE_DEVFREEEP, (uint16_t)USB_EPNO(ep->eplog)); if (priv && privep) { /* Free the PMA buffer assigned to this endpoint */ - stm32l4_epfreepma(priv, privep); + stm32_epfreepma(priv, privep); /* Mark the endpoint as available */ - stm32l4_epunreserve(priv, privep); + stm32_epunreserve(priv, privep); } } /**************************************************************************** - * Name: stm32l4_getframe + * Name: stm32_getframe ****************************************************************************/ -static int stm32l4_getframe(struct usbdev_s *dev) +static int stm32_getframe(struct usbdev_s *dev) { uint16_t fnr; @@ -3412,18 +3412,18 @@ static int stm32l4_getframe(struct usbdev_s *dev) /* Return the last frame number detected by the hardware */ - fnr = stm32l4_getreg(STM32_USB_FNR); + fnr = stm32_getreg(STM32_USB_FNR); usbtrace(TRACE_DEVGETFRAME, fnr); return (fnr & USB_FNR_FN_MASK); } /**************************************************************************** - * Name: stm32l4_wakeup + * Name: stm32_wakeup ****************************************************************************/ -static int stm32l4_wakeup(struct usbdev_s *dev) +static int stm32_wakeup(struct usbdev_s *dev) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; irqstate_t flags; usbtrace(TRACE_DEVWAKEUP, 0); @@ -3440,7 +3440,7 @@ static int stm32l4_wakeup(struct usbdev_s *dev) */ flags = enter_critical_section(); - stm32l4_initresume(priv); + stm32_initresume(priv); priv->rsmstate = RSMSTATE_STARTED; /* Disable the SUSP interrupt (until we are fully resumed), disable @@ -3449,19 +3449,19 @@ static int stm32l4_wakeup(struct usbdev_s *dev) * pending ESOF interrupt. */ - stm32l4_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); - stm32l4_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); + stm32_setimask(priv, USB_CNTR_ESOFM, USB_CNTR_WKUPM | USB_CNTR_SUSPM); + stm32_putreg(~USB_ISTR_ESOF, STM32_USB_ISTR); leave_critical_section(flags); return OK; } /**************************************************************************** - * Name: stm32l4_selfpowered + * Name: stm32_selfpowered ****************************************************************************/ -static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) { - struct stm32l4_usbdev_s *priv = (struct stm32l4_usbdev_s *)dev; + struct stm32_usbdev_s *priv = (struct stm32_usbdev_s *)dev; usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); @@ -3478,10 +3478,10 @@ static int stm32l4_selfpowered(struct usbdev_s *dev, bool selfpowered) } /**************************************************************************** - * Name: stm32l4_pullup + * Name: stm32_pullup ****************************************************************************/ -static int stm32l4_pullup(struct usbdev_s *dev, bool enable) +static int stm32_pullup(struct usbdev_s *dev, bool enable) { uint32_t regval; irqstate_t flags; @@ -3489,7 +3489,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); flags = enter_critical_section(); - regval = stm32l4_getreg(STM32_USB_BCDR); + regval = stm32_getreg(STM32_USB_BCDR); if (enable) { /* Connect the device by setting the DP pull-up bit in the BCDR @@ -3507,7 +3507,7 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) regval &= ~USB_BCDR_DPPU; } - stm32l4_putreg(regval, STM32_USB_BCDR); + stm32_putreg(regval, STM32_USB_BCDR); leave_critical_section(flags); return OK; } @@ -3517,16 +3517,16 @@ static int stm32l4_pullup(struct usbdev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_reset + * Name: stm32_reset ****************************************************************************/ -static void stm32l4_reset(struct stm32l4_usbdev_s *priv) +static void stm32_reset(struct stm32_usbdev_s *priv) { int epno; /* Put the USB controller in reset, disable all interrupts */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Tell the class driver that we are disconnected. The class driver * should then accept any new configurations. @@ -3544,17 +3544,17 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) for (epno = 0; epno < STM32_NENDPOINTS; epno++) { - struct stm32l4_ep_s *privep = &priv->eplist[epno]; + struct stm32_ep_s *privep = &priv->eplist[epno]; /* Cancel any queued requests. Since they are canceled * with status -ESHUTDOWN, then will not be requeued * until the configuration is reset. NOTE: This should * not be necessary... the CLASS_DISCONNECT above should - * result in the class implementation calling stm32l4_epdisable + * result in the class implementation calling stm32_epdisable * for each of its configured endpoints. */ - stm32l4_cancelrequests(privep); + stm32_cancelrequests(privep); /* Reset endpoint status */ @@ -3566,59 +3566,59 @@ static void stm32l4_reset(struct stm32l4_usbdev_s *priv) /* Re-configure the USB controller in its initial, unconnected state */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); priv->usbdev.speed = USB_SPEED_FULL; } /**************************************************************************** - * Name: stm32l4_hwreset + * Name: stm32_hwreset ****************************************************************************/ -static void stm32l4_hwreset(struct stm32l4_usbdev_s *priv) +static void stm32_hwreset(struct stm32_usbdev_s *priv) { /* Put the USB controller into reset, clear all interrupt enables */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Disable interrupts (and perhaps take the USB controller out of reset) */ priv->imask = 0; - stm32l4_putreg(priv->imask, STM32_USB_CNTR); + stm32_putreg(priv->imask, STM32_USB_CNTR); /* Set the STM32 BTABLE address */ - stm32l4_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); + stm32_putreg(STM32_BTABLE_ADDRESS & 0xfff8, STM32_USB_BTABLE); /* Initialize EP0 */ - stm32l4_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); - stm32l4_seteptxstatus(EP0, USB_EPR_STATTX_NAK); - stm32l4_seteprxaddr(EP0, STM32_EP0_RXADDR); - stm32l4_seteprxcount(EP0, STM32_EP0MAXPACKET); - stm32l4_seteptxaddr(EP0, STM32_EP0_TXADDR); - stm32l4_clrstatusout(EP0); - stm32l4_seteprxstatus(EP0, USB_EPR_STATRX_VALID); + stm32_seteptype(EP0, USB_EPR_EPTYPE_CONTROL); + stm32_seteptxstatus(EP0, USB_EPR_STATTX_NAK); + stm32_seteprxaddr(EP0, STM32_EP0_RXADDR); + stm32_seteprxcount(EP0, STM32_EP0MAXPACKET); + stm32_seteptxaddr(EP0, STM32_EP0_TXADDR); + stm32_clrstatusout(EP0); + stm32_seteprxstatus(EP0, USB_EPR_STATRX_VALID); /* Set the device to respond on default address */ - stm32l4_setdevaddr(priv, 0); + stm32_setdevaddr(priv, 0); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Enable interrupts at the USB controller */ - stm32l4_setimask(priv, STM32_CNTR_SETUP, + stm32_setimask(priv, STM32_CNTR_SETUP, (USB_CNTR_ALLINTS & ~STM32_CNTR_SETUP)); - stm32l4_dumpep(EP0); + stm32_dumpep(EP0); } /**************************************************************************** - * Name: stm32l4_hwsetup + * Name: stm32_hwsetup ****************************************************************************/ -static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) +static void stm32_hwsetup(struct stm32_usbdev_s *priv) { int epno; @@ -3626,20 +3626,20 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * all USB interrupts */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); /* Disconnect the device / disable the pull-up. We don't want the * host to enumerate us until the class driver is registered. */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Initialize the device state structure. NOTE: many fields * have the initial value of zero and, hence, are not explicitly * initialized here. */ - memset(priv, 0, sizeof(struct stm32l4_usbdev_s)); + memset(priv, 0, sizeof(struct stm32_usbdev_s)); priv->usbdev.ops = &g_devops; priv->usbdev.ep0 = &priv->eplist[EP0].ep; priv->epavail = STM32_ENDP_ALLSET & ~STM32_ENDP_BIT(EP0); @@ -3691,33 +3691,33 @@ static void stm32l4_hwsetup(struct stm32l4_usbdev_s *priv) * class driver has been bound. */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); up_mdelay(5); } /**************************************************************************** - * Name: stm32l4_hwshutdown + * Name: stm32_hwshutdown ****************************************************************************/ -static void stm32l4_hwshutdown(struct stm32l4_usbdev_s *priv) +static void stm32_hwshutdown(struct stm32_usbdev_s *priv) { priv->usbdev.speed = USB_SPEED_UNKNOWN; /* Disable all interrupts and force the USB controller into reset */ - stm32l4_putreg(USB_CNTR_FRES, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES, STM32_USB_CNTR); /* Clear any pending interrupts */ - stm32l4_putreg(0, STM32_USB_ISTR); + stm32_putreg(0, STM32_USB_ISTR); /* Disconnect the device / disable the pull-up */ - stm32l4_pullup(&priv->usbdev, false); + stm32_pullup(&priv->usbdev, false); /* Power down the USB controller */ - stm32l4_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); + stm32_putreg(USB_CNTR_FRES | USB_CNTR_PDWN, STM32_USB_CNTR); } /**************************************************************************** @@ -3739,25 +3739,25 @@ void arm_usbinitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; usbtrace(TRACE_DEVINIT, 0); - stm32l4_checksetup(); + stm32_checksetup(); /* Enable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); /* Power up the USB controller, but leave it in the reset state */ - stm32l4_hwsetup(priv); + stm32_hwsetup(priv); /* Attach USB controller interrupt handler. The hardware will not be * initialized and interrupts will not be enabled until the class device * driver is bound. */ - if (irq_attach(STM32_IRQ_USB_FS, stm32l4_usbinterrupt, NULL) != 0) + if (irq_attach(STM32_IRQ_USB_FS, stm32_usbinterrupt, NULL) != 0) { usbtrace(TRACE_DEVERROR(STM32_TRACEERR_IRQREGISTRATION), (uint16_t)STM32_IRQ_USB_FS); @@ -3780,7 +3780,7 @@ void arm_usbuninitialize(void) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; flags = enter_critical_section(); @@ -3799,11 +3799,11 @@ void arm_usbuninitialize(void) /* Put the hardware in an inactive state */ - stm32l4_hwshutdown(priv); + stm32_hwshutdown(priv); /* Disable Vbus monitoring in the Power control */ - stm32l4_pwr_enableusv(false); + stm32_pwr_enableusv(false); leave_critical_section(flags); } @@ -3824,7 +3824,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; int ret; usbtrace(TRACE_DEVREGISTER, 0); @@ -3861,7 +3861,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * the USB controller */ - stm32l4_hwreset(priv); + stm32_hwreset(priv); /* Enable USB controller interrupt at the NVIC */ @@ -3871,7 +3871,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) * The host should enumerate us some time after this */ - stm32l4_pullup(&priv->usbdev, true); + stm32_pullup(&priv->usbdev, true); priv->usbdev.speed = USB_SPEED_FULL; } @@ -3896,7 +3896,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) * easier. */ - struct stm32l4_usbdev_s *priv = &g_usbdev; + struct stm32_usbdev_s *priv = &g_usbdev; irqstate_t flags; usbtrace(TRACE_DEVUNREGISTER, 0); @@ -3914,7 +3914,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) */ flags = enter_critical_section(); - stm32l4_reset(priv); + stm32_reset(priv); /* Unbind the class driver */ @@ -3925,12 +3925,12 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) up_disable_irq(STM32_IRQ_USB_FS); /* Put the hardware in an inactive state. Then bring the hardware back up - * in the reset state (this is probably not necessary, the stm32l4_reset() + * in the reset state (this is probably not necessary, the stm32_reset() * call above was probably sufficient). */ - stm32l4_hwshutdown(priv); - stm32l4_hwsetup(priv); + stm32_hwshutdown(priv); + stm32_hwsetup(priv); /* Unhook the driver */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.h b/arch/arm/src/stm32l4/stm32l4_usbdev.h index 97492ddf7d7..129e7e3b2da 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.h @@ -50,17 +50,17 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. * ****************************************************************************/ -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume); +void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index f0446e960db..92fe5d17a78 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -168,7 +168,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -196,7 +196,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_usbhost_vbusdrive(int iface, bool enable); +void stm32_usbhost_vbusdrive(int iface, bool enable); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c index 178beee45e5..8ff12523480 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c +++ b/arch/arm/src/stm32l4/stm32l4_usbhost_trace.c @@ -47,7 +47,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_usbhost_trace_s +struct stm32_usbhost_trace_s { #if 0 uint16_t id; @@ -60,7 +60,7 @@ struct stm32l4_usbhost_trace_s * Private Data ****************************************************************************/ -static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = { TRENTRY(OTGFS_TRACE1_DEVDISCONN, TR_FMT1, "OTGFS ERROR: Host Port %d. Device disconnected\n"), @@ -117,7 +117,7 @@ static const struct stm32l4_usbhost_trace_s g_trace1[TRACE1_NSTRINGS] = #endif }; -static const struct stm32l4_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = +static const struct stm32_usbhost_trace_s g_trace2[TRACE2_NSTRINGS] = { TRENTRY(OTGFS_TRACE2_CLIP, TR_FMT2, "OTGFS CLIP: chidx: %d buflen: %d\n"), diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.c b/arch/arm/src/stm32l4/stm32l4_userspace.c index e6e181f9e19..d2368763253 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.c +++ b/arch/arm/src/stm32l4/stm32l4_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l4_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l4_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l4_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l4/stm32l4_userspace.h b/arch/arm/src/stm32l4/stm32l4_userspace.h index f965dc09ffd..46ef7f79706 100644 --- a/arch/arm/src/stm32l4/stm32l4_userspace.h +++ b/arch/arm/src/stm32l4/stm32l4_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l4_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USERSPACE_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_waste.c b/arch/arm/src/stm32l4/stm32l4_waste.c index 1335005e75b..054d0324afe 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.c +++ b/arch/arm/src/stm32l4/stm32l4_waste.c @@ -38,7 +38,7 @@ uint32_t g_waste_counter = 0; * Public Functions ****************************************************************************/ -void stm32l4_waste(void) +void stm32_waste(void) { g_waste_counter++; } diff --git a/arch/arm/src/stm32l4/stm32l4_waste.h b/arch/arm/src/stm32l4/stm32l4_waste.h index bc24eff6c39..6281c7dbde0 100644 --- a/arch/arm/src/stm32l4/stm32l4_waste.h +++ b/arch/arm/src/stm32l4/stm32l4_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32l4_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a * measure of badly written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32l4_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index 1e2a8e1dbdd..7d7bbfb8d37 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_iwdginitialize + * Name: stm32_iwdginitialize * * Description: * Initialize the IWDG watchdog time. The watchdog timer is initialized @@ -72,11 +72,11 @@ extern "C" ****************************************************************************/ #ifdef CONFIG_STM32L4_IWDG -void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); +void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif /**************************************************************************** - * Name: stm32l4_wwdginitialize + * Name: stm32_wwdginitialize * * Description: * Initialize the WWDG watchdog time. The watchdog timer is initialized @@ -93,7 +93,7 @@ void stm32l4_iwdginitialize(const char *devpath, uint32_t lsifreq); ****************************************************************************/ #ifdef CONFIG_STM32L4_WWDG -void stm32l4_wwdginitialize(const char *devpath); +void stm32_wwdginitialize(const char *devpath); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index 99cce2c222b..a558bbaa59f 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -591,7 +591,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -601,7 +601,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -690,7 +690,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -886,7 +886,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -901,7 +901,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -912,7 +912,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -942,7 +942,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 0c90408ee34..5dadb8cb232 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -581,7 +581,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -591,7 +591,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -680,7 +680,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -876,7 +876,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -891,7 +891,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -902,7 +902,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index 61ba84d2491..bf916f033a9 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -41,7 +41,7 @@ #include "sched/sched.h" #include "chip.h" #include "stm32l4_dma.h" -#include "stm32l4.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ /* This structure describes one DMA channel */ -struct stm32l4_dma_s +struct stm32_dma_s { uint8_t chan; /* DMA channel number (0-6) */ uint8_t function; /* DMA peripheral connected to this channel (0-7) */ @@ -82,7 +82,7 @@ struct stm32l4_dma_s /* This array describes the state of each DMA */ -static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static struct stm32_dma_s g_dma[DMA_NCHANNELS] = { { .chan = 0, @@ -182,7 +182,7 @@ static struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* Get non-channel register from DMA1 or DMA2 */ -static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmabase_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(DMA_BASE(dmach->base) + offset); @@ -190,7 +190,7 @@ static inline uint32_t dmabase_getreg(struct stm32l4_dma_s *dmach, /* Write to non-channel register in DMA1 or DMA2 */ -static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, +static inline void dmabase_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, DMA_BASE(dmach->base) + offset); @@ -198,7 +198,7 @@ static inline void dmabase_putreg(struct stm32l4_dma_s *dmach, /* Get channel register from DMA1 or DMA2 */ -static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, +static inline uint32_t dmachan_getreg(struct stm32_dma_s *dmach, uint32_t offset) { return getreg32(dmach->base + offset); @@ -206,21 +206,21 @@ static inline uint32_t dmachan_getreg(struct stm32l4_dma_s *dmach, /* Write to channel register in DMA1 or DMA2 */ -static inline void dmachan_putreg(struct stm32l4_dma_s *dmach, +static inline void dmachan_putreg(struct stm32_dma_s *dmach, uint32_t offset, uint32_t value) { putreg32(value, dmach->base + offset); } /**************************************************************************** - * Name: stm32l4_dmachandisable + * Name: stm32_dmachandisable * * Description: * Disable the DMA channel * ****************************************************************************/ -static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) +static void stm32_dmachandisable(struct stm32_dma_s *dmach) { uint32_t regval; @@ -241,16 +241,16 @@ static void stm32l4_dmachandisable(struct stm32l4_dma_s *dmach) } /**************************************************************************** - * Name: stm32l4_dmainterrupt + * Name: stm32_dmainterrupt * * Description: * DMA interrupt handler * ****************************************************************************/ -static int stm32l4_dmainterrupt(int irq, void *context, void *arg) +static int stm32_dmainterrupt(int irq, void *context, void *arg) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; uint32_t isr; int chndx = 0; @@ -303,7 +303,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dmainitialize + * Name: stm32_dmainitialize * * Description: * Initialize the DMA subsystem @@ -315,7 +315,7 @@ static int stm32l4_dmainterrupt(int irq, void *context, void *arg) void weak_function arm_dma_initialize(void) { - struct stm32l4_dma_s *dmach; + struct stm32_dma_s *dmach; int chndx; /* Initialize each DMA channel */ @@ -326,11 +326,11 @@ void weak_function arm_dma_initialize(void) /* Attach DMA interrupt vectors */ - irq_attach(dmach->irq, stm32l4_dmainterrupt, NULL); + irq_attach(dmach->irq, stm32_dmainterrupt, NULL); /* Disable the DMA channel */ - stm32l4_dmachandisable(dmach); + stm32_dmachandisable(dmach); /* Enable the IRQ at the NVIC (still disabled at the DMA controller) */ @@ -339,7 +339,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -348,10 +348,10 @@ void weak_function arm_dma_initialize(void) * channel cannot do DMA concurrently! See the DMACHAN_* definitions in * stm32l4_dma.h. * - * If the DMA channel is not available, then stm32l4_dmachannel() will wait + * If the DMA channel is not available, then stm32_dmachannel() will wait * until the holder of the channel relinquishes the channel by calling - * stm32l4_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32l4_dmachannel + * stm32_dmafree(). WARNING: If you have two devices sharing a DMA + * channel and the code never releases the channel, the stm32_dmachannel * call for the other will hang forever in this function! Don't let your * design do that! * @@ -375,12 +375,12 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) +DMA_HANDLE stm32_dmachannel(unsigned int chndef) { int ret; int chndx = (chndef & DMACHAN_SETTING_CHANNEL_MASK) >> DMACHAN_SETTING_CHANNEL_SHIFT; - struct stm32l4_dma_s *dmach = &g_dma[chndx]; + struct stm32_dma_s *dmach = &g_dma[chndx]; DEBUGASSERT(chndx < DMA_NCHANNELS); @@ -407,13 +407,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA channel - * in a call to stm32l4_dmachannel, then this function will re-assign the + * in a call to stm32_dmachannel, then this function will re-assign the * DMA channel to that thread and wake it up. NOTE: The 'handle' used - * in this argument must NEVER be used again until stm32l4_dmachannel() is + * in this argument must NEVER be used again until stm32_dmachannel() is * called again to re-gain access to the channel. * * Returned Value: @@ -425,9 +425,9 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int chndef) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; DEBUGASSERT(handle != NULL); @@ -437,17 +437,17 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t regval; DEBUGASSERT(handle != NULL); @@ -505,21 +505,21 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t ccr; DEBUGASSERT(handle != NULL); @@ -571,44 +571,44 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; - stm32l4_dmachandisable(dmach); + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; + stm32_dmachandisable(dmach); } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; return dmachan_getreg(dmach, STM32_DMACHAN_CNDTR_OFFSET); } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -622,7 +622,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; uint32_t mend; @@ -698,20 +698,20 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; irqstate_t flags; flags = enter_critical_section(); @@ -726,21 +726,21 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { - struct stm32l4_dma_s *dmach = (struct stm32l4_dma_s *)handle; + struct stm32_dma_s *dmach = (struct stm32_dma_s *)handle; uint32_t dmabase = DMA_BASE(dmach->base); dmainfo("DMA Registers: %s\n", msg); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index c89579c15ac..5e14421ea49 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -659,7 +659,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -669,7 +669,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -793,7 +793,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -812,7 +812,7 @@ static void stm32l4_stdclockconfig(void) /* TODO: this seems to hang on STM32L476, at least for MSI@48MHz */ #if 0 - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(1); #endif } @@ -822,7 +822,7 @@ static void stm32l4_stdclockconfig(void) * frequencies below 24 MHz */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); stm32_pwr_setvos(2); } @@ -1002,7 +1002,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_BOARD_USEHSI) @@ -1025,7 +1025,7 @@ static void stm32l4_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l4_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -1036,7 +1036,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -1066,7 +1066,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 056a18024d3..735ce580c69 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -82,20 +82,20 @@ /* This structure described one DMAMUX device */ -struct stm32l4_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32l4_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32l4_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32l4_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -104,7 +104,7 @@ struct stm32l4_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32l4_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -117,11 +117,11 @@ struct stm32l4_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32l4_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32l4_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -152,12 +152,12 @@ struct stm32l4_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -167,19 +167,19 @@ struct stm32l4_dma_ops_s ****************************************************************************/ #if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan); -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg); -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32l4_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_sample(DMA_HANDLE handle, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -194,14 +194,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs); -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -210,20 +210,20 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { #ifdef CONFIG_STM32L4_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -236,14 +236,14 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* 1 - DMA2 */ { - .dma_disable = stm32l4_dma12_disable, - .dma_interrupt = stm32l4_dma12_interrupt, - .dma_setup = stm32l4_dma12_setup, - .dma_start = stm32l4_dma12_start, - .dma_residual = stm32l4_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32l4_dma12_sample, - .dma_dump = stm32l4_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -255,7 +255,7 @@ static const struct stm32l4_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, @@ -266,7 +266,7 @@ static const struct stm32l4_dmamux_s g_dmamux[DMAMUX_NUM] = /* This array describes the state of each controller */ -static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ @@ -291,7 +291,7 @@ static const struct stm32l4_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32l4_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { #ifdef CONFIG_STM32L4_DMA1 /* DMA1 */ @@ -524,7 +524,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32l4_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -532,7 +532,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -540,7 +540,7 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -548,14 +548,14 @@ static DMA_CHANNEL stm32l4_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32l4_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -574,14 +574,14 @@ static void stm32l4_gdma_limits_get(uint8_t controller, uint8_t *first, #if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) /**************************************************************************** - * Name: stm32l4_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -604,14 +604,14 @@ static void stm32l4_dma12_disable(DMA_CHANNEL dmachan) } /**************************************************************************** - * Name: stm32l4_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -650,7 +650,7 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32l4_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ @@ -673,14 +673,14 @@ static int stm32l4_dma12_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32l4_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -745,13 +745,13 @@ static void stm32l4_dma12_setup(DMA_HANDLE handle, uint32_t paddr, } /**************************************************************************** - * Name: stm32l4_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -807,10 +807,10 @@ static void stm32l4_dma12_start(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32l4_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32l4_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -820,11 +820,11 @@ static size_t stm32l4_dma12_residual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; @@ -837,7 +837,7 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32l4_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -846,12 +846,12 @@ void stm32l4_dma12_sample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dma12_dump(DMA_HANDLE handle, - const struct stm32l4_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -879,7 +879,7 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32l4_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } @@ -888,12 +888,12 @@ static void stm32l4_dma12_dump(DMA_HANDLE handle, #endif /* CONFIG_STM32L4_DMA1 || CONFIG_STM32L4_DMA2 */ /**************************************************************************** - * Name: stm32l4_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); @@ -906,12 +906,12 @@ static void stm32l4_dmamux_sample(DMA_MUX dmamux, uint8_t chan, #endif /**************************************************************************** - * Name: stm32l4_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32l4_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32l4_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08" PRIx32 "]: %08" PRIx32 "\n", @@ -987,7 +987,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32l4_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1011,7 +1011,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1033,7 +1033,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32l4_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1077,13 +1077,13 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32l4_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32l4_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1095,7 +1095,7 @@ DMA_HANDLE stm32l4_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32l4_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1121,14 +1121,14 @@ void stm32l4_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1145,18 +1145,18 @@ void stm32l4_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32l4_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1194,19 +1194,19 @@ void stm32l4_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32l4_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32l4_dmastop() is called, the DMA channel is - * reset and stm32l4_dmasetup() must be called before stm32l4_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32l4_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1235,17 +1235,17 @@ void stm32l4_dmastop(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32l4_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1261,7 +1261,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32l4_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1278,7 +1278,7 @@ size_t stm32l4_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32L4_DMACAPABLE -bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1354,18 +1354,18 @@ bool stm32l4_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32l4_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1382,18 +1382,18 @@ void stm32l4_dmasample(DMA_HANDLE handle, struct stm32l4_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32l4_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32l4_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32l4_dmadump(DMA_HANDLE handle, const struct stm32l4_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 607f2e9cc1b..c6a08bed6d2 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -646,7 +646,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32l4_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -656,7 +656,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -static void stm32l4_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -746,7 +746,7 @@ static void stm32l4_stdclockconfig(void) } #else -# error stm32l4_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -951,7 +951,7 @@ static void stm32l4_stdclockconfig(void) #if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -967,7 +967,7 @@ static void stm32l4_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l4_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -997,7 +997,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32l4_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h index 831f891cc5a..9d7cd5733aa 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h @@ -133,7 +133,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -142,11 +142,11 @@ ****************************************************************************/ #if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) -int stm32l4_bringup(void); +int stm32_bringup(void); #endif /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -156,7 +156,7 @@ int stm32l4_bringup(void); #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ defined(CONFIG_STM32L4_SPI3) -void weak_function stm32l4_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif /**************************************************************************** @@ -175,11 +175,11 @@ void weak_function stm32l4_spidev_initialize(void); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void); +int stm32_timer_driver_setup(void); #endif /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -191,7 +191,7 @@ int stm32l4_timer_driver_setup(void); ****************************************************************************/ #ifdef HAVE_SPSGRF -int stm32l4_spirit_initialize(void); +int stm32_spirit_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c index 065c7aca0d0..269354efbc1 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_autoleds.c @@ -73,7 +73,7 @@ void board_autoled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED2); } /**************************************************************************** @@ -84,7 +84,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); } } @@ -96,7 +96,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); } } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index 27bca5f9bae..c49b58bebb5 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -38,7 +38,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -48,17 +48,17 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) /* Configure SPI chip selects if * 1) SPI is not disabled, and 2) the weak function - * stm32l4_spidev_initialize() has been brought into the link. + * stm32_spidev_initialize() has been brought into the link. */ - if (stm32l4_spidev_initialize) + if (stm32_spidev_initialize) { - stm32l4_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -88,6 +88,6 @@ void board_late_initialize(void) { /* Perform board initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c index cdbb58f24fb..838b4349ff6 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_bringup.c @@ -49,7 +49,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * This function initializes and configures all on-board features @@ -57,7 +57,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; @@ -95,10 +95,10 @@ int stm32l4_bringup(void) struct qspi_dev_s *g_qspi; struct mtd_dev_s *g_mtd_fs; - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (g_qspi == NULL) { - syslog(LOG_ERR, "ERROR: stm32l4_qspi_initialize failed\n"); + syslog(LOG_ERR, "ERROR: stm32_qspi_initialize failed\n"); return -EIO; } @@ -222,10 +222,10 @@ process_next_part: #ifdef HAVE_SPSGRF /* Configure Spirit/SPSGRF wireless */ - ret = stm32l4_spirit_initialize(); + ret = stm32_spirit_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_spirit_initialize() failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_spirit_initialize() failed: %d\n", ret); } #endif @@ -233,7 +233,7 @@ process_next_part: #ifdef CONFIG_TIMER /* Register timer drivers */ - ret = stm32l4_timer_driver_setup(); + ret = stm32_timer_driver_setup(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index d3a2d3b320e..789daee3080 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -79,7 +79,7 @@ struct spi_dev_s *g_spi3; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-F401RE and @@ -87,12 +87,12 @@ struct spi_dev_s *g_spi3; * ****************************************************************************/ -void weak_function stm32l4_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { #ifdef CONFIG_STM32L4_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -104,7 +104,7 @@ void weak_function stm32l4_spidev_initialize(void) #ifdef CONFIG_STM32L4_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); /* Configure chip select GPIOs */ #endif @@ -112,30 +112,30 @@ void weak_function stm32l4_spidev_initialize(void) #ifdef CONFIG_STM32L4_SPI3 /* Configure SPI-based devices */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); /* Configure chip select GPIOs */ #ifdef HAVE_SPSGRF - stm32l4_configgpio(GPIO_SPSGRF_CS); + stm32_configgpio(GPIO_SPSGRF_CS); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. * They are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by * common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -149,35 +149,35 @@ void weak_function stm32l4_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -186,19 +186,19 @@ void stm32l4_spi3select(struct spi_dev_s *dev, #ifdef HAVE_SPSGRF if (devid == SPIDEV_WIRELESS(0)) { - stm32l4_gpiowrite(GPIO_SPSGRF_CS, !selected); + stm32_gpiowrite(GPIO_SPSGRF_CS, !selected); } #endif } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -222,21 +222,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c index 0adaebb0c18..9a471bd9f0c 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spirit.c @@ -59,7 +59,7 @@ * Private Types ****************************************************************************/ -struct stm32l4_priv_s +struct stm32_priv_s { struct spirit_lower_s dev; xcpt_t handler; @@ -77,18 +77,18 @@ struct stm32l4_priv_s * to isolate the Spirit driver from differences in GPIO interrupt handling * varying boards and MCUs. * - * stm32l4_reset - Reset the Spirit part. - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_reset - Reset the Spirit part. + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_reset(const struct spirit_lower_s *lower); -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_reset(const struct spirit_lower_s *lower); +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg); -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state); -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); +static int stm32_spirit_devsetup(struct stm32_priv_s *priv); /**************************************************************************** * Private Data @@ -104,11 +104,11 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv); * may modify frequency or X plate resistance values. */ -static struct stm32l4_priv_s g_spirit = +static struct stm32_priv_s g_spirit = { - .dev.reset = stm32l4_reset, - .dev.attach = stm32l4_attach_irq, - .dev.enable = stm32l4_enable_irq, + .dev.reset = stm32_reset, + .dev.attach = stm32_attach_irq, + .dev.enable = stm32_enable_irq, .handler = NULL, .arg = NULL, .intcfg = GPIO_SPSGRF_INT, @@ -122,16 +122,16 @@ static struct stm32l4_priv_s g_spirit = /* Reset the Spirit 1 part */ -static int stm32l4_reset(const struct spirit_lower_s *lower) +static int stm32_reset(const struct spirit_lower_s *lower) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); /* Reset pulse */ - stm32l4_gpiowrite(priv->sdncfg, true); - stm32l4_gpiowrite(priv->sdncfg, false); + stm32_gpiowrite(priv->sdncfg, true); + stm32_gpiowrite(priv->sdncfg, false); /* Wait minimum 1.5 ms to allow Spirit a proper boot-up sequence */ @@ -145,15 +145,15 @@ static int stm32l4_reset(const struct spirit_lower_s *lower) * interrupts should be configured on both rising and falling edges * so that contact and loss-of-contact events can be detected. * - * stm32l4_attach_irq - Attach the Spirit interrupt handler to the GPIO + * stm32_attach_irq - Attach the Spirit interrupt handler to the GPIO * interrupt - * stm32l4_enable_irq - Enable or disable the GPIO interrupt + * stm32_enable_irq - Enable or disable the GPIO interrupt */ -static int stm32l4_attach_irq(const struct spirit_lower_s *lower, +static int stm32_attach_irq(const struct spirit_lower_s *lower, xcpt_t handler, void *arg) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; DEBUGASSERT(priv != NULL); @@ -164,10 +164,10 @@ static int stm32l4_attach_irq(const struct spirit_lower_s *lower, return OK; } -static void stm32l4_enable_irq(const struct spirit_lower_s *lower, +static void stm32_enable_irq(const struct spirit_lower_s *lower, bool state) { - struct stm32l4_priv_s *priv = (struct stm32l4_priv_s *)lower; + struct stm32_priv_s *priv = (struct stm32_priv_s *)lower; /* The caller should not attempt to enable interrupts if the handler * has not yet been 'attached' @@ -183,20 +183,20 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, { /* Enable interrupts on falling edge (active low) */ - stm32l4_gpiosetevent(priv->intcfg, false, true, false, + stm32_gpiosetevent(priv->intcfg, false, true, false, priv->handler, priv->arg); } else { /* Disable interrupts */ - stm32l4_gpiosetevent(priv->intcfg, false, false, false, + stm32_gpiosetevent(priv->intcfg, false, false, false, NULL, NULL); } } /**************************************************************************** - * Name: stm32l4_spirit_devsetup + * Name: stm32_spirit_devsetup * * Description: * Initialize one the Spirit device @@ -207,7 +207,7 @@ static void stm32l4_enable_irq(const struct spirit_lower_s *lower, * ****************************************************************************/ -static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) +static int stm32_spirit_devsetup(struct stm32_priv_s *priv) { struct spi_dev_s *spi; int ret; @@ -216,12 +216,12 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * powers down the Spirit. */ - stm32l4_configgpio(priv->intcfg); - stm32l4_configgpio(priv->sdncfg); + stm32_configgpio(priv->intcfg); + stm32_configgpio(priv->sdncfg); /* Initialize the SPI bus and get an instance of the SPI interface */ - spi = stm32l4_spibus_initialize(priv->spidev); + spi = stm32_spibus_initialize(priv->spidev); if (spi == NULL) { wlerr("ERROR: Failed to initialize SPI bus %d\n", priv->spidev); @@ -245,7 +245,7 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spirit_initialize + * Name: stm32_spirit_initialize * * Description: * Initialize the Spirit device. @@ -256,13 +256,13 @@ static int stm32l4_spirit_devsetup(struct stm32l4_priv_s *priv) * ****************************************************************************/ -int stm32l4_spirit_initialize(void) +int stm32_spirit_initialize(void) { int ret; wlinfo("Configuring Spirit\n"); - ret = stm32l4_spirit_devsetup(&g_spirit); + ret = stm32_spirit_devsetup(&g_spirit); if (ret < 0) { wlerr("ERROR: Failed to initialize Spirit: %d\n", ret); diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 36ef0fddd93..119d3f6c57f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -52,12 +52,12 @@ ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l4_timer_driver_setup(void) +int stm32_timer_driver_setup(void) { int ret = OK; #ifdef CONFIG_STM32L4_TIM1 - ret = stm32l4_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM1 at /dev/timer0: %d\n", @@ -66,7 +66,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM2 - ret = stm32l4_timer_initialize("/dev/timer1", 2); + ret = stm32_timer_initialize("/dev/timer1", 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer1: %d\n", @@ -75,7 +75,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM3 - ret = stm32l4_timer_initialize("/dev/timer2", 3); + ret = stm32_timer_initialize("/dev/timer2", 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM3 at /dev/timer2: %d\n", @@ -84,7 +84,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM4 - ret = stm32l4_timer_initialize("/dev/timer3", 4); + ret = stm32_timer_initialize("/dev/timer3", 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM2 at /dev/timer3: %d\n", @@ -93,7 +93,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM5 - ret = stm32l4_timer_initialize("/dev/timer4", 5); + ret = stm32_timer_initialize("/dev/timer4", 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM5 at /dev/timer4: %d\n", @@ -102,7 +102,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM6 - ret = stm32l4_timer_initialize("/dev/timer5", 6); + ret = stm32_timer_initialize("/dev/timer5", 6); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM6 at /dev/timer5: %d\n", @@ -111,7 +111,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM7 - ret = stm32l4_timer_initialize("/dev/timer6", 7); + ret = stm32_timer_initialize("/dev/timer6", 7); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM7 at /dev/timer6: %d\n", @@ -120,7 +120,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM8 - ret = stm32l4_timer_initialize("/dev/timer7", 8); + ret = stm32_timer_initialize("/dev/timer7", 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM8 at /dev/timer7: %d\n", @@ -129,7 +129,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM15 - ret = stm32l4_timer_initialize("/dev/timer8", 15); + ret = stm32_timer_initialize("/dev/timer8", 15); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM15 at /dev/time8: %d\n", @@ -138,7 +138,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM16 - ret = stm32l4_timer_initialize("/dev/timer9", 16); + ret = stm32_timer_initialize("/dev/timer9", 16); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM16 at /dev/time9: %d\n", @@ -147,7 +147,7 @@ int stm32l4_timer_driver_setup(void) #endif #ifdef CONFIG_STM32L4_TIM17 - ret = stm32l4_timer_initialize("/dev/timer10", 17); + ret = stm32_timer_initialize("/dev/timer10", 17); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to setup TIM17 at /dev/time10: %d\n", diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c index e431ebdcee9..d4bf80c9c5f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_userleds.c @@ -46,8 +46,8 @@ uint32_t board_userled_initialize(void) { /* Configure LED gpio as output */ - stm32l4_configgpio(GPIO_LED1); - stm32l4_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); return BOARD_NLEDS; } @@ -59,11 +59,11 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LED1) { - stm32l4_gpiowrite(GPIO_LED1, ledon); + stm32_gpiowrite(GPIO_LED1, ledon); } else if (led == BOARD_LED2) { - stm32l4_gpiowrite(GPIO_LED2, ledon); + stm32_gpiowrite(GPIO_LED2, ledon); } } @@ -73,8 +73,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); - stm32l4_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); + stm32_gpiowrite(GPIO_LED1, !!(ledset & BOARD_LED1_BIT)); + stm32_gpiowrite(GPIO_LED2, !!(ledset & BOARD_LED2_BIT)); } #endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index 8b8519497ca..a639e4fc63b 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -294,7 +294,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -304,7 +304,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h index b9f111e886a..03bc8bc6c09 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h @@ -133,7 +133,7 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -141,11 +141,11 @@ int stm32_bringup(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of initialized @@ -153,30 +153,30 @@ int stm32l4_gpio_initialize(void); * ****************************************************************************/ -void stm32l4_spiregister(void); +void stm32_spiregister(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -184,11 +184,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -196,11 +196,11 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. @@ -208,7 +208,7 @@ int stm32l4_adc_setup(void); ****************************************************************************/ #ifdef CONFIG_DAC -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); #endif /**************************************************************************** @@ -284,7 +284,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -292,7 +292,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif #endif /* __BOARDS_ARM_STM32L4_NUCLEO_L432KC_SRC_NUCLEO_L432KC_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c index e7663aef961..e3cb1ffeec3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c @@ -98,14 +98,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -115,12 +115,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c index 9accb5984f0..60218b2de0c 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c @@ -79,7 +79,7 @@ int stm32_at45dbinitialize(int minor) finfo("INFO: Initializing AT45DB\n"); - spi = stm32l4_spibus_initialize(AT45DB_SPI_PORT); + spi = stm32_spibus_initialize(AT45DB_SPI_PORT); if (spi == NULL) { ferr("ERROR: Failed to initialize SPI port %d\n", AT45DB_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c index 1631395cab7..c2f3cff13fb 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, true); + stm32_gpiowrite(GPIO_LD3, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD3, false); + stm32_gpiowrite(GPIO_LD3, false); } } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c index 1241ab202ff..d8416cda87b 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c @@ -50,7 +50,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -60,7 +60,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -69,21 +69,21 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ defined(CONFIG_STM32L4_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c index d8dead5bc11..a5c437d9652 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c @@ -40,7 +40,7 @@ #include #include -#include +#include #include #include @@ -119,7 +119,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -130,7 +130,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -154,7 +154,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_I2C1 /* Get the I2C lower half instance */ - i2c1 = stm32l4_i2cbus_initialize(1); + i2c1 = stm32_i2cbus_initialize(1); if (i2c1 == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -174,7 +174,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_I2C3 /* Get the I2C lower half instance */ - i2c3 = stm32l4_i2cbus_initialize(3); + i2c3 = stm32_i2cbus_initialize(3); if (i2c3 == NULL) { i2cerr("ERROR: Initialize I2C3: %d\n", ret); @@ -192,7 +192,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SPI_DRIVER - stm32l4_spiregister(); + stm32_spiregister(); /* If called it during board_init, * registering failed due to heap doesn't be initialized yet. */ @@ -213,30 +213,30 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif #ifdef CONFIG_STM32L4_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif #ifdef CONFIG_STM32L4_DAC /* Initialize DAC and register the DAC driver. */ - ret = stm32l4_dac_setup(); + ret = stm32_dac_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_dac_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_dac_setup failed: %d\n", ret); } #endif @@ -300,7 +300,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -311,7 +311,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -322,7 +322,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -333,7 +333,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -344,7 +344,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -355,7 +355,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c index 4e57f555eb2..21d0208c7cd 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c @@ -50,10 +50,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -62,7 +62,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32L4_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c index a62e824fbc0..8b241b1398e 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ defined(CONFIG_DAC7571) @@ -80,12 +80,12 @@ int stm32_dac7571initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -110,7 +110,7 @@ int stm32_dac7571initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c index 32d73de7783..a98c0f1e492 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c @@ -104,7 +104,7 @@ struct dac_wgen_s static struct dac_wgen_s g_dac_wgen = { .dac = NULL, - .dac_dmabuffer = stm32l4_dac1_dmabuffer, + .dac_dmabuffer = stm32_dac1_dmabuffer, .samples = CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES, .waveform_freq = ((float)CONFIG_NUCLEOL432KC_DAC_WGEN_FREQ) }; @@ -199,7 +199,7 @@ int dac_wgen_setup(struct dac_wgen_s *dac_wgen) int ret = OK; - dac = stm32l4_dacinitialize(0); + dac = stm32_dacinitialize(0); if (dac == NULL) { syslog(LOG_ERR, "Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c index 6b762ea2186..9164fd1db31 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_gpio.c @@ -151,7 +151,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } #endif @@ -165,7 +165,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -177,7 +177,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } #endif @@ -205,7 +205,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -219,7 +219,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -240,7 +240,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -248,7 +248,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) else { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -268,7 +268,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int i; int pincount = 0; @@ -285,7 +285,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -303,8 +303,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -322,7 +322,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c index 7a0ca30e193..bb07eb99530 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ defined(CONFIG_SENSORS_INA219) @@ -84,12 +84,12 @@ int stm32_ina219initialize(const char *devpath) /* Configure D4(PA5) and D5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_D4); - stm32l4_configgpio(GPIO_I2C1_D5); + stm32_configgpio(GPIO_I2C1_D4); + stm32_configgpio(GPIO_I2C1_D5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina219initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c index cfa9af0ae10..cd4a2e747da 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ defined(CONFIG_SENSORS_INA226) @@ -84,12 +84,12 @@ int stm32_ina226initialize(const char *devpath) /* Configure A4(PA5) and A5(PA6) as input floating */ - stm32l4_configgpio(GPIO_I2C1_A4); - stm32l4_configgpio(GPIO_I2C1_A5); + stm32_configgpio(GPIO_I2C1_A4); + stm32_configgpio(GPIO_I2C1_A5); /* Get an instance of the I2C1 interface */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (!i2c) { return -ENODEV; @@ -114,7 +114,7 @@ int stm32_ina226initialize(const char *devpath) return OK; error: - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c index fedfb033508..95dc42e521a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM interface + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ /* PWM @@ -88,7 +88,7 @@ int stm32l4_pwm_setup(void) */ #if defined(CONFIG_STM32L4_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -106,7 +106,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -124,7 +124,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -142,7 +142,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -160,7 +160,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -178,7 +178,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c index 1a02e18bb8c..311955dee90 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index 421a2497b2c..06b202c9581 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l432kc.h" @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiregister + * Name: stm32_spiregister * * Description: * Called to register spi character driver of @@ -68,7 +68,7 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void stm32l4_spiregister(void) +void stm32_spiregister(void) { #ifdef CONFIG_STM32L4_SPI1 int ret = spi_register(g_spi1, 1); @@ -88,7 +88,7 @@ void stm32l4_spiregister(void) } /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L432KC @@ -96,12 +96,12 @@ void stm32l4_spiregister(void) * ****************************************************************************/ -void stm32l4_spiinitialize(void) +void stm32_spiinitialize(void) { #ifdef CONFIG_STM32L4_SPI1 /* Configure SPI1-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -114,14 +114,14 @@ void stm32l4_spiinitialize(void) /* Setup CS, EN & IRQ line IOs */ #ifdef CONFIG_MTD_AT45DB - stm32l4_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ + stm32_configgpio(AT45DB_SPI1_CS); /* FLASH chip select */ #endif #endif #ifdef CONFIG_STM32L4_SPI2 /* Configure SPI2-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 2\n"); @@ -136,19 +136,19 @@ void stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2select and stm32l4_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32l4_spi1/2select and stm32l4_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including * up_spiinitialize()) are provided by common STM32 logic. To use this * common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2select() and stm32l4_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. @@ -162,7 +162,7 @@ void stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %08X CS: %s\n", (int)devid, @@ -171,33 +171,33 @@ void stm32l4_spi1select(struct spi_dev_s *dev, uint32_t devid, #ifdef CONFIG_MTD_AT45DB if (devid == SPIDEV_FLASH(0)) { - stm32l4_gpiowrite(AT45DB_SPI1_CS, !selected); + stm32_gpiowrite(AT45DB_SPI1_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -221,14 +221,14 @@ uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index ad672643696..48ce28fe0b6 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -138,9 +138,9 @@ struct spwm_s { - struct stm32l4_pwm_dev_s *pwm; + struct stm32_pwm_dev_s *pwm; #ifdef CONFIG_NUCLEOL432KC_SPWM_USE_TIM1 - struct stm32l4_tim_dev_s *tim; + struct stm32_tim_dev_s *tim; #endif float waveform[SAMPLES_NUM]; /* Waveform samples */ float phase_step; /* Waveform phase step */ @@ -314,8 +314,8 @@ static int spwm_stop(struct spwm_s *spwm) static void tim6_handler(void) { struct spwm_s *spwm = &g_spwm; - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_pwm_dev_s *pwm = spwm->pwm; + struct stm32_tim_dev_s *tim = spwm->tim; uint8_t i = 0; for (i = 0; i < spwm->phases; i += 1) @@ -345,13 +345,13 @@ static void tim6_handler(void) static int spwm_tim6_setup(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = NULL; + struct stm32_tim_dev_s *tim = NULL; uint64_t freq = 0; int ret = OK; /* Get TIM6 interface */ - tim = stm32l4_tim_init(6); + tim = stm32_tim_init(6); if (tim == NULL) { printf("ERROR: Failed to get TIM6 interface\n"); @@ -403,7 +403,7 @@ errout: static int spwm_tim6_start(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Enable the timer interrupt at the NVIC and at TIM6 */ @@ -419,7 +419,7 @@ static int spwm_tim6_start(struct spwm_s *spwm) static int spwm_tim6_stop(struct spwm_s *spwm) { - struct stm32l4_tim_dev_s *tim = spwm->tim; + struct stm32_tim_dev_s *tim = spwm->tim; /* Disable the timer interrupt at the NVIC and at TIM6 */ @@ -435,12 +435,12 @@ static int spwm_tim6_stop(struct spwm_s *spwm) static int spwm_tim1_setup(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = NULL; + struct stm32_pwm_dev_s *pwm = NULL; int ret = OK; /* Get TIM1 PWM interface */ - pwm = (struct stm32l4_pwm_dev_s *)stm32l4_pwminitialize(1); + pwm = (struct stm32_pwm_dev_s *)stm32_pwminitialize(1); if (pwm == NULL) { printf("ERROR: Failed to get TIM1 PWM interface\n"); @@ -486,7 +486,7 @@ errout: static int spwm_tim1_start(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; @@ -514,7 +514,7 @@ static int spwm_tim1_start(struct spwm_s *spwm) static int spwm_tim1_stop(struct spwm_s *spwm) { - struct stm32l4_pwm_dev_s *pwm = spwm->pwm; + struct stm32_pwm_dev_s *pwm = spwm->pwm; uint16_t outputs = 0; int i = 0; diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c index d0b9d26524b..8d7ac77627f 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c index bf21e6c4ea1..848add8c3b7 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c index c80bd6b7004..8009c8346e5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l432kc.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD3 GPIO for output */ - stm32l4_configgpio(GPIO_LD3); + stm32_configgpio(GPIO_LD3); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD3) { - stm32l4_gpiowrite(GPIO_LD3, ledon); + stm32_gpiowrite(GPIO_LD3, ledon); } } @@ -176,7 +176,7 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); + stm32_gpiowrite(GPIO_LD3, (ledset & BOARD_LD3_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c index f717e304965..010e9af5d50 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_zerocross.c @@ -98,7 +98,7 @@ static void zcross_enable(const struct zc_lowerhalf_s *lower, g_zcrossarg = arg; } - stm32l4_gpiosetevent(GPIO_ZEROCROSS, rising, falling, + stm32_gpiosetevent(GPIO_ZEROCROSS, rising, falling, true, zcross_interrupt, NULL); leave_critical_section(flags); @@ -120,7 +120,7 @@ static void zcross_disable(void) flags = enter_critical_section(); - stm32l4_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); + stm32_gpiosetevent(GPIO_ZEROCROSS, false, false, false, NULL, NULL); leave_critical_section(flags); @@ -164,10 +164,10 @@ static int zcross_interrupt(int irq, void *context, void *arg) int stm32_zerocross_initialize(void) { /* Configure the GPIO pin as input. NOTE: This is unnecessary for - * interrupting pins since it will also be done by stm32l4_gpiosetevent(). + * interrupting pins since it will also be done by stm32_gpiosetevent(). */ - stm32l4_configgpio(GPIO_ZEROCROSS); + stm32_configgpio(GPIO_ZEROCROSS); /* Make sure that all interrupts are disabled */ diff --git a/boards/arm/stm32l4/nucleo-l452re/include/board.h b/boards/arm/stm32l4/nucleo-l452re/include/board.h index f4bf2ebf864..a557ca31a3d 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/board.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/board.h @@ -257,7 +257,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -267,7 +267,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index 08cecef4150..c740f7bd1f7 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -118,36 +118,36 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_bringup diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c index 2cd9d75fb25..943ed50997a 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c @@ -147,14 +147,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct file filestruct; @@ -277,10 +277,10 @@ out: } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; @@ -296,15 +296,15 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c index 86102cae00a..3abec894bc5 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_autoleds.c @@ -53,7 +53,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -64,7 +64,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -76,7 +76,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c index 94bf0983a8c..0031ce09d05 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_boot.c @@ -40,7 +40,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -50,7 +50,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c index 31eac2e1376..cfb99ae3d6d 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c @@ -102,7 +102,7 @@ int stm32_bringup(void) #ifdef HAVE_I2C_DRIVER /* Get the I2C lower half instance */ - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { i2cerr("ERROR: Initialize I2C1: %d\n", ret); @@ -122,13 +122,13 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); + stm32_adc_setup(); #endif UNUSED(ret); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c index 261d03e6f29..18ea50c5ace 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -75,7 +75,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -108,7 +108,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c index 09b56bc5ff4..204594da235 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c @@ -48,10 +48,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -60,7 +60,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32L4_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index 4c43919bd20..ef717f106eb 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -34,7 +34,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l452re.h" @@ -60,33 +60,33 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { #ifdef CONFIG_STM32L4_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif #ifdef CONFIG_STM32L4_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -95,19 +95,19 @@ void weak_function stm32l4_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -121,7 +121,7 @@ void weak_function stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -130,47 +130,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -194,21 +194,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c index 6911949d111..8344890d1ab 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_userleds.c @@ -155,7 +155,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -167,7 +167,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -177,15 +177,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h index adf24d58b9a..afd37181c06 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h @@ -293,27 +293,27 @@ extern struct sdio_dev_s *g_sdio; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32l4_spiinitialize(void); +void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio @@ -322,11 +322,11 @@ void stm32l4_usbinitialize(void); ****************************************************************************/ #ifdef CONFIG_DEV_GPIO -int stm32l4_gpio_initialize(void); +int stm32_gpio_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_can_setup -- DisruptiveNL + * Name: stm32_can_setup -- DisruptiveNL * * Description: * Initialize CAN and register the CAN device. @@ -335,11 +335,11 @@ int stm32l4_gpio_initialize(void); ****************************************************************************/ #ifdef CONFIG_CAN -int stm32l4_can_setup(void); +int stm32_can_setup(void); #endif /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. @@ -347,11 +347,11 @@ int stm32l4_can_setup(void); ****************************************************************************/ #ifdef CONFIG_PWM -int stm32l4_pwm_setup(void); +int stm32_pwm_setup(void); #endif /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. @@ -359,7 +359,7 @@ int stm32l4_pwm_setup(void); ****************************************************************************/ #ifdef CONFIG_ADC -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); #endif /**************************************************************************** @@ -375,7 +375,7 @@ int board_ajoy_initialize(void); #endif /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initializes SPI-based SD card @@ -383,7 +383,7 @@ int board_ajoy_initialize(void); ****************************************************************************/ #ifdef CONFIG_MMCSD_SPI -int stm32l4_mmcsd_initialize(int minor); +int stm32_mmcsd_initialize(int minor); #endif /**************************************************************************** @@ -399,7 +399,7 @@ int board_timer_driver_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_qencoder_initialize + * Name: stm32_qencoder_initialize * * Description: * Initialize and register a qencoder @@ -407,11 +407,11 @@ int board_timer_driver_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_SENSORS_QENCODER -int stm32l4_qencoder_initialize(const char *devpath, int timer); +int stm32_qencoder_initialize(const char *devpath, int timer); #endif /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver @@ -419,7 +419,7 @@ int stm32l4_qencoder_initialize(const char *devpath, int timer); ****************************************************************************/ #ifdef CONFIG_WL_CC1101 -int stm32l4_cc1101_initialize(void); +int stm32_cc1101_initialize(void); #endif /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 4fc545de40e..33a7c5f05f8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -103,14 +103,14 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { struct adc_dev_s *adc; int ret; @@ -120,12 +120,12 @@ int stm32l4_adc_setup(void) for (i = 0; i < ADC1_NCHANNELS; i++) { - stm32l4_configgpio(g_adc1_pinlist[i]); + stm32_configgpio(g_adc1_pinlist[i]); } - /* Call stm32l4_adc_initialize() to get an instance of the ADC interface */ + /* Call stm32_adc_initialize() to get an instance of the ADC interface */ - adc = stm32l4_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index 4b1f6a776a1..e83a6e23d77 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -298,7 +298,7 @@ ajoy_buttons(const struct ajoy_lowerhalf_s *lower) * button is pressed. */ - if (!stm32l4_gpioread(g_joygpio[i])) + if (!stm32_gpioread(g_joygpio[i])) { ret |= (1 << i); } @@ -368,7 +368,7 @@ static void ajoy_enable(const struct ajoy_lowerhalf_s *lower, iinfo("GPIO %d: rising: %d falling: %d\n", i, rising, falling); - stm32l4_gpiosetevent(g_joygpio[i], rising, falling, + stm32_gpiosetevent(g_joygpio[i], rising, falling, true, ajoy_interrupt, NULL); } } @@ -395,7 +395,7 @@ static void ajoy_disable(void) flags = up_irq_save(); for (i = 0; i < AJOY_NGPIOS; i++) { - stm32l4_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); + stm32_gpiosetevent(g_joygpio[i], false, false, false, NULL, NULL); } up_irq_restore(flags); @@ -461,14 +461,14 @@ int board_ajoy_initialize(void) /* Configure the GPIO pins as interrupting inputs. NOTE: This is * unnecessary for interrupting pins since it will also be done by - * stm32l4_gpiosetevent(). + * stm32_gpiosetevent(). */ for (i = 0; i < AJOY_NGPIOS; i++) { /* Configure the PIO as an input */ - stm32l4_configgpio(g_joygpio[i]); + stm32_configgpio(g_joygpio[i]); } /* Register the joystick device as /dev/ajoy0 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c index 01913bd594e..12bb3c4aedc 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_as726x.c @@ -46,7 +46,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -83,7 +83,7 @@ int stm32_as726xinitialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(AS726X_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(AS726X_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c index b3af9c5a740..fd2c0f744c8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_ARCH_LEDS @@ -52,7 +52,7 @@ void board_autoled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); } /**************************************************************************** @@ -63,7 +63,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, true); + stm32_gpiowrite(GPIO_LD2, true); } } @@ -75,7 +75,7 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD2, false); + stm32_gpiowrite(GPIO_LD2, false); } } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c index d6fb3086228..208b8c59a33 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp180.c @@ -32,7 +32,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "nucleo-l476rg.h" @@ -65,7 +65,7 @@ int stm32_bmp180initialize(const char *devpath) /* Initialize I2C */ - i2c = stm32l4_i2cbus_initialize(BMP180_I2C_PORTNO); + i2c = stm32_i2cbus_initialize(BMP180_I2C_PORTNO); if (!i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c index b5f07c0a8f0..55b74b50d38 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_bmp280.h" @@ -89,7 +89,7 @@ int board_bmp280_initialize(int devno, int busno) /* Initialize BMP280 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index 4800e811aa0..1ec0b006d17 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -61,20 +61,20 @@ void stm32l4_board_initialize(void) #endif /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak - * function stm32l4_spiinitialize() has been brought into the link. + * function stm32_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c index 9864ec4040a..4b632d44f55 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c @@ -39,7 +39,7 @@ #include #include -#include +#include #include #include @@ -95,7 +95,7 @@ static void stm32_i2c_register(int bus) struct i2c_master_s *i2c; int ret; - i2c = stm32l4_i2cbus_initialize(bus); + i2c = stm32_i2cbus_initialize(bus); if (i2c == NULL) { syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); @@ -107,7 +107,7 @@ static void stm32_i2c_register(int bus) { syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - stm32l4_i2cbus_uninitialize(i2c); + stm32_i2cbus_uninitialize(i2c); } } } @@ -178,7 +178,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32L4 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -261,28 +261,28 @@ int stm32_bringup(void) #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ - ret = stm32l4_pwm_setup(); + ret = stm32_pwm_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_pwm_setup() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); } #endif #ifdef CONFIG_ADC /* Initialize ADC and register the ADC driver. */ - ret = stm32l4_adc_setup(); + ret = stm32_adc_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_adc_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } #endif #ifdef CONFIG_CAN - ret = stm32l4_can_setup(); + ret = stm32_can_setup(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_can_setup failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); return ret; } #endif @@ -290,7 +290,7 @@ int stm32_bringup(void) /* Initialize MMC and register the MMC driver. */ #ifdef HAVE_MMCSD_SPI - ret = stm32l4_mmcsd_initialize(MMCSD_MINOR); + ret = stm32_mmcsd_initialize(MMCSD_MINOR); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize SD slot %d: %d\n", ret); @@ -329,7 +329,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 1); + ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -340,7 +340,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 2); + ret = stm32_qencoder_initialize(buf, 2); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -351,7 +351,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 3); + ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -362,7 +362,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 4); + ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -373,7 +373,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 5); + ret = stm32_qencoder_initialize(buf, 5); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -384,7 +384,7 @@ int stm32_bringup(void) #ifdef CONFIG_STM32L4_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); - ret = stm32l4_qencoder_initialize(buf, 8); + ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the qencoder: %d\n", @@ -395,7 +395,7 @@ int stm32_bringup(void) #endif /* CONFIG_SENSORS_QENCODER */ #ifdef CONFIG_SENSORS_HTS221 - ret = stm32l4_hts221_initialize("/dev/hts221"); + ret = stm32_hts221_initialize("/dev/hts221"); if (ret < 0) { serr("ERROR: Failed to initialize HTC221 driver: %d\n", ret); @@ -403,7 +403,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM6DSL - ret = stm32l4_lsm6dsl_initialize("/dev/lsm6dsl0"); + ret = stm32_lsm6dsl_initialize("/dev/lsm6dsl0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM6DSL driver: %d\n", ret); @@ -411,7 +411,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_SENSORS_LSM303AGR - ret = stm32l4_lsm303agr_initialize("/dev/lsm303mag0"); + ret = stm32_lsm303agr_initialize("/dev/lsm303mag0"); if (ret < 0) { serr("ERROR: Failed to initialize LSM303AGR driver: %d\n", ret); @@ -419,7 +419,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = stm32l4_gpio_initialize(); + ret = stm32_gpio_initialize(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -430,10 +430,10 @@ int stm32_bringup(void) #ifdef CONFIG_WL_CC1101 /* Initialize and register the cc1101 radio */ - ret = stm32l4_cc1101_initialize(); + ret = stm32_cc1101_initialize(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32l4_cc1101_initialize failed: %d\n", + syslog(LOG_ERR, "ERROR: stm32_cc1101_initialize failed: %d\n", ret); return ret; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c index b44a8deaedc..efcfb4efe31 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_buttons.c @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -72,7 +72,7 @@ uint32_t board_buttons(void) * pressed. */ - bool released = stm32l4_gpioread(GPIO_BTN_USER); + bool released = stm32_gpioread(GPIO_BTN_USER); return !released; } @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c index 7a59c087c87..30bfae87ba1 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c @@ -56,22 +56,22 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_can_setup + * Name: stm32_can_setup * * Description: * Initialize CAN and register the CAN device * ****************************************************************************/ -int stm32l4_can_setup(void) +int stm32_can_setup(void) { #ifdef CONFIG_STM32L4_CAN1 struct can_dev_s *can; int ret; - /* Call stm32l4can_initialize() to get an instance of the CAN interface */ + /* Call stm32_caninitialize() to get an instance of the CAN interface */ - can = stm32l4can_initialize(CAN_PORT); + can = stm32_caninitialize(CAN_PORT); if (can == NULL) { canerr("ERROR: Failed to get CAN interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c index 6a29402d6df..c1bfb8febdb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_cc1101.c @@ -36,7 +36,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifdef CONFIG_WL_CC1101 @@ -54,7 +54,7 @@ static void cc1101_wait(struct cc1101_dev_s *dev, uint32_t pin) { - while (stm32l4_gpioread(pin) == true) + while (stm32_gpioread(pin) == true) { } } @@ -70,11 +70,11 @@ static void cc1101_irq(struct cc1101_dev_s *dev, bool enable) { if (enable) { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); + stm32_gpiosetevent(dev->isr_pin, false, true, true, cc1101_isr, dev); } else { - stm32l4_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); + stm32_gpiosetevent(dev->isr_pin, false, true, true, NULL, NULL); } } @@ -94,19 +94,19 @@ static void cc1101_pwr(struct cc1101_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_cc1101_initialize + * Name: stm32_cc1101_initialize * * Description: * Initialize and register the cc1101 radio driver * ****************************************************************************/ -int stm32l4_cc1101_initialize(void) +int stm32_cc1101_initialize(void) { struct spi_dev_s *spi = NULL; struct cc1101_dev_s *dev = NULL; - spi = stm32l4_spibus_initialize(CONFIG_CC1101_SPIDEV); + spi = stm32_spibus_initialize(CONFIG_CC1101_SPIDEV); if (spi == NULL) { ierr("ERROR: Failed to initialize SPI bus %d\n", CONFIG_CC1101_SPIDEV); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c index f772ef0a32b..473fc52a0b6 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_gpio.c @@ -40,7 +40,7 @@ #include "chip.h" -#include +#include #include "nucleo-l476rg.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -160,7 +160,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpioinputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); return OK; } @@ -173,7 +173,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = stm32l4_gpioread(g_gpiooutputs[stm32gpio->id]); + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); return OK; } @@ -186,7 +186,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - stm32l4_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); return OK; } @@ -199,7 +199,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = stm32l4_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); return OK; } @@ -213,7 +213,7 @@ static int gpint_attach(struct gpio_dev_s *dev, /* Make sure the interrupt is disabled */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); gpioinfo("Attach %p\n", callback); @@ -234,7 +234,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], true, false, false, stm32gpio_interrupt, &g_gpint[stm32gpint->stm32gpio.id]); } @@ -243,7 +243,7 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { gpioinfo("Disable the interrupt\n"); - stm32l4_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, false, false, NULL, NULL); } @@ -255,14 +255,14 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_gpio_initialize + * Name: stm32_gpio_initialize * * Description: * Initialize GPIO drivers for use with /apps/examples/gpio * ****************************************************************************/ -int stm32l4_gpio_initialize(void) +int stm32_gpio_initialize(void) { int pincount = 0; int i; @@ -279,7 +279,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as input */ - stm32l4_configgpio(g_gpioinputs[i]); + stm32_configgpio(g_gpioinputs[i]); pincount++; } @@ -297,8 +297,8 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as output */ - stm32l4_gpiowrite(g_gpiooutputs[i], 0); - stm32l4_configgpio(g_gpiooutputs[i]); + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); pincount++; } @@ -316,7 +316,7 @@ int stm32l4_gpio_initialize(void) /* Configure the pin that will be used as interrupt input */ - stm32l4_configgpio(g_gpiointinputs[i]); + stm32_configgpio(g_gpiointinputs[i]); pincount++; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c index 43b8d711a5c..ef81043b182 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -48,13 +48,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm303agr_initialize + * Name: stm32_lsm303agr_initialize * * Description: * Initialize I2C-based LSM303AGR. ****************************************************************************/ -int stm32l4_lsm303agr_initialize(char *devpath) +int stm32_lsm303agr_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; @@ -62,7 +62,7 @@ int stm32l4_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); #if defined(CONFIG_STM32L4_I2C1) - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c index df404b8147e..99de5344b06 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include #include @@ -48,13 +48,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_lsm6dsl_initialize + * Name: stm32_lsm6dsl_initialize * * Description: * Initialize I2C-based LSM6DSL. ****************************************************************************/ -int stm32l4_lsm6dsl_initialize(char *devpath) +int stm32_lsm6dsl_initialize(char *devpath) { struct i2c_master_s *i2c; int ret = OK; @@ -63,10 +63,10 @@ int stm32l4_lsm6dsl_initialize(char *devpath) /* Configure the GPIO interrupt */ - stm32l4_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ + stm32_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ #if defined(CONFIG_STM32L4_I2C1) - i2c = stm32l4_i2cbus_initialize(1); + i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c index cd5252a2003..3211666f237 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c @@ -33,7 +33,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_i2c.h" #include "stm32_mpu9250.h" @@ -94,7 +94,7 @@ int board_mpu9250_initialize(int devno, int busno) /* Initialize MPU9250 */ - i2c = stm32l4_i2cbus_initialize(busno); + i2c = stm32_i2cbus_initialize(busno); if (i2c) { /* Then try to register the IMU sensor in I2Cx */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c index eb9316cb51f..ab30d3c77a8 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pcd8544.c @@ -72,12 +72,12 @@ int board_lcd_initialize(void) { /* Configure the GPIO pins */ - stm32l4_configgpio(STM32_LCD_RST); - stm32l4_configgpio(STM32_LCD_CD); - stm32l4_gpiowrite(STM32_LCD_RST, 1); - stm32l4_gpiowrite(STM32_LCD_CD, 1); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_CD); + stm32_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_CD, 1); - g_spidev = stm32l4_spibus_initialize(LCD_SPI_PORTNO); + g_spidev = stm32_spibus_initialize(LCD_SPI_PORTNO); if (!g_spidev) { @@ -85,9 +85,9 @@ int board_lcd_initialize(void) return -ENODEV; } - stm32l4_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(10); - stm32l4_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index 231a62a88ff..b1ad17da3b2 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -60,14 +60,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_pwm_setup + * Name: stm32_pwm_setup * * Description: * Initialize PWM and register the PWM device. * ****************************************************************************/ -int stm32l4_pwm_setup(void) +int stm32_pwm_setup(void) { static bool initialized = false; struct pwm_lowerhalf_s *pwm; @@ -77,7 +77,7 @@ int stm32l4_pwm_setup(void) if (!initialized) { - /* Call stm32l4_pwminitialize() to get an instance of the PWM + /* Call stm32_pwminitialize() to get an instance of the PWM * interface */ @@ -89,7 +89,7 @@ int stm32l4_pwm_setup(void) */ #if defined(CONFIG_STM32L4_TIM1_PWM) - pwm = stm32l4_pwminitialize(1); + pwm = stm32_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -107,7 +107,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM2_PWM) - pwm = stm32l4_pwminitialize(2); + pwm = stm32_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -125,7 +125,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM3_PWM) - pwm = stm32l4_pwminitialize(3); + pwm = stm32_pwminitialize(3); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -143,7 +143,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM4_PWM) - pwm = stm32l4_pwminitialize(4); + pwm = stm32_pwminitialize(4); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -161,7 +161,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM5_PWM) - pwm = stm32l4_pwminitialize(5); + pwm = stm32_pwminitialize(5); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -179,7 +179,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM8_PWM) - pwm = stm32l4_pwminitialize(8); + pwm = stm32_pwminitialize(8); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -197,7 +197,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM15_PWM) - pwm = stm32l4_pwminitialize(15); + pwm = stm32_pwminitialize(15); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -215,7 +215,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM16_PWM) - pwm = stm32l4_pwminitialize(16); + pwm = stm32_pwminitialize(16); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -233,7 +233,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_TIM17_PWM) - pwm = stm32l4_pwminitialize(17); + pwm = stm32_pwminitialize(17); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -251,7 +251,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_LPTIM1_PWM) - pwm = stm32l4_lp_pwminitialize(1); + pwm = stm32_lp_pwminitialize(1); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); @@ -269,7 +269,7 @@ int stm32l4_pwm_setup(void) #endif #if defined(CONFIG_STM32L4_LPTIM2_PWM) - pwm = stm32l4_lp_pwminitialize(2); + pwm = stm32_lp_pwminitialize(2); if (!pwm) { aerr("ERROR: Failed to get the STM32L4 PWM lower half\n"); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c index 9e366385cf0..a87fc8c8916 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_qencoder.c @@ -50,17 +50,17 @@ * ****************************************************************************/ -int stm32l4_qencoder_initialize(const char *devpath, int timer) +int stm32_qencoder_initialize(const char *devpath, int timer) { int ret; /* Initialize a quadrature encoder interface. */ sninfo("Initializing the quadrature encoder using TIM%d\n", timer); - ret = stm32l4_qeinitialize(devpath, timer); + ret = stm32_qeinitialize(devpath, timer); if (ret < 0) { - snerr("ERROR: stm32l4_qeinitialize failed: %d\n", ret); + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); } return ret; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index a7877547415..39bbd5a6d59 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "nucleo-l476rg.h" @@ -60,7 +60,7 @@ struct spi_dev_s *g_spi2; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spiinitialize + * Name: stm32_spiinitialize * * Description: * Called to configure SPI chip select GPIO pins for the Nucleo-L476RG @@ -68,57 +68,57 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32l4_spiinitialize(void) +void weak_function stm32_spiinitialize(void) { #ifdef CONFIG_STM32L4_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); } #ifdef HAVE_MMCSD_SPI - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #ifdef CONFIG_LCD_PCD8544 - stm32l4_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ + stm32_configgpio(STM32_LCD_CS); /* PCD8544 chip select */ #endif #endif #ifdef CONFIG_STM32L4_SPI2 /* Configure SPI-based devices */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); #ifdef CONFIG_WL_CC1101 /* Setup CS, IRQ(gdo2) line IOs */ - stm32l4_configgpio(GPIO_CC1101_PWR); - stm32l4_configgpio(GPIO_CC1101_CS); - stm32l4_configgpio(GPIO_CC1101_GDO2); + stm32_configgpio(GPIO_CC1101_PWR); + stm32_configgpio(GPIO_CC1101_CS); + stm32_configgpio(GPIO_CC1101_GDO2); #endif #endif } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32l4_spi1/2/3select and - * stm32l4_spi1/2/3status must be provided by board-specific logic. They + * The external functions, stm32_spi1/2/3select and + * stm32_spi1/2/3status must be provided by board-specific logic. They * are implementations of the select and status methods of the SPI * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). * All other methods (including up_spiinitialize()) are provided by common * STM32 logic. To use this common SPI logic on your * board: * - * 1. Provide logic in stm32l4_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l4_spi1/2/3select() and stm32l4_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. @@ -132,7 +132,7 @@ void weak_function stm32l4_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -141,19 +141,19 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD_SPI if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) { - stm32l4_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { uint8_t status = 0; @@ -169,7 +169,7 @@ uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -178,33 +178,33 @@ void stm32l4_spi2select(struct spi_dev_s *dev, #ifdef CONFIG_WL_CC1101 if (devid == SPIDEV_WIRELESS(5)) { - stm32l4_gpiowrite(GPIO_CC1101_CS, !selected); + stm32_gpiowrite(GPIO_CC1101_CS, !selected); } #endif } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1cmddata + * Name: stm32_spi1cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -228,7 +228,7 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_PCD8544 if (devid == SPIDEV_DISPLAY(0)) @@ -237,7 +237,7 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - stm32l4_gpiowrite(STM32_LCD_CD, !cmd); + stm32_gpiowrite(STM32_LCD_CD, !cmd); return OK; } @@ -248,14 +248,14 @@ int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c index d41d00e3f60..a02484fbf5d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c @@ -33,7 +33,7 @@ #include #include -#include +#include #include "stm32l4_spi.h" /**************************************************************************** @@ -68,14 +68,14 @@ static const int SD_SLOT_NO = 0; /* There is only one SD slot */ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_spi1register + * Name: stm32_spi1register * * Description: * Registers media change callback * ****************************************************************************/ -int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg) { spiinfo("INFO: Registering spi1 device\n"); @@ -83,21 +83,21 @@ int stm32l4_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, } /**************************************************************************** - * Name: stm32l4_mmcsd_initialize + * Name: stm32_mmcsd_initialize * * Description: * Initialize SPI-based SD card and card detect thread. * ****************************************************************************/ -int stm32l4_mmcsd_initialize(int minor) +int stm32_mmcsd_initialize(int minor) { struct spi_dev_s *spi; int rv; mcinfo("INFO: Initializing mmcsd card\n"); - spi = stm32l4_spibus_initialize(SD_SPI_PORT); + spi = stm32_spibus_initialize(SD_SPI_PORT); if (spi == NULL) { mcerr("ERROR: Failed to initialize SPI port %d\n", SD_SPI_PORT); diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c index a0c347aea59..7ae7885ca8b 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_timer.c @@ -61,7 +61,7 @@ int board_timer_driver_initialize(const char *devpath, int timer) { - return stm32l4_timer_initialize(devpath, timer); + return stm32_timer_initialize(devpath, timer); } #endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c index 278b51f7c2a..15536f8784b 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c index 92c96b1dc00..34384cb9dc3 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "nucleo-l476rg.h" #ifndef CONFIG_ARCH_LEDS @@ -154,7 +154,7 @@ uint32_t board_userled_initialize(void) { /* Configure LD2 GPIO for output */ - stm32l4_configgpio(GPIO_LD2); + stm32_configgpio(GPIO_LD2); return BOARD_NLEDS; } @@ -166,7 +166,7 @@ void board_userled(int led, bool ledon) { if (led == BOARD_LD2) { - stm32l4_gpiowrite(GPIO_LD2, ledon); + stm32_gpiowrite(GPIO_LD2, ledon); } } @@ -176,15 +176,15 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); + stm32_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0); } /**************************************************************************** - * Name: stm32l4_led_pminitialize + * Name: stm32_led_pminitialize ****************************************************************************/ #ifdef CONFIG_PM -void stm32l4_led_pminitialize(void) +void stm32_led_pminitialize(void) { /* Register to receive power management callbacks */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 30d1bcd22eb..84cda5cbb59 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -655,7 +655,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -665,7 +665,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 0ad0e10887d..549d4d1e873 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -158,7 +158,7 @@ int stm32_adc_setup(void) { if (g_pinlist_adc1[i] != 0) { - stm32l4_configgpio(g_pinlist_adc1[i]); + stm32_configgpio(g_pinlist_adc1[i]); } } #endif @@ -168,7 +168,7 @@ int stm32_adc_setup(void) { if (g_pinlist_adc2[i] != 0) { - stm32l4_configgpio(g_pinlist_adc2[i]); + stm32_configgpio(g_pinlist_adc2[i]); } } #endif @@ -178,17 +178,17 @@ int stm32_adc_setup(void) { if (g_pinlist_adc3[i] != 0) { - stm32l4_configgpio(g_pinlist_adc3[i]); + stm32_configgpio(g_pinlist_adc3[i]); } } #endif - /* Call stm32l4_adc_initialize() to get an instance of the ADC + /* Call stm32_adc_initialize() to get an instance of the ADC * interface */ #ifdef CONFIG_STM32L4_ADC1 - adc = stm32l4_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); + adc = stm32_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC1 interface\n"); @@ -206,7 +206,7 @@ int stm32_adc_setup(void) #endif #ifdef CONFIG_STM32L4_ADC2 - adc = stm32l4_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); + adc = stm32_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC2 interface\n"); @@ -224,7 +224,7 @@ int stm32_adc_setup(void) #endif #ifdef CONFIG_STM32L4_ADC3 - adc = stm32l4_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); + adc = stm32_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); if (adc == NULL) { aerr("ERROR: Failed to get ADC3 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c index f0d57f250fe..1c728a838d8 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_autoleds.c @@ -61,7 +61,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l4_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -80,7 +80,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l4_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c index a195c97e019..9a0caa0d36f 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c @@ -46,7 +46,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. @@ -56,7 +56,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c index 06a09421d54..e3022335e3e 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c @@ -148,7 +148,7 @@ int stm32_bringup(void) /* Initialize the SDIO block driver */ - ret = stm32l4_sdio_initialize(); + ret = stm32_sdio_initialize(); if (ret != OK) { ferr("ERROR: Failed to initialize MMC/SD driver: %d\n", ret); @@ -162,16 +162,16 @@ int stm32_bringup(void) /* REVISIT: this is ugly! */ #if defined(CONFIG_STM32L4_I2C1) - i2c1 = stm32l4_i2cbus_initialize(1); + i2c1 = stm32_i2cbus_initialize(1); #endif #if defined(CONFIG_STM32L4_I2C2) - i2c2 = stm32l4_i2cbus_initialize(2); + i2c2 = stm32_i2cbus_initialize(2); #endif #if defined(CONFIG_STM32L4_I2C3) - i2c3 = stm32l4_i2cbus_initialize(3); + i2c3 = stm32_i2cbus_initialize(3); #endif #if defined(CONFIG_STM32L4_I2C4) - i2c4 = stm32l4_i2cbus_initialize(4); + i2c4 = stm32_i2cbus_initialize(4); #endif #ifdef CONFIG_I2C_DRIVER #if defined(CONFIG_STM32L4_I2C1) diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c index 02382651672..16d7a80a1cc 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_buttons.c @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - stm32l4_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -66,7 +66,7 @@ uint32_t board_button_initialize(void) uint32_t board_buttons(void) { - return stm32l4_gpioread(GPIO_BTN_USER) ? 1 : 0; + return stm32_gpioread(GPIO_BTN_USER) ? 1 : 0; } /**************************************************************************** @@ -98,7 +98,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l4_gpiosetevent(GPIO_BTN_USER, true, true, true, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c index 9a303be8f8c..42ff6951b54 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c @@ -66,7 +66,7 @@ int stm32_dac_setup(void) int ret; #ifdef CONFIG_STM32L4_DAC1 - g_dac1 = stm32l4_dacinitialize(0); + g_dac1 = stm32_dacinitialize(0); if (g_dac1 == NULL) { aerr("ERROR: Failed to get DAC1 interface\n"); @@ -82,7 +82,7 @@ int stm32_dac_setup(void) #endif #ifdef CONFIG_STM32L4_DAC2 - g_dac2 = stm32l4_dacinitialize(1); + g_dac2 = stm32_dacinitialize(1); if (g_dac2 == NULL) { aerr("ERROR: Failed to get DAC2 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c index 39751a7adad..9d0a6261495 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c @@ -89,7 +89,7 @@ int stm32_dfsdm_setup(void) */ #ifdef CONFIG_STM32L4_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -105,7 +105,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -121,7 +121,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -137,7 +137,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c index 30d768cbc0f..9a7df66b11e 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_sdio.c @@ -76,11 +76,11 @@ static bool g_sd_inserted; ****************************************************************************/ #ifdef HAVE_NCD -static int stm32l4_ncd_interrupt(int irq, void *context) +static int stm32_ncd_interrupt(int irq, void *context) { bool present; - present = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + present = !stm32_gpioread(GPIO_SDMMC1_NCD); if (g_sdio_dev && present != g_sd_inserted) { sdio_mediachange(g_sdio_dev, present); @@ -103,19 +103,19 @@ static int stm32l4_ncd_interrupt(int irq, void *context) * ****************************************************************************/ -int stm32l4_sdio_initialize(void) +int stm32_sdio_initialize(void) { int ret; #ifdef HAVE_NCD /* Configure the card detect GPIO */ - stm32l4_configgpio(GPIO_SDMMC1_NCD); + stm32_configgpio(GPIO_SDMMC1_NCD); /* Register an interrupt handler for the card detect pin */ - stm32l4_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, - stm32l4_ncd_interrupt, NULL); + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, + stm32_ncd_interrupt, NULL); #endif /* Mount the SDIO-based MMC/SD block driver */ @@ -147,7 +147,7 @@ int stm32l4_sdio_initialize(void) #ifdef HAVE_NCD /* Use SD card detect pin to check if a card is g_sd_inserted */ - g_sd_inserted = !stm32l4_gpioread(GPIO_SDMMC1_NCD); + g_sd_inserted = !stm32_gpioread(GPIO_SDMMC1_NCD); finfo("Card detect : %d\n", g_sd_inserted); sdio_mediachange(g_sdio_dev, g_sd_inserted); diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 5dc14e26e14..2e0d5f1fc03 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi1gpio[i] != 0) { - stm32l4_configgpio(g_spi1gpio[i]); + stm32_configgpio(g_spi1gpio[i]); } } #endif @@ -216,7 +216,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi2gpio[i] != 0) { - stm32l4_configgpio(g_spi2gpio[i]); + stm32_configgpio(g_spi2gpio[i]); } } #endif @@ -226,7 +226,7 @@ void weak_function stm32_spidev_initialize(void) { if (g_spi3gpio[i] != 0) { - stm32l4_configgpio(g_spi3gpio[i]); + stm32_configgpio(g_spi3gpio[i]); } } #endif @@ -269,7 +269,7 @@ void stm32_spi1select(struct spi_dev_s *dev, if (g_spi1gpio[index] != 0) { - stm32l4_gpiowrite(g_spi1gpio[index], !selected); + stm32_gpiowrite(g_spi1gpio[index], !selected); } } @@ -290,7 +290,7 @@ void stm32_spi2select(struct spi_dev_s *dev, if (g_spi2gpio[index] != 0) { - stm32l4_gpiowrite(g_spi2gpio[index], !selected); + stm32_gpiowrite(g_spi2gpio[index], !selected); } } @@ -311,7 +311,7 @@ void stm32_spi3select(struct spi_dev_s *dev, if (g_spi3gpio[index] != 0) { - stm32l4_gpiowrite(g_spi3gpio[index], !selected); + stm32_gpiowrite(g_spi3gpio[index], !selected); } } @@ -393,7 +393,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) - spi2 = stm32l4_spibus_initialize(2); + spi2 = stm32_spibus_initialize(2); if (!spi2) { @@ -410,7 +410,7 @@ int stm32_spidev_bus_test(void) #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) - spi3 = stm32l4_spibus_initialize(3); + spi3 = stm32_spibus_initialize(3); if (!spi3) { diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c index 277f8527b9a..13d47f603d6 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index 4e6e5010ed8..0344866c619 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -139,9 +139,9 @@ void stm32_usbinitialize(void) */ #ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } @@ -220,7 +220,7 @@ int stm32_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uinfo("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -273,7 +273,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) /* Set the Power Switch by driving the active low enable pin */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, !enable); + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); } #endif @@ -297,7 +297,7 @@ void stm32_usbhost_vbusdrive(int iface, bool enable) #ifdef CONFIG_USBHOST int stm32_setup_overcurrent(xcpt_t handler, void *arg) { - return stm32l4_gpiosetevent(GPIO_OTGFS_OVER, + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); } #endif @@ -314,7 +314,7 @@ int stm32_setup_overcurrent(xcpt_t handler, void *arg) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c index 578fa289a31..a981d49c6fb 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l4_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -120,7 +120,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l4_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h index b206a8d27d8..bcf021af660 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h @@ -72,7 +72,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture specific initialization @@ -82,10 +82,10 @@ * ****************************************************************************/ -int stm32l4_bringup(void); +int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called from stm32_usbinitialize very early in initialization to setup @@ -94,7 +94,7 @@ int stm32l4_bringup(void); ****************************************************************************/ #ifdef CONFIG_STM32L4_OTGFS -void weak_function stm32l4_usbinitialize(void); +void weak_function stm32_usbinitialize(void); #endif #endif /* __BOARDS_ARM_STM32L4_STEVAL_STLCS01V1_SRC_STEVAL_STLCS01V1_H */ diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c index 577914d757f..ea26a991800 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_autoleds.c @@ -31,7 +31,7 @@ #include #include -#include "stm32l4.h" +#include "stm32.h" #include "steval-stlcs01v1.h" @@ -47,7 +47,7 @@ void board_autoled_initialize(void) { /* Configure LD1 GPIO for output */ - stm32l4_configgpio(GPIO_LD1); + stm32_configgpio(GPIO_LD1); } /**************************************************************************** @@ -58,7 +58,7 @@ void board_autoled_on(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, true); + stm32_gpiowrite(GPIO_LD1, true); } } @@ -70,6 +70,6 @@ void board_autoled_off(int led) { if (led == 1) { - stm32l4_gpiowrite(GPIO_LD1, false); + stm32_gpiowrite(GPIO_LD1, false); } } diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 08d07d743c6..1d8f7a02cb6 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,10 +52,10 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Initialize USB if the 1) OTG FS controller is in the configuration and - * 2) disabled, and 3) the weak function stm32l4_usbinitialize() has been + * 2) disabled, and 3) the weak function stm32_usbinitialize() has been * brought into the build. Presumably either CONFIG_USBDEV is also * selected. */ @@ -63,17 +63,17 @@ void stm32l4_board_initialize(void) #ifdef CONFIG_STM32L4_OTGFS /* Enable Vddusb - mandatory to use the USB OTG FS peripheral */ - stm32l4_pwr_enableusv(true); + stm32_pwr_enableusv(true); - if (stm32l4_usbinitialize) + if (stm32_usbinitialize) { - stm32l4_usbinitialize(); + stm32_usbinitialize(); } #endif /* Enable Vddio2 - mandatory to use the PG2 - PG15 I/Os. */ - stm32l4_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); /* Configure on-board LEDs if LED support has been selected. */ @@ -101,6 +101,6 @@ void board_late_initialize(void) { /* Perform board-specific initialization */ - stm32l4_bringup(); + stm32_bringup(); } #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c index d885272feb3..108b28ef490 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_bringup.c @@ -36,7 +36,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_bringup + * Name: stm32_bringup * * Description: * Perform architecture-specific initialization @@ -46,7 +46,7 @@ * ****************************************************************************/ -int stm32l4_bringup(void) +int stm32_bringup(void) { int ret = OK; diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index 933115652db..cc7945e71a6 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -35,7 +35,7 @@ #include #include #include -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "steval-stlcs01v1.h" @@ -65,15 +65,15 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -81,10 +81,10 @@ void stm32l4_usbinitialize(void) } /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. * This is an opportunity for the board logic to shutdown clocks, power, @@ -93,7 +93,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/board.h b/boards/arm/stm32l4/stm32l476-mdk/include/board.h index 679e0d42ce8..1fd4d9fc5c0 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/board.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/board.h @@ -200,7 +200,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -210,7 +210,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c index d4585229ecf..990571be006 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_autoleds.c @@ -89,9 +89,9 @@ void board_autoled_initialize(void) { /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); } /**************************************************************************** @@ -102,7 +102,7 @@ void board_autoled_on(int led) { if (led == 1 || led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, false); /* Low illuminates */ } } @@ -114,7 +114,7 @@ void board_autoled_off(int led) { if (led == 3) { - stm32l4_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ + stm32_gpiowrite(GPIO_LED_WHITE, true); /* High extinguishes */ } } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c index ab4b6b3ddc4..9600a50507a 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c @@ -43,7 +43,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_uid.h" #include "stm32l476-mdk.h" @@ -66,7 +66,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -76,7 +76,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ @@ -90,7 +90,7 @@ void stm32l4_board_initialize(void) * stm32_spiinitialize() has been brought into the link. */ - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif } @@ -133,7 +133,7 @@ void board_late_initialize(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { syslog(LOG_ERR, @@ -181,7 +181,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c index a39653988ec..e8aa789c2fc 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_buttons.c @@ -76,7 +76,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); } return NUM_BUTTONS; @@ -97,7 +97,7 @@ uint32_t board_buttons(void) { /* A LOW value means that the key is pressed. */ - bool released = stm32l4_gpioread(g_buttons[i]); + bool released = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -139,7 +139,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index bf16becc8f3..38b64581120 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c index 766cd2f1646..74f07782157 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476-mdk.h" diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c index 19b645de1a0..db4d7ded751 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_userleds.c @@ -48,9 +48,9 @@ uint32_t board_userled_initialize(void) #ifndef CONFIG_ARCH_LEDS /* Configure LED GPIOs for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GREEN); - stm32l4_configgpio(GPIO_LED_WHITE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_WHITE); #endif return BOARD_NLEDS; } @@ -63,16 +63,16 @@ void board_userled(int led, bool ledon) { if (led == BOARD_RED_LED) { - stm32l4_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_RED, !ledon); /* Low illuminates */ } else if (led == BOARD_GREEN_LED) { - stm32l4_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_GREEN, !ledon); /* Low illuminates */ } #ifndef CONFIG_ARCH_LEDS else if (led == BOARD_WHITE_LED) { - stm32l4_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ + stm32_gpiowrite(GPIO_LED_WHITE, !ledon); /* Low illuminates */ } #endif } @@ -85,9 +85,9 @@ void board_userled_all(uint32_t ledset) { /* Low illuminates */ - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); - stm32l4_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_RED_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_GREEN, (ledset & BOARD_GREEN_LED_BIT) == 0); #ifndef CONFIG_ARCH_LEDS - stm32l4_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); + stm32_gpiowrite(GPIO_LED_WHITE, (ledset & BOARD_WHITE_LED_BIT) == 0); #endif } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h index 1923d5b3055..ba96e8f62ea 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h @@ -281,7 +281,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -291,7 +291,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c index a5c0dceaba4..bf1c2cd5103 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index 74a290c5550..be69ca1b000 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -65,7 +65,7 @@ void stm32l4_board_initialize(void) */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - stm32l4_spiinitialize(); + stm32_spiinitialize(); #endif #ifdef CONFIG_STM32L4_OTGFS @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c index f96a416d761..f3137ceb232 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_bringup.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include @@ -124,7 +124,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -148,10 +148,10 @@ int stm32_bringup(void) #ifdef HAVE_N25QXXX /* Create an instance of the STM32L4 QSPI device driver */ - g_qspi = stm32l4_qspi_initialize(0); + g_qspi = stm32_qspi_initialize(0); if (!g_qspi) { - _err("ERROR: stm32l4_qspi_initialize failed\n"); + _err("ERROR: stm32_qspi_initialize failed\n"); return ret; } else @@ -242,11 +242,11 @@ int stm32_bringup(void) #endif #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c index 4bc824ac869..13e713e8998 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index b2a93e9b22b..ad5a8de00b9 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c index fcb4521d789..dc297132fa9 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_spi.c @@ -35,7 +35,7 @@ #include #include "chip.h" -#include +#include #include "stm32l476vg-disco.h" diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c index 7c6da8f1cdc..60809d9a07f 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c index f5aa212e955..700c408c3e1 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c @@ -40,7 +40,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l476vg-disco.h" @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to + * Called from stm32_usbinitialize very early in initialization to * setup USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -138,14 +138,14 @@ void stm32l4_usbinitialize(void) */ #ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be provided @@ -265,7 +265,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -273,19 +273,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -300,18 +300,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -319,7 +319,7 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c index 5ff1fcd886e..39f749747e4 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l476vg-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h index a8e921a60d0..79b85d1a564 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -274,13 +274,13 @@ int stm32_bringup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); #endif /* __BOARDS_ARM_STM32L4_STM32L476VG_DISCO_SRC_STM32L476VG_DISCO_H */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h index cabf4cd5f47..d1fc951f438 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/board.h @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. @@ -285,7 +285,7 @@ extern "C" * ****************************************************************************/ -void stm32l4_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c index 0e26c9ca5e9..c756acc8a31 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c @@ -144,14 +144,14 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext) { struct adc_msg_s sample[ADC1_NCHANNELS]; @@ -265,10 +265,10 @@ out: } /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup ****************************************************************************/ -int stm32l4_adc_setup(void) +int stm32_adc_setup(void) { static bool initialized = false; @@ -284,13 +284,13 @@ int stm32l4_adc_setup(void) { if (g_pinlist[i] != 0xffffffffu) { - stm32l4_configgpio(g_pinlist[i]); + stm32_configgpio(g_pinlist[i]); } } - /* Call stm32l4_adc_initialize() to get an instance of the ADC */ + /* Call stm32_adc_initialize() to get an instance of the ADC */ - g_adc = stm32l4_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); + g_adc = stm32_adc_initialize(1, g_chanlist, ADC1_NCHANNELS); if (g_adc == NULL) { aerr("ERROR: Failed to get ADC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c index a7af9a1dda8..fb79f4dbec3 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_autoleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifdef CONFIG_ARCH_LEDS @@ -52,8 +52,8 @@ void board_autoled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); } /**************************************************************************** @@ -92,7 +92,7 @@ void board_autoled_on(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_RED, true); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=ON @@ -101,13 +101,13 @@ void board_autoled_on(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, true); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, true); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, true); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, true); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } @@ -141,7 +141,7 @@ void board_autoled_off(int led) case LED_INIRQ: case LED_SIGNAL: case LED_ASSERTION: - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; /* 3: LED_PANIC: GPIO_LED_GRN=OFF RX=OFF @@ -150,13 +150,13 @@ void board_autoled_off(int led) */ case LED_PANIC: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; case LED_IDLE: - stm32l4_gpiowrite(GPIO_LED_GRN, false); - stm32l4_gpiowrite(GPIO_LED_RED, false); + stm32_gpiowrite(GPIO_LED_GRN, false); + stm32_gpiowrite(GPIO_LED_RED, false); break; } } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index ccc12956c6a..32a642f5190 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L4 architectures must provide the following entry point. This @@ -52,7 +52,7 @@ * ****************************************************************************/ -void stm32l4_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -77,7 +77,7 @@ void stm32l4_board_initialize(void) * also selected. */ - stm32l4_usbinitialize(); + stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index ae5c959cc34..9bd8d1ff612 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -37,7 +37,7 @@ #include #include -#include +#include #include #include @@ -112,7 +112,7 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER /* Instantiate the STM32 lower-half RTC driver */ - rtclower = stm32l4_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -136,14 +136,14 @@ int stm32_bringup(void) #ifdef CONFIG_I2C i2cinfo("Initializing I2C buses\n"); #ifdef CONFIG_STM32L4_I2C1 - g_i2c1 = stm32l4_i2cbus_initialize(1); + g_i2c1 = stm32_i2cbus_initialize(1); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c1, 1); #endif #endif #ifdef CONFIG_STM32L4_I2C3 - g_i2c3 = stm32l4_i2cbus_initialize(3); + g_i2c3 = stm32_i2cbus_initialize(3); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c3, 3); #endif @@ -151,11 +151,11 @@ int stm32_bringup(void) #endif /* CONFIG_I2C */ #ifdef HAVE_USBHOST - /* Initialize USB host operation. stm32l4_usbhost_initialize() starts a + /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread that will monitor for USB connection and disconnection events. */ - ret = stm32l4_usbhost_initialize(); + ret = stm32_usbhost_initialize(); if (ret != OK) { udbg("ERROR: Failed to initialize USB host: %d\n", ret); @@ -177,7 +177,7 @@ int stm32_bringup(void) #ifdef CONFIG_ADC ainfo("Initializing ADC\n"); - stm32l4_adc_setup(); + stm32_adc_setup(); #ifdef CONFIG_STM32L4_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ @@ -192,7 +192,7 @@ int stm32_bringup(void) #ifdef CONFIG_DAC ainfo("Initializing DAC\n"); - stm32l4_dac_setup(); + stm32_dac_setup(); #endif return ret; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c index ba8240c175c..3c50102b131 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_buttons.c @@ -229,7 +229,7 @@ uint32_t board_button_initialize(void) for (i = 0; i < NUM_BUTTONS; i++) { - stm32l4_configgpio(g_buttons[i]); + stm32_configgpio(g_buttons[i]); /* It's not clear if this is correct; I think so, but then there are * conflicts with the 'buttons' sample app. @@ -260,7 +260,7 @@ uint32_t board_buttons(void) { /* A HIGH value means that the key is pressed. */ - bool pressed = stm32l4_gpioread(g_buttons[i]); + bool pressed = stm32_gpioread(g_buttons[i]); /* Accumulate the set of depressed (not released) keys */ @@ -315,7 +315,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) { - ret = stm32l4_gpiosetevent(g_buttons[id], true, true, true, + ret = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index cfd2d047792..5119c7b5f56 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -53,7 +53,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) -void stm32l4_board_clockconfig(void) +void stm32_board_clockconfig(void) { uint32_t regval; @@ -201,7 +201,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -212,8 +212,8 @@ void stm32l4_board_clockconfig(void) * be enabled: if the MCO1 pin selects LSE as source. */ - stm32l4_pwr_enableclk(true); - stm32l4_rcc_enablelse(); + stm32_pwr_enableclk(true); + stm32_rcc_enablelse(); #endif } #endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c index 99e82f4d6d2..fd2d8f541d4 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c @@ -48,10 +48,10 @@ static struct dac_dev_s *g_dac; ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup ****************************************************************************/ -int stm32l4_dac_setup(void) +int stm32_dac_setup(void) { static bool initialized = false; @@ -60,7 +60,7 @@ int stm32l4_dac_setup(void) #ifdef CONFIG_STM32L4_DAC1 int ret; - g_dac = stm32l4_dacinitialize(0); + g_dac = stm32_dacinitialize(0); if (g_dac == NULL) { aerr("ERROR: Failed to get DAC interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c index ba31c3d3d17..fd1716501c6 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c @@ -92,7 +92,7 @@ int stm32_dfsdm_setup(void) */ #ifdef CONFIG_STM32L4_DFSDM1_FLT0 - adc = stm32l4_dfsdm_initialize(0, chanlist0, 1); + adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { aerr("Failed to get DFSDM FLT0 interface\n"); @@ -108,7 +108,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT1 - adc = stm32l4_dfsdm_initialize(1, chanlist1, 2); + adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { aerr("Failed to get DFSDM FLT1 interface\n"); @@ -124,7 +124,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT2 - adc = stm32l4_dfsdm_initialize(2, chanlist2, 8); + adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { aerr("Failed to get DFSDM FLT2 interface\n"); @@ -140,7 +140,7 @@ int stm32_dfsdm_setup(void) #endif #ifdef CONFIG_STM32L4_DFSDM1_FLT3 - adc = stm32l4_dfsdm_initialize(3, chanlist3, 4); + adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { aerr("Failed to get DFSDM FLT3 interface\n"); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index f86e4621d12..cc871792ae4 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -36,7 +36,7 @@ #include #include "chip.h" -#include +#include #include "stm32l4r9ai-disco.h" @@ -75,7 +75,7 @@ void weak_function stm32_spiinitialize(void) #ifdef CONFIG_STM32L4_SPI1 /* Configure SPI-based devices on SPI1 */ - g_spi1 = stm32l4_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: [boot] FAILED to initialize SPI port 1\n"); @@ -86,14 +86,14 @@ void weak_function stm32_spiinitialize(void) #endif #ifdef HAVE_MMCSD - stm32l4_configgpio(GPIO_SPI_CS_SD_CARD); + stm32_configgpio(GPIO_SPI_CS_SD_CARD); #endif #endif #ifdef CONFIG_STM32L4_SPI2 /* Configure SPI-based devices on SPI2 */ - g_spi2 = stm32l4_spibus_initialize(2); + g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) { spierr("ERROR: [boot] FAILED to initialize SPI port 2\n"); @@ -109,7 +109,7 @@ void weak_function stm32_spiinitialize(void) #ifdef CONFIG_STM32L4_SPI3 /* Configure SPI-based devices on SPI3 */ - g_spi3 = stm32l4_spibus_initialize(3); + g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) { spierr("ERROR: [boot] FAILED to initialize SPI port 3\n"); @@ -124,14 +124,14 @@ void weak_function stm32_spiinitialize(void) } /**************************************************************************** - * Name: stm32l4_spi1/2/3select and stm32l4_spi1/2/3status + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32l4_spibus_initialize()) are provided by common STM32 + * (including stm32_spibus_initialize()) are provided by common STM32 * logic. To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -140,9 +140,9 @@ void weak_function stm32_spiinitialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32l4_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l4_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -150,7 +150,7 @@ void weak_function stm32_spiinitialize(void) ****************************************************************************/ #ifdef CONFIG_STM32L4_SPI1 -void stm32l4_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", @@ -159,47 +159,47 @@ void stm32l4_spi1select(struct spi_dev_s *dev, #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32l4_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32l4_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI2 -void stm32l4_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif #ifdef CONFIG_STM32L4_SPI3 -void stm32l4_spi3select(struct spi_dev_s *dev, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) { return 0; } #endif /**************************************************************************** - * Name: stm32l4_spi1/2/3cmddata + * Name: stm32_spi1/2/3cmddata * * Description: * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) @@ -223,21 +223,21 @@ uint8_t stm32l4_spi3status(struct spi_dev_s *dev, uint32_t devid) #ifdef CONFIG_SPI_CMDDATA #ifdef CONFIG_STM32L4_SPI1 -int stm32l4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI2 -int stm32l4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif #ifdef CONFIG_STM32L4_SPI3 -int stm32l4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c index bb1720bae25..94a5221d7ef 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_uid.c @@ -56,6 +56,6 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32l4_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c index d36a3b17952..52eacbacede 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c @@ -40,7 +40,7 @@ #include #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4_otgfs.h" #include "stm32l4r9ai-disco.h" @@ -119,15 +119,15 @@ static int usbhost_waiter(int argc, char *argv[]) ****************************************************************************/ /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: - * Called from stm32l4_usbinitialize very early in initialization to setup + * Called from stm32_usbinitialize very early in initialization to setup * USB-related GPIO pins for the STM32L4Discovery board. * ****************************************************************************/ -void stm32l4_usbinitialize(void) +void stm32_usbinitialize(void) { /* The OTG FS has an internal soft pull-up. * No GPIO configuration is required @@ -138,14 +138,14 @@ void stm32l4_usbinitialize(void) */ #ifdef CONFIG_STM32L4_OTGFS - stm32l4_configgpio(GPIO_OTGFS_VBUS); - stm32l4_configgpio(GPIO_OTGFS_PWRON); - stm32l4_configgpio(GPIO_OTGFS_OVER); + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); #endif } /**************************************************************************** - * Name: stm32l4_usbhost_initialize + * Name: stm32_usbhost_initialize * * Description: * Called at application startup time to initialize the USB host @@ -156,7 +156,7 @@ void stm32l4_usbinitialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -int stm32l4_usbhost_initialize(void) +int stm32_usbhost_initialize(void) { int ret; @@ -219,7 +219,7 @@ int stm32l4_usbhost_initialize(void) /* Then get an instance of the USB host interface */ uvdbg("Initialize USB host\n"); - g_usbconn = stm32l4_otgfshost_initialize(0); + g_usbconn = stm32_otgfshost_initialize(0); if (g_usbconn) { /* Start a thread to handle device connection. */ @@ -237,7 +237,7 @@ int stm32l4_usbhost_initialize(void) #endif /**************************************************************************** - * Name: stm32l4_usbhost_vbusdrive + * Name: stm32_usbhost_vbusdrive * * Description: * Enable/disable driving of VBUS 5V output. This function must be @@ -266,7 +266,7 @@ int stm32l4_usbhost_initialize(void) ****************************************************************************/ #ifdef CONFIG_USBHOST -void stm32l4_usbhost_vbusdrive(int iface, bool enable) +void stm32_usbhost_vbusdrive(int iface, bool enable) { DEBUGASSERT(iface == 0); @@ -274,19 +274,19 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) { /* Enable the Power Switch by driving the enable pin low */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, false); + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); } else { /* Disable the Power Switch by driving the enable pin high */ - stm32l4_gpiowrite(GPIO_OTGFS_PWRON, true); + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); } } #endif /**************************************************************************** - * Name: stm32l4_setup_overcurrent + * Name: stm32_setup_overcurrent * * Description: * Setup to receive an interrupt-level callback if an over current @@ -301,18 +301,18 @@ void stm32l4_usbhost_vbusdrive(int iface, bool enable) ****************************************************************************/ #ifdef CONFIG_USBHOST -xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) +xcpt_t stm32_setup_overcurrent(xcpt_t handler) { - stm32l4_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); + stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, NULL); return NULL; } #endif /**************************************************************************** - * Name: stm32l4_usbsuspend + * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32l4_usbsuspend logic if the USBDEV + * Board logic must provide the stm32_usbsuspend logic if the USBDEV * driver is used. This function is called whenever the USB enters or * leaves suspend mode. This is an opportunity for the board logic to * shutdown clocks, power, etc. while the USB is suspended. @@ -320,7 +320,7 @@ xcpt_t stm32l4_setup_overcurrent(xcpt_t handler) ****************************************************************************/ #ifdef CONFIG_USBDEV -void stm32l4_usbsuspend(struct usbdev_s *dev, bool resume) +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); } diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c index 557436dade8..5d07a4d3584 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_userleds.c @@ -36,7 +36,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l4.h" +#include "stm32.h" #include "stm32l4r9ai-disco.h" #ifndef CONFIG_ARCH_LEDS @@ -89,11 +89,11 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Restore normal LEDs operation */ - /* stm32l4_gpiowrite(GPIO_LED_RED, + /* stm32_gpiowrite(GPIO_LED_RED, * (ledset & BOARD_LED_RED_BIT) != 0); */ - /* stm32l4_gpiowrite(GPIO_LED_GRN, + /* stm32_gpiowrite(GPIO_LED_GRN, * (ledset & BOARD_LED_GRN_BIT) != 0); */ } @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -121,8 +121,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32l4_gpiowrite(GPIO_LED_RED, 0); - stm32l4_gpiowrite(GPIO_LED_GRN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GRN, 0); } break; @@ -171,8 +171,8 @@ uint32_t board_userled_initialize(void) { /* Configure LD4,5 GPIO for output */ - stm32l4_configgpio(GPIO_LED_RED); - stm32l4_configgpio(GPIO_LED_GRN); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GRN); return BOARD_NLEDS; } @@ -185,11 +185,11 @@ void board_userled(int led, bool ledon) switch (led) { case BOARD_LED_RED: - stm32l4_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case BOARD_LED_GRN: - stm32l4_gpiowrite(GPIO_LED_GRN, ledon); + stm32_gpiowrite(GPIO_LED_GRN, ledon); break; } } @@ -200,8 +200,8 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32l4_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); - stm32l4_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); + stm32_gpiowrite(GPIO_LED_RED, (ledset & BOARD_LED_RED_BIT) != 0); + stm32_gpiowrite(GPIO_LED_GRN, (ledset & BOARD_LED_GRN_BIT) != 0); } /**************************************************************************** diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h index b3e2fa0db7f..b113923cce0 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h @@ -213,36 +213,36 @@ extern struct spi_dev_s *g_spi2; int stm32_bringup(void); /**************************************************************************** - * Name: stm32l4_adc_setup + * Name: stm32_adc_setup * * Description: * Initialize ADC and register the ADC driver. * ****************************************************************************/ -int stm32l4_adc_setup(void); +int stm32_adc_setup(void); /**************************************************************************** - * Name: stm32l4_adc_measure_voltages + * Name: stm32_adc_measure_voltages * * Description: * Read internal reference voltage, internal VBAT and one external voltage. * ****************************************************************************/ -int stm32l4_adc_measure_voltages(uint32_t *vrefint, +int stm32_adc_measure_voltages(uint32_t *vrefint, uint32_t *vbat, uint32_t *vext); /**************************************************************************** - * Name: stm32l4_dac_setup + * Name: stm32_dac_setup * * Description: * Initialize DAC and register the DAC driver. * ****************************************************************************/ -int stm32l4_dac_setup(void); +int stm32_dac_setup(void); /**************************************************************************** * Name: stm32_dfsdm_setup @@ -267,13 +267,13 @@ int stm32_dfsdm_setup(void); void stm32_spiinitialize(void); /**************************************************************************** - * Name: stm32l4_usbinitialize + * Name: stm32_usbinitialize * * Description: * Called to setup USB-related GPIO pins. * ****************************************************************************/ -void stm32l4_usbinitialize(void); +void stm32_usbinitialize(void); #endif /* __BOARDS_ARM_STM32L4_STM32L4R9AI_DISCO_SRC_STM32L4R9AI_DISCO_H */ diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h index 25e759e26c0..19bcaad40e2 100644 --- a/include/nuttx/analog/ioctl.h +++ b/include/nuttx/analog/ioctl.h @@ -93,12 +93,12 @@ /* See arch/arm/src/stm32l4/stm32l4_adc.h */ -#define AN_STM32L4_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) -#define AN_STM32L4_NCMDS 2 +#define AN_STM32_FIRST (AN_ADS7828_FIRST + AN_ADS7828_NCMDS) +#define AN_STM32_NCMDS 2 /* See include/nuttx/analog/max1161x.h */ -#define AN_MAX1161X_FIRST (AN_STM32L4_FIRST + AN_STM32L4_NCMDS) +#define AN_MAX1161X_FIRST (AN_STM32_FIRST + AN_STM32_NCMDS) #define AN_MAX1161X_NCMDS 8 /* See include/nuttx/analog/mcp48xx.h */ From 60dffa100433f5c2a5b415d1b019810a238f8e34 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:44 +0200 Subject: [PATCH 068/268] !arm/stm32l5: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32L5 interfaces were renamed from stm32l5_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32L5 timer/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32L5 root family header was renamed from stm32l5.h to stm32.h; all STM32L5 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32l5/{stm32l5.h => stm32.h} | 2 +- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 18 +- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 8 +- arch/arm/src/stm32l5/stm32l5_dumpgpio.c | 4 +- arch/arm/src/stm32l5/stm32l5_exti.h | 16 +- arch/arm/src/stm32l5/stm32l5_exti_gpio.c | 10 +- arch/arm/src/stm32l5/stm32l5_flash.c | 16 +- arch/arm/src/stm32l5/stm32l5_flash.h | 8 +- arch/arm/src/stm32l5/stm32l5_gpio.c | 28 +- arch/arm/src/stm32l5/stm32l5_gpio.h | 36 +- arch/arm/src/stm32l5/stm32l5_irq.c | 40 +- arch/arm/src/stm32l5/stm32l5_lowputc.c | 20 +- arch/arm/src/stm32l5/stm32l5_lowputc.h | 4 +- arch/arm/src/stm32l5/stm32l5_lse.c | 10 +- arch/arm/src/stm32l5/stm32l5_lsi.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.c | 8 +- arch/arm/src/stm32l5/stm32l5_mpuinit.h | 12 +- arch/arm/src/stm32l5/stm32l5_pwr.c | 44 +- arch/arm/src/stm32l5/stm32l5_pwr.h | 14 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 28 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 42 +- arch/arm/src/stm32l5/stm32l5_serial.c | 204 ++++---- arch/arm/src/stm32l5/stm32l5_spi.c | 184 +++---- arch/arm/src/stm32l5/stm32l5_spi.h | 48 +- arch/arm/src/stm32l5/stm32l5_start.c | 12 +- arch/arm/src/stm32l5/stm32l5_start.h | 4 +- arch/arm/src/stm32l5/stm32l5_tim.c | 460 +++++++++--------- arch/arm/src/stm32l5/stm32l5_tim.h | 54 +- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 110 ++--- arch/arm/src/stm32l5/stm32l5_timerisr.c | 8 +- arch/arm/src/stm32l5/stm32l5_uart.h | 4 +- arch/arm/src/stm32l5/stm32l5_uid.c | 2 +- arch/arm/src/stm32l5/stm32l5_uid.h | 2 +- arch/arm/src/stm32l5/stm32l5_userspace.c | 6 +- arch/arm/src/stm32l5/stm32l5_userspace.h | 4 +- arch/arm/src/stm32l5/stm32l5_waste.c | 2 +- arch/arm/src/stm32l5/stm32l5_waste.h | 4 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 4 +- .../nucleo-l552ze/src/stm32_autoleds.c | 4 +- .../stm32l5/nucleo-l552ze/src/stm32_boot.c | 12 +- .../stm32l5/nucleo-l552ze/src/stm32_buttons.c | 6 +- .../nucleo-l552ze/src/stm32_userleds.c | 6 +- .../arm/stm32l5/stm32l562e-dk/include/board.h | 4 +- .../stm32l562e-dk/src/stm32_autoleds.c | 4 +- .../stm32l5/stm32l562e-dk/src/stm32_boot.c | 6 +- .../stm32l5/stm32l562e-dk/src/stm32_buttons.c | 6 +- .../stm32l562e-dk/src/stm32_clockconfig.c | 2 +- .../stm32l562e-dk/src/stm32_userleds.c | 6 +- 48 files changed, 772 insertions(+), 772 deletions(-) rename arch/arm/src/stm32l5/{stm32l5.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32l5/stm32l5.h b/arch/arm/src/stm32l5/stm32.h similarity index 98% rename from arch/arm/src/stm32l5/stm32l5.h rename to arch/arm/src/stm32l5/stm32.h index 7cedda9b78c..da1a85b295c 100644 --- a/arch/arm/src/stm32l5/stm32l5.h +++ b/arch/arm/src/stm32l5/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32l5/stm32l5.h + * arch/arm/src/stm32l5/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index 39636e57719..50591f093a3 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -575,10 +575,10 @@ static inline void rcc_enableccip(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { rcc_enableccip(); rcc_enableahb1(); @@ -589,7 +589,7 @@ void stm32l5_rcc_enableperipherals(void) } /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -599,7 +599,7 @@ void stm32l5_rcc_enableperipherals(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void) +void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -687,7 +687,7 @@ void stm32l5_stdclockconfig(void) } #else -# error stm32l5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -704,7 +704,7 @@ void stm32l5_stdclockconfig(void) /* Ensure Power control is enabled before modifying it. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* Select correct main regulator range */ @@ -901,7 +901,7 @@ void stm32l5_stdclockconfig(void) #if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32l5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif #if defined(STM32_USE_LSE) @@ -916,7 +916,7 @@ void stm32l5_stdclockconfig(void) * to alter the LSE parameters. */ - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); /* XXX other LSE settings must be made before turning on the oscillator * and we need to ensure it is first off before doing so. @@ -927,7 +927,7 @@ void stm32l5_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32l5_rcc_enablelse(); + stm32_rcc_enablelse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index 5547109564e..d2c56c99527 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -240,7 +240,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32l5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -318,7 +318,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif @@ -338,7 +338,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM3 heap */ - stm32l5_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); + stm32_mpu_uheap((uintptr_t)SRAM3_START, SRAM3_END - SRAM3_START); #endif @@ -357,7 +357,7 @@ void arm_addregion(void) /* Allow user-mode access to the FSMC SRAM user heap memory */ - stm32l5_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); + stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c index f5dc0ed6ce7..cf5760c43f6 100644 --- a/arch/arm/src/stm32l5/stm32l5_dumpgpio.c +++ b/arch/arm/src/stm32l5/stm32l5_dumpgpio.c @@ -86,14 +86,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32l5_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index 7093f76a75e..b64a8055015 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32l5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32l5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32l5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32l5_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32L5_COMP -int stm32l5_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c index 67a6a051e23..10e1099e0ec 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_exti_gpio.c @@ -67,7 +67,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routine - Dispatcher ****************************************************************************/ -static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) +static int stm32_exti0_15_isr(int irq, void *context, void *arg) { int ret = OK; int exti; @@ -98,7 +98,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -120,7 +120,7 @@ static int stm32l5_exti0_15_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { uint32_t pin = pinset & GPIO_PIN_MASK; @@ -134,7 +134,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, if (func) { - irq_attach(irq, stm32l5_exti0_15_isr, NULL); + irq_attach(irq, stm32_exti0_15_isr, NULL); up_enable_irq(irq); } else @@ -151,7 +151,7 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32l5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index d7d9915e709..8f9625bb34c 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -107,7 +107,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_NSCR) & FLASH_CR_LOCK) @@ -156,7 +156,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_NSCR, FLASH_CR_PAGE_ERASE, 0); @@ -166,14 +166,14 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -void stm32l5_flash_unlock(void) +void stm32_flash_unlock(void) { nxmutex_lock(&g_lock); flash_unlock(); nxmutex_unlock(&g_lock); } -void stm32l5_flash_lock(void) +void stm32_flash_lock(void) { nxmutex_lock(&g_lock); flash_lock(); @@ -181,7 +181,7 @@ void stm32l5_flash_lock(void) } /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -197,7 +197,7 @@ void stm32l5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; @@ -229,7 +229,7 @@ uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -431,7 +431,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_NSSR) & FLASH_SR_BSY) { - stm32l5_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32l5/stm32l5_flash.h b/arch/arm/src/stm32l5/stm32l5_flash.h index 0a3f7076c90..81d15ed8a13 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/stm32l5_flash.h @@ -34,11 +34,11 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_flash_lock(void); -void stm32l5_flash_unlock(void); +void stm32_flash_lock(void); +void stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32l5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -54,6 +54,6 @@ void stm32l5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32l5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_FLASH_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.c b/arch/arm/src/stm32l5/stm32l5_gpio.c index 2d9afa34849..297a5deb182 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.c +++ b/arch/arm/src/stm32l5/stm32l5_gpio.c @@ -91,13 +91,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -105,17 +105,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32l5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -126,7 +126,7 @@ void stm32l5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -169,7 +169,7 @@ int stm32l5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32l5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -304,7 +304,7 @@ int stm32l5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -324,7 +324,7 @@ int stm32l5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -333,18 +333,18 @@ int stm32l5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32l5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -378,14 +378,14 @@ void stm32l5_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index 2bb1f035651..16caeb1a50e 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32l5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -248,12 +248,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32l5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -262,10 +262,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32l5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -284,30 +284,30 @@ int stm32l5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32l5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32l5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32l5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32l5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32l5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32l5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -326,11 +326,11 @@ bool stm32l5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32l5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -338,23 +338,23 @@ int stm32l5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32l5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32l5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32l5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32l5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32l5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_irq.c b/arch/arm/src/stm32l5/stm32l5_irq.c index f42f2dda2ab..46195910a0c 100644 --- a/arch/arm/src/stm32l5/stm32l5_irq.c +++ b/arch/arm/src/stm32l5/stm32l5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32l5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -112,11 +112,11 @@ static void stm32l5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32l5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32l5_nmi, stm32l5_pendsv, stm32l5_pendsv, stm32l5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -126,7 +126,7 @@ static void stm32l5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32l5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -134,7 +134,7 @@ static int stm32l5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32l5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -142,7 +142,7 @@ static int stm32l5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32l5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -152,7 +152,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32l5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -160,7 +160,7 @@ static int stm32l5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32l5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -173,7 +173,7 @@ static inline void stm32l5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32l5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -181,7 +181,7 @@ static inline void stm32l5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32l5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -309,7 +309,7 @@ void up_irqinitialize(void) #endif - stm32l5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -323,19 +323,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32l5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32l5_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32l5_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32l5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -360,7 +360,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -395,7 +395,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32l5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -472,7 +472,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32l5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.c b/arch/arm/src/stm32l5/stm32l5_lowputc.c index 6229979f9a2..d10ce831abf 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.c +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_rcc.h" #include "stm32l5_gpio.h" #include "stm32l5_uart.h" @@ -308,7 +308,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -319,7 +319,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -327,7 +327,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -336,7 +336,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32l5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -352,19 +352,19 @@ void stm32l5_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32l5_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32l5_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32l5_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32l5_configgpio(STM32_CONSOLE_RS485_DIR); - stm32l5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_lowputc.h b/arch/arm/src/stm32l5/stm32l5_lowputc.h index 29e808377c3..c3e60eb22ae 100644 --- a/arch/arm/src/stm32l5/stm32l5_lowputc.h +++ b/arch/arm/src/stm32l5/stm32l5_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32l5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index f3e6827279b..e89c3a1887b 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -68,14 +68,14 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32l5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { bool writable; uint32_t regval; @@ -100,7 +100,7 @@ void stm32l5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32l5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -173,7 +173,7 @@ void stm32l5_rcc_enablelse(void) while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32l5_waste(); + stm32_waste(); } } @@ -188,6 +188,6 @@ void stm32l5_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - stm32l5_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32l5/stm32l5_lsi.c b/arch/arm/src/stm32l5/stm32l5_lsi.c index a47bd5ea1dd..6d57b07aac4 100644 --- a/arch/arm/src/stm32l5/stm32l5_lsi.c +++ b/arch/arm/src/stm32l5/stm32l5_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32l5_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.c b/arch/arm/src/stm32l5/stm32l5_mpuinit.c index 94d42c795ae..2c70971fdde 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.c +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32l5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32l5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32l5_mpuinitialize(void) * ****************************************************************************/ -void stm32l5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32l5/stm32l5_mpuinit.h b/arch/arm/src/stm32l5/stm32l5_mpuinit.h index 94ee60dc285..d31d148496d 100644 --- a/arch/arm/src/stm32l5/stm32l5_mpuinit.h +++ b/arch/arm/src/stm32l5/stm32l5_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32l5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32l5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32l5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32l5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_MPUINIT_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.c b/arch/arm/src/stm32l5/stm32l5_pwr.c index 3b306923e8e..90ac2900f6b 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.c +++ b/arch/arm/src/stm32l5/stm32l5_pwr.c @@ -39,12 +39,12 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32l5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } @@ -70,7 +70,7 @@ static inline void stm32l5_pwr_putreg(uint8_t offset, uint16_t value) * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable) +bool stm32_pwr_enableclk(bool enable) { uint32_t regval; bool wasenabled; @@ -99,7 +99,7 @@ bool stm32l5_pwr_enableclk(bool enable) } /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -113,14 +113,14 @@ bool stm32l5_pwr_enableclk(bool enable) * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32L5 PWR control register 1 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -130,14 +130,14 @@ bool stm32l5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32l5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -148,7 +148,7 @@ bool stm32l5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -163,7 +163,7 @@ bool stm32l5_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; @@ -174,12 +174,12 @@ bool stm32l5_pwr_enableusv(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -189,26 +189,26 @@ bool stm32l5_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; } /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -223,7 +223,7 @@ bool stm32l5_pwr_enableusv(bool set) * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set) +bool stm32_pwr_vddio2_valid(bool set) { uint32_t regval; bool was_set; @@ -234,12 +234,12 @@ bool stm32l5_pwr_vddio2_valid(bool set) if (!was_clk_enabled) { - stm32l5_pwr_enableclk(true); + stm32_pwr_enableclk(true); } /* Get the current state of the STM32L5 PWR control register 2 */ - regval = stm32l5_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_IOSV) != 0); /* Enable or disable the ability to write */ @@ -249,19 +249,19 @@ bool stm32l5_pwr_vddio2_valid(bool set) /* Reset the Vddio2 independent I/O supply valid bit. */ regval &= ~PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Set the Vddio2 independent I/O supply valid bit. */ regval |= PWR_CR2_IOSV; - stm32l5_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } if (!was_clk_enabled) { - stm32l5_pwr_enableclk(false); + stm32_pwr_enableclk(false); } return was_set; diff --git a/arch/arm/src/stm32l5/stm32l5_pwr.h b/arch/arm/src/stm32l5/stm32l5_pwr.h index 611eaf8e001..637150d65c1 100644 --- a/arch/arm/src/stm32l5/stm32l5_pwr.h +++ b/arch/arm/src/stm32l5/stm32l5_pwr.h @@ -70,10 +70,10 @@ extern "C" * ****************************************************************************/ -bool stm32l5_pwr_enableclk(bool enable); +bool stm32_pwr_enableclk(bool enable); /**************************************************************************** - * Name: stm32l5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -87,10 +87,10 @@ bool stm32l5_pwr_enableclk(bool enable); * ****************************************************************************/ -bool stm32l5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32l5_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -105,10 +105,10 @@ bool stm32l5_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32l5_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** - * Name: stm32l5_pwr_vddio2_valid + * Name: stm32_pwr_vddio2_valid * * Description: * Report that the Vddio2 independent I/Os supply voltage is valid or not. @@ -123,7 +123,7 @@ bool stm32l5_pwr_enableusv(bool set); * ****************************************************************************/ -bool stm32l5_pwr_vddio2_valid(bool set); +bool stm32_pwr_vddio2_valid(bool set); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index 8164097f5a0..d0a29a8c2c6 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -37,7 +37,7 @@ #include "chip.h" #include "stm32l5_rcc.h" #include "stm32l5_flash.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_waste.h" /**************************************************************************** @@ -90,7 +90,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32l5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -107,7 +107,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32l5_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -128,7 +128,7 @@ static inline void rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - stm32l5_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -150,7 +150,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -160,7 +160,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32l5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -175,7 +175,7 @@ void stm32l5_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -183,13 +183,13 @@ void stm32l5_clockconfig(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32l5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -202,12 +202,12 @@ void stm32l5_clockconfig(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -218,13 +218,13 @@ void stm32l5_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32l5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -232,7 +232,7 @@ void stm32l5_clockenable(void) * board.h */ - stm32l5_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index 5157e85ce53..0b3f4a7740a 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -58,7 +58,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32l562xx @@ -75,7 +75,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32l5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -92,7 +92,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -102,7 +102,7 @@ static inline void stm32l5_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -112,10 +112,10 @@ static inline void stm32l5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32l5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32l5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32L5 board may replace the "standard" board clock configuration @@ -124,11 +124,11 @@ void stm32l5_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -139,11 +139,11 @@ void stm32l5_board_clockconfig(void); ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG -void stm32l5_stdclockconfig(void); +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32l5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -152,12 +152,12 @@ void stm32l5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32l5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32l5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,11 +168,11 @@ void stm32l5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32l5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32l5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -185,30 +185,30 @@ void stm32l5_clockenable(void); * ****************************************************************************/ -void stm32l5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32l5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32l5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32l5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -217,7 +217,7 @@ void stm32l5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32l5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index e39dad2f74e..ea07188a10c 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -212,7 +212,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -327,9 +327,9 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev); static void stm32l5serial_dmashutdown(struct uart_dev_s *dev); static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv); +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv); +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev); @@ -446,7 +446,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER -static struct stm32l5_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -506,7 +506,7 @@ static struct stm32l5_serial_s g_lpuart1priv = #endif #ifdef CONFIG_STM32L5_USART1_SERIALDRIVER -static struct stm32l5_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -568,7 +568,7 @@ static struct stm32l5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32L5_USART2_SERIALDRIVER -static struct stm32l5_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -630,7 +630,7 @@ static struct stm32l5_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ #ifdef CONFIG_STM32L5_USART3_SERIALDRIVER -static struct stm32l5_serial_s g_usart3priv = +static struct stm32_serial_s g_usart3priv = { .dev = { @@ -692,7 +692,7 @@ static struct stm32l5_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ #ifdef CONFIG_STM32L5_UART4_SERIALDRIVER -static struct stm32l5_serial_s g_uart4priv = +static struct stm32_serial_s g_uart4priv = { .dev = { @@ -754,7 +754,7 @@ static struct stm32l5_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ #ifdef CONFIG_STM32L5_UART5_SERIALDRIVER -static struct stm32l5_serial_s g_uart5priv = +static struct stm32_serial_s g_uart5priv = { .dev = { @@ -815,7 +815,7 @@ static struct stm32l5_serial_s g_uart5priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32l5_serial_s * const +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { #ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER @@ -862,7 +862,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) +uint32_t stm32l5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -872,7 +872,7 @@ uint32_t stm32l5serial_getreg(struct stm32l5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32l5serial_putreg(struct stm32l5_serial_s *priv, +void stm32l5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -883,7 +883,7 @@ void stm32l5serial_putreg(struct stm32l5_serial_s *priv, ****************************************************************************/ static inline -void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, +void stm32l5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -911,7 +911,7 @@ void stm32l5serial_setusartint(struct stm32l5_serial_s *priv, * Name: up_restoreusartint ****************************************************************************/ -static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -927,7 +927,7 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, * Name: stm32l5serial_disableusartint ****************************************************************************/ -static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, +static void stm32l5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -988,11 +988,11 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) +static int stm32l5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32l5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -1009,8 +1009,8 @@ static int stm32l5serial_dmanextrx(struct stm32l5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32l5serial_setformat(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -1140,7 +1140,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -1159,7 +1159,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32l5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -1188,7 +1188,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1229,7 +1229,7 @@ static void stm32l5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32l5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1278,7 +1278,7 @@ static void stm32l5serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1304,8 +1304,8 @@ static void stm32l5serial_pm_setsuspend(bool suspend) static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1376,14 +1376,14 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32l5serial_setup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32l5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1394,18 +1394,18 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1419,15 +1419,15 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32l5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_configgpio(priv->rs485_dir_gpio); - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1502,8 +1502,8 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1520,14 +1520,14 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32l5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1538,7 +1538,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1565,7 +1565,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -1576,7 +1576,7 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -1595,8 +1595,8 @@ static int stm32l5serial_dmasetup(struct uart_dev_s *dev) static void stm32l5serial_shutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1627,32 +1627,32 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32l5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32l5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32l5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32l5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1669,8 +1669,8 @@ static void stm32l5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1678,11 +1678,11 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32l5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32l5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1705,8 +1705,8 @@ static void stm32l5serial_dmashutdown(struct uart_dev_s *dev) static int stm32l5serial_attach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1737,8 +1737,8 @@ static int stm32l5serial_attach(struct uart_dev_s *dev) static void stm32l5serial_detach(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1757,7 +1757,7 @@ static void stm32l5serial_detach(struct uart_dev_s *dev) static int stm32l5serial_interrupt(int irq, void *context, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1817,7 +1817,7 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32l5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1883,8 +1883,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1893,9 +1893,9 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32l5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32l5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1903,7 +1903,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32l5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1958,7 +1958,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1969,7 +1969,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32l5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -2195,7 +2195,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32l5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -2212,7 +2212,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32l5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2275,8 +2275,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, static int stm32l5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2305,8 +2305,8 @@ static int stm32l5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2365,8 +2365,8 @@ static void stm32l5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2400,8 +2400,8 @@ static bool stm32l5serial_rxavailable(struct uart_dev_s *dev) static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) @@ -2409,7 +2409,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32l5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2484,8 +2484,8 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32l5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32l5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2523,14 +2523,14 @@ static int stm32l5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) +static void stm32l5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2541,7 +2541,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32l5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2562,7 +2562,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, false); } else @@ -2573,7 +2573,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32l5_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32l5serial_dmarxcallback, (void *)priv, true); } @@ -2594,7 +2594,7 @@ static void stm32l5serial_dmareenable(struct stm32l5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) +static bool stm32l5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2645,8 +2645,8 @@ static bool stm32l5serial_dmaiflowrestart(struct stm32l5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2680,8 +2680,8 @@ static void stm32l5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2701,13 +2701,13 @@ static bool stm32l5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32l5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32l5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2724,8 +2724,8 @@ static void stm32l5serial_send(struct uart_dev_s *dev, int ch) static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2793,8 +2793,8 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32l5serial_txready(struct uart_dev_s *dev) { - struct stm32l5_serial_s *priv = - (struct stm32l5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32l5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); @@ -2813,7 +2813,7 @@ static bool stm32l5serial_txready(struct uart_dev_s *dev) static void stm32l5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32l5_serial_s *priv = (struct stm32l5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32l5serial_dmarxavailable(&priv->dev)) { @@ -2971,7 +2971,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32l5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2980,7 +2980,7 @@ static int stm32l5serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++) { - struct stm32l5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -3144,7 +3144,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -3155,7 +3155,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -3218,7 +3218,7 @@ void stm32l5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32l5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32l5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index 6fc62e9eaab..c1a374c8b91 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32l5_spi1/2/3select and stm32l5_spi1/2/3status + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/3select() and stm32l5_spi1/2/3status() + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your board * is configured. - * 3. Add a calls to stm32l5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32l5_spibus_initialize() may then be used to + * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -74,7 +74,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #ifdef CONFIG_STM32L5_SPI_DMA # include "stm32l5_dma.h" @@ -135,7 +135,7 @@ * Private Types ****************************************************************************/ -struct stm32l5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -176,34 +176,34 @@ struct stm32l5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv); -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv); -static void spi_dmatxwait(struct stm32l5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv); +static void spi_dmarxwait(struct stm32_spidev_s *priv); +static void spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -234,7 +234,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -251,16 +251,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32l5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -273,13 +273,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -309,16 +309,16 @@ static struct stm32l5_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32l5_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -331,13 +331,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -365,16 +365,16 @@ static struct stm32l5_spidev_s g_spi2dev = static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, - .select = stm32l5_spi3select, + .select = stm32_spi3select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32l5_spi3status, + .status = stm32_spi3status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32l5_spi3cmddata, + .cmddata = stm32_spi3cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -387,13 +387,13 @@ static const struct spi_ops_s g_spi3ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32l5_spi3register, /* provided externally */ + .registercallback = stm32_spi3register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32l5_spidev_s g_spi3dev = +static struct stm32_spidev_s g_spi3dev = { .spidev = { @@ -436,7 +436,7 @@ static struct stm32l5_spidev_s g_spi3dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -458,7 +458,7 @@ static inline uint16_t spi_getreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32l5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -479,7 +479,7 @@ static inline void spi_putreg(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -498,7 +498,7 @@ static inline uint8_t spi_getreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32l5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -518,7 +518,7 @@ static inline void spi_putreg8(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -543,7 +543,7 @@ static inline uint16_t spi_readword(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -569,7 +569,7 @@ static inline uint8_t spi_readbyte(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32l5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -596,7 +596,7 @@ static inline void spi_writeword(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32l5_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -622,7 +622,7 @@ static inline void spi_writebyte(struct stm32l5_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -636,7 +636,7 @@ static inline bool spi_16bitmode(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxwait(struct stm32l5_spidev_s *priv) +static void spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -667,7 +667,7 @@ static void spi_dmarxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxwait(struct stm32l5_spidev_s *priv) +static void spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -698,7 +698,7 @@ static void spi_dmatxwait(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -713,7 +713,7 @@ static inline void spi_dmarxwakeup(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -730,7 +730,7 @@ static inline void spi_dmatxwakeup(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32L5_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -750,7 +750,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32L5_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -768,7 +768,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -805,7 +805,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, /* Configure the RX DMA */ - stm32l5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -819,7 +819,7 @@ static void spi_dmarxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -856,7 +856,7 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, /* Setup the TX DMA */ - stm32l5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -870,10 +870,10 @@ static void spi_dmatxsetup(struct stm32l5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32l5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -886,10 +886,10 @@ static inline void spi_dmarxstart(struct stm32l5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI_DMA -static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32l5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -909,7 +909,7 @@ static inline void spi_dmatxstart(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -943,7 +943,7 @@ static void spi_modifycr(uint32_t addr, struct stm32l5_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -979,7 +979,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1087,7 +1087,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1155,7 +1155,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; int savbits = nbits; @@ -1225,7 +1225,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1289,7 +1289,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1363,7 +1363,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1464,13 +1464,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32l5_spidev_s *priv = (struct stm32l5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #ifdef CONFIG_STM32L5_DMACAPABLE if ((txbuffer && - !stm32l5_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && - !stm32l5_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1654,9 +1654,9 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32l5_spidev_s *priv = - (struct stm32l5_spidev_s *)((char *)cb - - offsetof(struct stm32l5_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = + (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1707,7 +1707,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32l5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1750,17 +1750,17 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) #ifdef CONFIG_STM32L5_SPI_DMA /* Get DMA channels. - * NOTE: stm32l5_dmachannel() will always assign the DMA channel. - * If the channel is not available, then stm32l5_dmachannel() will + * NOTE: stm32_dmachannel() will always assign the DMA channel. + * If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. * WARNING: If you have another device sharing a DMA channel with SPI and * the code never releases that channel, then the call to - * stm32l5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32l5_dmachannel(priv->rxch); - priv->txdma = stm32l5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1785,7 +1785,7 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1798,9 +1798,9 @@ static void spi_bus_initialize(struct stm32l5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32l5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1817,9 +1817,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI1_SCK); - stm32l5_configgpio(GPIO_SPI1_MISO); - stm32l5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1842,9 +1842,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI2_SCK); - stm32l5_configgpio(GPIO_SPI2_MISO); - stm32l5_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1867,9 +1867,9 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus) { /* Configure SPI3 pins: SCK, MISO, and MOSI */ - stm32l5_configgpio(GPIO_SPI3_SCK); - stm32l5_configgpio(GPIO_SPI3_MISO); - stm32l5_configgpio(GPIO_SPI3_MOSI); + stm32_configgpio(GPIO_SPI3_SCK); + stm32_configgpio(GPIO_SPI3_MISO); + stm32_configgpio(GPIO_SPI3_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index c13661243a8..005843df694 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32l5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32l5_spi1/2/...select and stm32l5_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32l5_spi1/2/...select, - * stm32l5_spi1/2/...status, and stm32l5_spi1/2/...cmddata must be provided + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be provided * by board-specific logic. These are implementations of the select, * status, and cmddata methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32l5_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32l5_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32l5_spi1/2/...select() and stm32l5_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32l5_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data * selection operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32l5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32l5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,28 +105,28 @@ struct spi_dev_s *stm32l5_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32L5_SPI1 -void stm32l5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L5_SPI2 -void stm32l5_spi2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32L5_SPI3 -void stm32l5_spi3select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32l5_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32l5_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -147,19 +147,19 @@ int stm32l5_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32L5_SPI1 -int stm32l5_spi1register(struct spi_dev_s *dev, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L5_SPI2 -int stm32l5_spi2register(struct spi_dev_s *dev, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32L5_SPI3 -int stm32l5_spi3register(struct spi_dev_s *dev, +int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 6978b6013b4..919e9edafea 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_userspace.h" #include "stm32l5_start.h" @@ -151,10 +151,10 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32l5_clockconfig(); + stm32_clockconfig(); arm_fpuconfig(); - stm32l5_lowsetup(); - stm32l5_gpioinit(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -205,13 +205,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32l5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32l5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32l5/stm32l5_start.h b/arch/arm/src/stm32l5/stm32l5_start.h index 11f34ab293a..45e47f28bf2 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.h +++ b/arch/arm/src/stm32l5/stm32l5_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_START_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 7e2d91bc1fd..509c9f3e9bb 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -40,7 +40,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32l5.h" +#include "stm32.h" #include "stm32l5_gpio.h" #include "stm32l5_tim.h" @@ -208,10 +208,10 @@ /* TIM Device Structure */ -struct stm32l5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32l5_tim_ops_s *ops; - enum stm32l5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -221,179 +221,179 @@ struct stm32l5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev); -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32l5_tim_getperiod(struct stm32l5_tim_dev_s *dev); -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev); -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32l5_tim_ops_s stm32l5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32l5_tim_enable, - .disable = stm32l5_tim_disable, - .setmode = stm32l5_tim_setmode, - .setclock = stm32l5_tim_setclock, - .getclock = stm32l5_tim_getclock, - .setperiod = stm32l5_tim_setperiod, - .getperiod = stm32l5_tim_getperiod, - .getcounter = stm32l5_tim_getcounter, - .setchannel = stm32l5_tim_setchannel, - .setcompare = stm32l5_tim_setcompare, - .getcapture = stm32l5_tim_getcapture, - .setisr = stm32l5_tim_setisr, - .enableint = stm32l5_tim_enableint, - .disableint = stm32l5_tim_disableint, - .ackint = stm32l5_tim_ackint, - .checkint = stm32l5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; #ifdef CONFIG_STM32L5_TIM1 -struct stm32l5_tim_priv_s stm32l5_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM2 -struct stm32l5_tim_priv_s stm32l5_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM3 -struct stm32l5_tim_priv_s stm32l5_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM4 -struct stm32l5_tim_priv_s stm32l5_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM5 -struct stm32l5_tim_priv_s stm32l5_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM6 -struct stm32l5_tim_priv_s stm32l5_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM7 -struct stm32l5_tim_priv_s stm32l5_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM8 -struct stm32l5_tim_priv_s stm32l5_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM15 -struct stm32l5_tim_priv_s stm32l5_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM16 -struct stm32l5_tim_priv_s stm32l5_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32L5_TIM17 -struct stm32l5_tim_priv_s stm32l5_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32l5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -404,51 +404,51 @@ struct stm32l5_tim_priv_s stm32l5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32l5_getreg16(struct stm32l5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_putreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32l5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32l5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -456,14 +456,14 @@ static inline void stm32l5_modifyreg16(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32l5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -471,48 +471,48 @@ static inline uint32_t stm32l5_getreg32(struct stm32l5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32l5_putreg32(struct stm32l5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32l5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32l5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32l5_tim_reload_counter(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32l5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32l5_tim_enable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32l5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32l5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -520,14 +520,14 @@ static void stm32l5_tim_disable(struct stm32l5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32l5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32l5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -535,28 +535,28 @@ static void stm32l5_tim_reset(struct stm32l5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32l5_tim_gpioconfig(uint32_t cfg, - enum stm32l5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ if (mode & STM32_TIM_CH_MODE_MASK) { - stm32l5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32l5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32l5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -567,10 +567,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -610,16 +610,16 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, return -EINVAL; } - stm32l5_tim_reload_counter(dev); - stm32l5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32l5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -627,10 +627,10 @@ static int stm32l5_tim_setmode(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -642,7 +642,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, if (freq == 0) { - stm32l5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -652,7 +652,7 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -745,17 +745,17 @@ static int stm32l5_tim_setclock(struct stm32l5_tim_dev_s *dev, prescaler = 0xffff; } - stm32l5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32l5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32l5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -767,7 +767,7 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -837,46 +837,46 @@ static uint32_t stm32l5_tim_getclock(struct stm32l5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32l5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32l5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32l5_tim_setperiod(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32l5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32l5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32l5_tim_getperiod (struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32l5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32l5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32l5_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5) - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM2 case STM32_TIM2_BASE: @@ -895,12 +895,12 @@ static uint32_t stm32l5_tim_getcounter(struct stm32l5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32l5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -919,7 +919,7 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32l5_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -928,10 +928,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32l5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -977,15 +977,15 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32l5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32l5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32l5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -993,25 +993,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1026,25 +1026,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1059,25 +1059,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1092,24 +1092,24 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1124,25 +1124,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1157,25 +1157,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1190,25 +1190,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1223,25 +1223,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1256,25 +1256,25 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32l5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1292,10 +1292,10 @@ static int stm32l5_tim_setchannel(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1303,19 +1303,19 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - stm32l5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32l5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32l5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32l5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1326,10 +1326,10 @@ static int stm32l5_tim_setcompare(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1337,26 +1337,26 @@ static int stm32l5_tim_getcapture(struct stm32l5_tim_dev_s *dev, switch (channel) { case 1: - return stm32l5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32l5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32l5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32l5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32l5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1364,7 +1364,7 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -1452,44 +1452,44 @@ static int stm32l5_tim_setisr(struct stm32l5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32l5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32l5_tim_enableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32l5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32l5_tim_disableint(struct stm32l5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32l5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32l5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32l5_tim_ackint(struct stm32l5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32l5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32l5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32l5_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1498,12 +1498,12 @@ static int stm32l5_tim_checkint(struct stm32l5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32l5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1511,76 +1511,76 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) { #ifdef CONFIG_STM32L5_TIM1 case 1: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32L5_TIM2 case 2: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32L5_TIM3 case 3: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32L5_TIM4 case 4: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32L5_TIM5 case 5: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32L5_TIM6 case 6: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32L5_TIM7 case 7: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32L5_TIM8 case 8: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32L5_TIM15 case 15: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32L5_TIM16 case 16: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32L5_TIM17 case 17: - dev = (struct stm32l5_tim_dev_s *)&stm32l5_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1591,30 +1591,30 @@ struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32l5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32l5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32l5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32l5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32L5_TIM1 case STM32_TIM1_BASE: @@ -1687,7 +1687,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32l5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32l5/stm32l5_tim.h b/arch/arm/src/stm32l5/stm32l5_tim.h index 9e420265f79..5a787e122f0 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.h +++ b/arch/arm/src/stm32l5/stm32l5_tim.h @@ -72,14 +72,14 @@ extern "C" /* TIM Device Structure */ -struct stm32l5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32l5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32l5_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -116,7 +116,7 @@ enum stm32l5_tim_mode_e /* TIM Channel Modes */ -enum stm32l5_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -147,36 +147,36 @@ enum stm32l5_tim_channel_e /* TIM Operations */ -struct stm32l5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32l5_tim_dev_s *dev); - void (*disable)(struct stm32l5_tim_dev_s *dev); - int (*setmode)(struct stm32l5_tim_dev_s *dev, - enum stm32l5_tim_mode_e mode); - int (*setclock)(struct stm32l5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32l5_tim_dev_s *dev); - void (*setperiod)(struct stm32l5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32l5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32l5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32l5_tim_dev_s *dev, uint8_t channel, - enum stm32l5_tim_channel_e mode); - int (*setcompare)(struct stm32l5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32l5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32l5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32l5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32l5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32l5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -185,14 +185,14 @@ struct stm32l5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32l5_tim_dev_s *stm32l5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -210,7 +210,7 @@ int stm32l5_tim_deinit(struct stm32l5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32l5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index b5e7ebcf759..bc5367fa376 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32l5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32l5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32l5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower); -static int stm32l5_stop(struct timer_lowerhalf_s *lower); -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,16 +110,16 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32l5_start, - .stop = stm32l5_stop, - .getstatus = stm32l5_getstatus, - .settimeout = stm32l5_settimeout, - .setcallback = stm32l5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32L5_TIM1 -static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -127,7 +127,7 @@ static struct stm32l5_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM2 -static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -135,7 +135,7 @@ static struct stm32l5_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM3 -static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -143,7 +143,7 @@ static struct stm32l5_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM4 -static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -151,7 +151,7 @@ static struct stm32l5_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM5 -static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -159,7 +159,7 @@ static struct stm32l5_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM6 -static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -167,7 +167,7 @@ static struct stm32l5_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM7 -static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -175,7 +175,7 @@ static struct stm32l5_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM8 -static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -183,7 +183,7 @@ static struct stm32l5_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM15 -static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -191,7 +191,7 @@ static struct stm32l5_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM16 -static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -199,7 +199,7 @@ static struct stm32l5_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32L5_TIM17 -static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -211,7 +211,7 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,10 +222,10 @@ static struct stm32l5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32l5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32l5_lowerhalf_s *lower = - (struct stm32l5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -239,14 +239,14 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) } else { - stm32l5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32l5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,10 +260,10 @@ static int stm32l5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32l5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -271,7 +271,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -285,7 +285,7 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,10 +299,10 @@ static int stm32l5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -319,7 +319,7 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32l5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32l5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -386,7 +386,7 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32l5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -430,7 +430,7 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32l5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32l5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32l5_lowerhalf_s *priv = - (struct stm32l5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,7 +463,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32l5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -480,7 +480,7 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,9 +497,9 @@ static void stm32l5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32l5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32l5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -576,7 +576,7 @@ int stm32l5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32l5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32l5/stm32l5_timerisr.c b/arch/arm/src/stm32l5/stm32l5_timerisr.c index 85089050ec0..169200141ce 100644 --- a/arch/arm/src/stm32l5/stm32l5_timerisr.c +++ b/arch/arm/src/stm32l5/stm32l5_timerisr.c @@ -37,7 +37,7 @@ #include "clock/clock.h" #include "arm_internal.h" #include "chip.h" -#include "stm32l5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32l5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -87,7 +87,7 @@ * ****************************************************************************/ -static int stm32l5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -137,7 +137,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32l5_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index 07fb79ab2bc..30bbad7b7bc 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -275,7 +275,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -288,7 +288,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32l5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32l5/stm32l5_uid.c b/arch/arm/src/stm32l5/stm32l5_uid.c index 1b354bc4b7b..762f4e0c631 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.c +++ b/arch/arm/src/stm32l5/stm32l5_uid.c @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32l5/stm32l5_uid.h b/arch/arm/src/stm32l5/stm32l5_uid.h index 6113ef1edd0..c71e4c43fd9 100644 --- a/arch/arm/src/stm32l5/stm32l5_uid.h +++ b/arch/arm/src/stm32l5/stm32l5_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32l5_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_UID_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.c b/arch/arm/src/stm32l5/stm32l5_userspace.c index 7b97d5b6b64..bd7d6944ab8 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.c +++ b/arch/arm/src/stm32l5/stm32l5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32l5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32l5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32l5/stm32l5_userspace.h b/arch/arm/src/stm32l5/stm32l5_userspace.h index 0e6d63d68a6..523b8c1b62b 100644 --- a/arch/arm/src/stm32l5/stm32l5_userspace.h +++ b/arch/arm/src/stm32l5/stm32l5_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32l5_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32L5_STM32L5_USERSPACE_H */ diff --git a/arch/arm/src/stm32l5/stm32l5_waste.c b/arch/arm/src/stm32l5/stm32l5_waste.c index 7a6a60bc8e6..5d0055c04bb 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.c +++ b/arch/arm/src/stm32l5/stm32l5_waste.c @@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0; * Public Functions ****************************************************************************/ -void stm32l5_waste(void) +void stm32_waste(void) { idle_wastecounter++; } diff --git a/arch/arm/src/stm32l5/stm32l5_waste.h b/arch/arm/src/stm32l5/stm32l5_waste.h index e9fe2209dfc..2f7b068ed28 100644 --- a/arch/arm/src/stm32l5/stm32l5_waste.h +++ b/arch/arm/src/stm32l5/stm32l5_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32l5_waste() is the logic that will be executed when portions of kernel + * stm32_waste() is the logic that will be executed when portions of kernel * or user-app is polling some register or similar, waiting for desired * status. This time is wasted away. This function offers a measure of badly * written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32l5_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 86a474e5a64..26c4c29257a 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -262,7 +262,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -272,7 +272,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c index 012f7938fbd..f27e0286dd9 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_autoleds.c @@ -64,7 +64,7 @@ static void phy_set_led(int led, bool state) { /* Active High */ - stm32l5_gpiowrite(g_ledmap[led], state); + stm32_gpiowrite(g_ledmap[led], state); } /**************************************************************************** @@ -83,7 +83,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 05cd210fce0..218995b6634 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -42,7 +42,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -52,18 +52,18 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #if defined(CONFIG_STM32L5_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in - * stm32l5_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes + * stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. */ - stm32l5_configgpio(GPIO_LPUART1_TX); - stm32l5_configgpio(GPIO_LPUART1_RX); + stm32_configgpio(GPIO_LPUART1_TX); + stm32_configgpio(GPIO_LPUART1_RX); #endif #ifdef CONFIG_ARCH_LEDS diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c index 0ade669c511..429c818dd11 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c index f13c4b5f627..8318cb30f2c 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_userleds.c @@ -77,7 +77,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -97,7 +97,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], ledon); + stm32_gpiowrite(g_ledcfg[led], ledon); } } @@ -119,7 +119,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/include/board.h b/boards/arm/stm32l5/stm32l562e-dk/include/board.h index 256110d0743..a5039f79e34 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/include/board.h +++ b/boards/arm/stm32l5/stm32l562e-dk/include/board.h @@ -185,7 +185,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32L5 architectures must provide the following entry point. @@ -195,7 +195,7 @@ extern "C" * ****************************************************************************/ -void stm32l5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c index 0206ca6ca48..4d3dd824946 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_autoleds.c @@ -63,7 +63,7 @@ static void phy_set_led(int led, bool state) { /* Active Low */ - stm32l5_gpiowrite(g_ledmap[led], !state); + stm32_gpiowrite(g_ledmap[led], !state); } /**************************************************************************** @@ -82,7 +82,7 @@ void board_autoled_initialize(void) for (i = 0; i < nitems(g_ledmap); i++) { - stm32l5_configgpio(g_ledmap[i]); + stm32_configgpio(g_ledmap[i]); } } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c index 9f40e9807a7..458aab58733 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_boot.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32l5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32 architectures must provide the following entry point. This @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32l5_board_initialize(void) +void stm32_board_initialize(void) { /* On the STM32L562E-DK Vddio2 is supplied by Vdd_mcu. Thus, when the MCU * is running Vddio2 is guaranteed to be valid. LED LD10 is driven by @@ -59,7 +59,7 @@ void stm32l5_board_initialize(void) * Vddio2 to be valid here. */ - stm32l5_pwr_vddio2_valid(true); + stm32_pwr_vddio2_valid(true); #ifdef CONFIG_ARCH_LEDS /* Configure on-board LEDs if LED support has been selected. */ diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c index 133fb020e88..3091f179081 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_buttons.c @@ -61,7 +61,7 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32l5_configgpio(GPIO_BTN_USER); + stm32_configgpio(GPIO_BTN_USER); return NUM_BUTTONS; } @@ -73,7 +73,7 @@ uint32_t board_buttons(void) { /* Check the state of the USER button. */ - return stm32l5_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; + return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0; } /**************************************************************************** @@ -105,7 +105,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BUTTON_USER) { - ret = stm32l5_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, + ret = stm32_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg); } diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index 170aab2fe92..4dd66b53512 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -44,7 +44,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) -void stm32l5_board_clockconfig(void) +void stm32_board_clockconfig(void) { } #endif diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c index 97342f1dfe8..fa01c257261 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_userleds.c @@ -76,7 +76,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_configgpio(g_ledcfg[i]); + stm32_configgpio(g_ledcfg[i]); } return BOARD_NLEDS; @@ -96,7 +96,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < nitems(g_ledcfg)) { - stm32l5_gpiowrite(g_ledcfg[led], !ledon); + stm32_gpiowrite(g_ledcfg[led], !ledon); } } @@ -118,7 +118,7 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < nitems(g_ledcfg); i++) { - stm32l5_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); + stm32_gpiowrite(g_ledcfg[i], !(ledset & (1 << i))); } } From 6e7db8dadab22d213392a3daad572d5ef289e6ca Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:52 +0200 Subject: [PATCH 069/268] !arm/stm32wb: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32WB interfaces were renamed from stm32wb_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32WB timer/dma/freerun/oneshot/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32WB root family header was renamed from stm32wb.h to stm32.h; all STM32WB arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32wb/{stm32wb.h => stm32.h} | 2 +- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 6 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 62 +- arch/arm/src/stm32wb/stm32wb_blehci.h | 4 +- arch/arm/src/stm32wb/stm32wb_dma.c | 196 +++--- arch/arm/src/stm32wb/stm32wb_dma.h | 60 +- arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 4 +- arch/arm/src/stm32wb/stm32wb_exti.h | 12 +- arch/arm/src/stm32wb/stm32wb_exti_alarm.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_gpio.c | 40 +- arch/arm/src/stm32wb/stm32wb_exti_pwr.c | 10 +- arch/arm/src/stm32wb/stm32wb_exti_wakeup.c | 10 +- arch/arm/src/stm32wb/stm32wb_flash.c | 16 +- arch/arm/src/stm32wb/stm32wb_flash.h | 8 +- arch/arm/src/stm32wb/stm32wb_freerun.c | 32 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 26 +- arch/arm/src/stm32wb/stm32wb_gpio.c | 28 +- arch/arm/src/stm32wb/stm32wb_gpio.h | 36 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 516 ++++++++-------- arch/arm/src/stm32wb/stm32wb_i2c.h | 10 +- arch/arm/src/stm32wb/stm32wb_idle.c | 6 +- arch/arm/src/stm32wb/stm32wb_ipcc.c | 8 +- arch/arm/src/stm32wb/stm32wb_ipcc.h | 36 +- arch/arm/src/stm32wb/stm32wb_irq.c | 38 +- arch/arm/src/stm32wb/stm32wb_lowputc.c | 20 +- arch/arm/src/stm32wb/stm32wb_lowputc.h | 4 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 330 +++++----- arch/arm/src/stm32wb/stm32wb_mbox.h | 32 +- arch/arm/src/stm32wb/stm32wb_mbox_list.h | 36 +- arch/arm/src/stm32wb/stm32wb_mbox_shci.h | 2 +- arch/arm/src/stm32wb/stm32wb_mpuinit.c | 8 +- arch/arm/src/stm32wb/stm32wb_mpuinit.h | 12 +- arch/arm/src/stm32wb/stm32wb_oneshot.c | 42 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 28 +- .../src/stm32wb/stm32wb_oneshot_lowerhalf.c | 78 +-- arch/arm/src/stm32wb/stm32wb_pm.h | 20 +- arch/arm/src/stm32wb/stm32wb_pmlpr.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmsleep.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstandby.c | 4 +- arch/arm/src/stm32wb/stm32wb_pmstop.c | 8 +- arch/arm/src/stm32wb/stm32wb_pwr.c | 26 +- arch/arm/src/stm32wb/stm32wb_pwr.h | 8 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 40 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c | 8 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 10 +- arch/arm/src/stm32wb/stm32wb_rcc_lsi.c | 8 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 90 +-- arch/arm/src/stm32wb/stm32wb_rtc.h | 42 +- arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c | 152 ++--- arch/arm/src/stm32wb/stm32wb_serial.c | 574 +++++++++--------- arch/arm/src/stm32wb/stm32wb_spi.c | 166 ++--- arch/arm/src/stm32wb/stm32wb_spi.h | 40 +- arch/arm/src/stm32wb/stm32wb_start.c | 12 +- arch/arm/src/stm32wb/stm32wb_start.h | 4 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 94 +-- arch/arm/src/stm32wb/stm32wb_tim.c | 436 ++++++------- arch/arm/src/stm32wb/stm32wb_tim.h | 60 +- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 84 +-- arch/arm/src/stm32wb/stm32wb_timerisr.c | 6 +- arch/arm/src/stm32wb/stm32wb_uart.h | 4 +- arch/arm/src/stm32wb/stm32wb_uid.c | 2 +- arch/arm/src/stm32wb/stm32wb_uid.h | 2 +- arch/arm/src/stm32wb/stm32wb_userspace.c | 6 +- arch/arm/src/stm32wb/stm32wb_userspace.h | 4 +- arch/arm/src/stm32wb/stm32wb_waste.c | 2 +- arch/arm/src/stm32wb/stm32wb_waste.h | 4 +- .../arm/stm32wb/flipperzero/include/board.h | 4 +- .../arm/stm32wb/flipperzero/src/flipperzero.h | 4 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 16 +- .../flipperzero/src/stm32_lcd_st7565.c | 54 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 28 +- .../arm/stm32wb/nucleo-wb55rg/include/board.h | 4 +- .../nucleo-wb55rg/src/stm32_autoleds.c | 20 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 12 +- .../nucleo-wb55rg/src/stm32_userleds.c | 32 +- 76 files changed, 1954 insertions(+), 1954 deletions(-) rename arch/arm/src/stm32wb/{stm32wb.h => stm32.h} (98%) diff --git a/arch/arm/src/stm32wb/stm32wb.h b/arch/arm/src/stm32wb/stm32.h similarity index 98% rename from arch/arm/src/stm32wb/stm32wb.h rename to arch/arm/src/stm32wb/stm32.h index 25327d74d90..539f3eb9ea4 100644 --- a/arch/arm/src/stm32wb/stm32wb.h +++ b/arch/arm/src/stm32wb/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wb/stm32wb.h + * arch/arm/src/stm32wb/stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index fb2f6dc9451..d22ff6b51de 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -201,7 +201,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wb_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -289,7 +289,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2a heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); + stm32_mpu_uheap((uintptr_t)SRAM2A_START, SRAM2A_END - SRAM2A_START); #endif @@ -309,7 +309,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2b heap */ - stm32wb_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); + stm32_mpu_uheap((uintptr_t)SRAM2B_START, SRAM2B_END - SRAM2B_START); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 3b41a7bee2c..7b69d9b314f 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -106,14 +106,14 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev); -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driveropen(struct bt_driver_s *btdev); +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len); -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt); -static void stm32wb_blehci_bleinit(void); -static int stm32wb_blehci_driverinitialize(void); -static void stm32wb_blehci_drvinitworker(void *arg); +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt); +static void stm32_blehci_bleinit(void); +static int stm32_blehci_driverinitialize(void); +static void stm32_blehci_drvinitworker(void *arg); /**************************************************************************** * Private Data @@ -122,8 +122,8 @@ static void stm32wb_blehci_drvinitworker(void *arg); static struct bt_driver_s g_blehci_driver = { .head_reserve = 0, - .open = stm32wb_blehci_driveropen, - .send = stm32wb_blehci_driversend + .open = stm32_blehci_driveropen, + .send = stm32_blehci_driversend }; static mutex_t g_lock = NXMUTEX_INITIALIZER; @@ -134,19 +134,19 @@ struct work_s g_drv_init_work; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_driveropen + * Name: stm32_blehci_driveropen ****************************************************************************/ -static int stm32wb_blehci_driveropen(struct bt_driver_s *btdev) +static int stm32_blehci_driveropen(struct bt_driver_s *btdev) { return 0; } /**************************************************************************** - * Name: stm32wb_blehci_driversend + * Name: stm32_blehci_driversend ****************************************************************************/ -static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, +static int stm32_blehci_driversend(struct bt_driver_s *btdev, enum bt_buf_type_e type, void *data, size_t len) { @@ -177,11 +177,11 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, if (type == BT_CMD) { - ret = stm32wb_mbox_blecmd(data, len); + ret = stm32_mbox_blecmd(data, len); } else { - ret = stm32wb_mbox_bleacl(data, len); + ret = stm32_mbox_bleacl(data, len); } nxmutex_unlock(&g_lock); @@ -191,10 +191,10 @@ static int stm32wb_blehci_driversend(struct bt_driver_s *btdev, } /**************************************************************************** - * Name: stm32wb_blehci_rxevt + * Name: stm32_blehci_rxevt ****************************************************************************/ -static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) +static int stm32_blehci_rxevt(struct stm32_mbox_evt_s *evt) { size_t len; @@ -259,7 +259,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) if (evt->evt_hdr.evt == STM32_SHCI_ASYNC_EVT && *(uint16_t *)(&evt->evt_hdr + 1) == STM32_SHCI_ASYNC_EVT_C2RDY) { - stm32wb_blehci_bleinit(); + stm32_blehci_bleinit(); } break; @@ -276,7 +276,7 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) /* Make driver initialisation in low priority work queue */ work_queue(LPWORK, &g_drv_init_work, - stm32wb_blehci_drvinitworker, NULL, 0); + stm32_blehci_drvinitworker, NULL, 0); } break; @@ -288,14 +288,14 @@ static int stm32wb_blehci_rxevt(struct stm32wb_mbox_evt_s *evt) } /**************************************************************************** - * Name: stm32wb_blehci_bleinit + * Name: stm32_blehci_bleinit ****************************************************************************/ -static void stm32wb_blehci_bleinit(void) +static void stm32_blehci_bleinit(void) { /* Prepare BLE configuration */ - struct stm32wb_shci_ble_init_cfg_s params = + struct stm32_shci_ble_init_cfg_s params = { .ble_buf = NULL, .ble_buf_size = 0, @@ -323,14 +323,14 @@ static void stm32wb_blehci_bleinit(void) /* Initialise BLE */ - stm32wb_mbox_bleinit(¶ms); + stm32_mbox_bleinit(¶ms); } /**************************************************************************** - * Name: stm32wb_blehci_driverinitialize + * Name: stm32_blehci_driverinitialize ****************************************************************************/ -static int stm32wb_blehci_driverinitialize(void) +static int stm32_blehci_driverinitialize(void) { int ret = 0; @@ -345,12 +345,12 @@ static int stm32wb_blehci_driverinitialize(void) } /**************************************************************************** - * Name: stm32wb_blehci_drvinitworker + * Name: stm32_blehci_drvinitworker ****************************************************************************/ -static void stm32wb_blehci_drvinitworker(void *arg) +static void stm32_blehci_drvinitworker(void *arg) { - stm32wb_blehci_driverinitialize(); + stm32_blehci_driverinitialize(); } /**************************************************************************** @@ -358,7 +358,7 @@ static void stm32wb_blehci_drvinitworker(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -367,15 +367,15 @@ static void stm32wb_blehci_drvinitworker(void *arg) * ****************************************************************************/ -void stm32wb_blehci_initialize(void) +void stm32_blehci_initialize(void) { /* Initialize mbox internal data structures and set * event receive handler. */ - stm32wb_mboxinitialize(stm32wb_blehci_rxevt); + stm32_mboxinitialize(stm32_blehci_rxevt); /* Enable communication hardware and boot up CPU2 */ - stm32wb_mboxenable(); + stm32_mboxenable(); } diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.h b/arch/arm/src/stm32wb/stm32wb_blehci.h index a8d5f6229d5..01b93c012d5 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.h +++ b/arch/arm/src/stm32wb/stm32wb_blehci.h @@ -50,7 +50,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_blehci_initialize + * Name: stm32_blehci_initialize * * Description: * Initialize and register BLE HCI driver which interfaces a BLE host @@ -59,7 +59,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_blehci_initialize(void); +void stm32_blehci_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index 9789c80b45c..d8674fd279c 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -75,20 +75,20 @@ /* This structure described one DMAMUX device */ -struct stm32wb_dmamux_s +struct stm32_dmamux_s { uint8_t id; /* DMAMUX id */ uint8_t nchan; /* DMAMUX channels */ uint32_t base; /* DMAMUX base address */ }; -typedef const struct stm32wb_dmamux_s *DMA_MUX; +typedef const struct stm32_dmamux_s *DMA_MUX; /* This structure describes one DMA controller */ -struct stm32wb_dma_s +struct stm32_dma_s { - uint8_t first; /* Offset in stm32wb_dmach_s array */ + uint8_t first; /* Offset in stm32_dmach_s array */ uint8_t nchan; /* Number of channels */ uint8_t dmamux_offset; /* DMAMUX channel offset */ uint32_t base; /* Base address */ @@ -97,7 +97,7 @@ struct stm32wb_dma_s /* This structure describes one DMA channel (DMA1, DMA2) */ -struct stm32wb_dmach_s +struct stm32_dmach_s { bool used; /* Channel in use */ uint8_t dmamux_req; /* Configured DMAMUX input request */ @@ -110,11 +110,11 @@ struct stm32wb_dmach_s void *arg; /* Argument passed to callback function */ }; -typedef struct stm32wb_dmach_s *DMA_CHANNEL; +typedef struct stm32_dmach_s *DMA_CHANNEL; /* DMA operations */ -struct stm32wb_dma_ops_s +struct stm32_dma_ops_s { /* Disable the DMA transfer */ @@ -145,12 +145,12 @@ struct stm32wb_dma_ops_s #ifdef CONFIG_DEBUG_DMA_INFO /* Sample the DMA registers */ - void (*dma_sample)(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); + void (*dma_sample)(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); /* Dump the DMA registers */ void (*dma_dump)(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, + const struct stm32_dmaregs_s *regs, const char *msg); #endif }; @@ -160,19 +160,19 @@ struct stm32wb_dma_ops_s ****************************************************************************/ #if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan); -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg); -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_disable(DMA_CHANNEL dmachan); +static int stm32_dma12_interrupt(int irq, void *context, void *arg); +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); -static size_t stm32wb_dma12_residual(DMA_HANDLE handle); +static size_t stm32_dma12_residual(DMA_HANDLE handle); #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_sample(DMA_HANDLE handle, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_sample(DMA_HANDLE handle, + struct stm32_dmaregs_s *regs); +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg); #endif #endif @@ -187,14 +187,14 @@ static void dmachan_putreg(DMA_CHANNEL dmachan, uint32_t offset, static void dmamux_putreg(DMA_MUX dmamux, uint32_t offset, uint32_t value); #ifdef CONFIG_DEBUG_DMA_INFO static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset); -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs); -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs); +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs); +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs); #endif -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller); -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *last); /**************************************************************************** @@ -203,20 +203,20 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, /* Operations specific to DMA controller */ -static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = +static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { #ifdef CONFIG_STM32WB_DMA1 /* 0 - DMA1 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif }, #else @@ -229,14 +229,14 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* 1 - DMA2 */ { - .dma_disable = stm32wb_dma12_disable, - .dma_interrupt = stm32wb_dma12_interrupt, - .dma_setup = stm32wb_dma12_setup, - .dma_start = stm32wb_dma12_start, - .dma_residual = stm32wb_dma12_residual, + .dma_disable = stm32_dma12_disable, + .dma_interrupt = stm32_dma12_interrupt, + .dma_setup = stm32_dma12_setup, + .dma_start = stm32_dma12_start, + .dma_residual = stm32_dma12_residual, #ifdef CONFIG_DEBUG_DMA_INFO - .dma_sample = stm32wb_dma12_sample, - .dma_dump = stm32wb_dma12_dump, + .dma_sample = stm32_dma12_sample, + .dma_dump = stm32_dma12_dump, #endif } #else @@ -248,7 +248,7 @@ static const struct stm32wb_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = /* This array describes the state of DMAMUX controller */ -static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = +static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = { { .id = 1, @@ -259,7 +259,7 @@ static const struct stm32wb_dmamux_s g_dmamux[DMAMUX_NUM] = /* This array describes the state of each controller */ -static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = +static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { /* 0 - DMA1 */ @@ -284,7 +284,7 @@ static const struct stm32wb_dma_s g_dma[DMA_NCHANNELS] = /* This array describes the state of each DMA channel. */ -static struct stm32wb_dmach_s g_dmach[DMA_NCHANNELS] = +static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { #ifdef CONFIG_STM32WB_DMA1 /* DMA1 */ @@ -517,7 +517,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) #endif /**************************************************************************** - * Name: stm32wb_dma_channel_get + * Name: stm32_dma_channel_get * * Description: * Get the g_dmach table entry associated with a given DMA controller @@ -525,7 +525,7 @@ static uint32_t dmamux_getreg(DMA_MUX dmamux, uint32_t offset) * ****************************************************************************/ -static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, +static DMA_CHANNEL stm32_dma_channel_get(uint8_t channel, uint8_t controller) { uint8_t first = 0; @@ -533,7 +533,7 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, /* Get limits for g_dma array */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); DEBUGASSERT(channel <= nchan); @@ -541,14 +541,14 @@ static DMA_CHANNEL stm32wb_dma_channel_get(uint8_t channel, } /**************************************************************************** - * Name: stm32wb_gdma_limits_get + * Name: stm32_gdma_limits_get * * Description: * Get g_dma array limits for a given DMA controller. * ****************************************************************************/ -static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, +static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, uint8_t *nchan) { DEBUGASSERT(first != NULL); @@ -567,14 +567,14 @@ static void stm32wb_gdma_limits_get(uint8_t controller, uint8_t *first, #if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) /**************************************************************************** - * Name: stm32wb_dma12_disable + * Name: stm32_dma12_disable * * Description: * Disable DMA channel (DMA1/DMA2) * ****************************************************************************/ -static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) +static void stm32_dma12_disable(DMA_CHANNEL dmachan) { uint32_t regval; @@ -597,14 +597,14 @@ static void stm32wb_dma12_disable(DMA_CHANNEL dmachan) } /**************************************************************************** - * Name: stm32wb_dma12_interrupt + * Name: stm32_dma12_interrupt * * Description: * DMA channel interrupt handler * ****************************************************************************/ -static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) +static int stm32_dma12_interrupt(int irq, void *context, void *arg) { DMA_CHANNEL dmachan; uint32_t isr; @@ -643,7 +643,7 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) /* Get the channel structure from the stream and controller numbers */ - dmachan = stm32wb_dma_channel_get(channel, controller); + dmachan = stm32_dma_channel_get(channel, controller); /* Get the interrupt status (for this channel only) */ @@ -666,14 +666,14 @@ static int stm32wb_dma12_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_dma12_setup + * Name: stm32_dma12_setup * * Description: * Configure DMA before using * ****************************************************************************/ -static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, +static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { @@ -738,13 +738,13 @@ static void stm32wb_dma12_setup(DMA_HANDLE handle, uint32_t paddr, } /**************************************************************************** - * Name: stm32wb_dma12_start + * Name: stm32_dma12_start * * Description: * Start the standard DMA transfer ****************************************************************************/ -static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, +static void stm32_dma12_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -800,10 +800,10 @@ static void stm32wb_dma12_start(DMA_HANDLE handle, dma_callback_t callback, } /**************************************************************************** - * Name: stm32wb_dma12_residual + * Name: stm32_dma12_residual ****************************************************************************/ -static size_t stm32wb_dma12_residual(DMA_HANDLE handle) +static size_t stm32_dma12_residual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -813,11 +813,11 @@ static size_t stm32wb_dma12_residual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dma12_sample + * Name: stm32_dma12_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dma12_sample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; irqstate_t flags; @@ -830,7 +830,7 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) regs->cpar = dmachan_getreg(dmachan, STM32_DMACHAN_CPAR_OFFSET); regs->cmar = dmachan_getreg(dmachan, STM32_DMACHAN_CMAR_OFFSET); - stm32wb_dmamux_sample(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_sample(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); @@ -839,12 +839,12 @@ void stm32wb_dma12_sample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dma12_dump + * Name: stm32_dma12_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dma12_dump(DMA_HANDLE handle, - const struct stm32wb_dmaregs_s *regs, +static void stm32_dma12_dump(DMA_HANDLE handle, + const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -872,7 +872,7 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, dmachan->base + STM32_DMACHAN_CMAR_OFFSET, regs->cmar); - stm32wb_dmamux_dump(g_dma[dmachan->ctrl].dmamux, + stm32_dmamux_dump(g_dma[dmachan->ctrl].dmamux, dmachan->chan + g_dma[dmachan->ctrl].dmamux_offset, regs); } @@ -881,12 +881,12 @@ static void stm32wb_dma12_dump(DMA_HANDLE handle, #endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ /**************************************************************************** - * Name: stm32wb_dmamux_sample + * Name: stm32_dmamux_sample ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, - struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_sample(DMA_MUX dmamux, uint8_t chan, + struct stm32_dmaregs_s *regs) { regs->dmamux.ccr = dmamux_getreg(dmamux, STM32_DMAMUX_CXCR_OFFSET(chan)); regs->dmamux.csr = dmamux_getreg(dmamux, STM32_DMAMUX_CSR_OFFSET); @@ -899,12 +899,12 @@ static void stm32wb_dmamux_sample(DMA_MUX dmamux, uint8_t chan, #endif /**************************************************************************** - * Name: stm32wb_dmamux_dump + * Name: stm32_dmamux_dump ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -static void stm32wb_dmamux_dump(DMA_MUX dmamux, uint8_t channel, - const struct stm32wb_dmaregs_s *regs) +static void stm32_dmamux_dump(DMA_MUX dmamux, uint8_t channel, + const struct stm32_dmaregs_s *regs) { dmainfo("DMAMUX%d CH=%d\n", dmamux->id, channel); dmainfo(" CCR[%08x]: %08x\n", @@ -980,7 +980,7 @@ void weak_function arm_dma_initialize(void) } /**************************************************************************** - * Name: stm32wb_dmachannel + * Name: stm32_dmachannel * * Description: * Allocate a DMA channel. This function gives the caller mutually @@ -1004,7 +1004,7 @@ void weak_function arm_dma_initialize(void) * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) +DMA_HANDLE stm32_dmachannel(unsigned int dmamap) { DMA_CHANNEL dmachan; uint8_t dmamux_req; @@ -1026,7 +1026,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) /* Get g_dma array limits for given controller */ - stm32wb_gdma_limits_get(controller, &first, &nchan); + stm32_gdma_limits_get(controller, &first, &nchan); /* Find available channel for given controller */ @@ -1070,13 +1070,13 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) } /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel and unmap DMAMUX if required. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to the + * until stm32_dmachannel() is called again to re-gain access to the * channel. * * Returned Value: @@ -1088,7 +1088,7 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap) * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle) +void stm32_dmafree(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1114,14 +1114,14 @@ void stm32wb_dmafree(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1138,18 +1138,18 @@ void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, } /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; @@ -1187,19 +1187,19 @@ void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, } /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle) +void stm32_dmastop(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; DMA_MUX dmamux; @@ -1228,17 +1228,17 @@ void stm32wb_dmastop(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Read the DMA bytes-remaining register. * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle) +size_t stm32_dmaresidual(DMA_HANDLE handle) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1254,7 +1254,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) } /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -1271,7 +1271,7 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle) ****************************************************************************/ #ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) +bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; uint32_t transfer_size; @@ -1347,18 +1347,18 @@ bool stm32wb_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; uint8_t controller; @@ -1375,18 +1375,18 @@ void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index 6caff116906..baf212c4dbd 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -71,7 +71,7 @@ typedef void *DMA_HANDLE; typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); #ifdef CONFIG_DEBUG_DMA_INFO -struct stm32wb_dmaregs_s +struct stm32_dmaregs_s { uint32_t isr; /* Interrupt Status Register; each channel gets 4 bits */ uint32_t ccr; /* Channel Configuration Register; determines functionality */ @@ -139,18 +139,18 @@ extern "C" * ****************************************************************************/ -DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); +DMA_HANDLE stm32_dmachannel(unsigned int dmamap); /**************************************************************************** - * Name: stm32wb_dmafree + * Name: stm32_dmafree * * Description: * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32wb_dmachannel, then this function will + * channel in a call to stm32_dmachannel, then this function will * re-assign the DMA channel to that thread and wake it up. * * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32wb_dmachannel() is called again to re-gain access to + * until stm32_dmachannel() is called again to re-gain access to * the channel. * * Returned Value: @@ -162,64 +162,64 @@ DMA_HANDLE stm32wb_dmachannel(unsigned int dmamap); * ****************************************************************************/ -void stm32wb_dmafree(DMA_HANDLE handle); +void stm32_dmafree(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmasetup + * Name: stm32_dmasetup * * Description: * Configure DMA before using * ****************************************************************************/ -void stm32wb_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, +void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t ccr); /**************************************************************************** - * Name: stm32wb_dmastart + * Name: stm32_dmastart * * Description: * Start the DMA transfer * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * - No DMA in progress * ****************************************************************************/ -void stm32wb_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, +void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); /**************************************************************************** - * Name: stm32wb_dmastop + * Name: stm32_dmastop * * Description: - * Cancel the DMA. After stm32wb_dmastop() is called, the DMA channel is - * reset and stm32wb_dmasetup() must be called before stm32wb_dmastart() + * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is + * reset and stm32_dmasetup() must be called before stm32_dmastart() * can be called again * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -void stm32wb_dmastop(DMA_HANDLE handle); +void stm32_dmastop(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmaresidual + * Name: stm32_dmaresidual * * Description: * Returns the number of bytes remaining to be transferred * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ -size_t stm32wb_dmaresidual(DMA_HANDLE handle); +size_t stm32_dmaresidual(DMA_HANDLE handle); /**************************************************************************** - * Name: stm32wb_dmacapable + * Name: stm32_dmacapable * * Description: * Check if the DMA controller can transfer data to/from given memory @@ -234,44 +234,44 @@ size_t stm32wb_dmaresidual(DMA_HANDLE handle); ****************************************************************************/ #ifdef CONFIG_STM32WB_DMACAPABLE -bool stm32wb_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); +bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else -# define stm32wb_dmacapable(maddr, count, ccr) (true) +# define stm32_dmacapable(maddr, count, ccr) (true) #endif /**************************************************************************** - * Name: stm32wb_dmasample + * Name: stm32_dmasample * * Description: * Sample DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmasample(DMA_HANDLE handle, struct stm32wb_dmaregs_s *regs); +void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); #else -# define stm32wb_dmasample(handle,regs) ((void)0) +# define stm32_dmasample(handle,regs) ((void)0) #endif /**************************************************************************** - * Name: stm32wb_dmadump + * Name: stm32_dmadump * * Description: * Dump previously sampled DMA register contents * * Assumptions: - * - DMA handle allocated by stm32wb_dmachannel() + * - DMA handle allocated by stm32_dmachannel() * ****************************************************************************/ #ifdef CONFIG_DEBUG_DMA_INFO -void stm32wb_dmadump(DMA_HANDLE handle, const struct stm32wb_dmaregs_s *regs, +void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, const char *msg); #else -# define stm32wb_dmadump(handle,regs,msg) ((void)0) +# define stm32_dmadump(handle,regs,msg) ((void)0) #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index 3a45d0e54c7..2b33764174a 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -66,14 +66,14 @@ static const char g_portchar[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address * ****************************************************************************/ -int stm32wb_dumpgpio(uint32_t pinset, const char *msg) +int stm32_dumpgpio(uint32_t pinset, const char *msg) { irqstate_t flags; uint32_t base; diff --git a/arch/arm/src/stm32wb/stm32wb_exti.h b/arch/arm/src/stm32wb/stm32wb_exti.h index 40494223991..9e0b370fbe4 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti.h +++ b/arch/arm/src/stm32wb/stm32wb_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,7 +118,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c index 8a4b9cf1538..cff98eaeb93 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_alarm.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_alarm.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm_isr + * Name: stm32_exti_alarm_isr * * Description: * EXTI ALARM interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) +static int stm32_exti_alarm_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_alarm_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_alarm_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_alarm(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTCALRM, stm32wb_exti_alarm_isr, NULL); + irq_attach(STM32_IRQ_RTCALRM, stm32_exti_alarm_isr, NULL); up_enable_irq(STM32_IRQ_RTCALRM); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c index 6d5afe56e69..6e6597b60ca 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_gpio.c @@ -65,7 +65,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wb_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -107,7 +107,7 @@ static int stm32wb_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -128,7 +128,7 @@ static int stm32wb_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -149,7 +149,7 @@ static int stm32wb_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -170,7 +170,7 @@ static int stm32wb_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wb_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -214,14 +214,14 @@ static int stm32wb_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wb_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wb_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wb_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -229,7 +229,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -251,7 +251,7 @@ static int stm32wb_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -271,37 +271,37 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32wb_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wb_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wb_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wb_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wb_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32wb_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32wb_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -347,7 +347,7 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wb_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c index 8caaed92019..0cc045d27ca 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_pwr.c @@ -56,14 +56,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd_isr + * Name: stm32_exti_pvd_isr * * Description: * EXTI PVD interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) +static int stm32_exti_pvd_isr(int irq, void *context, void *arg) { int ret = OK; @@ -86,7 +86,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_pvd + * Name: stm32_exti_pvd * * Description: * Sets/clears EXTI PVD interrupt. @@ -102,7 +102,7 @@ static int stm32wb_exti_pvd_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, +int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { /* Get the previous GPIO IRQ handler; Save the new IRQ handler. */ @@ -114,7 +114,7 @@ int stm32wb_exti_pvd(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_PVD, stm32wb_exti_pvd_isr, NULL); + irq_attach(STM32_IRQ_PVD, stm32_exti_pvd_isr, NULL); up_enable_irq(STM32_IRQ_PVD); } else diff --git a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c index 0e44b3f4dcc..32fba5d71e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c +++ b/arch/arm/src/stm32wb/stm32wb_exti_wakeup.c @@ -51,14 +51,14 @@ static void *g_callback_arg; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup_isr + * Name: stm32_exti_wakeup_isr * * Description: * EXTI periodic WAKEUP interrupt service routine/dispatcher * ****************************************************************************/ -static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) +static int stm32_exti_wakeup_isr(int irq, void *context, void *arg) { int ret = OK; @@ -81,7 +81,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -97,7 +97,7 @@ static int stm32wb_exti_wakeup_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { g_wakeup_callback = func; @@ -107,7 +107,7 @@ int stm32wb_exti_wakeup(bool risingedge, bool fallingedge, bool event, if (func) { - irq_attach(STM32_IRQ_RTC_WKUP, stm32wb_exti_wakeup_isr, NULL); + irq_attach(STM32_IRQ_RTC_WKUP, stm32_exti_wakeup_isr, NULL); up_enable_irq(STM32_IRQ_RTC_WKUP); } else diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 346a1355940..4d6432f6af5 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -93,7 +93,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -143,7 +143,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -153,7 +153,7 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -int stm32wb_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -169,7 +169,7 @@ int stm32wb_flash_unlock(void) return ret; } -int stm32wb_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -186,7 +186,7 @@ int stm32wb_flash_lock(void) } /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -202,7 +202,7 @@ int stm32wb_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -240,7 +240,7 @@ uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -453,7 +453,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wb_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32wb/stm32wb_flash.h b/arch/arm/src/stm32wb/stm32wb_flash.h index 36077d8b0f8..704b3106fe8 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/stm32wb_flash.h @@ -35,11 +35,11 @@ * Public Function Prototypes ****************************************************************************/ -int stm32wb_flash_lock(void); -int stm32wb_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wb_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -55,6 +55,6 @@ int stm32wb_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wb_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FLASH_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index bd56695e121..570f3b3f2f1 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -44,7 +44,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_handler + * Name: stm32_freerun_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -62,9 +62,9 @@ ****************************************************************************/ #ifndef CONFIG_CLOCK_TIMEKEEPING -static int stm32wb_freerun_handler(int irq, void *context, void *arg) +static int stm32_freerun_handler(int irq, void *context, void *arg) { - struct stm32wb_freerun_s *freerun = (struct stm32wb_freerun_s *)arg; + struct stm32_freerun_s *freerun = (struct stm32_freerun_s *)arg; DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); freerun->overflow++; @@ -79,7 +79,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -97,7 +97,7 @@ static int stm32wb_freerun_handler(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution) { uint32_t frequency; @@ -110,7 +110,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, frequency = USEC_PER_SEC / (uint32_t)resolution; freerun->frequency = frequency; - freerun->tch = stm32wb_tim_init(chan); + freerun->tch = stm32_tim_init(chan); if (!freerun->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -135,7 +135,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(freerun->tch, stm32wb_freerun_handler, freerun, 0); + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, freerun, 0); #endif /* Set timer period */ @@ -156,7 +156,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, } /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -164,7 +164,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time from the free-running * timer. * @@ -176,7 +176,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts) { uint64_t usec; @@ -190,7 +190,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, DEBUGASSERT(freerun && freerun->tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -253,7 +253,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter) { *counter = STM32_TIM_GETCOUNTER(freerun->tch); @@ -263,7 +263,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -271,7 +271,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -279,7 +279,7 @@ int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) { DEBUGASSERT(freerun && freerun->tch); @@ -291,7 +291,7 @@ int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun) /* Free the timer */ - stm32wb_tim_deinit(freerun->tch); + stm32_tim_deinit(freerun->tch); freerun->tch = NULL; return OK; diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index ef95f59c32e..9f1a86dc817 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -42,17 +42,17 @@ ****************************************************************************/ /* The freerun client must allocate an instance of this structure and called - * stm32wb_freerun_initialize() before using the freerun facilities. The + * stm32_freerun_initialize() before using the freerun facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_freerun_s +struct stm32_freerun_s { uint8_t chan; /* The timer/counter in use */ uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; #ifndef CONFIG_CLOCK_TIMEKEEPING @@ -82,7 +82,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_freerun_initialize + * Name: stm32_freerun_initialize * * Description: * Initialize the freerun timer wrapper @@ -100,11 +100,11 @@ extern "C" * ****************************************************************************/ -int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_freerun_counter + * Name: stm32_freerun_counter * * Description: * Read the counter register of the free-running timer. @@ -112,7 +112,7 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. * @@ -124,18 +124,18 @@ int stm32wb_freerun_initialize(struct stm32wb_freerun_s *freerun, int chan, #ifndef CONFIG_CLOCK_TIMEKEEPING -int stm32wb_freerun_counter(struct stm32wb_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, struct timespec *ts); #else /* CONFIG_CLOCK_TIMEKEEPING */ -int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, +int stm32_freerun_counter(struct stm32_freerun_s *freerun, uint64_t *counter); #endif /* CONFIG_CLOCK_TIMEKEEPING */ /**************************************************************************** - * Name: stm32wb_freerun_uninitialize + * Name: stm32_freerun_uninitialize * * Description: * Stop the free-running timer and release all resources that it uses. @@ -143,7 +143,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * Input Parameters: * freerun Caller allocated instance of the freerun state structure. This * structure must have been previously initialized via a call to - * stm32wb_freerun_initialize(); + * stm32_freerun_initialize(); * * Returned Value: * Zero (OK) is returned on success; a negated errno value is returned @@ -151,7 +151,7 @@ int stm32wb_freerun_counter(struct stm32_freerun_s *freerun, * ****************************************************************************/ -int stm32wb_freerun_uninitialize(struct stm32wb_freerun_s *freerun); +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.c b/arch/arm/src/stm32wb/stm32wb_gpio.c index 433df3cea15..a38e7398b74 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.c +++ b/arch/arm/src/stm32wb/stm32wb_gpio.c @@ -71,13 +71,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -85,17 +85,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32wb_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -106,7 +106,7 @@ void stm32wb_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -147,7 +147,7 @@ int stm32wb_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wb_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -305,7 +305,7 @@ int stm32wb_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -325,7 +325,7 @@ int stm32wb_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -334,18 +334,18 @@ int stm32wb_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wb_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -379,14 +379,14 @@ void stm32wb_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index e407a28a564..1103b50cbc2 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -52,7 +52,7 @@ # define STM32_NPORTS 4 #endif -/* Bit-encoded input to stm32wb_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -257,12 +257,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wb_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -271,10 +271,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32wb_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -293,30 +293,30 @@ int stm32wb_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wb_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wb_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wb_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wb_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wb_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wb_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -335,11 +335,11 @@ bool stm32wb_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wb_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -347,23 +347,23 @@ int stm32wb_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wb_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wb_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wb_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wb_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wb_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 182d588027a..85d42440330 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -245,10 +245,10 @@ */ #ifndef CONFIG_I2C_TRACE -# define stm32wb_i2c_tracereset(p) -# define stm32wb_i2c_tracenew(p,s) -# define stm32wb_i2c_traceevent(p,e,a) -# define stm32wb_i2c_tracedump(p) +# define stm32_i2c_tracereset(p) +# define stm32_i2c_tracenew(p,s) +# define stm32_i2c_traceevent(p,e,a) +# define stm32_i2c_tracedump(p) #endif #ifndef CONFIG_I2C_NTRACE @@ -261,7 +261,7 @@ /* Interrupt state */ -enum stm32wb_intstate_e +enum stm32_intstate_e { INTSTATE_IDLE = 0, /* No I2C activity */ INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ @@ -270,7 +270,7 @@ enum stm32wb_intstate_e /* Trace events */ -enum stm32wb_trace_e +enum stm32_trace_e { I2CEVENT_NONE = 0, I2CEVENT_STATE_ERROR, @@ -293,18 +293,18 @@ enum stm32wb_trace_e /* Trace data */ -struct stm32wb_trace_s +struct stm32_trace_s { uint32_t status; /* I2C 32-bit SR2|SR1 status */ uint32_t count; /* Interrupt count when status change */ - enum stm32wb_intstate_e event; /* Last event that occurred with this status */ + enum stm32_intstate_e event; /* Last event that occurred with status */ uint32_t parm; /* Parameter associated with the event */ clock_t time; /* First of event or first status */ }; /* I2C Device hardware configuration */ -struct stm32wb_i2c_config_s +struct stm32_i2c_config_s { uint32_t base; /* I2C base address */ uint32_t clk_bit; /* Clock enable bit */ @@ -319,18 +319,18 @@ struct stm32wb_i2c_config_s /* I2C Device Private Data */ -struct stm32wb_i2c_priv_s +struct stm32_i2c_priv_s { /* Port configuration */ - const struct stm32wb_i2c_config_s *config; + const struct stm32_i2c_config_s *config; int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifndef CONFIG_I2C_POLLED sem_t sem_isr; /* Interrupt wait semaphore */ #endif - volatile uint8_t intstate; /* Interrupt handshake (see enum stm32wb_intstate_e) */ + volatile uint8_t intstate; /* Interrupt handshake (see enum stm32_intstate_e) */ uint8_t msgc; /* Message count */ struct i2c_msg_s *msgv; /* Message list */ @@ -348,7 +348,7 @@ struct stm32wb_i2c_priv_s /* The actual trace data */ - struct stm32wb_trace_s trace[CONFIG_I2C_NTRACE]; + struct stm32_trace_s trace[CONFIG_I2C_NTRACE]; #endif uint32_t status; /* End of transfer SR2|SR1 status */ @@ -360,10 +360,10 @@ struct stm32wb_i2c_priv_s /* I2C Device, Instance */ -struct stm32wb_i2c_inst_s +struct stm32_i2c_inst_s { - const struct i2c_ops_s *ops; /* Standard I2C operations */ - struct stm32wb_i2c_priv_s *priv; /* Common driver private data structure */ + const struct i2c_ops_s *ops; /* Standard I2C operations */ + struct stm32_i2c_priv_s *priv; /* Common driver private data structure */ }; /**************************************************************************** @@ -371,57 +371,57 @@ struct stm32wb_i2c_inst_s ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset); static inline -void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value); static inline -void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value); static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); #ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs); +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); #endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv); +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv); -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv); +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status); static void -stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm); -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv); +stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm); +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv); #endif /* CONFIG_I2C_TRACE */ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency); static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv); -static inline void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv); +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv); +static inline void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv); static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv); +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv); #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg); +static int stm32_i2c_isr(int irq, void *context, void *arg); #endif -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv); -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv); +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv); +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv); -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s *dev); +static int stm32_i2c_reset(struct i2c_master_s *dev); #endif #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -430,7 +430,7 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_STM32WB_I2C1 -static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = +static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, .clk_bit = RCC_APB1ENR1_I2C1EN, @@ -443,9 +443,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c1_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = +static struct stm32_i2c_priv_s stm32_i2c1_priv = { - .config = &stm32wb_i2c1_config, + .config = &stm32_i2c1_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -460,13 +460,13 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c1_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif #ifdef CONFIG_STM32WB_I2C3 -static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = +static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, .clk_bit = RCC_APB1ENR1_I2C3EN, @@ -479,9 +479,9 @@ static const struct stm32wb_i2c_config_s stm32wb_i2c3_config = #endif }; -static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = +static struct stm32_i2c_priv_s stm32_i2c3_priv = { - .config = &stm32wb_i2c3_config, + .config = &stm32_i2c3_config, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifndef CONFIG_I2C_POLLED @@ -496,18 +496,18 @@ static struct stm32wb_i2c_priv_s stm32wb_i2c3_priv = .flags = 0, .status = 0, #ifdef CONFIG_PM - .pm_cb.prepare = stm32wb_i2c_pm_prepare, + .pm_cb.prepare = stm32_i2c_pm_prepare, #endif }; #endif /* Device Structures, Instantiation */ -static const struct i2c_ops_s stm32wb_i2c_ops = +static const struct i2c_ops_s stm32_i2c_ops = { - .transfer = stm32wb_i2c_transfer, + .transfer = stm32_i2c_transfer, #ifdef CONFIG_I2C_RESET - .reset = stm32wb_i2c_reset + .reset = stm32_i2c_reset #endif }; @@ -516,7 +516,7 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2c_getreg + * Name: stm32_i2c_getreg * * Description: * Get a 16-bit register value by offset @@ -524,14 +524,14 @@ static const struct i2c_ops_s stm32wb_i2c_ops = ****************************************************************************/ static inline -uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, +uint16_t stm32_i2c_getreg(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg16(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_getreg32 + * Name: stm32_i2c_getreg32 * * Description: * Get a 32-bit register value by offset @@ -539,42 +539,42 @@ uint16_t stm32wb_i2c_getreg(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getreg32(struct stm32wb_i2c_priv_s *priv, +uint32_t stm32_i2c_getreg32(struct stm32_i2c_priv_s *priv, uint8_t offset) { return getreg32(priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg + * Name: stm32_i2c_putreg * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg(struct stm32_i2c_priv_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_putreg32 + * Name: stm32_i2c_putreg32 * * Description: * Put a 32-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, +static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t value) { putreg32(value, priv->config->base + offset); } /**************************************************************************** - * Name: stm32wb_i2c_modifyreg32 + * Name: stm32_i2c_modifyreg32 * * Description: * Modify a 32-bit register value by offset @@ -582,7 +582,7 @@ static inline void stm32wb_i2c_putreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, +void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits) { @@ -590,7 +590,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_toticks + * Name: stm32_i2c_toticks * * Description: * Return a micro-second delay based on the number of bytes left to be @@ -599,7 +599,7 @@ void stm32wb_i2c_modifyreg32(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_I2C_DYNTIMEO -static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) +static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; int i; @@ -620,7 +620,7 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #endif /**************************************************************************** - * Name: stm32wb_i2c_enableinterrupts + * Name: stm32_i2c_enableinterrupts * * Description: * Enable I2C interrupts @@ -629,15 +629,15 @@ static uint32_t stm32wb_i2c_toticks(int msgc, struct i2c_msg_s *msgs) #ifndef CONFIG_I2C_POLLED static inline -void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_TXRX | I2C_CR1_NACKIE)); } #endif /**************************************************************************** - * Name: stm32wb_i2c_sem_waitdone + * Name: stm32_i2c_sem_waitdone * * Description: * Wait for a transfer to complete @@ -649,7 +649,7 @@ void stm32wb_i2c_enableinterrupts(struct stm32wb_i2c_priv_s *priv) #ifndef CONFIG_I2C_POLLED static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { irqstate_t flags; int ret; @@ -659,11 +659,11 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Enable I2C interrupts */ /* The TXIE and RXIE interrupts are enabled initially in - * stm32wb_i2c_process. The remainder of the interrupts, including + * stm32_i2c_process. The remainder of the interrupts, including * error-related, are enabled here. */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, (I2C_CR1_ALLINTS & ~I2C_CR1_TXRX)); /* Signal the interrupt handler that we are waiting */ @@ -675,7 +675,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #ifdef CONFIG_STM32WB_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - stm32wb_i2c_toticks(priv->msgc, priv->msgv)); + stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, CONFIG_STM32WB_I2CTIMEOTICKS); @@ -701,14 +701,14 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Disable I2C interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_ALLINTS, 0); leave_critical_section(flags); return ret; } #else static inline -int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) +int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { clock_t timeout; clock_t start; @@ -718,7 +718,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) /* Get the timeout value */ #ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = stm32wb_i2c_toticks(priv->msgc, priv->msgv); + timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else timeout = CONFIG_STM32WB_I2CTIMEOTICKS; #endif @@ -741,7 +741,7 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) * reports that it is done. */ - stm32wb_i2c_isr_process(priv); + stm32_i2c_isr_process(priv); } /* Loop until the transfer is complete. */ @@ -760,92 +760,92 @@ int stm32wb_i2c_sem_waitdone(struct stm32wb_i2c_priv_s *priv) #endif /**************************************************************************** - * Name: stm32wb_i2c_set_7bit_address + * Name: stm32_i2c_set_7bit_address * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_7bit_address(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_7bit_address(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_SADD7_MASK, (priv->msgv->addr << I2C_CR2_SADD7_SHIFT) & I2C_CR2_SADD7_MASK); } /**************************************************************************** - * Name: stm32wb_i2c_set_bytes_to_transfer + * Name: stm32_i2c_set_bytes_to_transfer * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_bytes_to_transfer(struct stm32wb_i2c_priv_s *priv, +stm32_i2c_set_bytes_to_transfer(struct stm32_i2c_priv_s *priv, uint8_t n_bytes) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_NBYTES_MASK, (n_bytes << I2C_CR2_NBYTES_SHIFT)); } /**************************************************************************** - * Name: stm32wb_i2c_set_write_transfer_dir + * Name: stm32_i2c_set_write_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_write_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_write_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RD_WRN, 0); } /**************************************************************************** - * Name: stm32wb_i2c_set_read_transfer_dir + * Name: stm32_i2c_set_read_transfer_dir * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_set_read_transfer_dir(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_set_read_transfer_dir(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RD_WRN); } /**************************************************************************** - * Name: stm32wb_i2c_enable_reload + * Name: stm32_i2c_enable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_enable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_enable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_RELOAD); } /**************************************************************************** - * Name: stm32wb_i2c_disable_reload + * Name: stm32_i2c_disable_reload * * Description: * ****************************************************************************/ static inline void -stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) +stm32_i2c_disable_reload(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, I2C_CR2_RELOAD, 0); } /**************************************************************************** - * Name: stm32wb_i2c_sem_waitstop + * Name: stm32_i2c_sem_waitstop * * Description: * Wait for a STOP to complete @@ -853,7 +853,7 @@ stm32wb_i2c_disable_reload(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) { clock_t start; clock_t elapsed; @@ -880,7 +880,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for STOP condition */ - cr = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); if ((cr & I2C_CR2_STOP) == 0) { return; @@ -888,7 +888,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) /* Check for timeout error */ - sr = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + sr = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); if ((sr & I2C_INT_TIMEOUT) != 0) { i2cerr("ERROR: waiting for a STOP isr timeout, elapsed: %lu\n", @@ -909,7 +909,7 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_trace* + * Name: stm32_i2c_trace* * * Description: * I2C trace instrumentation @@ -917,9 +917,9 @@ void stm32wb_i2c_sem_waitstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifdef CONFIG_I2C_TRACE -static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_traceclear(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; trace->status = 0; /* I2C 32-bit status */ trace->count = 0; /* Interrupt count when status change */ @@ -928,19 +928,19 @@ static void stm32wb_i2c_traceclear(struct stm32wb_i2c_priv_s *priv) trace->time = 0; /* Time of first status or event */ } -static void stm32wb_i2c_tracereset(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracereset(struct stm32_i2c_priv_s *priv) { /* Reset the trace info for a new data collection */ priv->tndx = 0; priv->start_time = clock_systime_ticks(); - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } -static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_tracenew(struct stm32_i2c_priv_s *priv, uint32_t status) { - struct stm32wb_trace_s *trace = &priv->trace[priv->tndx]; + struct stm32_trace_s *trace = &priv->trace[priv->tndx]; /* Is the current entry uninitialized? Has the status changed? */ @@ -966,7 +966,7 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, /* Initialize the new trace entry */ - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); trace->status = status; trace->count = 1; trace->time = clock_systime_ticks(); @@ -979,10 +979,10 @@ static void stm32wb_i2c_tracenew(struct stm32wb_i2c_priv_s *priv, } } -static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, - enum stm32wb_trace_e event, uint32_t parm) +static void stm32_i2c_traceevent(struct stm32_i2c_priv_s *priv, + enum stm32_trace_e event, uint32_t parm) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; if (event != I2CEVENT_NONE) { @@ -1002,13 +1002,13 @@ static void stm32wb_i2c_traceevent(struct stm32wb_i2c_priv_s *priv, } priv->tndx++; - stm32wb_i2c_traceclear(priv); + stm32_i2c_traceclear(priv); } } -static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) +static void stm32_i2c_tracedump(struct stm32_i2c_priv_s *priv) { - struct stm32wb_trace_s *trace; + struct stm32_trace_s *trace; int i; syslog(LOG_DEBUG, "Elapsed time: %d\n", @@ -1026,7 +1026,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) #endif /* CONFIG_I2C_TRACE */ /**************************************************************************** - * Name: stm32wb_i2c_setclock + * Name: stm32_i2c_setclock * * Description: * @@ -1066,7 +1066,7 @@ static void stm32wb_i2c_tracedump(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, +static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, uint32_t frequency) { uint32_t pe; @@ -1076,10 +1076,10 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, { /* I2C peripheral must be disabled to update clocking configuration */ - pe = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; + pe = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET) & I2C_CR1_PE; if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, I2C_CR1_PE, 0); } @@ -1128,11 +1128,11 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } #endif - stm32wb_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); + stm32_i2c_putreg32(priv, STM32_I2C_TIMINGR_OFFSET, timingr); if (pe) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); } @@ -1141,7 +1141,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, } /**************************************************************************** - * Name: stm32wb_i2c_sendstart + * Name: stm32_i2c_sendstart * * Description: * Send the START condition / force Master mode @@ -1168,7 +1168,7 @@ static void stm32wb_i2c_setclock(struct stm32wb_i2c_priv_s *priv, ****************************************************************************/ static inline -void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstart(struct stm32_i2c_priv_s *priv) { bool next_norestart = false; @@ -1230,13 +1230,13 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) { i2cinfo("RELOAD enabled: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); } else { i2cinfo("RELOAD disable: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Set the number of bytes to transfer (I2C_CR2->NBYTES) to the number of @@ -1246,18 +1246,18 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 255) { - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } /* Set the (7 bit) address. * 10 bit addressing is not yet supported. */ - stm32wb_i2c_set_7bit_address(priv); + stm32_i2c_set_7bit_address(priv); /* The flag of the current message is used to determine the direction of * transfer required for the current message. @@ -1265,11 +1265,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) if (priv->flags & I2C_M_READ) { - stm32wb_i2c_set_read_transfer_dir(priv); + stm32_i2c_set_read_transfer_dir(priv); } else { - stm32wb_i2c_set_write_transfer_dir(priv); + stm32_i2c_set_write_transfer_dir(priv); } /* Set the I2C_CR2->START bit to 1 to instruct the hardware to send the @@ -1279,11 +1279,11 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) i2cinfo("Sending START: dcnt=%i msgc=%i flags=0x%04x\n", priv->dcnt, priv->msgc, priv->flags); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_START); } /**************************************************************************** - * Name: stm32wb_i2c_sendstop + * Name: stm32_i2c_sendstop * * Description: * Send the STOP conditions @@ -1295,17 +1295,17 @@ void stm32wb_i2c_sendstart(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_sendstop(struct stm32_i2c_priv_s *priv) { i2cinfo("Sending STOP\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_STOP, 0); - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_CR2_OFFSET, 0, I2C_CR2_STOP); } /**************************************************************************** - * Name: stm32wb_i2c_getstatus + * Name: stm32_i2c_getstatus * * Description: * Get 32-bit status (SR1 and SR2 combined) @@ -1313,13 +1313,13 @@ void stm32wb_i2c_sendstop(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) +uint32_t stm32_i2c_getstatus(struct stm32_i2c_priv_s *priv) { return getreg32(priv->config->base + STM32_I2C_ISR_OFFSET); } /**************************************************************************** - * Name: stm32wb_i2c_clearinterrupts + * Name: stm32_i2c_clearinterrupts * * Description: * Clear all interrupts @@ -1327,14 +1327,14 @@ uint32_t stm32wb_i2c_getstatus(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ static inline -void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) +void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv) { - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); } /**************************************************************************** - * Name: stm32wb_i2c_isr_process + * Name: stm32_i2c_isr_process * * Description: * Common interrupt service routine (ISR) that handles I2C protocol logic. @@ -1342,22 +1342,22 @@ void stm32wb_i2c_clearinterrupts(struct stm32wb_i2c_priv_s *priv) * * This ISR is activated and deactivated by: * - * stm32wb_i2c_process + * stm32_i2c_process * and - * stm32wb_i2c_waitdone + * stm32_i2c_waitdone * * Input Parameters: * priv - The private struct of the I2C driver. * ****************************************************************************/ -static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) { uint32_t status; /* Get state of the I2C controller */ - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("ENTER: status = 0x%08" PRIx32 "\n", status); @@ -1367,8 +1367,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* If this is a new transmission set up the trace table accordingly */ - stm32wb_i2c_tracenew(priv, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); + stm32_i2c_tracenew(priv, status); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_CALL, 0); /* ------------------- Start of I2C protocol handling ------------------ */ @@ -1410,7 +1410,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: Address invalid: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } else @@ -1420,7 +1420,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("NACK: NACK received: dcnt=%i " "msgc=%i status=0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr); } @@ -1474,7 +1474,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* TXIS interrupt occurred, address valid, ready to transmit */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE, 0); i2cinfo("TXIS: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1487,7 +1487,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->astart == true) { i2cinfo("TXIS: Address Valid\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, + stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_ACKED, priv->msgv->addr); priv->astart = false; } @@ -1498,7 +1498,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Prepare to transmit the current byte */ - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt); i2cinfo("TXIS: Write Data 0x%02x\n", *priv->ptr); /* Decrement byte counter */ @@ -1520,13 +1520,13 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->msgc == 1) { - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } } /* Transmit current byte */ - stm32wb_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); + stm32_i2c_putreg(priv, STM32_I2C_TXDR_OFFSET, *priv->ptr); /* Advance to next byte */ @@ -1539,7 +1539,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cerr("ERROR: TXIS Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); - stm32wb_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0); } i2cinfo("TXIS: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1582,7 +1582,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * (RXNE is set) then the driver can read from the data register. */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ, 0); + stm32_i2c_traceevent(priv, I2CEVENT_READ, 0); i2cinfo("RXNE: ENTER dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", priv->dcnt, priv->msgc, status); @@ -1590,7 +1590,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) if (priv->dcnt > 0) { - stm32wb_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); /* No interrupts or context switches may occur in the following * sequence. Otherwise, additional bytes may be received. @@ -1601,7 +1601,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif /* Receive a byte */ - *priv->ptr = stm32wb_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); + *priv->ptr = stm32_i2c_getreg(priv, STM32_I2C_RXDR_OFFSET); i2cinfo("RXNE: Read Data 0x%02x\n", *priv->ptr); @@ -1621,8 +1621,8 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { /* Unsupported state */ - stm32wb_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: RXNE Unsupported state detected, dcnt=%i, " "status 0x%08" PRIx32 "\n", priv->dcnt, status); @@ -1688,7 +1688,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); + stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc); /* Issue a START condition. * @@ -1702,7 +1702,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->msgv++; - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); } else { @@ -1715,9 +1715,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TC: STOP: dcnt=%i msgc=%i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); + stm32_i2c_traceevent(priv, I2CEVENT_STOP, priv->dcnt); - stm32wb_i2c_sendstop(priv); + stm32_i2c_sendstop(priv); /* Set signals that will terminate ISR and wake waiting thread */ @@ -1796,7 +1796,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); } /* Update NBYTES with length of current message */ @@ -1804,7 +1804,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: NEXT MSG dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } else { @@ -1829,9 +1829,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) * the transfer. */ - stm32wb_i2c_enable_reload(priv); + stm32_i2c_enable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, 255); + stm32_i2c_set_bytes_to_transfer(priv, 255); } else { @@ -1848,9 +1848,9 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32wb_i2c_disable_reload(priv); + stm32_i2c_disable_reload(priv); - stm32wb_i2c_set_bytes_to_transfer(priv, priv->dcnt); + stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", @@ -1866,10 +1866,10 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else if (priv->dcnt == -1 && priv->msgc == 0) { - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cwarn("WARNING: EMPTY CALL: Stopping ISR: status 0x%08" PRIx32 "\n", status); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_EMPTY_CALL, 0); } /* Error handler @@ -1885,11 +1885,11 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) else { #ifdef CONFIG_I2C_POLLED - stm32wb_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); + stm32_i2c_traceevent(priv, I2CEVENT_POLL_DEV_NOT_RDY, 0); #else /* Read rest of the state */ - status = stm32wb_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg(priv, STM32_I2C_ISR_OFFSET); i2cerr("ERROR: Invalid state detected, status 0x%08" PRIx32 "\n", status); @@ -1898,7 +1898,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->dcnt = -1; priv->msgc = 0; - stm32wb_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); + stm32_i2c_traceevent(priv, I2CEVENT_STATE_ERROR, 0); #endif } @@ -1907,7 +1907,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Message Handling * * Transmission of the whole message chain has been completed. We have to - * terminate the ISR and wake up stm32wb_i2c_process() that is waiting for + * terminate the ISR and wake up stm32_i2c_process() that is waiting for * the ISR cycle to handle the sending/receiving of the messages. */ @@ -1915,7 +1915,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) { i2cinfo("MSG: Shutting down I2C ISR\n"); - stm32wb_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); + stm32_i2c_traceevent(priv, I2CEVENT_ISR_SHUTDOWN, 0); /* Clear pointer to message content to reflect we are done * with the current transaction. @@ -1927,7 +1927,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) priv->intstate = INTSTATE_DONE; #else - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); /* Update private state to capture NACK which is used in combination * with the astart flag to report the type of NACK received (address @@ -1941,7 +1941,7 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) /* Clear all interrupts */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, + stm32_i2c_modifyreg32(priv, STM32_I2C_ICR_OFFSET, 0, I2C_ICR_CLEARMASK); /* If a thread is waiting then inform it transfer is complete */ @@ -1954,14 +1954,14 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) #endif } - status = stm32wb_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); + status = stm32_i2c_getreg32(priv, STM32_I2C_ISR_OFFSET); i2cinfo("EXIT: status = 0x%08" PRIx32 "\n", status); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_isr + * Name: stm32_i2c_isr * * Description: * Common I2C interrupt service routine @@ -1969,24 +1969,24 @@ static int stm32wb_i2c_isr_process(struct stm32wb_i2c_priv_s *priv) ****************************************************************************/ #ifndef CONFIG_I2C_POLLED -static int stm32wb_i2c_isr(int irq, void *context, void *arg) +static int stm32_i2c_isr(int irq, void *context, void *arg) { - struct stm32wb_i2c_priv_s *priv = (struct stm32wb_i2c_priv_s *)arg; + struct stm32_i2c_priv_s *priv = (struct stm32_i2c_priv_s *)arg; DEBUGASSERT(priv != NULL); - return stm32wb_i2c_isr_process(priv); + return stm32_i2c_isr_process(priv); } #endif /**************************************************************************** - * Name: stm32wb_i2c_init + * Name: stm32_i2c_init * * Description: * Setup the I2C hardware, ready for operation with defaults * ****************************************************************************/ -static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) { /* Power-up and configure GPIOs */ @@ -1998,22 +1998,22 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Configure pins */ - if (stm32wb_configgpio(priv->config->scl_pin) < 0) + if (stm32_configgpio(priv->config->scl_pin) < 0) { return ERROR; } - if (stm32wb_configgpio(priv->config->sda_pin) < 0) + if (stm32_configgpio(priv->config->sda_pin) < 0) { - stm32wb_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->scl_pin); return ERROR; } #ifndef CONFIG_I2C_POLLED /* Attach error and event interrupts to the ISRs */ - irq_attach(priv->config->ev_irq, stm32wb_i2c_isr, priv); - irq_attach(priv->config->er_irq, stm32wb_i2c_isr, priv); + irq_attach(priv->config->ev_irq, stm32_i2c_isr, priv); + irq_attach(priv->config->er_irq, stm32_i2c_isr, priv); up_enable_irq(priv->config->ev_irq); up_enable_irq(priv->config->er_irq); #endif @@ -2026,33 +2026,33 @@ static int stm32wb_i2c_init(struct stm32wb_i2c_priv_s *priv) /* Force a frequency update */ priv->frequency = 0; - stm32wb_i2c_setclock(priv, 100000); + stm32_i2c_setclock(priv, 100000); /* Enable I2C peripheral */ - stm32wb_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); + stm32_i2c_modifyreg32(priv, STM32_I2C_CR1_OFFSET, 0, I2C_CR1_PE); return OK; } /**************************************************************************** - * Name: stm32wb_i2c_deinit + * Name: stm32_i2c_deinit * * Description: * Shutdown the I2C hardware * ****************************************************************************/ -static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) +static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) { /* Disable I2C */ - stm32wb_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); + stm32_i2c_putreg32(priv, STM32_I2C_CR1_OFFSET, 0); /* Unconfigure GPIO pins */ - stm32wb_unconfiggpio(priv->config->scl_pin); - stm32wb_unconfiggpio(priv->config->sda_pin); + stm32_unconfiggpio(priv->config->scl_pin); + stm32_unconfiggpio(priv->config->sda_pin); #ifndef CONFIG_I2C_POLLED @@ -2072,7 +2072,7 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) } /**************************************************************************** - * Name: stm32wb_i2c_process + * Name: stm32_i2c_process * * Description: * Common I2C transfer logic @@ -2082,11 +2082,11 @@ static int stm32wb_i2c_deinit(struct stm32wb_i2c_priv_s *priv) * ****************************************************************************/ -static int stm32wb_i2c_process(struct i2c_master_s *dev, +static int stm32_i2c_process(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { - struct stm32wb_i2c_inst_s *inst = (struct stm32wb_i2c_inst_s *)dev; - struct stm32wb_i2c_priv_s *priv = inst->priv; + struct stm32_i2c_inst_s *inst = (struct stm32_i2c_inst_s *)dev; + struct stm32_i2c_priv_s *priv = inst->priv; uint32_t status = 0; uint32_t cr1; uint32_t cr2; @@ -2097,11 +2097,11 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Wait for any STOP in progress */ - stm32wb_i2c_sem_waitstop(priv); + stm32_i2c_sem_waitstop(priv); /* Clear any pending error interrupts */ - stm32wb_i2c_clearinterrupts(priv); + stm32_i2c_clearinterrupts(priv); /* Old transfers are done */ @@ -2110,14 +2110,14 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Reset I2C trace logic */ - stm32wb_i2c_tracereset(priv); + stm32_i2c_tracereset(priv); /* Set I2C clock frequency (on change it toggles I2C_CR1_PE !) */ - stm32wb_i2c_setclock(priv, msgs->frequency); + stm32_i2c_setclock(priv, msgs->frequency); /* Trigger start condition, then the process moves into the ISR. I2C - * interrupts will be enabled within stm32wb_i2c_waitdone(). + * interrupts will be enabled within stm32_i2c_waitdone(). */ priv->status = 0; @@ -2126,17 +2126,17 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* Enable transmit and receive interrupts here so when we send the start * condition below the ISR will fire if the data was sent and some * response from the slave received. All other interrupts relevant to - * our needs are enabled in stm32wb_i2c_sem_waitdone() below. + * our needs are enabled in stm32_i2c_sem_waitdone() below. */ - stm32wb_i2c_enableinterrupts(priv); + stm32_i2c_enableinterrupts(priv); #endif /* Trigger START condition generation, which also sends the slave address * with read/write flag and the data in the first message */ - stm32wb_i2c_sendstart(priv); + stm32_i2c_sendstart(priv); /* Wait for the ISR to tell us that the transfer is complete by attempting * to grab the semaphore that is initially locked by the ISR. If the ISR @@ -2144,10 +2144,10 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * the timeout period waitdone returns error and we report a timeout. */ - waitrc = stm32wb_i2c_sem_waitdone(priv); + waitrc = stm32_i2c_sem_waitdone(priv); - cr1 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); - cr2 = stm32wb_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); + cr1 = stm32_i2c_getreg32(priv, STM32_I2C_CR1_OFFSET); + cr2 = stm32_i2c_getreg32(priv, STM32_I2C_CR2_OFFSET); #if !defined(CONFIG_DEBUG_I2C) UNUSED(cr1); UNUSED(cr2); @@ -2161,7 +2161,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * like a NACK, so we reset the status field to include that information. */ - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); /* The priv->status field can hold additional information like a NACK * event so we include that information. @@ -2266,7 +2266,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, /* This is not an error, but should not happen. The BUSY signal can be * present if devices on the bus are in an odd state and need to be reset. * NOTE: - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared. */ @@ -2276,7 +2276,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, * * This is a status condition rather than an error. * - * We will only see this busy indication if stm32wb_i2c_sem_waitdone() + * We will only see this busy indication if stm32_i2c_sem_waitdone() * fails above; Otherwise it is cleared by the hardware when the ISR * wraps up the transfer with a STOP condition. */ @@ -2284,7 +2284,7 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, clock_t start = clock_systime_ticks(); clock_t timeout = USEC2TICK(USEC_PER_SEC / priv->frequency) + 1; - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); while (status & I2C_ISR_BUSY) { @@ -2295,27 +2295,27 @@ static int stm32wb_i2c_process(struct i2c_master_s *dev, break; } - status = stm32wb_i2c_getstatus(priv); + status = stm32_i2c_getstatus(priv); } } /* Dump the trace result */ - stm32wb_i2c_tracedump(priv); + stm32_i2c_tracedump(priv); nxmutex_unlock(&priv->lock); return -errval; } /**************************************************************************** - * Name: stm32wb_i2c_transfer + * Name: stm32_i2c_transfer * * Description: * Generic I2C transfer function * ****************************************************************************/ -static int stm32wb_i2c_transfer(struct i2c_master_s *dev, +static int stm32_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count) { @@ -2323,17 +2323,17 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, /* Ensure that address or flags don't change meanwhile */ - ret = nxmutex_lock(&((struct stm32wb_i2c_inst_s *)dev)->priv->lock); + ret = nxmutex_lock(&((struct stm32_i2c_inst_s *)dev)->priv->lock); if (ret >= 0) { - ret = stm32wb_i2c_process(dev, msgs, count); + ret = stm32_i2c_process(dev, msgs, count); } return ret; } /**************************************************************************** - * Name: stm32wb_i2c_reset + * Name: stm32_i2c_reset * * Description: * Reset an I2C bus @@ -2341,9 +2341,9 @@ static int stm32wb_i2c_transfer(struct i2c_master_s *dev, ****************************************************************************/ #ifdef CONFIG_I2C_RESET -static int stm32wb_i2c_reset(struct i2c_master_s * dev) +static int stm32_i2c_reset(struct i2c_master_s * dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; unsigned int clock_count; unsigned int stretch_count; uint32_t scl_gpio; @@ -2355,7 +2355,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Get I2C private structure */ - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Our caller must own a ref */ @@ -2377,24 +2377,24 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* De-init the port */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); /* Use GPIO configuration to un-wedge the bus */ scl_gpio = MKI2C_OUTPUT(priv->config->scl_pin); sda_gpio = MKI2C_OUTPUT(priv->config->sda_pin); - stm32wb_configgpio(sda_gpio); - stm32wb_configgpio(scl_gpio); + stm32_configgpio(sda_gpio); + stm32_configgpio(scl_gpio); /* Let SDA go high */ - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!stm32wb_gpioread(sda_gpio)) + while (!stm32_gpioread(sda_gpio)) { /* Give up if we have tried too hard */ @@ -2409,7 +2409,7 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) */ stretch_count = 0; - while (!stm32wb_gpioread(scl_gpio)) + while (!stm32_gpioread(scl_gpio)) { /* Give up if we have tried too hard */ @@ -2423,12 +2423,12 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) /* Drive SCL low */ - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); /* Drive SCL high again */ - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); } @@ -2436,27 +2436,27 @@ static int stm32wb_i2c_reset(struct i2c_master_s * dev) * state machines. */ - stm32wb_gpiowrite(sda_gpio, 0); + stm32_gpiowrite(sda_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 0); + stm32_gpiowrite(scl_gpio, 0); up_udelay(10); - stm32wb_gpiowrite(scl_gpio, 1); + stm32_gpiowrite(scl_gpio, 1); up_udelay(10); - stm32wb_gpiowrite(sda_gpio, 1); + stm32_gpiowrite(sda_gpio, 1); up_udelay(10); /* Revert the GPIO configuration. */ - stm32wb_unconfiggpio(sda_gpio); - stm32wb_unconfiggpio(scl_gpio); + stm32_unconfiggpio(sda_gpio); + stm32_unconfiggpio(scl_gpio); /* Re-init the port */ - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); /* Restore the frequency */ - stm32wb_i2c_setclock(priv, frequency); + stm32_i2c_setclock(priv, frequency); ret = OK; out: @@ -2469,7 +2469,7 @@ out: #endif /* CONFIG_I2C_RESET */ /**************************************************************************** - * Name: stm32wb_i2c_pm_prepare + * Name: stm32_i2c_pm_prepare * * Description: * Request the driver to prepare for a new power state. This is a @@ -2498,12 +2498,12 @@ out: ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, +static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_i2c_priv_s *priv = - (struct stm32wb_i2c_priv_s *)((char *)cb - - offsetof(struct stm32wb_i2c_priv_s, pm_cb)); + struct stm32_i2c_priv_s *priv = + (struct stm32_i2c_priv_s *)((char *)cb - + offsetof(struct stm32_i2c_priv_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -2545,17 +2545,17 @@ static int stm32wb_i2c_pm_prepare(struct pm_callback_s *cb, int domain, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize one I2C bus * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port) +struct i2c_master_s *stm32_i2cbus_initialize(int port) { - struct stm32wb_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ - struct stm32wb_i2c_inst_s *inst = NULL; /* device, single instance */ + struct stm32_i2c_priv_s *priv = NULL; /* private data of device with multiple instances */ + struct stm32_i2c_inst_s *inst = NULL; /* device, single instance */ /* Get I2C private structure */ @@ -2563,12 +2563,12 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) { #ifdef CONFIG_STM32WB_I2C1 case 1: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c1_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif #ifdef CONFIG_STM32WB_I2C3 case 3: - priv = (struct stm32wb_i2c_priv_s *)&stm32wb_i2c3_priv; + priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif default: @@ -2577,14 +2577,14 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) /* Allocate instance */ - if (!(inst = kmm_malloc(sizeof(struct stm32wb_i2c_inst_s)))) + if (!(inst = kmm_malloc(sizeof(struct stm32_i2c_inst_s)))) { return NULL; } /* Initialize instance */ - inst->ops = &stm32wb_i2c_ops; + inst->ops = &stm32_i2c_ops; inst->priv = priv; /* Init private data for the first time, increment refs count, @@ -2594,7 +2594,7 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) nxmutex_lock(&priv->lock); if (priv->refs++ == 0) { - stm32wb_i2c_init(priv); + stm32_i2c_init(priv); #ifdef CONFIG_PM /* Register to receive power management callbacks */ @@ -2608,19 +2608,19 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port) } /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * Uninitialize an I2C bus * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) { - struct stm32wb_i2c_priv_s *priv; + struct stm32_i2c_priv_s *priv; DEBUGASSERT(dev); - priv = ((struct stm32wb_i2c_inst_s *)dev)->priv; + priv = ((struct stm32_i2c_inst_s *)dev)->priv; /* Decrement refs and check for underflow */ @@ -2645,7 +2645,7 @@ int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev) /* Disable power and other HW resource (GPIO's) */ - stm32wb_i2c_deinit(priv); + stm32_i2c_deinit(priv); nxmutex_unlock(&priv->lock); kmm_free(dev); diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index 3c9ea624557..adb5a001e6e 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -53,7 +53,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_i2cbus_initialize + * Name: stm32_i2cbus_initialize * * Description: * Initialize the selected I2C port. And return a unique instance of struct @@ -69,16 +69,16 @@ * ****************************************************************************/ -struct i2c_master_s *stm32wb_i2cbus_initialize(int port); +struct i2c_master_s *stm32_i2cbus_initialize(int port); /**************************************************************************** - * Name: stm32wb_i2cbus_uninitialize + * Name: stm32_i2cbus_uninitialize * * Description: * De-initialize the selected I2C port, and power down the device. * * Input Parameters: - * Device structure as returned by the stm32wb_i2cbus_initialize() + * Device structure as returned by the stm32_i2cbus_initialize() * * Returned Value: * OK on success, ERROR when internal reference count mismatch or dev @@ -86,6 +86,6 @@ struct i2c_master_s *stm32wb_i2cbus_initialize(int port); * ****************************************************************************/ -int stm32wb_i2cbus_uninitialize(struct i2c_master_s *dev); +int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_I2C_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 977ff297093..0a0e6d1ad06 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -119,12 +119,12 @@ static void up_idlepm(void) /* Enter STOP mode */ BEGIN_IDLE(); - stm32wb_pmstop(true); + stm32_pmstop(true); END_IDLE(); /* Set correct clock again after returning from STOP */ - stm32wb_clockenable(); + stm32_clockenable(); /* Inform of all drivers of the new state */ @@ -137,7 +137,7 @@ static void up_idlepm(void) break; case PM_SLEEP: - stm32wb_pmstandby(); + stm32_pmstandby(); break; default: diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.c b/arch/arm/src/stm32wb/stm32wb_ipcc.c index 795ec398c46..c9b889aec9a 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.c +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.c @@ -40,14 +40,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void) +void stm32_ipccreset(void) { uint32_t regval; @@ -77,14 +77,14 @@ void stm32wb_ipccreset(void) } /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void) +void stm32_ipccenable(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_ipcc.h b/arch/arm/src/stm32wb/stm32wb_ipcc.h index b130c899662..679c4cd6728 100644 --- a/arch/arm/src/stm32wb/stm32wb_ipcc.h +++ b/arch/arm/src/stm32wb/stm32wb_ipcc.h @@ -55,77 +55,77 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipccreset + * Name: stm32_ipccreset * * Description: * Reset the IPCC registers to default state * ****************************************************************************/ -void stm32wb_ipccreset(void); +void stm32_ipccreset(void); /**************************************************************************** - * Name: stm32wb_ipccenable + * Name: stm32_ipccenable * * Description: * Enable the IPCC and start CPU2 * ****************************************************************************/ -void stm32wb_ipccenable(void); +void stm32_ipccenable(void); /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxactive + * Name: stm32_ipcc_rxactive * * Description: * Check channel receive active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_rxactive(uint8_t chan) +static inline bool stm32_ipcc_rxactive(uint8_t chan) { return (getreg32(STM32_IPCC_C2TOC1SR) & IPCC_C2TOC1SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_txactive + * Name: stm32_ipcc_txactive * * Description: * Check channel transmit active flag. * ****************************************************************************/ -static inline bool stm32wb_ipcc_txactive(uint8_t chan) +static inline bool stm32_ipcc_txactive(uint8_t chan) { return (getreg32(STM32_IPCC_C1TOC2SR) & IPCC_C1TOC2SR_BIT(chan)) != 0; } /**************************************************************************** - * Name: stm32wb_ipcc_settxactive + * Name: stm32_ipcc_settxactive * * Description: * Set channel transmit active flag. * ****************************************************************************/ -static inline void stm32wb_ipcc_settxactive(uint8_t chan) +static inline void stm32_ipcc_settxactive(uint8_t chan) { putreg32(IPCC_C1SCR_SET_BIT(chan), STM32_IPCC_C1SCR); } /**************************************************************************** - * Name: stm32wb_ipcc_masktxf + * Name: stm32_ipcc_masktxf * * Description: * Mask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_masktxf(uint8_t chan) +static inline void stm32_ipcc_masktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_FM_BIT(chan); @@ -133,14 +133,14 @@ static inline void stm32wb_ipcc_masktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_unmasktxf + * Name: stm32_ipcc_unmasktxf * * Description: * Unmask channel transmit free interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) +static inline void stm32_ipcc_unmasktxf(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_FM_BIT(chan); @@ -148,14 +148,14 @@ static inline void stm32wb_ipcc_unmasktxf(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Mask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_maskrxo(uint8_t chan) +static inline void stm32_ipcc_maskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval |= IPCC_C1MR_OM_BIT(chan); @@ -163,14 +163,14 @@ static inline void stm32wb_ipcc_maskrxo(uint8_t chan) } /**************************************************************************** - * Name: stm32wb_ipcc_maskrxo + * Name: stm32_ipcc_maskrxo * * Description: * Unmask channel receive occupied interrupt. * ****************************************************************************/ -static inline void stm32wb_ipcc_unmaskrxo(uint8_t chan) +static inline void stm32_ipcc_unmaskrxo(uint8_t chan) { uint32_t regval = getreg32(STM32_IPCC_C1MR); regval &= ~IPCC_C1MR_OM_BIT(chan); diff --git a/arch/arm/src/stm32wb/stm32wb_irq.c b/arch/arm/src/stm32wb/stm32wb_irq.c index f87503a7802..d03886cee30 100644 --- a/arch/arm/src/stm32wb/stm32wb_irq.c +++ b/arch/arm/src/stm32wb/stm32wb_irq.c @@ -65,7 +65,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -73,7 +73,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wb_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -129,11 +129,11 @@ static void stm32wb_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wb_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wb_nmi, stm32wb_pendsv,stm32wb_pendsv, stm32wb_reserved + * Name: stm32_nmi, stm32_pendsv,stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -143,7 +143,7 @@ static void stm32wb_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wb_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -151,7 +151,7 @@ static int stm32wb_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wb_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -159,7 +159,7 @@ static int stm32wb_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wb_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -169,7 +169,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wb_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -177,7 +177,7 @@ static int stm32wb_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wb_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -190,7 +190,7 @@ static inline void stm32wb_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wb_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -198,7 +198,7 @@ static inline void stm32wb_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wb_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -328,7 +328,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wb_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -342,19 +342,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32wb_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32wb_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32wb_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wb_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -379,7 +379,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -414,7 +414,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wb_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -491,7 +491,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wb_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.c b/arch/arm/src/stm32wb/stm32wb_lowputc.c index c8807a1f5bf..9175c37cffd 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.c +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.c @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_rcc.h" #include "stm32wb_gpio.h" #include "stm32wb_uart.h" @@ -214,7 +214,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -225,7 +225,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -233,7 +233,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -242,7 +242,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wb_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -258,19 +258,19 @@ void stm32wb_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wb_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32wb_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32wb_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32wb_configgpio(STM32_CONSOLE_RS485_DIR); - stm32wb_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_lowputc.h b/arch/arm/src/stm32wb/stm32wb_lowputc.h index 8a8ca85b338..bd55c77c74f 100644 --- a/arch/arm/src/stm32wb/stm32wb_lowputc.h +++ b/arch/arm/src/stm32wb/stm32wb_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index 232e03af6f7..f92be7547f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -48,14 +48,14 @@ /* Mailbox shared buffer fields */ -#define stm32wb_mbox_shared \ - (*(struct stm32wb_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) +#define stm32_mbox_shared \ + (*(struct stm32_mbox_shared_buffer_s *)STM32_MBOX_SHARED_BASE) -#define stm32wb_mbox_ref_table (stm32wb_mbox_shared.ref_table) -#define stm32wb_mbox_di_table (stm32wb_mbox_shared.dev_info_table) -#define stm32wb_mbox_sys_table (stm32wb_mbox_shared.sys_table) -#define stm32wb_mbox_mm_table (stm32wb_mbox_shared.mm_table) -#define stm32wb_mbox_ble_table (stm32wb_mbox_shared.ble_table) +#define stm32_mbox_ref_table (stm32_mbox_shared.ref_table) +#define stm32_mbox_di_table (stm32_mbox_shared.dev_info_table) +#define stm32_mbox_sys_table (stm32_mbox_shared.sys_table) +#define stm32_mbox_mm_table (stm32_mbox_shared.mm_table) +#define stm32_mbox_ble_table (stm32_mbox_shared.ble_table) /* Mailbox buffer sizes */ @@ -72,19 +72,19 @@ /* Mailbox shared buffer structures */ -begin_packed_struct struct stm32wb_mbox_safe_boot_info_table_s +begin_packed_struct struct stm32_mbox_safe_boot_info_table_s { uint32_t version; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_fus_info_table_s +begin_packed_struct struct stm32_mbox_fus_info_table_s { uint32_t version; uint32_t memory_size; uint32_t fus_info; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s +begin_packed_struct struct stm32_mbox_wireless_fw_info_table_s { uint32_t version; uint32_t memory_size; @@ -92,14 +92,14 @@ begin_packed_struct struct stm32wb_mbox_wireless_fw_info_table_s uint32_t reserved; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_device_info_table_s +begin_packed_struct struct stm32_mbox_device_info_table_s { - struct stm32wb_mbox_safe_boot_info_table_s safe_boot_info_table; - struct stm32wb_mbox_fus_info_table_s fus_info_table; - struct stm32wb_mbox_wireless_fw_info_table_s wireless_fw_info_table; + struct stm32_mbox_safe_boot_info_table_s safe_boot_info_table; + struct stm32_mbox_fus_info_table_s fus_info_table; + struct stm32_mbox_wireless_fw_info_table_s wireless_fw_info_table; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ble_table_s +begin_packed_struct struct stm32_mbox_ble_table_s { void *cmd_buffer; void *cs_buffer; @@ -107,13 +107,13 @@ begin_packed_struct struct stm32wb_mbox_ble_table_s void *acl_buffer; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_sys_table_s +begin_packed_struct struct stm32_mbox_sys_table_s { void *cmd_buffer; void *evt_queue; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_mem_manager_table_s +begin_packed_struct struct stm32_mbox_mem_manager_table_s { void *ble_spare_buffer; void *sys_spare_buffer; @@ -124,13 +124,13 @@ begin_packed_struct struct stm32wb_mbox_mem_manager_table_s uint32_t traces_evtpool_size; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_ref_table_s +begin_packed_struct struct stm32_mbox_ref_table_s { - struct stm32wb_mbox_device_info_table_s *dev_info_table; - struct stm32wb_mbox_ble_table_s *ble_table; + struct stm32_mbox_device_info_table_s *dev_info_table; + struct stm32_mbox_ble_table_s *ble_table; void *thread_table; - struct stm32wb_mbox_sys_table_s *sys_table; - struct stm32wb_mbox_mem_manager_table_s *mm_table; + struct stm32_mbox_sys_table_s *sys_table; + struct stm32_mbox_mem_manager_table_s *mm_table; void *traces_table; void *mac_802_15_4_table; void *zigbee_table; @@ -140,20 +140,20 @@ begin_packed_struct struct stm32wb_mbox_ref_table_s /* Mailbox shared buffer memory layout structure */ -struct stm32wb_mbox_shared_buffer_s +struct stm32_mbox_shared_buffer_s { - aligned_data(4) struct stm32wb_mbox_ref_table_s ref_table; + aligned_data(4) struct stm32_mbox_ref_table_s ref_table; - aligned_data(4) struct stm32wb_mbox_device_info_table_s dev_info_table; - aligned_data(4) struct stm32wb_mbox_ble_table_s ble_table; - aligned_data(4) struct stm32wb_mbox_sys_table_s sys_table; - aligned_data(4) struct stm32wb_mbox_mem_manager_table_s mm_table; + aligned_data(4) struct stm32_mbox_device_info_table_s dev_info_table; + aligned_data(4) struct stm32_mbox_ble_table_s ble_table; + aligned_data(4) struct stm32_mbox_sys_table_s sys_table; + aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; - aligned_data(4) stm32wb_mbox_list_t evtfree_buffer; + aligned_data(4) stm32_mbox_list_t evtfree_buffer; #ifdef CONFIG_STM32WB_BLE - aligned_data(4) stm32wb_mbox_list_t ble_evt_queue; + aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif - aligned_data(4) stm32wb_mbox_list_t sys_evt_queue; + aligned_data(4) stm32_mbox_list_t sys_evt_queue; #ifdef CONFIG_STM32WB_BLE aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; @@ -170,11 +170,11 @@ struct stm32wb_mbox_shared_buffer_s /* Mailbox channel data type */ -struct stm32wb_mbox_channel_s +struct stm32_mbox_channel_s { uint8_t ch_num; - stm32wb_mbox_list_t cmd_buf_queue; - struct stm32wb_mbox_cmd_s *cmd_buf; + stm32_mbox_list_t cmd_buf_queue; + struct stm32_mbox_cmd_s *cmd_buf; bool ack_ready; }; @@ -182,18 +182,18 @@ struct stm32wb_mbox_channel_s * Private Function prototypes ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg); +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg); -static void stm32wb_mbox_rxworker(void *arg); -static void stm32wb_mbox_txworker(void *arg); +static void stm32_mbox_rxworker(void *arg); +static void stm32_mbox_txworker(void *arg); -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt); -static void stm32wb_mbox_acksyscmd(void); +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt); +static void stm32_mbox_acksyscmd(void); -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len); -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan); /**************************************************************************** * Private Data @@ -202,26 +202,26 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan); static struct work_s g_rx_evt_work; static struct work_s g_tx_cmd_work; -static stm32wb_mbox_list_t g_rx_evt_queue; -static stm32wb_mbox_list_t g_tx_evtfree_queue; +static stm32_mbox_list_t g_rx_evt_queue; +static stm32_mbox_list_t g_tx_evtfree_queue; static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] [STM32_MBOX_CMDPKT_BUF_SIZE]; -static stm32wb_mbox_list_t g_free_buffers_pool; +static stm32_mbox_list_t g_free_buffers_pool; -static struct stm32wb_mbox_channel_s g_syscmd_channel; +static struct stm32_mbox_channel_s g_syscmd_channel; #ifdef CONFIG_STM32WB_BLE -static struct stm32wb_mbox_channel_s g_blecmd_channel; -static struct stm32wb_mbox_channel_s g_bleacl_channel; +static struct stm32_mbox_channel_s g_blecmd_channel; +static struct stm32_mbox_channel_s g_bleacl_channel; #endif -static stm32wb_mbox_evt_handler_t receive_evt_handler; +static stm32_mbox_evt_handler_t receive_evt_handler; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_ipcc_rxoisr + * Name: stm32_ipcc_rxoisr * * Description: * RX channel occupied interrupt handler (communication data posted @@ -229,15 +229,15 @@ static stm32wb_mbox_evt_handler_t receive_evt_handler; * ****************************************************************************/ -static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) { uint32_t clrmask = 0; /* Pull events from system channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_SYSEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.sys_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.sys_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); @@ -247,9 +247,9 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) /* Pull events from BLE channel into processing queue */ - if (stm32wb_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) + if (stm32_ipcc_rxactive(STM32_MBOX_BLEEVT_CHANNEL)) { - stm32wb_mbox_list_moveall(&stm32wb_mbox_shared.ble_evt_queue, + stm32_mbox_list_moveall(&stm32_mbox_shared.ble_evt_queue, &g_rx_evt_queue); clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_BLEEVT_CHANNEL); @@ -260,7 +260,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_rx_evt_work)) { - work_queue(HPWORK, &g_rx_evt_work, stm32wb_mbox_rxworker, NULL, 0); + work_queue(HPWORK, &g_rx_evt_work, stm32_mbox_rxworker, NULL, 0); } /* Clear active statuses */ @@ -269,7 +269,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_ipcc_txfisr + * Name: stm32_ipcc_txfisr * * Description: * TX channel free interrupt handler (communication data retrieved @@ -277,7 +277,7 @@ static void stm32wb_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) * ****************************************************************************/ -static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) +static void stm32_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { uint32_t c1mr = getreg32(STM32_IPCC_C1MR); uint32_t txfsrc; @@ -296,14 +296,14 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) { /* Move all released events (if any) into transmission mailbox */ - if (!stm32wb_mbox_list_is_empty(&g_tx_evtfree_queue)) + if (!stm32_mbox_list_is_empty(&g_tx_evtfree_queue)) { - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start release channel transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } } @@ -327,7 +327,7 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) if (work_available(&g_tx_cmd_work)) { - work_queue(HPWORK, &g_tx_cmd_work, stm32wb_mbox_txworker, NULL, 0); + work_queue(HPWORK, &g_tx_cmd_work, stm32_mbox_txworker, NULL, 0); } } @@ -337,10 +337,10 @@ static void stm32wb_ipcc_txfisr(int irq, uint32_t *regs, void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_txworker + * Name: stm32_mbox_txworker ****************************************************************************/ -static void stm32wb_mbox_txworker(void *arg) +static void stm32_mbox_txworker(void *arg) { bool handled; @@ -350,28 +350,28 @@ static void stm32wb_mbox_txworker(void *arg) { handled = false; - if (!stm32wb_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_SYSCMD_CHANNEL)) { /* Process ack response before send new command */ if (g_syscmd_channel.ack_ready) { - stm32wb_mbox_acksyscmd(); + stm32_mbox_acksyscmd(); g_syscmd_channel.ack_ready = false; } - handled = stm32wb_mbox_txnext(&g_syscmd_channel); + handled = stm32_mbox_txnext(&g_syscmd_channel); } #ifdef CONFIG_STM32WB_BLE - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_blecmd_channel); + handled |= stm32_mbox_txnext(&g_blecmd_channel); } - if (!stm32wb_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_BLEACL_CHANNEL)) { - handled |= stm32wb_mbox_txnext(&g_bleacl_channel); + handled |= stm32_mbox_txnext(&g_bleacl_channel); } #endif } @@ -379,12 +379,12 @@ static void stm32wb_mbox_txworker(void *arg) } /**************************************************************************** - * Name: stm32wb_mbox_rxworker + * Name: stm32_mbox_rxworker ****************************************************************************/ -static void stm32wb_mbox_rxworker(void *arg) +static void stm32_mbox_rxworker(void *arg) { - stm32wb_mbox_list_t *evt; + stm32_mbox_list_t *evt; irqstate_t flags; while (1) @@ -393,7 +393,7 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pull an event from the queue */ - evt = stm32wb_mbox_list_remove_head(&g_rx_evt_queue); + evt = stm32_mbox_list_remove_head(&g_rx_evt_queue); leave_critical_section(flags); @@ -404,18 +404,18 @@ static void stm32wb_mbox_rxworker(void *arg) /* Pass event to a callback function without a list header */ - receive_evt_handler((struct stm32wb_mbox_evt_s *)(evt + 1)); + receive_evt_handler((struct stm32_mbox_evt_s *)(evt + 1)); /* Free completed event. Released event needs to return to CPU2 * via release channel. */ - stm32wb_mbox_eventfree((stm32wb_mbox_list_t *)evt); + stm32_mbox_eventfree((stm32_mbox_list_t *)evt); } } /**************************************************************************** - * Name: stm32wb_mbox_txdata + * Name: stm32_mbox_txdata * * Description: * Send data over specified mailbox channel if possible. If the @@ -423,11 +423,11 @@ static void stm32wb_mbox_rxworker(void *arg) * ****************************************************************************/ -static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, +static int stm32_mbox_txdata(struct stm32_mbox_channel_s *chan, uint8_t type, void *data, size_t len) { irqstate_t flags; - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; flags = enter_critical_section(); @@ -435,8 +435,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * none of other waiting commands and none of unprocessed ack responses. */ - if (stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) && - !stm32wb_ipcc_txactive(chan->ch_num) && !chan->ack_ready) + if (stm32_mbox_list_is_empty(&chan->cmd_buf_queue) && + !stm32_ipcc_txactive(chan->ch_num) && !chan->ack_ready) { /* Channel is ready, copy command into transmission buffer */ @@ -446,8 +446,8 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Otherwise get temp buffer for command */ - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&g_free_buffers_pool); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&g_free_buffers_pool); } leave_critical_section(flags); @@ -464,9 +464,9 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, { /* Command is ready in mailbox buffer, start transmission now */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue) || + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue) || chan->ch_num == STM32_MBOX_SYSCMD_CHANNEL) { /* There are more commands awaiting, so unmask interrupt to get @@ -474,7 +474,7 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, * And the system channel needs to check ack on completion. */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } } else @@ -482,31 +482,31 @@ static int stm32wb_mbox_txdata(struct stm32wb_mbox_channel_s *chan, /* Command is in temp buffer, push it into queue */ flags = enter_critical_section(); - stm32wb_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&chan->cmd_buf_queue, &pkt_buf->list_hdr); leave_critical_section(flags); /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } return OK; } /**************************************************************************** - * Name: stm32wb_mbox_txnext + * Name: stm32_mbox_txnext * * Description: * Send next command from the queue. * ****************************************************************************/ -static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) +static bool stm32_mbox_txnext(struct stm32_mbox_channel_s *chan) { - struct stm32wb_mbox_cmd_s *pkt_buf; + struct stm32_mbox_cmd_s *pkt_buf; - pkt_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_list_remove_head(&chan->cmd_buf_queue); + pkt_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_list_remove_head(&chan->cmd_buf_queue); if (pkt_buf != NULL) { @@ -525,32 +525,32 @@ static bool stm32wb_mbox_txnext(struct stm32wb_mbox_channel_s *chan) /* Start transmission */ - stm32wb_ipcc_settxactive(chan->ch_num); + stm32_ipcc_settxactive(chan->ch_num); - if (!stm32wb_mbox_list_is_empty(&chan->cmd_buf_queue)) + if (!stm32_mbox_list_is_empty(&chan->cmd_buf_queue)) { /* Unmask TXF interrupt to get notified when completed */ - stm32wb_ipcc_unmasktxf(chan->ch_num); + stm32_ipcc_unmasktxf(chan->ch_num); } /* Put back to pool the freed command buffer */ - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); + stm32_mbox_list_add_tail(&g_free_buffers_pool, &pkt_buf->list_hdr); } return pkt_buf != NULL; } /**************************************************************************** - * Name: stm32wb_mbox_eventfree + * Name: stm32_mbox_eventfree * * Description: * Free handled mailbox event. * ****************************************************************************/ -static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) +static void stm32_mbox_eventfree(stm32_mbox_list_t *evt) { irqstate_t flags; @@ -558,48 +558,48 @@ static void stm32wb_mbox_eventfree(stm32wb_mbox_list_t *evt) /* Collect releasing events in the global list */ - stm32wb_mbox_list_add_tail(&g_tx_evtfree_queue, evt); + stm32_mbox_list_add_tail(&g_tx_evtfree_queue, evt); /* Check if release channel is ready to process now */ - if (!stm32wb_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) + if (!stm32_ipcc_txactive(STM32_MBOX_EVT_RELEASE_CHANNEL)) { /* Move all collected events into transmission queue */ - stm32wb_mbox_list_moveall(&g_tx_evtfree_queue, - &stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_moveall(&g_tx_evtfree_queue, + &stm32_mbox_shared.evtfree_buffer); /* Start transmission */ - stm32wb_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_settxactive(STM32_MBOX_EVT_RELEASE_CHANNEL); } else { /* Unmask interrupt to get notified when channel gets free */ - stm32wb_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); + stm32_ipcc_unmasktxf(STM32_MBOX_EVT_RELEASE_CHANNEL); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_mbox_acksyscmd + * Name: stm32_mbox_acksyscmd * * Description: * Send ACK response event for completed system command. * ****************************************************************************/ -static void stm32wb_mbox_acksyscmd(void) +static void stm32_mbox_acksyscmd(void) { - struct stm32wb_mbox_evt_s *evt; + struct stm32_mbox_evt_s *evt; /* System command ACK response is placed at the same address as the * processed command but without a list header. */ - evt = (struct stm32wb_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); + evt = (struct stm32_mbox_evt_s *)(&g_syscmd_channel.cmd_buf); evt->type = STM32_MBOX_SYSACK; receive_evt_handler(evt); @@ -610,7 +610,7 @@ static void stm32wb_mbox_acksyscmd(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -620,79 +620,79 @@ static void stm32wb_mbox_acksyscmd(void) * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) { int i; /* Init mailbox shared data */ - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.sys_evt_queue); - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.evtfree_buffer); + stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_list_initialize(&stm32wb_mbox_shared.ble_evt_queue); + stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif - stm32wb_mbox_ref_table.dev_info_table = &stm32wb_mbox_di_table; - stm32wb_mbox_ref_table.ble_table = &stm32wb_mbox_ble_table; - stm32wb_mbox_ref_table.sys_table = &stm32wb_mbox_sys_table; - stm32wb_mbox_ref_table.mm_table = &stm32wb_mbox_mm_table; + stm32_mbox_ref_table.dev_info_table = &stm32_mbox_di_table; + stm32_mbox_ref_table.ble_table = &stm32_mbox_ble_table; + stm32_mbox_ref_table.sys_table = &stm32_mbox_sys_table; + stm32_mbox_ref_table.mm_table = &stm32_mbox_mm_table; - stm32wb_mbox_sys_table.cmd_buffer = &stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_sys_table.evt_queue = &stm32wb_mbox_shared.sys_evt_queue; + stm32_mbox_sys_table.cmd_buffer = &stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_sys_table.evt_queue = &stm32_mbox_shared.sys_evt_queue; - stm32wb_mbox_mm_table.evtpool_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_buffer = &stm32_mbox_shared .evtpool_buffer; - stm32wb_mbox_mm_table.evtpool_size = sizeof(stm32wb_mbox_shared + stm32_mbox_mm_table.evtpool_size = sizeof(stm32_mbox_shared .evtpool_buffer); - stm32wb_mbox_mm_table.evtfree_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.evtfree_buffer = &stm32_mbox_shared .evtfree_buffer; - stm32wb_mbox_mm_table.sys_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_mm_table.ble_spare_buffer = &stm32wb_mbox_shared + stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif #ifdef CONFIG_STM32WB_BLE - stm32wb_mbox_ble_table.cmd_buffer = &stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_ble_table.acl_buffer = &stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_ble_table.cs_buffer = &stm32wb_mbox_shared.ble_cs_buffer; - stm32wb_mbox_ble_table.evt_queue = &stm32wb_mbox_shared.ble_evt_queue; + stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; + stm32_mbox_ble_table.evt_queue = &stm32_mbox_shared.ble_evt_queue; #endif /* Init system channel data */ g_syscmd_channel.ch_num = STM32_MBOX_SYSCMD_CHANNEL; - g_syscmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.sys_cmd_buffer; - stm32wb_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); + g_syscmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.sys_cmd_buffer; + stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); #ifdef CONFIG_STM32WB_BLE /* Init BLE command channel data */ g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; - g_blecmd_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_cmd_buffer; - stm32wb_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); + g_blecmd_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_cmd_buffer; + stm32_mbox_list_initialize(&g_blecmd_channel.cmd_buf_queue); /* Init BLE ACL channel data */ g_bleacl_channel.ch_num = STM32_MBOX_BLEACL_CHANNEL; - g_bleacl_channel.cmd_buf = (struct stm32wb_mbox_cmd_s *) - stm32wb_mbox_shared.ble_acl_buffer; - stm32wb_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); + g_bleacl_channel.cmd_buf = (struct stm32_mbox_cmd_s *) + stm32_mbox_shared.ble_acl_buffer; + stm32_mbox_list_initialize(&g_bleacl_channel.cmd_buf_queue); #endif /* Init local (not shared) queues */ - stm32wb_mbox_list_initialize(&g_rx_evt_queue); - stm32wb_mbox_list_initialize(&g_tx_evtfree_queue); + stm32_mbox_list_initialize(&g_rx_evt_queue); + stm32_mbox_list_initialize(&g_tx_evtfree_queue); - stm32wb_mbox_list_initialize(&g_free_buffers_pool); + stm32_mbox_list_initialize(&g_free_buffers_pool); for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) { - stm32wb_mbox_list_add_tail(&g_free_buffers_pool, - (stm32wb_mbox_list_t *)g_free_buffers[i]); + stm32_mbox_list_add_tail(&g_free_buffers_pool, + (stm32_mbox_list_t *)g_free_buffers[i]); } /* Set event receive function */ @@ -701,7 +701,7 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) } /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -709,16 +709,16 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler) * ****************************************************************************/ -void stm32wb_mboxenable(void) +void stm32_mboxenable(void) { uint32_t regval; /* Setup RXO and TXF interrupts */ - irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32wb_ipcc_rxoisr, NULL); + irq_attach(STM32_IRQ_IPCCRX, (xcpt_t)stm32_ipcc_rxoisr, NULL); up_enable_irq(STM32_IRQ_IPCCRX); - irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32wb_ipcc_txfisr, NULL); + irq_attach(STM32_IRQ_IPCCTX, (xcpt_t)stm32_ipcc_txfisr, NULL); up_enable_irq(STM32_IRQ_IPCCTX); regval = getreg32(STM32_IPCC_C1CR); @@ -729,15 +729,15 @@ void stm32wb_mboxenable(void) * to receive C2READY event via system channel. */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_SYSEVT_CHANNEL); /* Enable IPCC hardware and boot up CPU2 */ - stm32wb_ipccenable(); + stm32_ipccenable(); } /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -745,15 +745,15 @@ void stm32wb_mboxenable(void) * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len) +int stm32_mbox_syscmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, + return stm32_mbox_txdata(&g_syscmd_channel, STM32_MBOX_SYSCMD, data, len); } #ifdef CONFIG_STM32WB_BLE /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -761,14 +761,14 @@ int stm32wb_mbox_syscmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len) +int stm32_mbox_blecmd(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, + return stm32_mbox_txdata(&g_blecmd_channel, STM32_MBOX_HCICMD, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -776,27 +776,27 @@ int stm32wb_mbox_blecmd(void *data, size_t len) * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len) +int stm32_mbox_bleacl(void *data, size_t len) { - return stm32wb_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, + return stm32_mbox_txdata(&g_bleacl_channel, STM32_MBOX_HCIACL, data, len); } /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) { struct bt_hci_cmd_hdr_s *cmd; /* Just borrow a temporary free buffer for command data */ - cmd = (struct bt_hci_cmd_hdr_s *)stm32wb_mbox_shared.sys_spare_buffer; + cmd = (struct bt_hci_cmd_hdr_s *)stm32_mbox_shared.sys_spare_buffer; /* Prepare command data */ @@ -806,10 +806,10 @@ void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params) /* Send BLE init command to CPU2 */ - stm32wb_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); + stm32_mbox_syscmd(cmd, sizeof(*cmd) + sizeof(*params)); /* Unmask BLE event channel RXO interrupt */ - stm32wb_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); + stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } #endif /* CONFIG_STM32WB_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.h b/arch/arm/src/stm32wb/stm32wb_mbox.h index 6d5f9cc7932..2d7ea4b437c 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox.h @@ -77,7 +77,7 @@ /* Mailbox data transfer packets */ -begin_packed_struct struct stm32wb_mbox_evt_s +begin_packed_struct struct stm32_mbox_evt_s { uint8_t type; union @@ -87,9 +87,9 @@ begin_packed_struct struct stm32wb_mbox_evt_s }; } end_packed_struct; -begin_packed_struct struct stm32wb_mbox_cmd_s +begin_packed_struct struct stm32_mbox_cmd_s { - stm32wb_mbox_list_t list_hdr; + stm32_mbox_list_t list_hdr; uint8_t type; union { @@ -100,14 +100,14 @@ begin_packed_struct struct stm32wb_mbox_cmd_s /* Mailbox receive event handler type */ -typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); +typedef int (*stm32_mbox_evt_handler_t)(struct stm32_mbox_evt_s *); /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mboxinitialize + * Name: stm32_mboxinitialize * * Description: * Initialize mailbox driver memory. @@ -117,10 +117,10 @@ typedef int (*stm32wb_mbox_evt_handler_t)(struct stm32wb_mbox_evt_s *); * ****************************************************************************/ -void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); +void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler); /**************************************************************************** - * Name: stm32wb_mboxenable + * Name: stm32_mboxenable * * Description: * Enable mailbox hardware and start communication. The CPU2 responses @@ -128,10 +128,10 @@ void stm32wb_mboxinitialize(stm32wb_mbox_evt_handler_t evt_handler); * ****************************************************************************/ -void stm32wb_mboxenable(void); +void stm32_mboxenable(void); /**************************************************************************** - * Name: stm32wb_mbox_syscmd + * Name: stm32_mbox_syscmd * * Description: * Send command over mailbox system channel. Command data must be @@ -139,10 +139,10 @@ void stm32wb_mboxenable(void); * ****************************************************************************/ -int stm32wb_mbox_syscmd(void *data, size_t len); +int stm32_mbox_syscmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_blecmd + * Name: stm32_mbox_blecmd * * Description: * Send command over mailbox BLE channel. Command data must be @@ -150,10 +150,10 @@ int stm32wb_mbox_syscmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_blecmd(void *data, size_t len); +int stm32_mbox_blecmd(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleacl + * Name: stm32_mbox_bleacl * * Description: * Send BLE ACL data over mailbox BLE ACL channel. Data must be @@ -161,16 +161,16 @@ int stm32wb_mbox_blecmd(void *data, size_t len); * ****************************************************************************/ -int stm32wb_mbox_bleacl(void *data, size_t len); +int stm32_mbox_bleacl(void *data, size_t len); /**************************************************************************** - * Name: stm32wb_mbox_bleinit + * Name: stm32_mbox_bleinit * * Description: * Initialize and start BLE subsystem with provided configuration params. * ****************************************************************************/ -void stm32wb_mbox_bleinit(struct stm32wb_shci_ble_init_cfg_s *params); +void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MBOX_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_list.h b/arch/arm/src/stm32wb/stm32wb_mbox_list.h index 4208da7fbec..80b3838155d 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_list.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_list.h @@ -38,42 +38,42 @@ * a new list_moveall function. */ -begin_packed_struct struct stm32wb_mbox_list_s +begin_packed_struct struct stm32_mbox_list_s { - struct stm32wb_mbox_list_s *next; - struct stm32wb_mbox_list_s *prev; + struct stm32_mbox_list_s *next; + struct stm32_mbox_list_s *prev; } end_packed_struct; -typedef struct stm32wb_mbox_list_s stm32wb_mbox_list_t; +typedef struct stm32_mbox_list_s stm32_mbox_list_t; /**************************************************************************** * Inline Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mbox_list_initialize + * Name: stm32_mbox_list_initialize * * Description: * Initialize internal fields. * ****************************************************************************/ -static inline void stm32wb_mbox_list_initialize(stm32wb_mbox_list_t *list) +static inline void stm32_mbox_list_initialize(stm32_mbox_list_t *list) { list->prev = list; list->next = list; } /**************************************************************************** - * Name: stm32wb_mbox_list_add_tail + * Name: stm32_mbox_list_add_tail * * Description: * Add new node at the end of the list. * ****************************************************************************/ -static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, - stm32wb_mbox_list_t *item) +static inline void stm32_mbox_list_add_tail(stm32_mbox_list_t *list, + stm32_mbox_list_t *item) { item->prev = list->prev; item->next = list; @@ -82,19 +82,19 @@ static inline void stm32wb_mbox_list_add_tail(stm32wb_mbox_list_t *list, } /**************************************************************************** - * Name: stm32wb_mbox_list_remove_head + * Name: stm32_mbox_list_remove_head * * Description: * Remove and return first node from the list head (if any). * ****************************************************************************/ -static inline stm32wb_mbox_list_t * -stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) +static inline stm32_mbox_list_t * +stm32_mbox_list_remove_head(stm32_mbox_list_t *list) { if (list->next != list) { - stm32wb_mbox_list_t *item = list->next; + stm32_mbox_list_t *item = list->next; item->next->prev = item->prev; item->prev->next = item->next; item->prev = NULL; @@ -108,20 +108,20 @@ stm32wb_mbox_list_remove_head(stm32wb_mbox_list_t *list) } /**************************************************************************** - * Name: stm32wb_mbox_list_is_empty + * Name: stm32_mbox_list_is_empty * * Description: * Check if the list is empty. * ****************************************************************************/ -static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) +static inline bool stm32_mbox_list_is_empty(stm32_mbox_list_t *list) { return (list->next == list); } /**************************************************************************** - * Name: stm32wb_mbox_list_moveall + * Name: stm32_mbox_list_moveall * * Description: * Remove all nodes from source list and add them to the end of the @@ -129,8 +129,8 @@ static inline bool stm32wb_mbox_list_is_empty(stm32wb_mbox_list_t *list) * ****************************************************************************/ -static inline void stm32wb_mbox_list_moveall(stm32wb_mbox_list_t *src, - stm32wb_mbox_list_t *dst) +static inline void stm32_mbox_list_moveall(stm32_mbox_list_t *src, + stm32_mbox_list_t *dst) { if (src->next != src) { diff --git a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h index 442dee86f15..e1eeffeb066 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox_shci.h +++ b/arch/arm/src/stm32wb/stm32wb_mbox_shci.h @@ -119,7 +119,7 @@ /* STM32_SHCI_BLE_INIT command params */ -begin_packed_struct struct stm32wb_shci_ble_init_cfg_s +begin_packed_struct struct stm32_shci_ble_init_cfg_s { void *ble_buf; /* Not used, must be NULL. */ uint32_t ble_buf_size; /* Not used, must be 0. */ diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.c b/arch/arm/src/stm32wb/stm32wb_mpuinit.c index b9d878aadd0..acc1576a646 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.c +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wb_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wb_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wb_mpuinitialize(void) * ****************************************************************************/ -void stm32wb_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wb/stm32wb_mpuinit.h b/arch/arm/src/stm32wb/stm32wb_mpuinit.h index 1cc8d755c37..18ac01dea38 100644 --- a/arch/arm/src/stm32wb/stm32wb_mpuinit.h +++ b/arch/arm/src/stm32wb/stm32wb_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wb_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wb_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wb_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wb_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_MPUINIT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index bd8ffa00d19..9666c714bda 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -45,20 +45,20 @@ * Private Function Prototypes ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg); +static int stm32_oneshot_handler(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Common timer interrupt callback. When any oneshot timer interrupt @@ -73,9 +73,9 @@ static struct stm32wb_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; * ****************************************************************************/ -static int stm32wb_oneshot_handler(int irq, void *context, void *arg) +static int stm32_oneshot_handler(int irq, void *context, void *arg) { - struct stm32wb_oneshot_s *oneshot = (struct stm32wb_oneshot_s *)arg; + struct stm32_oneshot_s *oneshot = (struct stm32_oneshot_s *)arg; oneshot_handler_t oneshot_handler; void *oneshot_arg; @@ -107,7 +107,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_allocate_handler + * Name: stm32_allocate_handler * * Description: * Allocate a timer callback handler for the oneshot instance. @@ -121,7 +121,7 @@ static int stm32wb_oneshot_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) +static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { #if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; @@ -162,7 +162,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -180,7 +180,7 @@ static inline int stm32wb_allocate_handler(struct stm32wb_oneshot_s *oneshot) * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution) { uint32_t frequency; @@ -193,7 +193,7 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, frequency = USEC_PER_SEC / (uint32_t)resolution; oneshot->frequency = frequency; - oneshot->tch = stm32wb_tim_init(chan); + oneshot->tch = stm32_tim_init(chan); if (!oneshot->tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", chan); @@ -211,18 +211,18 @@ int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, /* Assign a callback handler to the oneshot */ - return stm32wb_allocate_handler(oneshot); + return stm32_allocate_handler(oneshot); } /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) { DEBUGASSERT(oneshot != NULL && usec != NULL); @@ -233,7 +233,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -241,7 +241,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -252,7 +252,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts) { @@ -273,7 +273,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Yes.. then cancel it */ tmrinfo("Already running... cancelling\n"); - stm32wb_oneshot_cancel(oneshot, NULL); + stm32_oneshot_cancel(oneshot, NULL); } /* Save the new handler and its argument */ @@ -301,7 +301,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, /* Set up to receive the callback when the interrupt occurs */ - STM32_TIM_SETISR(oneshot->tch, stm32wb_oneshot_handler, oneshot, 0); + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, oneshot, 0); /* Set timer period */ @@ -325,7 +325,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, } /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -336,7 +336,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. ts may be zero in which case the time remaining @@ -349,7 +349,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts) { irqstate_t flags; diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index 37d45ac8ed2..d84e8f15b1c 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -67,20 +67,20 @@ typedef void (*oneshot_handler_t)(void *arg); /* The oneshot client must allocate an instance of this structure and called - * stm32wb_oneshot_initialize() before using the oneshot facilities. The + * stm32_oneshot_initialize() before using the oneshot facilities. The * client should not access the contents of this structure directly since * the contents are subject to change. */ -struct stm32wb_oneshot_s +struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ #if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ volatile oneshot_handler_t handler; /* Oneshot expiration callback */ volatile void *arg; /* The argument that will accompany * the callback */ @@ -106,7 +106,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_initialize + * Name: stm32_oneshot_initialize * * Description: * Initialize the oneshot timer wrapper @@ -124,22 +124,22 @@ extern "C" * ****************************************************************************/ -int stm32wb_oneshot_initialize(struct stm32wb_oneshot_s *oneshot, int chan, +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, uint16_t resolution); /**************************************************************************** - * Name: stm32wb_oneshot_max_delay + * Name: stm32_oneshot_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) * ****************************************************************************/ -int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); /**************************************************************************** - * Name: stm32wb_oneshot_start + * Name: stm32_oneshot_start * * Description: * Start the oneshot timer @@ -147,7 +147,7 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * handler The function to call when when the oneshot timer expires. * arg An opaque argument that will accompany the callback. * ts Provides the duration of the one shot timer. @@ -158,12 +158,12 @@ int stm32wb_oneshot_max_delay(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, oneshot_handler_t handler, void *arg, const struct timespec *ts); /**************************************************************************** - * Name: stm32wb_oneshot_cancel + * Name: stm32_oneshot_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -174,7 +174,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * Input Parameters: * oneshot Caller allocated instance of the oneshot state structure. This * structure must have been previously initialized via a call to - * stm32wb_oneshot_initialize(); + * stm32_oneshot_initialize(); * ts The location in which to return the time remaining on the * oneshot timer. A time of zero is returned if the timer is * not running. @@ -186,7 +186,7 @@ int stm32wb_oneshot_start(struct stm32wb_oneshot_s *oneshot, * ****************************************************************************/ -int stm32wb_oneshot_cancel(struct stm32wb_oneshot_s *oneshot, +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, struct timespec *ts); #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c index 4c1b7030377..d98270362c4 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot_lowerhalf.c @@ -45,32 +45,32 @@ * driver */ -struct stm32wb_oneshot_lowerhalf_s +struct stm32_oneshot_lowerhalf_s { /* This is the part of the lower half driver that is visible to the upper- * half client of the driver. This must be the first thing in this * structure so that pointers to struct oneshot_lowerhalf_s are cast - * compatible to struct stm32wb_oneshot_lowerhalf_s and vice versa. + * compatible to struct stm32_oneshot_lowerhalf_s and vice versa. */ struct oneshot_lowerhalf_s lh; /* Common lower-half driver fields */ /* Private lower half data follows */ - struct stm32wb_oneshot_s oneshot; /* STM32-specific oneshot state */ + struct stm32_oneshot_s oneshot; /* STM32-specific oneshot state */ }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg); +static void stm32_oneshot_handler(void *arg); -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts); -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts); -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts); /**************************************************************************** @@ -81,9 +81,9 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, static const struct oneshot_operations_s g_oneshot_ops = { - .max_delay = stm32wb_max_delay, - .start = stm32wb_start, - .cancel = stm32wb_cancel, + .max_delay = stm32_max_delay, + .start = stm32_start, + .cancel = stm32_cancel, }; /**************************************************************************** @@ -91,13 +91,13 @@ static const struct oneshot_operations_s g_oneshot_ops = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_oneshot_handler + * Name: stm32_oneshot_handler * * Description: * Timer expiration handler * * Input Parameters: - * arg - Should be the same argument provided when stm32wb_oneshot_start() + * arg - Should be the same argument provided when stm32_oneshot_start() * was called. * * Returned Value: @@ -105,22 +105,22 @@ static const struct oneshot_operations_s g_oneshot_ops = * ****************************************************************************/ -static void stm32wb_oneshot_handler(void *arg) +static void stm32_oneshot_handler(void *arg) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)arg; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)arg; DEBUGASSERT(priv != NULL); /* Perhaps the callback was nullified in a race condition with - * stm32wb_cancel? + * stm32_cancel? */ oneshot_process_callback(&priv->lh); } /**************************************************************************** - * Name: stm32wb_max_delay + * Name: stm32_max_delay * * Description: * Determine the maximum delay of the one-shot timer (in microseconds) @@ -137,16 +137,16 @@ static void stm32wb_oneshot_handler(void *arg) * ****************************************************************************/ -static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, +static int stm32_max_delay(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; uint64_t usecs; int ret; DEBUGASSERT(priv != NULL && ts != NULL); - ret = stm32wb_oneshot_max_delay(&priv->oneshot, &usecs); + ret = stm32_oneshot_max_delay(&priv->oneshot, &usecs); if (ret >= 0) { uint64_t sec = usecs / 1000000; @@ -160,7 +160,7 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the oneshot timer @@ -179,11 +179,11 @@ static int stm32wb_max_delay(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_start(struct oneshot_lowerhalf_s *lower, +static int stm32_start(struct oneshot_lowerhalf_s *lower, const struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -192,20 +192,20 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, /* Save the callback information and start the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_start(&priv->oneshot, - stm32wb_oneshot_handler, priv, ts); + ret = stm32_oneshot_start(&priv->oneshot, + stm32_oneshot_handler, priv, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_start failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_start failed: %d\n", flags); } return ret; } /**************************************************************************** - * Name: stm32wb_cancel + * Name: stm32_cancel * * Description: * Cancel the oneshot timer and return the time remaining on the timer. @@ -228,11 +228,11 @@ static int stm32wb_start(struct oneshot_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, +static int stm32_cancel(struct oneshot_lowerhalf_s *lower, struct timespec *ts) { - struct stm32wb_oneshot_lowerhalf_s *priv = - (struct stm32wb_oneshot_lowerhalf_s *)lower; + struct stm32_oneshot_lowerhalf_s *priv = + (struct stm32_oneshot_lowerhalf_s *)lower; irqstate_t flags; int ret; @@ -241,12 +241,12 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, /* Cancel the timer */ flags = enter_critical_section(); - ret = stm32wb_oneshot_cancel(&priv->oneshot, ts); + ret = stm32_oneshot_cancel(&priv->oneshot, ts); leave_critical_section(flags); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_cancel failed: %d\n", flags); + tmrerr("ERROR: stm32_oneshot_cancel failed: %d\n", flags); } return ret; @@ -277,13 +277,13 @@ static int stm32wb_cancel(struct oneshot_lowerhalf_s *lower, struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) { - struct stm32wb_oneshot_lowerhalf_s *priv; + struct stm32_oneshot_lowerhalf_s *priv; int ret; /* Allocate an instance of the lower half driver */ - priv = (struct stm32wb_oneshot_lowerhalf_s *) - kmm_zalloc(sizeof(struct stm32wb_oneshot_lowerhalf_s)); + priv = (struct stm32_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct stm32_oneshot_lowerhalf_s)); if (priv == NULL) { @@ -297,10 +297,10 @@ struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) /* Initialize the contained STM32 oneshot timer */ - ret = stm32wb_oneshot_initialize(&priv->oneshot, chan, resolution); + ret = stm32_oneshot_initialize(&priv->oneshot, chan, resolution); if (ret < 0) { - tmrerr("ERROR: stm32wb_oneshot_initialize failed: %d\n", ret); + tmrerr("ERROR: stm32_oneshot_initialize failed: %d\n", ret); kmm_free(priv); return NULL; } diff --git a/arch/arm/src/stm32wb/stm32wb_pm.h b/arch/arm/src/stm32wb/stm32wb_pm.h index 3876288bc1a..9da094f711e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pm.h +++ b/arch/arm/src/stm32wb/stm32wb_pm.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -66,10 +66,10 @@ extern "C" * ****************************************************************************/ -int stm32wb_pmstop(bool lpds); +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -84,10 +84,10 @@ int stm32wb_pmstop(bool lpds); * ****************************************************************************/ -int stm32wb_pmstop2(void); +int stm32_pmstop2(void); /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -103,10 +103,10 @@ int stm32wb_pmstop2(void); * ****************************************************************************/ -int stm32wb_pmstandby(void); +int stm32_pmstandby(void); /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -122,10 +122,10 @@ int stm32wb_pmstandby(void); * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit); +void stm32_pmsleep(bool sleeponexit); /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -140,7 +140,7 @@ void stm32wb_pmsleep(bool sleeponexit); * ****************************************************************************/ -int stm32wb_pmlpr(void); +int stm32_pmlpr(void); #undef EXTERN #ifdef __cplusplus diff --git a/arch/arm/src/stm32wb/stm32wb_pmlpr.c b/arch/arm/src/stm32wb/stm32wb_pmlpr.c index fa601b27961..a86617edbfa 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmlpr.c +++ b/arch/arm/src/stm32wb/stm32wb_pmlpr.c @@ -39,7 +39,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmlpr + * Name: stm32_pmlpr * * Description: * Enter Low-Power Run (LPR) mode. @@ -54,7 +54,7 @@ * ****************************************************************************/ -int stm32wb_pmlpr(void) +int stm32_pmlpr(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmsleep.c b/arch/arm/src/stm32wb/stm32wb_pmsleep.c index b9b64dd940c..8a2b0d62967 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmsleep.c +++ b/arch/arm/src/stm32wb/stm32wb_pmsleep.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmsleep + * Name: stm32_pmsleep * * Description: * Enter SLEEP mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -void stm32wb_pmsleep(bool sleeponexit) +void stm32_pmsleep(bool sleeponexit) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstandby.c b/arch/arm/src/stm32wb/stm32wb_pmstandby.c index 657f4bf6779..09b81ae0236 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstandby.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstandby.c @@ -37,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstandby + * Name: stm32_pmstandby * * Description: * Enter STANDBY mode. @@ -53,7 +53,7 @@ * ****************************************************************************/ -int stm32wb_pmstandby(void) +int stm32_pmstandby(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pmstop.c b/arch/arm/src/stm32wb/stm32wb_pmstop.c index 1cbd80f0e23..31a53a91602 100644 --- a/arch/arm/src/stm32wb/stm32wb_pmstop.c +++ b/arch/arm/src/stm32wb/stm32wb_pmstop.c @@ -72,7 +72,7 @@ static int do_stop(void) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pmstop + * Name: stm32_pmstop * * Description: * Enter STOP mode. @@ -90,7 +90,7 @@ static int do_stop(void) * ****************************************************************************/ -int stm32wb_pmstop(bool lpds) +int stm32_pmstop(bool lpds) { uint32_t regval; @@ -114,7 +114,7 @@ int stm32wb_pmstop(bool lpds) } /**************************************************************************** - * Name: stm32wb_pmstop2 + * Name: stm32_pmstop2 * * Description: * Enter STOP2 mode. @@ -129,7 +129,7 @@ int stm32wb_pmstop(bool lpds) * ****************************************************************************/ -int stm32wb_pmstop2(void) +int stm32_pmstop2(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.c b/arch/arm/src/stm32wb/stm32wb_pwr.c index 62fe1b7be84..7e7338b9e1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.c +++ b/arch/arm/src/stm32wb/stm32wb_pwr.c @@ -39,17 +39,17 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wb_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg32(STM32_PWR_BASE + (uint32_t)offset, @@ -61,7 +61,7 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers and backup @@ -75,14 +75,14 @@ static inline void stm32wb_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WB PWR control register 1 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -92,14 +92,14 @@ bool stm32wb_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wb_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -110,7 +110,7 @@ bool stm32wb_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -125,14 +125,14 @@ bool stm32wb_pwr_enablebkp(bool writable) * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set) +bool stm32_pwr_enableusv(bool set) { uint32_t regval; bool was_set; /* Get the current state of the STM32WB PWR control register 2 */ - regval = stm32wb_pwr_getreg(STM32_PWR_CR2_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR2_OFFSET); was_set = ((regval & PWR_CR2_USV) != 0); /* Enable or disable the ability to write */ @@ -142,14 +142,14 @@ bool stm32wb_pwr_enableusv(bool set) /* Disable the Vddusb monitoring */ regval &= ~PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } else if (!was_set && set) { /* Enable the Vddusb monitoring */ regval |= PWR_CR2_USV; - stm32wb_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR2_OFFSET, regval); } return was_set; diff --git a/arch/arm/src/stm32wb/stm32wb_pwr.h b/arch/arm/src/stm32wb/stm32wb_pwr.h index e9dea014de0..9f2e517dc7c 100644 --- a/arch/arm/src/stm32wb/stm32wb_pwr.h +++ b/arch/arm/src/stm32wb/stm32wb_pwr.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wb_pwr_enableusv + * Name: stm32_pwr_enableusv * * Description: * Enables or disables the USB Supply Valid monitoring. Setting this bit @@ -86,7 +86,7 @@ bool stm32wb_pwr_enablebkp(bool writable); * ****************************************************************************/ -bool stm32wb_pwr_enableusv(bool set); +bool stm32_pwr_enableusv(bool set); /**************************************************************************** * Name: stm32_pwr_setvos diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index e731a9448e5..5a7bb4f22ba 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -504,7 +504,7 @@ static inline void rcc_enableccip(void) } /**************************************************************************** - * Name: stm32wb_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -514,7 +514,7 @@ static inline void rcc_enableccip(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -static void stm32wb_stdclockconfig(void) +static void stm32_stdclockconfig(void) { uint32_t regval; volatile int32_t timeout; @@ -604,7 +604,7 @@ static void stm32wb_stdclockconfig(void) } #else -# error stm32wb_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -789,7 +789,7 @@ static void stm32wb_stdclockconfig(void) #if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wb_rcc_enable_lsi(); + stm32_rcc_enable_lsi(); #endif #if defined(STM32_USE_LSE) @@ -805,7 +805,7 @@ static void stm32wb_stdclockconfig(void) * this for automatically trimming MSI, etc. */ - stm32wb_rcc_enable_lse(); + stm32_rcc_enable_lse(); # if defined(STM32_BOARD_USEMSI) /* Now that LSE is up, auto trim the MSI */ @@ -846,7 +846,7 @@ static inline void rcc_enableperipherals(void) #ifdef STM32_USE_HSI48 /* Enable HSI48 clocking to support USB transfers or RNG */ - stm32wb_enable_hsi48(STM32_HSI48_SYNCSRC); + stm32_enable_hsi48(STM32_HSI48_SYNCSRC); #endif } @@ -878,7 +878,7 @@ static inline void rcc_resetbkp(void) /* Check if the RTC is already configured */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -895,7 +895,7 @@ static inline void rcc_resetbkp(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -914,7 +914,7 @@ static inline void rcc_resetbkp(void) } } - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } #else @@ -922,7 +922,7 @@ static inline void rcc_resetbkp(void) #endif /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -932,7 +932,7 @@ static inline void rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -942,7 +942,7 @@ static inline void rcc_resetbkp(void) * ****************************************************************************/ -void stm32wb_clockconfig(void) +void stm32_clockconfig(void) { /* Make sure that we are starting in the reset state */ @@ -956,7 +956,7 @@ void stm32wb_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -964,7 +964,7 @@ void stm32wb_clockconfig(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif @@ -974,7 +974,7 @@ void stm32wb_clockconfig(void) } /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -984,12 +984,12 @@ void stm32wb_clockconfig(void) * re-enable/re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -1000,13 +1000,13 @@ void stm32wb_clockconfig(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wb_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -1014,7 +1014,7 @@ void stm32wb_clockenable(void) * board.h */ - stm32wb_stdclockconfig(); + stm32_stdclockconfig(); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index e6e675a3534..a8cd788caeb 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -68,7 +68,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output and clock divider on MC pin @@ -84,7 +84,7 @@ typedef enum crs_syncsrc_e crs_syncsrc_t; * ****************************************************************************/ -static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) +static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) { uint32_t regval; @@ -107,7 +107,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -117,7 +117,7 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -127,10 +127,10 @@ static inline void stm32wb_mcoconfig(uint32_t source, uint32_t divider) * ****************************************************************************/ -void stm32wb_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wb_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WB board may replace the "standard" board clock configuration @@ -139,11 +139,11 @@ void stm32wb_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG -void stm32wb_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wb_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -153,12 +153,12 @@ void stm32wb_board_clockconfig(void); * re-start the PLL * * This functional performs a subset of the operations performed by - * stm32wb_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wb_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -169,11 +169,11 @@ void stm32wb_board_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wb_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -186,30 +186,30 @@ void stm32wb_clockenable(void); * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void); +void stm32_rcc_enable_lse(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void); +void stm32_rcc_enable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void); +void stm32_rcc_disable_lsi(void); /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -235,10 +235,10 @@ void stm32wb_rcc_disable_lsi(void); * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc); /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -251,7 +251,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc); * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void); +void stm32_rcc_disable_hsi48(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c index abdb78b4b44..c3276e6d236 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_hsi48.c @@ -35,7 +35,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_hsi48 + * Name: stm32_rcc_enable_hsi48 * * Description: * HSI48 clock signal is generated from an internal 48 MHz RC oscillator @@ -61,7 +61,7 @@ * ****************************************************************************/ -void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) +void stm32_rcc_enable_hsi48(crs_syncsrc_t syncsrc) { uint32_t regval; @@ -130,7 +130,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) } /**************************************************************************** - * Name: stm32wb_rcc_disable_hsi48 + * Name: stm32_rcc_disable_hsi48 * * Description: * Disable the HSI48 clock. @@ -143,7 +143,7 @@ void stm32wb_rcc_enable_hsi48(crs_syncsrc_t syncsrc) * ****************************************************************************/ -void stm32wb_rcc_disable_hsi48(void) +void stm32_rcc_disable_hsi48(void) { uint32_t regval; diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index e032a1a1c6d..1e56d0e3cd8 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -54,14 +54,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lse + * Name: stm32_rcc_enable_lse * * Description: * Enable the External Low-Speed (LSE) oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lse(void) +void stm32_rcc_enable_lse(void) { bool writable; uint32_t regval; @@ -78,7 +78,7 @@ void stm32wb_rcc_enable_lse(void) * in the PWR CR register before to configuring the LSE. */ - writable = stm32wb_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the * LSEON bit the RCC BDCR register. @@ -100,7 +100,7 @@ void stm32wb_rcc_enable_lse(void) while (((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSERDY) == 0) { - stm32wb_waste(); + stm32_waste(); } #if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ @@ -121,6 +121,6 @@ void stm32wb_rcc_enable_lse(void) /* Disable backup domain access if it was disabled on entry */ - stm32wb_pwr_enablebkp(writable); + stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c index 9fa23cfc73a..7dcdc39a50b 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lsi.c @@ -34,14 +34,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rcc_enable_lsi + * Name: stm32_rcc_enable_lsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_enable_lsi(void) +void stm32_rcc_enable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -55,14 +55,14 @@ void stm32wb_rcc_enable_lsi(void) } /**************************************************************************** - * Name: stm32wb_rcc_disable_lsi + * Name: stm32_rcc_disable_lsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wb_rcc_disable_lsi(void) +void stm32_rcc_disable_lsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index 78c793ef038..2b849fd12c2 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -199,7 +199,7 @@ static void rtc_wprunlock(void) { /* Enable write access to the backup domain. */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* The following steps are required to unlock the write protection on * all the RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and @@ -237,7 +237,7 @@ static inline void rtc_wprlock(void) /* Disable write access to the backup domain. */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /**************************************************************************** @@ -436,7 +436,7 @@ static void rtc_resume(void) } /**************************************************************************** - * Name: stm32wb_rtc_alarm_handler + * Name: stm32_rtc_alarm_handler * * Description: * RTC ALARM interrupt service routine through the EXTI line @@ -451,7 +451,7 @@ static void rtc_resume(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_alarm_handler(int irq, void *context, +static int stm32_rtc_alarm_handler(int irq, void *context, void *rtc_handler_arg) { struct alm_cbinfo_s *cbinfo; @@ -465,7 +465,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Check for EXTI from Alarm A or B and handle according */ @@ -531,7 +531,7 @@ static int stm32wb_rtc_alarm_handler(int irq, void *context, * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); return ret; } @@ -737,14 +737,14 @@ static inline void rtc_enable_alarm(void) * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). */ - stm32wb_exti_alarm(true, false, true, stm32wb_rtc_alarm_handler, NULL); + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler, NULL); g_alarm_enabled = true; } } #endif /**************************************************************************** - * Name: stm32wb_rtc_getalarmdatetime + * Name: stm32_rtc_getalarmdatetime * * Description: * Get the current date and time for a RTC alarm. @@ -759,7 +759,7 @@ static inline void rtc_enable_alarm(void) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, +static int stm32_rtc_getalarmdatetime(rtc_alarmreg_t reg, struct tm *tp) { uint32_t data; @@ -800,7 +800,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -816,7 +816,7 @@ static int stm32wb_rtc_getalarmdatetime(rtc_alarmreg_t reg, * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void) +bool stm32_rtc_is_initialized(void) { uint32_t regval; @@ -851,14 +851,14 @@ int up_rtc_initialize(void) * backed, we don't need or want to re-initialize on each reset. */ - init_stat = stm32wb_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { /* Enable write access to the backup domain (RTC registers, RTC * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); #if defined(CONFIG_STM32WB_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, @@ -893,7 +893,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); rtc_dumpregs("After Failed Initialization"); @@ -960,7 +960,7 @@ int up_rtc_initialize(void) * RTC backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } } else @@ -969,7 +969,7 @@ int up_rtc_initialize(void) * backup data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); /* Write protection for RTC registers does not need to be disabled. */ @@ -979,7 +979,7 @@ int up_rtc_initialize(void) * data registers and backup SRAM). */ - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } g_rtc_enabled = true; @@ -989,7 +989,7 @@ int up_rtc_initialize(void) } /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -1009,7 +1009,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS @@ -1140,7 +1140,7 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, int up_rtc_getdatetime(struct tm *tp) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, NULL); + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); } /**************************************************************************** @@ -1174,12 +1174,12 @@ int up_rtc_getdatetime(struct tm *tp) # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { - return stm32wb_rtc_getdatetime_with_subseconds(tp, nsec); + return stm32_rtc_getdatetime_with_subseconds(tp, nsec); } #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -1194,7 +1194,7 @@ int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) * ****************************************************************************/ -int stm32wb_rtc_setdatetime(const struct tm *tp) +int stm32_rtc_setdatetime(const struct tm *tp) { uint32_t tr; uint32_t dr; @@ -1257,9 +1257,9 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) if (getreg32(RTC_MAGIC_REG) != RTC_MAGIC_TIME_SET) { - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); putreg32(RTC_MAGIC_TIME_SET, RTC_MAGIC_REG); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); } /* Re-enable the write protection for RTC registers */ @@ -1270,7 +1270,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) } /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -1280,7 +1280,7 @@ int stm32wb_rtc_setdatetime(const struct tm *tp) * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void) +bool stm32_rtc_havesettime(void) { return getreg32(RTC_MAGIC_REG) == RTC_MAGIC_TIME_SET; } @@ -1309,11 +1309,11 @@ int up_rtc_settime(const struct timespec *tp) */ gmtime_r(&tp->tv_sec, &newtime); - return stm32wb_rtc_setdatetime(&newtime); + return stm32_rtc_setdatetime(&newtime); } /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -1327,7 +1327,7 @@ int up_rtc_settime(const struct timespec *tp) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo) { struct alm_cbinfo_s *cbinfo; rtc_alarmreg_t alarmreg; @@ -1402,7 +1402,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -1416,7 +1416,7 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid) +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) { int ret = -EINVAL; @@ -1502,7 +1502,7 @@ errout_with_wprunlock: #endif /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -1516,7 +1516,7 @@ errout_with_wprunlock: ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo) { rtc_alarmreg_t alarmreg; int ret = -EINVAL; @@ -1529,7 +1529,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMA: { alarmreg = STM32_RTC_ALRMAR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1538,7 +1538,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) case RTC_ALARMB: { alarmreg = STM32_RTC_ALRMBR; - ret = stm32wb_rtc_getalarmdatetime(alarmreg, + ret = stm32_rtc_getalarmdatetime(alarmreg, (struct tm *)alminfo->ar_time); } break; @@ -1554,7 +1554,7 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) #endif /**************************************************************************** - * Name: stm32wb_rtc_wakeup_handler + * Name: stm32_rtc_wakeup_handler * * Description: * RTC WAKEUP interrupt service routine through the EXTI line @@ -1568,17 +1568,17 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_rtc_wakeup_handler(int irq, void *context, void *arg) +static int stm32_rtc_wakeup_handler(int irq, void *context, void *arg) { uint32_t regval = 0; - stm32wb_pwr_enablebkp(true); + stm32_pwr_enablebkp(true); regval = getreg32(STM32_RTC_ISR); regval &= ~RTC_ISR_WUTF; putreg32(regval, STM32_RTC_ISR); - stm32wb_pwr_enablebkp(false); + stm32_pwr_enablebkp(false); if (g_wakeupcb != NULL) { @@ -1602,7 +1602,7 @@ static inline void rtc_enable_wakeup(void) { if (!g_wakeup_enabled) { - stm32wb_exti_wakeup(true, false, true, stm32wb_rtc_wakeup_handler, + stm32_exti_wakeup(true, false, true, stm32_rtc_wakeup_handler, NULL); g_wakeup_enabled = true; } @@ -1630,7 +1630,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) #endif /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -1645,7 +1645,7 @@ static inline void rtc_set_wcksel(unsigned int wucksel) ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback) { unsigned int wutr_val; @@ -1774,7 +1774,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, #endif /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -1787,7 +1787,7 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wb_rtc_cancelperiodic(void) +int stm32_rtc_cancelperiodic(void) { int ret = OK; int timeout = 0; diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index b83811499da..65a8edf5387 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -120,7 +120,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_is_initialized + * Name: stm32_rtc_is_initialized * * Description: * Returns 'true' if the RTC has been initialized @@ -135,10 +135,10 @@ extern "C" * ****************************************************************************/ -bool stm32wb_rtc_is_initialized(void); +bool stm32_rtc_is_initialized(void); /**************************************************************************** - * Name: stm32wb_rtc_getdatetime_with_subseconds + * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface @@ -159,11 +159,11 @@ bool stm32wb_rtc_is_initialized(void); ****************************************************************************/ #ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); +int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif /**************************************************************************** - * Name: stm32wb_rtc_setdatetime + * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide @@ -180,11 +180,11 @@ int stm32wb_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #ifdef CONFIG_RTC_DATETIME struct tm; -int stm32wb_rtc_setdatetime(const struct tm *tp); +int stm32_rtc_setdatetime(const struct tm *tp); #endif /**************************************************************************** - * Name: stm32wb_rtc_havesettime + * Name: stm32_rtc_havesettime * * Description: * Check if RTC time has been set. @@ -194,11 +194,11 @@ int stm32wb_rtc_setdatetime(const struct tm *tp); * ****************************************************************************/ -bool stm32wb_rtc_havesettime(void); +bool stm32_rtc_havesettime(void); #ifdef CONFIG_RTC_ALARM /**************************************************************************** - * Name: stm32wb_rtc_setalarm + * Name: stm32_rtc_setalarm * * Description: * Set an alarm to an absolute time using associated hardware. @@ -211,10 +211,10 @@ bool stm32wb_rtc_havesettime(void); * ****************************************************************************/ -int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); +int stm32_rtc_setalarm(struct alm_setalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_rdalarm + * Name: stm32_rtc_rdalarm * * Description: * Query an alarm configured in hardware. @@ -227,10 +227,10 @@ int stm32wb_rtc_setalarm(struct alm_setalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); +int stm32_rtc_rdalarm(struct alm_rdalarm_s *alminfo); /**************************************************************************** - * Name: stm32wb_rtc_cancelalarm + * Name: stm32_rtc_cancelalarm * * Description: * Cancel an alarm. @@ -243,13 +243,13 @@ int stm32wb_rtc_rdalarm(struct alm_rdalarm_s *alminfo); * ****************************************************************************/ -int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); #endif /* CONFIG_RTC_ALARM */ #ifdef CONFIG_RTC_PERIODIC /**************************************************************************** - * Name: stm32wb_rtc_setperiodic + * Name: stm32_rtc_setperiodic * * Description: * Set a periodic RTC wakeup @@ -263,11 +263,11 @@ int stm32wb_rtc_cancelalarm(enum alm_id_e alarmid); * ****************************************************************************/ -int stm32wb_rtc_setperiodic(const struct timespec *period, +int stm32_rtc_setperiodic(const struct timespec *period, wakeupcb_t callback); /**************************************************************************** - * Name: stm32wb_rtc_cancelperiodic + * Name: stm32_rtc_cancelperiodic * * Description: * Cancel a periodic wakeup @@ -279,11 +279,11 @@ int stm32wb_rtc_setperiodic(const struct timespec *period, * ****************************************************************************/ -int stm32wb_rtc_cancelperiodic(void); +int stm32_rtc_cancelperiodic(void); #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32WB. General usage: @@ -292,7 +292,7 @@ int stm32wb_rtc_cancelperiodic(void); * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -306,7 +306,7 @@ int stm32wb_rtc_cancelperiodic(void); #ifdef CONFIG_RTC_DRIVER struct rtc_lowerhalf_s; -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void); +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c index 16fc6ea8558..fca4009e4bf 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc_lowerhalf.c @@ -52,7 +52,7 @@ ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -struct stm32wb_cbinfo_s +struct stm32_cbinfo_s { volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ volatile void *priv; /* Private argument for callback */ @@ -64,7 +64,7 @@ struct stm32wb_cbinfo_s * with struct rtc_lowerhalf_s. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { /* This is the contained reference to the read-only, lower-half * operations vtable (which may lie in FLASH or ROM) @@ -81,7 +81,7 @@ struct stm32wb_lowerhalf_s #ifdef CONFIG_RTC_ALARM /* Alarm callback information */ - struct stm32wb_cbinfo_s cbinfo[STM32_NALARMS]; + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; #endif #ifdef CONFIG_RTC_PERIODIC @@ -97,29 +97,29 @@ struct stm32wb_lowerhalf_s /* Prototypes for static methods in struct rtc_ops_s */ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime); -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime); -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower); +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower); #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo); static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo); -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo); #endif #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo); static int -stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); +stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); #endif /**************************************************************************** @@ -130,24 +130,24 @@ stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id); static const struct rtc_ops_s g_rtc_ops = { - .rdtime = stm32wb_rdtime, - .settime = stm32wb_settime, - .havesettime = stm32wb_havesettime, + .rdtime = stm32_rdtime, + .settime = stm32_settime, + .havesettime = stm32_havesettime, #ifdef CONFIG_RTC_ALARM - .setalarm = stm32wb_setalarm, - .setrelative = stm32wb_setrelative, - .cancelalarm = stm32wb_cancelalarm, - .rdalarm = stm32wb_rdalarm, + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, + .rdalarm = stm32_rdalarm, #endif #ifdef CONFIG_RTC_PERIODIC - .setperiodic = stm32wb_setperiodic, - .cancelperiodic = stm32wb_cancelperiodic, + .setperiodic = stm32_setperiodic, + .cancelperiodic = stm32_cancelperiodic, #endif }; /* STM32WB RTC device state */ -static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = +static struct stm32_lowerhalf_s g_rtc_lowerhalf = { .ops = &g_rtc_ops, .devlock = NXMUTEX_INITIALIZER, @@ -158,7 +158,7 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_alarm_callback + * Name: stm32_alarm_callback * * Description: * This is the function that is called from the RTC driver when the alarm @@ -173,17 +173,17 @@ static struct stm32wb_lowerhalf_s g_rtc_lowerhalf = ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) +static void stm32_alarm_callback(void *arg, unsigned int alarmid) { - struct stm32wb_lowerhalf_s *lower; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *lower; + struct stm32_cbinfo_s *cbinfo; rtc_alarm_callback_t cb; void *priv; DEBUGASSERT(arg != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - lower = (struct stm32wb_lowerhalf_s *)arg; + lower = (struct stm32_lowerhalf_s *)arg; cbinfo = &lower->cbinfo[alarmid]; /* Sample and clear the callback information to minimize the window in @@ -206,7 +206,7 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) #endif /* CONFIG_RTC_ALARM */ /**************************************************************************** - * Name: stm32wb_rdtime + * Name: stm32_rdtime * * Description: * Implements the rdtime() method of the RTC driver interface @@ -221,13 +221,13 @@ static void stm32wb_alarm_callback(void *arg, unsigned int alarmid) * ****************************************************************************/ -static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, +static int stm32_rdtime(struct rtc_lowerhalf_s *lower, struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -246,7 +246,7 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settime + * Name: stm32_settime * * Description: * Implements the settime() method of the RTC driver interface @@ -261,13 +261,13 @@ static int stm32wb_rdtime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settime(struct rtc_lowerhalf_s *lower, +static int stm32_settime(struct rtc_lowerhalf_s *lower, const struct rtc_time *rtctime) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -279,14 +279,14 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * compatible with struct tm. */ - ret = stm32wb_rtc_setdatetime((const struct tm *)rtctime); + ret = stm32_rtc_setdatetime((const struct tm *)rtctime); nxmutex_unlock(&priv->devlock); return ret; } /**************************************************************************** - * Name: stm32wb_havesettime + * Name: stm32_havesettime * * Description: * Implements the havesettime() method of the RTC driver interface @@ -299,13 +299,13 @@ static int stm32wb_settime(struct rtc_lowerhalf_s *lower, * ****************************************************************************/ -static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) +static bool stm32_havesettime(struct rtc_lowerhalf_s *lower) { - return stm32wb_rtc_havesettime(); + return stm32_rtc_havesettime(); } /**************************************************************************** - * Name: stm32wb_setalarm + * Name: stm32_setalarm * * Description: * Set a new alarm. This function implements the setalarm() method of the @@ -322,11 +322,11 @@ static bool stm32wb_havesettime(struct rtc_lowerhalf_s *lower) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, +static int stm32_setalarm(struct rtc_lowerhalf_s *lower, const struct lower_setalarm_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; struct alm_setalarm_s lowerinfo; int ret; @@ -334,7 +334,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, DEBUGASSERT(lower != NULL && alarminfo != NULL); DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -355,13 +355,13 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, /* Set the alarm */ lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = stm32wb_alarm_callback; + lowerinfo.as_cb = stm32_alarm_callback; lowerinfo.as_arg = priv; memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); /* And set the alarm */ - ret = stm32wb_rtc_setalarm(&lowerinfo); + ret = stm32_rtc_setalarm(&lowerinfo); if (ret < 0) { cbinfo->cb = NULL; @@ -375,7 +375,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_setrelative + * Name: stm32_setrelative * * Description: * Set a new alarm relative to the current time. This function implements @@ -393,7 +393,7 @@ static int stm32wb_setalarm(struct rtc_lowerhalf_s *lower, #ifdef CONFIG_RTC_ALARM static int -stm32wb_setrelative(struct rtc_lowerhalf_s *lower, +stm32_setrelative(struct rtc_lowerhalf_s *lower, const struct lower_setrelative_s *alarminfo) { struct lower_setalarm_s setalarm; @@ -439,7 +439,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, setalarm.cb = alarminfo->cb; setalarm.priv = alarminfo->priv; - ret = stm32wb_setalarm(lower, &setalarm); + ret = stm32_setalarm(lower, &setalarm); } leave_critical_section(flags); @@ -450,7 +450,7 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelalarm + * Name: stm32_cancelalarm * * Description: * Cancel the current alarm. This function implements the cancelalarm() @@ -467,15 +467,15 @@ stm32wb_setrelative(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +static int stm32_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) { - struct stm32wb_lowerhalf_s *priv; - struct stm32wb_cbinfo_s *cbinfo; + struct stm32_lowerhalf_s *priv; + struct stm32_cbinfo_s *cbinfo; int ret; DEBUGASSERT(lower != NULL); DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -496,7 +496,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) /* Then cancel the alarm */ - ret = stm32wb_rtc_cancelalarm((enum alm_id_e)alarmid); + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); } nxmutex_unlock(&priv->devlock); @@ -505,7 +505,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) #endif /**************************************************************************** - * Name: stm32wb_rdalarm + * Name: stm32_rdalarm * * Description: * Query the RTC alarm. @@ -521,7 +521,7 @@ static int stm32wb_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, +static int stm32_rdalarm(struct rtc_lowerhalf_s *lower, struct lower_rdalarm_s *alarminfo) { struct alm_rdalarm_s lowerinfo; @@ -542,7 +542,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, lowerinfo.ar_id = alarminfo->id; lowerinfo.ar_time = alarminfo->time; - ret = stm32wb_rtc_rdalarm(&lowerinfo); + ret = stm32_rtc_rdalarm(&lowerinfo); leave_critical_section(flags); } @@ -552,7 +552,7 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_periodic_callback + * Name: stm32_periodic_callback * * Description: * This is the function that is called from the RTC driver when the @@ -568,14 +568,14 @@ static int stm32wb_rdalarm(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_periodic_callback(void) +static int stm32_periodic_callback(void) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; struct lower_setperiodic_s *cbinfo; rtc_wakeup_callback_t cb; void *priv; - lower = (struct stm32wb_lowerhalf_s *)&g_rtc_lowerhalf; + lower = (struct stm32_lowerhalf_s *)&g_rtc_lowerhalf; cbinfo = &lower->periodic; cb = (rtc_wakeup_callback_t)cbinfo->cb; @@ -593,7 +593,7 @@ static int stm32wb_periodic_callback(void) #endif /* CONFIG_RTC_PERIODIC */ /**************************************************************************** - * Name: stm32wb_setperiodic + * Name: stm32_setperiodic * * Description: * Set a new periodic wakeup relative to the current time, with a given @@ -612,14 +612,14 @@ static int stm32wb_periodic_callback(void) #ifdef CONFIG_RTC_PERIODIC static int -stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, +stm32_setperiodic(struct rtc_lowerhalf_s *lower, const struct lower_setperiodic_s *alarminfo) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL && alarminfo != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; ret = nxmutex_lock(&priv->devlock); if (ret < 0) @@ -628,8 +628,8 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, } memcpy(&priv->periodic, alarminfo, sizeof(struct lower_setperiodic_s)); - ret = stm32wb_rtc_setperiodic(&alarminfo->period, - stm32wb_periodic_callback); + ret = stm32_rtc_setperiodic(&alarminfo->period, + stm32_periodic_callback); nxmutex_unlock(&priv->devlock); return ret; @@ -637,7 +637,7 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, #endif /**************************************************************************** - * Name: stm32wb_cancelperiodic + * Name: stm32_cancelperiodic * * Description: * Cancel the current periodic wakeup activity. This function implements @@ -653,13 +653,13 @@ stm32wb_setperiodic(struct rtc_lowerhalf_s *lower, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) +static int stm32_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) { - struct stm32wb_lowerhalf_s *priv; + struct stm32_lowerhalf_s *priv; int ret; DEBUGASSERT(lower != NULL); - priv = (struct stm32wb_lowerhalf_s *)lower; + priv = (struct stm32_lowerhalf_s *)lower; DEBUGASSERT(id == 0); @@ -669,7 +669,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) return ret; } - ret = stm32wb_rtc_cancelperiodic(); + ret = stm32_rtc_cancelperiodic(); nxmutex_unlock(&priv->devlock); return ret; @@ -681,7 +681,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_rtc_lowerhalf + * Name: stm32_rtc_lowerhalf * * Description: * Instantiate the RTC lower half driver for the STM32. General usage: @@ -690,7 +690,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * #include "stm32wb_rtc.h> * * struct rtc_lowerhalf_s *lower; - * lower = stm32wb_rtc_lowerhalf(); + * lower = stm32_rtc_lowerhalf(); * rtc_initialize(0, lower); * * Input Parameters: @@ -702,7 +702,7 @@ static int stm32wb_cancelperiodic(struct rtc_lowerhalf_s *lower, int id) * ****************************************************************************/ -struct rtc_lowerhalf_s *stm32wb_rtc_lowerhalf(void) +struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) { return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; } diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 5289b289fa7..78bd2aaef33 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -138,7 +138,7 @@ * register. It must not collide with USART_CR1_USED_INTS or USART_CR3_EIE * 2) USART_CR3_EIE is also carried in the up_dev_s ie member. * - * See stm32wb_serial_restoreusartint where the masking is done. + * See stm32_serial_restoreusartint where the masking is done. */ #ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT @@ -153,7 +153,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -239,51 +239,51 @@ struct stm32wb_serial_s ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev); +static void stm32_serial_setformat(struct uart_dev_s *dev); #endif -static int stm32wb_serial_setup(struct uart_dev_s *dev); -static void stm32wb_serial_shutdown(struct uart_dev_s *dev); -static int stm32wb_serial_attach(struct uart_dev_s *dev); -static void stm32wb_serial_detach(struct uart_dev_s *dev); +static int stm32_serial_setup(struct uart_dev_s *dev); +static void stm32_serial_shutdown(struct uart_dev_s *dev); +static int stm32_serial_attach(struct uart_dev_s *dev); +static void stm32_serial_detach(struct uart_dev_s *dev); static int up_interrupt(int irq, void *context, void *arg); -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg); #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev); +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_rxavailable(struct uart_dev_s *dev); #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch); -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_txready(struct uart_dev_s *dev); +static void stm32_serial_send(struct uart_dev_s *dev, int ch); +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_txready(struct uart_dev_s *dev); #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev); -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev); -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmasetup(struct uart_dev_s *dev); +static void stm32_serial_dmashutdown(struct uart_dev_s *dev); +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv); +static void stm32_serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv); +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable); -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev); +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable); +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev); -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend); -static void stm32wb_serial_pm_setsuspend(bool suspend); -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend); +static void stm32_serial_pm_setsuspend(bool suspend); +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); #endif @@ -294,42 +294,42 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, #ifndef SERIAL_HAVE_ONLY_DMA static const struct uart_ops_s g_uart_ops = { - .setup = stm32wb_serial_setup, - .shutdown = stm32wb_serial_shutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_receive, - .rxint = stm32wb_serial_rxint, - .rxavailable = stm32wb_serial_rxavailable, + .setup = stm32_serial_setup, + .shutdown = stm32_serial_shutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_receive, + .rxint = stm32_serial_rxint, + .rxavailable = stm32_serial_rxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif #ifdef SERIAL_HAVE_RXDMA static const struct uart_ops_s g_uart_dma_ops = { - .setup = stm32wb_serial_dmasetup, - .shutdown = stm32wb_serial_dmashutdown, - .attach = stm32wb_serial_attach, - .detach = stm32wb_serial_detach, - .ioctl = stm32wb_serial_ioctl, - .receive = stm32wb_serial_dmareceive, - .rxint = stm32wb_serial_dmarxint, - .rxavailable = stm32wb_serial_dmarxavailable, + .setup = stm32_serial_dmasetup, + .shutdown = stm32_serial_dmashutdown, + .attach = stm32_serial_attach, + .detach = stm32_serial_detach, + .ioctl = stm32_serial_ioctl, + .receive = stm32_serial_dmareceive, + .rxint = stm32_serial_dmarxint, + .rxavailable = stm32_serial_dmarxavailable, #ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = stm32wb_serial_rxflowcontrol, + .rxflowcontrol = stm32_serial_rxflowcontrol, #endif - .send = stm32wb_serial_send, - .txint = stm32wb_serial_txint, - .txready = stm32wb_serial_txready, - .txempty = stm32wb_serial_txready, + .send = stm32_serial_send, + .txint = stm32_serial_txint, + .txready = stm32_serial_txready, + .txempty = stm32_serial_txready, }; #endif @@ -354,7 +354,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static struct stm32wb_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -416,7 +416,7 @@ static struct stm32wb_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ #ifdef CONFIG_STM32WB_USART1_SERIALDRIVER -static struct stm32wb_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -477,7 +477,7 @@ static struct stm32wb_serial_s g_usart1priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wb_serial_s * +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER @@ -495,8 +495,8 @@ static struct bool serial_suspended; } g_serialpm = { - .pm_cb.notify = stm32wb_serial_pmnotify, - .pm_cb.prepare = stm32wb_serial_pmprepare, + .pm_cb.notify = stm32_serial_pmnotify, + .pm_cb.prepare = stm32_serial_pmprepare, .serial_suspended = false }; #endif @@ -506,31 +506,31 @@ static struct ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_getreg + * Name: stm32_serial_getreg ****************************************************************************/ static inline -uint32_t stm32wb_serial_getreg(struct stm32wb_serial_s *priv, int offset) +uint32_t stm32_serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_putreg + * Name: stm32_serial_putreg ****************************************************************************/ -static inline void stm32wb_serial_putreg(struct stm32wb_serial_s *priv, +static inline void stm32_serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); } /**************************************************************************** - * Name: stm32wb_serial_setusartint + * Name: stm32_serial_setusartint ****************************************************************************/ static inline -void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) +void stm32_serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -542,38 +542,38 @@ void stm32wb_serial_setusartint(struct stm32wb_serial_s *priv, uint16_t ie) * enable/usage table above) */ - cr = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr &= ~(USART_CR1_USED_INTS); cr |= (ie & (USART_CR1_USED_INTS)); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr); - cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); cr &= ~USART_CR3_EIE; cr |= (ie & USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); } /**************************************************************************** * Name: up_restoreusartint ****************************************************************************/ -static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; flags = spin_lock_irqsave(&priv->lock); - stm32wb_serial_setusartint(priv, ie); + stm32_serial_setusartint(priv, ie); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_disableusartint + * Name: stm32_serial_disableusartint ****************************************************************************/ -static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, +static void stm32_serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -610,8 +610,8 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, * USART_CR3_CTSIE USART_ISR_CTS CTS flag (not used) */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - cr3 = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr3 = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); /* Return the current interrupt mask value for the used interrupts. * Notice that this depends on the fact that none of the used interrupt @@ -624,13 +624,13 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, /* Disable all interrupts */ - stm32wb_serial_setusartint(priv, 0); + stm32_serial_setusartint(priv, 0); spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** - * Name: stm32wb_serial_dmanextrx + * Name: stm32_serial_dmanextrx * * Description: * Returns the index into the RX FIFO where the DMA will place the next @@ -639,18 +639,18 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) +static int stm32_serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wb_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_usart + * Name: stm32_serial_setbaud_usart * * Description: * Set the serial line baud rate (USART only). @@ -658,7 +658,7 @@ static int stm32wb_serial_dmanextrx(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) { /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. @@ -686,8 +686,8 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) /* Use oversamply by 8 only if the divisor is small. But what is small? */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - brr = stm32wb_serial_getreg(priv, STM32_USART_BRR_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + brr = stm32_serial_getreg(priv, STM32_USART_BRR_OFFSET); brr &= ~(USART_BRR_MANT_MASK | USART_BRR_FRAC_MASK); if (usartdiv8 > 100) @@ -713,13 +713,13 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) cr1 |= USART_CR1_OVER8; } - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif /**************************************************************************** - * Name: stm32wb_serial_setbaud_lpuart + * Name: stm32_serial_setbaud_lpuart * * Description: * Set the serial line baud rate (LPUART only). @@ -728,7 +728,7 @@ static void stm32wb_serial_setbaud_usart(struct stm32wb_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER -static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) +static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -750,13 +750,13 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) brr = LPUART_BRR_MIN; } - stm32wb_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); + stm32_serial_putreg(priv, STM32_USART_BRR_OFFSET, brr); } #endif #endif /**************************************************************************** - * Name: stm32wb_serial_setformat + * Name: stm32_serial_setformat * * Description: * Set the serial line format and speed. @@ -764,9 +764,9 @@ static void stm32wb_serial_setbaud_lpuart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -static void stm32wb_serial_setformat(struct uart_dev_s *dev) +static void stm32_serial_setformat(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Set baud rate */ @@ -774,17 +774,17 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { - stm32wb_serial_setbaud_lpuart(priv); + stm32_serial_setbaud_lpuart(priv); } else #endif { - stm32wb_serial_setbaud_usart(priv); + stm32_serial_setbaud_usart(priv); } /* Configure parity mode */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_PCE | USART_CR1_PS | USART_CR1_M0 | USART_CR1_M1); if (priv->parity == 1) /* Odd parity */ @@ -822,11 +822,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) * 1 start, 8 data (no parity), n stop. */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure STOP bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK); if (priv->stopbits2) @@ -834,11 +834,11 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure hardware flow control */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -855,12 +855,12 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) } #endif - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); } #endif /* CONFIG_SUPPRESS_UART_CONFIG */ /**************************************************************************** - * Name: stm32wb_serial_setsuspend + * Name: stm32_serial_setsuspend * * Description: * Suspend or resume serial peripheral. @@ -868,9 +868,9 @@ static void stm32wb_serial_setformat(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) +static void stm32_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_RXDMA bool dmarestored = false; #endif @@ -889,18 +889,18 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wb_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif /* Disable interrupts to prevent Tx. */ - stm32wb_serial_disableusartint(priv, &priv->suspended_ie); + stm32_serial_disableusartint(priv, &priv->suspended_ie); /* Wait last Tx to complete. */ - while ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + while ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); #ifdef SERIAL_HAVE_RXDMA @@ -918,7 +918,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -932,7 +932,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } else #endif @@ -942,7 +942,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) * to DMA buffer before suspending). */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); priv->rxdmasusp = false; } @@ -952,14 +952,14 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) /* Re-enable interrupts to resume Tx. */ - stm32wb_serial_restoreusartint(priv, priv->suspended_ie); + stm32_serial_restoreusartint(priv, priv->suspended_ie); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Restore peripheral RTS control. */ - stm32wb_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -977,7 +977,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) if (priv->rxdma != NULL) { - stm32wb_serial_dmarxcallback(priv->rxdma, 0, priv); + stm32_serial_dmarxcallback(priv->rxdma, 0, priv); } leave_critical_section(flags); @@ -987,7 +987,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) #endif /**************************************************************************** - * Name: stm32wb_serial_pm_setsuspend + * Name: stm32_serial_pm_setsuspend * * Description: * Suspend or resume serial peripherals for/from deep-sleep/stop modes. @@ -995,7 +995,7 @@ static void stm32wb_serial_setsuspend(struct uart_dev_s *dev, bool suspend) ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pm_setsuspend(bool suspend) +static void stm32_serial_pm_setsuspend(bool suspend) { int n; @@ -1010,18 +1010,18 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (priv != NULL && priv->initialized != NULL) { - stm32wb_serial_setsuspend(&priv->dev, suspend); + stm32_serial_setsuspend(&priv->dev, suspend); } } } #endif /**************************************************************************** - * Name: stm32wb_serial_setapbclock + * Name: stm32_serial_setapbclock * * Description: * Enable or disable APB clock for the USART peripheral @@ -1032,9 +1032,9 @@ static void stm32wb_serial_pm_setsuspend(bool suspend) * ****************************************************************************/ -static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) +static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1071,7 +1071,7 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) } /**************************************************************************** - * Name: stm32wb_serial_setup + * Name: stm32_serial_setup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1079,37 +1079,37 @@ static void stm32wb_serial_setapbclock(struct uart_dev_s *dev, bool on) * ****************************************************************************/ -static int stm32wb_serial_setup(struct uart_dev_s *dev) +static int stm32_serial_setup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wb_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, true); + stm32_serial_setapbclock(dev, true); /* Configure pins for USART use */ if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1123,15 +1123,15 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wb_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_configgpio(priv->rs485_dir_gpio); - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1139,7 +1139,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) /* Clear STOP, CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); regval &= ~(USART_CR2_STOP_MASK | USART_CR2_CLKEN | USART_CR2_CPOL | USART_CR2_CPHA | USART_CR2_LBCL | USART_CR2_LBDIE); @@ -1150,36 +1150,36 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) regval |= USART_CR2_STOP2; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, regval); /* Configure CR1 */ /* Clear TE, REm and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_TE | USART_CR1_RE | USART_CR1_ALLINTS); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Configure CR3 */ /* Clear CTSE, RTSE, and all interrupt enable bits */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSIE | USART_CR3_CTSE | USART_CR3_RTSE | USART_CR3_EIE); - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); /* Configure the USART line format and speed. */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); /* Enable Rx, Tx, and the USART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval |= (USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); #endif /* CONFIG_SUPPRESS_UART_CONFIG */ @@ -1195,7 +1195,7 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_dmasetup + * Name: stm32_serial_dmasetup * * Description: * Configure the USART baud, bits, parity, etc. This method is called the @@ -1204,9 +1204,9 @@ static int stm32wb_serial_setup(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) +static int stm32_serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1214,7 +1214,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) if (!dev->isconsole) { - result = stm32wb_serial_setup(dev); + result = stm32_serial_setup(dev); if (result != OK) { return result; @@ -1223,14 +1223,14 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wb_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1241,7 +1241,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1256,9 +1256,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) /* Enable receive DMA for the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval |= USART_CR3_DMAR; - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, regval); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) @@ -1268,7 +1268,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -1279,7 +1279,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -1288,7 +1288,7 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) #endif /**************************************************************************** - * Name: stm32wb_serial_shutdown + * Name: stm32_serial_shutdown * * Description: * Disable the USART. This method is called when the serial @@ -1296,9 +1296,9 @@ static int stm32wb_serial_dmasetup(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_shutdown(struct uart_dev_s *dev) +static void stm32_serial_shutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1307,17 +1307,17 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) /* Disable all interrupts */ - stm32wb_serial_disableusartint(priv, NULL); + stm32_serial_disableusartint(priv, NULL); /* Disable USART APB1/2 clock */ - stm32wb_serial_setapbclock(dev, false); + stm32_serial_setapbclock(dev, false); /* Disable Rx, Tx, and the UART */ - regval = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + regval = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); regval &= ~(USART_CR1_UE | USART_CR1_TE | USART_CR1_RE); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, regval); /* Release pins. "If the serial-attached device is powered down, the TX * pin causes back-powering, potentially confusing the device to the point @@ -1329,38 +1329,38 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wb_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wb_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wb_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wb_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } /**************************************************************************** - * Name: stm32wb_serial_dmashutdown + * Name: stm32_serial_dmashutdown * * Description: * Disable the USART. This method is called when the serial @@ -1369,27 +1369,27 @@ static void stm32wb_serial_shutdown(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) +static void stm32_serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ - stm32wb_serial_shutdown(dev); + stm32_serial_shutdown(dev); /* Stop the DMA channel */ - stm32wb_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wb_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif /**************************************************************************** - * Name: stm32wb_serial_attach + * Name: stm32_serial_attach * * Description: * Configure the USART to operation in interrupt driven mode. This method @@ -1404,9 +1404,9 @@ static void stm32wb_serial_dmashutdown(struct uart_dev_s *dev) * ****************************************************************************/ -static int stm32wb_serial_attach(struct uart_dev_s *dev) +static int stm32_serial_attach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1425,7 +1425,7 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_serial_detach + * Name: stm32_serial_detach * * Description: * Detach USART interrupts. This method is called when the serial port is @@ -1434,9 +1434,9 @@ static int stm32wb_serial_attach(struct uart_dev_s *dev) * ****************************************************************************/ -static void stm32wb_serial_detach(struct uart_dev_s *dev) +static void stm32_serial_detach(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1455,7 +1455,7 @@ static void stm32wb_serial_detach(struct uart_dev_s *dev) static int up_interrupt(int irq, void *context, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1478,7 +1478,7 @@ static int up_interrupt(int irq, void *context, void *arg) /* Get the masked USART status word. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); /* USART interrupts: * @@ -1520,8 +1520,8 @@ static int up_interrupt(int irq, void *context, void *arg) (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } #endif @@ -1550,7 +1550,7 @@ static int up_interrupt(int irq, void *context, void *arg) * interrupt clear register (ICR). */ - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -1571,14 +1571,14 @@ static int up_interrupt(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wb_serial_ioctl + * Name: stm32_serial_ioctl * * Description: * All ioctl calls will be routed through this method * ****************************************************************************/ -static int stm32wb_serial_ioctl(struct file *filep, int cmd, +static int stm32_serial_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) @@ -1586,7 +1586,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1595,14 +1595,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wb_serial_s *user = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *user = (struct stm32_serial_s *)arg; if (!user) { ret = -EINVAL; } else { - memcpy(user, dev, sizeof(struct stm32wb_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1619,19 +1619,19 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, HDSEL can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Change the TX port to be open-drain/push-pull and enable/disable * half-duplex mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR3_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { @@ -1648,7 +1648,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1659,7 +1659,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wb_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1667,11 +1667,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR3_HDSEL; } - stm32wb_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR3_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1688,17 +1688,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, {R,T}XINV can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable signal inversion. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg & SER_INVERT_ENABLED_RX) { @@ -1718,11 +1718,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_TXINV; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1739,17 +1739,17 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, /* Get the original state of UE */ - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); cr1_ue = cr1 & USART_CR1_UE; cr1 &= ~USART_CR1_UE; /* Disable UE, SWAP can only be written when UE=0 */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1); /* Enable/disable Swap mode. */ - uint32_t cr = stm32wb_serial_getreg(priv, STM32_USART_CR2_OFFSET); + uint32_t cr = stm32_serial_getreg(priv, STM32_USART_CR2_OFFSET); if (arg == SER_SWAP_ENABLED) { @@ -1760,11 +1760,11 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, cr &= ~USART_CR2_SWAP; } - stm32wb_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); + stm32_serial_putreg(priv, STM32_USART_CR2_OFFSET, cr); /* Re-enable UE if appropriate */ - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | cr1_ue); leave_critical_section(flags); } break; @@ -1860,7 +1860,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, * TCSADRAIN / TCSAFLUSH */ - stm32wb_serial_setformat(dev); + stm32_serial_setformat(dev); } break; #endif /* CONFIG_SERIAL_TERMIOS */ @@ -1877,7 +1877,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, priv->ie |= USART_CR1_IE_BREAK_INPROGRESS; - stm32wb_serial_txint(dev, false); + stm32_serial_txint(dev, false); /* Configure TX as a GPIO output pin and Send a break signal */ @@ -1885,7 +1885,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wb_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1902,14 +1902,14 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wb_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; /* Enable further tx activity */ - stm32wb_serial_txint(dev, true); + stm32_serial_txint(dev, true); leave_critical_section(flags); } @@ -1921,8 +1921,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 | USART_CR1_SBK); leave_critical_section(flags); } @@ -1934,8 +1934,8 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, irqstate_t flags; flags = enter_critical_section(); - cr1 = stm32wb_serial_getreg(priv, STM32_USART_CR1_OFFSET); - stm32wb_serial_putreg(priv, STM32_USART_CR1_OFFSET, + cr1 = stm32_serial_getreg(priv, STM32_USART_CR1_OFFSET); + stm32_serial_putreg(priv, STM32_USART_CR1_OFFSET, cr1 & ~USART_CR1_SBK); leave_critical_section(flags); } @@ -1952,7 +1952,7 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, } /**************************************************************************** - * Name: stm32wb_serial_receive + * Name: stm32_serial_receive * * Description: * Called (usually) from the interrupt level to receive one @@ -1962,15 +1962,15 @@ static int stm32wb_serial_ioctl(struct file *filep, int cmd, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static int stm32wb_serial_receive(struct uart_dev_s *dev, +static int stm32_serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ - rdr = stm32wb_serial_getreg(priv, STM32_USART_RDR_OFFSET); + rdr = stm32_serial_getreg(priv, STM32_USART_RDR_OFFSET); /* Get the Rx byte plux error information. Return those in status */ @@ -1984,7 +1984,7 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_rxint + * Name: stm32_serial_rxint * * Description: * Call to enable or disable RX interrupts @@ -1992,9 +1992,9 @@ static int stm32wb_serial_receive(struct uart_dev_s *dev, ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2040,13 +2040,13 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) /* Then set the new interrupt state */ - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); leave_critical_section(flags); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxavailable + * Name: stm32_serial_rxavailable * * Description: * Return true if the receive register is not empty @@ -2054,17 +2054,17 @@ static void stm32wb_serial_rxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifndef SERIAL_HAVE_ONLY_DMA -static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) +static bool stm32_serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); } #endif /**************************************************************************** - * Name: stm32wb_serial_rxflowcontrol + * Name: stm32_serial_rxflowcontrol * * Description: * Called when Rx buffer is full (or exceeds configured watermark levels @@ -2087,10 +2087,10 @@ static bool stm32wb_serial_rxavailable(struct uart_dev_s *dev) ****************************************************************************/ #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, +static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) @@ -2098,7 +2098,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wb_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2160,7 +2160,7 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareceive + * Name: stm32_serial_dmareceive * * Description: * Called (usually) from the interrupt level to receive one @@ -2170,13 +2170,13 @@ static bool stm32wb_serial_rxflowcontrol(struct uart_dev_s *dev, ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, +static int stm32_serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; int c = 0; - if (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext) + if (stm32_serial_dmanextrx(priv) != priv->rxdmanext) { c = priv->rxfifo[priv->rxdmanext]; @@ -2203,7 +2203,7 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, #endif /**************************************************************************** - * Name: stm32wb_serial_dmareenable + * Name: stm32_serial_dmareenable * * Description: * Call to re-enable RX DMA. @@ -2211,14 +2211,14 @@ static int stm32wb_serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) -static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) +static void stm32_serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2229,7 +2229,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wb_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2250,7 +2250,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, false); } else @@ -2261,7 +2261,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wb_dmastart(priv->rxdma, stm32wb_serial_dmarxcallback, priv, + stm32_dmastart(priv->rxdma, stm32_serial_dmarxcallback, priv, true); } @@ -2274,7 +2274,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) #endif /**************************************************************************** - * Name: stm32wb_serial_dmaiflowrestart + * Name: stm32_serial_dmaiflowrestart * * Description: * Call to restart RX DMA for input flow-controlled USART @@ -2282,7 +2282,7 @@ static void stm32wb_serial_dmareenable(struct stm32wb_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) +static bool stm32_serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2298,7 +2298,7 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) { /* Rx DMA in suspended state. */ - if (stm32wb_serial_dmarxavailable(&priv->dev)) + if (stm32_serial_dmarxavailable(&priv->dev)) { /* DMA buffer has unprocessed data, do not re-enable yet. */ @@ -2316,14 +2316,14 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) * re-enabling without data loss is now safe. */ - stm32wb_serial_dmareenable(priv); + stm32_serial_dmareenable(priv); return true; } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxint + * Name: stm32_serial_dmarxint * * Description: * Call to enable or disable RX interrupts @@ -2331,9 +2331,9 @@ static bool stm32wb_serial_dmaiflowrestart(struct stm32wb_serial_s *priv) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2350,14 +2350,14 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } #endif /**************************************************************************** - * Name: stm32wb_serial_dmarxavailable + * Name: stm32_serial_dmarxavailable * * Description: * Return true if the receive register is not empty @@ -2365,51 +2365,51 @@ static void stm32wb_serial_dmarxint(struct uart_dev_s *dev, bool enable) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static bool stm32wb_serial_dmarxavailable(struct uart_dev_s *dev) +static bool stm32_serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. */ - return (stm32wb_serial_dmanextrx(priv) != priv->rxdmanext); + return (stm32_serial_dmanextrx(priv) != priv->rxdmanext); } #endif /**************************************************************************** - * Name: stm32wb_serial_send + * Name: stm32_serial_send * * Description: * This method will send one byte on the USART * ****************************************************************************/ -static void stm32wb_serial_send(struct uart_dev_s *dev, int ch) +static void stm32_serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wb_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif - stm32wb_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); + stm32_serial_putreg(priv, STM32_USART_TDR_OFFSET, (uint32_t)ch); } /**************************************************************************** - * Name: stm32wb_serial_txint + * Name: stm32_serial_txint * * Description: * Call to enable or disable TX interrupts * ****************************************************************************/ -static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) +static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; irqstate_t flags; @@ -2452,7 +2452,7 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) } # endif - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); /* Fake a TX interrupt here by just calling uart_xmitchars() with * interrupts disabled (note this may recurse). @@ -2465,29 +2465,29 @@ static void stm32wb_serial_txint(struct uart_dev_s *dev, bool enable) { /* Disable the TX interrupt */ - stm32wb_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); + stm32_serial_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE); } leave_critical_section(flags); } /**************************************************************************** - * Name: stm32wb_serial_txready + * Name: stm32_serial_txready * * Description: * Return true if the transmit data register is empty * ****************************************************************************/ -static bool stm32wb_serial_txready(struct uart_dev_s *dev) +static bool stm32_serial_txready(struct uart_dev_s *dev) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)dev->priv; - return ((stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET) & + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; + return ((stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); } /**************************************************************************** - * Name: stm32wb_serial_dmarxcallback + * Name: stm32_serial_dmarxcallback * * Description: * This function checks the current DMA state and calls the generic @@ -2496,12 +2496,12 @@ static bool stm32wb_serial_txready(struct uart_dev_s *dev) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, +static void stm32_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wb_serial_s *priv = (struct stm32wb_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; - if (priv->rxenable && stm32wb_serial_dmarxavailable(&priv->dev)) + if (priv->rxenable && stm32_serial_dmarxavailable(&priv->dev)) { uart_recvchars(&priv->dev); @@ -2510,7 +2510,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, { /* Re-enable RX DMA. */ - stm32wb_serial_dmaiflowrestart(priv); + stm32_serial_dmaiflowrestart(priv); } #endif } @@ -2525,11 +2525,11 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, * will release Rx DMA. */ - priv->sr = stm32wb_serial_getreg(priv, STM32_USART_ISR_OFFSET); + priv->sr = stm32_serial_getreg(priv, STM32_USART_ISR_OFFSET); if ((priv->sr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE)) != 0) { - stm32wb_serial_putreg(priv, STM32_USART_ICR_OFFSET, + stm32_serial_putreg(priv, STM32_USART_ICR_OFFSET, (USART_ICR_NCF | USART_ICR_ORECF | USART_ICR_FECF)); } @@ -2537,7 +2537,7 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, #endif /**************************************************************************** - * Name: stm32wb_serial_pmnotify + * Name: stm32_serial_pmnotify * * Description: * Notify the driver of new power state. This callback is called after @@ -2559,17 +2559,17 @@ static void stm32wb_serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, ****************************************************************************/ #ifdef CONFIG_PM -static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, +static void stm32_serial_pmnotify(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { switch (pmstate) { case PM_NORMAL: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_IDLE: - stm32wb_serial_pm_setsuspend(false); + stm32_serial_pm_setsuspend(false); break; case PM_STANDBY: @@ -2579,11 +2579,11 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, * Rx/Tx buffers are empty (checked in pmprepare). */ - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; case PM_SLEEP: - stm32wb_serial_pm_setsuspend(true); + stm32_serial_pm_setsuspend(true); break; default: @@ -2594,7 +2594,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, #endif /**************************************************************************** - * Name: stm32wb_serial_pmprepare + * Name: stm32_serial_pmprepare * * Description: * Request the driver to prepare for a new power state. This is a warning @@ -2627,7 +2627,7 @@ static void stm32wb_serial_pmnotify(struct pm_callback_s *cb, int domain, ****************************************************************************/ #ifdef CONFIG_PM -static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, +static int stm32_serial_pmprepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { int n; @@ -2648,7 +2648,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wb_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2657,7 +2657,7 @@ static int stm32wb_serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wb_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2727,14 +2727,14 @@ void arm_earlyserialinit(void) { if (g_uart_devs[i]) { - stm32wb_serial_disableusartint(g_uart_devs[i], NULL); + stm32_serial_disableusartint(g_uart_devs[i], NULL); } } /* Configure whichever one is the console */ #if CONSOLE_UART > 0 - stm32wb_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_setup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* HAVE UART */ } @@ -2779,7 +2779,7 @@ void arm_serialinit(void) #ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ - stm32wb_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); + stm32_serial_dmasetup(&g_uart_devs[CONSOLE_UART - 1]->dev); #endif #endif /* CONSOLE_UART > 0 */ @@ -2814,7 +2814,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2825,7 +2825,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2834,14 +2834,14 @@ void stm32wb_serial_dma_poll(void) #ifdef CONFIG_LPUART1_RXDMA if (g_lpuart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); + stm32_serial_dmarxcallback(g_lpuart1priv.rxdma, 0, &g_lpuart1priv); } #endif #ifdef CONFIG_USART1_RXDMA if (g_usart1priv.rxdma != NULL) { - stm32wb_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); + stm32_serial_dmarxcallback(g_usart1priv.rxdma, 0, &g_usart1priv); } #endif @@ -2860,12 +2860,12 @@ void stm32wb_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wb_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; - stm32wb_serial_disableusartint(priv, &ie); + stm32_serial_disableusartint(priv, &ie); arm_lowputc(ch); - stm32wb_serial_restoreusartint(priv, ie); + stm32_serial_restoreusartint(priv, ie); #endif } diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 67e1cf36b01..84e96d003b6 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. To use + * stm32_spibus_initialize()) are provided by common STM32 logic. To use * this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -73,7 +73,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_gpio.h" #include "stm32wb_dma.h" #include "stm32wb_spi.h" @@ -131,7 +131,7 @@ * Private Types ****************************************************************************/ -struct stm32wb_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -172,34 +172,34 @@ struct stm32wb_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv); -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv); +static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv); -static int spi_dmatxwait(struct stm32wb_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -230,7 +230,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /* PM interface */ @@ -247,16 +247,16 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, - .select = stm32wb_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -269,13 +269,13 @@ static const struct spi_ops_s g_spi1ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -305,16 +305,16 @@ static struct stm32wb_spidev_s g_spi1dev = static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, - .select = stm32wb_spi2select, + .select = stm32_spi2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wb_spi2status, + .status = stm32_spi2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wb_spi2cmddata, + .cmddata = stm32_spi2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -327,13 +327,13 @@ static const struct spi_ops_s g_spi2ops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wb_spi2register, /* provided externally */ + .registercallback = stm32_spi2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif }; -static struct stm32wb_spidev_s g_spi2dev = +static struct stm32_spidev_s g_spi2dev = { .spidev = { @@ -376,7 +376,7 @@ static struct stm32wb_spidev_s g_spi2dev = * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -398,7 +398,7 @@ static inline uint16_t spi_getreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wb_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { putreg16(value, priv->spibase + offset); @@ -419,7 +419,7 @@ static inline void spi_putreg(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -438,7 +438,7 @@ static inline uint8_t spi_getreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wb_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { putreg8(value, priv->spibase + offset); @@ -458,7 +458,7 @@ static inline void spi_putreg8(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -483,7 +483,7 @@ static inline uint16_t spi_readword(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) +static inline uint8_t spi_readbyte(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -509,7 +509,7 @@ static inline uint8_t spi_readbyte(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wb_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -536,7 +536,7 @@ static inline void spi_writeword(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline void spi_writebyte(struct stm32wb_spidev_s *priv, +static inline void spi_writebyte(struct stm32_spidev_s *priv, uint8_t byte) { /* Wait until the transmit buffer is empty */ @@ -562,7 +562,7 @@ static inline void spi_writebyte(struct stm32wb_spidev_s *priv, * ****************************************************************************/ -static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) +static inline bool spi_16bitmode(struct stm32_spidev_s *priv) { return (priv->nbits > 8); } @@ -576,7 +576,7 @@ static inline bool spi_16bitmode(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmarxwait(struct stm32wb_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -609,7 +609,7 @@ static int spi_dmarxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static int spi_dmatxwait(struct stm32wb_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -642,7 +642,7 @@ static int spi_dmatxwait(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -657,7 +657,7 @@ static inline void spi_dmarxwakeup(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -674,7 +674,7 @@ static inline void spi_dmatxwakeup(struct stm32wb_spidev_s *priv) #ifdef CONFIG_STM32WB_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -694,7 +694,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32WB_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -712,7 +712,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { /* 8- or 16-bit mode? */ @@ -748,7 +748,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, /* Configure the RX DMA */ - stm32wb_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -762,7 +762,7 @@ static void spi_dmarxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -799,7 +799,7 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, /* Setup the TX DMA */ - stm32wb_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -813,10 +813,10 @@ static void spi_dmatxsetup(struct stm32wb_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wb_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -829,10 +829,10 @@ static inline void spi_dmarxstart(struct stm32wb_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI_DMA -static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wb_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -852,7 +852,7 @@ static inline void spi_dmatxstart(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, +static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr; @@ -886,7 +886,7 @@ static void spi_modifycr(uint32_t addr, struct stm32wb_spidev_s *priv, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -918,7 +918,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1026,7 +1026,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1094,7 +1094,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1162,7 +1162,7 @@ static void spi_setbits(struct spi_dev_s *dev, int nbits) static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1226,7 +1226,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1300,7 +1300,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, size_t nwords) #endif { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1401,14 +1401,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; #ifdef CONFIG_STM32WB_DMACAPABLE if ((txbuffer != NULL && - !stm32wb_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && - !stm32wb_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uint32_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region, fall back to non-DMA method. */ @@ -1596,8 +1596,8 @@ static void spi_recvblock(struct spi_dev_s *dev, void *rxbuffer, static int spi_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e pmstate) { - struct stm32wb_spidev_s *priv = (struct stm32wb_spidev_s *)((char *)cb - - offsetof(struct stm32wb_spidev_s, pm_cb)); + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)((char *)cb - + offsetof(struct stm32_spidev_s, pm_cb)); /* Logic to prepare for a reduced power state goes here. */ @@ -1647,7 +1647,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wb_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1689,16 +1689,16 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); #ifdef CONFIG_STM32WB_SPI_DMA - /* Get DMA channels. NOTE: stm32wb_dmachannel() will always assign the DMA - * channel. If the channel is not available, then stm32wb_dmachannel() + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA + * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If * you have another device sharing a DMA channel with SPI and the code - * never releases that channel, then the call to stm32wb_dmachannel() will + * never releases that channel, then the call to stm32_dmachannel() will * hang forever in this function! Don't let your design do that! */ - priv->rxdma = stm32wb_dmachannel(priv->rxch); - priv->txdma = stm32wb_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr(STM32_SPI_CR2_OFFSET, priv, @@ -1723,7 +1723,7 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1736,9 +1736,9 @@ static void spi_bus_initialize(struct stm32wb_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wb_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1755,9 +1755,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI1_SCK); - stm32wb_configgpio(GPIO_SPI1_MISO); - stm32wb_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1780,9 +1780,9 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus) { /* Configure SPI2 pins: SCK, MISO, and MOSI */ - stm32wb_configgpio(GPIO_SPI2_SCK); - stm32wb_configgpio(GPIO_SPI2_MISO); - stm32wb_configgpio(GPIO_SPI2_MOSI); + stm32_configgpio(GPIO_SPI2_SCK); + stm32_configgpio(GPIO_SPI2_MISO); + stm32_configgpio(GPIO_SPI2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index f7998c56b6e..79fb78f1dee 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -58,7 +58,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -71,33 +71,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wb_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wb_spi1/2/...select and stm32wb_spi1/2/...status + * Name: stm32_spi1/2/...select and stm32_spi1/2/...status * * Description: - * The external functions, stm32wb_spi1/2/...select, - * stm32wb_spi1/2/...status, and stm32wb_spi1/2/...cmddata must be + * The external functions, stm32_spi1/2/...select, + * stm32_spi1/2/...status, and stm32_spi1/2/...cmddata must be * provided by board-specific logic. These are implementations of the * select, status, and cmddata methods of the SPI interface defined by * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods - * (including stm32wb_spibus_initialize()) are provided by common + * (including stm32_spibus_initialize()) are provided by common * STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_board_initialize() to configure SPI chip + * 1. Provide logic in stm32_board_initialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2/...select() and stm32wb_spi1/2/...status() + * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() * functions in your board-specific logic. These functions will perform * chip selection and status operations using GPIOs in the way your * board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wb_spi1/2/...cmddata() functions in your + * then provide stm32_spi1/2/...cmddata() functions in your * board-specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wb_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wb_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -105,21 +105,21 @@ struct spi_dev_s *stm32wb_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI1 -void stm32wb_spi1select(struct spi_dev_s *dev, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wb_spi1/2/...register + * Name: stm32_spi1/2/...register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -140,12 +140,12 @@ int stm32wb_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32WB_SPI1 -int stm32wb_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32WB_SPI2 -int stm32wb_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index 660cd4db3a6..eade4167de7 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -164,15 +164,15 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wb_clockconfig(); + stm32_clockconfig(); #ifdef CONFIG_STM32WB_IPCC - stm32wb_ipccreset(); + stm32_ipccreset(); #endif arm_fpuconfig(); - /* Todo: stm32wb_lowsetup(); */ + /* Todo: stm32_lowsetup(); */ - stm32wb_gpioinit(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -223,13 +223,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wb_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wb_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wb/stm32wb_start.h b/arch/arm/src/stm32wb/stm32wb_start.h index e59d2843c56..c8c3eaecb1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.h +++ b/arch/arm/src/stm32wb/stm32wb_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_START_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index acefc6af5ab..7d99e9082c9 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -52,7 +52,7 @@ * There are two interrupts generated from our timer, the overflow interrupt * which drives the timing handler and the capture/compare interrupt which * drives the interval handler. There are some low level timer control - * functions implemented here because the API of stm32wb_tim.c does not + * functions implemented here because the API of stm32_tim.c does not * provide adequate control over capture/compare interrupts. * ****************************************************************************/ @@ -96,13 +96,13 @@ * Private Types ****************************************************************************/ -struct stm32wb_tickless_s +struct stm32_tickless_s { uint8_t timer; /* The timer/counter in use */ uint8_t channel; /* The timer channel to use * for intervals */ - struct stm32wb_tim_dev_s *tch; /* Pointer returned by - * stm32wb_tim_init() */ + struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ uint32_t frequency; uint32_t overflow; /* Timer counter overflow */ volatile bool pending; /* True: pending task */ @@ -114,93 +114,93 @@ struct stm32wb_tickless_s * Private Data ****************************************************************************/ -static struct stm32wb_tickless_s g_tickless; +static struct stm32_tickless_s g_tickless; /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(uint8_t offset) +static inline uint16_t stm32_getreg16(uint8_t offset) { return getreg16(g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(uint8_t offset, uint16_t value) +static inline void stm32_putreg16(uint8_t offset, uint16_t value) { putreg16(value, g_tickless.base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(uint8_t offset, uint16_t clearbits, +static inline void stm32_modifyreg16(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg16(g_tickless.base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_tickless_enableint + * Name: stm32_tickless_enableint ****************************************************************************/ -static inline void stm32wb_tickless_enableint(int channel) +static inline void stm32_tickless_enableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 0, 1 << channel); } /**************************************************************************** - * Name: stm32wb_tickless_disableint + * Name: stm32_tickless_disableint ****************************************************************************/ -static inline void stm32wb_tickless_disableint(int channel) +static inline void stm32_tickless_disableint(int channel) { - stm32wb_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); + stm32_modifyreg16(STM32_TIM_DIER_OFFSET, 1 << channel, 0); } /**************************************************************************** - * Name: stm32wb_tickless_ackint + * Name: stm32_tickless_ackint ****************************************************************************/ -static inline void stm32wb_tickless_ackint(int channel) +static inline void stm32_tickless_ackint(int channel) { - stm32wb_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); + stm32_putreg16(STM32_TIM_SR_OFFSET, ~(1 << channel)); } /**************************************************************************** - * Name: stm32wb_tickless_getint + * Name: stm32_tickless_getint ****************************************************************************/ -static inline uint16_t stm32wb_tickless_getint(void) +static inline uint16_t stm32_tickless_getint(void) { - return stm32wb_getreg16(STM32_TIM_SR_OFFSET); + return stm32_getreg16(STM32_TIM_SR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tickless_setchannel + * Name: stm32_tickless_setchannel ****************************************************************************/ -static int stm32wb_tickless_setchannel(uint8_t channel) +static int stm32_tickless_setchannel(uint8_t channel) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -216,7 +216,7 @@ static int stm32wb_tickless_setchannel(uint8_t channel) /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Frozen mode because we don't want to change the GPIO, preload register @@ -234,17 +234,17 @@ static int stm32wb_tickless_setchannel(uint8_t channel) ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(ccmr_offset); + ccmr_orig = stm32_getreg16(ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(ccmr_offset, ccmr_orig); - stm32wb_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(ccmr_offset, ccmr_orig); + stm32_putreg16(STM32_TIM_CCER_OFFSET, ccer_val); return OK; } /**************************************************************************** - * Name: stm32wb_interval_handler + * Name: stm32_interval_handler * * Description: * Called when the timer counter matches the compare register @@ -261,14 +261,14 @@ static int stm32wb_tickless_setchannel(uint8_t channel) * ****************************************************************************/ -static void stm32wb_interval_handler(void) +static void stm32_interval_handler(void) { tmrinfo("Expired...\n"); /* Disable the compare interrupt now. */ - stm32wb_tickless_disableint(g_tickless.channel); - stm32wb_tickless_ackint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); g_tickless.pending = false; @@ -276,7 +276,7 @@ static void stm32wb_interval_handler(void) } /**************************************************************************** - * Name: stm32wb_timing_handler + * Name: stm32_timing_handler * * Description: * Timer interrupt callback. When the freerun timer counter overflows, @@ -290,7 +290,7 @@ static void stm32wb_interval_handler(void) * ****************************************************************************/ -static void stm32wb_timing_handler(void) +static void stm32_timing_handler(void) { g_tickless.overflow++; @@ -298,7 +298,7 @@ static void stm32wb_timing_handler(void) } /**************************************************************************** - * Name: stm32wb_tickless_handler + * Name: stm32_tickless_handler * * Description: * Generic interrupt handler for this timer. It checks the source of the @@ -312,18 +312,18 @@ static void stm32wb_timing_handler(void) * ****************************************************************************/ -static int stm32wb_tickless_handler(int irq, void *context, void *arg) +static int stm32_tickless_handler(int irq, void *context, void *arg) { - int interrupt_flags = stm32wb_tickless_getint(); + int interrupt_flags = stm32_tickless_getint(); if (interrupt_flags & GTIM_SR_UIF) { - stm32wb_timing_handler(); + stm32_timing_handler(); } if (interrupt_flags & (1 << g_tickless.channel)) { - stm32wb_interval_handler(); + stm32_interval_handler(); } return OK; @@ -402,7 +402,7 @@ void up_timer_initialize(void) tmrinfo("timer=%d channel=%d frequency=%lu Hz\n", g_tickless.timer, g_tickless.channel, g_tickless.frequency); - g_tickless.tch = stm32wb_tim_init(g_tickless.timer); + g_tickless.tch = stm32_tim_init(g_tickless.timer); if (!g_tickless.tch) { tmrerr("ERROR: Failed to allocate TIM%d\n", g_tickless.timer); @@ -413,7 +413,7 @@ void up_timer_initialize(void) /* Set up to receive the callback when the counter overflow occurs */ - STM32_TIM_SETISR(g_tickless.tch, stm32wb_tickless_handler, NULL, 0); + STM32_TIM_SETISR(g_tickless.tch, stm32_tickless_handler, NULL, 0); /* Initialize interval to zero */ @@ -421,7 +421,7 @@ void up_timer_initialize(void) /* Setup compare channel for the interval timing */ - stm32wb_tickless_setchannel(g_tickless.channel); + stm32_tickless_setchannel(g_tickless.channel); /* Set timer period */ @@ -493,7 +493,7 @@ int up_timer_gettime(struct timespec *ts) DEBUGASSERT(g_tickless.tch && ts); /* Temporarily disable the overflow counter. NOTE that we have to be - * careful here because stm32wb_tc_getpending() will reset the pending + * careful here because stm32_tc_getpending() will reset the pending * interrupt status. If we do not handle the overflow here then, it will * be lost. */ @@ -679,7 +679,7 @@ int up_timer_cancel(struct timespec *ts) /* Disable the interrupt. */ - stm32wb_tickless_disableint(g_tickless.channel); + stm32_tickless_disableint(g_tickless.channel); count = STM32_TIM_GETCOUNTER(g_tickless.tch); period = g_tickless.period; @@ -829,8 +829,8 @@ int up_timer_start(const struct timespec *ts) * occurs. */ - stm32wb_tickless_ackint(g_tickless.channel); - stm32wb_tickless_enableint(g_tickless.channel); + stm32_tickless_ackint(g_tickless.channel); + stm32_tickless_enableint(g_tickless.channel); g_tickless.pending = true; leave_critical_section(flags); diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index d784f103c2a..2e7b56cf817 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wb.h" +#include "stm32.h" #include "stm32wb_tim.h" #include "stm32wb_gpio.h" #include "stm32wb_rcc.h" @@ -128,10 +128,10 @@ /* TIM Device Structure */ -struct stm32wb_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wb_tim_ops_s *ops; - enum stm32wb_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -141,116 +141,116 @@ struct stm32wb_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev); +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev); /* Timer methods */ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq); -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev); -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wb_tim_getperiod(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev); -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev); -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source); -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source); -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source); +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wb_tim_ops_s stm32wb_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wb_tim_enable, - .disable = stm32wb_tim_disable, - .setmode = stm32wb_tim_setmode, - .setfreq = stm32wb_tim_setfreq, - .setclock = stm32wb_tim_setclock, - .getclock = stm32wb_tim_getclock, - .setperiod = stm32wb_tim_setperiod, - .getperiod = stm32wb_tim_getperiod, - .getcounter = stm32wb_tim_getcounter, - .getwidth = stm32wb_tim_getwidth, - .setchannel = stm32wb_tim_setchannel, - .setcompare = stm32wb_tim_setcompare, - .getcapture = stm32wb_tim_getcapture, - .setisr = stm32wb_tim_setisr, - .enableint = stm32wb_tim_enableint, - .disableint = stm32wb_tim_disableint, - .ackint = stm32wb_tim_ackint, - .checkint = stm32wb_tim_checkint, - .dump_regs = stm32wb_tim_dumpregs, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setfreq = stm32_tim_setfreq, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .getwidth = stm32_tim_getwidth, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, + .dump_regs = stm32_tim_dumpregs, }; #ifdef CONFIG_STM32WB_TIM1 -struct stm32wb_tim_priv_s stm32wb_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM2 -struct stm32wb_tim_priv_s stm32wb_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM16 -struct stm32wb_tim_priv_s stm32wb_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32WB_TIM17 -struct stm32wb_tim_priv_s stm32wb_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wb_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -261,51 +261,51 @@ struct stm32wb_tim_priv_s stm32wb_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wb_getreg16(struct stm32wb_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_putreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wb_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wb_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the STM32WB @@ -313,14 +313,14 @@ static inline void stm32wb_modifyreg16(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wb_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the STM32WB @@ -328,49 +328,49 @@ static inline uint32_t stm32wb_getreg32(struct stm32wb_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wb_putreg32(struct stm32wb_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wb_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wb_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wb_tim_reload_counter(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wb_putreg16(dev, STM32_TIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wb_tim_enable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_TIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wb_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -378,86 +378,86 @@ static void stm32wb_tim_disable(struct stm32wb_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wb_tim_reset(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32wb_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wb_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM16_GPIOCONFIG) || defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wb_tim_gpioconfig(uint32_t cfg, - enum stm32wb_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wb_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wb_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wb_tim_dumpregs + * Name: stm32_tim_dumpregs ****************************************************************************/ -static void stm32wb_tim_dumpregs(struct stm32wb_tim_dev_s *dev) +static void stm32_tim_dumpregs(struct stm32_tim_dev_s *dev) { - struct stm32wb_tim_priv_s *priv = (struct stm32wb_tim_priv_s *)dev; + struct stm32_tim_priv_s *priv = (struct stm32_tim_priv_s *)dev; ainfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_SMCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DIER_OFFSET) + stm32_getreg16(dev, STM32_TIM_CR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_SMCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DIER_OFFSET) ); ainfo(" SR: %04x EGR: 0000 CCMR1: %04x CCMR2: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCMR2_OFFSET) + stm32_getreg16(dev, STM32_TIM_SR_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCMR2_OFFSET) ); ainfo(" CCER: %04x CNT: %04x PSC: %04x ARR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CNT_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_ARR_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCER_OFFSET), + stm32_getreg16(dev, STM32_TIM_CNT_OFFSET), + stm32_getreg16(dev, STM32_TIM_PSC_OFFSET), + stm32_getreg16(dev, STM32_TIM_ARR_OFFSET) ); ainfo(" CCR1: %04x CCR2: %04x CCR3: %04x CCR4: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_CCR1_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR2_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR3_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_CCR4_OFFSET) + stm32_getreg16(dev, STM32_TIM_CCR1_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR2_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR3_OFFSET), + stm32_getreg16(dev, STM32_TIM_CCR4_OFFSET) ); if (priv->base == STM32_TIM1_BASE) { ainfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_RCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_BDTR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_RCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_BDTR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } else { ainfo(" DCR: %04x DMAR: %04x\n", - stm32wb_getreg16(dev, STM32_TIM_DCR_OFFSET), - stm32wb_getreg16(dev, STM32_TIM_DMAR_OFFSET)); + stm32_getreg16(dev, STM32_TIM_DCR_OFFSET), + stm32_getreg16(dev, STM32_TIM_DMAR_OFFSET)); } } /**************************************************************************** - * Name: stm32wb_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val; @@ -469,14 +469,14 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { #if defined(CONFIG_STM32WB_TIM16) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM16_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif #if defined(CONFIG_STM32WB_TIM17) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM17_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; } @@ -519,15 +519,15 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, return -EINVAL; } - stm32wb_tim_reload_counter(dev); - stm32wb_putreg16(dev, STM32_TIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); #ifdef CONFIG_STM32WB_TIM1 /* Advanced registers require Main Output Enable */ - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM1_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) { - stm32wb_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); + stm32_modifyreg16(dev, STM32_TIM_BDTR_OFFSET, 0, TIM1_BDTR_MOE); } #endif @@ -535,10 +535,10 @@ static int stm32wb_tim_setmode(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setfreq + * Name: stm32_tim_setfreq ****************************************************************************/ -static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -551,7 +551,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -561,7 +561,7 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -647,17 +647,17 @@ static int stm32wb_tim_setfreq(struct stm32wb_tim_dev_s *dev, uint32_t freq) /* Set the reload and prescaler values */ - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); - stm32wb_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler - 1); + stm32_putreg16(dev, STM32_TIM_ARR_OFFSET, reload); return (timclk / reload); } /**************************************************************************** - * Name: stm32wb_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; int prescaler; @@ -668,7 +668,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) if (freq == 0) { - stm32wb_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -678,7 +678,7 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -730,16 +730,16 @@ static int stm32wb_tim_setclock(struct stm32wb_tim_dev_s *dev, uint32_t freq) prescaler = 0xffff; } - stm32wb_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); + stm32_putreg16(dev, STM32_TIM_PSC_OFFSET, prescaler); return prescaler; } /**************************************************************************** - * Name: stm32wb_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -751,7 +751,7 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -782,44 +782,44 @@ static uint32_t stm32wb_tim_getclock(struct stm32wb_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wb_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_TIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wb_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wb_tim_setperiod(struct stm32wb_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wb_putreg32(dev, STM32_TIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_TIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wb_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wb_tim_getperiod (struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wb_getreg32 (dev, STM32_TIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_TIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wb_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wb_getreg32(dev, STM32_TIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_TIM_CNT_OFFSET); /* TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; } @@ -829,15 +829,15 @@ static uint32_t stm32wb_tim_getcounter(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_getwidth + * Name: stm32_tim_getwidth ****************************************************************************/ -static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) +static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ #if defined(CONFIG_STM32WB_TIM2) - if (((struct stm32wb_tim_priv_s *)dev)->base == STM32_TIM2_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; } @@ -849,12 +849,12 @@ static uint32_t stm32wb_tim_getwidth(struct stm32wb_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wb_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -872,7 +872,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wb_getreg16(dev, STM32_TIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_TIM_CCER_OFFSET); ccer_val &= ~(GTIM_CCER_CCXE(channel) | GTIM_CCER_CCXP(channel)); /* Decode configuration */ @@ -903,15 +903,15 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, ccmr_offset = STM32_TIM_CCMR2_OFFSET; } - ccmr_orig = stm32wb_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~(GTIM_CCMR_OCXM_MASK(channel) | GTIM_CCMR_OCXPE(channel)); ccmr_orig |= ccmr_val; - stm32wb_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wb_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_TIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -919,25 +919,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -952,25 +952,25 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wb_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -985,7 +985,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif @@ -1000,7 +1000,7 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wb_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif @@ -1018,10 +1018,10 @@ static int stm32wb_tim_setchannel(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1029,19 +1029,19 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - stm32wb_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR1_OFFSET, compare); break; case 2: - stm32wb_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR2_OFFSET, compare); break; case 3: - stm32wb_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR3_OFFSET, compare); break; case 4: - stm32wb_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_TIM_CCR4_OFFSET, compare); break; default: @@ -1052,10 +1052,10 @@ static int stm32wb_tim_setcompare(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, +static uint32_t stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1063,26 +1063,26 @@ static uint32_t stm32wb_tim_getcapture(struct stm32wb_tim_dev_s *dev, switch (channel) { case 1: - return stm32wb_getreg32(dev, STM32_TIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR1_OFFSET); case 2: - return stm32wb_getreg32(dev, STM32_TIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR2_OFFSET); case 3: - return stm32wb_getreg32(dev, STM32_TIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR3_OFFSET); case 4: - return stm32wb_getreg32(dev, STM32_TIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_TIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wb_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1090,7 +1090,7 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -1138,41 +1138,41 @@ static int stm32wb_tim_setisr(struct stm32wb_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wb_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wb_tim_enableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, 0, source); } /**************************************************************************** - * Name: stm32wb_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wb_tim_disableint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wb_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); + stm32_modifyreg16(dev, STM32_TIM_DIER_OFFSET, source, 0); } /**************************************************************************** - * Name: stm32wb_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wb_tim_ackint(struct stm32wb_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wb_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); + stm32_putreg16(dev, STM32_TIM_SR_OFFSET, ~source); } /**************************************************************************** - * Name: stm32wb_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wb_getreg16(dev, STM32_TIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_TIM_SR_OFFSET); return (regval & source) ? 1 : 0; } @@ -1181,12 +1181,12 @@ static int stm32wb_tim_checkint(struct stm32wb_tim_dev_s *dev, int source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wb_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1194,28 +1194,28 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) { #ifdef CONFIG_STM32WB_TIM1 case 1: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WB_TIM2 case 2: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WB_TIM16 case 16: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WB_TIM17 case 17: - dev = (struct stm32wb_tim_dev_s *)&stm32wb_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1226,30 +1226,30 @@ struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wb_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wb_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wb_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wb_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WB_TIM1 case STM32_TIM1_BASE: @@ -1281,7 +1281,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wb_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wb/stm32wb_tim.h b/arch/arm/src/stm32wb/stm32wb_tim.h index ead07f60195..a7ea2c73451 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.h +++ b/arch/arm/src/stm32wb/stm32wb_tim.h @@ -101,14 +101,14 @@ extern "C" /* TIM Device Structure */ -struct stm32wb_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wb_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wb_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -145,7 +145,7 @@ enum stm32wb_tim_mode_e /* TIM Channel Modes */ -enum stm32wb_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -178,37 +178,37 @@ enum stm32wb_tim_channel_e /* TIM Operations */ -struct stm32wb_tim_ops_s +struct stm32_tim_ops_s { - void (*enable)(struct stm32wb_tim_dev_s *dev); - void (*disable)(struct stm32wb_tim_dev_s *dev); - int (*setmode)(struct stm32wb_tim_dev_s *dev, - enum stm32wb_tim_mode_e mode); - int (*setfreq)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - int (*setclock)(struct stm32wb_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wb_tim_dev_s *dev); - void (*setperiod)(struct stm32wb_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wb_tim_dev_s *dev); - uint32_t (*getwidth)(struct stm32wb_tim_dev_s *dev); - int (*setchannel)(struct stm32wb_tim_dev_s *dev, uint8_t channel, - enum stm32wb_tim_channel_e mode); - int (*setcompare)(struct stm32wb_tim_dev_s *dev, uint8_t channel, + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setfreq)(struct stm32_tim_dev_s *dev, uint32_t freq); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); + uint32_t (*getwidth)(struct stm32_tim_dev_s *dev); + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - uint32_t (*getcapture)(struct stm32wb_tim_dev_s *dev, uint8_t channel); + uint32_t (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wb_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wb_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wb_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wb_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); /* Debug */ - void (*dump_regs)(struct stm32wb_tim_dev_s *dev); + void (*dump_regs)(struct stm32_tim_dev_s *dev); }; /**************************************************************************** @@ -217,14 +217,14 @@ struct stm32wb_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wb_tim_dev_s *stm32wb_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -242,7 +242,7 @@ int stm32wb_tim_deinit(struct stm32wb_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wb_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index ced3f62d5f9..37e35b0f985 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -58,10 +58,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wb_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wb_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -74,17 +74,17 @@ struct stm32wb_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower); -static int stm32wb_stop(struct timer_lowerhalf_s *lower); -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -95,16 +95,16 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wb_start, - .stop = stm32wb_stop, - .getstatus = stm32wb_getstatus, - .settimeout = stm32wb_settimeout, - .setcallback = stm32wb_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32WB_TIM1 -static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -112,7 +112,7 @@ static struct stm32wb_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM2 -static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -120,7 +120,7 @@ static struct stm32wb_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM16 -static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -128,7 +128,7 @@ static struct stm32wb_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32WB_TIM17 -static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -140,7 +140,7 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -151,9 +151,9 @@ static struct stm32wb_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wb_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wb_lowerhalf_s *lower = (struct stm32wb_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, GTIM_DIER_UIE); @@ -167,14 +167,14 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) } else { - stm32wb_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wb_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -188,9 +188,9 @@ static int stm32wb_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wb_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -198,7 +198,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } @@ -212,7 +212,7 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -226,9 +226,9 @@ static int stm32wb_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -245,7 +245,7 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wb_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -260,10 +260,10 @@ static int stm32wb_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -311,7 +311,7 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -326,10 +326,10 @@ static int stm32wb_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -354,7 +354,7 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wb_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -373,10 +373,10 @@ static int stm32wb_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wb_lowerhalf_s *priv = (struct stm32wb_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -386,7 +386,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32wb_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, GTIM_DIER_UIE); } else @@ -403,7 +403,7 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -420,9 +420,9 @@ static void stm32wb_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wb_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wb_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -458,7 +458,7 @@ int stm32wb_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wb_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index a01219c737b..7a9f118a595 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -77,7 +77,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wb_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -85,7 +85,7 @@ * ****************************************************************************/ -static int stm32wb_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -135,7 +135,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wb_timerisr, NULL); + irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index dc4e2dadff4..2fd4f3019d1 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -151,7 +151,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32WB UART is configured for DMA. @@ -164,7 +164,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void stm32wb_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wb/stm32wb_uid.c b/arch/arm/src/stm32wb/stm32wb_uid.c index 17a3808d363..da688a44086 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.c +++ b/arch/arm/src/stm32wb/stm32wb_uid.c @@ -35,7 +35,7 @@ * Public Functions ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32wb/stm32wb_uid.h b/arch/arm/src/stm32wb/stm32wb_uid.h index e1f01292df5..8b95f7d1f68 100644 --- a/arch/arm/src/stm32wb/stm32wb_uid.h +++ b/arch/arm/src/stm32wb/stm32wb_uid.h @@ -33,6 +33,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32wb_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_UID_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.c b/arch/arm/src/stm32wb/stm32wb_userspace.c index 6f9a3451e63..e07473c8d67 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.c +++ b/arch/arm/src/stm32wb/stm32wb_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wb_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wb_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wb_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wb/stm32wb_userspace.h b/arch/arm/src/stm32wb/stm32wb_userspace.h index 4a428e9b7c8..26526ef2128 100644 --- a/arch/arm/src/stm32wb/stm32wb_userspace.h +++ b/arch/arm/src/stm32wb/stm32wb_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wb_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32W_STM32W_USERSPACE_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_waste.c b/arch/arm/src/stm32wb/stm32wb_waste.c index 48f022c7d48..a3660b4ee5b 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.c +++ b/arch/arm/src/stm32wb/stm32wb_waste.c @@ -40,7 +40,7 @@ uint32_t g_waste_counter; * Public Functions ****************************************************************************/ -void stm32wb_waste(void) +void stm32_waste(void) { g_waste_counter++; } diff --git a/arch/arm/src/stm32wb/stm32wb_waste.h b/arch/arm/src/stm32wb/stm32wb_waste.h index 97660bf1608..66c493178f5 100644 --- a/arch/arm/src/stm32wb/stm32wb_waste.h +++ b/arch/arm/src/stm32wb/stm32wb_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32wb_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a * measure of badly written piece of software or some undesired behavior. @@ -55,7 +55,7 @@ extern "C" * cannot be used for other purposes (yet). */ -void stm32wb_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/include/board.h b/boards/arm/stm32wb/flipperzero/include/board.h index bb948a3f3c6..606ccde42c5 100644 --- a/boards/arm/stm32wb/flipperzero/include/board.h +++ b/boards/arm/stm32wb/flipperzero/include/board.h @@ -113,7 +113,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -123,7 +123,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/flipperzero/src/flipperzero.h b/boards/arm/stm32wb/flipperzero/src/flipperzero.h index b7b1015a424..db2509ef533 100644 --- a/boards/arm/stm32wb/flipperzero/src/flipperzero.h +++ b/boards/arm/stm32wb/flipperzero/src/flipperzero.h @@ -82,7 +82,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. @@ -90,7 +90,7 @@ ****************************************************************************/ #ifdef CONFIG_SPI -void weak_function stm32wb_spidev_initialize(void); +void weak_function stm32_spidev_initialize(void); #endif #endif /* __ASSEMBLY__ */ diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index b83f7f7bab3..334cf54abbe 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,16 +68,16 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ #ifdef CONFIG_SPI - if (stm32wb_spidev_initialize) + if (stm32_spidev_initialize) { - stm32wb_spidev_initialize(); + stm32_spidev_initialize(); } #endif @@ -142,7 +142,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -166,7 +166,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -186,7 +186,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32WB_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif } #endif @@ -206,7 +206,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c index 4eea343833d..de3771d6062 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_lcd_st7565.c @@ -55,14 +55,14 @@ * Private Function Prototypes ****************************************************************************/ -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on); -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd); -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on); +static void stm32_st7565_select(struct st7565_lcd_s *lcd); +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd); +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd); -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size); -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level); +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level); /**************************************************************************** * Private Data @@ -73,43 +73,43 @@ static struct lcd_dev_s *g_lcddev; static struct st7565_lcd_s g_st7565_dev = { - .reset = stm32wb_st7565_reset, - .select = stm32wb_st7565_select, - .deselect = stm32wb_st7565_deselect, - .cmddata = stm32wb_st7565_cmddata, - .senddata = stm32wb_st7565_senddata, - .backlight = stm32wb_st7565_backlight + .reset = stm32_st7565_reset, + .select = stm32_st7565_select, + .deselect = stm32_st7565_deselect, + .cmddata = stm32_st7565_cmddata, + .senddata = stm32_st7565_senddata, + .backlight = stm32_st7565_backlight }; -static void stm32wb_st7565_reset(struct st7565_lcd_s *lcd, bool on) +static void stm32_st7565_reset(struct st7565_lcd_s *lcd, bool on) { - stm32wb_gpiowrite(STM32_LCD_RST, !on); + stm32_gpiowrite(STM32_LCD_RST, !on); } -static void stm32wb_st7565_select(struct st7565_lcd_s *lcd) +static void stm32_st7565_select(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 0); + stm32_gpiowrite(STM32_LCD_CS, 0); } -static void stm32wb_st7565_deselect(struct st7565_lcd_s *lcd) +static void stm32_st7565_deselect(struct st7565_lcd_s *lcd) { - stm32wb_gpiowrite(STM32_LCD_CS, 1); + stm32_gpiowrite(STM32_LCD_CS, 1); } -static void stm32wb_st7565_cmddata(struct st7565_lcd_s *lcd, +static void stm32_st7565_cmddata(struct st7565_lcd_s *lcd, const uint8_t cmd) { - stm32wb_gpiowrite(STM32_LCD_A0, !cmd); + stm32_gpiowrite(STM32_LCD_A0, !cmd); } -static int stm32wb_st7565_senddata(struct st7565_lcd_s *lcd, +static int stm32_st7565_senddata(struct st7565_lcd_s *lcd, const uint8_t *data, int size) { SPI_SNDBLOCK(g_spidev, data, size); return 0; } -static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) +static int stm32_st7565_backlight(struct st7565_lcd_s *lcd, int level) { return 0; } @@ -124,10 +124,10 @@ static int stm32wb_st7565_backlight(struct st7565_lcd_s *lcd, int level) int board_lcd_initialize(void) { - stm32wb_configgpio(STM32_LCD_RST); - stm32wb_configgpio(STM32_LCD_A0); + stm32_configgpio(STM32_LCD_RST); + stm32_configgpio(STM32_LCD_A0); - g_spidev = stm32wb_spibus_initialize(STM32_LCD_SPINO); + g_spidev = stm32_spibus_initialize(STM32_LCD_SPINO); if (!g_spidev) { @@ -139,9 +139,9 @@ int board_lcd_initialize(void) g_spidev->ops->setbits(g_spidev, 8); g_spidev->ops->setfrequency(g_spidev, 1000000); - stm32wb_gpiowrite(STM32_LCD_RST, 0); + stm32_gpiowrite(STM32_LCD_RST, 0); up_mdelay(1); - stm32wb_gpiowrite(STM32_LCD_RST, 1); + stm32_gpiowrite(STM32_LCD_RST, 1); return OK; } diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index cfb057dae1e..9e4e5fd13be 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -40,45 +40,45 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void weak_function stm32wb_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { - /* NOTE: Clocking was already provided in stm32wb_rcc.c. + /* NOTE: Clocking was already provided in stm32_rcc.c. * Here, we only initialize chip select pins unique to the board * architecture. */ #ifdef CONFIG_LCD_ST7565 - stm32wb_configgpio(STM32_LCD_CS); /* ST7565 chip select */ + stm32_configgpio(STM32_LCD_CS); /* ST7565 chip select */ #endif } /**************************************************************************** - * Name: stm32wb_spi1/2select and stm32wb_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wb_spi1/2select and stm32wb_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wb_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wb_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wb_spi1/2select() and stm32wb_spi1/2status() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wb_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wb_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -86,17 +86,17 @@ void weak_function stm32wb_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32WB_SPI2 -void stm32wb_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 if (devid == SPIDEV_DISPLAY(0)) { - stm32wb_gpiowrite(STM32_LCD_CS, !selected); + stm32_gpiowrite(STM32_LCD_CS, !selected); } #endif } -uint8_t stm32wb_spi2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h index 328fba31d5f..22040bc8c1a 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/include/board.h +++ b/boards/arm/stm32wb/nucleo-wb55rg/include/board.h @@ -183,7 +183,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. @@ -193,7 +193,7 @@ extern "C" * ****************************************************************************/ -void stm32wb_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c index 1b81d27c678..61ff88b7ea0 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_autoleds.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifdef CONFIG_ARCH_LEDS @@ -51,9 +51,9 @@ void board_autoled_initialize(void) { /* Configure LEDs GPIO for output. Initial state is OFF */ - stm32wb_configgpio(GPIO_LED1); - stm32wb_configgpio(GPIO_LED2); - stm32wb_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); } /**************************************************************************** @@ -68,15 +68,15 @@ void board_autoled_on(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, true); + stm32_gpiowrite(GPIO_LED1, true); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, true); + stm32_gpiowrite(GPIO_LED2, true); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, true); + stm32_gpiowrite(GPIO_LED3, true); break; } } @@ -93,15 +93,15 @@ void board_autoled_off(int led) break; case BOARD_LED1: - stm32wb_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED1, false); break; case BOARD_LED2: - stm32wb_gpiowrite(GPIO_LED2, false); + stm32_gpiowrite(GPIO_LED2, false); break; case BOARD_LED3: - stm32wb_gpiowrite(GPIO_LED3, false); + stm32_gpiowrite(GPIO_LED3, false); break; } } diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index a8199219abe..140f2dbb255 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -58,7 +58,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wb_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WB architectures must provide the following entry point. This @@ -68,7 +68,7 @@ * ****************************************************************************/ -void stm32wb_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs if LED support has been selected. */ @@ -131,7 +131,7 @@ void board_late_initialize(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the STM32WB lower-half RTC driver */ - rtclower = stm32wb_rtc_lowerhalf(); + rtclower = stm32_rtc_lowerhalf(); if (!rtclower) { serr("ERROR: Failed to instantiate the RTC lower-half driver\n"); @@ -155,7 +155,7 @@ void board_late_initialize(void) #ifdef CONFIG_TIMER /* Initialize and register the timer driver */ - ret = stm32wb_timer_initialize("/dev/timer0", 1); + ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to register the timer driver: %d\n", @@ -167,7 +167,7 @@ void board_late_initialize(void) #ifdef CONFIG_STM32WB_BLE /* Initialize and register BLE HCI driver */ - stm32wb_blehci_initialize(); + stm32_blehci_initialize(); #endif UNUSED(ret); } @@ -188,7 +188,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wb_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c index 054482588df..6c911a423c8 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_userleds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wb.h" +#include "stm32.h" #include "nucleo-wb55rg.h" #ifndef CONFIG_ARCH_LEDS @@ -94,8 +94,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering IDLE mode - Turn leds off */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -103,8 +103,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -112,8 +112,8 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - stm32wb_gpiowrite(GPIO_LED_RED, 0); - stm32wb_gpiowrite(GPIO_LED_GREEN, 0); + stm32_gpiowrite(GPIO_LED_RED, 0); + stm32_gpiowrite(GPIO_LED_GREEN, 0); } break; @@ -160,9 +160,9 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, uint32_t board_userled_initialize(void) { - stm32wb_configgpio(GPIO_LED_RED); - stm32wb_configgpio(GPIO_LED_GREEN); - stm32wb_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); return BOARD_NLEDS; } @@ -178,15 +178,15 @@ void board_userled(int led, bool ledon) break; case BOARD_LED_RED: - stm32wb_gpiowrite(GPIO_LED_RED, ledon); + stm32_gpiowrite(GPIO_LED_RED, ledon); break; case GPIO_LED_GREEN: - stm32wb_gpiowrite(GPIO_LED_GREEN, ledon); + stm32_gpiowrite(GPIO_LED_GREEN, ledon); break; case GPIO_LED_BLUE: - stm32wb_gpiowrite(GPIO_LED_BLUE, ledon); + stm32_gpiowrite(GPIO_LED_BLUE, ledon); break; } } @@ -197,9 +197,9 @@ void board_userled(int led, bool ledon) void board_userled_all(uint32_t ledset) { - stm32wb_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); - stm32wb_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); + stm32_gpiowrite(GPIO_LED1, (ledset & BOARD_LED1_BIT) != 0); + stm32_gpiowrite(GPIO_LED2, (ledset & BOARD_LED2_BIT) != 0); + stm32_gpiowrite(GPIO_LED3, (ledset & BOARD_LED3_BIT) != 0); } /**************************************************************************** From 80312dbb2d0d1bea6aefe468f16f72fbf43833f9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 29 May 2026 16:28:59 +0200 Subject: [PATCH 070/268] !arm/stm32wl5: standardize public API/type prefix to stm32_ BREAKING CHANGE: Public STM32WL5 interfaces were renamed from stm32wl5_* forms to canonical stm32_* forms across arch and board headers/sources. Public type names in STM32WL5 timer/GPIO/EXTI and related API-facing declarations were normalized to stm32_* equivalents. The STM32WL5 root family header was renamed from stm32wl5.h to stm32.h; all STM32WL5 arch/board includes were updated accordingly. Signed-off-by: raiden00pl --- arch/arm/src/stm32wl5/{stm32wl5.h => stm32.h} | 6 +- arch/arm/src/stm32wl5/stm32wl5_allocateheap.c | 4 +- arch/arm/src/stm32wl5/stm32wl5_exti.h | 16 +- arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c | 40 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 16 +- arch/arm/src/stm32wl5/stm32wl5_flash.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_gpio.c | 28 +- arch/arm/src/stm32wl5/stm32wl5_gpio.h | 36 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.c | 110 ++--- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_irq.c | 40 +- arch/arm/src/stm32wl5/stm32wl5_lowputc.c | 20 +- arch/arm/src/stm32wl5/stm32wl5_lowputc.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_lse.c | 10 +- arch/arm/src/stm32wl5/stm32wl5_lsi.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_mpuinit.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_mpuinit.h | 12 +- arch/arm/src/stm32wl5/stm32wl5_pwr.c | 20 +- arch/arm/src/stm32wl5/stm32wl5_pwr.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 66 +-- arch/arm/src/stm32wl5/stm32wl5_rcc.h | 42 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 198 ++++---- arch/arm/src/stm32wl5/stm32wl5_spi.c | 162 +++--- arch/arm/src/stm32wl5/stm32wl5_spi.h | 40 +- arch/arm/src/stm32wl5/stm32wl5_start.c | 12 +- arch/arm/src/stm32wl5/stm32wl5_start.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_tim.c | 460 +++++++++--------- arch/arm/src/stm32wl5/stm32wl5_tim.h | 54 +- .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 110 ++--- arch/arm/src/stm32wl5/stm32wl5_timerisr.c | 8 +- arch/arm/src/stm32wl5/stm32wl5_uart.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_uid.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_uid.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_userspace.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_userspace.h | 4 +- arch/arm/src/stm32wl5/stm32wl5_waste.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_waste.h | 4 +- .../stm32wl5/nucleo-wl55jc/include/board.h | 4 +- .../nucleo-wl55jc/src/nucleo-wl55jc.h | 10 +- .../stm32wl5/nucleo-wl55jc/src/stm32_boot.c | 16 +- .../nucleo-wl55jc/src/stm32_buttons.c | 18 +- .../stm32wl5/nucleo-wl55jc/src/stm32_flash.c | 2 +- .../stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c | 4 +- .../stm32wl5/nucleo-wl55jc/src/stm32_leds.c | 20 +- .../stm32wl5/nucleo-wl55jc/src/stm32_spi.c | 97 +--- .../nucleo-wl55jc/src/stm32_ssd1680.c | 14 +- 46 files changed, 854 insertions(+), 907 deletions(-) rename arch/arm/src/stm32wl5/{stm32wl5.h => stm32.h} (95%) diff --git a/arch/arm/src/stm32wl5/stm32wl5.h b/arch/arm/src/stm32wl5/stm32.h similarity index 95% rename from arch/arm/src/stm32wl5/stm32wl5.h rename to arch/arm/src/stm32wl5/stm32.h index 5b7eb440430..9cb9b9bbf3f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5.h +++ b/arch/arm/src/stm32wl5/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32wl5/stm32wl5.h + * arch/arm/src/stm32wl5/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -55,13 +55,13 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Called to configure SPI chip select GPIO pins. * ****************************************************************************/ -void stm32wl5_spidev_initialize(void); +void stm32_spidev_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 7b8dc6081ba..162ec9e3e51 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -192,7 +192,7 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) /* Allow user-mode access to the user heap memory */ - stm32wl5_mpu_uheap((uintptr_t)ubase, usize); + stm32_mpu_uheap((uintptr_t)ubase, usize); #else /* Return the heap settings */ @@ -270,7 +270,7 @@ void arm_addregion(void) /* Allow user-mode access to the SRAM2 heap */ - stm32wl5_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); + stm32_mpu_uheap((uintptr_t)SRAM2_START, SRAM2_END - SRAM2_START); #endif /* Colorize the heap for debug */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti.h b/arch/arm/src/stm32wl5/stm32wl5_exti.h index 9535111414e..79308c15432 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/stm32wl5_exti.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -73,11 +73,11 @@ extern "C" * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Name: stm32wl5_exti_alarm + * Name: stm32_exti_alarm * * Description: * Sets/clears EXTI alarm interrupt. @@ -95,12 +95,12 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_RTC_ALARM -int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, +int stm32_exti_alarm(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_wakeup + * Name: stm32_exti_wakeup * * Description: * Sets/clears EXTI wakeup interrupt. @@ -118,12 +118,12 @@ int stm32wl5_exti_alarm(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_RTC_PERIODIC -int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, +int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif /**************************************************************************** - * Name: stm32wl5_exti_comp + * Name: stm32_exti_comp * * Description: * Sets/clears comparator based events and interrupt triggers. @@ -142,7 +142,7 @@ int stm32wl5_exti_wakeup(bool risingedge, bool fallingedge, bool event, ****************************************************************************/ #ifdef CONFIG_STM32WL5_COMP -int stm32wl5_exti_comp(int cmp, bool risingedge, bool fallingedge, +int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c index f94f6f9bbda..eec0c58a667 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c @@ -66,7 +66,7 @@ static struct gpio_callback_s g_gpio_handlers[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -static int stm32wl5_exti0_isr(int irq, void *context, void *arg) +static int stm32_exti0_isr(int irq, void *context, void *arg) { int ret = OK; @@ -87,7 +87,7 @@ static int stm32wl5_exti0_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti1_isr(int irq, void *context, void *arg) +static int stm32_exti1_isr(int irq, void *context, void *arg) { int ret = OK; @@ -108,7 +108,7 @@ static int stm32wl5_exti1_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti2_isr(int irq, void *context, void *arg) +static int stm32_exti2_isr(int irq, void *context, void *arg) { int ret = OK; @@ -129,7 +129,7 @@ static int stm32wl5_exti2_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti3_isr(int irq, void *context, void *arg) +static int stm32_exti3_isr(int irq, void *context, void *arg) { int ret = OK; @@ -150,7 +150,7 @@ static int stm32wl5_exti3_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti4_isr(int irq, void *context, void *arg) +static int stm32_exti4_isr(int irq, void *context, void *arg) { int ret = OK; @@ -171,7 +171,7 @@ static int stm32wl5_exti4_isr(int irq, void *context, void *arg) return ret; } -static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, +static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { uint32_t pr; @@ -215,14 +215,14 @@ static int stm32wl5_exti_multiisr(int irq, void *context, void *arg, return ret; } -static int stm32wl5_exti95_isr(int irq, void *context, void *arg) +static int stm32_exti95_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 5, 9); + return stm32_exti_multiisr(irq, context, arg, 5, 9); } -static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) +static int stm32_exti1510_isr(int irq, void *context, void *arg) { - return stm32wl5_exti_multiisr(irq, context, arg, 10, 15); + return stm32_exti_multiisr(irq, context, arg, 10, 15); } /**************************************************************************** @@ -230,7 +230,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -252,7 +252,7 @@ static int stm32wl5_exti1510_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg) { struct gpio_callback_s *shared_cbs; @@ -273,37 +273,37 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, switch (pin) { case 0: - handler = stm32wl5_exti0_isr; + handler = stm32_exti0_isr; break; case 1: - handler = stm32wl5_exti1_isr; + handler = stm32_exti1_isr; break; case 2: - handler = stm32wl5_exti2_isr; + handler = stm32_exti2_isr; break; case 3: - handler = stm32wl5_exti3_isr; + handler = stm32_exti3_isr; break; default: - handler = stm32wl5_exti4_isr; + handler = stm32_exti4_isr; break; } } else if (pin < 10) { irq = STM32_IRQ_EXTI95; - handler = stm32wl5_exti95_isr; + handler = stm32_exti95_isr; shared_cbs = &g_gpio_handlers[5]; nshared = 5; } else { irq = STM32_IRQ_EXTI1510; - handler = stm32wl5_exti1510_isr; + handler = stm32_exti1510_isr; shared_cbs = &g_gpio_handlers[10]; nshared = 6; } @@ -349,7 +349,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, pinset |= GPIO_EXTI; } - stm32wl5_configgpio(pinset); + stm32_configgpio(pinset); /* Configure rising/falling edges */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index bb83f736a46..d26cac244cc 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -95,7 +95,7 @@ static void flash_unlock(void) { while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } if (getreg32(STM32_FLASH_CR) & FLASH_CR_LOCK) @@ -145,7 +145,7 @@ static inline void flash_erase(size_t page) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); @@ -155,7 +155,7 @@ static inline void flash_erase(size_t page) * Public Functions ****************************************************************************/ -int stm32wl5_flash_unlock(void) +int stm32_flash_unlock(void) { int ret; @@ -171,7 +171,7 @@ int stm32wl5_flash_unlock(void) return ret; } -int stm32wl5_flash_lock(void) +int stm32_flash_lock(void) { int ret; @@ -188,7 +188,7 @@ int stm32wl5_flash_lock(void) } /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -204,7 +204,7 @@ int stm32wl5_flash_lock(void) * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) { uint32_t regval; int ret; @@ -242,7 +242,7 @@ uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } flash_optbytes_lock(); @@ -457,7 +457,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) { - stm32wl5_waste(); + stm32_waste(); } /* Verify */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.h b/arch/arm/src/stm32wl5/stm32wl5_flash.h index 87f0abbdeb3..1421569ecbf 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.h @@ -36,11 +36,11 @@ * Public Functions Prototypes ****************************************************************************/ -int stm32wl5_flash_lock(void); -int stm32wl5_flash_unlock(void); +int stm32_flash_lock(void); +int stm32_flash_unlock(void); /**************************************************************************** - * Name: stm32wl5_flash_user_optbytes + * Name: stm32_flash_user_optbytes * * Description: * Modify the contents of the user option bytes (USR OPT) on the flash. @@ -56,6 +56,6 @@ int stm32wl5_flash_unlock(void); * ****************************************************************************/ -uint32_t stm32wl5_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); +uint32_t stm32_flash_user_optbytes(uint32_t clrbits, uint32_t setbits); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_FLASH_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.c b/arch/arm/src/stm32wl5/stm32wl5_gpio.c index b3ec90cac4c..402d44079f9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.c +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.c @@ -80,13 +80,13 @@ const uint32_t g_gpiobase[STM32_NPORTS] = ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * * Assumptions: * This function is called early in the initialization sequence so that @@ -94,17 +94,17 @@ const uint32_t g_gpiobase[STM32_NPORTS] = * ****************************************************************************/ -void stm32wl5_gpioinit(void) +void stm32_gpioinit(void) { } /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -115,7 +115,7 @@ void stm32wl5_gpioinit(void) * To-Do: Auto Power Enable ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset) +int stm32_configgpio(uint32_t cfgset) { uintptr_t base; uint32_t regval; @@ -158,7 +158,7 @@ int stm32wl5_configgpio(uint32_t cfgset) /* Set the initial output value */ - stm32wl5_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); + stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0); pinmode = GPIO_MODER_OUTPUT; break; @@ -317,7 +317,7 @@ int stm32wl5_configgpio(uint32_t cfgset) } /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -337,7 +337,7 @@ int stm32wl5_configgpio(uint32_t cfgset) * To-Do: Auto Power Disable ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset) +int stm32_unconfiggpio(uint32_t cfgset) { /* Reuse port and pin number and set it to default HiZ INPUT */ @@ -346,18 +346,18 @@ int stm32wl5_unconfiggpio(uint32_t cfgset) /* To-Do: Mark its unuse for automatic power saving options */ - return stm32wl5_configgpio(cfgset); + return stm32_configgpio(cfgset); } /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value) +void stm32_gpiowrite(uint32_t pinset, bool value) { uint32_t base; uint32_t bit; @@ -391,14 +391,14 @@ void stm32wl5_gpiowrite(uint32_t pinset, bool value) } /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset) +bool stm32_gpioread(uint32_t pinset) { uint32_t base; unsigned int port; diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 9e583c880e8..6d75dfd10cb 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -49,7 +49,7 @@ * Pre-Processor Declarations ****************************************************************************/ -/* Bit-encoded input to stm32wl5_configgpio() */ +/* Bit-encoded input to stm32_configgpio() */ /* Each port bit of the general-purpose I/O (GPIO) ports can be individually * configured by software in several modes: @@ -244,12 +244,12 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_configgpio + * Name: stm32_configgpio * * Description: * Configure a GPIO pin based on bit-encoded description of the pin. * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...) - * function, it must be unconfigured with stm32wl5_unconfiggpio() with + * function, it must be unconfigured with stm32_unconfiggpio() with * the same cfgset first before it can be set to non-alternative function. * * Returned Value: @@ -258,10 +258,10 @@ EXTERN const uint32_t g_gpiobase[STM32_NPORTS]; * ****************************************************************************/ -int stm32wl5_configgpio(uint32_t cfgset); +int stm32_configgpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_unconfiggpio + * Name: stm32_unconfiggpio * * Description: * Unconfigure a GPIO pin based on bit-encoded description of the pin, set @@ -280,30 +280,30 @@ int stm32wl5_configgpio(uint32_t cfgset); * ****************************************************************************/ -int stm32wl5_unconfiggpio(uint32_t cfgset); +int stm32_unconfiggpio(uint32_t cfgset); /**************************************************************************** - * Name: stm32wl5_gpiowrite + * Name: stm32_gpiowrite * * Description: * Write one or zero to the selected GPIO pin * ****************************************************************************/ -void stm32wl5_gpiowrite(uint32_t pinset, bool value); +void stm32_gpiowrite(uint32_t pinset, bool value); /**************************************************************************** - * Name: stm32wl5_gpioread + * Name: stm32_gpioread * * Description: * Read one or zero from the selected GPIO pin * ****************************************************************************/ -bool stm32wl5_gpioread(uint32_t pinset); +bool stm32_gpioread(uint32_t pinset); /**************************************************************************** - * Name: stm32wl5_gpiosetevent + * Name: stm32_gpiosetevent * * Description: * Sets/clears GPIO based event and interrupt triggers. @@ -322,11 +322,11 @@ bool stm32wl5_gpioread(uint32_t pinset); * ****************************************************************************/ -int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, +int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); /**************************************************************************** - * Function: stm32wl5_dumpgpio + * Function: stm32_dumpgpio * * Description: * Dump all GPIO registers associated with the provided base address @@ -334,23 +334,23 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -int stm32wl5_dumpgpio(uint32_t pinset, const char *msg); +int stm32_dumpgpio(uint32_t pinset, const char *msg); #else -# define stm32wl5_dumpgpio(p,m) +# define stm32_dumpgpio(p,m) #endif /**************************************************************************** - * Function: stm32wl5_gpioinit + * Function: stm32_gpioinit * * Description: * Based on configuration within the .config file, it does: * - Remaps positions of alternative functions. * - * Typically called from stm32wl5_start(). + * Typically called from stm32_start(). * ****************************************************************************/ -void stm32wl5_gpioinit(void); +void stm32_gpioinit(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c index d625e58f1e6..e8960ddced0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.c @@ -35,7 +35,7 @@ #include #include "hardware/stm32wl5_ipcc.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_ipcc.h" /**************************************************************************** @@ -44,7 +44,7 @@ /* This structure describes tx or rx of single channel in memory */ -struct stm32wl5_ipcc_chan_mem_s +struct stm32_ipcc_chan_mem_s { unsigned len; /* Number of valid bytes in data[] */ char data[]; /* Data in IPCC memory */ @@ -52,7 +52,7 @@ struct stm32wl5_ipcc_chan_mem_s /* Internal stm32wl5 ipcc structure describing channel state. */ -struct stm32wl5_ipcc_s +struct stm32_ipcc_s { /* Pointer to API connecting upper and lower half of the driver */ @@ -65,14 +65,14 @@ struct stm32wl5_ipcc_s char *rxmem; /* Maximum length of data that rxmem can hold. It is size of the - * reserved space for rxmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for rxmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned rxlen; /* Number of bytes copied from IPCC memory to buffer. Can be less than - * stm32wl5_ipcc_chan_mem_s.len after copy operation when buffer is full. - * Value can persist between multiple ISR and stm32wl5_ipcc_buffer_data() + * stm32_ipcc_chan_mem_s.len after copy operation when buffer is full. + * Value can persist between multiple ISR and stm32_ipcc_buffer_data() * calls, until all data from IPCC memory is successfully buffered. * * When unbuffered version is used, this holds number of bytes already @@ -89,7 +89,7 @@ struct stm32wl5_ipcc_s char *txmem; /* Maximum length of data that txmem can hold. It is size of the - * reserved space for txmem minus sizeof(stm32wl5_ipcc_chan_mem_s.len) + * reserved space for txmem minus sizeof(stm32_ipcc_chan_mem_s.len) */ unsigned txlen; @@ -99,24 +99,24 @@ struct stm32wl5_ipcc_s * Private Function Prototypes ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen); -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen); #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf); -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf); #endif -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg); -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg); +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg); /**************************************************************************** * Private Data ****************************************************************************/ -struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = +struct stm32_ipcc_s g_ipccpriv[IPCC_NCHAN] = { /* Channel 1 is always enabled when IPCC is enabled */ @@ -183,7 +183,7 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_tx_isr + * Name: stm32_ipcc_tx_isr * * Description: * IPCC TX interrupt service routine. This interrupt is called when @@ -209,16 +209,16 @@ struct stm32wl5_ipcc_s g_ipccpriv[IPCC_NCHAN] = * ****************************************************************************/ -static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_tx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED size_t nwritten; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_chan_mem_s *txmem; #endif UNUSED(context); @@ -251,7 +251,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Copy as much as we can into IPCC memory, circbuf won't copy * more than there is in the buffer. @@ -297,7 +297,7 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_write + * Name: stm32_ipcc_write * * Description: * Function writes buffer to IPCC memory that will be later read by @@ -316,12 +316,12 @@ static int stm32wl5_ipcc_tx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_write(struct ipcc_lower_s *ipcc, const char *buffer, size_t buflen) { size_t to_copy; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *txmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *txmem; uint32_t sr; sr = getreg32(STM32_IPCC_C1TOC2SR); @@ -339,7 +339,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, } priv = &g_ipccpriv[ipcc->chan]; - txmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->txmem; + txmem = (struct stm32_ipcc_chan_mem_s *)priv->txmem; /* Disable TX interrupt since we will modify shared data */ @@ -366,7 +366,7 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, } /**************************************************************************** - * Name: stm32wl5_ipcc_rx_isr + * Name: stm32_ipcc_rx_isr * * Description: * Interrupt service routine - this function is called when another CPU @@ -389,13 +389,13 @@ static ssize_t stm32wl5_ipcc_write(struct ipcc_lower_s *ipcc, * ****************************************************************************/ -static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) +static int stm32_ipcc_rx_isr(int irq, void *context, void *arg) { int chan; uint32_t mr; uint32_t sr; uint32_t status; - struct stm32wl5_ipcc_s *priv; + struct stm32_ipcc_s *priv; #ifdef CONFIG_IPCC_BUFFERED ssize_t nread; #endif @@ -429,7 +429,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) priv = &g_ipccpriv[chan]; #ifdef CONFIG_IPCC_BUFFERED - nread = stm32wl5_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); + nread = stm32_ipcc_copy_to_buffer(chan, &priv->ipcc->rxbuf); if (nread) #endif /* CONFIG_IPCC_BUFFERED */ @@ -454,7 +454,7 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) } /**************************************************************************** - * Name: stm32wl5_ipcc_read + * Name: stm32_ipcc_read * * Description: * Function will copy requests number of bytes to buffer. If there is not @@ -477,13 +477,13 @@ static int stm32wl5_ipcc_rx_isr(int irq, void *context, void *arg) * ****************************************************************************/ -static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_read(struct ipcc_lower_s *ipcc, char *buffer, size_t buflen) { size_t to_copy; uint32_t sr; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; sr = getreg32(STM32_IPCC_C2TOC1SR); @@ -498,7 +498,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, } priv = &g_ipccpriv[ipcc->chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* Disable RX interrupt since we will modify shared data */ @@ -541,7 +541,7 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, } /**************************************************************************** - * Name: stm32wl5_ipcc_copy_to_buffer + * Name: stm32_ipcc_copy_to_buffer * * Description: * Copies as much bytes from channel as possible to rxbuf circ buffer. @@ -560,13 +560,13 @@ static ssize_t stm32wl5_ipcc_read(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, +static ssize_t stm32_ipcc_copy_to_buffer(int chan, struct circbuf_s *rxbuf) { size_t to_copy; size_t rxbuf_space; - struct stm32wl5_ipcc_s *priv; - struct stm32wl5_ipcc_chan_mem_s *rxmem; + struct stm32_ipcc_s *priv; + struct stm32_ipcc_chan_mem_s *rxmem; uint32_t sr; sr = getreg32(STM32_IPCC_C2TOC1SR); @@ -582,7 +582,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, } priv = &g_ipccpriv[chan]; - rxmem = (struct stm32wl5_ipcc_chan_mem_s *)priv->rxmem; + rxmem = (struct stm32_ipcc_chan_mem_s *)priv->rxmem; /* If buffer is full, it's possible we did not copy everything from * IPCC memory to buffer in previous interrupt. Then when another @@ -641,7 +641,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_buffer_data + * Name: stm32_ipcc_buffer_data * * Description: * Copies as many bytes as possible from ipcc channel to rxbuf. @@ -658,7 +658,7 @@ static ssize_t stm32wl5_ipcc_copy_to_buffer(int chan, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, +static ssize_t stm32_ipcc_buffer_data(struct ipcc_lower_s *ipcc, struct circbuf_s *rxbuf) { int ret; @@ -669,7 +669,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, /* Copy data to buffer */ - ret = stm32wl5_ipcc_copy_to_buffer(ipcc->chan, rxbuf); + ret = stm32_ipcc_copy_to_buffer(ipcc->chan, rxbuf); /* Re-enable interrupt */ @@ -682,7 +682,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, #endif /**************************************************************************** - * Name: stm32wl5_ipcc_write_notify + * Name: stm32_ipcc_write_notify * * Description: * This function is called when there is new data on circ buffer. @@ -699,7 +699,7 @@ static ssize_t stm32wl5_ipcc_buffer_data(struct ipcc_lower_s *ipcc, ****************************************************************************/ #ifdef CONFIG_IPCC_BUFFERED -static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) +static ssize_t stm32_ipcc_write_notify(struct ipcc_lower_s *ipcc) { modifyreg32(STM32_IPCC_C1MR, STM32_IPCC_MR_CHNFM(ipcc->chan), 0); return 0; @@ -707,10 +707,10 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) #endif /**************************************************************************** - * Name: stm32wl5_ipcc_cleanup + * Name: stm32_ipcc_cleanup * * Description: - * Cleans up resources initialized by stm32wl5_ipcc_init(). This will + * Cleans up resources initialized by stm32_ipcc_init(). This will * free() ipcc pointer! * * Input Parameters: @@ -721,7 +721,7 @@ static ssize_t stm32wl5_ipcc_write_notify(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) +static int stm32_ipcc_cleanup(struct ipcc_lower_s *ipcc) { DEBUGASSERT(ipcc); DEBUGASSERT(ipcc->chan <= IPCC_NCHAN); @@ -743,7 +743,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_ipcc_init + * Name: stm32_ipcc_init * * Description: * Function initializes runtime options for IPCC. This function is called @@ -762,7 +762,7 @@ static int stm32wl5_ipcc_cleanup(struct ipcc_lower_s *ipcc) * ****************************************************************************/ -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) +struct ipcc_lower_s *stm32_ipcc_init(int chan) { int ret; static int ipcc_fti; @@ -786,12 +786,12 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * upper half needs to call to work properly. */ - ipcc->ops.read = stm32wl5_ipcc_read; - ipcc->ops.write = stm32wl5_ipcc_write; - ipcc->ops.cleanup = stm32wl5_ipcc_cleanup; + ipcc->ops.read = stm32_ipcc_read; + ipcc->ops.write = stm32_ipcc_write; + ipcc->ops.cleanup = stm32_ipcc_cleanup; #ifdef CONFIG_IPCC_BUFFERED - ipcc->ops.buffer_data = stm32wl5_ipcc_buffer_data; - ipcc->ops.write_notify = stm32wl5_ipcc_write_notify; + ipcc->ops.buffer_data = stm32_ipcc_buffer_data; + ipcc->ops.write_notify = stm32_ipcc_write_notify; #endif ipcc->chan = chan; @@ -810,14 +810,14 @@ struct ipcc_lower_s *stm32wl5_ipcc_init(int chan) * interrupt functions */ - ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32wl5_ipcc_rx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_RX_IT, stm32_ipcc_rx_isr, NULL); if (ret) { kmm_free(ipcc); return NULL; } - ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32wl5_ipcc_tx_isr, NULL); + ret = irq_attach(STM32_IRQ_IPCC_C1_TX_IT, stm32_ipcc_tx_isr, NULL); if (ret) { kmm_free(ipcc); diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index 1e632661c05..bbee1c57eb8 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -142,6 +142,6 @@ IPCC_CHAN3_SIZE + IPCC_CHAN4_SIZE + \ IPCC_CHAN5_SIZE + IPCC_CHAN6_SIZE) -struct ipcc_lower_s *stm32wl5_ipcc_init(int chan); +struct ipcc_lower_s *stm32_ipcc_init(int chan); #endif /* __ARCH_ARM_SRC_STM32WL5_IPCC_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_irq.c b/arch/arm/src/stm32wl5/stm32wl5_irq.c index b0b25e844bc..3fc635c72f7 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_irq.c +++ b/arch/arm/src/stm32wl5/stm32wl5_irq.c @@ -38,7 +38,7 @@ #include "nvic.h" #include "ram_vectors.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -64,7 +64,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_dumpnvic + * Name: stm32_dumpnvic * * Description: * Dump some interesting NVIC registers @@ -72,7 +72,7 @@ ****************************************************************************/ #if defined(CONFIG_DEBUG_IRQ_INFO) -static void stm32wl5_dumpnvic(const char *msg, int irq) +static void stm32_dumpnvic(const char *msg, int irq) { irqstate_t flags; @@ -128,11 +128,11 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) leave_critical_section(flags); } #else -# define stm32wl5_dumpnvic(msg, irq) +# define stm32_dumpnvic(msg, irq) #endif /**************************************************************************** - * Name: stm32wl5_nmi, stm32wl5_pendsv, stm32wl5_pendsv, stm32wl5_reserved + * Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved * * Description: * Handlers for various exceptions. None are handled and all are fatal @@ -142,7 +142,7 @@ static void stm32wl5_dumpnvic(const char *msg, int irq) ****************************************************************************/ #ifdef CONFIG_DEBUG_FEATURES -static int stm32wl5_nmi(int irq, void *context, void *arg) +static int stm32_nmi(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! NMI received\n"); @@ -150,7 +150,7 @@ static int stm32wl5_nmi(int irq, void *context, void *arg) return 0; } -static int stm32wl5_pendsv(int irq, void *context, void *arg) +static int stm32_pendsv(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! PendSV received\n"); @@ -158,7 +158,7 @@ static int stm32wl5_pendsv(int irq, void *context, void *arg) return 0; } -static int stm32wl5_reserved(int irq, void *context, void *arg) +static int stm32_reserved(int irq, void *context, void *arg) { up_irq_save(); _err("PANIC!!! Reserved interrupt\n"); @@ -168,7 +168,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) #endif /**************************************************************************** - * Name: stm32wl5_prioritize_syscall + * Name: stm32_prioritize_syscall * * Description: * Set the priority of an exception. This function may be needed @@ -176,7 +176,7 @@ static int stm32wl5_reserved(int irq, void *context, void *arg) * ****************************************************************************/ -static inline void stm32wl5_prioritize_syscall(int priority) +static inline void stm32_prioritize_syscall(int priority) { uint32_t regval; @@ -189,7 +189,7 @@ static inline void stm32wl5_prioritize_syscall(int priority) } /**************************************************************************** - * Name: stm32wl5_irqinfo + * Name: stm32_irqinfo * * Description: * Given an IRQ number, provide the register and bit setting to enable or @@ -197,7 +197,7 @@ static inline void stm32wl5_prioritize_syscall(int priority) * ****************************************************************************/ -static int stm32wl5_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, +static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { int n; @@ -323,7 +323,7 @@ void up_irqinitialize(void) /* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ #endif - stm32wl5_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); + stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); /* If the MPU is enabled, then attach and enable the Memory Management * Fault handler. @@ -337,19 +337,19 @@ void up_irqinitialize(void) /* Attach all other processor exceptions (except reset and sys tick) */ #ifdef CONFIG_DEBUG_FEATURES - irq_attach(STM32_IRQ_NMI, stm32wl5_nmi, NULL); + irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL); #ifndef CONFIG_ARM_MPU irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL); #endif irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL); irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL); - irq_attach(STM32_IRQ_PENDSV, stm32wl5_pendsv, NULL); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL); arm_enable_dbgmonitor(); irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); - irq_attach(STM32_IRQ_RESERVED, stm32wl5_reserved, NULL); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL); #endif - stm32wl5_dumpnvic("initial", NR_IRQS); + stm32_dumpnvic("initial", NR_IRQS); #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -374,7 +374,7 @@ void up_disable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to disable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -409,7 +409,7 @@ void up_enable_irq(int irq) uint32_t regval; uint32_t bit; - if (stm32wl5_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) { /* Modify the appropriate bit in the register to enable the interrupt. * For normal interrupts, we need to set the bit in the associated @@ -486,7 +486,7 @@ int up_prioritize_irq(int irq, int priority) regval |= (priority << shift); putreg32(regval, regaddr); - stm32wl5_dumpnvic("prioritize", irq); + stm32_dumpnvic("prioritize", irq); return OK; } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c index 47431555928..fd992865e70 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.c @@ -34,7 +34,7 @@ #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_rcc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_uart.h" @@ -241,7 +241,7 @@ void arm_lowputc(char ch) while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0); #ifdef STM32_CONSOLE_RS485_DIR - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -252,7 +252,7 @@ void arm_lowputc(char ch) #ifdef STM32_CONSOLE_RS485_DIR while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0); - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif @@ -260,7 +260,7 @@ void arm_lowputc(char ch) } /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * This performs basic initialization of the USART used for the serial @@ -269,7 +269,7 @@ void arm_lowputc(char ch) * ****************************************************************************/ -void stm32wl5_lowsetup(void) +void stm32_lowsetup(void) { #if defined(HAVE_UART) #if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) @@ -285,19 +285,19 @@ void stm32wl5_lowsetup(void) /* Enable the console USART and configure GPIO pins needed for rx/tx. * * NOTE: Clocking for selected U[S]ARTs was already provided in - * stm32wl5_rcc.c + * stm32_rcc.c */ #ifdef STM32_CONSOLE_TX - stm32wl5_configgpio(STM32_CONSOLE_TX); + stm32_configgpio(STM32_CONSOLE_TX); #endif #ifdef STM32_CONSOLE_RX - stm32wl5_configgpio(STM32_CONSOLE_RX); + stm32_configgpio(STM32_CONSOLE_RX); #endif #ifdef STM32_CONSOLE_RS485_DIR - stm32wl5_configgpio(STM32_CONSOLE_RS485_DIR); - stm32wl5_gpiowrite(STM32_CONSOLE_RS485_DIR, + stm32_configgpio(STM32_CONSOLE_RS485_DIR); + stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h index 3ab795bc58c..5361886ba16 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lowputc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_lowputc.h @@ -47,7 +47,7 @@ extern "C" #endif /**************************************************************************** - * Name: stm32wl5_lowsetup + * Name: stm32_lowsetup * * Description: * Called at the very beginning of _start. Performs low level @@ -55,7 +55,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_lowsetup(void); +void stm32_lowsetup(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index fe1bcb5ff4d..2225bf11e1c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -69,14 +69,14 @@ static const uint32_t drives[4] = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) oscillator and the LSE system clock. * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void) +void stm32_rcc_enablelse(void) { int writable; uint32_t regval; @@ -101,7 +101,7 @@ void stm32wl5_rcc_enablelse(void) * the PWR CR register before to configuring the LSE. */ - writable = stm32wl5_pwr_enablebkp(true); + writable = stm32_pwr_enablebkp(true); /* Enable the External Low-Speed (LSE) oscillator by setting the LSEON * bit the RCC BDCR register. @@ -174,7 +174,7 @@ void stm32wl5_rcc_enablelse(void) while (!((regval = getreg32(STM32_RCC_BDCR)) & RCC_BDCR_LSESYSRDY)) { - stm32wl5_waste(); + stm32_waste(); } } @@ -189,6 +189,6 @@ void stm32wl5_rcc_enablelse(void) /* Disable backup domain access if it was disabled on entry */ - (void)stm32wl5_pwr_enablebkp(writable); + (void)stm32_pwr_enablebkp(writable); } } diff --git a/arch/arm/src/stm32wl5/stm32wl5_lsi.c b/arch/arm/src/stm32wl5/stm32wl5_lsi.c index 5b5b36395df..12ce587823d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lsi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lsi.c @@ -33,14 +33,14 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void) +void stm32_rcc_enablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. @@ -54,14 +54,14 @@ void stm32wl5_rcc_enablelsi(void) } /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void) +void stm32_rcc_disablelsi(void) { /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION * bit the RCC CSR register. diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c index beab699c025..07fe40f5aef 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only restricted SAM3U @@ -49,7 +49,7 @@ * ****************************************************************************/ -void stm32wl5_mpuinitialize(void) +void stm32_mpuinitialize(void) { uintptr_t datastart = MIN(USERSPACE->us_datastart, USERSPACE->us_bssstart); uintptr_t dataend = MAX(USERSPACE->us_dataend, USERSPACE->us_bssend); @@ -74,7 +74,7 @@ void stm32wl5_mpuinitialize(void) } /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user-heap region. @@ -83,7 +83,7 @@ void stm32wl5_mpuinitialize(void) * ****************************************************************************/ -void stm32wl5_mpu_uheap(uintptr_t start, size_t size) +void stm32_mpu_uheap(uintptr_t start, size_t size) { mpu_user_intsram(start, size); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h index 46968b5add0..a2b518541f0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h +++ b/arch/arm/src/stm32wl5/stm32wl5_mpuinit.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mpuinitialize + * Name: stm32_mpuinitialize * * Description: * Configure the MPU to permit user-space access to only unrestricted MCU @@ -43,13 +43,13 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpuinitialize(void); +void stm32_mpuinitialize(void); #else -# define stm32wl5_mpuinitialize() +# define stm32_mpuinitialize() #endif /**************************************************************************** - * Name: stm32wl5_mpu_uheap + * Name: stm32_mpu_uheap * * Description: * Map the user heap region. @@ -57,9 +57,9 @@ void stm32wl5_mpuinitialize(void); ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_mpu_uheap(uintptr_t start, size_t size); +void stm32_mpu_uheap(uintptr_t start, size_t size); #else -# define stm32wl5_mpu_uheap(start,size) +# define stm32_mpu_uheap(start,size) #endif #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_MPUINIT_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.c b/arch/arm/src/stm32wl5/stm32wl5_pwr.c index 1e0fa171389..001302dab92 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.c @@ -40,17 +40,17 @@ * Private Functions ****************************************************************************/ -static inline uint16_t stm32wl5_pwr_getreg(uint8_t offset) +static inline uint16_t stm32_pwr_getreg(uint8_t offset) { return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_putreg(uint8_t offset, uint16_t value) +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) { putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); } -static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) { modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, @@ -62,7 +62,7 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -76,14 +76,14 @@ static inline void stm32wl5_pwr_modifyreg(uint8_t offset, uint16_t clearbits, * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable) +bool stm32_pwr_enablebkp(bool writable) { uint16_t regval; bool waswritable; /* Get the current state of the STM32WL5 PWR control register 1 */ - regval = stm32wl5_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); waswritable = ((regval & PWR_CR1_DBP) != 0); /* Enable or disable the ability to write */ @@ -93,14 +93,14 @@ bool stm32wl5_pwr_enablebkp(bool writable) /* Disable backup domain access */ regval &= ~PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); } else if (!waswritable && writable) { /* Enable backup domain access */ regval |= PWR_CR1_DBP; - stm32wl5_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); /* Enable does not happen right away */ @@ -111,7 +111,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) } /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -119,7 +119,7 @@ bool stm32wl5_pwr_enablebkp(bool writable) * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void) +void stm32_pwr_boot_c2(void) { modifyreg32(STM32_PWR_CR4, 0, PWR_CR4_C2BOOT); } diff --git a/arch/arm/src/stm32wl5/stm32wl5_pwr.h b/arch/arm/src/stm32wl5/stm32wl5_pwr.h index 7ad52432853..6432351988d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_pwr.h +++ b/arch/arm/src/stm32wl5/stm32wl5_pwr.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_pwr_enablebkp + * Name: stm32_pwr_enablebkp * * Description: * Enables access to the backup domain (RTC registers, RTC backup data @@ -68,10 +68,10 @@ extern "C" * ****************************************************************************/ -bool stm32wl5_pwr_enablebkp(bool writable); +bool stm32_pwr_enablebkp(bool writable); /**************************************************************************** - * Name: stm32wl5_pwr_boot_c2 + * Name: stm32_pwr_boot_c2 * * Description: * Boots up CPU2 (cortex-m0) after reset or wakeup from stop or standby @@ -79,7 +79,7 @@ bool stm32wl5_pwr_enablebkp(bool writable); * ****************************************************************************/ -void stm32wl5_pwr_boot_c2(void); +void stm32_pwr_boot_c2(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index cbc5c60afc8..78699514946 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -38,7 +38,7 @@ #include "chip.h" #include "stm32wl5_rcc.h" #include "stm32wl5_flash.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_waste.h" /**************************************************************************** @@ -75,13 +75,13 @@ ****************************************************************************/ #if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC) -static inline void stm32wl5_rcc_resetbkp(void) +static inline void stm32_rcc_resetbkp(void) { bool init_stat; /* Check if the RTC is already configured */ - init_stat = stm32wl5_rtc_is_initialized(); + init_stat = stm32_rtc_is_initialized(); if (!init_stat) { uint32_t bkregs[STM32_RTC_BKCOUNT]; @@ -98,7 +98,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * backup data registers and backup SRAM). */ - (void)stm32wl5_pwr_enablebkp(true); + (void)stm32_pwr_enablebkp(true); /* We might be changing RTCSEL - to ensure such changes work, we must * reset the backup domain (having backed up the RTC_MAGIC token) @@ -119,7 +119,7 @@ static inline void stm32wl5_rcc_resetbkp(void) putreg32(bkregs[i], STM32_RTC_BKR(i)); } - (void)stm32wl5_pwr_enablebkp(false); + (void)stm32_pwr_enablebkp(false); } } #else @@ -141,7 +141,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -151,7 +151,7 @@ static inline void stm32wl5_rcc_resetbkp(void) * ****************************************************************************/ -void stm32wl5_clockconfig(void) +void stm32_clockconfig(void) { #if 0 /* Make sure that we are starting in the reset state */ @@ -166,7 +166,7 @@ void stm32wl5_clockconfig(void) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -174,13 +174,13 @@ void stm32wl5_clockconfig(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif /* Enable peripheral clocking */ - stm32wl5_rcc_enableperipherals(); + stm32_rcc_enableperipherals(); } /**************************************************************************** @@ -191,7 +191,7 @@ void stm32wl5_clockconfig(void) * ****************************************************************************/ -static void stm32wl5_rcc_enableahb1(void) +static void stm32_rcc_enableahb1(void) { uint32_t regval; @@ -230,7 +230,7 @@ static void stm32wl5_rcc_enableahb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb2(void) +static inline void stm32_rcc_enableahb2(void) { uint32_t regval; @@ -267,7 +267,7 @@ static inline void stm32wl5_rcc_enableahb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableahb3(void) +static inline void stm32_rcc_enableahb3(void) { uint32_t regval; @@ -312,7 +312,7 @@ static inline void stm32wl5_rcc_enableahb3(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb1(void) +static inline void stm32_rcc_enableapb1(void) { uint32_t regval; @@ -405,7 +405,7 @@ static inline void stm32wl5_rcc_enableapb1(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableapb2(void) +static inline void stm32_rcc_enableapb2(void) { uint32_t regval; @@ -462,7 +462,7 @@ static inline void stm32wl5_rcc_enableapb2(void) * ****************************************************************************/ -static inline void stm32wl5_rcc_enableccip(void) +static inline void stm32_rcc_enableccip(void) { uint32_t regval; @@ -545,12 +545,12 @@ static inline void stm32wl5_rcc_enableccip(void) * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig() + * stm32_clockconfig() * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters * None @@ -561,13 +561,13 @@ static inline void stm32wl5_rcc_enableccip(void) ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void) +void stm32_clockenable(void) { #if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ - stm32wl5_board_clockconfig(); + stm32_board_clockconfig(); #else @@ -575,28 +575,28 @@ void stm32wl5_clockenable(void) * board.h */ - stm32wl5_stdclockconfig(); + stm32_stdclockconfig(); #endif } #endif /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void) +void stm32_rcc_enableperipherals(void) { - stm32wl5_rcc_enableccip(); - stm32wl5_rcc_enableahb1(); - stm32wl5_rcc_enableahb2(); - stm32wl5_rcc_enableahb3(); - stm32wl5_rcc_enableapb1(); - stm32wl5_rcc_enableapb2(); + stm32_rcc_enableccip(); + stm32_rcc_enableahb1(); + stm32_rcc_enableahb2(); + stm32_rcc_enableahb3(); + stm32_rcc_enableapb1(); + stm32_rcc_enableapb2(); } /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * Called to change to new clock based on settings in board.h @@ -606,7 +606,7 @@ void stm32wl5_rcc_enableperipherals(void) ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void) +void stm32_stdclockconfig(void) { uint32_t regval; @@ -704,7 +704,7 @@ void stm32wl5_stdclockconfig(void) } #else -# error stm32wl5_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined +# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined #endif @@ -852,7 +852,7 @@ void stm32wl5_stdclockconfig(void) #if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK) /* Low speed internal clock source LSI */ - stm32wl5_rcc_enablelsi(); + stm32_rcc_enablelsi(); #endif } #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 3d563c431c4..6524b3232af 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -54,7 +54,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_mcoconfig + * Name: stm32_mcoconfig * * Description: * Selects the clock source to output on MC pin (PA8) for stm32wl562xx @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -static inline void stm32wl5_mcoconfig(uint32_t source) +static inline void stm32_mcoconfig(uint32_t source) { uint32_t regval; @@ -88,7 +88,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_clockconfig + * Name: stm32_clockconfig * * Description: * Called to establish the clock settings based on the values in board.h. @@ -98,7 +98,7 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -108,10 +108,10 @@ static inline void stm32wl5_mcoconfig(uint32_t source) * ****************************************************************************/ -void stm32wl5_clockconfig(void); +void stm32_clockconfig(void); /**************************************************************************** - * Name: stm32wl5_board_clockconfig + * Name: stm32_board_clockconfig * * Description: * Any STM32WL5 board may replace the "standard" board clock configuration @@ -120,11 +120,11 @@ void stm32wl5_clockconfig(void); ****************************************************************************/ #ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_board_clockconfig(void); +void stm32_board_clockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_stdclockconfig + * Name: stm32_stdclockconfig * * Description: * The standard logic to configure the clocks based on settings in board.h. @@ -135,11 +135,11 @@ void stm32wl5_board_clockconfig(void); ****************************************************************************/ #ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG -void stm32wl5_stdclockconfig(void); +void stm32_stdclockconfig(void); #endif /**************************************************************************** - * Name: stm32wl5_clockenable + * Name: stm32_clockenable * * Description: * Re-enable the clock and restore the clock settings based on settings in @@ -148,12 +148,12 @@ void stm32wl5_stdclockconfig(void); * re-enable/re-start the PLL * * This function performs a subset of the operations performed by - * stm32wl5_clockconfig(): It does not reset any devices, and it does not + * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific - * function called stm32wl5_board_clockconfig(). + * function called stm32_board_clockconfig(). * * Input Parameters: * None @@ -164,11 +164,11 @@ void stm32wl5_stdclockconfig(void); ****************************************************************************/ #ifdef CONFIG_PM -void stm32wl5_clockenable(void); +void stm32_clockenable(void); #endif /**************************************************************************** - * Name: stm32wl5_rcc_enablelse + * Name: stm32_rcc_enablelse * * Description: * Enable the External Low-Speed (LSE) Oscillator. @@ -181,30 +181,30 @@ void stm32wl5_clockenable(void); * ****************************************************************************/ -void stm32wl5_rcc_enablelse(void); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32wl5_rcc_enablelsi + * Name: stm32_rcc_enablelsi * * Description: * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_enablelsi(void); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_disablelsi + * Name: stm32_rcc_disablelsi * * Description: * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32wl5_rcc_disablelsi(void); +void stm32_rcc_disablelsi(void); /**************************************************************************** - * Name: stm32wl5_rcc_enableperipherals + * Name: stm32_rcc_enableperipherals * * Description: * Enable all the chip peripherals according to configuration. This is @@ -213,7 +213,7 @@ void stm32wl5_rcc_disablelsi(void); * ****************************************************************************/ -void stm32wl5_rcc_enableperipherals(void); +void stm32_rcc_enableperipherals(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 462d9170324..3bc1cb4ab5f 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -182,7 +182,7 @@ * Private Types ****************************************************************************/ -struct stm32wl5_serial_s +struct stm32_serial_s { struct uart_dev_s dev; /* Generic UART device */ uint16_t ie; /* Saved interrupt mask bits value */ @@ -297,9 +297,9 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev); static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev); static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status); -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv); +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv); #ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv); +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv); #endif static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable); static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev); @@ -393,7 +393,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER -static struct stm32wl5_serial_s g_lpuart1priv = +static struct stm32_serial_s g_lpuart1priv = { .dev = { @@ -453,7 +453,7 @@ static struct stm32wl5_serial_s g_lpuart1priv = #endif #ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER -static struct stm32wl5_serial_s g_usart1priv = +static struct stm32_serial_s g_usart1priv = { .dev = { @@ -515,7 +515,7 @@ static struct stm32wl5_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ #ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER -static struct stm32wl5_serial_s g_usart2priv = +static struct stm32_serial_s g_usart2priv = { .dev = { @@ -576,7 +576,7 @@ static struct stm32wl5_serial_s g_usart2priv = /* This table lets us iterate over the configured USARTs */ -static struct stm32wl5_serial_s * const +static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { #ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER @@ -614,7 +614,7 @@ static struct serialpm_s g_serialpm = ****************************************************************************/ static inline -uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) +uint32_t stm32wl5serial_getreg(struct stm32_serial_s *priv, int offset) { return getreg32(priv->usartbase + offset); } @@ -624,7 +624,7 @@ uint32_t stm32wl5serial_getreg(struct stm32wl5_serial_s *priv, int offset) ****************************************************************************/ static inline -void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, +void stm32wl5serial_putreg(struct stm32_serial_s *priv, int offset, uint32_t value) { putreg32(value, priv->usartbase + offset); @@ -635,7 +635,7 @@ void stm32wl5serial_putreg(struct stm32wl5_serial_s *priv, ****************************************************************************/ static inline -void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) +void stm32wl5serial_setusartint(struct stm32_serial_s *priv, uint16_t ie) { uint32_t cr; @@ -662,7 +662,7 @@ void stm32wl5serial_setusartint(struct stm32wl5_serial_s *priv, uint16_t ie) * Name: up_restoreusartint ****************************************************************************/ -static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_restoreusartint(struct stm32_serial_s *priv, uint16_t ie) { irqstate_t flags; @@ -678,7 +678,7 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, * Name: stm32wl5serial_disableusartint ****************************************************************************/ -static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, +static void stm32wl5serial_disableusartint(struct stm32_serial_s *priv, uint16_t *ie) { irqstate_t flags; @@ -739,11 +739,11 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) +static int stm32wl5serial_dmanextrx(struct stm32_serial_s *priv) { size_t dmaresidual; - dmaresidual = stm32wl5_dmaresidual(priv->rxdma); + dmaresidual = stm32_dmaresidual(priv->rxdma); return (RXDMA_BUFFER_SIZE - (int)dmaresidual); } @@ -760,8 +760,8 @@ static int stm32wl5serial_dmanextrx(struct stm32wl5_serial_s *priv) #ifndef CONFIG_SUPPRESS_UART_CONFIG static void stm32wl5serial_setformat(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* This first implementation is for U[S]ARTs that support oversampling @@ -921,7 +921,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) #ifdef CONFIG_PM static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #ifdef SERIAL_HAVE_DMA bool dmarestored = false; #endif @@ -940,7 +940,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Force RTS high to prevent further Rx. */ - stm32wl5_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) + stm32_configgpio((priv->rts_gpio & ~GPIO_MODE_MASK) | (GPIO_OUTPUT | GPIO_OUTPUT_SET)); } #endif @@ -969,7 +969,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Suspend Rx DMA. */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); priv->rxdmasusp = true; } } @@ -1010,7 +1010,7 @@ static void stm32wl5serial_setsuspend(struct uart_dev_s *dev, bool suspend) { /* Restore peripheral RTS control. */ - stm32wl5_configgpio(priv->rts_gpio); + stm32_configgpio(priv->rts_gpio); } #endif } @@ -1059,7 +1059,7 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -1085,8 +1085,8 @@ static void stm32wl5serial_pm_setsuspend(bool suspend) static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rcc_en; uint32_t regaddr; @@ -1139,14 +1139,14 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) static int stm32wl5serial_setup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifndef CONFIG_SUPPRESS_UART_CONFIG uint32_t regval; /* Note: The logic here depends on the fact that that the USART module - * was enabled in stm32wl5_lowsetup(). + * was enabled in stm32_lowsetup(). */ /* Enable USART APB1/2 clock */ @@ -1157,18 +1157,18 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_configgpio(priv->rx_gpio); + stm32_configgpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_configgpio(priv->cts_gpio); + stm32_configgpio(priv->cts_gpio); } #endif @@ -1182,15 +1182,15 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; #endif - stm32wl5_configgpio(config); + stm32_configgpio(config); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_configgpio(priv->rs485_dir_gpio); - stm32wl5_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + stm32_configgpio(priv->rs485_dir_gpio); + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif @@ -1265,8 +1265,8 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int result; uint32_t regval; @@ -1283,14 +1283,14 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) /* Acquire the DMA channel. This should always succeed. */ - priv->rxdma = stm32wl5_dmachannel(priv->rxdma_channel); + priv->rxdma = stm32_dmachannel(priv->rxdma_channel); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1301,7 +1301,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -1328,7 +1328,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -1339,7 +1339,7 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -1358,8 +1358,8 @@ static int stm32wl5serial_dmasetup(struct uart_dev_s *dev) static void stm32wl5serial_shutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t regval; /* Mark device as uninitialized. */ @@ -1390,32 +1390,32 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) if (priv->tx_gpio != 0) { - stm32wl5_unconfiggpio(priv->tx_gpio); + stm32_unconfiggpio(priv->tx_gpio); } if (priv->rx_gpio != 0) { - stm32wl5_unconfiggpio(priv->rx_gpio); + stm32_unconfiggpio(priv->rx_gpio); } #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->cts_gpio != 0) { - stm32wl5_unconfiggpio(priv->cts_gpio); + stm32_unconfiggpio(priv->cts_gpio); } #endif #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->rts_gpio != 0) { - stm32wl5_unconfiggpio(priv->rts_gpio); + stm32_unconfiggpio(priv->rts_gpio); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_unconfiggpio(priv->rs485_dir_gpio); + stm32_unconfiggpio(priv->rs485_dir_gpio); } #endif } @@ -1432,8 +1432,8 @@ static void stm32wl5serial_shutdown(struct uart_dev_s *dev) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Perform the normal UART shutdown */ @@ -1441,11 +1441,11 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) /* Stop the DMA channel */ - stm32wl5_dmastop(priv->rxdma); + stm32_dmastop(priv->rxdma); /* Release the DMA channel */ - stm32wl5_dmafree(priv->rxdma); + stm32_dmafree(priv->rxdma); priv->rxdma = NULL; } #endif @@ -1468,8 +1468,8 @@ static void stm32wl5serial_dmashutdown(struct uart_dev_s *dev) static int stm32wl5serial_attach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int ret; /* Attach and enable the IRQ */ @@ -1500,8 +1500,8 @@ static int stm32wl5serial_attach(struct uart_dev_s *dev) static void stm32wl5serial_detach(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; up_disable_irq(priv->irq); irq_detach(priv->irq); } @@ -1521,7 +1521,7 @@ static void stm32wl5serial_detach(struct uart_dev_s *dev) static int stm32wl5serial_interrupt(int irq, void *context, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; int passes; bool handled; @@ -1581,7 +1581,7 @@ static int stm32wl5serial_interrupt(int irq, void *context, (priv->ie & USART_CR1_TCIE) != 0 && (priv->ie & USART_CR1_TXEIE) == 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, + stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); stm32wl5serial_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE); } @@ -1648,8 +1648,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #endif int ret = OK; @@ -1658,9 +1658,9 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, #ifdef CONFIG_SERIAL_TIOCSERGSTRUCT case TIOCSERGSTRUCT: { - struct stm32wl5_serial_s *user; + struct stm32_serial_s *user; - user = (struct stm32wl5_serial_s *)arg; + user = (struct stm32_serial_s *)arg; if (!user) { @@ -1668,7 +1668,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, } else { - memcpy(user, dev, sizeof(struct stm32wl5_serial_s)); + memcpy(user, dev, sizeof(struct stm32_serial_s)); } } break; @@ -1723,7 +1723,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | gpio_val); } @@ -1734,7 +1734,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { if (priv->tx_gpio != 0) { - stm32wl5_configgpio((priv->tx_gpio & + stm32_configgpio((priv->tx_gpio & ~(GPIO_PUPD_MASK | GPIO_OPENDRAIN)) | GPIO_PUSHPULL); } @@ -1960,7 +1960,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, { uint32_t tx_break = GPIO_OUTPUT | (~(GPIO_MODE_MASK | GPIO_OUTPUT_SET) & priv->tx_gpio); - stm32wl5_configgpio(tx_break); + stm32_configgpio(tx_break); } leave_critical_section(flags); @@ -1977,7 +1977,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, if (priv->tx_gpio != 0) { - stm32wl5_configgpio(priv->tx_gpio); + stm32_configgpio(priv->tx_gpio); } priv->ie &= ~USART_CR1_IE_BREAK_INPROGRESS; @@ -2040,8 +2040,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, static int stm32wl5serial_receive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; uint32_t rdr; /* Get the Rx byte */ @@ -2070,8 +2070,8 @@ static int stm32wl5serial_receive(struct uart_dev_s *dev, #ifndef SERIAL_HAVE_ONLY_DMA static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; uint16_t ie; @@ -2130,8 +2130,8 @@ static void stm32wl5serial_rxint(struct uart_dev_s *dev, bool enable) #ifndef SERIAL_HAVE_ONLY_DMA static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_RXNE) != 0); @@ -2165,8 +2165,8 @@ static bool stm32wl5serial_rxavailable(struct uart_dev_s *dev) static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) @@ -2174,7 +2174,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, { /* Assert/de-assert nRTS set it high resume/stop sending */ - stm32wl5_gpiowrite(priv->rts_gpio, upper); + stm32_gpiowrite(priv->rts_gpio, upper); if (upper) { @@ -2249,8 +2249,8 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, unsigned int *status) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; int c = 0; if (stm32wl5serial_dmanextrx(priv) != priv->rxdmanext) @@ -2288,14 +2288,14 @@ static int stm32wl5serial_dmareceive(struct uart_dev_s *dev, ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) -static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) +static void stm32wl5serial_dmareenable(struct stm32_serial_s *priv) { #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { /* Configure for non-circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2306,7 +2306,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) { /* Configure for circular DMA reception into the RX FIFO */ - stm32wl5_dmasetup(priv->rxdma, + stm32_dmasetup(priv->rxdma, priv->usartbase + STM32_USART_RDR_OFFSET, (uint32_t)priv->rxfifo, RXDMA_BUFFER_SIZE, @@ -2327,7 +2327,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * in and DMA transfer is stopped. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, false); } else @@ -2338,7 +2338,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) * worth of time to claim bytes before they are overwritten. */ - stm32wl5_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, + stm32_dmastart(priv->rxdma, stm32wl5serial_dmarxcallback, (void *)priv, true); } @@ -2359,7 +2359,7 @@ static void stm32wl5serial_dmareenable(struct stm32wl5_serial_s *priv) ****************************************************************************/ #if defined(SERIAL_HAVE_DMA) && defined(CONFIG_SERIAL_IFLOWCONTROL) -static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) +static bool stm32wl5serial_dmaiflowrestart(struct stm32_serial_s *priv) { if (!priv->rxenable) { @@ -2410,8 +2410,8 @@ static bool stm32wl5serial_dmaiflowrestart(struct stm32wl5_serial_s *priv) #ifdef SERIAL_HAVE_DMA static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* En/disable DMA reception. * @@ -2445,8 +2445,8 @@ static void stm32wl5serial_dmarxint(struct uart_dev_s *dev, bool enable) #ifdef SERIAL_HAVE_DMA static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; /* Compare our receive pointer to the current DMA pointer, if they * do not match, then there are bytes to be received. @@ -2466,13 +2466,13 @@ static bool stm32wl5serial_dmarxavailable(struct uart_dev_s *dev) static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - stm32wl5_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif @@ -2489,8 +2489,8 @@ static void stm32wl5serial_send(struct uart_dev_s *dev, int ch) static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; irqstate_t flags; /* USART transmit interrupts: @@ -2558,8 +2558,8 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) static bool stm32wl5serial_txready(struct uart_dev_s *dev) { - struct stm32wl5_serial_s *priv = - (struct stm32wl5_serial_s *)dev->priv; + struct stm32_serial_s *priv = + (struct stm32_serial_s *)dev->priv; return ((stm32wl5serial_getreg(priv, STM32_USART_ISR_OFFSET) & USART_ISR_TXE) != 0); @@ -2578,7 +2578,7 @@ static bool stm32wl5serial_txready(struct uart_dev_s *dev) static void stm32wl5serial_dmarxcallback(DMA_HANDLE handle, uint8_t status, void *arg) { - struct stm32wl5_serial_s *priv = (struct stm32wl5_serial_s *)arg; + struct stm32_serial_s *priv = (struct stm32_serial_s *)arg; if (priv->rxenable && stm32wl5serial_dmarxavailable(&priv->dev)) { @@ -2736,7 +2736,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, * buffers. */ - stm32wl5_serial_dma_poll(); + stm32_serial_dma_poll(); #endif /* Check if any of the active ports have data pending on Tx/Rx @@ -2745,7 +2745,7 @@ static int stm32wl5serial_pmprepare(struct pm_callback_s *cb, int domain, for (n = 0; n < STM32_NLPUART + STM32_NUSART; n++) { - struct stm32wl5_serial_s *priv = g_uart_devs[n]; + struct stm32_serial_s *priv = g_uart_devs[n]; if (!priv || !priv->initialized) { @@ -2909,7 +2909,7 @@ void arm_serialinit(void) } /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Checks receive DMA buffers for received bytes that have not accumulated @@ -2920,7 +2920,7 @@ void arm_serialinit(void) ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void) +void stm32_serial_dma_poll(void) { irqstate_t flags; @@ -2962,7 +2962,7 @@ void stm32wl5_serial_dma_poll(void) void up_putc(int ch) { #if CONSOLE_UART > 0 - struct stm32wl5_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; + struct stm32_serial_s *priv = g_uart_devs[CONSOLE_UART - 1]; uint16_t ie; stm32wl5serial_disableusartint(priv, &ie); diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 55229b62434..45a5a2c2dda 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -21,22 +21,22 @@ ****************************************************************************/ /**************************************************************************** - * The external functions, stm32wl5_spi1/2select and stm32wl5_spi1/2status + * The external functions, stm32_spi1/2select and stm32_spi1/2status * must be provided by board-specific logic. They are implementations of the * select and status methods of the SPI interface defined by struct spi_ops_s * (see include/nuttx/spi/spi.h). - * All other methods (including stm32wl5_spibus_initialize()) are provided + * All other methods (including stm32_spibus_initialize()) are provided * by common STM32 logic. To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2() functions + * 2. Provide stm32_spi1/2select() and stm32_spi1/2() functions * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -67,7 +67,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #ifdef CONFIG_STM32WL5_SPI_DMA #include "stm32wl5_dma.h" @@ -155,7 +155,7 @@ * Private Types ****************************************************************************/ -struct stm32wl5_spidev_s +struct stm32_spidev_s { struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ @@ -196,45 +196,45 @@ struct stm32wl5_spidev_s /* Helpers */ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset); -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset); -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value); -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value); -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv); -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_readword(struct stm32_spidev_s *priv); +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t byte); /* DMA support */ #ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv); -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv); -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv); +static int spi_dmarxwait(struct stm32_spidev_s *priv); +static int spi_dmatxwait(struct stm32_spidev_s *priv); +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv); static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords); -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords); -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv); -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv); +static inline void spi_dmarxstart(struct stm32_spidev_s *priv); +static inline void spi_dmatxstart(struct stm32_spidev_s *priv); #endif /* SPI methods */ @@ -267,7 +267,7 @@ static void spi_recvblock(struct spi_dev_s *dev, /* Initialization */ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); +static void spi_bus_initialize(struct stm32_spidev_s *priv); /**************************************************************************** * Private Data @@ -277,16 +277,16 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv); static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, - .select = stm32wl5_spi1select, + .select = stm32_spi1select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi1status, + .status = stm32_spi1status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi1cmddata, + .cmddata = stm32_spi1cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -299,7 +299,7 @@ static const struct spi_ops_s g_sp1iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_spi1register, /* Provided externally */ + .registercallback = stm32_spi1register, /* Provided externally */ #else .registercallback = 0, /* Not implemented */ #endif @@ -310,7 +310,7 @@ static uint8_t g_spi1_txbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; static uint8_t g_spi1_rxbuf[SPI1_DMABUFSIZE_ADJUSTED] SPI1_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi1dev = +static struct stm32_spidev_s g_spi1dev = { .spidev = { @@ -345,16 +345,16 @@ static struct stm32wl5_spidev_s g_spi1dev = static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, - .select = stm32wl5_spi2s2select, + .select = stm32_spi2s2select, .setfrequency = spi_setfrequency, .setmode = spi_setmode, .setbits = spi_setbits, #ifdef CONFIG_SPI_HWFEATURES .hwfeatures = spi_hwfeatures, #endif - .status = stm32wl5_spi2s2status, + .status = stm32_spi2s2status, #ifdef CONFIG_SPI_CMDDATA - .cmddata = stm32wl5_spi2s2cmddata, + .cmddata = stm32_spi2s2cmddata, #endif .send = spi_send, #ifdef CONFIG_SPI_EXCHANGE @@ -367,7 +367,7 @@ static const struct spi_ops_s g_sp2iops = .trigger = spi_trigger, #endif #ifdef CONFIG_SPI_CALLBACK - .registercallback = stm32wl5_s2register, /* provided externally */ + .registercallback = stm32_s2register, /* provided externally */ #else .registercallback = 0, /* not implemented */ #endif @@ -380,7 +380,7 @@ static uint8_t g_spi2s2_rxbuf[SPI2S2_DMABUFSIZE_ADJUSTED] SPI2S2_DMABUFSIZE_ALGN; #endif -static struct stm32wl5_spidev_s g_spi2s2dev = +static struct stm32_spidev_s g_spi2s2dev = { .spidev = { @@ -427,7 +427,7 @@ static struct stm32wl5_spidev_s g_spi2s2dev = * ****************************************************************************/ -static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, +static inline uint8_t spi_getreg8(struct stm32_spidev_s *priv, uint8_t offset) { return getreg8(priv->spibase + offset); @@ -448,7 +448,7 @@ static inline uint8_t spi_getreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, +static inline uint16_t spi_getreg(struct stm32_spidev_s *priv, uint8_t offset) { return getreg16(priv->spibase + offset); @@ -470,7 +470,7 @@ static inline uint16_t spi_getreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg(struct stm32_spidev_s *priv, uint8_t offset, uint16_t value) { @@ -493,7 +493,7 @@ static inline void spi_putreg(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, +static inline void spi_putreg8(struct stm32_spidev_s *priv, uint8_t offset, uint8_t value) { @@ -514,7 +514,7 @@ static inline void spi_putreg8(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) +static inline uint16_t spi_readword(struct stm32_spidev_s *priv) { /* Wait until the receive buffer is not empty */ @@ -563,7 +563,7 @@ static inline uint16_t spi_readword(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static inline void spi_writeword(struct stm32wl5_spidev_s *priv, +static inline void spi_writeword(struct stm32_spidev_s *priv, uint16_t word) { /* Wait until the transmit buffer is empty */ @@ -593,7 +593,7 @@ static inline void spi_writeword(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) +static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -626,7 +626,7 @@ static int spi_dmarxwait(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) +static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -659,7 +659,7 @@ static int spi_dmatxwait(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) +static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); } @@ -674,7 +674,7 @@ static inline void spi_dmarxwakeup(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) +static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); } @@ -691,7 +691,7 @@ static inline void spi_dmatxwakeup(struct stm32wl5_spidev_s *priv) #ifdef CONFIG_STM32WL5_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -711,7 +711,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) #ifdef CONFIG_STM32WL5_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)arg; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; /* Wake-up the SPI driver */ @@ -729,7 +729,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -766,7 +766,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, /* Configure the RX DMA */ - stm32wl5_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->rxdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)rxbuffer, nwords, priv->rxccr); } #endif @@ -780,7 +780,7 @@ static void spi_dmarxsetup(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, +static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) { @@ -817,7 +817,7 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, /* Setup the TX DMA */ - stm32wl5_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, + stm32_dmasetup(priv->txdma, priv->spibase + STM32_SPI_DR_OFFSET, (uint32_t)txbuffer, nwords, priv->txccr); } #endif @@ -831,10 +831,10 @@ static void spi_dmatxsetup(struct stm32wl5_spidev_s *priv, ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) +static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; - stm32wl5_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); + stm32_dmastart(priv->rxdma, spi_dmarxcallback, priv, false); } #endif @@ -847,10 +847,10 @@ static inline void spi_dmarxstart(struct stm32wl5_spidev_s *priv) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI_DMA -static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) +static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; - stm32wl5_dmastart(priv->txdma, spi_dmatxcallback, priv, false); + stm32_dmastart(priv->txdma, spi_dmatxcallback, priv, false); } #endif @@ -870,7 +870,7 @@ static inline void spi_dmatxstart(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -static void spi_modifycr1(struct stm32wl5_spidev_s *priv, +static void spi_modifycr1(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { @@ -900,7 +900,7 @@ static void spi_modifycr1(struct stm32wl5_spidev_s *priv, * ****************************************************************************/ -static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, +static void spi_modifycr2(struct stm32_spidev_s *priv, uint16_t setbits, uint16_t clrbits) { uint16_t cr2; @@ -935,7 +935,7 @@ static void spi_modifycr2(struct stm32wl5_spidev_s *priv, uint16_t setbits, static int spi_lock(struct spi_dev_s *dev, bool lock) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; if (lock) @@ -968,7 +968,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock) static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint32_t actual; @@ -1069,7 +1069,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1168,7 +1168,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) static void spi_setbits(struct spi_dev_s *dev, int nbits) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; @@ -1237,7 +1237,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, spi_hwfeatures_t features) { #if defined(CONFIG_SPI_BITORDER) || defined(CONFIG_SPI_TRIGGER) - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; #endif #ifdef CONFIG_SPI_BITORDER @@ -1301,7 +1301,7 @@ static int spi_hwfeatures(struct spi_dev_s *dev, static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint32_t regval; uint32_t ret; @@ -1359,7 +1359,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, void *rxbuffer, size_t nwords) #endif { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; DEBUGASSERT(priv && priv->spibase); spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); @@ -1460,7 +1460,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; void *xbuffer = rxbuffer; int ret; @@ -1495,9 +1495,9 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_STM32WL5_DMACAPABLE if ((txbuffer != NULL && priv->txbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || + !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && priv->rxbuf == NULL && - !stm32wl5_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) + !stm32_dmacapable((uintptr_t)rxbuffer, nwords, priv->rxccr))) { /* Unsupported memory region fall back to non-DMA method. */ @@ -1602,7 +1602,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, static int spi_trigger(struct spi_dev_s *dev) { #ifdef CONFIG_STM32WL5_SPI_DMA - struct stm32wl5_spidev_s *priv = (struct stm32wl5_spidev_s *)dev; + struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) { @@ -1695,7 +1695,7 @@ static void spi_recvblock(struct spi_dev_s *dev, * ****************************************************************************/ -static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) +static void spi_bus_initialize(struct stm32_spidev_s *priv) { uint16_t setbits; uint16_t clrbits; @@ -1736,18 +1736,18 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) #ifdef CONFIG_STM32WL5_SPI_DMA if (priv->rxch && priv->txch) { - /* Get DMA channels. NOTE: stm32wl5_dmachannel() will always assign + /* Get DMA channels. NOTE: stm32_dmachannel() will always assign * the DMA channel. If the channel is not available, then - * stm32wl5_dmachannel() will block and wait until the channel becomes + * stm32_dmachannel() will block and wait until the channel becomes * available. * WARNING: If you have another device sharing a DMA channel with * SPI and the code never releases that channel, then the call to - * stm32wl5_dmachannel() will hang forever in this function! + * stm32_dmachannel() will hang forever in this function! * Don't let your design do that! */ - priv->rxdma = stm32wl5_dmachannel(priv->rxch); - priv->txdma = stm32wl5_dmachannel(priv->txch); + priv->rxdma = stm32_dmachannel(priv->rxch); + priv->txdma = stm32_dmachannel(priv->txch); DEBUGASSERT(priv->rxdma && priv->txdma); spi_modifycr2(priv, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN, 0); @@ -1769,7 +1769,7 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -1782,9 +1782,9 @@ static void spi_bus_initialize(struct stm32wl5_spidev_s *priv) * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus) +struct spi_dev_s *stm32_spibus_initialize(int bus) { - struct stm32wl5_spidev_s *priv = NULL; + struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); @@ -1801,9 +1801,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI1 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI1_SCK); - stm32wl5_configgpio(GPIO_SPI1_MISO); - stm32wl5_configgpio(GPIO_SPI1_MOSI); + stm32_configgpio(GPIO_SPI1_SCK); + stm32_configgpio(GPIO_SPI1_MISO); + stm32_configgpio(GPIO_SPI1_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ @@ -1826,9 +1826,9 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus) { /* Configure SPI2S2 pins: SCK, MISO, and MOSI */ - stm32wl5_configgpio(GPIO_SPI2S2_SCK); - stm32wl5_configgpio(GPIO_SPI2S2_MISO); - stm32wl5_configgpio(GPIO_SPI2S2_MOSI); + stm32_configgpio(GPIO_SPI2S2_SCK); + stm32_configgpio(GPIO_SPI2S2_MISO); + stm32_configgpio(GPIO_SPI2S2_MOSI); /* Set up default configuration: Master, 8-bit, etc. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.h b/arch/arm/src/stm32wl5/stm32wl5_spi.h index 17071c7fa32..32b3d1c792b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.h @@ -61,7 +61,7 @@ struct spi_dev_s; ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_spibus_initialize + * Name: stm32_spibus_initialize * * Description: * Initialize the selected SPI bus @@ -74,33 +74,33 @@ struct spi_dev_s; * ****************************************************************************/ -struct spi_dev_s *stm32wl5_spibus_initialize(int bus); +struct spi_dev_s *stm32_spibus_initialize(int bus); /**************************************************************************** - * Name: stm32wl5_spi1/2select and stm32wl5_spi1/2status + * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32wl5_spi1/2select, stm32wl5_spi1/2status, - * and stm32wl5_spi1/2cmddata must be provided by board-specific logic. + * The external functions, stm32_spi1/2select, stm32_spi1/2status, + * and stm32_spi1/2cmddata must be provided by board-specific logic. * These are implementations of the select, status, and cmddata methods of * the SPI interface defined by struct spi_ops_s (see * include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * - * 1. Provide logic in stm32wl5_boardinitialize() to configure SPI chip + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip * select pins. - * 2. Provide stm32wl5_spi1/2select() and stm32wl5_spi1/2status() + * 2. Provide stm32_spi1/2select() and stm32_spi1/2status() * functions in your board-specific logic. These functions will * perform chip selection and status operations using GPIOs in the way * your board is configured. * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32wl5_spi1/2cmddata() functions in your board- + * then provide stm32_spi1/2cmddata() functions in your board- * specific logic. These functions will perform cmd/data selection * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32wl5_spibus_initialize() in your low level + * 4. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 5. The handle returned by stm32wl5_spibus_initialize() may then be used + * 5. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -108,21 +108,21 @@ struct spi_dev_s *stm32wl5_spibus_initialize(int bus); ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif #ifdef CONFIG_STM32WL5_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected); -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid); -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid); +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif /**************************************************************************** - * Name: stm32wl5_spi1/2s2register + * Name: stm32_spi1/2s2register * * Description: * If the board supports a card detect callback to inform the SPI-based @@ -143,12 +143,12 @@ int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #ifdef CONFIG_SPI_CALLBACK #ifdef CONFIG_STM32WL5_SPI1 -int stm32wl5_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, +int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif #ifdef CONFIG_STM32WL5_SPI2S2 -int stm32wl5_spi2s2register(struct spi_dev_s *dev, +int stm32_spi2s2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index aedd8b76cbf..e42585e0c82 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "nvic.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_userspace.h" #include "stm32wl5_start.h" @@ -153,9 +153,9 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ - stm32wl5_clockconfig(); - stm32wl5_lowsetup(); - stm32wl5_gpioinit(); + stm32_clockconfig(); + stm32_lowsetup(); + stm32_gpioinit(); showprogress('A'); /* Clear .bss. We'll do this inline (vs. calling memset) just to be @@ -202,13 +202,13 @@ void __start(void) */ #ifdef CONFIG_BUILD_PROTECTED - stm32wl5_userspace(); + stm32_userspace(); showprogress('E'); #endif /* Initialize onboard resources */ - stm32wl5_board_initialize(); + stm32_board_initialize(); showprogress('F'); /* Then start NuttX */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.h b/arch/arm/src/stm32wl5/stm32wl5_start.h index b36f7600b60..9d9a6676f5a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.h +++ b/arch/arm/src/stm32wl5/stm32wl5_start.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. This @@ -42,6 +42,6 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_START_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 9ecd2811a6e..3ca352fb788 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -41,7 +41,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "stm32wl5_gpio.h" #include "stm32wl5_tim.h" @@ -209,10 +209,10 @@ /* TIM Device Structure */ -struct stm32wl5_tim_priv_s +struct stm32_tim_priv_s { - const struct stm32wl5_tim_ops_s *ops; - enum stm32wl5_tim_mode_e mode; + const struct stm32_tim_ops_s *ops; + enum stm32_tim_mode_e mode; uint32_t base; /* TIMn base address */ }; @@ -222,179 +222,179 @@ struct stm32wl5_tim_priv_s /* Register helpers */ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value); -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits); -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset); -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value); /* Timer helpers */ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev); +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(struct stm32_tim_dev_s *dev); #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ defined(HAVE_TIM3_GPIOCONFIG) || defined(HAVE_TIM4_GPIOCONFIG) || \ defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode); +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode); #endif /* Timer methods */ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq); -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev); -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev); +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period); -static uint32_t stm32wl5_tim_getperiod(struct stm32wl5_tim_dev_s *dev); -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev); -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static uint32_t stm32_tim_getperiod(struct stm32_tim_dev_s *dev); +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, + enum stm32_tim_channel_e mode); +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel); -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source); -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source); -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source); /**************************************************************************** * Private Data ****************************************************************************/ -static const struct stm32wl5_tim_ops_s stm32wl5_tim_ops = +static const struct stm32_tim_ops_s stm32_tim_ops = { - .enable = stm32wl5_tim_enable, - .disable = stm32wl5_tim_disable, - .setmode = stm32wl5_tim_setmode, - .setclock = stm32wl5_tim_setclock, - .getclock = stm32wl5_tim_getclock, - .setperiod = stm32wl5_tim_setperiod, - .getperiod = stm32wl5_tim_getperiod, - .getcounter = stm32wl5_tim_getcounter, - .setchannel = stm32wl5_tim_setchannel, - .setcompare = stm32wl5_tim_setcompare, - .getcapture = stm32wl5_tim_getcapture, - .setisr = stm32wl5_tim_setisr, - .enableint = stm32wl5_tim_enableint, - .disableint = stm32wl5_tim_disableint, - .ackint = stm32wl5_tim_ackint, - .checkint = stm32wl5_tim_checkint, + .enable = stm32_tim_enable, + .disable = stm32_tim_disable, + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .getclock = stm32_tim_getclock, + .setperiod = stm32_tim_setperiod, + .getperiod = stm32_tim_getperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, }; #ifdef CONFIG_STM32WL5_TIM1 -struct stm32wl5_tim_priv_s stm32wl5_tim1_priv = +struct stm32_tim_priv_s stm32_tim1_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM1_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM2 -struct stm32wl5_tim_priv_s stm32wl5_tim2_priv = +struct stm32_tim_priv_s stm32_tim2_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM2_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM3 -struct stm32wl5_tim_priv_s stm32wl5_tim3_priv = +struct stm32_tim_priv_s stm32_tim3_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM3_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM4 -struct stm32wl5_tim_priv_s stm32wl5_tim4_priv = +struct stm32_tim_priv_s stm32_tim4_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM4_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM5 -struct stm32wl5_tim_priv_s stm32wl5_tim5_priv = +struct stm32_tim_priv_s stm32_tim5_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM5_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM6 -struct stm32wl5_tim_priv_s stm32wl5_tim6_priv = +struct stm32_tim_priv_s stm32_tim6_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM6_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM7 -struct stm32wl5_tim_priv_s stm32wl5_tim7_priv = +struct stm32_tim_priv_s stm32_tim7_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM7_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM8 -struct stm32wl5_tim_priv_s stm32wl5_tim8_priv = +struct stm32_tim_priv_s stm32_tim8_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM8_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM15 -struct stm32wl5_tim_priv_s stm32wl5_tim15_priv = +struct stm32_tim_priv_s stm32_tim15_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM15_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM16 -struct stm32wl5_tim_priv_s stm32wl5_tim16_priv = +struct stm32_tim_priv_s stm32_tim16_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM16_BASE, }; #endif #ifdef CONFIG_STM32WL5_TIM17 -struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = +struct stm32_tim_priv_s stm32_tim17_priv = { - .ops = &stm32wl5_tim_ops, + .ops = &stm32_tim_ops, .mode = STM32_TIM_MODE_UNUSED, .base = STM32_TIM17_BASE, }; @@ -405,51 +405,51 @@ struct stm32wl5_tim_priv_s stm32wl5_tim17_priv = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_getreg16 + * Name: stm32_getreg16 * * Description: * Get a 16-bit register value by offset * ****************************************************************************/ -static inline uint16_t stm32wl5_getreg16(struct stm32wl5_tim_dev_s *dev, +static inline uint16_t stm32_getreg16(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg16 + * Name: stm32_putreg16 * * Description: * Put a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_putreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) { - putreg16(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_modifyreg16 + * Name: stm32_modifyreg16 * * Description: * Modify a 16-bit register value by offset * ****************************************************************************/ -static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_modifyreg16(struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits) { - modifyreg16(((struct stm32wl5_tim_priv_s *)dev)->base + offset, clearbits, + modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } /**************************************************************************** - * Name: stm32wl5_getreg32 + * Name: stm32_getreg32 * * Description: * Get a 32-bit register value by offset. This applies only for the @@ -457,14 +457,14 @@ static inline void stm32wl5_modifyreg16(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, +static inline uint32_t stm32_getreg32(struct stm32_tim_dev_s *dev, uint8_t offset) { - return getreg32(((struct stm32wl5_tim_priv_s *)dev)->base + offset); + return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_putreg32 + * Name: stm32_putreg32 * * Description: * Put a 32-bit register value by offset. This applies only for the @@ -472,48 +472,48 @@ static inline uint32_t stm32wl5_getreg32(struct stm32wl5_tim_dev_s *dev, * ****************************************************************************/ -static inline void stm32wl5_putreg32(struct stm32wl5_tim_dev_s *dev, +static inline void stm32_putreg32(struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) { - putreg32(value, ((struct stm32wl5_tim_priv_s *)dev)->base + offset); + putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } /**************************************************************************** - * Name: stm32wl5_tim_reload_counter + * Name: stm32_tim_reload_counter ****************************************************************************/ -static void stm32wl5_tim_reload_counter(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reload_counter(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_EGR_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_EGR_OFFSET); val |= GTIM_EGR_UG; - stm32wl5_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_EGR_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_enable + * Name: stm32_tim_enable ****************************************************************************/ -static void stm32wl5_tim_enable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_enable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val |= GTIM_CR1_CEN; - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_disable + * Name: stm32_tim_disable ****************************************************************************/ -static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_disable(struct stm32_tim_dev_s *dev) { - uint16_t val = stm32wl5_getreg16(dev, STM32_GTIM_CR1_OFFSET); + uint16_t val = stm32_getreg16(dev, STM32_GTIM_CR1_OFFSET); val &= ~GTIM_CR1_CEN; - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); } /**************************************************************************** - * Name: stm32wl5_tim_reset + * Name: stm32_tim_reset * * Description: * Reset timer into system default state, but do not affect output/input @@ -521,14 +521,14 @@ static void stm32wl5_tim_disable(struct stm32wl5_tim_dev_s *dev) * ****************************************************************************/ -static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) +static void stm32_tim_reset(struct stm32_tim_dev_s *dev) { - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; - stm32wl5_tim_disable(dev); + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_DISABLED; + stm32_tim_disable(dev); } /**************************************************************************** - * Name: stm32wl5_tim_gpioconfig + * Name: stm32_tim_gpioconfig ****************************************************************************/ #if defined(HAVE_TIM1_GPIOCONFIG) || defined(HAVE_TIM2_GPIOCONFIG) || \ @@ -536,28 +536,28 @@ static void stm32wl5_tim_reset(struct stm32wl5_tim_dev_s *dev) defined(HAVE_TIM5_GPIOCONFIG) || defined(HAVE_TIM8_GPIOCONFIG) || \ defined(HAVE_TIM15_GPIOCONFIG) || defined(HAVE_TIM16_GPIOCONFIG) || \ defined(HAVE_TIM17_GPIOCONFIG) -static void stm32wl5_tim_gpioconfig(uint32_t cfg, - enum stm32wl5_tim_channel_e mode) +static void stm32_tim_gpioconfig(uint32_t cfg, + enum stm32_tim_channel_e mode) { /* TODO: Add support for input capture and bipolar dual outputs for TIM8 */ if (mode & STM32_TIM_CH_MODE_MASK) { - stm32wl5_configgpio(cfg); + stm32_configgpio(cfg); } else { - stm32wl5_unconfiggpio(cfg); + stm32_unconfiggpio(cfg); } } #endif /**************************************************************************** - * Name: stm32wl5_tim_setmode + * Name: stm32_tim_setmode ****************************************************************************/ -static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode) +static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode) { uint16_t val = GTIM_CR1_CEN | GTIM_CR1_ARPE; @@ -568,10 +568,10 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -611,16 +611,16 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, return -EINVAL; } - stm32wl5_tim_reload_counter(dev); - stm32wl5_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); #if STM32_NATIM > 0 /* Advanced registers require Main Output Enable */ - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) { - stm32wl5_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } #endif @@ -629,10 +629,10 @@ static int stm32wl5_tim_setmode(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setclock + * Name: stm32_tim_setclock ****************************************************************************/ -static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) { uint32_t freqin; @@ -644,7 +644,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, if (freq == 0) { - stm32wl5_tim_disable(dev); + stm32_tim_disable(dev); return 0; } @@ -654,7 +654,7 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 case STM32_TIM1_BASE: @@ -747,17 +747,17 @@ static int stm32wl5_tim_setclock(struct stm32wl5_tim_dev_s *dev, prescaler = 0xffff; } - stm32wl5_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); - stm32wl5_tim_enable(dev); + stm32_putreg16(dev, STM32_GTIM_PSC_OFFSET, prescaler); + stm32_tim_enable(dev); return prescaler; } /**************************************************************************** - * Name: stm32wl5_tim_getclock + * Name: stm32_tim_getclock ****************************************************************************/ -static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) { uint32_t freqin; uint32_t clock; @@ -769,7 +769,7 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) * must be defined in the board.h header file. */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 case STM32_TIM1_BASE: @@ -839,46 +839,46 @@ static uint32_t stm32wl5_tim_getclock(struct stm32wl5_tim_dev_s *dev) /* From chip datasheet, at page 1179. */ - clock = freqin / (stm32wl5_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); + clock = freqin / (stm32_getreg16(dev, STM32_GTIM_PSC_OFFSET) + 1); return clock; } /**************************************************************************** - * Name: stm32wl5_tim_setperiod + * Name: stm32_tim_setperiod ****************************************************************************/ -static void stm32wl5_tim_setperiod(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_setperiod(struct stm32_tim_dev_s *dev, uint32_t period) { DEBUGASSERT(dev != NULL); - stm32wl5_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); + stm32_putreg32(dev, STM32_GTIM_ARR_OFFSET, period); } /**************************************************************************** - * Name: stm32wl5_tim_getperiod + * Name: stm32_tim_getperiod ****************************************************************************/ -static uint32_t stm32wl5_tim_getperiod (struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getperiod (struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - return stm32wl5_getreg32 (dev, STM32_GTIM_ARR_OFFSET); + return stm32_getreg32 (dev, STM32_GTIM_ARR_OFFSET); } /**************************************************************************** - * Name: stm32wl5_tim_getcounter + * Name: stm32_tim_getcounter ****************************************************************************/ -static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) +static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); - uint32_t counter = stm32wl5_getreg32(dev, STM32_GTIM_CNT_OFFSET); + uint32_t counter = stm32_getreg32(dev, STM32_GTIM_CNT_OFFSET); /* In datasheet page 988, there is a useless bit named UIFCPY in TIMx_CNT. * reset it it result when not TIM2 or TIM5. */ #if defined(CONFIG_STM32WL5_TIM2) || defined(CONFIG_STM32WL5_TIM5) - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM2 case STM32_TIM2_BASE: @@ -897,12 +897,12 @@ static uint32_t stm32wl5_tim_getcounter(struct stm32wl5_tim_dev_s *dev) } /**************************************************************************** - * Name: stm32wl5_tim_setchannel + * Name: stm32_tim_setchannel ****************************************************************************/ -static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode) + enum stm32_tim_channel_e mode) { uint16_t ccmr_orig = 0; uint16_t ccmr_val = 0; @@ -921,7 +921,7 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, /* Assume that channel is disabled and polarity is active high */ - ccer_val = stm32wl5_getreg16(dev, STM32_GTIM_CCER_OFFSET); + ccer_val = stm32_getreg16(dev, STM32_GTIM_CCER_OFFSET); ccer_val &= ~((GTIM_CCER_CC1P | GTIM_CCER_CC1E) << GTIM_CCER_CCXBASE(channel)); @@ -930,10 +930,10 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, */ #if STM32_NBTIM > 0 - if (((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM6_BASE + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE #endif #if STM32_NBTIM > 1 - || ((struct stm32wl5_tim_priv_s *)dev)->base == STM32_TIM7_BASE + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE #endif #if STM32_NBTIM > 0 ) @@ -979,15 +979,15 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, ccmr_offset = STM32_GTIM_CCMR2_OFFSET; } - ccmr_orig = stm32wl5_getreg16(dev, ccmr_offset); + ccmr_orig = stm32_getreg16(dev, ccmr_offset); ccmr_orig &= ~ccmr_mask; ccmr_orig |= ccmr_val; - stm32wl5_putreg16(dev, ccmr_offset, ccmr_orig); - stm32wl5_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); + stm32_putreg16(dev, ccmr_offset, ccmr_orig); + stm32_putreg16(dev, STM32_GTIM_CCER_OFFSET, ccer_val); /* set GPIO */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 case STM32_TIM1_BASE: @@ -995,25 +995,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM1_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break; #endif #if defined(GPIO_TIM1_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break; #endif #if defined(GPIO_TIM1_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break; #endif #if defined(GPIO_TIM1_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break; #endif @@ -1028,25 +1028,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM2_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break; #endif #if defined(GPIO_TIM2_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break; #endif #if defined(GPIO_TIM2_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break; #endif #if defined(GPIO_TIM2_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break; #endif @@ -1061,25 +1061,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM3_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break; #endif #if defined(GPIO_TIM3_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break; #endif #if defined(GPIO_TIM3_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break; #endif #if defined(GPIO_TIM3_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break; #endif @@ -1094,24 +1094,24 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM4_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break; #endif #if defined(GPIO_TIM4_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break; #endif #if defined(GPIO_TIM4_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break; #endif #if defined(GPIO_TIM4_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break; #endif @@ -1126,25 +1126,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM5_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break; #endif #if defined(GPIO_TIM5_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break; #endif #if defined(GPIO_TIM5_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break; #endif #if defined(GPIO_TIM5_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break; #endif @@ -1159,25 +1159,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM8_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break; #endif #if defined(GPIO_TIM8_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break; #endif #if defined(GPIO_TIM8_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break; #endif #if defined(GPIO_TIM8_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break; #endif @@ -1192,25 +1192,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM15_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH1OUT, mode); break; #endif #if defined(GPIO_TIM15_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH2OUT, mode); break; #endif #if defined(GPIO_TIM15_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH3OUT, mode); break; #endif #if defined(GPIO_TIM15_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM15_CH4OUT, mode); break; #endif @@ -1225,25 +1225,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM16_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH1OUT, mode); break; #endif #if defined(GPIO_TIM16_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH2OUT, mode); break; #endif #if defined(GPIO_TIM16_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH3OUT, mode); break; #endif #if defined(GPIO_TIM16_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM16_CH4OUT, mode); break; #endif @@ -1258,25 +1258,25 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, { #if defined(GPIO_TIM17_CH1OUT) case 0: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH1OUT, mode); break; #endif #if defined(GPIO_TIM17_CH2OUT) case 1: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH2OUT, mode); break; #endif #if defined(GPIO_TIM17_CH3OUT) case 2: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH3OUT, mode); break; #endif #if defined(GPIO_TIM17_CH4OUT) case 3: - stm32wl5_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); + stm32_tim_gpioconfig(GPIO_TIM17_CH4OUT, mode); break; #endif @@ -1294,10 +1294,10 @@ static int stm32wl5_tim_setchannel(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_setcompare + * Name: stm32_tim_setcompare ****************************************************************************/ -static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setcompare(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { DEBUGASSERT(dev != NULL); @@ -1305,19 +1305,19 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - stm32wl5_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR1_OFFSET, compare); break; case 2: - stm32wl5_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR2_OFFSET, compare); break; case 3: - stm32wl5_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR3_OFFSET, compare); break; case 4: - stm32wl5_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); + stm32_putreg32(dev, STM32_GTIM_CCR4_OFFSET, compare); break; default: @@ -1328,10 +1328,10 @@ static int stm32wl5_tim_setcompare(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_getcapture + * Name: stm32_tim_getcapture ****************************************************************************/ -static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_getcapture(struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1339,26 +1339,26 @@ static int stm32wl5_tim_getcapture(struct stm32wl5_tim_dev_s *dev, switch (channel) { case 1: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR1_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); case 2: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR2_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); case 3: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR3_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); case 4: - return stm32wl5_getreg32(dev, STM32_GTIM_CCR4_OFFSET); + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); } return -EINVAL; } /**************************************************************************** - * Name: stm32wl5_tim_setisr + * Name: stm32_tim_setisr ****************************************************************************/ -static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source) { int vectorno; @@ -1366,7 +1366,7 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, DEBUGASSERT(dev != NULL); DEBUGASSERT(source == 0); - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 case STM32_TIM1_BASE: @@ -1454,44 +1454,44 @@ static int stm32wl5_tim_setisr(struct stm32wl5_tim_dev_s *dev, } /**************************************************************************** - * Name: stm32wl5_tim_enableint + * Name: stm32_tim_enableint ****************************************************************************/ -static void stm32wl5_tim_enableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_enableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, 0, GTIM_DIER_UIE); } /**************************************************************************** - * Name: stm32wl5_tim_disableint + * Name: stm32_tim_disableint ****************************************************************************/ -static void stm32wl5_tim_disableint(struct stm32wl5_tim_dev_s *dev, +static void stm32_tim_disableint(struct stm32_tim_dev_s *dev, int source) { DEBUGASSERT(dev != NULL); - stm32wl5_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); + stm32_modifyreg16(dev, STM32_GTIM_DIER_OFFSET, GTIM_DIER_UIE, 0); } /**************************************************************************** - * Name: stm32wl5_tim_ackint + * Name: stm32_tim_ackint ****************************************************************************/ -static void stm32wl5_tim_ackint(struct stm32wl5_tim_dev_s *dev, int source) +static void stm32_tim_ackint(struct stm32_tim_dev_s *dev, int source) { - stm32wl5_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); + stm32_putreg16(dev, STM32_GTIM_SR_OFFSET, ~GTIM_SR_UIF); } /**************************************************************************** - * Name: stm32wl5_tim_checkint + * Name: stm32_tim_checkint ****************************************************************************/ -static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, +static int stm32_tim_checkint(struct stm32_tim_dev_s *dev, int source) { - uint16_t regval = stm32wl5_getreg16(dev, STM32_GTIM_SR_OFFSET); + uint16_t regval = stm32_getreg16(dev, STM32_GTIM_SR_OFFSET); return (regval & GTIM_SR_UIF) ? 1 : 0; } @@ -1500,12 +1500,12 @@ static int stm32wl5_tim_checkint(struct stm32wl5_tim_dev_s *dev, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_tim_init + * Name: stm32_tim_init ****************************************************************************/ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) +struct stm32_tim_dev_s *stm32_tim_init(int timer) { - struct stm32wl5_tim_dev_s *dev = NULL; + struct stm32_tim_dev_s *dev = NULL; /* Get structure and enable power */ @@ -1513,76 +1513,76 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) { #ifdef CONFIG_STM32WL5_TIM1 case 1: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim1_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif #ifdef CONFIG_STM32WL5_TIM2 case 2: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim2_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif #ifdef CONFIG_STM32WL5_TIM3 case 3: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim3_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif #ifdef CONFIG_STM32WL5_TIM4 case 4: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim4_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif #ifdef CONFIG_STM32WL5_TIM5 case 5: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim5_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif #ifdef CONFIG_STM32WL5_TIM6 case 6: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim6_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif #ifdef CONFIG_STM32WL5_TIM7 case 7: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim7_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif #ifdef CONFIG_STM32WL5_TIM8 case 8: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim8_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif #ifdef CONFIG_STM32WL5_TIM15 case 15: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim15_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif #ifdef CONFIG_STM32WL5_TIM16 case 16: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim16_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif #ifdef CONFIG_STM32WL5_TIM17 case 17: - dev = (struct stm32wl5_tim_dev_s *)&stm32wl5_tim17_priv; + dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); break; #endif @@ -1593,30 +1593,30 @@ struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer) /* Is device already allocated */ - if (((struct stm32wl5_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) + if (((struct stm32_tim_priv_s *)dev)->mode != STM32_TIM_MODE_UNUSED) { return NULL; } - stm32wl5_tim_reset(dev); + stm32_tim_reset(dev); return dev; } /**************************************************************************** - * Name: stm32wl5_tim_deinit + * Name: stm32_tim_deinit * * TODO: Detach interrupts, and close down all TIM Channels * ****************************************************************************/ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) +int stm32_tim_deinit(struct stm32_tim_dev_s *dev) { DEBUGASSERT(dev != NULL); /* Disable power */ - switch (((struct stm32wl5_tim_priv_s *)dev)->base) + switch (((struct stm32_tim_priv_s *)dev)->base) { #ifdef CONFIG_STM32WL5_TIM1 case STM32_TIM1_BASE: @@ -1689,7 +1689,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev) /* Mark it as free */ - ((struct stm32wl5_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; + ((struct stm32_tim_priv_s *)dev)->mode = STM32_TIM_MODE_UNUSED; return OK; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.h b/arch/arm/src/stm32wl5/stm32wl5_tim.h index 53292055355..10f16b1695e 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.h +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.h @@ -72,14 +72,14 @@ extern "C" /* TIM Device Structure */ -struct stm32wl5_tim_dev_s +struct stm32_tim_dev_s { - struct stm32wl5_tim_ops_s *ops; + struct stm32_tim_ops_s *ops; }; /* TIM Modes of Operation */ -enum stm32wl5_tim_mode_e +enum stm32_tim_mode_e { STM32_TIM_MODE_UNUSED = -1, @@ -116,7 +116,7 @@ enum stm32wl5_tim_mode_e /* TIM Channel Modes */ -enum stm32wl5_tim_channel_e +enum stm32_tim_channel_e { STM32_TIM_CH_DISABLED = 0x00, @@ -139,36 +139,36 @@ enum stm32wl5_tim_channel_e /* TIM Operations */ -struct stm32wl5_tim_ops_s +struct stm32_tim_ops_s { /* Basic Timers */ - void (*enable)(struct stm32wl5_tim_dev_s *dev); - void (*disable)(struct stm32wl5_tim_dev_s *dev); - int (*setmode)(struct stm32wl5_tim_dev_s *dev, - enum stm32wl5_tim_mode_e mode); - int (*setclock)(struct stm32wl5_tim_dev_s *dev, uint32_t freq); - uint32_t (*getclock)(struct stm32wl5_tim_dev_s *dev); - void (*setperiod)(struct stm32wl5_tim_dev_s *dev, uint32_t period); - uint32_t (*getperiod)(struct stm32wl5_tim_dev_s *dev); - uint32_t (*getcounter)(struct stm32wl5_tim_dev_s *dev); + void (*enable)(struct stm32_tim_dev_s *dev); + void (*disable)(struct stm32_tim_dev_s *dev); + int (*setmode)(struct stm32_tim_dev_s *dev, + enum stm32_tim_mode_e mode); + int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq); + uint32_t (*getclock)(struct stm32_tim_dev_s *dev); + void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getperiod)(struct stm32_tim_dev_s *dev); + uint32_t (*getcounter)(struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, - enum stm32wl5_tim_channel_e mode); - int (*setcompare)(struct stm32wl5_tim_dev_s *dev, uint8_t channel, + int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel, + enum stm32_tim_channel_e mode); + int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); - int (*getcapture)(struct stm32wl5_tim_dev_s *dev, uint8_t channel); + int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(struct stm32wl5_tim_dev_s *dev, + int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg, int source); - void (*enableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*disableint)(struct stm32wl5_tim_dev_s *dev, int source); - void (*ackint)(struct stm32wl5_tim_dev_s *dev, int source); - int (*checkint)(struct stm32wl5_tim_dev_s *dev, int source); + void (*enableint)(struct stm32_tim_dev_s *dev, int source); + void (*disableint)(struct stm32_tim_dev_s *dev, int source); + void (*ackint)(struct stm32_tim_dev_s *dev, int source); + int (*checkint)(struct stm32_tim_dev_s *dev, int source); }; /**************************************************************************** @@ -177,14 +177,14 @@ struct stm32wl5_tim_ops_s /* Power-up timer and get its structure */ -struct stm32wl5_tim_dev_s *stm32wl5_tim_init(int timer); +struct stm32_tim_dev_s *stm32_tim_init(int timer); /* Power-down timer, mark it as unused */ -int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); +int stm32_tim_deinit(struct stm32_tim_dev_s *dev); /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -202,7 +202,7 @@ int stm32wl5_tim_deinit(struct stm32wl5_tim_dev_s *dev); ****************************************************************************/ #ifdef CONFIG_TIMER -int stm32wl5_timer_initialize(const char *devpath, int timer); +int stm32_timer_initialize(const char *devpath, int timer); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index 10c2a3c3243..d32824d14ad 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -73,10 +73,10 @@ * timer_lowerhalf_s structure. */ -struct stm32wl5_lowerhalf_s +struct stm32_lowerhalf_s { const struct timer_ops_s *ops; /* Lower half operations */ - struct stm32wl5_tim_dev_s *tim; /* stm32 timer driver */ + struct stm32_tim_dev_s *tim; /* stm32 timer driver */ tccb_t callback; /* Current upper half interrupt callback */ void *arg; /* Argument passed to upper half callback */ bool started; /* True: Timer has been started */ @@ -89,17 +89,17 @@ struct stm32wl5_lowerhalf_s /* Interrupt handling *******************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg); +static int stm32_timer_handler(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower); -static int stm32wl5_stop(struct timer_lowerhalf_s *lower); -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_start(struct timer_lowerhalf_s *lower); +static int stm32_stop(struct timer_lowerhalf_s *lower); +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status); -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout); -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg); /**************************************************************************** @@ -110,16 +110,16 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, static const struct timer_ops_s g_timer_ops = { - .start = stm32wl5_start, - .stop = stm32wl5_stop, - .getstatus = stm32wl5_getstatus, - .settimeout = stm32wl5_settimeout, - .setcallback = stm32wl5_setcallback, + .start = stm32_start, + .stop = stm32_stop, + .getstatus = stm32_getstatus, + .settimeout = stm32_settimeout, + .setcallback = stm32_setcallback, .ioctl = NULL, }; #ifdef CONFIG_STM32WL5_TIM1 -static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = +static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM1_RES, @@ -127,7 +127,7 @@ static struct stm32wl5_lowerhalf_s g_tim1_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM2 -static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = +static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM2_RES, @@ -135,7 +135,7 @@ static struct stm32wl5_lowerhalf_s g_tim2_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM3 -static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = +static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM3_RES, @@ -143,7 +143,7 @@ static struct stm32wl5_lowerhalf_s g_tim3_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM4 -static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = +static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM4_RES, @@ -151,7 +151,7 @@ static struct stm32wl5_lowerhalf_s g_tim4_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM5 -static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = +static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM5_RES, @@ -159,7 +159,7 @@ static struct stm32wl5_lowerhalf_s g_tim5_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM6 -static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = +static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM6_RES, @@ -167,7 +167,7 @@ static struct stm32wl5_lowerhalf_s g_tim6_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM7 -static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = +static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM7_RES, @@ -175,7 +175,7 @@ static struct stm32wl5_lowerhalf_s g_tim7_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM8 -static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = +static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM8_RES, @@ -183,7 +183,7 @@ static struct stm32wl5_lowerhalf_s g_tim8_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM15 -static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = +static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM15_RES, @@ -191,7 +191,7 @@ static struct stm32wl5_lowerhalf_s g_tim15_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM16 -static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = +static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM16_RES, @@ -199,7 +199,7 @@ static struct stm32wl5_lowerhalf_s g_tim16_lowerhalf = #endif #ifdef CONFIG_STM32WL5_TIM17 -static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = +static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, .resolution = STM32_TIM17_RES, @@ -211,7 +211,7 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_handler + * Name: stm32_timer_handler * * Description: * timer interrupt handler @@ -222,10 +222,10 @@ static struct stm32wl5_lowerhalf_s g_tim17_lowerhalf = * ****************************************************************************/ -static int stm32wl5_timer_handler(int irq, void *context, void *arg) +static int stm32_timer_handler(int irq, void *context, void *arg) { - struct stm32wl5_lowerhalf_s *lower = - (struct stm32wl5_lowerhalf_s *)arg; + struct stm32_lowerhalf_s *lower = + (struct stm32_lowerhalf_s *)arg; uint32_t next_interval_us = 0; STM32_TIM_ACKINT(lower->tim, 0); @@ -239,14 +239,14 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) } else { - stm32wl5_stop((struct timer_lowerhalf_s *)lower); + stm32_stop((struct timer_lowerhalf_s *)lower); } return OK; } /**************************************************************************** - * Name: stm32wl5_start + * Name: stm32_start * * Description: * Start the timer, resetting the time to the current timeout, @@ -260,10 +260,10 @@ static int stm32wl5_timer_handler(int irq, void *context, void *arg) * ****************************************************************************/ -static int stm32wl5_start(struct timer_lowerhalf_s *lower) +static int stm32_start(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (!priv->started) { @@ -271,7 +271,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) if (priv->callback != NULL) { - STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } @@ -285,7 +285,7 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_stop + * Name: stm32_stop * * Description: * Stop the timer @@ -299,10 +299,10 @@ static int stm32wl5_start(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_stop(struct timer_lowerhalf_s *lower) +static int stm32_stop(struct timer_lowerhalf_s *lower) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; if (priv->started) { @@ -319,7 +319,7 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) } /**************************************************************************** - * Name: stm32wl5_getstatus + * Name: stm32_getstatus * * Description: * get timer status @@ -334,11 +334,11 @@ static int stm32wl5_stop(struct timer_lowerhalf_s *lower) * ****************************************************************************/ -static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, +static int stm32_getstatus(struct timer_lowerhalf_s *lower, struct timer_status_s *status) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; uint32_t timeout; uint32_t clock; @@ -386,7 +386,7 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wl5_settimeout + * Name: stm32_settimeout * * Description: * Set a new timeout value (and reset the timer) @@ -401,11 +401,11 @@ static int stm32wl5_getstatus(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, +static int stm32_settimeout(struct timer_lowerhalf_s *lower, uint32_t timeout) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; uint64_t maxtimeout; if (priv->started) @@ -430,7 +430,7 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, } /**************************************************************************** - * Name: stm32wl5_sethandler + * Name: stm32_sethandler * * Description: * Call this user provided timeout handler. @@ -449,11 +449,11 @@ static int stm32wl5_settimeout(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, +static void stm32_setcallback(struct timer_lowerhalf_s *lower, tccb_t callback, void *arg) { - struct stm32wl5_lowerhalf_s *priv = - (struct stm32wl5_lowerhalf_s *)lower; + struct stm32_lowerhalf_s *priv = + (struct stm32_lowerhalf_s *)lower; irqstate_t flags = enter_critical_section(); /* Save the new callback */ @@ -463,7 +463,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, if (callback != NULL && priv->started) { - STM32_TIM_SETISR(priv->tim, stm32wl5_timer_handler, priv, 0); + STM32_TIM_SETISR(priv->tim, stm32_timer_handler, priv, 0); STM32_TIM_ENABLEINT(priv->tim, 0); } else @@ -480,7 +480,7 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_timer_initialize + * Name: stm32_timer_initialize * * Description: * Bind the configuration timer to a timer lower half instance and @@ -497,9 +497,9 @@ static void stm32wl5_setcallback(struct timer_lowerhalf_s *lower, * ****************************************************************************/ -int stm32wl5_timer_initialize(const char *devpath, int timer) +int stm32_timer_initialize(const char *devpath, int timer) { - struct stm32wl5_lowerhalf_s *lower; + struct stm32_lowerhalf_s *lower; switch (timer) { @@ -576,7 +576,7 @@ int stm32wl5_timer_initialize(const char *devpath, int timer) lower->started = false; lower->callback = NULL; - lower->tim = stm32wl5_tim_init(timer); + lower->tim = stm32_tim_init(timer); if (lower->tim == NULL) { diff --git a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c index 070fbc8b745..393417ca3d9 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_timerisr.c +++ b/arch/arm/src/stm32wl5/stm32wl5_timerisr.c @@ -38,7 +38,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" /**************************************************************************** * Pre-processor Definitions @@ -80,7 +80,7 @@ ****************************************************************************/ /**************************************************************************** - * Function: stm32wl5_timerisr + * Function: stm32_timerisr * * Description: * The timer ISR will perform a variety of services for various portions @@ -88,7 +88,7 @@ * ****************************************************************************/ -static int stm32wl5_timerisr(int irq, uint32_t *regs, void *arg) +static int stm32_timerisr(int irq, uint32_t *regs, void *arg) { /* Process timer interrupt */ @@ -138,7 +138,7 @@ void up_timer_initialize(void) /* Attach the timer interrupt vector */ - (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32wl5_timerisr, NULL); + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL); /* Enable SysTick interrupts */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_uart.h b/arch/arm/src/stm32wl5/stm32wl5_uart.h index 8abf47c83c5..00f859e2f68 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uart.h @@ -202,7 +202,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_serial_dma_poll + * Name: stm32_serial_dma_poll * * Description: * Must be called periodically if any STM32 UART is configured for DMA. @@ -215,7 +215,7 @@ extern "C" ****************************************************************************/ #ifdef SERIAL_HAVE_DMA -void stm32wl5_serial_dma_poll(void); +void stm32_serial_dma_poll(void); #endif #undef EXTERN diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.c b/arch/arm/src/stm32wl5/stm32wl5_uid.c index 311458d7adb..1bd3fa1ce94 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.c +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.c @@ -50,7 +50,7 @@ * Public Functions ****************************************************************************/ -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]) +void stm32_get_uniqueid(uint8_t uniqueid[12]) { int i; diff --git a/arch/arm/src/stm32wl5/stm32wl5_uid.h b/arch/arm/src/stm32wl5/stm32wl5_uid.h index 6992f84b9c3..3735cf07bd1 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uid.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uid.h @@ -48,6 +48,6 @@ * Public Function Prototypes ****************************************************************************/ -void stm32wl5_get_uniqueid(uint8_t uniqueid[12]); +void stm32_get_uniqueid(uint8_t uniqueid[12]); #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_UID_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.c b/arch/arm/src/stm32wl5/stm32wl5_userspace.c index 345a6f0f457..23a8bfe9bba 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.c +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.c @@ -41,7 +41,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -51,7 +51,7 @@ * ****************************************************************************/ -void stm32wl5_userspace(void) +void stm32_userspace(void) { uint8_t *src; uint8_t *dest; @@ -87,7 +87,7 @@ void stm32wl5_userspace(void) /* Configure the MPU to permit user-space access to its FLASH and RAM */ - stm32wl5_mpuinitialize(); + stm32_mpuinitialize(); } #endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_userspace.h b/arch/arm/src/stm32wl5/stm32wl5_userspace.h index 3ca2fdf521c..01d88f7596c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_userspace.h +++ b/arch/arm/src/stm32wl5/stm32wl5_userspace.h @@ -34,7 +34,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_userspace + * Name: stm32_userspace * * Description: * For the case of the separate user-/kernel-space build, perform whatever @@ -45,7 +45,7 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_PROTECTED -void stm32wl5_userspace(void); +void stm32_userspace(void); #endif #endif /* __ARCH_ARM_SRC_STM32WL5_STM32WL5_USERSPACE_H */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.c b/arch/arm/src/stm32wl5/stm32wl5_waste.c index 96f0e621cf3..c2da5213d4c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.c +++ b/arch/arm/src/stm32wl5/stm32wl5_waste.c @@ -38,7 +38,7 @@ uint32_t idle_wastecounter = 0; * Public Functions ****************************************************************************/ -void stm32wl5_waste(void) +void stm32_waste(void) { idle_wastecounter++; } diff --git a/arch/arm/src/stm32wl5/stm32wl5_waste.h b/arch/arm/src/stm32wl5/stm32wl5_waste.h index 348469b4982..f79b8b1f591 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_waste.h +++ b/arch/arm/src/stm32wl5/stm32wl5_waste.h @@ -46,7 +46,7 @@ extern "C" /* Waste CPU Time * - * stm32wl5_waste() is the logic that will be executed when portions of + * stm32_waste() is the logic that will be executed when portions of * kernel or user-app is polling some register or similar, waiting for * desired status. This time is wasted away. This function offers a measure * of badly written piece of software or some undesired behavior. At @@ -54,7 +54,7 @@ extern "C" * be used for other purposes (yet). */ -void stm32wl5_waste(void); +void stm32_waste(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h index b00acf8b0d2..83ebe454552 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/include/board.h @@ -231,7 +231,7 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -241,7 +241,7 @@ extern "C" * ****************************************************************************/ -void stm32wl5_board_initialize(void); +void stm32_board_initialize(void); #undef EXTERN #if defined(__cplusplus) diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h index c25831b622e..391e3847af7 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/nucleo-wl55jc.h @@ -31,7 +31,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions @@ -148,24 +148,24 @@ void board_leds_initialize(void); /**************************************************************************** - * Name: stm32wl5_flash_init + * Name: stm32_flash_init * * Description: * Initialize on-board FLASH partition table * ****************************************************************************/ -int stm32wl5_flash_init(void); +int stm32_flash_init(void); /**************************************************************************** - * Name: stm32wl5_spidev_initialize + * Name: stm32_spidev_initialize * * Description: * Initialize SPIs * ****************************************************************************/ -void stm32wl5_spidev_initialize(void); +void stm32_spidev_initialize(void); /**************************************************************************** * Name: ipcc_init diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c index b823f818470..1335387ce8d 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c @@ -47,7 +47,7 @@ #include #endif -#include +#include #include #include @@ -73,7 +73,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: stm32wl5_board_initialize + * Name: stm32_board_initialize * * Description: * All STM32WL5 architectures must provide the following entry point. @@ -83,7 +83,7 @@ * ****************************************************************************/ -void stm32wl5_board_initialize(void) +void stm32_board_initialize(void) { /* Configure on-board LEDs, which are always enabled */ @@ -109,7 +109,7 @@ void board_late_initialize(void) int ret; #if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) - stm32wl5_spidev_initialize(); + stm32_spidev_initialize(); #endif #if defined(CONFIG_LCD_SSD1680) && !defined(CONFIG_VIDEO_FB) @@ -161,10 +161,10 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_FLASH_MOUNT) /* Register partition table for on-board FLASH memory */ - ret = stm32wl5_flash_init(); + ret = stm32_flash_init(); if (ret < 0) { - syslog(LOG_ERR, "ERROR: stm32wl5_flash_init() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: stm32_flash_init() failed: %d\n", ret); } #endif @@ -181,7 +181,7 @@ void board_late_initialize(void) #if defined(CONFIG_ARCH_BOARD_ENABLE_CPU2) /* Start second CPU */ - stm32wl5_pwr_boot_c2(); + stm32_pwr_boot_c2(); #endif UNUSED(ret); @@ -203,7 +203,7 @@ int board_uniqueid(uint8_t *uniqueid) return -EINVAL; } - stm32wl5_get_uniqueid(uniqueid); + stm32_get_uniqueid(uniqueid); return OK; } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c index adf9448398c..1ef9e8a33d0 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_buttons.c @@ -57,10 +57,10 @@ uint32_t board_button_initialize(void) * also configured for the pin. */ - stm32wl5_configgpio(GPIO_BUTTON1); - stm32wl5_configgpio(GPIO_BUTTON2); + stm32_configgpio(GPIO_BUTTON1); + stm32_configgpio(GPIO_BUTTON2); #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - stm32wl5_configgpio(GPIO_BUTTON3); + stm32_configgpio(GPIO_BUTTON3); return 3; /* number of buttons */ #else return 2; /* number of buttons */ @@ -81,18 +81,18 @@ uint32_t board_buttons(void) state = 0; - if (stm32wl5_gpioread(GPIO_BUTTON1) == 0) + if (stm32_gpioread(GPIO_BUTTON1) == 0) { state |= BUTTON1_BIT; } - if (stm32wl5_gpioread(GPIO_BUTTON2) == 0) + if (stm32_gpioread(GPIO_BUTTON2) == 0) { state |= BUTTON2_BIT; } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ - if (stm32wl5_gpioread(GPIO_BUTTON3) == 0) + if (stm32_gpioread(GPIO_BUTTON3) == 0) { state |= BUTTON3_BIT; } @@ -130,20 +130,20 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) if (id == BOARD_BUTTON1) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON1, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON1, true, true, false, irqhandler, arg); } if (id == BOARD_BUTTON2) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON2, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON2, true, true, false, irqhandler, arg); } #ifndef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ if (id == BOARD_BUTTON3) { - ret = stm32wl5_gpiosetevent(GPIO_BUTTON3, true, true, false, + ret = stm32_gpiosetevent(GPIO_BUTTON3, true, true, false, irqhandler, arg); } #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c index 16b17248230..4ae514cd0c6 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_flash.c @@ -173,7 +173,7 @@ static const struct part_table part_table[] = * Public Functions ****************************************************************************/ -int stm32wl5_flash_init(void) +int stm32_flash_init(void) { struct mtd_dev_s *mtd; struct mtd_dev_s *mtd_part; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c index 8d6b8f1d913..de0cce3e3a1 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ipcc.c @@ -116,9 +116,9 @@ static int init_ipcc(int chan, size_t rxbuflen, size_t txbuflen) struct ipcc_lower_s *ipcc; int ret; - if ((ipcc = stm32wl5_ipcc_init(chan)) == NULL) + if ((ipcc = stm32_ipcc_init(chan)) == NULL) { - syslog(LOG_ERR, "ERROR: stm32wl5_ipcc_init(%d) failed\n", chan); + syslog(LOG_ERR, "ERROR: stm32_ipcc_init(%d) failed\n", chan); return -1; } diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c index a0a23318bfd..c276a1c52c0 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_leds.c @@ -35,7 +35,7 @@ #include "chip.h" #include "arm_internal.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include @@ -64,17 +64,17 @@ static void led_state(int state, unsigned int leds) { if (leds & BOARD_LED_BLUE_BIT) { - stm32wl5_gpiowrite(GPIO_LED_BLUE, state); + stm32_gpiowrite(GPIO_LED_BLUE, state); } if (leds & BOARD_LED_RED_BIT) { - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); } if (leds & BOARD_LED_GREEN_BIT) { - stm32wl5_gpiowrite(GPIO_LED_GREEN, state); + stm32_gpiowrite(GPIO_LED_GREEN, state); } } @@ -93,12 +93,12 @@ static int button3_led(int irq, void *context, void *arg) (void)arg; int state; - state = stm32wl5_gpioread(GPIO_LED_RED); + state = stm32_gpioread(GPIO_LED_RED); /* toggle state */ state = !state; - stm32wl5_gpiowrite(GPIO_LED_RED, state); + stm32_gpiowrite(GPIO_LED_RED, state); return 0; } #endif @@ -113,9 +113,9 @@ static int button3_led(int irq, void *context, void *arg) void board_leds_initialize(void) { - stm32wl5_configgpio(GPIO_LED_BLUE); - stm32wl5_configgpio(GPIO_LED_RED); - stm32wl5_configgpio(GPIO_LED_GREEN); + stm32_configgpio(GPIO_LED_BLUE); + stm32_configgpio(GPIO_LED_RED); + stm32_configgpio(GPIO_LED_GREEN); } /**************************************************************************** @@ -222,7 +222,7 @@ uint32_t board_userled_initialize(void) #ifdef CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ /* Configure B3 button to fire an interrupt on falling edge (on press) */ - stm32wl5_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); + stm32_gpiosetevent(GPIO_BUTTON3, false, true, false, button3_led, NULL); #endif return BOARD_NLEDS; diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c index 1e1275e2ce4..7299f52ba57 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "chip.h" -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) @@ -68,12 +68,12 @@ struct spi_dev_s *g_spi2; * ****************************************************************************/ -void weak_function stm32wl5_spidev_initialize(void) +void weak_function stm32_spidev_initialize(void) { #ifdef CONFIG_STM32WL5_SPI1 /* Configure SPI-based devices */ - g_spi1 = stm32wl5_spibus_initialize(1); + g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) { spierr("ERROR: FAILED to initialize SPI port 1\n"); @@ -82,15 +82,15 @@ void weak_function stm32wl5_spidev_initialize(void) #ifdef CONFIG_LCD_SSD1680 spiinfo("Preparing additional lines for SSD1680 device\n"); - stm32wl5_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ - stm32wl5_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_CS); /* SSD1680 chip select */ + stm32_configgpio(GPIO_SSD1680_CMD); /* SSD1680 data/!command */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ #endif #endif -#ifdef CONFIG_STM32_SPI2S2 +#ifdef CONFIG_STM32WL5_SPI2S2 /* Configure SPI-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -105,7 +105,7 @@ void weak_function stm32wl5_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32wl5_spibus_initialize()) are provided by common STM32 logic. + * stm32_spibus_initialize()) are provided by common STM32 logic. * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select @@ -114,9 +114,9 @@ void weak_function stm32wl5_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32wl5_spibus_initialize() in your low level + * 3. Add a calls to stm32_spibus_initialize() in your low level * application initialization logic - * 4. The handle returned by stm32wl5_spibus_initialize() may then be used + * 4. The handle returned by stm32_spibus_initialize() may then be used * to bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). @@ -124,7 +124,7 @@ void weak_function stm32wl5_spidev_initialize(void) ****************************************************************************/ #ifdef CONFIG_STM32WL5_SPI1 -void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : @@ -133,26 +133,26 @@ void stm32wl5_spi1select(struct spi_dev_s *dev, uint32_t devid, #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CS, !selected); + stm32_gpiowrite(GPIO_SSD1680_CS, !selected); } #endif #if defined(CONFIG_CAN_MCP2515) if (devid == SPIDEV_CANBUS(0)) { - stm32wl5_gpiowrite(GPIO_MCP2515_CS, !selected); + stm32_gpiowrite(GPIO_MCP2515_CS, !selected); } #endif #ifdef HAVE_MMCSD if (devid == SPIDEV_MMCSD(0)) { - stm32wl5_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); + stm32_gpiowrite(GPIO_SPI_CS_SD_CARD, !selected); } #endif } -uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) @@ -164,12 +164,12 @@ uint8_t stm32wl5_spi1status(struct spi_dev_s *dev, uint32_t devid) return 0; } -int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #if defined(CONFIG_LCD_SSD1680) if (devid == SPIDEV_DISPLAY(0)) { - stm32wl5_gpiowrite(GPIO_SSD1680_CMD, !cmd); + stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); } #endif @@ -179,76 +179,23 @@ int stm32wl5_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #ifdef CONFIG_STM32WL5_SPI2S2 -void stm32wl5_spi2s2select(struct spi_dev_s *dev, uint32_t devid, +void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); } -uint8_t stm32wl5_spi2s2status(struct spi_dev_s *dev, uint32_t devid) +uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -int stm32wl5_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -/**************************************************************************** - * Name: stm32_spi1cmddata - * - * Description: - * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) - * or command (false). This function must be provided by platform-specific - * logic. This is an implementation of the cmddata method of the SPI - * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). - * - * Input Parameters: - * - * spi - SPI device that controls the bus the device that requires the CMD/ - * DATA selection. - * devid - If there are multiple devices on the bus, this selects which one - * to select cmd or data. NOTE: This design restricts, for example, - * one one SPI display per SPI bus. - * cmd - true: select command; false: select data - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ -#if defined(CONFIG_LCD_SSD16800) - if (devid == SPIDEV_DISPLAY(0)) - { - stm32_gpiowrite(GPIO_SSD1680_CMD, !cmd); - } -#endif - - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) -{ - return OK; -} -#endif -#endif /* CONFIG_SPI_CMDDATA */ - -#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ +#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */ diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c index d57e2c42bfb..289609b19b4 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_ssd1680.c @@ -33,7 +33,7 @@ #include #include -#include "stm32wl5.h" +#include "stm32.h" #include "nucleo-wl55jc.h" #include "stm32wl5_gpio.h" #include "stm32wl5_ssd1680.h" @@ -59,7 +59,7 @@ static bool ssd1680_set_vcc(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_RST) static bool ssd1680_set_rst(bool state) { - stm32wl5_gpiowrite(GPIO_SSD1680_RST, state); + stm32_gpiowrite(GPIO_SSD1680_RST, state); return true; } #endif @@ -67,7 +67,7 @@ static bool ssd1680_set_rst(bool state) #if defined(CONFIG_SSD1680_GPIO_PIN_BUSY) static bool ssd1680_check_busy(void) { - return stm32wl5_gpioread(GPIO_SSD1680_BUSY); + return stm32_gpioread(GPIO_SSD1680_BUSY); } #endif @@ -106,20 +106,20 @@ int board_lcd_initialize(void) /* Initialize additional I/O for e-ink display */ #if defined(GPIO_SSD1680_PWR) - stm32wl5_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ + stm32_configgpio(GPIO_SSD1680_PWR); /* SSD1680 pwr */ lcdinfo("SSD1680 power line is available (0x%08x)\n", GPIO_SSD1680_PWR); #else lcdinfo("PWR control line is disabled\n"); #endif #if defined(GPIO_SSD1680_RST) - stm32wl5_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ + stm32_configgpio(GPIO_SSD1680_RST); /* SSD1680 reset */ lcdinfo("SSD1680 reset line is available (0x%08x)\n", GPIO_SSD1680_RST); #elif lcdinfo("SSD1680 RESET line is disabled\n"); #endif #if defined(GPIO_SSD1680_BUSY) - stm32wl5_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ + stm32_configgpio(GPIO_SSD1680_BUSY); /* SSD1680 busy */ lcdinfo("SSD1680 Line for reading busy state is available (0x%08x)\n", GPIO_SSD1680_BUSY); #elif @@ -128,7 +128,7 @@ int board_lcd_initialize(void) /* Initialize SPI */ - spi = stm32wl5_spibus_initialize(CONFIG_SSD1680_SPI_BUS); + spi = stm32_spibus_initialize(CONFIG_SSD1680_SPI_BUS); if (!spi) { lcderr("ERROR: Failed to initialize SPI port %d\n", From 84aba62f26a1edc61f34173b317ba088b2f255f4 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Fri, 12 Jun 2026 17:35:54 +0200 Subject: [PATCH 071/268] Docs/platforms: Add missing defconfig docs for esp32[-c3|-c6|-h2] Add missing defconfig docs for risc-v based Espressif devices --- .../esp32c3/boards/esp32c3-devkit/index.rst | 26 +++++++++ .../esp32c6/boards/esp32c6-devkitc/index.rst | 45 ++++++++++++++++ .../esp32c6/boards/esp32c6-devkitm/index.rst | 36 +++++++++++++ .../esp32h2/boards/esp32h2-devkit/index.rst | 54 +++++++++++++++++++ 4 files changed, 161 insertions(+) diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst index 8a313748066..2a02af8ab48 100644 --- a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst +++ b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst @@ -464,6 +464,18 @@ To test it, just execute the ``pwm`` application:: pwm_main: starting output with frequency: 10000 duty: 00008000 pwm_main: stopping output +random +------ + +This configuration shows the use of the ESP32-C3's True Random Number Generator. +To test it, just run ``rand`` to get 32 randomly generated bytes:: + + nsh> rand + Reading 8 random numbers + Random values (0x3ffe0b00): + 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... + 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. + rmt --- @@ -660,6 +672,20 @@ using WPA2. The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. +temperature_sensor +------------------ + +This configuration enables the on-chip temperature sensor driver. The sensor is +exposed through the uORB interface and can be read with the ``sensortest`` +utility:: + + nsh> sensortest temp + +tickless +-------- + +This configuration enables the support for tickless scheduler mode. + timer ----- diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst index ba228e8e913..3eb958c06b9 100644 --- a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst +++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst @@ -556,6 +556,18 @@ using 1 second delay):: nsh> qe +random +------ + +This configuration shows the use of the ESP32-C6's True Random Number Generator. +To test it, just run ``rand`` to get 32 randomly generated bytes:: + + nsh> rand + Reading 8 random numbers + Random values (0x3ffe0b00): + 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... + 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. + rmt --- @@ -687,6 +699,25 @@ If SPI peripherals are already in use you can also use bitbang driver which is a software implemented SPI peripheral by enabling `CONFIG_ESPRESSIF_SPI_BITBANG` option. +spislv +------ + +This configuration enables the SPI2 peripheral in **slave mode** and +provides the ``spislv`` example application to test data exchange with an +external SPI master. + +After building and flashing the firmware, run the following command on the +board terminal:: + + nsh> spislv -x 5 1a2b3c4d5e + +This command enqueues the data sequence ``1a2b3c4d5e`` in the slave buffer. +On the next transfer, the external SPI master should receive this data back +from the slave. + +By default, SPI2 is used with chip select on GPIO16. The pin mapping can be +adjusted through ``menuconfig`` under *System type → SPI configuration*. + sdmmc_spi --------- @@ -752,6 +783,20 @@ using WPA2. The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. +temperature_sensor +------------------ + +This configuration enables the on-chip temperature sensor driver. The sensor is +exposed through the uORB interface and can be read with the ``sensortest`` +utility:: + + nsh> sensortest temp + +tickless +-------- + +This configuration enables the support for tickless scheduler mode. + timer ----- diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst index 00cfba252e0..43cfccbfa7e 100644 --- a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst +++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst @@ -324,6 +324,18 @@ To test it, just execute the ``pwm`` application:: pwm_main: starting output with frequency: 10000 duty: 00008000 pwm_main: stopping output +random +------ + +This configuration shows the use of the ESP32-C6's True Random Number Generator. +To test it, just run ``rand`` to get 32 randomly generated bytes:: + + nsh> rand + Reading 8 random numbers + Random values (0x3ffe0b00): + 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... + 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. + rmt --- @@ -475,6 +487,25 @@ If SPI peripherals are already in use you can also use bitbang driver which is a software implemented SPI peripheral by enabling `CONFIG_ESPRESSIF_SPI_BITBANG` option. +spislv +------ + +This configuration enables the SPI2 peripheral in **slave mode** and +provides the ``spislv`` example application to test data exchange with an +external SPI master. + +After building and flashing the firmware, run the following command on the +board terminal:: + + nsh> spislv -x 5 1a2b3c4d5e + +This command enqueues the data sequence ``1a2b3c4d5e`` in the slave buffer. +On the next transfer, the external SPI master should receive this data back +from the slave. + +By default, SPI2 is used with chip select on GPIO1. The pin mapping can be +adjusted through ``menuconfig`` under *System type → SPI configuration*. + spiflash -------- @@ -507,6 +538,11 @@ using WPA2. The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. +tickless +-------- + +This configuration enables the support for tickless scheduler mode. + timer ----- diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst index ff979d67572..ce548f96968 100644 --- a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst +++ b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst @@ -240,6 +240,22 @@ the ``buttons`` application and pressing the ``BOOT`` button on the board:: nsh> Sample = 1 Sample = 0 +capture +-------- + +The capture configuration enables the capture driver and the capture example, allowing +the user to measure duty cycle and frequency of a signal. Default pin is GPIO12 with +an internal pull-up resistor enabled. When connecting a 50 Hz pulse with 50% duty cycle, +the following output is expected:: + + nsh> cap + cap_main: Hardware initialized. Opening the capture device: /dev/capture0 + cap_main: Number of samples: 0 + pwm duty cycle: 50 % + pwm frequency: 50 Hz + pwm duty cycle: 50 % + pwm frequency: 50 Hz + coremark -------- @@ -416,6 +432,18 @@ This configuration is the same as the ``nsh`` configuration, but it generates th image in a format that can be used by MCUboot. It also makes the ``make bootloader`` command to build the MCUboot bootloader image using the Espressif HAL. +motor +------- + +The motor configuration enables the MCPWM peripheral with support to brushed DC motor +control. + +It creates a ``/dev/motor0`` device with speed and direction control capabilities +by using two GPIOs (GPIO10 and GPIO11) for PWM output. PWM frequency is configurable +from 25 Hz to 3 kHz, however it defaults to 1 kHz. +There is also support for an optional fault GPIO (defaults to GPIO9), which can be used +for quick motor braking. All GPIOs are configurable in ``menuconfig``. + nsh --- @@ -514,6 +542,18 @@ using 1 second delay):: nsh> qe +random +------ + +This configuration shows the use of the ESP32-H2's hardware True Random Number Generator. +To test it, just run ``rand`` to get 32 randomly generated bytes:: + + nsh> rand + Reading 8 random numbers + Random values (0x3ffe0b00): + 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... + 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. + rmt --- @@ -703,6 +743,20 @@ To test it, just run the following:: Where x in the timer instance. +temperature_sensor +------------------ + +This configuration enables the on-chip temperature sensor driver. The sensor is +exposed through the uORB interface and can be read with the ``sensortest`` +utility:: + + nsh> sensortest temp + +tickless +-------- + +This configuration enables the support for tickless scheduler mode. + twai ---- From 03685825c9f56ca2221ed455ed497e9c3eea17f3 Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Tue, 9 Jun 2026 08:02:57 +0000 Subject: [PATCH 072/268] fs/binfmt: Enforce POSIX execute permissions prior to binary load Adds a pre-load permission check in exec_internal() to verify the calling task has the required execute (x) bits for the target file. Properly evaluates root (euid == 0), owner, group, and other permissions. This ensures POSIX compliance and cleanly rejects unauthorized files with -EACCES before they reach the ELF loader, preventing unnecessary memory allocation and downstream hardware execution faults. Signed-off-by: Abhishek Mishra --- binfmt/CMakeLists.txt | 4 ++ binfmt/Makefile | 4 ++ binfmt/binfmt.h | 20 ++++++++ binfmt/binfmt_checkexec.c | 100 +++++++++++++++++++++++++++++++++++++ binfmt/binfmt_exec.c | 7 +-- binfmt/binfmt_loadmodule.c | 8 +++ binfmt/builtin.c | 22 ++++++-- binfmt/elf.c | 24 ++++++--- binfmt/nxflat.c | 26 ++++++++++ 9 files changed, 199 insertions(+), 16 deletions(-) create mode 100644 binfmt/binfmt_checkexec.c diff --git a/binfmt/CMakeLists.txt b/binfmt/CMakeLists.txt index 0f0578ebce3..1af4cd3042b 100644 --- a/binfmt/CMakeLists.txt +++ b/binfmt/CMakeLists.txt @@ -41,6 +41,10 @@ list( binfmt_copyactions.c binfmt_dumpmodule.c) +if(CONFIG_SCHED_USER_IDENTITY) + list(APPEND SRCS binfmt_checkexec.c) +endif() + if(CONFIG_BINFMT_LOADABLE) list(APPEND SRCS binfmt_exit.c) endif() diff --git a/binfmt/Makefile b/binfmt/Makefile index e88e1a9c27e..31d84b1d50c 100644 --- a/binfmt/Makefile +++ b/binfmt/Makefile @@ -28,6 +28,10 @@ CSRCS = binfmt_globals.c binfmt_initialize.c binfmt_register.c binfmt_unregiste CSRCS += binfmt_loadmodule.c binfmt_unloadmodule.c binfmt_execmodule.c CSRCS += binfmt_exec.c binfmt_copyargv.c binfmt_copyactions.c binfmt_dumpmodule.c +ifeq ($(CONFIG_SCHED_USER_IDENTITY),y) +CSRCS += binfmt_checkexec.c +endif + ifeq ($(CONFIG_BINFMT_LOADABLE),y) CSRCS += binfmt_exit.c endif diff --git a/binfmt/binfmt.h b/binfmt/binfmt.h index 3cdf07ecbfa..c362bf041c6 100644 --- a/binfmt/binfmt.h +++ b/binfmt/binfmt.h @@ -213,6 +213,26 @@ void binfmt_freeactions(FAR const posix_spawn_file_actions_t *copy); # define binfmt_freeactions(copy) #endif +#ifdef CONFIG_SCHED_USER_IDENTITY +/**************************************************************************** + * Name: binfmt_checkexecperm + * + * Description: + * Verify that the calling task has execute permission on the file + * described by 'bin'. The file owner, group, and mode must already be + * populated in the binary_s structure. + * + * Input Parameters: + * bin - Load structure with uid, gid, and mode populated + * + * Returned Value: + * Zero (OK) on success; -EACCES if execute permission is denied. + * + ****************************************************************************/ + +int binfmt_checkexecperm(FAR struct binary_s *bin); +#endif + #ifdef CONFIG_BUILTIN /**************************************************************************** * Name: builtin_initialize diff --git a/binfmt/binfmt_checkexec.c b/binfmt/binfmt_checkexec.c new file mode 100644 index 00000000000..1436298dc24 --- /dev/null +++ b/binfmt/binfmt_checkexec.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * binfmt/binfmt_checkexec.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "binfmt.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: binfmt_checkexecperm + * + * Description: + * Verify that the calling task has execute permission on the file + * described by 'bin'. The file owner, group, and mode must already be + * populated in the binary_s structure before calling this function. + * + * Input Parameters: + * bin - Pointer to the binary descriptor with uid, gid, and mode set. + * + * Returned Value: + * Zero (OK) on success; -EACCES if execute permission is denied. + * + ****************************************************************************/ + +int binfmt_checkexecperm(FAR struct binary_s *bin) +{ + FAR struct tcb_s *rtcb; + mode_t xbits; + + rtcb = nxsched_self(); + + if (bin == NULL || rtcb == NULL || rtcb->group == NULL) + { + return OK; + } + + if (rtcb->group->tg_euid == 0) + { + /* Root can execute any file that has at least one execute bit set */ + + if ((bin->mode & (S_IXUSR | S_IXGRP | S_IXOTH)) == 0) + { + return -EACCES; + } + + return OK; + } + + if (rtcb->group->tg_euid == bin->uid) + { + xbits = S_IXUSR; + } + else if (rtcb->group->tg_egid == bin->gid) + { + xbits = S_IXGRP; + } + else + { + xbits = S_IXOTH; + } + + if ((bin->mode & xbits) == 0) + { + return -EACCES; + } + + return OK; +} diff --git a/binfmt/binfmt_exec.c b/binfmt/binfmt_exec.c index c2c73ee876b..ae3e4643b1e 100644 --- a/binfmt/binfmt_exec.c +++ b/binfmt/binfmt_exec.c @@ -31,7 +31,6 @@ #include #include -#include #include #include "binfmt.h" @@ -81,11 +80,13 @@ static int exec_internal(FAR const char *filename, FAR const posix_spawnattr_t *attr, bool spawn) { FAR struct binary_s *bin; - int pid; - int ret; #ifndef CONFIG_BINFMT_LOADABLE struct binary_s sbin; +#endif + int pid; + int ret; +#ifndef CONFIG_BINFMT_LOADABLE bin = &sbin; memset(bin, 0, sizeof(*bin)); #else diff --git a/binfmt/binfmt_loadmodule.c b/binfmt/binfmt_loadmodule.c index 4d5f9416de0..06d56c0c9b5 100644 --- a/binfmt/binfmt_loadmodule.c +++ b/binfmt/binfmt_loadmodule.c @@ -134,6 +134,14 @@ static int load_absmodule(FAR struct binary_s *bin, FAR const char *filename, binfmt_dumpmodule(bin); break; } + else if (ret == -EACCES) + { + /* Access explicitly denied -- stop here; do not let a fallback + * loader bypass the execute-permission check that already ran. + */ + + break; + } } return ret; diff --git a/binfmt/builtin.c b/binfmt/builtin.c index b2116806f46..5ec818b3dd9 100644 --- a/binfmt/builtin.c +++ b/binfmt/builtin.c @@ -34,6 +34,8 @@ #include #include +#include "binfmt.h" + #ifdef CONFIG_BUILTIN /**************************************************************************** @@ -76,6 +78,9 @@ static int builtin_loadbinary(FAR struct binary_s *binp, FAR const struct builtin_s *builtin; FAR char *name; int index; +#ifdef CONFIG_SCHED_USER_IDENTITY + int chk; +#endif binfo("Loading file: %s\n", filename); @@ -105,14 +110,21 @@ static int builtin_loadbinary(FAR struct binary_s *binp, return -ENOENT; } +#ifdef CONFIG_SCHED_USER_IDENTITY + binp->uid = builtin->uid; + binp->gid = builtin->gid; + binp->mode = builtin->mode; + + chk = binfmt_checkexecperm(binp); + if (chk < 0) + { + return chk; + } +#endif + binp->entrypt = builtin->main; binp->stacksize = builtin->stacksize; binp->priority = builtin->priority; -#ifdef CONFIG_SCHED_USER_IDENTITY - binp->uid = builtin->uid; - binp->gid = builtin->gid; - binp->mode = builtin->mode; -#endif return OK; } diff --git a/binfmt/elf.c b/binfmt/elf.c index 087c73589ae..cfe146cb26e 100644 --- a/binfmt/elf.c +++ b/binfmt/elf.c @@ -37,6 +37,8 @@ #include #include +#include "binfmt.h" + #ifdef CONFIG_ELF /**************************************************************************** @@ -110,6 +112,20 @@ static int elf_loadbinary(FAR struct binary_s *binp, goto errout_with_init; } +#ifdef CONFIG_SCHED_USER_IDENTITY + /* Save IDs and mode from file system before loading segments */ + + binp->uid = loadinfo.fileuid; + binp->gid = loadinfo.filegid; + binp->mode = loadinfo.filemode; + + ret = binfmt_checkexecperm(binp); + if (ret < 0) + { + goto errout_with_init; + } +#endif + /* Load the program binary */ ret = libelf_load_with_addrenv(&loadinfo); @@ -201,14 +217,6 @@ static int elf_loadbinary(FAR struct binary_s *binp, binp->mod.nfini = loadinfo.nfini; #endif -#ifdef CONFIG_SCHED_USER_IDENTITY - /* Save IDs and mode from file system */ - - binp->uid = loadinfo.fileuid; - binp->gid = loadinfo.filegid; - binp->mode = loadinfo.filemode; -#endif - libelf_dumpentrypt(&loadinfo); #ifdef CONFIG_PIC if (loadinfo.gotindex >= 0) diff --git a/binfmt/nxflat.c b/binfmt/nxflat.c index 010cf42546a..f390e5081f5 100644 --- a/binfmt/nxflat.c +++ b/binfmt/nxflat.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include @@ -36,10 +37,13 @@ #include +#include #include #include #include +#include "binfmt.h" + #ifdef CONFIG_NXFLAT /**************************************************************************** @@ -142,6 +146,9 @@ static int nxflat_loadbinary(FAR struct binary_s *binp, int nexports) { struct nxflat_loadinfo_s loadinfo; /* Contains globals for libnxflat */ +#ifdef CONFIG_SCHED_USER_IDENTITY + struct stat st; +#endif int ret; binfo("Loading file: %s\n", filename); @@ -156,6 +163,25 @@ static int nxflat_loadbinary(FAR struct binary_s *binp, goto errout; } +#ifdef CONFIG_SCHED_USER_IDENTITY + ret = file_fstat(&loadinfo.file, &st); + if (ret < 0) + { + berr("Failed to stat NXFLAT program binary: %d\n", ret); + goto errout_with_init; + } + + binp->uid = st.st_uid; + binp->gid = st.st_gid; + binp->mode = st.st_mode; + + ret = binfmt_checkexecperm(binp); + if (ret < 0) + { + goto errout_with_init; + } +#endif + /* Load the program binary */ ret = nxflat_load(&loadinfo); From e5d895912827be50517e13cb333e9ef423e3372f Mon Sep 17 00:00:00 2001 From: Felipe Moura Date: Sun, 7 Jun 2026 23:23:43 -0300 Subject: [PATCH 073/268] drivers/crypto: add Microchip RNG90 driver Add Microchip RNG90 TRNG driver with board integration for esp32c3 and rng90 defconfig support. Signed-off-by: Felipe Moura --- .../esp32c3/common/include/esp_board_rng90.h | 74 ++++ .../risc-v/esp32c3/common/src/CMakeLists.txt | 4 + boards/risc-v/esp32c3/common/src/Make.defs | 4 + .../esp32c3/common/src/esp_board_rng90.c | 95 +++++ .../esp32c3-devkit/configs/rng90/defconfig | 51 +++ .../esp32c3-devkit/src/esp32c3_bringup.c | 13 + drivers/crypto/CMakeLists.txt | 4 + drivers/crypto/Kconfig | 10 + drivers/crypto/Make.defs | 4 + drivers/crypto/rng90.c | 372 ++++++++++++++++++ include/nuttx/crypto/rng90.h | 66 ++++ 11 files changed, 697 insertions(+) create mode 100644 boards/risc-v/esp32c3/common/include/esp_board_rng90.h create mode 100644 boards/risc-v/esp32c3/common/src/esp_board_rng90.c create mode 100644 boards/risc-v/esp32c3/esp32c3-devkit/configs/rng90/defconfig create mode 100644 drivers/crypto/rng90.c create mode 100644 include/nuttx/crypto/rng90.h diff --git a/boards/risc-v/esp32c3/common/include/esp_board_rng90.h b/boards/risc-v/esp32c3/common/include/esp_board_rng90.h new file mode 100644 index 00000000000..f316efe866b --- /dev/null +++ b/boards/risc-v/esp32c3/common/include/esp_board_rng90.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/include/esp_board_rng90.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RNG90_H +#define __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RNG90_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rng90_initialize + * + * Description: + * Initialize and register the RNG90 True Random Number Generator driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/rngN + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + ****************************************************************************/ + +#ifdef CONFIG_DEV_RNG90 +int board_rng90_initialize(int devno); +#endif /* CONFIG_DEV_RNG90 */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RNG90_H */ \ No newline at end of file diff --git a/boards/risc-v/esp32c3/common/src/CMakeLists.txt b/boards/risc-v/esp32c3/common/src/CMakeLists.txt index d8b1323adb3..23feed738c0 100644 --- a/boards/risc-v/esp32c3/common/src/CMakeLists.txt +++ b/boards/risc-v/esp32c3/common/src/CMakeLists.txt @@ -76,6 +76,10 @@ if(CONFIG_ARCH_BOARD_COMMON) list(APPEND SRCS esp_board_bmp280.c) endif() + if(CONFIG_DEV_RNG90) + list(APPEND SRCS esp_board_rng90.c) + endif() + if(CONFIG_MMCSD_SPI) list(APPEND SRCS esp_board_mmcsd.c) endif() diff --git a/boards/risc-v/esp32c3/common/src/Make.defs b/boards/risc-v/esp32c3/common/src/Make.defs index 03d09271575..4f7a968440b 100644 --- a/boards/risc-v/esp32c3/common/src/Make.defs +++ b/boards/risc-v/esp32c3/common/src/Make.defs @@ -74,6 +74,10 @@ ifeq ($(CONFIG_SENSORS_BMP280),y) CSRCS += esp_board_bmp280.c endif +ifeq ($(CONFIG_DEV_RNG90),y) + CSRCS += esp_board_rng90.c +endif + ifeq ($(CONFIG_MMCSD_SPI),y) CSRCS += esp_board_mmcsd.c endif diff --git a/boards/risc-v/esp32c3/common/src/esp_board_rng90.c b/boards/risc-v/esp32c3/common/src/esp_board_rng90.c new file mode 100644 index 00000000000..3d14b53806a --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_rng90.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_rng90.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#ifndef CONFIG_ESPRESSIF_I2C_BITBANG +# include "espressif/esp_i2c.h" +#else +# include "espressif/esp_i2c_bitbang.h" +#endif + +#include "esp_board_rng90.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rng90_initialize + * + * Description: + * Initialize and register the RNG90 True Random Number Generator driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/rngN + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + ****************************************************************************/ + +int board_rng90_initialize(int devno) +{ + struct i2c_master_s *i2c; + char devpath[16]; + int ret; + + sninfo("Initializing RNG90\n"); + + /* Initialize I2C */ + +#ifndef CONFIG_ESPRESSIF_I2C_BITBANG + i2c = esp_i2cbus_initialize(ESPRESSIF_I2C0); +#else + i2c = esp_i2cbus_bitbang_initialize(); +#endif + + if (i2c == NULL) + { + snerr("ERROR: Failed to initialize I2C for RNG90\n"); + return -ENODEV; + } + + /* Register the RNG90 driver at "/dev/rngN" */ + + snprintf(devpath, sizeof(devpath), "/dev/rng%d", devno); + ret = rng90_register(devpath, i2c, RNG90_I2C_ADDR); + if (ret < 0) + { + snerr("ERROR: Failed to register RNG90 driver: %d\n", ret); + return ret; + } + + return OK; +} + diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rng90/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rng90/defconfig new file mode 100644 index 00000000000..170cbd0ecb1 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rng90/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_CRYPTO=y +CONFIG_DEV_RNG90=y +CONFIG_ESPRESSIF_I2C0=y +CONFIG_EXAMPLES_RNG90=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index 942d6a1def0..36023aa21c2 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -41,6 +41,10 @@ #include "esp_board_i2c.h" #include "esp_board_bmp180.h" +#ifdef CONFIG_DEV_RNG90 +# include "esp_board_rng90.h" +#endif + #include "espressif/esp_start.h" #ifdef CONFIG_ESPRESSIF_ADC @@ -404,6 +408,15 @@ int esp_bringup(void) } #endif +#ifdef CONFIG_DEV_RNG90 + ret = board_rng90_initialize(0); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RNG90 driver: %d\n", ret); + } +#endif + #ifdef CONFIG_ESP_SDM struct esp_sdm_chan_config_s config = { diff --git a/drivers/crypto/CMakeLists.txt b/drivers/crypto/CMakeLists.txt index f310ae115e5..3c93183635e 100644 --- a/drivers/crypto/CMakeLists.txt +++ b/drivers/crypto/CMakeLists.txt @@ -23,3 +23,7 @@ if(CONFIG_DEV_URANDOM AND NOT CONFIG_DEV_URANDOM_ARCH) target_sources(drivers PRIVATE dev_urandom.c) endif() + +if(CONFIG_DEV_RNG90) + target_sources(drivers PRIVATE rng90.c) +endif() diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 00b4d3f9155..e53927894a0 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -137,3 +137,13 @@ config SE05X_LOG_DEBUG endchoice # SE05x debug log level endif #DEV_SE05X + +config DEV_RNG90 + bool "Enable Microchip RNG90 TRNG" + depends on I2C + depends on CRYPTO + default n + ---help--- + Enable support for /dev/rng90 random number generator provided by + Microchip RNG90 TRNG. + diff --git a/drivers/crypto/Make.defs b/drivers/crypto/Make.defs index 240ba5ceab8..e243bd916fa 100644 --- a/drivers/crypto/Make.defs +++ b/drivers/crypto/Make.defs @@ -31,6 +31,10 @@ ifeq ($(CONFIG_DEV_SE05X),y) include crypto/pnt/Make.defs endif +ifeq ($(CONFIG_DEV_RNG90),y) + CSRCS += rng90.c +endif + # Include crypto device driver build support DEPPATH += --dep-path crypto diff --git a/drivers/crypto/rng90.c b/drivers/crypto/rng90.c new file mode 100644 index 00000000000..3c7b065fe69 --- /dev/null +++ b/drivers/crypto/rng90.c @@ -0,0 +1,372 @@ +/**************************************************************************** + * drivers/crypto/rng90.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RNG90_WAKE_I2C_ADDR 0x00 +#define RNG90_WAKE_I2C_MAXFREQ 100000 +#define RNG90_WAKE_RETRIES 3 +#define RNG90_WAKE_DELAY_MS 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rng90_dev_s +{ + FAR struct i2c_master_s *i2c; + uint8_t addr; + mutex_t lock; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static bool rng90_wakeup(FAR struct rng90_dev_s *priv); +static bool rng90_sleep(FAR struct rng90_dev_s *priv); +static void rng90_send_wake_token(FAR struct rng90_dev_s *priv); +static void rng90_i2c_config(FAR struct i2c_config_s *config, + uint32_t frequency, uint8_t address); +static bool rng90_genrnd(FAR struct rng90_dev_s *priv, FAR uint8_t *buffer, + size_t buflen); + +/* Character driver methods */ + +static int rng90_open(FAR struct file *filep); +static int rng90_close(FAR struct file *filep); +static ssize_t rng90_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static int rng90_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_rng90_fops = +{ + rng90_open, rng90_close, rng90_read, NULL, + NULL, rng90_ioctl, NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int rng90_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct rng90_dev_s *priv = inode->i_private; + + /* The close path puts the device into explicit sleep, so wake it here. */ + + nxmutex_lock(&priv->lock); + if (!rng90_wakeup(priv)) + { + crypterr("ERROR: Failed to wake rng90 device\n"); + } + + nxmutex_unlock(&priv->lock); + + return OK; +} + +static int rng90_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct rng90_dev_s *priv = inode->i_private; + + nxmutex_lock(&priv->lock); + if (!rng90_sleep(priv)) + { + crypterr("ERROR: Failed to put rng90 device to sleep\n"); + } + + nxmutex_unlock(&priv->lock); + return OK; +} + +static ssize_t rng90_read(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct rng90_dev_s *priv = inode->i_private; + bool ret; + + nxmutex_lock(&priv->lock); + ret = rng90_genrnd(priv, (FAR uint8_t *)buffer, buflen); + nxmutex_unlock(&priv->lock); + + /* rng90 always returns 32 bytes */ + + return ret ? (ssize_t)MIN(buflen, 32u) : -EIO; +} + +static int rng90_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct rng90_dev_s *priv = inode->i_private; + int ret; + + ret = nxmutex_lock(&priv->lock); + if (ret != 0) + { + return ret; + } + + switch (cmd) + { + case RNG90_IOC_WAKEUP: + ret = rng90_wakeup(priv) ? OK : ERROR; + break; + + case RNG90_IOC_SLEEP: + ret = rng90_sleep(priv) ? OK : ERROR; + break; + + case RNG90_IOC_GENRND: + ret = rng90_genrnd(priv, (FAR uint8_t *)arg, 32) ? OK : ERROR; + break; + + default: + crypterr("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +static void rng90_i2c_config(FAR struct i2c_config_s *config, + uint32_t frequency, uint8_t address) +{ + config->frequency = frequency; + config->address = address; + config->addrlen = 7; +} + +static bool rng90_is_wake_response(FAR const uint8_t *response) +{ + return response[0] == 0x04 && response[1] == 0x11 && + response[2] == 0x33 && response[3] == 0x43; +} + +static void rng90_send_wake_token(FAR struct rng90_dev_s *priv) +{ + struct i2c_config_s config; + uint8_t wake_token = 0x01; + uint32_t wake_freq; + + /* Wake is an SDA-low pulse, not a normal transaction with an ACK. */ + + wake_freq = MIN(RNG90_I2C_FREQ, RNG90_WAKE_I2C_MAXFREQ); + rng90_i2c_config(&config, wake_freq, RNG90_WAKE_I2C_ADDR); + i2c_write(priv->i2c, &config, &wake_token, 1); + up_mdelay(RNG90_WAKE_DELAY_MS); +} + +static bool rng90_wakeup(FAR struct rng90_dev_s *priv) +{ + struct i2c_config_s config; + uint8_t response[4]; + int attempt; + int ret; + + for (attempt = 0; attempt < RNG90_WAKE_RETRIES; attempt++) + { + rng90_send_wake_token(priv); + + rng90_i2c_config(&config, RNG90_I2C_FREQ, priv->addr); + ret = i2c_read(priv->i2c, &config, response, sizeof(response)); + if (ret >= 0 && rng90_is_wake_response(response)) + { + return true; + } + } + + return false; +} + +static bool rng90_sleep(FAR struct rng90_dev_s *priv) +{ + struct i2c_config_s config; + uint8_t word_address = 0x01; + int ret; + + rng90_i2c_config(&config, RNG90_I2C_FREQ, priv->addr); + + /* Sleep sequence: device address + word address 0x01 + Stop condition */ + + ret = i2c_write(priv->i2c, &config, &word_address, 1); + return (ret >= 0); +} + +static uint16_t rng90_crc16(FAR const uint8_t *data, size_t len) +{ + uint16_t crc = 0x0000; + size_t i; + + for (i = 0; i < len; i++) + { + uint8_t byte = data[i]; + uint8_t shift; + + for (shift = 0x01; shift != 0; shift <<= 1) + { + bool dbit = (byte & shift) != 0; + bool cbit = (crc & 0x8000) != 0; + + crc <<= 1; + if (dbit != cbit) + { + crc ^= 0x8005; + } + } + } + + return crc; +} + +static bool rng90_genrnd(FAR struct rng90_dev_s *priv, FAR uint8_t *buffer, + size_t buflen) +{ + struct i2c_config_s config; + uint8_t response[35]; + int ret; + int attempt; + + /* Random command packet (datasheet section 6.2) */ + + uint8_t pkt[28]; + uint16_t crc; + + pkt[0] = 0x03; /* word address: command */ + pkt[1] = 27; /* count */ + pkt[2] = 0x16; /* opcode: Random */ + pkt[3] = 0x00; /* param1 */ + pkt[4] = 0x00; /* param2 lo */ + pkt[5] = 0x00; /* param2 hi */ + + /* data: 20 bytes, any value */ + + memset(&pkt[6], 0x00, 20); + + /* CRC over count + packet (pkt[1] through pkt[25]) */ + + crc = rng90_crc16(&pkt[1], 25); + pkt[26] = (uint8_t)(crc & 0xff); /* CRC lo */ + pkt[27] = (uint8_t)(crc >> 8); /* CRC hi */ + + rng90_i2c_config(&config, RNG90_I2C_FREQ, priv->addr); + + for (attempt = 0; attempt < 2; attempt++) + { + if (attempt > 0) + { + rng90_wakeup(priv); + } + + ret = i2c_write(priv->i2c, &config, pkt, sizeof(pkt)); + if (ret < 0) + { + continue; + } + + /* Wait for command execution (datasheet section 5.6.2) */ + + up_mdelay(72); + + /* Response: [count=35][32 random bytes][crc_lo][crc_hi] */ + + ret = i2c_read(priv->i2c, &config, response, sizeof(response)); + if (ret >= 0) + { + memcpy(buffer, &response[1], MIN(buflen, 32u)); + return true; + } + } + + return false; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int rng90_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, + uint8_t addr) +{ + int ret; + FAR struct rng90_dev_s *priv; + + /* Sanity check */ + + DEBUGASSERT(devpath != NULL); + DEBUGASSERT(i2c != NULL); + + /* Initialize the device's structure */ + + priv = (FAR struct rng90_dev_s *)kmm_malloc(sizeof(*priv)); + if (priv == NULL) + { + crypterr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + priv->i2c = i2c; + priv->addr = addr; + nxmutex_init(&priv->lock); + + /* Register the character driver */ + + ret = register_driver(devpath, &g_rng90_fops, 0666, priv); + if (ret < 0) + { + crypterr("ERROR: Failed to register driver: %d\n", ret); + nxmutex_destroy(&priv->lock); + kmm_free(priv); + return ret; + } + + return OK; +} diff --git a/include/nuttx/crypto/rng90.h b/include/nuttx/crypto/rng90.h new file mode 100644 index 00000000000..a83afd1db7b --- /dev/null +++ b/include/nuttx/crypto/rng90.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * include/nuttx/crypto/rng90.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_CRYPTO_RNG90_H +#define __INCLUDE_NUTTX_CRYPTO_RNG90_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_DEV_RNG90) + +#define RNG90_I2C_ADDR 0x40 +#define RNG90_I2C_FREQ 400000 + +#define _RNG90IOCBASE (0x3b00) /* RNG90 ioctl base */ +#define _RNG90IOC(nr) _IOC(_RNG90IOCBASE, nr) + +#define RNG90_IOC_WAKEUP _RNG90IOC(0x01) +#define RNG90_IOC_SLEEP _RNG90IOC(0x02) +#define RNG90_IOC_GENRND _RNG90IOC(0x03) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct i2c_master_s; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int rng90_register(FAR const char *devpath, + FAR struct i2c_master_s *i2c, + uint8_t addr); + +#endif /* CONFIG_I2C && CONFIG_DEV_RNG90 */ +#endif /* __INCLUDE_NUTTX_CRYPTO_RNG90_H */ From cf9c51d14485f462c1a2a091a5989fe4b8e3c3d7 Mon Sep 17 00:00:00 2001 From: Felipe Moura Date: Sun, 7 Jun 2026 23:23:43 -0300 Subject: [PATCH 074/268] Documentation/examples/rng90: add RNG90 application documentation Document configuration, usage, Kconfig enable path, and hardware validation for the RNG90 example. Signed-off-by: Felipe Moura --- .../applications/examples/rng90/index.rst | 118 ++++++++++++++++++ 1 file changed, 118 insertions(+) create mode 100644 Documentation/applications/examples/rng90/index.rst diff --git a/Documentation/applications/examples/rng90/index.rst b/Documentation/applications/examples/rng90/index.rst new file mode 100644 index 00000000000..1f91ace7101 --- /dev/null +++ b/Documentation/applications/examples/rng90/index.rst @@ -0,0 +1,118 @@ +============================= +``rng90`` RNG90 TRNG Example +============================= + +The ``rng90`` example is a simple NuttX application that opens an RNG90 device +node, reads random bytes, and prints them in hexadecimal format. + +RNG90 is a dedicated hardware random number generator IC from Microchip. It can +be used as a companion device for microcontrollers that do not provide native +true random number generation (TRNG). + +According to the Microchip RNG90 product page and linked validation artifacts, +the device is presented as a FIPS 140-3 compliant random number generator with +SP 800-90 A/B/C alignment, with references to NIST validation entries such as +entropy certificate E194 and DRBG validation A3013. + +Microchip also positions this device for disposable/ecosystem-control +applications, which makes it a practical choice for cost-sensitive designs. + +Configuration +============= + +Enable this application in ``menuconfig``: + +- ``Application Configuration -> Examples -> Microchip RNG90 TRNG example`` + +Required dependency: + +- Enable the driver in ``menuconfig``: + ``Device Drivers -> Cryptographic Device Drivers -> Enable Microchip RNG90 TRNG`` + (``CONFIG_DEV_RNG90``) + +Application options: + +- ``CONFIG_EXAMPLES_RNG90`` +- ``CONFIG_EXAMPLES_RNG90_PROGNAME`` (default: ``"rng90"``) +- ``CONFIG_EXAMPLES_RNG90_DEVPATH`` (default: ``"/dev/rng0"``) +- ``CONFIG_EXAMPLES_RNG90_PRIORITY`` +- ``CONFIG_EXAMPLES_RNG90_STACKSIZE`` + +Usage +===== + +From NSH:: + + rng90 [] [] + +Arguments: + +- ````: RNG90 device path (default from + ``CONFIG_EXAMPLES_RNG90_DEVPATH``) +- ````: number of random bytes to read (``1..32``, default ``32``) + +Examples:: + + rng90 + rng90 /dev/rng0 16 + +Expected output +=============== + +:: + + RNG90 example: device /dev/rng0 + Read 16 random byte(s): + 3f a1 7c ... + +Notes +===== + +- Opening the device wakes up RNG90. +- Closing the device puts RNG90 back to sleep. +- If ```` is outside ``1..32``, the app clamps it to ``32``. + +Hardware validation log +======================= + +The following session was executed on real hardware to validate this example. + +Test setup: + +- Host: macOS +- Board: ``esp32c3-devkit`` +- Serial port: ``/dev/cu.wchusbserial140`` +- Serial settings: ``115200 8N1`` + +Console transcript:: + + nsh> uname -a + NuttX 12.6.0-RC1 4130050287-dirty Jun 7 2026 22:11:21 risc-v esp32c3-devkit + nsh> ls /dev/rng0 + /dev/rng0 + nsh> rng90 + RNG90 example: device /dev/rng0 + Read 32 random byte(s): + 0d b2 71 d1 40 1f 3c 50 52 3d c6 2c a9 74 ec 60 + 44 ab 67 bb c4 34 1b ac 48 62 fe b9 fd 95 c9 cb + nsh> rng90 /dev/rng0 16 + RNG90 example: device /dev/rng0 + Read 16 random byte(s): + ef 82 5f b7 41 f1 48 13 5a 41 16 3a 67 1b 90 f2 + nsh> rng90 /dev/rng0 64 + Invalid count 64, clamping to 32 + RNG90 example: device /dev/rng0 + Read 32 random byte(s): + bb be 2f 20 7f c8 33 8d 18 90 c8 fb 94 db bc e6 + 84 41 17 6f 5a be 5a 06 c3 7b f1 30 ac f2 a6 f5 + nsh> + +References +========== + +- Microchip product page: + https://www.microchip.com/en-us/product/RNG90 +- NIST CMVP entropy certificate E194: + https://csrc.nist.gov/projects/cryptographic-module-validation-program/entropy-validations/certificate/194 +- NIST CAVP DRBG validation A3013: + https://csrc.nist.gov/projects/cryptographic-algorithm-validation-program/details?validation=35623 From 2bcc59b42f1c55d56c00272de560b4e03e796eb7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 12 Jun 2026 19:15:30 +0200 Subject: [PATCH 075/268] arch/nrf91: defer GNSS start until the modem is GNSS-capable When the GNSS sensor is opened before the LTE stack has powered the modem on, the modem is not yet in a GNSS-capable functional mode. Instead of failing the activate with -EACCES, remember the request (priv->pending) and let the GNSS thread poll the modem functional mode (AT+CFUN?) and start GNSS once it becomes GNSS-capable. The LTE stack keeps ownership of modem power. Extract the configure/start sequence into nrf91_gnss_start() so it can be used both from nrf91_gnss_enable() and from the thread's CFUN poll. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_gnss.c | 134 ++++++++++++++++++++------ 1 file changed, 104 insertions(+), 30 deletions(-) diff --git a/arch/arm/src/nrf91/nrf91_modem_gnss.c b/arch/arm/src/nrf91/nrf91_modem_gnss.c index 95268f89599..b5539567a95 100644 --- a/arch/arm/src/nrf91/nrf91_modem_gnss.c +++ b/arch/arm/src/nrf91/nrf91_modem_gnss.c @@ -28,7 +28,10 @@ #include +#include #include +#include +#include #include #include #include @@ -70,6 +73,12 @@ /* Shorten some names */ +/* While a start is deferred (modem not yet GNSS-capable), the GNSS thread + * re-checks the modem functional mode at this interval. + */ + +#define NRF91_GNSS_CFUN_POLL_TICKS (SEC2TICK(2)) + #define NRF_GNSS_PVT_FRAME_LEN (sizeof(struct nrf_modem_gnss_pvt_data_frame)) #define NRF_GNSS_NMEA_FRAME_LEN (sizeof(struct nrf_modem_gnss_nmea_data_frame)) #define NRF_GNSS_AGPS_FRAME_LEN (sizeof(struct nrf_modem_gnss_agps_data_frame)) @@ -84,6 +93,7 @@ struct nrf91_gnss_s struct gnss_lowerhalf_s lower; bool running; + bool pending; bool singlefix; int notime_cntr; sem_t rx_sem; @@ -208,6 +218,40 @@ static bool nrf91_gnss_isactive(int cfun) * Name: nrf91_gnss_enable ****************************************************************************/ +/**************************************************************************** + * Name: nrf91_gnss_start + * + * Description: + * Configure and start the GNSS engine. The caller must have verified that + * the modem is in a GNSS-capable functional mode (see nrf91_gnss_isactive). + * + ****************************************************************************/ + +static int nrf91_gnss_start(struct nrf91_gnss_s *priv) +{ + int ret; + + /* Configure GNSS modem */ + + ret = nrf91_gnss_configure(); + if (ret < 0) + { + snerr("nrf91_gnss_configure failed %d\n", ret); + return ret; + } + + ret = nrf_modem_gnss_start(); + if (ret < 0) + { + snerr("nrf_modem_gnss_start failed %d", ret); + return ret; + } + + priv->pending = false; + priv->running = true; + return OK; +} + static int nrf91_gnss_enable(struct nrf91_gnss_s *priv, bool enable) { int ret = OK; @@ -224,43 +268,44 @@ static int nrf91_gnss_enable(struct nrf91_gnss_s *priv, bool enable) goto errout; } - /* GNSS must be active */ + /* The modem must be in a GNSS-capable functional mode before GNSS can + * be started. When the sensor is opened early (e.g. before the LTE + * stack has powered the modem on), it is not yet active. Rather than + * failing the open, remember the request and let the GNSS thread start + * GNSS once the modem reaches a GNSS-capable mode (see CFUN poll in + * nrf91_gnss_thread). The LTE stack keeps ownership of modem power. + */ if (!nrf91_gnss_isactive(cfun)) { - snerr("GNSS is not activated!"); - ret = -EACCES; - goto errout; + sninfo("GNSS not yet active (CFUN=%d); deferring start\n", cfun); + priv->pending = true; + + /* Kick the thread so it enters its CFUN-poll wait */ + + nxsem_post(&priv->rx_sem); + return OK; } - /* Configure GNSS modem */ - - ret = nrf91_gnss_configure(); - if (ret < 0) - { - snerr("nrf91_gnss_configure failed %d\n", ret); - return ret; - } - - ret = nrf_modem_gnss_start(); - if (ret < 0) - { - snerr("nrf_modem_gnss_start failed %d", ret); - goto errout; - } - - priv->running = true; + ret = nrf91_gnss_start(priv); } else { - ret = nrf_modem_gnss_stop(); - if (ret < 0) - { - snerr("nrf_modem_gnss_stop failed %d", ret); - goto errout; - } + /* Cancel any pending deferred start */ - priv->running = false; + priv->pending = false; + + if (priv->running) + { + ret = nrf_modem_gnss_stop(); + if (ret < 0) + { + snerr("nrf_modem_gnss_stop failed %d", ret); + goto errout; + } + + priv->running = false; + } } errout: @@ -624,9 +669,38 @@ static int nrf91_gnss_thread(int argc, char** argv) while (true) { - /* Read data */ + /* While a start is deferred, wait with a timeout and poll the modem + * functional mode; start GNSS once the modem becomes GNSS-capable + * (e.g. after the LTE stack has powered it on). Otherwise wait + * indefinitely for the next GNSS event. + */ + + if (priv->pending && !priv->running) + { + ret = nxsem_tickwait(&priv->rx_sem, NRF91_GNSS_CFUN_POLL_TICKS); + if (ret == -ETIMEDOUT) + { + int cfun = 0; + + if (priv->pending && !priv->running && + nrf_modem_at_scanf("AT+CFUN?", "+CFUN: %d", &cfun) >= 0 && + nrf91_gnss_isactive(cfun)) + { + sninfo("modem GNSS-capable (CFUN=%d); starting GNSS\n", + cfun); + nrf91_gnss_start(priv); + } + + continue; + } + } + else + { + /* Read data */ + + ret = nxsem_wait(&priv->rx_sem); + } - ret = nxsem_wait(&priv->rx_sem); if (ret < 0) { return ret; From 3a8d4ba3dd4d547e043326b0584d8a8e53ebf24b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 12 Jun 2026 19:15:41 +0200 Subject: [PATCH 076/268] arch/nrf91: convert GNSS UTC time with timegm() not mktime() The GNSS datetime reported by the modem is UTC. mktime() interprets the broken-down time as local time, so a configured timezone would skew the reported epoch. Use timegm() to convert it directly as UTC. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_gnss.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/nrf91/nrf91_modem_gnss.c b/arch/arm/src/nrf91/nrf91_modem_gnss.c index b5539567a95..79298234e41 100644 --- a/arch/arm/src/nrf91/nrf91_modem_gnss.c +++ b/arch/arm/src/nrf91/nrf91_modem_gnss.c @@ -223,7 +223,8 @@ static bool nrf91_gnss_isactive(int cfun) * * Description: * Configure and start the GNSS engine. The caller must have verified that - * the modem is in a GNSS-capable functional mode (see nrf91_gnss_isactive). + * the modem is in a GNSS-capable functional mode + * (see nrf91_gnss_isactive). * ****************************************************************************/ @@ -510,7 +511,12 @@ static void nrf91_gnss_pvt_event(struct nrf91_gnss_s *priv) tm.tm_isdst = 0; gps.timestamp = timestamp; - gps.time_utc = mktime(&tm); + + /* The GNSS datetime is UTC; use timegm() (not mktime(), which would + * apply the local timezone) to convert it to epoch seconds. + */ + + gps.time_utc = timegm(&tm); gps.latitude = priv->pvt.latitude; gps.longitude = priv->pvt.longitude; gps.altitude = priv->pvt.altitude; From ef211d6f3cff93076cd9792ad1a0a7583a0430e0 Mon Sep 17 00:00:00 2001 From: Catalin Visinescu Date: Sat, 13 Jun 2026 09:33:52 -0400 Subject: [PATCH 077/268] drivers/contactless/pn532: Fix Stack Overflow in PN532 Contactless Driver When calling Set RF Configuration command, a compromised user process can trigger memory corruption in the kernel. This can lead to a system crash or potentially arbitrary code execution in the kernel. It addresses an earlier incomplete fix. Tested locally. Signed-off-by: Your Name --- drivers/contactless/pn532.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/contactless/pn532.c b/drivers/contactless/pn532.c index 722ca843ea1..7fea654be86 100644 --- a/drivers/contactless/pn532.c +++ b/drivers/contactless/pn532.c @@ -788,13 +788,18 @@ static int pn532_read_passive_target(FAR struct pn532_dev_s *dev, bool pn532_set_rf_config(struct pn532_dev_s * dev, struct pn_rf_config_s * conf) { + /* cmd_buffer is sizeof(pn532_frame) + up to 16 bytes data */ + bool res = false; - uint8_t cmd_buffer[15 + 7]; + uint8_t cmd_buffer[6 + 16]; FAR struct pn532_frame *f = (FAR struct pn532_frame *) cmd_buffer; pn532_frame_init(f, PN532_COMMAND_RFCONFIGURATION); f->data[1] = conf->cfg_item; - DEBUGASSERT(conf->data_size <= 16); + + /* only copy 16 bytes minus 1 byte for each: cmd and cfg_item */ + + DEBUGASSERT(conf->data_size <= 16 - 2); memcpy(&f->data[2], conf->config, conf->data_size); f->len += conf->data_size + 1; pn532_frame_finish(f); From f9912abf5f8e83b02dc6e0f321cd3af36fe2b8df Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 12 Jun 2026 19:17:05 +0200 Subject: [PATCH 078/268] arch/nrf91: expose GNSS priority as a control ioctl Coexistence policy does not belong in the driver. Replace the in-driver priority-boost arbitration (the NRF91_MODEM_GNSS_BOOST_PRIO knob and the NOT_ENOUGH_WINDOW_TIME counter heuristic) with a user space mechanism: SNIOC_GNSS_SET_PRIORITY toggles nrf_modem_gnss priority mode on request, leaving the when-to-use-it decision to the application. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/Kconfig | 12 ----- arch/arm/src/nrf91/nrf91_modem_gnss.c | 77 +++++++++------------------ include/nuttx/sensors/ioctl.h | 11 +++- 3 files changed, 35 insertions(+), 65 deletions(-) diff --git a/arch/arm/src/nrf91/Kconfig b/arch/arm/src/nrf91/Kconfig index 120688899fd..5e9d77b84e9 100644 --- a/arch/arm/src/nrf91/Kconfig +++ b/arch/arm/src/nrf91/Kconfig @@ -808,16 +808,4 @@ config NRF91_MODEM_PREFERENCE For details look at "nRF9160 AT Commands Command Reference Guid" from Nordic, section "5.27 System mode" -if NRF91_MODEM_GNSS - -config NRF91_MODEM_GNSS_BOOST_PRIO - bool "Modem GNSS support for priority boost" - default y - ---help--- - Enables GNSS priority boos over LTE idle mode. - For details look at nrf_modem_gnss_prio_mode_enable() documentation - in sdk-nrfxlib/nrf_modem/include/nrf_modem_gnss.h - -endif # NRF91_MODEM_GNSS - endif # NRF91_MODEM diff --git a/arch/arm/src/nrf91/nrf91_modem_gnss.c b/arch/arm/src/nrf91/nrf91_modem_gnss.c index 79298234e41..47ac7766025 100644 --- a/arch/arm/src/nrf91/nrf91_modem_gnss.c +++ b/arch/arm/src/nrf91/nrf91_modem_gnss.c @@ -37,6 +37,7 @@ #include #include +#include #include #include "nrf_modem.h" @@ -61,6 +62,7 @@ #define NRF91_GNSS_USE_CASE NRF_MODEM_GNSS_USE_CASE_MULTIPLE_HOT_START #define NRF91_GNSS_POWER_MODE NRF_MODEM_GNSS_PSM_DISABLED + #ifdef NRF91_GNSS_NMEA # define NRF91_GNSS_NMEA_MASK (NRF_MODEM_GNSS_NMEA_GGA_MASK | \ NRF_MODEM_GNSS_NMEA_GLL_MASK | \ @@ -95,7 +97,6 @@ struct nrf91_gnss_s bool running; bool pending; bool singlefix; - int notime_cntr; sem_t rx_sem; /* PVT support */ @@ -141,9 +142,6 @@ static ssize_t nrf91_gnss_inject_data(struct gnss_lowerhalf_s *lower, static int nrf91_gnss_configure(void); static bool nrf91_gnss_isactive(int cfun); static int nrf91_gnss_enable(struct nrf91_gnss_s *priv, bool enable); -#ifdef CONFIG_NRF91_MODEM_GNSS_BOOST_PRIO -static void nrf91_gnss_boost_prio(struct nrf91_gnss_s *priv); -#endif static void nrf91_gnss_pvt_event(struct nrf91_gnss_s *priv); static void nrf91_gnss_event_handler(int event); static int nrf91_gnss_thread(int argc, char** argv); @@ -398,9 +396,30 @@ static int nrf91_gnss_control(struct gnss_lowerhalf_s *lower, struct file *filep, int cmd, unsigned long arg) { - /* TODO */ + int ret; - return 0; + switch (cmd) + { + case SNIOC_GNSS_SET_PRIORITY: + + /* Give GNSS priority over LTE idle (the "boost") or drop it. */ + + if (arg != 0) + { + ret = nrf_modem_gnss_prio_mode_enable(); + } + else + { + ret = nrf_modem_gnss_prio_mode_disable(); + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; } /**************************************************************************** @@ -416,33 +435,6 @@ static ssize_t nrf91_gnss_inject_data(struct gnss_lowerhalf_s *lower, return 0; } -#ifdef CONFIG_NRF91_MODEM_GNSS_BOOST_PRIO -/**************************************************************************** - * Name: nrf91_gnss_boost_prio - ****************************************************************************/ - -static void nrf91_gnss_boost_prio(struct nrf91_gnss_s *priv) -{ - int ret; - - /* Boost GNSS priority only once - we don't want to block LTE too long */ - - if (priv->notime_cntr != -1) - { - if (priv->notime_cntr > 5) - { - ret = nrf_modem_gnss_prio_mode_enable(); - if (ret < 0) - { - snerr("nrf_modem_gnss_prio_mode_enable failed %d!", ret); - } - - priv->notime_cntr = -1; - } - } -} -#endif - /**************************************************************************** * Name: nrf91_gnss_pvt_event ****************************************************************************/ @@ -547,25 +539,6 @@ static void nrf91_gnss_pvt_event(struct nrf91_gnss_s *priv) { snerr("GNSS DEADLINE_MISSED!"); } - - if (priv->pvt.flags & NRF_MODEM_GNSS_PVT_FLAG_NOT_ENOUGH_WINDOW_TIME) - { - snerr("GNSS NOT_ENOUGH_WINDOW_TIME!"); - -#ifdef CONFIG_NRF91_MODEM_GNSS_BOOST_PRIO - /* GNSS priority boost over LTE idle */ - - nrf91_gnss_boost_prio(priv); -#endif - - priv->notime_cntr++; - } - else - { - /* Reset counter */ - - priv->notime_cntr = 0; - } } /**************************************************************************** diff --git a/include/nuttx/sensors/ioctl.h b/include/nuttx/sensors/ioctl.h index 5cc397f76de..42099a63fd6 100644 --- a/include/nuttx/sensors/ioctl.h +++ b/include/nuttx/sensors/ioctl.h @@ -493,7 +493,7 @@ * Description: Sets the baud rate of the sensor. */ -#define SNIOC_SET_BAUD _SNIOC(0x00A4) +#define SNIOC_SET_BAUD _SNIOC(0x00A4) /* IOCTL commands unique to the L86XXX and other GNSS modules */ @@ -509,6 +509,15 @@ #define SNIOC_SET_NONWAKEUP _SNIOC(0x00A9) +/* Command: SNIOC_GNSS_SET_PRIORITY + * Description: Give GNSS priority over other radio activity (e.g. LTE idle) + * so it can acquire satellite window time. The decision of + * when to use it is left to the application. + * Argument: Non-zero enables GNSS priority, zero disables it. + */ + +#define SNIOC_GNSS_SET_PRIORITY _SNIOC(0x00AA) + /**************************************************************************** * Public types ****************************************************************************/ From 5976e86c6b576746a5a371b7d58f7590e47d8ad1 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 11 Jun 2026 20:13:54 +0200 Subject: [PATCH 079/268] arch/nrf91: add GPIOTE driver Port the GPIOTE driver from nrf53, which shares the same secure/non-secure TrustZone split. The non-secure application uses GPIOTE1 (the register base and interrupt are selected by the build security domain). This provides GPIO edge interrupts, e.g. for board buttons. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/hardware/nrf91_gpiote.h | 105 ++++ arch/arm/src/nrf91/nrf91_gpiote.c | 619 +++++++++++++++++++++ arch/arm/src/nrf91/nrf91_gpiote.h | 178 ++++++ 3 files changed, 902 insertions(+) create mode 100644 arch/arm/src/nrf91/hardware/nrf91_gpiote.h create mode 100644 arch/arm/src/nrf91/nrf91_gpiote.c create mode 100644 arch/arm/src/nrf91/nrf91_gpiote.h diff --git a/arch/arm/src/nrf91/hardware/nrf91_gpiote.h b/arch/arm/src/nrf91/hardware/nrf91_gpiote.h new file mode 100644 index 00000000000..4c19a09132e --- /dev/null +++ b/arch/arm/src/nrf91/hardware/nrf91_gpiote.h @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/nrf91/hardware/nrf91_gpiote.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIOTE_H +#define __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIOTE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/nrf91_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The nRF9160 has two GPIOTE instances: GPIOTE0 (secure) and GPIOTE1 + * (non-secure). Select the one belonging to the build's security domain. + */ + +#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE +# define NRF91_GPIOTE_BASE NRF91_GPIOTE1_BASE +#else +# define NRF91_GPIOTE_BASE NRF91_GPIOTE0_BASE +#endif + +/* Register offsets for GPIOTE **********************************************/ + +#define NRF91_GPIOTE_TASKS_OUT_OFFSET(x) (0x0000 + (0x04 * x)) /* TASKS_OUT[x] */ +#define NRF91_GPIOTE_TASKS_SET_OFFSET(x) (0x0030 + (0x04 * x)) /* TASKS_SET[x] */ +#define NRF91_GPIOTE_TASKS_CLR_OFFSET(x) (0x0060 + (0x04 * x)) /* TASKS_CLR[x] */ +#define NRF91_GPIOTE_EVENTS_IN_OFFSET(x) (0x0100 + (0x04 * x)) /* EVENTS_IN[x] */ +#define NRF91_GPIOTE_EVENTS_PORT_OFFSET 0x017c /* EVENTS_PORT */ +#define NRF91_GPIOTE_INTENSET_OFFSET 0x0304 /* INTENSET */ +#define NRF91_GPIOTE_INTENCLR_OFFSET 0x0308 /* INTENCLR */ +#define NRF91_GPIOTE_CONFIG_OFFSET(x) (0x0510 + (0x04 * x)) /* CONFIG[x] */ + +/* Register addresses for GPIOTE ********************************************/ + +#define NRF91_GPIOTE_TASKS_OUT(x) (NRF91_GPIOTE_BASE + NRF91_GPIOTE_TASKS_OUT_OFFSET(x)) +#define NRF91_GPIOTE_TASKS_SET(x) (NRF91_GPIOTE_BASE + NRF91_GPIOTE_TASKS_SET_OFFSET(x)) +#define NRF91_GPIOTE_TASKS_CLR(x) (NRF91_GPIOTE_BASE + NRF91_GPIOTE_TASKS_CLR_OFFSET(x)) +#define NRF91_GPIOTE_EVENTS_IN(x) (NRF91_GPIOTE_BASE + NRF91_GPIOTE_EVENTS_IN_OFFSET(x)) +#define NRF91_GPIOTE_EVENTS_PORT (NRF91_GPIOTE_BASE + NRF91_GPIOTE_EVENTS_PORT_OFFSET) +#define NRF91_GPIOTE_INTENSET (NRF91_GPIOTE_BASE + NRF91_GPIOTE_INTENSET_OFFSET) +#define NRF91_GPIOTE_INTENCLR (NRF91_GPIOTE_BASE + NRF91_GPIOTE_INTENCLR_OFFSET) +#define NRF91_GPIOTE_CONFIG(x) (NRF91_GPIOTE_BASE + NRF91_GPIOTE_CONFIG_OFFSET(x)) + +/* Register offsets for GPIOTE **********************************************/ + +/* EVENT_IN Register */ + +#define GPIOTE_EVENT_IN_EVENT (1 << 0) /* Bit 0: Event generated from pin */ + +/* INTENSET/INTENCLR Register */ + +#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */ + +#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT) +# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK) + +#define GPIOTE_INT_PORT_SHIFT 31 /* Bit 31: Enable interrupt for event PORT */ +#define GPIOTE_INT_PORT (1 << GPIOTE_INT_PORT_SHIFT) + +/* CONFIG Register */ + +#define GPIOTE_CONFIG_MODE_SHIFT 0 /* Bits 0-1: Mode */ +#define GPIOTE_CONFIG_MODE_MASK (0x3 << GPIOTE_CONFIG_MODE_SHIFT) +# define GPIOTE_CONFIG_MODE_DIS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 0: Disabled */ +# define GPIOTE_CONFIG_MODE_EV (0x1 << GPIOTE_CONFIG_MODE_SHIFT) /* 1: Event */ +# define GPIOTE_CONFIG_MODE_TS (0x3 << GPIOTE_CONFIG_MODE_SHIFT) /* 2: Task */ + +#define GPIOTE_CONFIG_PSEL_SHIFT (8) /* Bits 8-12: GPIO number */ +#define GPIOTE_CONFIG_PSEL_MASK (0x1f << GPIOTE_CONFIG_PSEL_SHIFT) +#define GPIOTE_CONFIG_PORT_SHIFT (13) /* Bit 13: GPIO port */ +#define GPIOTE_CONFIG_POL_SHIFT (16) /* Bits 16-17: Polarity */ +#define GPIOTE_CONFIG_POL_MASK (0x3 << GPIOTE_CONFIG_POL_SHIFT) +# define GPIOTE_CONFIG_POL_NONE (0x0 << GPIOTE_CONFIG_POL_SHIFT) /* 0: None */ +# define GPIOTE_CONFIG_POL_LTH (0x1 << GPIOTE_CONFIG_POL_SHIFT) /* 1: LoToHi */ +# define GPIOTE_CONFIG_POL_HTL (0x2 << GPIOTE_CONFIG_POL_SHIFT) /* 2: HiToLo */ +# define GPIOTE_CONFIG_POL_TG (0x3 << GPIOTE_CONFIG_POL_SHIFT) /* 3: Toggle */ + +#define GPIOTE_CONFIG_OUTINIT_SHIFT (20) /* Bit 20: Initial value */ + +#endif /* __ARCH_ARM_SRC_NRF91_HARDWARE_NRF91_GPIOTE_H */ diff --git a/arch/arm/src/nrf91/nrf91_gpiote.c b/arch/arm/src/nrf91/nrf91_gpiote.c new file mode 100644 index 00000000000..6f692b9efcf --- /dev/null +++ b/arch/arm/src/nrf91/nrf91_gpiote.c @@ -0,0 +1,619 @@ +/**************************************************************************** + * arch/arm/src/nrf91/nrf91_gpiote.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "nrf91_gpio.h" +#include "nrf91_gpiote.h" + +#include "hardware/nrf91_gpiote.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIOTE_CHANNELS 8 + +/* Use the GPIOTE instance (and its interrupt) for the build's security + * domain: GPIOTE1 when non-secure, GPIOTE0 when secure. The register base is + * selected in hardware/nrf91_gpiote.h. + */ + +#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE +# define NRF91_IRQ_GPIOTE NRF91_IRQ_GPIOTE1 +#else +# define NRF91_IRQ_GPIOTE NRF91_IRQ_GPIOTE0 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct nrf91_gpiote_callback_s +{ + xcpt_t callback; + void *arg; + uint32_t pinset; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Callbacks attached to each GPIOTE channel */ + +static struct nrf91_gpiote_callback_s g_gpiote_ch_callbacks[GPIOTE_CHANNELS]; + +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS +/* Callbacks attached to each GPIO pin */ + +static struct nrf91_gpiote_callback_s + g_gpiote_pin_callbacks[NRF91_GPIO_NPORTS][NRF91_GPIO_NPINS]; +#else +/* Callback for the PORT event */ + +static struct nrf91_gpiote_callback_s + g_gpiote_port_callback[NRF91_GPIO_NPORTS]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_gpiote_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void nrf91_gpiote_putreg(uint32_t offset, uint32_t value) +{ + putreg32(value, NRF91_GPIOTE_BASE + offset); +} + +/**************************************************************************** + * Name: nrf91_gpiote_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t nrf91_gpiote_getreg(uint32_t offset) +{ + return getreg32(NRF91_GPIOTE_BASE + offset); +} + +/**************************************************************************** + * Name: nrf91_gpiote_isr + * + * Description: + * Common GPIOTE interrupt handler + * + ****************************************************************************/ + +static int nrf91_gpiote_isr(int irq, void *context, void *arg) +{ + uint32_t regval = 0; + int ret = OK; + int i = 0; +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS + int j = 0; +#endif + + /* Scan all GPIOTE channels */ + + for (i = 0; i < GPIOTE_CHANNELS; i += 1) + { + /* Only if callback is registered */ + + if (g_gpiote_ch_callbacks[i].callback != NULL) + { + /* Get input event register */ + + regval = nrf91_gpiote_getreg(NRF91_GPIOTE_EVENTS_IN_OFFSET(i)); + if (regval == GPIOTE_EVENT_IN_EVENT) + { + /* Execute callback */ + + xcpt_t callback = g_gpiote_ch_callbacks[i].callback; + void *cbarg = g_gpiote_ch_callbacks[i].arg; + ret = callback(irq, context, cbarg); + + /* Clear event */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_EVENTS_IN_OFFSET(i), 0); + } + } + } + + /* Check for PORT event */ + + regval = nrf91_gpiote_getreg(NRF91_GPIOTE_EVENTS_PORT_OFFSET); + if (regval) + { + uint32_t addr = 0; + + /* Ack PORT event */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_EVENTS_PORT_OFFSET, 0); + + /* For each GPIO port, get LATCH register */ + + for (i = 0; i < NRF91_GPIO_NPORTS; i++) + { + switch (i) + { + case 0: + addr = NRF91_GPIO_P0_BASE + NRF91_GPIO_LATCH_OFFSET; + break; +#ifdef CONFIG_NRF91_HAVE_PORT1 + case 1: + addr = NRF91_GPIO_P1_BASE + NRF91_GPIO_LATCH_OFFSET; + break; +#endif + } + + /* Retrieve LATCH register */ + + regval = getreg32(addr); + + /* Clear LATCH register (this may set PORT again) */ + + putreg32(0xffffffff, addr); + +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS + /* Check for pins with DETECT bit high in LATCH register + * and dispatch callback if set + */ + + for (j = 0; j < NRF91_GPIO_NPINS && regval; j++) + { + if (regval & (1 << j) && g_gpiote_pin_callbacks[i][j].callback) + { + /* Run callback */ + + xcpt_t callback = g_gpiote_pin_callbacks[i][j].callback; + void *cbarg = g_gpiote_pin_callbacks[i][j].arg; + + ret = callback(irq, context, cbarg); + + /* Mark bit is as "visited", we can stop looping sooner + * this way + */ + + regval &= ~(1 << j); + } + } +#else + if (g_gpiote_port_callback[i].callback) + { + xcpt_t callback = g_gpiote_port_callback[i].callback; + void *cbarg = g_gpiote_port_callback[i].arg; + + ret = callback(irq, context, cbarg); + } +#endif + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS +/**************************************************************************** + * Name: nrf91_gpiote_set_pin_event + * + * Description: + * Sets/clears a handler for a given pin for the GPIO PORT event. This + * will mean edge-sensitive or level-sensitive according to GPIO detect + * mode configuration for the port (see nrf91_gpio_detectmode()). Pin + * will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH + * (set via nrf91_gpio_config()). + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + ****************************************************************************/ + +void nrf91_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, void *arg) +{ + int pin = 0; + int port = 0; + irqstate_t flags; + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; +#ifdef CONFIG_NRF91_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; +#endif + + flags = enter_critical_section(); + + g_gpiote_pin_callbacks[port][pin].callback = func; + g_gpiote_pin_callbacks[port][pin].arg = arg; + + leave_critical_section(flags); +} +#else +/**************************************************************************** + * Name: nrf91_gpiote_set_port_event + * + * Description: + * Sets/clears the handler for the GPIO PORT event. + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO port will be extracted from this parameter + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + ****************************************************************************/ + +void nrf91_gpiote_set_port_event(uint32_t pinset, xcpt_t func, void *arg) +{ + int port = 0; + irqstate_t flags; + +#ifdef CONFIG_NRF91_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; +#endif + + flags = enter_critical_section(); + + g_gpiote_port_callback[port].callback = func; + g_gpiote_port_callback[port].arg = arg; + + if (func) + { + /* Enable the ISR */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT); + } + else + { +#if NRF91_GPIO_NPORTS > 1 + /* Check if we can disable the ISR */ + + int i; + + for (i = 0; i < NRF91_GPIO_NPORTS; i++) + { + if (g_gpiote_port_callback[port].callback) + { + break; + } + } + + if (i == NRF91_GPIO_NPORTS) + { + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT); + } +#else + /* Disable the ISR */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENCLR_OFFSET, GPIOTE_INT_PORT); +#endif + } + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: nrf91_gpiote_set_ch_event + * + * Description: + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the corresponding channel events. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - channel: GPIOTE channel used to capture events + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + ****************************************************************************/ + +void nrf91_gpiote_set_ch_event(uint32_t pinset, int channel, + bool risingedge, bool fallingedge, + xcpt_t func, void *arg) +{ + int pin = 0; +#ifdef CONFIG_NRF91_HAVE_PORT1 + int port = 0; +#endif + uint32_t regval = 0; + irqstate_t flags; + + DEBUGASSERT(channel < GPIOTE_CHANNELS); + + /* NOTE: GPIOTE module has priority over GPIO module + * so GPIO configuration will be ignored + */ + + flags = enter_critical_section(); + + if (func) + { + /* Select EVENT mode */ + + regval |= GPIOTE_CONFIG_MODE_EV; + + /* Select GPIOTE pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + regval |= (pin << GPIOTE_CONFIG_PSEL_SHIFT); + +#ifdef CONFIG_NRF91_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + regval |= (port << GPIOTE_CONFIG_PORT_SHIFT); +#endif + + /* Select polarity */ + + if (risingedge == true && fallingedge == true) + { + regval |= GPIOTE_CONFIG_POL_TG; + } + else if (risingedge == true) + { + regval |= GPIOTE_CONFIG_POL_LTH; + } + else if (fallingedge == true) + { + regval |= GPIOTE_CONFIG_POL_HTL; + } + + /* Enable callback for channel */ + + g_gpiote_ch_callbacks[channel].callback = func; + g_gpiote_ch_callbacks[channel].arg = arg; + + /* Enable interrupt for given event */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENSET_OFFSET, + GPIOTE_INT_IN(channel)); + } + else + { + /* Leave register as zero (disabled mode) */ + + /* Disable interrupt for given event */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENCLR_OFFSET, + GPIOTE_INT_IN(channel)); + + /* Remove callback configuration */ + + g_gpiote_ch_callbacks[channel].callback = NULL; + g_gpiote_ch_callbacks[channel].arg = NULL; + } + + /* Write CONFIG register */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_CONFIG_OFFSET(channel), regval); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: nrf91_gpiote_set_event + * + * Description: + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the first available GPIOTE channel. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int nrf91_gpiote_set_event(uint32_t pinset, + bool risingedge, bool fallingedge, + xcpt_t func, void *arg) +{ + irqstate_t flags; + int ret = -ENOMEM; + int i = 0; + + flags = enter_critical_section(); + + /* Get free channel or channel already used by pinset */ + + for (i = 0; i < GPIOTE_CHANNELS; i++) + { + if (g_gpiote_ch_callbacks[i].callback == NULL || + g_gpiote_ch_callbacks[i].pinset == pinset) + { + g_gpiote_ch_callbacks[i].pinset = pinset; + + /* Configure channel */ + + nrf91_gpiote_set_ch_event(pinset, i, + risingedge, fallingedge, + func, arg); + + /* Return the channel index */ + + ret = i; + + break; + } + } + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: nrf91_gpio_set_task + * + * Description: + * Configure GPIO in TASK mode (to be controlled via tasks). + * Note that a pin can only be either in TASK or EVENT mode (set by + * nrf91_gpiosetevent with event set to true). Also, once set to TASK mode, + * pin control is only possible via tasks on the via nrf91_gpio_write and + * will automatically set the output mode. + * Finally, a given pin should only be assigned to a given channel. + * + * Input Parameters: + * - pinset: gpio pin configuration (only port + pin is important here) + * - channel: the GPIOTE channel used to control the given pin + * - output_high: set pin initially to output HIGH or LOW. + * - outcfg: configure pin behavior one OUT task is triggered + * + ****************************************************************************/ + +void nrf91_gpiote_set_task(uint32_t pinset, int channel, + bool output_high, + enum nrf91_gpiote_outcfg_e outcfg) +{ + uint32_t regval; + int pin; +#ifdef CONFIG_NRF91_HAVE_PORT1 + int port; +#endif + + /* Select GPIOTE pin */ + + pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + regval = (pin << GPIOTE_CONFIG_PSEL_SHIFT); + +#ifdef CONFIG_NRF91_HAVE_PORT1 + port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + regval |= (port << GPIOTE_CONFIG_PORT_SHIFT); +#endif + + /* Select TASK mode */ + + regval |= GPIOTE_CONFIG_MODE_TS; + + /* Select pin number */ + + regval |= (pin << GPIOTE_CONFIG_PSEL_SHIFT); + + /* Select initial output */ + + if (output_high) + { + regval |= (1 << GPIOTE_CONFIG_OUTINIT_SHIFT); + } + + /* Set polarity mode */ + + switch (outcfg) + { + case NRF91_GPIOTE_SET: + regval |= GPIOTE_CONFIG_POL_LTH; + break; + case NRF91_GPIOTE_CLEAR: + regval |= GPIOTE_CONFIG_POL_HTL; + break; + case NRF91_GPIOTE_TOGGLE: + regval |= GPIOTE_CONFIG_POL_TG; + break; + } + + /* Write register */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_CONFIG_OFFSET(channel), regval); +} + +/**************************************************************************** + * Name: nrf91_gpiote_init + * + * Description: + * Initialize GPIOTE + * + ****************************************************************************/ + +int nrf91_gpiote_init(void) +{ + /* Clear LATCH register(s) */ + + putreg32(0, NRF91_GPIO_P0_BASE + NRF91_GPIO_LATCH_OFFSET); + +#ifdef CONFIG_NRF91_HAVE_PORT1 + putreg32(0, NRF91_GPIO_P1_BASE + NRF91_GPIO_LATCH_OFFSET); +#endif + + /* Reset GPIOTE data */ + + memset(&g_gpiote_ch_callbacks, 0, sizeof(g_gpiote_ch_callbacks)); + +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS + memset(&g_gpiote_pin_callbacks, 0, sizeof(g_gpiote_pin_callbacks)); + + /* Enable PORT event interrupt */ + + nrf91_gpiote_putreg(NRF91_GPIOTE_INTENSET_OFFSET, GPIOTE_INT_PORT); +#else + memset(&g_gpiote_port_callback, 0, sizeof(g_gpiote_port_callback)); +#endif + + /* Attach GPIOTE interrupt handler */ + + irq_attach(NRF91_IRQ_GPIOTE, nrf91_gpiote_isr, NULL); + up_enable_irq(NRF91_IRQ_GPIOTE); + + return OK; +} diff --git a/arch/arm/src/nrf91/nrf91_gpiote.h b/arch/arm/src/nrf91/nrf91_gpiote.h new file mode 100644 index 00000000000..ed82dd3759c --- /dev/null +++ b/arch/arm/src/nrf91/nrf91_gpiote.h @@ -0,0 +1,178 @@ +/**************************************************************************** + * arch/arm/src/nrf91/nrf91_gpiote.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF91_NRF91_GPIOTE_H +#define __ARCH_ARM_SRC_NRF91_NRF91_GPIOTE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "chip.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* GPIOTE OUT task configuration */ + +enum nrf91_gpiote_outcfg_e +{ + NRF91_GPIOTE_SET = 0, + NRF91_GPIOTE_CLEAR = 1, + NRF91_GPIOTE_TOGGLE = 2, +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf91_gpiote_set_ch_event + * + * Description: + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the corresponding channel events. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - channel: GPIOTE channel used to capture events + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + ****************************************************************************/ + +void nrf91_gpiote_set_ch_event(uint32_t pinset, int channel, + bool risingedge, bool fallingedge, + xcpt_t func, void *arg); + +/**************************************************************************** + * Name: nrf91_gpiote_set_event + * + * Description: + * Configures a GPIOTE channel in EVENT mode, assigns it to a given pin + * and sets a handler for the first available GPIOTE channel. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int nrf91_gpiote_set_event(uint32_t pinset, + bool risingedge, bool fallingedge, + xcpt_t func, void *arg); + +#ifdef CONFIG_NRF91_PER_PIN_INTERRUPTS +/**************************************************************************** + * Name: nrf91_gpiote_set_pin_event + * + * Description: + * Sets/clears a handler for a given pin for the GPIO PORT event. This + * will mean edge-sensitive or level-sensitive according to GPIO detect + * mode configuration for the port (see nrf91_gpio_detectmode()). Pin + * will be sensitive to high/low according to GPIO_SENSE_LOW/HIGH + * (set via nrf91_gpio_config()). + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +void nrf91_gpiote_set_pin_event(uint32_t pinset, xcpt_t func, void *arg); +#else + +/**************************************************************************** + * Name: nrf91_gpiote_set_port_event + * + * Description: + * Sets/clears the handler for the GPIO PORT event. + * + * The passed handler will be invoked from the main ISR for the PORT + * event and will take care of clearing the LATCH register. + * + * Input Parameters: + * - pinset: GPIO port will be extracted from this parameter + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + ****************************************************************************/ + +void nrf91_gpiote_set_port_event(uint32_t pinset, xcpt_t func, void *arg); + +#endif + +/**************************************************************************** + * Name: nrf91_gpio_set_task + * + * Description: + * Configure GPIO in TASK mode (to be controlled via tasks). + * Note that a pin can only be either in TASK or EVENT mode (set by + * nrf91_gpiosetevent with event set to true). Also, once set to TASK mode, + * pin control is only possible via tasks on the via nrf91_gpio_write and + * will automatically set the output mode. + * Finally, a given pin should only be assigned to a given channel. + * + * Input Parameters: + * - pinset: gpio pin configuration (only port + pin is important here) + * - channel: the GPIOTE channel used to control the given pin + * - output_high: set pin initially to output HIGH or LOW. + * - outcfg: configure pin behavior one OUT task is triggered + * + ****************************************************************************/ + +void nrf91_gpio_set_task(uint32_t pinset, int channel, + bool output_high, enum nrf91_gpiote_outcfg_e outcfg); + +/**************************************************************************** + * Name: nrf91_gpiote_init + * + * Description: + * Initialize GPIOTE + * + ****************************************************************************/ + +int nrf91_gpiote_init(void); + +#endif /* __ARCH_ARM_SRC_NRF91_NRF91_GPIOTE_H */ From a4c47746124e120e933693eb86dc1c54b499fa07 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 11 Jun 2026 20:14:46 +0200 Subject: [PATCH 080/268] arch/nrf91: grant GPIOTE1 to the non-secure domain Add CONFIG_NRF91_GPIOTE1_NS so the secure firmware can hand the non-secure GPIOTE instance to the application, allowing a non-secure app to use GPIO interrupts. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/Kconfig | 7 +++++++ arch/arm/src/nrf91/nrf91_spu.c | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/src/nrf91/Kconfig b/arch/arm/src/nrf91/Kconfig index 5e9d77b84e9..13591ed1720 100644 --- a/arch/arm/src/nrf91/Kconfig +++ b/arch/arm/src/nrf91/Kconfig @@ -258,6 +258,13 @@ config NRF91_GPIO0_NS bool "GPIO0 non-secure" default n +config NRF91_GPIOTE1_NS + bool "GPIOTE1 non-secure" + default n + ---help--- + Grant the non-secure GPIOTE instance (GPIOTE1) to the non-secure + domain, so a non-secure application can use GPIO interrupts. + config NRF91_NVMC_NS bool "NVMC non-secure" default n diff --git a/arch/arm/src/nrf91/nrf91_spu.c b/arch/arm/src/nrf91/nrf91_spu.c index 373fe8eedd8..33317de780e 100644 --- a/arch/arm/src/nrf91/nrf91_spu.c +++ b/arch/arm/src/nrf91/nrf91_spu.c @@ -87,6 +87,11 @@ static void nrf91_spu_periph(void) SPU_PERIPHID_PERM_SECATTR, 0); #endif +#ifdef CONFIG_NRF91_GPIOTE1_NS + modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_GPIOTE1_ID), + SPU_PERIPHID_PERM_SECATTR, 0); +#endif + #ifdef CONFIG_NRF91_NVMC_NS modifyreg32(NRF91_SPU_PERIPHIDPERM(NRF91_NVMC_ID), SPU_PERIPHID_PERM_SECATTR, 0); From 3271a441388280f60de37df6ef9dc1fb9fe7e573 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 11 Jun 2026 20:14:47 +0200 Subject: [PATCH 081/268] boards/nrf91/thingy91: ARCH_HAVE_IRQBUTTONS support select ARCH_HAVE_IRQBUTTONS so ARCH_IRQBUTTONS can be enabled. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_gpiote.c | 4 ++-- boards/Kconfig | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/nrf91/nrf91_gpiote.c b/arch/arm/src/nrf91/nrf91_gpiote.c index 6f692b9efcf..36fb06b5e3c 100644 --- a/arch/arm/src/nrf91/nrf91_gpiote.c +++ b/arch/arm/src/nrf91/nrf91_gpiote.c @@ -50,8 +50,8 @@ #define GPIOTE_CHANNELS 8 /* Use the GPIOTE instance (and its interrupt) for the build's security - * domain: GPIOTE1 when non-secure, GPIOTE0 when secure. The register base is - * selected in hardware/nrf91_gpiote.h. + * domain: GPIOTE1 when non-secure, GPIOTE0 when secure. The register base + * is selected in hardware/nrf91_gpiote.h. */ #ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE diff --git a/boards/Kconfig b/boards/Kconfig index 2a6a401dd15..5196f18cbc2 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1455,6 +1455,7 @@ config ARCH_BOARD_THINGY91 bool "Nordic Thingy:91 cellular IoT prototyping platform - nRF9160" depends on ARCH_CHIP_NRF91 select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS ---help--- This option selects the Thingy:91 cellular IoT prototyping platform - nRF9160 chip From c22a3d67d6da5a4079de1754dd30e4237eb60ed0 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 9 Jun 2026 09:00:52 +0200 Subject: [PATCH 082/268] arch/stm32: add common STM32 Kconfig support Add the shared STM32 Kconfig include and introduce the hidden common ARCH_CHIP_STM32 selector used by concrete STM32 families. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 3 + arch/arm/src/common/stm32/Kconfig | 1307 +++++++++++++++++++++++++++++ arch/arm/src/stm32/Kconfig | 1034 +---------------------- 3 files changed, 1335 insertions(+), 1009 deletions(-) create mode 100644 arch/arm/src/common/stm32/Kconfig diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 4eb585a6d76..f5d75cd9c05 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1839,6 +1839,9 @@ endif if ARCH_CHIP_STM32WL5 source "arch/arm/src/stm32wl5/Kconfig" endif +if ARCH_CHIP_STM32 +source "arch/arm/src/common/stm32/Kconfig" +endif if ARCH_CHIP_STR71X source "arch/arm/src/str71x/Kconfig" endif diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig new file mode 100644 index 00000000000..37c61bcc2c9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig @@ -0,0 +1,1307 @@ +# +# Common STM32 Kconfig options shared by STM32 families. +# + +menu "Common STM32 Configuration Options" + depends on ARCH_CHIP_STM32 + +config STM32_SERIALDRIVER + bool + +config STM32_1WIREDRIVER + bool + +config STM32_HCIUART + bool + +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice + +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration + +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration + +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration + +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration + +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source + +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "CAN character driver or SocketCAN support" + depends on STM32_CAN + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32F7 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32F7 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support + +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support + +choice + prompt "FDCAN1 frame format" + depends on STM32_FDCAN1 + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format + +choice + prompt "FDCAN1 mode" + depends on STM32_FDCAN1 + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode + +choice + prompt "FDCAN2 frame format" + depends on STM32_FDCAN2 + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format + +choice + prompt "FDCAN2 mode" + depends on STM32_FDCAN2 + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode + +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format + +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format + +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice + +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" + +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "Override Flash Size Designator" + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32F series parts numbering (sans the package type) ends with a number or letter + that designates the FLASH size. + + Designator Size in KiB + 4 16 + 6 32 + 8 64 + B 128 + C 256 + D 384 + E 512 + F 768 + G 1024 + I 2048 + + This configuration option defaults to using the configuration based on that designator + or the default smaller size if there is no last character designator is present in the + STM32 Chip Selection. + + Examples: + If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of + the part with a 2048 KiB Flash is released in the future one could simply select + the 'I' designator here. + +config STM32_FLASH_OVERRIDE_4 + bool "4 16KiB" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_D + bool "D 384KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_F + bool "F 768KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_C_256 + bool "C 256 KB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320 KB" + +config STM32_FLASH_OVERRIDE_E_512 + bool "E 512 KB" + +config STM32_FLASH_OVERRIDE_Y_640 + bool "Y 640 KB" + +config STM32_FLASH_OVERRIDE_G_1024 + bool "G 1024 KB" + +endchoice # Override Flash Size Designator + +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +choice + prompt "Transfer technique" + depends on STM32_QSPI + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice + +choice + prompt "Bank selection" + depends on STM32_QSPI + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice + +choice + prompt "DMA Priority" + depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice + +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_HAVE_ADC1_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_HAVE_ADC2_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_HAVE_ADC3_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice + +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice +endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index f9666d1c84e..b0315f1a414 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1207,77 +1207,41 @@ config ARCH_CHIP_STM32G474V endchoice -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_CONFIG_DEFAULT - depends on ARCH_CHIP_STM32 - ---help--- - STM32F/STM32G/STM32L series parts numbering (sans the package type) - ends with a number or letter that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - Z 192 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - If the STM32F407VE is chosen, the Flash configuration would be - 'E', if a variant of the part with a 2048 KiB Flash is released - in the future one could simply select the 'I' designator here. - - If an STM32F42xxx or Series parts is chosen the default Flash - configuration will be 'G' and can be set herein to 'I' to choose - the larger FLASH part. - config STM32_FLASH_CONFIG_DEFAULT - bool "Default" + bool config STM32_FLASH_CONFIG_4 - bool "4 16KiB" + bool config STM32_FLASH_CONFIG_6 - bool "6 32KiB" + bool config STM32_FLASH_CONFIG_8 - bool "8 64KiB" + bool config STM32_FLASH_CONFIG_B - bool "B 128KiB" + bool config STM32_FLASH_CONFIG_Z - bool "Z 192KiB" + bool config STM32_FLASH_CONFIG_C - bool "C 256KiB" + bool config STM32_FLASH_CONFIG_D - bool "D 384KiB" + bool config STM32_FLASH_CONFIG_E - bool "E 512KiB" + bool config STM32_FLASH_CONFIG_F - bool "F 768KiB" + bool config STM32_FLASH_CONFIG_G - bool "G 1024KiB" + bool config STM32_FLASH_CONFIG_I - bool "I 2048KiB" - -endchoice + bool # This is really 15XX/16XX, but we treat the two the same. config STM32_STM32L15XX @@ -2260,6 +2224,10 @@ config STM32_HAVE_LTDC bool default n +config STM32_HAVE_USART2 + bool + default n + config STM32_HAVE_USART3 bool default n @@ -2504,6 +2472,10 @@ config STM32_HAVE_ETHMAC bool default n +config STM32_HAVE_I2C1 + bool + default n + config STM32_HAVE_I2C2 bool default n @@ -2524,6 +2496,10 @@ config STM32_HAVE_LPUART1 bool default n +config STM32_HAVE_SPI1 + bool + default n + config STM32_HAVE_SPI2 bool default n @@ -3709,26 +3685,6 @@ config STM32_FLASH_PREFETCH on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch properly and enabling this option may interfere with ADC accuracy. -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG bool "Disable IDLE Sleep (WFI) in debug mode" default n @@ -6131,34 +6087,6 @@ config STM32_TIM1_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM1 ADC channel" - default STM32_TIM1_ADC1 - depends on STM32_TIM1_ADC - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - config STM32_TIM2_ADC bool "TIM2 ADC" default n @@ -6173,34 +6101,6 @@ config STM32_TIM2_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM2 ADC channel" - default STM32_TIM2_ADC1 - depends on STM32_TIM2_ADC - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - config STM32_TIM3_ADC bool "TIM3 ADC" default n @@ -6215,34 +6115,6 @@ config STM32_TIM3_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM3 ADC channel" - default STM32_TIM3_ADC1 - depends on STM32_TIM3_ADC - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - config STM32_TIM4_ADC bool "TIM4 ADC" default n @@ -6257,34 +6129,6 @@ config STM32_TIM4_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM4 ADC channel" - default STM32_TIM4_ADC1 - depends on STM32_TIM4_ADC - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - config STM32_TIM5_ADC bool "TIM5 ADC" default n @@ -6299,34 +6143,6 @@ config STM32_TIM5_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM5 ADC channel" - default STM32_TIM5_ADC1 - depends on STM32_TIM5_ADC - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - config STM32_TIM8_ADC bool "TIM8 ADC" default n @@ -6341,34 +6157,6 @@ config STM32_TIM8_ADC for used by the ADC, but then you also have to configure which ADC channel it is assigned to. -choice - prompt "Select TIM8 ADC channel" - default STM32_TIM8_ADC1 - depends on STM32_TIM8_ADC - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - config STM32_HAVE_ADC1_TIMER bool @@ -6443,23 +6231,6 @@ config STM32_TIM1_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM1 DAC channel" - default STM32_TIM1_DAC1 - depends on STM32_TIM1_DAC - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - config STM32_TIM2_DAC bool "TIM2 DAC" default n @@ -6474,23 +6245,6 @@ config STM32_TIM2_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM2 DAC channel" - default STM32_TIM2_DAC1 - depends on STM32_TIM2_DAC - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - config STM32_TIM3_DAC bool "TIM3 DAC" default n @@ -6505,23 +6259,6 @@ config STM32_TIM3_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM3 DAC channel" - default STM32_TIM3_DAC1 - depends on STM32_TIM3_DAC - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - config STM32_TIM4_DAC bool "TIM4 DAC" default n @@ -6536,23 +6273,6 @@ config STM32_TIM4_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM4 DAC channel" - default STM32_TIM4_DAC1 - depends on STM32_TIM4_DAC - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - config STM32_TIM5_DAC bool "TIM5 DAC" default n @@ -6567,23 +6287,6 @@ config STM32_TIM5_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM5 DAC channel" - default STM32_TIM5_DAC1 - depends on STM32_TIM5_DAC - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - config STM32_TIM6_DAC bool "TIM6 DAC" default n @@ -6598,23 +6301,6 @@ config STM32_TIM6_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM6 DAC channel" - default STM32_TIM6_DAC1 - depends on STM32_TIM6_DAC - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - config STM32_TIM7_DAC bool "TIM7 DAC" default n @@ -6629,23 +6315,6 @@ config STM32_TIM7_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM7 DAC channel" - default STM32_TIM7_DAC1 - depends on STM32_TIM7_DAC - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - config STM32_TIM8_DAC bool "TIM8 DAC" default n @@ -6660,23 +6329,6 @@ config STM32_TIM8_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM8 DAC channel" - default STM32_TIM8_DAC1 - depends on STM32_TIM8_DAC - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - config STM32_TIM9_DAC bool "TIM9 DAC" default n @@ -6691,23 +6343,6 @@ config STM32_TIM9_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM9 DAC channel" - default STM32_TIM9_DAC1 - depends on STM32_TIM9_DAC - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - config STM32_TIM10_DAC bool "TIM10 DAC" default n @@ -6722,23 +6357,6 @@ config STM32_TIM10_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM10 DAC channel" - default STM32_TIM10_DAC1 - depends on STM32_TIM10_DAC - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - config STM32_TIM11_DAC bool "TIM11 DAC" default n @@ -6753,23 +6371,6 @@ config STM32_TIM11_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM11 DAC channel" - default STM32_TIM11_DAC1 - depends on STM32_TIM11_DAC - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - config STM32_TIM12_DAC bool "TIM12 DAC" default n @@ -6784,23 +6385,6 @@ config STM32_TIM12_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM12 DAC channel" - default STM32_TIM12_DAC1 - depends on STM32_TIM12_DAC - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - config STM32_TIM13_DAC bool "TIM13 DAC" default n @@ -6815,23 +6399,6 @@ config STM32_TIM13_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM13 DAC channel" - default STM32_TIM13_DAC1 - depends on STM32_TIM13_DAC - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - config STM32_TIM14_DAC bool "TIM14 DAC" default n @@ -6846,23 +6413,6 @@ config STM32_TIM14_DAC for used by the DAC, but then you also have to configure which DAC channel it is assigned to. -choice - prompt "Select TIM14 DAC channel" - default STM32_TIM14_DAC1 - depends on STM32_TIM14_DAC - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - config STM32_TIM1_CAP bool "TIM1 Capture" default n @@ -9705,28 +9255,6 @@ menu "U[S]ART Configuration" comment "U[S]ART Device Configuration" -choice - prompt "USART1 Driver Configuration" - default STM32_USART1_SERIALDRIVER - depends on STM32_USART1 - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration - if STM32_USART1_SERIALDRIVER config USART1_RS485 @@ -9798,28 +9326,6 @@ config STM32_HCIUART1_RXDMA endif # STM32_USART1_HCIUART -choice - prompt "USART2 Driver Configuration" - default STM32_USART2_SERIALDRIVER - depends on STM32_USART2 - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration - if STM32_USART2_SERIALDRIVER config USART2_RS485 @@ -9891,28 +9397,6 @@ config STM32_HCIUART2_RXDMA endif # STM32_USART2_HCIUART -choice - prompt "USART3 Driver Configuration" - default STM32_USART3_SERIALDRIVER - depends on STM32_USART3 - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration - if STM32_USART3_SERIALDRIVER config USART3_RS485 @@ -9984,23 +9468,6 @@ config STM32_HCIUART3_RXDMA endif # STM32_USART3_HCIUART -choice - prompt "UART4 Driver Configuration" - default STM32_UART4_SERIALDRIVER - depends on STM32_UART4 - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration - if STM32_UART4_SERIALDRIVER config UART4_RS485 @@ -10036,23 +9503,6 @@ config UART4_TXDMA endif # STM32_UART4_SERIALDRIVER -choice - prompt "UART5 Driver Configuration" - default STM32_UART5_SERIALDRIVER - depends on STM32_UART5 - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration - if STM32_UART5_SERIALDRIVER config UART5_RS485 @@ -10088,28 +9538,6 @@ config UART5_TXDMA endif # STM32_UART5_SERIALDRIVER -choice - prompt "USART6 Driver Configuration" - default STM32_USART6_SERIALDRIVER - depends on STM32_USART6 - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration - if STM32_USART6_SERIALDRIVER config USART6_RS485 @@ -10367,19 +9795,6 @@ config STM32_HCIUART8_RXDMA endif # STM32_UART8_HCIUART -choice - prompt "LPUART1 Driver Configuration" - default STM32_LPUART1_SERIALDRIVER - depends on STM32_LPUART1 - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - if STM32_LPUART1_SERIALDRIVER config LPUART1_RS485 @@ -10919,26 +10334,6 @@ config STM32_RTC_MAGIC_TIME_SET Value used as Magic to determine if the RTC has been setup and has time set -choice - prompt "RTC clock source" - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source endmenu # RTC configuration menu "Ethernet MAC configuration" @@ -10966,38 +10361,6 @@ config STM32_MII ---help--- Support Ethernet MII interface. -choice - prompt "MII clock configuration" - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_MII - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice - config STM32_AUTONEG bool "Use autonegotiation" default y @@ -11147,38 +10510,6 @@ config STM32_RMII bool default !STM32_MII -choice - prompt "RMII clock configuration" - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - depends on STM32_RMII - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] - -endchoice - config STM32_ETHMAC_REGDEBUG bool "Register-Level Debug" default n @@ -11340,21 +10671,6 @@ config STM32_USB_ITRMP menu "CAN driver configuration" depends on STM32_CAN -choice - prompt "CAN character driver or SocketCAN support" - default STM32_CAN_CHARDRIVER - -config STM32_CAN_CHARDRIVER - bool "STM32 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - config STM32_CAN1_BAUD int "CAN1 BAUD" default 250000 @@ -11394,22 +10710,6 @@ endmenu # "CAN driver configuration" menu "FDCAN driver configuration" depends on STM32_FDCAN -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32_FDCAN_CHARDRIVER - -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - config STM32_FDCAN_REGDEBUG bool "CAN Register level debug" depends on DEBUG_CAN_INFO @@ -11425,45 +10725,6 @@ config STM32_FDCAN_QUEUE_MODE menu "FDCAN1 device driver options" depends on STM32_FDCAN1 -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 - -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC - -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - config STM32_FDCAN1_LOOPBACK bool "Enable FDCAN1 loopback mode" default n @@ -11539,45 +10800,6 @@ endmenu # FDCAN1 device driver options menu "FDCAN2 device driver options" depends on STM32_FDCAN2 -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 - -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - config STM32_FDCAN2_LOOPBACK bool "Enable FDCAN2 loopback mode" default n @@ -11839,44 +11061,6 @@ config STM32_LTDC_L1_COLOR hex "Layer L1 default color" default 0x00000000 -choice - prompt "Layer 1 color format" - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format - config STM32_LTDC_L2 bool "Enable Layer 2 support" default y @@ -11895,44 +11079,6 @@ config STM32_LTDC_L2_CHROMAKEY hex "Layer L2 initial chroma key" default 0x00000000 -choice - prompt "Layer 2 (top layer) color format" - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - depends on STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32_LTDC_L2_AL44 - depends on STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32_LTDC_L2_AL88 - depends on STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32_LTDC_L2_RGB565 - depends on STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32_LTDC_L2_ARGB4444 - depends on STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32_LTDC_L2_ARGB1555 - depends on STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32_LTDC_L2_RGB888 - depends on STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32_LTDC_L2_ARGB8888 - depends on STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - endif # STM32_LTDC_L2 config STM32_FB_CMAP @@ -12189,71 +11335,13 @@ config STM32_QENCODER_FILTER bool "Enable filtering on STM32 QEncoder input" default y -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32_QENCODER_SAMPLE_FDTS_4 - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32_QENCODER_FILTER - prompt "Input channel event count" - default STM32_QENCODER_SAMPLE_EVENT_6 - -config STM32_QENCODER_SAMPLE_EVENT_1 - depends on STM32_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32_QENCODER_SAMPLE_EVENT_2 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32_QENCODER_SAMPLE_EVENT_4 - depends on STM32_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32_QENCODER_SAMPLE_EVENT_5 - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32_QENCODER_SAMPLE_EVENT_6 - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32_QENCODER_SAMPLE_EVENT_8 - depends on !STM32_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - endmenu menuconfig STM32_FOC bool "STM32 lower-half FOC support" default n select ARCH_IRQPRIO + select STM32_ADC select STM32_PWM_MULTICHAN select STM32_PWM_LL_OPS select STM32_ADC_LL_OPS @@ -12278,84 +11366,12 @@ config STM32_FOC_FOC1 ---help--- Enable support for FOC1 device that uses TIM8 for PWM modulation -choice - prompt "FOC ADC trigger selection" - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - if STM32_FOC_FOC0 -choice - prompt "FOC0 device ADC selection" - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - endif # STM32_FOC_FOC0 if STM32_FOC_FOC1 -choice - prompt "FOC1 device ADC selection" - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - endif # STM32_FOC_FOC1 config STM32_FOC_HAS_PWM_COMPLEMENTARY From f08267ce4cb2e79540fa20198bab94aebcd98a1d Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 083/268] !arch/stm32f0l0g0: use common STM32 Kconfig symbols BREAKING CHANGE: STM32F0/L0/G0/C0 Kconfig symbols were renamed from CONFIG_STM32F0L0G0_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 4 + arch/arm/include/stm32f0l0g0/stm32g0_irq.h | 4 +- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 40 +- arch/arm/src/stm32f0l0g0/Kconfig | 2545 ++++++++--------- arch/arm/src/stm32f0l0g0/Make.defs | 40 +- arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h | 6 +- .../src/stm32f0l0g0/hardware/stm32_dmamux.h | 4 +- .../stm32f0l0g0/hardware/stm32_memorymap.h | 8 +- .../src/stm32f0l0g0/hardware/stm32_pinmap.h | 8 +- arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h | 8 +- arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h | 2 +- .../arm/src/stm32f0l0g0/hardware/stm32_uart.h | 4 +- .../src/stm32f0l0g0/hardware/stm32_usbdev.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_adc.c | 116 +- arch/arm/src/stm32f0l0g0/stm32_adc.h | 118 +- arch/arm/src/stm32f0l0g0/stm32_dma.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_dma.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_dma_v1.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c | 60 +- arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c | 6 +- arch/arm/src/stm32f0l0g0/stm32_fdcan.c | 64 +- arch/arm/src/stm32f0l0g0/stm32_fdcan.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c | 66 +- arch/arm/src/stm32f0l0g0/stm32_flash.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_gpio.c | 8 +- arch/arm/src/stm32f0l0g0/stm32_gpio.h | 2 +- arch/arm/src/stm32f0l0g0/stm32_hsi48.h | 4 +- arch/arm/src/stm32f0l0g0/stm32_i2c.c | 92 +- arch/arm/src/stm32f0l0g0/stm32_i2c.h | 8 +- arch/arm/src/stm32f0l0g0/stm32_idle.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_irq.c | 2 +- arch/arm/src/stm32f0l0g0/stm32_lowputc.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c | 10 +- arch/arm/src/stm32f0l0g0/stm32_pulsecount.c | 22 +- arch/arm/src/stm32f0l0g0/stm32_pwm.c | 178 +- arch/arm/src/stm32f0l0g0/stm32_pwm.h | 372 ++- arch/arm/src/stm32f0l0g0/stm32_pwr.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_pwr.h | 12 +- arch/arm/src/stm32f0l0g0/stm32_qencoder.c | 170 +- arch/arm/src/stm32f0l0g0/stm32_qencoder.h | 34 +- arch/arm/src/stm32f0l0g0/stm32_rcc.c | 14 +- arch/arm/src/stm32f0l0g0/stm32_rng.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_serial.c | 4 +- arch/arm/src/stm32f0l0g0/stm32_serial_v1.c | 76 +- arch/arm/src/stm32f0l0g0/stm32_serial_v2.c | 70 +- arch/arm/src/stm32f0l0g0/stm32_spi.c | 86 +- arch/arm/src/stm32f0l0g0/stm32_spi.h | 12 +- arch/arm/src/stm32f0l0g0/stm32_tim.c | 300 +- .../arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32f0l0g0/stm32_timerisr.c | 6 +- arch/arm/src/stm32f0l0g0/stm32_uart.h | 236 +- arch/arm/src/stm32f0l0g0/stm32_usbdev.c | 14 +- arch/arm/src/stm32f0l0g0/stm32_wdg.h | 4 +- arch/arm/src/stm32f0l0g0/stm32c0_rcc.c | 54 +- arch/arm/src/stm32f0l0g0/stm32f0_rcc.c | 74 +- arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c | 8 +- arch/arm/src/stm32f0l0g0/stm32g0_pwr.c | 4 +- arch/arm/src/stm32f0l0g0/stm32g0_rcc.c | 80 +- arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c | 68 +- arch/arm/src/stm32f0l0g0/stm32l0_rcc.c | 80 +- .../b-l072z-lrwan1/configs/adc/defconfig | 10 +- .../b-l072z-lrwan1/configs/nsh/defconfig | 4 +- .../configs/nxlines_oled/defconfig | 6 +- .../b-l072z-lrwan1/configs/sx127x/defconfig | 6 +- .../b-l072z-lrwan1/include/board.h | 2 +- .../b-l072z-lrwan1/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/b-l072z-lrwan1/src/Make.defs | 2 +- .../b-l072z-lrwan1/src/b-l072z-lrwan1.h | 2 +- .../b-l072z-lrwan1/src/stm32_adc.c | 4 +- .../b-l072z-lrwan1/src/stm32_boot.c | 2 +- .../b-l072z-lrwan1/src/stm32_bringup.c | 6 +- .../b-l072z-lrwan1/src/stm32_spi.c | 14 +- .../nucleo-c071rb/configs/adcscope/defconfig | 20 +- .../nucleo-c071rb/configs/jumbo/defconfig | 28 +- .../nucleo-c071rb/configs/nsh/defconfig | 2 +- .../nucleo-c071rb/src/stm32_boot.c | 2 +- .../nucleo-c071rb/src/stm32_bringup.c | 4 +- .../nucleo-c092rc/configs/can/defconfig | 10 +- .../nucleo-c092rc/configs/cansock/defconfig | 12 +- .../nucleo-c092rc/configs/jumbo/defconfig | 30 +- .../nucleo-c092rc/configs/nsh/defconfig | 2 +- .../nucleo-c092rc/src/CMakeLists.txt | 6 +- .../stm32f0l0g0/nucleo-c092rc/src/Make.defs | 6 +- .../nucleo-c092rc/src/nucleo-c092rc.h | 4 +- .../nucleo-c092rc/src/stm32_boot.c | 2 +- .../nucleo-c092rc/src/stm32_bringup.c | 8 +- .../nucleo-f072rb/configs/nsh/defconfig | 4 +- .../stm32f0l0g0/nucleo-f072rb/include/board.h | 4 +- .../nucleo-f072rb/src/nucleo-f072rb.h | 12 +- .../nucleo-f072rb/src/stm32_bringup.c | 2 +- .../nucleo-f091rc/configs/nsh/defconfig | 4 +- .../nucleo-f091rc/configs/sx127x/defconfig | 6 +- .../stm32f0l0g0/nucleo-f091rc/include/board.h | 4 +- .../nucleo-f091rc/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/nucleo-f091rc/src/Make.defs | 2 +- .../nucleo-f091rc/src/nucleo-f091rc.h | 14 +- .../nucleo-f091rc/src/stm32_boot.c | 2 +- .../stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c | 14 +- .../nucleo-g070rb/configs/nsh/defconfig | 82 +- .../nucleo-g070rb/src/stm32_boot.c | 2 +- .../nucleo-g070rb/src/stm32_bringup.c | 8 +- .../stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c | 14 +- .../nucleo-g071rb/configs/nsh/defconfig | 4 +- .../nucleo-g071rb/src/stm32_boot.c | 2 +- .../nucleo-g0b1re/configs/adc/defconfig | 6 +- .../nucleo-g0b1re/configs/adc_dma/defconfig | 24 +- .../nucleo-g0b1re/configs/nsh/defconfig | 4 +- .../nucleo-g0b1re/src/CMakeLists.txt | 4 + .../stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c | 2 +- .../nucleo-g0b1re/src/stm32_boot.c | 2 +- .../nucleo-l073rz/configs/nsh/defconfig | 4 +- .../nucleo-l073rz/configs/sx127x/defconfig | 6 +- .../stm32f0l0g0/nucleo-l073rz/include/board.h | 2 +- .../nucleo-l073rz/src/CMakeLists.txt | 2 +- .../stm32f0l0g0/nucleo-l073rz/src/Make.defs | 2 +- .../nucleo-l073rz/src/nucleo-l073rz.h | 2 +- .../nucleo-l073rz/src/stm32_boot.c | 2 +- .../nucleo-l073rz/src/stm32_mfrc522.c | 2 +- .../stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c | 18 +- .../stm32f051-discovery/configs/nsh/defconfig | 4 +- .../stm32f051-discovery/include/board.h | 4 +- .../stm32f051-discovery/src/CMakeLists.txt | 2 +- .../stm32f051-discovery/src/Make.defs | 2 +- .../src/stm32f051-discovery.h | 12 +- .../stm32f072-discovery/configs/nsh/defconfig | 4 +- .../stm32f072-discovery/include/board.h | 4 +- .../stm32f072-discovery/src/CMakeLists.txt | 2 +- .../stm32f072-discovery/src/Make.defs | 2 +- .../src/stm32f072-discovery.h | 12 +- .../stm32g071b-disco/configs/nsh/defconfig | 4 +- .../stm32g071b-disco/configs/oled/defconfig | 8 +- .../stm32g071b-disco/src/stm32_boot.c | 2 +- .../stm32g071b-disco/src/stm32_ina226.c | 2 +- .../stm32g071b-disco/src/stm32_spi.c | 18 +- .../stm32l0538-disco/configs/nsh/defconfig | 4 +- .../stm32l0538-disco/include/board.h | 2 +- 136 files changed, 2775 insertions(+), 3084 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5d75cd9c05..d6d54a5fd26 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -593,18 +593,21 @@ config ARCH_CHIP_STM32L1 config ARCH_CHIP_STM32F0 bool "STMicro STM32 F0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32F0 architectures (ARM Cortex-M0). config ARCH_CHIP_STM32L0 bool "STMicro STM32 L0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32L0 architectures (ARM Cortex-M0+). config ARCH_CHIP_STM32G0 bool "STMicro STM32 G0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 select ARCH_HAVE_PROGMEM ---help--- @@ -612,6 +615,7 @@ config ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32C0 bool "STMicro STM32 C0" + select ARCH_CHIP_STM32 select ARCH_CORTEXM0 ---help--- STMicro STM32C0 architectures (ARM Cortex-M0+). diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h index ef718cff085..ae5e5a29194 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32f0l0g0/stm32g0_irq.h @@ -80,8 +80,8 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */ #define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */ -#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +#if defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */ # define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */ # define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */ diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt index a60ec1966a7..44b85031e93 100644 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ b/arch/arm/src/stm32f0l0g0/CMakeLists.txt @@ -35,15 +35,15 @@ list( stm32_rcc.c stm32_uid.c) -if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F0L0G0_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32F0L0G0_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() @@ -59,11 +59,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c) endif() -if(CONFIG_STM32F0L0G0_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() -if(CONFIG_STM32F0L0G0_GPIOIRQ) +if(CONFIG_STM32_GPIOIRQ) list(APPEND SRCS stm32_gpioint.c) endif() @@ -71,59 +71,59 @@ if(CONFIG_ARCH_IRQPRIO) list(APPEND SRCS stm32_irqprio.c) endif() -if(CONFIG_STM32F0L0G0_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() -if(CONFIG_STM32F0L0G0_USB) +if(CONFIG_STM32_USB) list(APPEND SRCS stm32_usbdev.c) endif() -if(CONFIG_STM32F0L0G0_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F0L0G0_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() -if(CONFIG_PULSECOUNT AND CONFIG_STM32F0L0G0_TIM1_PULSECOUNT) +if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F0L0G0_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F0L0G0_AES) +if(CONFIG_STM32_AES) list(APPEND SRCS stm32_aes.c) endif() -if(CONFIG_STM32F0L0G0_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F0L0G0_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F0L0G0_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32F0L0G0_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_fdcan.c) endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) + if(CONFIG_STM32_FDCAN_SOCKET) list(APPEND SRCS stm32_fdcan_sock.c) endif() endif() diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 31cddad994e..1ae81719d04 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -15,712 +15,712 @@ choice config ARCH_CHIP_STM32F030C6 bool "STM32F030C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030C8 bool "STM32F030C8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030CC bool "STM32F030CC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030F4 bool "STM32F030F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030K6 bool "STM32F030K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030R8 bool "STM32F030R8" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F030RC bool "STM32F030RC" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_VALUELINE + select STM32_STM32F03X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C4 bool "STM32F031C4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031C6 bool "STM32F031C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031E6 bool "STM32F031E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F4 bool "STM32F031F4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031F6 bool "STM32F031F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G4 bool "STM32F031G4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031G6 bool "STM32F031G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K4 bool "STM32F031K4" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F031K6 bool "STM32F031K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F03X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038C6 bool "STM32F038C6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038E6 bool "STM32F038E6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038F6 bool "STM32F038F6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038G6 bool "STM32F038G6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F038K6 bool "STM32F038K6" - select STM32F0L0G0_STM32F03X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F03X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C4 bool "STM32F042C4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042C6 bool "STM32F042C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F4 bool "STM32F042F4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042F6 bool "STM32F042F6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G4 bool "STM32F042G4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042G6 bool "STM32F042G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K4 bool "STM32F042K4" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042K6 bool "STM32F042K6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F042T6 bool "STM32F042T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_USBLINE + select STM32_STM32F04X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048C6 bool "STM32F048C6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048G6 bool "STM32F048G6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F048T6 bool "STM32F048T6" - select STM32F0L0G0_STM32F04X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F04X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C4 bool "STM32F051C4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C6 bool "STM32F051C6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051C8 bool "STM32F051C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K4 bool "STM32F051K4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K6 bool "STM32F051K6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051K8 bool "STM32F051K8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R4 bool "STM32F051R4" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R6 bool "STM32F051R6" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051R8 bool "STM32F051R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F051T8 bool "STM32F051T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F05X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058C8 bool "STM32F058C8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058R8 bool "STM32F058R8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F058T8 bool "STM32F058T8" - select STM32F0L0G0_STM32F05X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F05X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070C6 bool "STM32F070C6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070CB bool "STM32F070CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070F6 bool "STM32F070F6" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F070RB bool "STM32F070RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_VALUELINE + select STM32_STM32F07X + select STM32_VALUELINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071C8 bool "STM32F071C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071CB bool "STM32F071CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071RB bool "STM32F071RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071V8 bool "STM32F071V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F071VB bool "STM32F071VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F07X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072C8 bool "STM32F072C8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072CB bool "STM32F072CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072R8 bool "STM32F072R8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072RB bool "STM32F072RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072V8 bool "STM32F072V8" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F072VB bool "STM32F072VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_USBLINE + select STM32_STM32F07X + select STM32_USBLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078CB bool "STM32F078CB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078RB bool "STM32F078RB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F078VB bool "STM32F078VB" - select STM32F0L0G0_STM32F07X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F07X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CB bool "STM32F091CB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091CC bool "STM32F091CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RB bool "STM32F091RB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091RC bool "STM32F091RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VB bool "STM32F091VB" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F091VC bool "STM32F091VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_ACCESSLINE + select STM32_STM32F09X + select STM32_ACCESSLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098CC bool "STM32F098CC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098RC bool "STM32F098RC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32F098VC bool "STM32F098VC" - select STM32F0L0G0_STM32F09X - select STM32F0L0G0_LOWVOLTLINE + select STM32_STM32F09X + select STM32_LOWVOLTLINE depends on ARCH_CHIP_STM32F0 config ARCH_CHIP_STM32G070CB bool "STM32G070CB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G070KB bool "STM32G070KB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G070RB bool "STM32G070RB" - select STM32F0L0G0_STM32G070 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071EB bool "STM32G071EB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8 bool "STM32G071G8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GB bool "STM32G071GB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071G8XN bool "STM32G071G8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071GBXN bool "STM32G071GBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8 bool "STM32G071K8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KB bool "STM32G071KB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071K8XN bool "STM32G071K8XN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071KBXN bool "STM32G071KBXN" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071C8 bool "STM32G071C8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071CB bool "STM32G071CB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071R8 bool "STM32G071R8" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G071RB bool "STM32G071RB" - select STM32F0L0G0_STM32G071 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KB bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CB bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RB bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MB bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VB bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KC bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CC bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RC bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MC bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VC bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KE bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CE bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RE bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1NE bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1ME bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VE bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 - select STM32F0L0G0_FLASH_CONFIG_E + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KB bool "STM32G0B1KB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CB bool "STM32G0B1CB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RB bool "STM32G0B1RB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MB bool "STM32G0B1MB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VB bool "STM32G0B1VB" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KC bool "STM32G0B1KC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CC bool "STM32G0B1CC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RC bool "STM32G0B1RC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1MC bool "STM32G0B1MC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VC bool "STM32G0B1VC" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1KE bool "STM32G0B1KE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1CE bool "STM32G0B1CE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1RE bool "STM32G0B1RE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1NE bool "STM32G0B1NE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1ME bool "STM32G0B1ME" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32G0B1VE bool "STM32G0B1VE" - select STM32F0L0G0_STM32G0B1 + select STM32_STM32G0B1 depends on ARCH_CHIP_STM32G0 config ARCH_CHIP_STM32L053C8 @@ -751,86 +751,86 @@ config ARCH_CHIP_STM32L071KZ config ARCH_CHIP_STM32L071C8 bool "STM32L071C8" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CB bool "STM32L071CB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071CZ bool "STM32L071CZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071V8 bool "STM32L071V8" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VB bool "STM32L071VB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071VZ bool "STM32L071VZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RB bool "STM32L071RB" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L071RZ bool "STM32L071RZ" select ARCH_CHIP_STM32L071XX - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072V8 bool "STM32L072V8" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VB bool "STM32L072VB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072VZ bool "STM32L072VZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072KB @@ -846,29 +846,29 @@ config ARCH_CHIP_STM32L072KZ config ARCH_CHIP_STM32L072CB bool "STM32L072CB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072CZ bool "STM32L072CZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RB bool "STM32L072RB" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L072RZ bool "STM32L072RZ" select ARCH_CHIP_STM32L072XX - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 depends on ARCH_CHIP_STM32L0 config ARCH_CHIP_STM32L073V8 @@ -909,683 +909,622 @@ config ARCH_CHIP_STM32L073RZ config ARCH_CHIP_STM32C051D8 bool "STM32C051D8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051F6 bool "STM32C051F6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051F8 bool "STM32C051F8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051G6 bool "STM32C051G6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051G8 bool "STM32C051G8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051K6 bool "STM32C051K6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051K8 bool "STM32C051K8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C051C6 bool "STM32C051C6" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_6 + select STM32_FLASH_CONFIG_6 config ARCH_CHIP_STM32C051C8 bool "STM32C051C8" select ARCH_CHIP_STM32C051XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071F8 bool "STM32C071F8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071FB bool "STM32C071FB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071G8 bool "STM32C071G8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071GB bool "STM32C071GB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071K8 bool "STM32C071K8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071KB bool "STM32C071KB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071C8 bool "STM32C071C8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071CB bool "STM32C071CB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C071R8 bool "STM32C071R8" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_8 + select STM32_FLASH_CONFIG_8 config ARCH_CHIP_STM32C071RB bool "STM32C071RB" select ARCH_CHIP_STM32C071XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091FB bool "STM32C091FB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091FC bool "STM32C091FC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091EC bool "STM32C091EC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091GB bool "STM32C091GB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091GC bool "STM32C091GC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091KB bool "STM32C091KB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091KC bool "STM32C091KC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091CB bool "STM32C091CB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091CC bool "STM32C091CC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C091RB bool "STM32C091RB" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C091RC bool "STM32C091RC" select ARCH_CHIP_STM32C091XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092FB bool "STM32C092FB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092FC bool "STM32C092FC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092EC bool "STM32C092EC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092GB bool "STM32C092GB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092GC bool "STM32C092GC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092KB bool "STM32C092KB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092KC bool "STM32C092KC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092CB bool "STM32C092CB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092CC bool "STM32C092CC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C config ARCH_CHIP_STM32C092RB bool "STM32C092RB" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_B + select STM32_FLASH_CONFIG_B config ARCH_CHIP_STM32C092RC bool "STM32C092RC" select ARCH_CHIP_STM32C092XX - select STM32F0L0G0_FLASH_CONFIG_C + select STM32_FLASH_CONFIG_C endchoice # ST STM32F0/L0/G0/C0 Chip Selection # Flash configurations -config STM32F0L0G0_FLASH_CONFIG_4 +config STM32_FLASH_CONFIG_4 bool default n -config STM32F0L0G0_FLASH_CONFIG_6 +config STM32_FLASH_CONFIG_6 bool default n -config STM32F0L0G0_FLASH_CONFIG_8 +config STM32_FLASH_CONFIG_8 bool default n -config STM32F0L0G0_FLASH_CONFIG_B +config STM32_FLASH_CONFIG_B bool default n -config STM32F0L0G0_FLASH_CONFIG_C +config STM32_FLASH_CONFIG_C bool default n -config STM32F0L0G0_FLASH_CONFIG_D +config STM32_FLASH_CONFIG_D bool default n -config STM32F0L0G0_FLASH_CONFIG_E +config STM32_FLASH_CONFIG_E bool default n -config STM32F0L0G0_FLASH_CONFIG_F +config STM32_FLASH_CONFIG_F bool default n -config STM32F0L0G0_FLASH_CONFIG_G +config STM32_FLASH_CONFIG_G bool default n -config STM32F0L0G0_FLASH_CONFIG_I +config STM32_FLASH_CONFIG_I bool default n -config STM32F0L0G0_FLASH_OVERRIDE +config STM32_FLASH_OVERRIDE bool "Override Flash Designator" default n -choice - prompt "Override Flash Size Designator" - depends on STM32F0L0G0_FLASH_OVERRIDE - default STM32F0L0G0_FLASH_OVERRIDE_B - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - -config STM32F0L0G0_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F0L0G0_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # Override Flash Size Designator - -config STM32F0L0G0_STM32F0 +config STM32_STM32F0 bool default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_EXTI_V1 -config STM32F0L0G0_STM32G0 +config STM32_STM32G0 bool default n - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_HAVE_I2C2 + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C2 select ARCH_HAVE_PROGMEM -config STM32F0L0G0_STM32L0 +config STM32_STM32L0 bool default n - select STM32F0L0G0_ENERGYLITE - select STM32F0L0G0_HAVE_VREFINT - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V1 - select STM32F0L0G0_HAVE_IP_EXTI_V1 + select STM32_ENERGYLITE + select STM32_HAVE_VREFINT + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_EXTI_V1 -config STM32F0L0G0_STM32C0 +config STM32_STM32C0 bool default n - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_DMAMUX - select STM32F0L0G0_HAVE_ADC1_DMA - select STM32F0L0G0_HAVE_IP_USART_V2 - select STM32F0L0G0_HAVE_IP_EXTI_V2 - select STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_HAVE_TIM17 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_ADC1_DMA + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 select ARCH_HAVE_PROGMEM -config STM32F0L0G0_STM32F03X +config STM32_STM32F03X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F04X +config STM32_STM32F04X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F05X +config STM32_STM32F05X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F07X +config STM32_STM32F07X bool default n - select STM32F0L0G0_STM32F0 + select STM32_STM32F0 -config STM32F0L0G0_STM32F09X +config STM32_STM32F09X bool default n - select STM32F0L0G0_STM32F0 - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_DMA2 + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 -config STM32F0L0G0_STM32G030 +config STM32_STM32G030 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X + select STM32_STM32G0 + select STM32_STM32G03X -config STM32F0L0G0_STM32G031 +config STM32_STM32G031 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G03X - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G03X + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G03X +config STM32_STM32G03X bool default n -config STM32F0L0G0_STM32G041 +config STM32_STM32G041 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G050 +config STM32_STM32G050 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X + select STM32_STM32G0 + select STM32_STM32G05X -config STM32F0L0G0_STM32G051 +config STM32_STM32G051 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G05X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G05X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G05X +config STM32_STM32G05X bool default n - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 -config STM32F0L0G0_STM32G061 +config STM32_STM32G061 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G070 +config STM32_STM32G070 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X + select STM32_STM32G0 + select STM32_STM32G07X -config STM32F0L0G0_STM32G071 +config STM32_STM32G071 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G07X - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_STM32G07X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G07X +config STM32_STM32G07X bool default n - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 -config STM32F0L0G0_STM32G081 +config STM32_STM32G081 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_LPUART1 + select STM32_STM32G0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 -config STM32F0L0G0_STM32G0B0 +config STM32_STM32G0B0 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX + select STM32_STM32G0 + select STM32_STM32G0BX -config STM32F0L0G0_STM32G0B1 +config STM32_STM32G0B1 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_STM32G0BX - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC + select STM32_STM32G0 + select STM32_STM32G0BX + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC -config STM32F0L0G0_STM32G0BX +config STM32_STM32G0BX bool default n - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_LPUART1 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_CRS + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_HSI48 -config STM32F0L0G0_STM32G0C1 +config STM32_STM32G0C1 bool default n - select STM32F0L0G0_STM32G0 - select STM32F0L0G0_HAVE_DMA2 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_HAVE_CRS - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_AES - select STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_HAVE_COMP1 - select STM32F0L0G0_HAVE_COMP2 - select STM32F0L0G0_HAVE_COMP3 - select STM32F0L0G0_HAVE_TIM4 - select STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_SPI3 - select STM32F0L0G0_HAVE_I2S2 - select STM32F0L0G0_HAVE_LPUART2 - select STM32F0L0G0_HAVE_USBDEV - select STM32F0L0G0_HAVE_UCPD1 - select STM32F0L0G0_HAVE_UCPD2 - select STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_HAVE_FDCAN2 - select STM32F0L0G0_HAVE_CEC - select STM32F0L0G0_HAVE_HSI48 + select STM32_STM32G0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_CRS + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_LPUART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + select STM32_HAVE_HSI48 -config STM32F0L0G0_VALUELINE +config STM32_VALUELINE bool default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 -config STM32F0L0G0_ACCESSLINE +config STM32_ACCESSLINE bool default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 -config STM32F0L0G0_LOWVOLTLINE +config STM32_LOWVOLTLINE bool default n - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 -config STM32F0L0G0_USBLINE +config STM32_USBLINE bool default n - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_CAN1 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_USBDEV + select STM32_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + select STM32_HAVE_USBDEV -config STM32F0L0G0_ENERGYLITE +config STM32_ENERGYLITE bool default n config ARCH_CHIP_STM32L053XX bool - select STM32F0L0G0_STM32L0 + select STM32_STM32L0 config ARCH_CHIP_STM32L071XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 config ARCH_CHIP_STM32L072XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_I2C2 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32L073XX bool - select STM32F0L0G0_STM32L0 - select STM32F0L0G0_HAVE_RNG - select STM32F0L0G0_HAVE_HSI48 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_HAVE_SPI2 - select STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32C051XX bool - select STM32F0L0G0_STM32C0 + select STM32_STM32C0 config ARCH_CHIP_STM32C071XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USBDEV + select STM32_STM32C0 + select STM32_HAVE_USBDEV config ARCH_CHIP_STM32C091XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_TIM15 + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM15 config ARCH_CHIP_STM32C092XX bool - select STM32F0L0G0_STM32C0 - select STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_HAVE_FDCAN1 + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_FDCAN1 -config STM32F0L0G0_DFU +config STM32_DFU bool "DFU bootloader" default n - depends on !STM32F0L0G0_VALUELINE + depends on !STM32_VALUELINE ---help--- Configure and position code for use with the STMicro DFU bootloader. Do not select this option if you will load code using JTAG/SWM. -config STM32F0L0G0_PROGMEM +config STM32_PROGMEM bool "Flash PROGMEM support" default n depends on ARCH_HAVE_PROGMEM @@ -1597,623 +1536,617 @@ config STM32F0L0G0_PROGMEM choice prompt "SysTick clock source" - default STM32F0L0G0_SYSTICK_CORECLK + default STM32_SYSTICK_CORECLK -config STM32F0L0G0_SYSTICK_CORECLK +config STM32_SYSTICK_CORECLK bool "Cortex-M0 core clock" -config STM32F0L0G0_SYSTICK_CORECLK_DIV16 +config STM32_SYSTICK_CORECLK_DIV16 bool "Cortex-M0 core clock divided by 16" endchoice # SysTick clock source -config ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available # for the selected MCU -config STM32F0L0G0_HAVE_AES +config STM32_HAVE_AES bool default n -config STM32F0L0G0_HAVE_VREFINT +config STM32_HAVE_VREFINT bool default n -config STM32F0L0G0_HAVE_CCM +config STM32_HAVE_CCM bool default n -config STM32F0L0G0_HAVE_HSI48 +config STM32_HAVE_HSI48 bool default n -config STM32F0L0G0_HAVE_LCD +config STM32_HAVE_LCD bool default n -config STM32F0L0G0_HAVE_USBDEV +config STM32_HAVE_USBDEV bool default n -config STM32F0L0G0_HAVE_FSMC +config STM32_HAVE_FSMC bool default n -config STM32F0L0G0_HAVE_USART3 +config STM32_HAVE_USART3 bool default n -config STM32F0L0G0_HAVE_USART4 +config STM32_HAVE_USART4 bool default n -config STM32F0L0G0_HAVE_USART5 +config STM32_HAVE_USART5 bool default n -config STM32F0L0G0_HAVE_USART6 +config STM32_HAVE_USART6 bool default n -config STM32F0L0G0_HAVE_USART7 +config STM32_HAVE_USART7 bool default n -config STM32F0L0G0_HAVE_USART8 +config STM32_HAVE_USART8 bool default n -config STM32F0L0G0_HAVE_LPUART1 +config STM32_HAVE_LPUART1 bool default n -config STM32F0L0G0_HAVE_LPUART2 +config STM32_HAVE_LPUART2 bool default n -config STM32F0L0G0_HAVE_TIM1 +config STM32_HAVE_TIM1 bool default n -config STM32F0L0G0_HAVE_TIM2 +config STM32_HAVE_TIM2 bool default n -config STM32F0L0G0_HAVE_TIM3 +config STM32_HAVE_TIM3 bool default n -config STM32F0L0G0_HAVE_TIM4 +config STM32_HAVE_TIM4 bool default n -config STM32F0L0G0_HAVE_TIM6 +config STM32_HAVE_TIM6 bool default n -config STM32F0L0G0_HAVE_TIM7 +config STM32_HAVE_TIM7 bool default n -config STM32F0L0G0_HAVE_TIM14 +config STM32_HAVE_TIM14 bool default n -config STM32F0L0G0_HAVE_TIM15 +config STM32_HAVE_TIM15 bool default n -config STM32F0L0G0_HAVE_TIM16 +config STM32_HAVE_TIM16 bool default n -config STM32F0L0G0_HAVE_TIM17 +config STM32_HAVE_TIM17 bool default n -config STM32F0L0G0_HAVE_TSC +config STM32_HAVE_TSC bool default n -config STM32F0L0G0_HAVE_ADC1_DMA +config STM32_HAVE_ADC1_DMA bool default n -config STM32F0L0G0_HAVE_ADC_OVERSAMPLE +config STM32_HAVE_ADC_OVERSAMPLE bool - default STM32F0L0G0_STM32L0 || STM32F0L0G0_STM32G0 || STM32F0L0G0_STM32C0 + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 -config STM32F0L0G0_HAVE_CEC +config STM32_HAVE_CEC bool default n -config STM32F0L0G0_HAVE_CAN1 +config STM32_HAVE_CAN1 bool default n -config STM32F0L0G0_HAVE_COMP1 +config STM32_HAVE_COMP1 bool default n -config STM32F0L0G0_HAVE_COMP2 +config STM32_HAVE_COMP2 bool default n -config STM32F0L0G0_HAVE_COMP3 +config STM32_HAVE_COMP3 bool default n -config STM32F0L0G0_HAVE_DAC1 +config STM32_HAVE_DAC1 bool default n -config STM32F0L0G0_HAVE_DMAMUX +config STM32_HAVE_DMAMUX bool default n -config STM32F0L0G0_HAVE_DMA2 +config STM32_HAVE_DMA2 bool default n -config STM32F0L0G0_HAVE_RNG +config STM32_HAVE_RNG bool default n -config STM32F0L0G0_HAVE_CRS +config STM32_HAVE_CRS bool default n -config STM32F0L0G0_HAVE_I2C2 +config STM32_HAVE_I2C2 bool default n -config STM32F0L0G0_HAVE_I2C3 +config STM32_HAVE_I2C3 bool default n -config STM32F0L0G0_HAVE_SPI2 +config STM32_HAVE_SPI2 bool default n -config STM32F0L0G0_HAVE_SPI3 +config STM32_HAVE_SPI3 bool default n -config STM32F0L0G0_HAVE_SAIPLL +config STM32_HAVE_SAIPLL bool default n -config STM32F0L0G0_HAVE_SDIO +config STM32_HAVE_SDIO bool default n -config STM32F0L0G0_HAVE_I2SPLL +config STM32_HAVE_I2SPLL bool default n -config STM32F0L0G0_HAVE_OPAMP1 +config STM32_HAVE_OPAMP1 bool default n -config STM32F0L0G0_HAVE_OPAMP2 +config STM32_HAVE_OPAMP2 bool default n -config STM32F0L0G0_HAVE_OPAMP3 +config STM32_HAVE_OPAMP3 bool default n -config STM32F0L0G0_HAVE_OPAMP4 +config STM32_HAVE_OPAMP4 bool default n -config STM32F0L0G0_HAVE_FDCAN1 +config STM32_HAVE_FDCAN1 bool default n -config STM32F0L0G0_HAVE_FDCAN2 +config STM32_HAVE_FDCAN2 bool default n -config STM32F0L0G0_HAVE_I2S2 +config STM32_HAVE_I2S2 bool default n -config STM32F0L0G0_HAVE_UCPD1 +config STM32_HAVE_UCPD1 bool default n -config STM32F0L0G0_HAVE_UCPD2 +config STM32_HAVE_UCPD2 bool default n # These are STM32 peripherals IP blocks -config STM32F0L0G0_HAVE_IP_USART_V1 +config STM32_HAVE_IP_USART_V1 bool default n -config STM32F0L0G0_HAVE_IP_USART_V2 +config STM32_HAVE_IP_USART_V2 bool default n -config STM32F0L0G0_HAVE_IP_EXTI_V1 +config STM32_HAVE_IP_EXTI_V1 bool default n -config STM32F0L0G0_HAVE_IP_EXTI_V2 +config STM32_HAVE_IP_EXTI_V2 bool default n # These are the peripheral selections proper -config STM32F0L0G0_ADC1 +config STM32_ADC1 bool "ADC1" default n - select STM32F0L0G0_ADC + select STM32_ADC -config STM32F0L0G0_COMP1 +config STM32_COMP1 bool "COMP1" default n - depends on STM32F0L0G0_HAVE_COMP1 + depends on STM32_HAVE_COMP1 -config STM32F0L0G0_COMP2 +config STM32_COMP2 bool "COMP2" default n - depends on STM32F0L0G0_HAVE_COMP2 + depends on STM32_HAVE_COMP2 -config STM32F0L0G0_BKP +config STM32_BKP bool "BKP" default n -config STM32F0L0G0_BKPSRAM +config STM32_BKPSRAM bool "Enable BKP RAM Domain" default n -config STM32F0L0G0_CAN1 +config STM32_CAN1 bool "CAN1" default n select CAN - select STM32F0L0G0_CAN - depends on STM32F0L0G0_HAVE_CAN1 + select STM32_CAN + depends on STM32_HAVE_CAN1 -config STM32F0L0G0_AES +config STM32_AES bool "128-bit AES" default n - depends on STM32F0L0G0_HAVE_AES + depends on STM32_HAVE_AES select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST -config STM32F0L0G0_VREFINT +config STM32_VREFINT bool "Enable VREFINT" default n - depends on STM32F0L0G0_HAVE_VREFINT + depends on STM32_HAVE_VREFINT -config STM32F0L0G0_CEC +config STM32_CEC bool "CEC" default n - depends on STM32F0L0G0_HAVE_CEC + depends on STM32_HAVE_CEC -config STM32F0L0G0_CRC +config STM32_CRC bool "CRC" default n -config STM32F0L0G0_CRYP +config STM32_CRYP bool "CRYP" default n - depends on STM32F0L0G0_HAVE_HASH + depends on STM32_HAVE_HASH -config STM32F0L0G0_DMA1 +config STM32_DMA1 bool "DMA1" default n select ARCH_DMA - select STM32F0L0G0_DMA + select STM32_DMA -config STM32F0L0G0_DMA2 +config STM32_DMA2 bool "DMA2" default n - depends on STM32F0L0G0_HAVE_DMA2 + depends on STM32_HAVE_DMA2 select ARCH_DMA - select STM32F0L0G0_DMA + select STM32_DMA -config STM32F0L0G0_DAC1 +config STM32_DAC1 bool "DAC1" default n - depends on STM32F0L0G0_HAVE_DAC1 - select STM32F0L0G0_DAC + depends on STM32_HAVE_DAC1 + select STM32_DAC -config STM32F0L0G0_FDCAN1 +config STM32_FDCAN1 bool "FDCAN1" default n - depends on STM32F0L0G0_HAVE_FDCAN1 - select STM32F0L0G0_FDCAN + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN -config STM32F0L0G0_FSMC +config STM32_FSMC bool "FSMC" default n - depends on STM32F0L0G0_HAVE_FSMC + depends on STM32_HAVE_FSMC -config STM32F0L0G0_HASH +config STM32_HASH bool "HASH" default n - depends on STM32F0L0G0_HAVE_HASH + depends on STM32_HAVE_HASH -config STM32F0L0G0_I2C1 +config STM32_I2C1 bool "I2C1" default n - select STM32F0L0G0_I2C + select STM32_I2C -config STM32F0L0G0_I2C2 +config STM32_I2C2 bool "I2C2" default n - depends on STM32F0L0G0_HAVE_I2C2 - select STM32F0L0G0_I2C + depends on STM32_HAVE_I2C2 + select STM32_I2C -config STM32F0L0G0_I2C3 +config STM32_I2C3 bool "I2C3" default n - depends on STM32F0L0G0_HAVE_I2C3 - select STM32F0L0G0_I2C + depends on STM32_HAVE_I2C3 + select STM32_I2C -config STM32F0L0G0_PWR +config STM32_PWR bool "PWR" default n -config STM32F0L0G0_RNG +config STM32_RNG bool "RNG" default n - depends on STM32F0L0G0_HAVE_RNG + depends on STM32_HAVE_RNG select ARCH_HAVE_RNG -config STM32F0L0G0_SDIO +config STM32_SDIO bool "SDIO" default n - depends on STM32F0L0G0_HAVE_SDIO + depends on STM32_HAVE_SDIO select ARCH_HAVE_SDIO select ARCH_HAVE_SDIOWAIT_WRCOMPLETE select ARCH_HAVE_SDIO_PREFLIGHT -config STM32F0L0G0_SPI1 +config STM32_SPI1 bool "SPI1" default n select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SPI2 +config STM32_SPI2 bool "SPI2" default n - depends on STM32F0L0G0_HAVE_SPI2 + depends on STM32_HAVE_SPI2 select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SPI3 +config STM32_SPI3 bool "SPI3" default n - depends on STM32F0L0G0_HAVE_SPI3 + depends on STM32_HAVE_SPI3 select SPI - select STM32F0L0G0_SPI + select STM32_SPI -config STM32F0L0G0_SYSCFG +config STM32_SYSCFG bool "SYSCFG" default y -config STM32F0L0G0_TIM1 +config STM32_TIM1 bool "TIM1" default n - depends on STM32F0L0G0_HAVE_TIM1 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM1 + select STM32_TIM -config STM32F0L0G0_TIM2 +config STM32_TIM2 bool "TIM2" default n - depends on STM32F0L0G0_HAVE_TIM2 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM2 + select STM32_TIM -config STM32F0L0G0_TIM3 +config STM32_TIM3 bool "TIM3" default n - depends on STM32F0L0G0_HAVE_TIM3 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM3 + select STM32_TIM -config STM32F0L0G0_TIM6 +config STM32_TIM6 bool "TIM6" default n - depends on STM32F0L0G0_HAVE_TIM6 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM6 + select STM32_TIM -config STM32F0L0G0_TIM7 +config STM32_TIM7 bool "TIM7" default n - depends on STM32F0L0G0_HAVE_TIM7 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM7 + select STM32_TIM -config STM32F0L0G0_TIM14 +config STM32_TIM14 bool "TIM14" default n - depends on STM32F0L0G0_HAVE_TIM14 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM14 + select STM32_TIM -config STM32F0L0G0_TIM15 +config STM32_TIM15 bool "TIM15" default n - depends on STM32F0L0G0_HAVE_TIM15 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM15 + select STM32_TIM -config STM32F0L0G0_TIM16 +config STM32_TIM16 bool "TIM16" default n - depends on STM32F0L0G0_HAVE_TIM16 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM16 + select STM32_TIM -config STM32F0L0G0_TIM17 +config STM32_TIM17 bool "TIM17" default n - depends on STM32F0L0G0_HAVE_TIM17 - select STM32F0L0G0_TIM + depends on STM32_HAVE_TIM17 + select STM32_TIM -config STM32F0L0G0_TSC +config STM32_TSC bool "TSC" default n - depends on STM32F0L0G0_HAVE_TSC + depends on STM32_HAVE_TSC -config STM32F0L0G0_USART1 +config STM32_USART1 bool "USART1" default n - select STM32F0L0G0_USART + select STM32_USART -config STM32F0L0G0_USART2 +config STM32_USART2 bool "USART2" default n - select STM32F0L0G0_USART + select STM32_USART -config STM32F0L0G0_USART3 +config STM32_USART3 bool "USART3" default n - depends on STM32F0L0G0_HAVE_USART3 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART3 + select STM32_USART -config STM32F0L0G0_USART4 +config STM32_USART4 bool "USART4" default n - depends on STM32F0L0G0_HAVE_USART4 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART4 + select STM32_USART -config STM32F0L0G0_USART5 +config STM32_USART5 bool "USART5" default n - depends on STM32F0L0G0_HAVE_USART5 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART5 + select STM32_USART -config STM32F0L0G0_USART6 +config STM32_USART6 bool "USART6" default n - depends on STM32F0L0G0_HAVE_USART6 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART6 + select STM32_USART -config STM32F0L0G0_USART7 +config STM32_USART7 bool "USART7" default n - depends on STM32F0L0G0_HAVE_USART7 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART7 + select STM32_USART -config STM32F0L0G0_USART8 +config STM32_USART8 bool "USART8" default n - depends on STM32F0L0G0_HAVE_USART8 - select STM32F0L0G0_USART + depends on STM32_HAVE_USART8 + select STM32_USART -config STM32F0L0G0_USB +config STM32_USB bool "USB Device" default n - depends on STM32F0L0G0_HAVE_USBDEV + depends on STM32_HAVE_USBDEV select USBDEV -config STM32F0L0G0_LCD +config STM32_LCD bool "Segment LCD" default n - depends on STM32F0L0G0_HAVE_LCD + depends on STM32_HAVE_LCD select USBDEV -config STM32F0L0G0_IWDG +config STM32_IWDG bool "IWDG" default n select WATCHDOG -config STM32F0L0G0_WWDG +config STM32_WWDG bool "WWDG" default n select WATCHDOG endmenu # STM32 Peripheral Support -config STM32F0L0G0_COMP +config STM32_COMP bool default n -config STM32F0L0G0_ADC +config STM32_ADC bool default n -config STM32F0L0G0_DAC +config STM32_DAC bool default n -config STM32F0L0G0_DMA +config STM32_DMA bool default n -config STM32F0L0G0_SPI +config STM32_SPI bool -config STM32F0L0G0_SPI_DMA +config STM32_SPI_DMA bool default n -config STM32F0L0G0_I2C +config STM32_I2C bool default n -config STM32F0L0G0_CAN +config STM32_CAN bool default n -config STM32F0L0G0_PWM +config STM32_PWM bool default n -config STM32F0L0G0_USART +config STM32_USART bool default n -config STM32F0L0G0_TIM +config STM32_TIM bool default n -config STM32F0L0G0_FDCAN +config STM32_FDCAN bool default n -config STM32F0L0G0_SERIALDRIVER +config STM32_SERIALDRIVER bool default n -config STM32F0L0G0_1WIREDRIVER +config STM32_1WIREDRIVER bool default n menu "Timer Configuration" -config STM32F0L0G0_TIM1_PULSECOUNT +config STM32_TIM1_PULSECOUNT bool "TIM1 pulse count" default n - depends on STM32F0L0G0_TIM1 + depends on STM32_TIM1 select ARCH_HAVE_PULSECOUNT select PULSECOUNT ---help--- Reserve timer 1 for use by the pulse count driver. - Timer devices may be used for different purposes. If STM32F0L0G0_TIM1 + Timer devices may be used for different purposes. If STM32_TIM1 is defined then this option may also be defined to indicate that TIM1 is intended to generate a fixed number of output pulses. -config STM32F0L0G0_TIM1_PWM +config STM32_TIM1_PWM bool "TIM1 PWM" default n - depends on STM32F0L0G0_TIM1 && !STM32F0L0G0_TIM1_PULSECOUNT - select STM32F0L0G0_PWM + depends on STM32_TIM1 && !STM32_TIM1_PULSECOUNT + select STM32_PWM ---help--- Reserve timer 1 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM1 is defined then this option may also be defined to + STM32_TIM1 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2225,9 +2158,9 @@ config STM32F0L0G0_TIM1_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM1_PWM +if STM32_TIM1_PWM -config STM32F0L0G0_TIM1_MODE +config STM32_TIM1_MODE int "TIM1 Mode" default 0 range 0 4 @@ -2240,126 +2173,126 @@ config STM32F0L0G0_TIM1_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM1_CHANNEL1 +config STM32_TIM1_CHANNEL1 bool "TIM1 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM1_CHANNEL1 +if STM32_TIM1_CHANNEL1 -config STM32F0L0G0_TIM1_CH1MODE +config STM32_TIM1_CH1MODE int "TIM1 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH1OUT +config STM32_TIM1_CH1OUT bool "TIM1 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM1_CH1NOUT +config STM32_TIM1_CH1NOUT bool "TIM1 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH1OUT + depends on STM32_TIM1_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL1 +endif # STM32_TIM1_CHANNEL1 -config STM32F0L0G0_TIM1_CHANNEL2 +config STM32_TIM1_CHANNEL2 bool "TIM1 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM1_CHANNEL2 +if STM32_TIM1_CHANNEL2 -config STM32F0L0G0_TIM1_CH2MODE +config STM32_TIM1_CH2MODE int "TIM1 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH2OUT +config STM32_TIM1_CH2OUT bool "TIM1 Channel 2 Output" default n ---help--- Enables channel 2 output. -config STM32F0L0G0_TIM1_CH2NOUT +config STM32_TIM1_CH2NOUT bool "TIM1 Channel 2 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH2OUT + depends on STM32_TIM1_CH2OUT ---help--- Enables channel 2 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL2 +endif # STM32_TIM1_CHANNEL2 -config STM32F0L0G0_TIM1_CHANNEL3 +config STM32_TIM1_CHANNEL3 bool "TIM1 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM1_CHANNEL3 +if STM32_TIM1_CHANNEL3 -config STM32F0L0G0_TIM1_CH3MODE +config STM32_TIM1_CH3MODE int "TIM1 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH3OUT +config STM32_TIM1_CH3OUT bool "TIM1 Channel 3 Output" default n ---help--- Enables channel 3 output. -config STM32F0L0G0_TIM1_CH3NOUT +config STM32_TIM1_CH3NOUT bool "TIM1 Channel 3 Complementary Output" default n - depends on STM32F0L0G0_TIM1_CH3OUT + depends on STM32_TIM1_CH3OUT ---help--- Enables channel 3 complementary output. -endif # STM32F0L0G0_TIM1_CHANNEL3 +endif # STM32_TIM1_CHANNEL3 -config STM32F0L0G0_TIM1_CHANNEL4 +config STM32_TIM1_CHANNEL4 bool "TIM1 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM1_CHANNEL4 +if STM32_TIM1_CHANNEL4 -config STM32F0L0G0_TIM1_CH4MODE +config STM32_TIM1_CH4MODE int "TIM1 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -config STM32F0L0G0_TIM1_CH4OUT +config STM32_TIM1_CH4OUT bool "TIM1 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM1_CHANNEL4 +endif # STM32_TIM1_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM1_CHANNEL +config STM32_TIM1_CHANNEL int "TIM1 PWM Output Channel" default 1 range 1 4 @@ -2367,46 +2300,46 @@ config STM32F0L0G0_TIM1_CHANNEL If TIM1 is enabled for output usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM1_CHMODE +config STM32_TIM1_CHMODE int "TIM1 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. + Specifies the channel mode. See STM32_TIM1_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM1_PWM +endif # STM32_TIM1_PWM -if STM32F0L0G0_TIM1_PULSECOUNT +if STM32_TIM1_PULSECOUNT -config STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL +config STM32_TIM1_PULSECOUNT_CHANNEL int "TIM1 pulse count channel" default 1 range 1 4 ---help--- Specifies the timer channel {1,..,4}. -endif # STM32F0L0G0_TIM1_PULSECOUNT +endif # STM32_TIM1_PULSECOUNT -config STM32F0L0G0_TIM1_QE +config STM32_TIM1_QE bool "TIM1 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM1 + depends on STM32_TIM1 ---help--- Reserve TIM1 for use by Quadrature Encoder. -config STM32F0L0G0_TIM2_PWM +config STM32_TIM2_PWM bool "TIM2 PWM" default n - depends on STM32F0L0G0_TIM2 - select STM32F0L0G0_PWM + depends on STM32_TIM2 + select STM32_PWM ---help--- Reserve timer 2 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM2 is defined then THIS option may also be defined to + STM32_TIM2 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2418,9 +2351,9 @@ config STM32F0L0G0_TIM2_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM2_PWM +if STM32_TIM2_PWM -config STM32F0L0G0_TIM2_MODE +config STM32_TIM2_MODE int "TIM2 Mode" default 0 range 0 4 @@ -2433,105 +2366,105 @@ config STM32F0L0G0_TIM2_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM2_CHANNEL1 +config STM32_TIM2_CHANNEL1 bool "TIM2 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM2_CHANNEL1 +if STM32_TIM2_CHANNEL1 -config STM32F0L0G0_TIM2_CH1MODE +config STM32_TIM2_CH1MODE int "TIM2 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH1OUT +config STM32_TIM2_CH1OUT bool "TIM2 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM2_CHANNEL1 +endif # STM32_TIM2_CHANNEL1 -config STM32F0L0G0_TIM2_CHANNEL2 +config STM32_TIM2_CHANNEL2 bool "TIM2 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM2_CHANNEL2 +if STM32_TIM2_CHANNEL2 -config STM32F0L0G0_TIM2_CH2MODE +config STM32_TIM2_CH2MODE int "TIM2 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH2OUT +config STM32_TIM2_CH2OUT bool "TIM2 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM2_CHANNEL2 +endif # STM32_TIM2_CHANNEL2 -config STM32F0L0G0_TIM2_CHANNEL3 +config STM32_TIM2_CHANNEL3 bool "TIM2 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM2_CHANNEL3 +if STM32_TIM2_CHANNEL3 -config STM32F0L0G0_TIM2_CH3MODE +config STM32_TIM2_CH3MODE int "TIM2 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH3OUT +config STM32_TIM2_CH3OUT bool "TIM2 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32F0L0G0_TIM2_CHANNEL3 +endif # STM32_TIM2_CHANNEL3 -config STM32F0L0G0_TIM2_CHANNEL4 +config STM32_TIM2_CHANNEL4 bool "TIM2 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM2_CHANNEL4 +if STM32_TIM2_CHANNEL4 -config STM32F0L0G0_TIM2_CH4MODE +config STM32_TIM2_CH4MODE int "TIM2 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -config STM32F0L0G0_TIM2_CH4OUT +config STM32_TIM2_CH4OUT bool "TIM2 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM2_CHANNEL4 +endif # STM32_TIM2_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM2_CHANNEL +config STM32_TIM2_CHANNEL int "TIM2 PWM Output Channel" default 1 range 1 4 @@ -2539,35 +2472,35 @@ config STM32F0L0G0_TIM2_CHANNEL If TIM2 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM2_CHMODE +config STM32_TIM2_CHMODE int "TIM2 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM2_PWM description for available modes. + Specifies the channel mode. See STM32_TIM2_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM2_PWM +endif # STM32_TIM2_PWM -config STM32F0L0G0_TIM2_QE +config STM32_TIM2_QE bool "TIM2 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM2 + depends on STM32_TIM2 ---help--- Reserve TIM2 for use by Quadrature Encoder. -config STM32F0L0G0_TIM3_PWM +config STM32_TIM3_PWM bool "TIM3 PWM" default n - depends on STM32F0L0G0_TIM3 - select STM32F0L0G0_PWM + depends on STM32_TIM3 + select STM32_PWM ---help--- Reserve timer 3 for use by PWM Timer devices may be used for different purposes. One special purpose is to generate modulated outputs for such things as motor control. If - STM32F0L0G0_TIM3 is defined then THIS option may also be defined to + STM32_TIM3 is defined then THIS option may also be defined to indicate that the timer is intended to be used for pulsed output modulation. Valid channel modes: @@ -2579,9 +2512,9 @@ config STM32F0L0G0_TIM3_PWM 4 -> Asymmetric PWM mode 1 5 -> Asymmetric PWM mode 2 -if STM32F0L0G0_TIM3_PWM +if STM32_TIM3_PWM -config STM32F0L0G0_TIM3_MODE +config STM32_TIM3_MODE int "TIM3 Mode" default 0 range 0 4 @@ -2594,105 +2527,105 @@ config STM32F0L0G0_TIM3_MODE 3 -> Center-aligned mode 2 4 -> Center-aligned mode 3 -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM3_CHANNEL1 +config STM32_TIM3_CHANNEL1 bool "TIM3 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM3_CHANNEL1 +if STM32_TIM3_CHANNEL1 -config STM32F0L0G0_TIM3_CH1MODE +config STM32_TIM3_CH1MODE int "TIM3 Channel 1 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH1OUT +config STM32_TIM3_CH1OUT bool "TIM3 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM3_CHANNEL1 +endif # STM32_TIM3_CHANNEL1 -config STM32F0L0G0_TIM3_CHANNEL2 +config STM32_TIM3_CHANNEL2 bool "TIM3 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM3_CHANNEL2 +if STM32_TIM3_CHANNEL2 -config STM32F0L0G0_TIM3_CH2MODE +config STM32_TIM3_CH2MODE int "TIM3 Channel 2 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH2OUT +config STM32_TIM3_CH2OUT bool "TIM3 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM3_CHANNEL2 +endif # STM32_TIM3_CHANNEL2 -config STM32F0L0G0_TIM3_CHANNEL3 +config STM32_TIM3_CHANNEL3 bool "TIM3 Channel 3" default n ---help--- Enables channel 3. -if STM32F0L0G0_TIM3_CHANNEL3 +if STM32_TIM3_CHANNEL3 -config STM32F0L0G0_TIM3_CH3MODE +config STM32_TIM3_CH3MODE int "TIM3 Channel 3 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH3OUT +config STM32_TIM3_CH3OUT bool "TIM3 Channel 3 Output" default n ---help--- Enables channel 3 output. -endif # STM32F0L0G0_TIM3_CHANNEL3 +endif # STM32_TIM3_CHANNEL3 -config STM32F0L0G0_TIM3_CHANNEL4 +config STM32_TIM3_CHANNEL4 bool "TIM3 Channel 4" default n ---help--- Enables channel 4. -if STM32F0L0G0_TIM3_CHANNEL4 +if STM32_TIM3_CHANNEL4 -config STM32F0L0G0_TIM3_CH4MODE +config STM32_TIM3_CH4MODE int "TIM3 Channel 4 Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -config STM32F0L0G0_TIM3_CH4OUT +config STM32_TIM3_CH4OUT bool "TIM3 Channel 4 Output" default n ---help--- Enables channel 4 output. -endif # STM32F0L0G0_TIM3_CHANNEL4 +endif # STM32_TIM3_CHANNEL4 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM3_CHANNEL +config STM32_TIM3_CHANNEL int "TIM3 PWM Output Channel" default 1 range 1 4 @@ -2700,68 +2633,68 @@ config STM32F0L0G0_TIM3_CHANNEL If TIM3 is enabled for PWM usage, you also need specifies the timer output channel {1,..,4} -config STM32F0L0G0_TIM3_CHMODE +config STM32_TIM3_CHMODE int "TIM3 Channel Mode" default 0 range 0 5 ---help--- - Specifies the channel mode. See STM32F0L0G0_TIM3_PWM description for available modes. + Specifies the channel mode. See STM32_TIM3_PWM description for available modes. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM3_PWM +endif # STM32_TIM3_PWM -config STM32F0L0G0_TIM3_QE +config STM32_TIM3_QE bool "TIM3 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM3 + depends on STM32_TIM3 ---help--- Reserve TIM3 for use by Quadrature Encoder. -config STM32F0L0G0_TIM4_QE +config STM32_TIM4_QE bool "TIM3 Quadrature Encoder" default n - depends on STM32F0L0G0_TIM4 + depends on STM32_TIM4 ---help--- Reserve TIM4 for use by Quadrature Encoder. menu "STM32F0L0G0 QEncoder Driver" depends on SENSORS_QENCODER - depends on STM32F0L0G0_TIM1 || STM32F0L0G0_TIM2 || STM32F0L0G0_TIM3 || STM32F0L0G0_TIM4 + depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 -config STM32F0L0G0_TIM1_QEPSC +config STM32_TIM1_QEPSC int "TIM1 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM1_QE + depends on STM32_TIM1_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM2_QEPSC +config STM32_TIM2_QEPSC int "TIM2 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM2_QE + depends on STM32_TIM2_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM3_QEPSC +config STM32_TIM3_QEPSC int "TIM3 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM3_QE + depends on STM32_TIM3_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_TIM4_QEPSC +config STM32_TIM4_QEPSC int "TIM3 QE pulse prescaler" default 1 - depends on STM32F0L0G0_TIM4_QE + depends on STM32_TIM4_QE ---help--- This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. -config STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS bool "Disable QEncoder timers extension from 16-bit to 32-bit" default n ---help--- @@ -2770,7 +2703,7 @@ config STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS counter width (16-bit or 32-bit). This reduces interrupt overhead but limits the position range for 16-bit timers. -config STM32F0L0G0_QENCODER_INDEX_PIN +config STM32_QENCODER_INDEX_PIN bool "Enable QEncoder timers support for index pin" default n ---help--- @@ -2778,122 +2711,59 @@ config STM32F0L0G0_QENCODER_INDEX_PIN used to reset the encoder position to a known value when the index pulse is detected. -config STM32F0L0G0_QENCODER_FILTER +config STM32_QENCODER_FILTER bool "Enable filtering on STM32F0L0G0 QEncoder input" default y ---help--- Enable input filtering on quadrature encoder channels to reduce noise. -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - ---help--- - Select the sampling frequency for the input filter. - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F0L0G0_QENCODER_FILTER - prompt "Input channel event count" - default STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - ---help--- - Select the number of consecutive events required to validate a transition. - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_1 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_2 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_4 - depends on STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_5 - depends on STM32F0L0G0_QENCODER_SAMPLE_FDTS_16 || STM32F0L0G0_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS && !STM32F0L0G0_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F0L0G0_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F0L0G0_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - endmenu # STM32F0L0G0 QEncoder Driver -config STM32F0L0G0_TIM14_PWM +config STM32_TIM14_PWM bool "TIM14 PWM" default n - depends on STM32F0L0G0_TIM14 - select STM32F0L0G0_PWM + depends on STM32_TIM14 + select STM32_PWM ---help--- Reserve timer 14 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM14 + to generate modulated outputs for such things as motor control. If STM32_TIM14 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM14_PWM +if STM32_TIM14_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM14_CHANNEL1 +config STM32_TIM14_CHANNEL1 bool "TIM14 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM14_CHANNEL1 +if STM32_TIM14_CHANNEL1 -config STM32F0L0G0_TIM14_CH1MODE +config STM32_TIM14_CH1MODE int "TIM14 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM14_CH1OUT +config STM32_TIM14_CH1OUT bool "TIM14 Channel 1 Output" default n ---help--- Enables channel 1 output. -endif # STM32F0L0G0_TIM14_CHANNEL1 +endif # STM32_TIM14_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM14_CHANNEL +config STM32_TIM14_CHANNEL int "TIM14 PWM Output Channel" default 1 range 1 1 @@ -2901,92 +2771,92 @@ config STM32F0L0G0_TIM14_CHANNEL If TIM14 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM14_CHMODE +config STM32_TIM14_CHMODE int "TIM14 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM14_PWM +endif # STM32_TIM14_PWM -config STM32F0L0G0_TIM15_PWM +config STM32_TIM15_PWM bool "TIM15 PWM" default n - depends on STM32F0L0G0_TIM15 - select STM32F0L0G0_PWM + depends on STM32_TIM15 + select STM32_PWM ---help--- Reserve timer 15 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM15 + to generate modulated outputs for such things as motor control. If STM32_TIM15 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM15_PWM +if STM32_TIM15_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM15_CHANNEL1 +config STM32_TIM15_CHANNEL1 bool "TIM15 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM15_CHANNEL1 +if STM32_TIM15_CHANNEL1 -config STM32F0L0G0_TIM15_CH1MODE +config STM32_TIM15_CH1MODE int "TIM15 Channel 1 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM15_CH1OUT +config STM32_TIM15_CH1OUT bool "TIM15 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM15_CH1NOUT +config STM32_TIM15_CH1NOUT bool "TIM15 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM15_CH1OUT + depends on STM32_TIM15_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM15_CHANNEL1 +endif # STM32_TIM15_CHANNEL1 -config STM32F0L0G0_TIM15_CHANNEL2 +config STM32_TIM15_CHANNEL2 bool "TIM15 Channel 2" default n ---help--- Enables channel 2. -if STM32F0L0G0_TIM15_CHANNEL2 +if STM32_TIM15_CHANNEL2 -config STM32F0L0G0_TIM15_CH2MODE +config STM32_TIM15_CH2MODE int "TIM15 Channel 2 Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM15_CH2OUT +config STM32_TIM15_CH2OUT bool "TIM15 Channel 2 Output" default n ---help--- Enables channel 2 output. -endif # STM32F0L0G0_TIM15_CHANNEL2 +endif # STM32_TIM15_CHANNEL2 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM15_CHANNEL +config STM32_TIM15_CHANNEL int "TIM15 PWM Output Channel" default 1 range 1 2 @@ -2994,69 +2864,69 @@ config STM32F0L0G0_TIM15_CHANNEL If TIM15 is enabled for PWM usage, you also need specifies the timer output channel {1,2} -config STM32F0L0G0_TIM15_CHMODE +config STM32_TIM15_CHMODE int "TIM15 Channel Mode" default 0 range 0 3 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM15_PWM +endif # STM32_TIM15_PWM -config STM32F0L0G0_TIM16_PWM +config STM32_TIM16_PWM bool "TIM16 PWM" default n - depends on STM32F0L0G0_TIM16 - select STM32F0L0G0_PWM + depends on STM32_TIM16 + select STM32_PWM ---help--- Reserve timer 16 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM16 + to generate modulated outputs for such things as motor control. If STM32_TIM16 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM16_PWM +if STM32_TIM16_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM16_CHANNEL1 +config STM32_TIM16_CHANNEL1 bool "TIM16 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM16_CHANNEL1 +if STM32_TIM16_CHANNEL1 -config STM32F0L0G0_TIM16_CH1MODE +config STM32_TIM16_CH1MODE int "TIM16 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM16_CH1OUT +config STM32_TIM16_CH1OUT bool "TIM16 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM16_CH1NOUT +config STM32_TIM16_CH1NOUT bool "TIM16 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM16_CH1OUT + depends on STM32_TIM16_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM16_CHANNEL1 +endif # STM32_TIM16_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM16_CHANNEL +config STM32_TIM16_CHANNEL int "TIM16 PWM Output Channel" default 1 range 1 1 @@ -3064,69 +2934,69 @@ config STM32F0L0G0_TIM16_CHANNEL If TIM16 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM16_CHMODE +config STM32_TIM16_CHMODE int "TIM16 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM16_PWM +endif # STM32_TIM16_PWM -config STM32F0L0G0_TIM17_PWM +config STM32_TIM17_PWM bool "TIM17 PWM" default n - depends on STM32F0L0G0_TIM17 - select STM32F0L0G0_PWM + depends on STM32_TIM17 + select STM32_PWM ---help--- Reserve timer 17 for use by PWM Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F0L0G0_TIM17 + to generate modulated outputs for such things as motor control. If STM32_TIM17 is defined then THIS following may also be defined to indicate that the timer is intended to be used for pulsed output modulation. -if STM32F0L0G0_TIM17_PWM +if STM32_TIM17_PWM -if STM32F0L0G0_PWM_MULTICHAN +if STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM17_CHANNEL1 +config STM32_TIM17_CHANNEL1 bool "TIM17 Channel 1" default n ---help--- Enables channel 1. -if STM32F0L0G0_TIM17_CHANNEL1 +if STM32_TIM17_CHANNEL1 -config STM32F0L0G0_TIM17_CH1MODE +config STM32_TIM17_CH1MODE int "TIM17 Channel 1 Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -config STM32F0L0G0_TIM17_CH1OUT +config STM32_TIM17_CH1OUT bool "TIM17 Channel 1 Output" default n ---help--- Enables channel 1 output. -config STM32F0L0G0_TIM17_CH1NOUT +config STM32_TIM17_CH1NOUT bool "TIM17 Channel 1 Complementary Output" default n - depends on STM32F0L0G0_TIM17_CH1OUT + depends on STM32_TIM17_CH1OUT ---help--- Enables channel 1 complementary output. -endif # STM32F0L0G0_TIM17_CHANNEL1 +endif # STM32_TIM17_CHANNEL1 -endif # STM32F0L0G0_PWM_MULTICHAN +endif # STM32_PWM_MULTICHAN -if !STM32F0L0G0_PWM_MULTICHAN +if !STM32_PWM_MULTICHAN -config STM32F0L0G0_TIM17_CHANNEL +config STM32_TIM17_CHANNEL int "TIM17 PWM Output Channel" default 1 range 1 1 @@ -3134,123 +3004,67 @@ config STM32F0L0G0_TIM17_CHANNEL If TIM17 is enabled for PWM usage, you also need specifies the timer output channel {1} -config STM32F0L0G0_TIM17_CHMODE +config STM32_TIM17_CHMODE int "TIM17 Channel Mode" default 0 range 0 1 ---help--- Specifies the channel mode. -endif # !STM32F0L0G0_PWM_MULTICHAN +endif # !STM32_PWM_MULTICHAN -endif # STM32F0L0G0_TIM17_PWM +endif # STM32_TIM17_PWM -config STM32F0L0G0_PWM_MULTICHAN +config STM32_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n - depends on STM32F0L0G0_PWM + depends on STM32_PWM ---help--- Specifies that the PWM driver supports multiple output channels per timer. -config STM32F0L0G0_TIM1_ADC +config STM32_TIM1_ADC bool "TIM1 ADC" default n - depends on STM32F0L0G0_TIM1 && STM32F0L0G0_ADC + depends on STM32_TIM1 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM1 ADC channel" - default STM32F0L0G0_TIM1_ADC1 - depends on STM32F0L0G0_TIM1_ADC - -config STM32F0L0G0_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM2_ADC +config STM32_TIM2_ADC bool "TIM2 ADC" default n - depends on STM32F0L0G0_TIM2 && STM32F0L0G0_ADC + depends on STM32_TIM2 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM2 ADC channel" - default STM32F0L0G0_TIM2_ADC1 - depends on STM32F0L0G0_TIM2_ADC - -config STM32F0L0G0_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM3_ADC +config STM32_TIM3_ADC bool "TIM3 ADC" default n - depends on STM32F0L0G0_TIM3 && STM32F0L0G0_ADC + depends on STM32_TIM3 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM3 ADC channel" - default STM32F0L0G0_TIM3_ADC1 - depends on STM32F0L0G0_TIM3_ADC - -config STM32F0L0G0_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -endchoice - -config STM32F0L0G0_TIM15_ADC +config STM32_TIM15_ADC bool "TIM15 ADC" default n - depends on STM32F0L0G0_TIM15 && STM32F0L0G0_ADC + depends on STM32_TIM15 && STM32_ADC ---help--- Reserve timer 1 for use by ADC -choice - prompt "Select TIM15 ADC channel" - default STM32F0L0G0_TIM15_ADC1 - depends on STM32F0L0G0_TIM15_ADC - -config STM32F0L0G0_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32F0L0G0_ADC1 - select STM32F0L0G0_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -endchoice - -config STM32F0L0G0_HAVE_ADC1_TIMER +config STM32_HAVE_ADC1_TIMER bool -config STM32F0L0G0_ADC1_SAMPLE_FREQUENCY +config STM32_ADC1_SAMPLE_FREQUENCY int "ADC1 Sampling Frequency" default 100 - depends on STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_HAVE_ADC1_TIMER ---help--- ADC1 sampling frequency. Default: 100Hz -config STM32F0L0G0_ADC1_TIMTRIG +config STM32_ADC1_TIMTRIG int "ADC1 Timer Trigger" default 0 range 0 5 - depends on STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_HAVE_ADC1_TIMER ---help--- Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. This option must match with the MCU's supported EXTSEL. @@ -3258,25 +3072,9 @@ config STM32F0L0G0_ADC1_TIMTRIG endmenu # Timer Configuration menu "FDCAN driver configuration" - depends on STM32F0L0G0_FDCAN + depends on STM32_FDCAN -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32F0L0G0_FDCAN_CHARDRIVER - -config STM32F0L0G0_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F0L0G0_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32F0L0G0_FDCAN_REGDEBUG +config STM32_FDCAN_REGDEBUG bool "CAN Register level debug" depends on DEBUG_CAN_INFO default n @@ -3284,53 +3082,14 @@ config STM32F0L0G0_FDCAN_REGDEBUG Output detailed register-level CAN device debug information. Requires also CONFIG_DEBUG_CAN_INFO. -config STM32F0L0G0_FDCAN_QUEUE_MODE +config STM32_FDCAN_QUEUE_MODE bool "FDCAN QUEUE mode (vs FIFO mode)" default n menu "FDCAN1 device driver options" - depends on STM32F0L0G0_FDCAN1 + depends on STM32_FDCAN1 -choice - prompt "FDCAN1 frame format" - default STM32F0L0G0_FDCAN1_ISO11898_1 - -config STM32F0L0G0_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32F0L0G0_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32F0L0G0_FDCAN1_CLASSIC - -config STM32F0L0G0_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32F0L0G0_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32F0L0G0_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -config STM32F0L0G0_FDCAN1_LOOPBACK +config STM32_FDCAN1_LOOPBACK bool "Enable FDCAN1 loopback mode" default n ---help--- @@ -3338,28 +3097,28 @@ config STM32F0L0G0_FDCAN1_LOOPBACK comment "Nominal Bit Timing" -config STM32F0L0G0_FDCAN1_BITRATE +config STM32_FDCAN1_BITRATE int "FDCAN bitrate" default 500000 range 0 1000000 ---help--- - FDCAN1 bitrate in bits per second. Required if STM32F0L0G0_FDCAN1 is defined. + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. -config STM32F0L0G0_FDCAN1_NTSEG1 +config STM32_FDCAN1_NTSEG1 int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" default 6 range 1 256 ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_NTSEG2 +config STM32_FDCAN1_NTSEG2 int "FDCAN1 NTSEG2 (PhaseSeg2)" default 7 range 1 128 ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_NSJW +config STM32_FDCAN1_NSJW int "FDCAN1 synchronization jump width" default 1 range 1 128 @@ -3367,36 +3126,36 @@ config STM32F0L0G0_FDCAN1_NSJW The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). comment "Data Bit Timing" - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS -config STM32F0L0G0_FDCAN1_DBITRATE +config STM32_FDCAN1_DBITRATE int "FDCAN1 data bitrate" default 2000000 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). -config STM32F0L0G0_FDCAN1_DTSEG1 +config STM32_FDCAN1_DTSEG1 int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" default 4 range 1 31 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_DTSEG2 +config STM32_FDCAN1_DTSEG2 int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" default 4 range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). -config STM32F0L0G0_FDCAN1_DSJW +config STM32_FDCAN1_DSJW int "FDCAN1 fast synchronization jump width" default 2 range 1 15 - depends on CAN_FD && STM32F0L0G0_FDCAN1_FD_BRS + depends on CAN_FD && STM32_FDCAN1_FD_BRS ---help--- The duration of a synchronization jump is Tcan_clk x DSJW. @@ -3405,34 +3164,17 @@ endmenu # FDCAN1 device driver options endmenu # "FDCAN driver configuration" menu "U[S]ART Configuration" - depends on STM32F0L0G0_USART + depends on STM32_USART comment "U[S]ART Device Configuration" -choice - prompt "USART1 Driver Configuration" - default STM32F0L0G0_USART1_SERIALDRIVER - depends on STM32F0L0G0_USART1 - -config STM32F0L0G0_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if STM32F0L0G0_USART1_SERIALDRIVER +if STM32_USART1_SERIALDRIVER config USART1_RXFIFO_THRES int "USART1 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 + depends on STM32_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -3463,32 +3205,15 @@ config USART1_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART1_SERIALDRIVER +endif # STM32_USART1_SERIALDRIVER -choice - prompt "USART2 Driver Configuration" - default STM32F0L0G0_USART2_SERIALDRIVER - depends on STM32F0L0G0_USART2 - -config STM32F0L0G0_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if STM32F0L0G0_USART2_SERIALDRIVER +if STM32_USART2_SERIALDRIVER config USART2_RXFIFO_THRES int "USART2 Rx FIFO Threshold" default 3 range 0 5 - depends on STM32F0L0G0_HAVE_IP_USART_V2 + depends on STM32_HAVE_IP_USART_V2 ---help--- Select the Rx FIFO threshold: @@ -3519,26 +3244,9 @@ config USART2_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART2_SERIALDRIVER +endif # STM32_USART2_SERIALDRIVER -choice - prompt "USART3 Driver Configuration" - default STM32F0L0G0_USART3_SERIALDRIVER - depends on STM32F0L0G0_USART3 - -config STM32F0L0G0_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if STM32F0L0G0_USART3_SERIALDRIVER +if STM32_USART3_SERIALDRIVER config USART3_RS485 bool "RS-485 on USART3" @@ -3556,26 +3264,26 @@ config USART3_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART3_SERIALDRIVER +endif # STM32_USART3_SERIALDRIVER choice prompt "USART4 Driver Configuration" - default STM32F0L0G0_USART4_SERIALDRIVER - depends on STM32F0L0G0_USART4 + default STM32_USART4_SERIALDRIVER + depends on STM32_USART4 -config STM32F0L0G0_USART4_SERIALDRIVER +config STM32_USART4_SERIALDRIVER bool "Standard serial driver" select USART4_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART4_1WIREDRIVER +config STM32_USART4_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART4 Driver Configuration -if STM32F0L0G0_USART4_SERIALDRIVER +if STM32_USART4_SERIALDRIVER config USART4_RS485 bool "RS-485 on USART4" @@ -3593,26 +3301,26 @@ config USART4_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART4_SERIALDRIVER +endif # STM32_USART4_SERIALDRIVER choice prompt "USART5 Driver Configuration" - default STM32F0L0G0_USART5_SERIALDRIVER - depends on STM32F0L0G0_USART5 + default STM32_USART5_SERIALDRIVER + depends on STM32_USART5 -config STM32F0L0G0_USART5_SERIALDRIVER +config STM32_USART5_SERIALDRIVER bool "Standard serial driver" select USART5_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART5_1WIREDRIVER +config STM32_USART5_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART5 Driver Configuration -if STM32F0L0G0_USART5_SERIALDRIVER +if STM32_USART5_SERIALDRIVER config USART5_RS485 bool "RS-485 on USART5" @@ -3630,26 +3338,9 @@ config USART5_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART5_SERIALDRIVER +endif # STM32_USART5_SERIALDRIVER -choice - prompt "USART6 Driver Configuration" - default STM32F0L0G0_USART6_SERIALDRIVER - depends on STM32F0L0G0_USART6 - -config STM32F0L0G0_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER - -config STM32F0L0G0_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER - -endchoice # USART6 Driver Configuration - -if STM32F0L0G0_USART6_SERIALDRIVER +if STM32_USART6_SERIALDRIVER config USART6_RS485 bool "RS-485 on USART6" @@ -3667,26 +3358,26 @@ config USART6_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART6_SERIALDRIVER +endif # STM32_USART6_SERIALDRIVER choice prompt "USART7 Driver Configuration" - default STM32F0L0G0_USART7_SERIALDRIVER - depends on STM32F0L0G0_USART7 + default STM32_USART7_SERIALDRIVER + depends on STM32_USART7 -config STM32F0L0G0_USART7_SERIALDRIVER +config STM32_USART7_SERIALDRIVER bool "Standard serial driver" select USART7_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART7_1WIREDRIVER +config STM32_USART7_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART7 Driver Configuration -if STM32F0L0G0_USART7_SERIALDRIVER +if STM32_USART7_SERIALDRIVER config USART7_RS485 bool "RS-485 on USART7" @@ -3704,26 +3395,26 @@ config USART7_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART7_SERIALDRIVER +endif # STM32_USART7_SERIALDRIVER choice prompt "USART8 Driver Configuration" - default STM32F0L0G0_USART8_SERIALDRIVER - depends on STM32F0L0G0_USART8 + default STM32_USART8_SERIALDRIVER + depends on STM32_USART8 -config STM32F0L0G0_USART8_SERIALDRIVER +config STM32_USART8_SERIALDRIVER bool "Standard serial driver" select USART8_SERIALDRIVER select ARCH_HAVE_SERIAL_TERMIOS - select STM32F0L0G0_SERIALDRIVER + select STM32_SERIALDRIVER -config STM32F0L0G0_USART8_1WIREDRIVER +config STM32_USART8_1WIREDRIVER bool "1-Wire driver" - select STM32F0L0G0_1WIREDRIVER + select STM32_1WIREDRIVER endchoice # USART8 Driver Configuration -if STM32F0L0G0_USART8_SERIALDRIVER +if STM32_USART8_SERIALDRIVER config USART8_RS485 bool "RS-485 on USART8" @@ -3741,12 +3432,12 @@ config USART8_RS485_DIR_POLARITY Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which enables TX (0 - low / nTXEN, 1 - high / TXEN). -endif # STM32F0L0G0_USART8_SERIALDRIVER +endif # STM32_USART8_SERIALDRIVER menu "Serial Driver Configuration" - depends on STM32F0L0G0_SERIALDRIVER + depends on STM32_SERIALDRIVER -config STM32F0L0G0_SERIAL_DISABLE_REORDERING +config STM32_SERIAL_DISABLE_REORDERING bool "Disable reordering of ttySx devices." default n ---help--- @@ -3759,10 +3450,10 @@ config STM32F0L0G0_SERIAL_DISABLE_REORDERING want the side effect of having all serial port names change when just the console is moved from serial to USB. -config STM32F0L0G0_USART_SINGLEWIRE +config STM32_USART_SINGLEWIRE bool "Single Wire Support" default n - depends on STM32F0L0G0_USART + depends on STM32_USART ---help--- Enable single wire UART support. The option enables support for the TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. @@ -3771,7 +3462,7 @@ endmenu # Serial Driver Configuration if PM -config STM32F0L0G0_PM_SERIAL_ACTIVITY +config STM32_PM_SERIAL_ACTIVITY int "PM serial activity" default 10 ---help--- @@ -3783,20 +3474,20 @@ endif # PM endmenu # U[S]ART Configuration menu "ADC Configuration" - depends on STM32F0L0G0_ADC + depends on STM32_ADC -config STM32F0L0G0_ADC1_RESOLUTION +config STM32_ADC1_RESOLUTION int "ADC1 resolution" - depends on STM32F0L0G0_ADC1 + depends on STM32_ADC1 default 0 range 0 3 ---help--- ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32F0L0G0_ADC_MAX_SAMPLES +config STM32_ADC_MAX_SAMPLES int "The maximum number of channels that can be sampled" - default 16 if STM32F0L0G0_ADC1_DMA - default 1 if !STM32F0L0G0_ADC1_DMA + default 16 if STM32_ADC1_DMA + default 1 if !STM32_ADC1_DMA ---help--- The maximum number of samples which can be handled without overrun depends on various factors. This is the user's @@ -3805,66 +3496,66 @@ config STM32F0L0G0_ADC_MAX_SAMPLES for all supported devices, the user can change the default values in the board initialization logic and avoid ADC overrun. -config STM32F0L0G0_ADC_NO_STARTUP_CONV +config STM32_ADC_NO_STARTUP_CONV bool "Do not start conversion when opening ADC device" default n ---help--- Do not start conversion when opening ADC device. -config STM32F0L0G0_ADC_NOIRQ +config STM32_ADC_NOIRQ bool "Do not use default ADC interrupts" default n ---help--- Do not use default ADC interrupts handlers. -config STM32F0L0G0_ADC_LL_OPS +config STM32_ADC_LL_OPS bool "ADC low-level operations" default n ---help--- Enable low-level ADC ops. -config STM32F0L0G0_ADC_CHANGE_SAMPLETIME +config STM32_ADC_CHANGE_SAMPLETIME bool "ADC sample time configuration" default n - depends on STM32F0L0G0_ADC_LL_OPS + depends on STM32_ADC_LL_OPS ---help--- Enable ADC sample time configuration (SMPRx registers). -config STM32F0L0G0_ADC1_DMA +config STM32_ADC1_DMA bool "ADC1 DMA" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC1_DMA + depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA default n ---help--- If DMA is selected, then the ADC may be configured to support DMA transfer, which is necessary if multiple channels are read or if very high trigger frequencies are used. -config STM32F0L0G0_ADC1_DMA_CFG +config STM32_ADC1_DMA_CFG int "ADC1 DMA configuration" - depends on STM32F0L0G0_ADC1_DMA && !STM32F0L0G0_HAVE_IP_ADC_V1_BASIC + depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC range 0 1 default 0 ---help--- 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode -config STM32F0L0G0_ADC_OVERSAMPLE +config STM32_ADC_OVERSAMPLE bool "Enable ADC hardware oversampling support" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_HAVE_ADC_OVERSAMPLE + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE default n ---help--- Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). Only STM32G0 and STM32L0 series include this hardware block. -if STM32F0L0G0_ADC_OVERSAMPLE +if STM32_ADC_OVERSAMPLE -config STM32F0L0G0_ADC_TOVS +config STM32_ADC_TOVS bool "Enable triggered oversampling (CFGR2.TOVS)" default n ---help--- If set, oversampling will only occur when a trigger event occurs. If not set, oversampling occurs continuously (TOVS=0). -config STM32F0L0G0_ADC_OVSR +config STM32_ADC_OVSR int "Oversampling ratio (CFGR2.OVSR)" default 0 range 0 7 @@ -3876,7 +3567,7 @@ config STM32F0L0G0_ADC_OVSR ... 7 -> 256× -config STM32F0L0G0_ADC_OVSS +config STM32_ADC_OVSS int "Oversampling right-shift bits (CFGR2.OVSS)" default 0 range 0 8 @@ -3884,11 +3575,11 @@ config STM32F0L0G0_ADC_OVSS Sets how many bits the accumulated result is right-shifted. Max of 8-bits. -endif # STM32F0L0G0_ADC_OVERSAMPLE +endif # STM32_ADC_OVERSAMPLE -config STM32F0L0G0_ADC1_DMA_BATCH +config STM32_ADC1_DMA_BATCH int "ADC1 DMA number of conversions" - depends on STM32F0L0G0_ADC1 && STM32F0L0G0_ADC1_DMA + depends on STM32_ADC1 && STM32_ADC1_DMA default 1 ---help--- This option allows you to select the number of regular group conversions @@ -3896,17 +3587,17 @@ config STM32F0L0G0_ADC1_DMA_BATCH By default, this value is 1, which means that data is transferred after each group conversion. -config STM32F0L0G0_ADC1_EXTSEL +config STM32_ADC1_EXTSEL bool "ADC1 external trigger for regular group" - depends on STM32F0L0G0_ADC1 && !STM32F0L0G0_HAVE_ADC1_TIMER + depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER default n ---help--- Enable EXTSEL for ADC1. -config STM32F0L0G0_ADC1_CONTINUOUS +config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" default n - depends on STM32F0L0G0_ADC1 + depends on STM32_ADC1 ---help--- If enabled, the ADC will operate in continuous conversion mode. Otherwise, it will perform single conversions. @@ -3916,9 +3607,9 @@ config STM32F0L0G0_ADC1_CONTINUOUS endmenu # ADC Configuration menu "SPI Configuration" - depends on STM32F0L0G0_SPI + depends on STM32_SPI -config STM32F0L0G0_SPI_INTERRUPTS +config STM32_SPI_INTERRUPTS bool "Interrupt driver SPI" default n ---help--- @@ -3926,87 +3617,87 @@ config STM32F0L0G0_SPI_INTERRUPTS poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -config STM32F0L0G0_SPI1_DMA +config STM32_SPI1_DMA bool "SPI1 DMA" default n - depends on STM32F0L0G0_SPI1 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI1 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI2_DMA +config STM32_SPI2_DMA bool "SPI2 DMA" default n - depends on STM32F0L0G0_SPI2 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI2 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI3_DMA +config STM32_SPI3_DMA bool "SPI3 DMA" default n - depends on STM32F0L0G0_SPI3 && !STM32F0L0G0_SPI_INTERRUPTS - select STM32F0L0G0_SPI_DMA + depends on STM32_SPI3 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F0L0G0_SPI_INTERRUPT. + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. -config STM32F0L0G0_SPI1_COMMTYPE +config STM32_SPI1_COMMTYPE int "SPI1 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI1 + depends on STM32_SPI1 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) -config STM32F0L0G0_SPI2_COMMTYPE +config STM32_SPI2_COMMTYPE int "SPI2 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI2 + depends on STM32_SPI2 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) -config STM32F0L0G0_SPI3_COMMTYPE +config STM32_SPI3_COMMTYPE int "SPI3 Operation mode" default 0 range 0 3 - depends on STM32F0L0G0_SPI3 + depends on STM32_SPI3 ---help--- Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) endmenu # SPI Configuration menu "I2C Configuration" - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2C_DYNTIMEO +config STM32_I2C_DYNTIMEO bool "Use dynamic timeouts" default n - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE +config STM32_I2C_DYNTIMEO_USECPERBYTE int "Timeout Microseconds per Byte" default 500 - depends on STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP +config STM32_I2C_DYNTIMEO_STARTSTOP int "Timeout for Start/Stop (Milliseconds)" default 1000 - depends on STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2CTIMEOSEC +config STM32_I2CTIMEOSEC int "Timeout seconds" default 0 - depends on STM32F0L0G0_I2C + depends on STM32_I2C -config STM32F0L0G0_I2CTIMEOMS +config STM32_I2CTIMEOMS int "Timeout Milliseconds" default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C && !STM32_I2C_DYNTIMEO -config STM32F0L0G0_I2CTIMEOTICKS +config STM32_I2CTIMEOTICKS int "Timeout for Done and Stop (ticks)" default 500 - depends on STM32F0L0G0_I2C && !STM32F0L0G0_I2C_DYNTIMEO + depends on STM32_I2C && !STM32_I2C_DYNTIMEO endmenu #I2C Configuration diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index e4ab1438876..8ff7580bde2 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -25,15 +25,15 @@ include armv6-m/Make.defs CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c -ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),) +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F0L0G0_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F0L0G0_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -49,69 +49,69 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32F0L0G0_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif -ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y) +ifeq ($(CONFIG_STM32_GPIOIRQ),y) CHIP_CSRCS += stm32_gpioint.c endif -ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32F0L0G0_USB),y) +ifeq ($(CONFIG_STM32_USB),y) CHIP_CSRCS += stm32_usbdev.c endif -ifeq ($(CONFIG_STM32F0L0G0_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F0L0G0_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32F0L0G0_TIM1_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif endif -ifeq ($(CONFIG_STM32F0L0G0_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F0L0G0_AES),y) +ifeq ($(CONFIG_STM32_AES),y) CHIP_CSRCS += stm32_aes.c endif -ifeq ($(CONFIG_STM32F0L0G0_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F0L0G0_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F0L0G0_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32F0L0G0_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CHIP_CSRCS += stm32_fdcan.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) CHIP_CSRCS += stm32_fdcan_sock.c endif endif diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h index b855b530df5..f074647fe54 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h @@ -49,7 +49,7 @@ /* Support for ADC clock prescaler */ -#if defined(CONFIG_STM32F0L0G0_STM32L0) || defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32L0) || defined(CONFIG_STM32_STM32G0) # define HAVE_ADC_PRE #else # undef HAVE_ADC_PRE @@ -57,7 +57,7 @@ /* Support for LCD voltage */ -#ifdef CONFIG_STM32F0L0G0_HAVE_LCD +#ifdef CONFIG_STM32_HAVE_LCD # define HAVE_ADC_VLCD #else # undef HAVE_ADC_VLCD @@ -65,7 +65,7 @@ /* Support for Low frequency mode */ -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE +#ifdef CONFIG_STM32_ENERGYLITE # define HAVE_ADC_LFM #else # undef HAVE_ADC_LFM diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h index 31402fafbc0..ccab2c6f14a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h @@ -151,9 +151,9 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32G0) # include "hardware/stm32g0_dmamux.h" -#elif defined(CONFIG_STM32F0L0G0_STM32C0) +#elif defined(CONFIG_STM32_STM32C0) # include "hardware/stm32c0_dmamux.h" #else # error "Unsupported STM32 M0 sub family" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h index dba663e2a36..f6f07839c12 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F03X) +#if defined(CONFIG_STM32_STM32F03X) # include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) || \ - defined(CONFIG_STM32F0L0G0_STM32F07X) || \ - defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_STM32_STM32F05X) || \ + defined(CONFIG_STM32_STM32F07X) || \ + defined(CONFIG_STM32_STM32F09X) # include "hardware/stm32f05xf07xf09x_memorymap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_memorymap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h index 54cea66eed1..3f1e617b3cb 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h @@ -30,13 +30,13 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_STM32F03X) +#if defined(CONFIG_STM32_STM32F03X) # include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F05X) +#elif defined(CONFIG_STM32_STM32F05X) # include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F07X) +#elif defined(CONFIG_STM32_STM32F07X) # include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_STM32_STM32F09X) # include "hardware/stm32f09x_pinmap.h" #elif defined(CONFIG_ARCH_CHIP_STM32L0) # include "hardware/stm32l0_pinmap.h" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h index 0a058ebf094..fd63397093e 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h @@ -32,11 +32,11 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32F0) || \ + defined(CONFIG_STM32_STM32G0) || \ + defined(CONFIG_STM32_STM32C0) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32L0) # define HAVE_IP_SPI_V1 #else # error Unsupported family diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h index 91fea96af14..7149293388a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h @@ -41,7 +41,7 @@ #if defined(CONFIG_ARCH_CHIP_STM32L0) # define HAVE_TIM2_16BIT 1 # undef HAVE_TIM2_32BIT -#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32F09X) +#elif defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_STM32_STM32F09X) # define HAVE_TIM2_32BIT 1 # undef HAVE_TIM2_16BIT #else diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h index 576fcddc3e3..1a03d8f4dcd 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "hardware/stm32_uart_v2.h" #else # error "Unsupported STM32 M0 USART" diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h index 9b1c6c78ce1..52f0df5aef2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ b/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_STM32F0L0G0_HAVE_USBDEV +#ifdef CONFIG_STM32_HAVE_USBDEV /**************************************************************************** * Pre-processor Definitions @@ -251,5 +251,5 @@ #define USB_COUNT_RX_SHIFT (0) /* Bits 9-0: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32F0L0G0_HAVE_USBDEV */ +#endif /* CONFIG_STM32_HAVE_USBDEV */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/stm32f0l0g0/stm32_adc.c index 8435f1f8b6f..6366eb0ed32 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.c @@ -54,13 +54,13 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F0L0G0_ADC +#ifdef CONFIG_STM32_ADC /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) -#if defined(CONFIG_STM32F0L0G0_STM32F0) +#if defined(CONFIG_STM32_STM32F0) # error Not tested #endif @@ -90,11 +90,11 @@ /* C0 and G0 support additional sample time selection 2 */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) # define ADC_HAVE_SMPR_SMP2 #endif -#if defined(ADC_HAVE_DMA) || (CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES == 1) +#if defined(ADC_HAVE_DMA) || (CONFIG_STM32_ADC_MAX_SAMPLES == 1) # if defined(CONFIG_ARCH_CHIP_STM32C0) || defined(CONFIG_ARCH_CHIP_STM32G0) # define ADC_SMP1_DEFAULT ADC_SMPR_12p5 # define ADC_SMP2_DEFAULT ADC_SMPR_12p5 @@ -121,10 +121,10 @@ * (ST manual) */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || \ - defined(CONFIG_STM32F0L0G0_STM32L0) || \ - defined(CONFIG_STM32F0L0G0_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32F0) || \ + defined(CONFIG_STM32_STM32L0) || \ + defined(CONFIG_STM32_STM32C0) || \ + defined(CONFIG_STM32_STM32G0) # define ADC_CHANNELS_NUMBER 19 #else # error "Not supported" @@ -155,7 +155,7 @@ #define ADC_HAVE_DMACFG 1 -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32L0) # ifndef ANIOC_SET_OVERSAMPLE # define ANIOC_SET_OVERSAMPLE _ANIOC(0x0f) # endif @@ -181,10 +181,10 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) | defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) | defined(ADC_HAVE_DMA) const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -206,7 +206,7 @@ struct stm32_dev_s bool hasdma; /* True: This channel supports DMA */ uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. */ # ifdef ADC_HAVE_SMPR_SMP2 @@ -242,7 +242,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -280,10 +280,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc1_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -334,7 +334,7 @@ static int adc_extcfg_set(struct adc_dev_s *dev, uint32_t extcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static void adc_llops_intack(struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(struct stm32_adc_dev_s *dev, @@ -349,7 +349,7 @@ static void adc_llops_reg_startconv(struct stm32_adc_dev_s *dev, static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, uint16_t *buffer, uint8_t len); # endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -375,7 +375,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -387,7 +387,7 @@ static const struct stm32_adc_ops_s g_adc_llops = # ifdef ADC_HAVE_DMA .regbuf_reg = adc_llops_regbufregister, # endif -# ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -397,47 +397,47 @@ static const struct stm32_adc_ops_s g_adc_llops = /* ADC1 state */ -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES * - CONFIG_STM32F0L0G0_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc1_interrupt, -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ #ifdef HAVE_ADC_CMN_DATA .cmn = &ADC1CMN_DATA, #endif .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32F0L0G0_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, #endif .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F0L0G0_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, # ifdef ADC_HAVE_DMACFG - .dmacfg = CONFIG_STM32F0L0G0_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, # endif .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F0L0G0_ADC1_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH #endif }; @@ -1178,7 +1178,7 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset) switch (priv->intf) { -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) case 1: { adcbit = RCC_RSTR_ADC1RST; @@ -1322,7 +1322,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, static int adc_bind(struct adc_dev_s *dev, const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1399,7 +1399,7 @@ static void adc_mode_cfg(struct stm32_dev_s *priv) clrbits |= ADC_CFGR1_EXTEN_MASK; setbits |= ADC_CFGR1_EXTEN_NONE; -#ifdef CONFIG_STM32F0L0G0_ADC1_CONTINUOUS +#ifdef CONFIG_STM32_ADC1_CONTINUOUS setbits |= ADC_CFGR1_CONT; #endif @@ -1432,7 +1432,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) /* Initialize the same sample time for each ADC. * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME struct adc_sample_time_s time_samples = { # ifdef STM32_ADC1_SMPR_SMP1 .smp1 = STM32_ADC1_SMPR_SMP1, @@ -1682,7 +1682,7 @@ static void adc_configure(struct adc_dev_s *dev) adc_dumpregs(priv); } - #ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE + #ifdef CONFIG_STM32_ADC_OVERSAMPLE /**************************************************************************** * Name: adc_oversample @@ -1696,10 +1696,10 @@ static void adc_oversample(struct adc_dev_s *dev) ADC_CFGR2_OVSR_MASK | ADC_CFGR2_OVSS_MASK; uint32_t setbits = ADC_CFGR2_OVSE | - (CONFIG_STM32F0L0G0_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | - (CONFIG_STM32F0L0G0_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); + (CONFIG_STM32_ADC_OVSR << ADC_CFGR2_OVSR_SHIFT) | + (CONFIG_STM32_ADC_OVSS << ADC_CFGR2_OVSS_SHIFT); -# ifdef CONFIG_STM32F0L0G0_ADC_TOVS +# ifdef CONFIG_STM32_ADC_TOVS setbits |= ADC_CFGR2_TOVS; # endif @@ -1779,15 +1779,15 @@ static void adc_reset(struct adc_dev_s *dev) static int adc_setup(struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32F0L0G0_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ - defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(HAVE_ADC_CMN_DATA) || \ + defined(ADC_HAVE_TIMER) || !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1804,7 +1804,7 @@ static int adc_setup(struct adc_dev_s *dev) adc_configure(dev); -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE +#ifdef CONFIG_STM32_ADC_OVERSAMPLE adc_oversample(dev); #endif @@ -1829,7 +1829,7 @@ static int adc_setup(struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32F0L0G0_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1838,7 +1838,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1880,7 +1880,7 @@ static void adc_shutdown(struct adc_dev_s *dev) adc_enable(priv, false); -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2274,7 +2274,7 @@ static int adc_ioc_change_ints(struct adc_dev_s *dev, int cmd, bool arg) return ret; } -#ifdef CONFIG_STM32F0L0G0_ADC_OVERSAMPLE +#ifdef CONFIG_STM32_ADC_OVERSAMPLE /**************************************************************************** * Name: adc_ioc_set_oversample @@ -2494,7 +2494,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) break; } -#if defined(CONFIG_STM32F0L0G0_ADC_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC_OVERSAMPLE) case ANIOC_SET_OVERSAMPLE: { ret = adc_ioc_set_oversample(dev, arg); @@ -2513,7 +2513,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F0L0G0_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2620,9 +2620,9 @@ static int adc1_interrupt(int irq, void *context, void *arg) return OK; } -#endif /* CONFIG_STM32F0L0G0_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2736,7 +2736,7 @@ static int adc_llops_regbufregister(struct stm32_adc_dev_s *dev, } #endif /* ADC_HAVE_DMA */ -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /**************************************************************************** * Name: adc_sampletime_write * @@ -2796,7 +2796,7 @@ static void adc_sampletime_set(struct stm32_adc_dev_s *dev, priv->smpsel = time_samples->smpsel; #endif } -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -2809,7 +2809,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -2841,7 +2841,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); @@ -2862,7 +2862,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(channels <= CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES); + DEBUGASSERT(channels <= CONFIG_STM32_ADC_MAX_SAMPLES); priv->cr_channels = channels; memcpy(priv->r_chanlist, chanlist, channels); @@ -2878,5 +2878,5 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32F0L0G0_ADC1 */ -#endif /* CONFIG_STM32F0L0G0_ADC */ +#endif /* CONFIG_STM32_ADC1 */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/stm32f0l0g0/stm32_adc.h index 89ac9b8da5d..579d1ffc21c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/stm32f0l0g0/stm32_adc.h @@ -43,45 +43,45 @@ /* Configuration ************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * to control periodic ADC sampling. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_ADC must also be defined to indicate that + * to control periodic ADC sampling. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_ADC must also be defined to indicate that * timer "n" is intended to be used for that purpose. Timers 1-6 and 8 may * be used. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_ADC -# undef CONFIG_STM32F0L0G0_TIM1_ADC1 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_ADC -# undef CONFIG_STM32F0L0G0_TIM2_ADC1 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_ADC -# undef CONFIG_STM32F0L0G0_TIM3_ADC1 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 #endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_ADC -# undef CONFIG_STM32F0L0G0_TIM15_ADC1 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 #endif /* Up to 1 ADC interfaces are supported */ #if STM32_NADC < 1 -# undef CONFIG_STM32F0L0G0_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_STM32_ADC1) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F0L0G0_ADC1_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F0L0G0_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA @@ -91,19 +91,19 @@ * information about the timer. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM15_CLKIN @@ -112,11 +112,11 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F0L0G0_ADC1_TIMTRIG -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -129,7 +129,7 @@ /* EXTSEL */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) +#if defined(CONFIG_STM32_STM32F0) # define ADC1_EXTSEL_T1TRGO ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -139,7 +139,7 @@ * TRG6 reserved * TRG7 reserved */ -#elif defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32L0) /* TRG0 reserved */ # define ADC1_EXTSEL_T21CC2 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -148,7 +148,7 @@ # define ADC1_EXTSEL_T2CC3 ADC12_CFGR1_EXTSEL_TRG5 /* TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0) +#elif defined(CONFIG_STM32_STM32G0) # define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -156,7 +156,7 @@ # define ADC1_EXTSEL_T15TRGO ADC12_CFGR1_EXTSEL_TRG4 /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 -#elif defined(CONFIG_STM32F0L0G0_STM32C0) +#elif defined(CONFIG_STM32_STM32C0) # define ADC1_EXTSEL_T1TRGO2 ADC12_CFGR1_EXTSEL_TRG0 # define ADC1_EXTSEL_T1CC4 ADC12_CFGR1_EXTSEL_TRG1 # define ADC1_EXTSEL_T2TRGO ADC12_CFGR1_EXTSEL_TRG2 @@ -171,49 +171,49 @@ /* EXTSEL configuration *****************************************************/ /* NOTE: - * this configuration if used only if CONFIG_STM32F0L0G0_TIMx_ADCy is + * this configuration if used only if CONFIG_STM32_TIMx_ADCy is * selected. * You can still connect the ADC with a timer trigger using the - * CONFIG_STM32F0L0G0_ADCx_EXTSEL option. + * CONFIG_STM32_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM2_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM3_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM15_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F0L0G0_TIM21_ADC1) -# if CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM21_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21CC2 -# elif CONFIG_STM32F0L0G0_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T21TRGO # else -# error "CONFIG_STM32F0L0G0_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif @@ -222,7 +222,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F0L0G0_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -322,9 +322,9 @@ enum stm32_adc_resoluton_e ADC_RESOLUTION_6BIT = 3 /* 6 bit */ }; -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME struct adc_sample_time_s { @@ -332,7 +332,7 @@ struct adc_sample_time_s uint8_t smp2; /* Sample time for channels with SMPSEL bit = 1 */ uint32_t smpsel; /* Bitmask for selecting which channels use SMP2 */ }; -#endif /* CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -380,7 +380,7 @@ struct stm32_adc_ops_s void (*reg_startconv)(struct stm32_adc_dev_s *dev, bool state); -#ifdef CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -394,7 +394,7 @@ struct stm32_adc_ops_s void (*dump_regs)(struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32F0L0G0_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -433,7 +433,7 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, * Name: stm32_adc_llops_get ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *stm32_adc_llops_get(struct adc_dev_s *dev); #endif @@ -444,5 +444,5 @@ const struct stm32_adc_ops_s #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/stm32f0l0g0/stm32_dma.c index 4d60de3763b..3e3b9af30ea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma.c @@ -28,7 +28,7 @@ #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_DMAMUX) +#if defined(CONFIG_STM32_HAVE_DMAMUX) # include "stm32_dma_v1mux.c" #else # include "stm32_dma_v1.c" diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h index 0d6d729a0cc..ce5cb1a18af 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ b/arch/arm/src/stm32f0l0g0/stm32_dma.h @@ -32,7 +32,7 @@ #include "hardware/stm32_dma_v1.h" -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX +#ifdef CONFIG_STM32_HAVE_DMAMUX # include "hardware/stm32_dmamux.h" #endif @@ -238,7 +238,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c index 28ffac90950..3117fad02ec 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c @@ -51,7 +51,7 @@ * the DMA requests for each channel. */ -#ifdef CONFIG_STM32F0L0G0_HAVE_DMAMUX +#ifdef CONFIG_STM32_HAVE_DMAMUX # error DMAMUX not supported here. Look at stm32_dma_v1mux.c #endif @@ -628,7 +628,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c index a179bc8b9de..e622ab417d5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c @@ -50,20 +50,20 @@ #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 # if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) # define DMA1_NCHAN 5 # define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) +# elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) # define DMA1_NCHAN 7 # define DMA2_NCHAN 0 -# elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +# elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define DMA1_NCHAN 7 # define DMA2_NCHAN 5 # else @@ -86,16 +86,16 @@ /* DMAMUX channels */ #if defined(CONFIG_ARCH_CHIP_STM32C0) || \ - defined(CONFIG_STM32F0L0G0_STM32G03X) || \ - defined(CONFIG_STM32F0L0G0_STM32G041) + defined(CONFIG_STM32_STM32G03X) || \ + defined(CONFIG_STM32_STM32G041) # define DMAMUX_NCHANNELS 5 -#elif defined(CONFIG_STM32F0L0G0_STM32G05X) || \ - defined(CONFIG_STM32F0L0G0_STM32G061) || \ - defined(CONFIG_STM32F0L0G0_STM32G07X) || \ - defined(CONFIG_STM32F0L0G0_STM32G081) +#elif defined(CONFIG_STM32_STM32G05X) || \ + defined(CONFIG_STM32_STM32G061) || \ + defined(CONFIG_STM32_STM32G07X) || \ + defined(CONFIG_STM32_STM32G081) # define DMAMUX_NCHANNELS 7 -#elif defined(CONFIG_STM32F0L0G0_STM32G0BX) || \ - defined(CONFIG_STM32F0L0G0_STM32G0C1) +#elif defined(CONFIG_STM32_STM32G0BX) || \ + defined(CONFIG_STM32_STM32G0C1) # define DMAMUX_NCHANNELS 12 #else # error "Unknown chip for DMAMUX channel count" @@ -191,7 +191,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_dma12_disable(DMA_CHANNEL dmachan); static int stm32_dma12_interrupt(int irq, void *context, void *arg); static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -237,7 +237,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -257,7 +257,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -293,7 +293,7 @@ static const struct stm32_dmamux_s g_dmamux[DMAMUX_NUM] = static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -305,7 +305,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -322,7 +322,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -396,7 +396,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = # endif #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -628,7 +628,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_DMA1) || defined(CONFIG_STM32F0L0G0_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_dma12_disable @@ -680,14 +680,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { channel = irq - STM32_IRQ_DMA2CH1; @@ -753,7 +753,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -942,7 +942,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32F0L0G0_DMA1 || CONFIG_STM32F0L0G0_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32_dmamux_sample @@ -1334,7 +1334,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c index 433b0b6e399..5e8beb51a12 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V2) # define STM32_EXTI_FTSR STM32_EXTI_FTSR1 # define STM32_EXTI_RTSR STM32_EXTI_RTSR1 # define STM32_EXTI_IMR STM32_EXTI_IMR1 @@ -77,7 +77,7 @@ static struct gpio_callback_s g_gpio_callbacks[16]; * Interrupt Service Routines - Dispatchers ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { @@ -121,7 +121,7 @@ static int stm32_exti_multiisr(int irq, void *context, void *arg, return ret; } -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) static int stm32_exti_multiisr(int irq, void *context, void *arg, int first, int last) { diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c index 8f35cb89f26..02d2c0f773d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c @@ -72,7 +72,7 @@ # define FDCAN_MSGRAM_WORDS (212) # define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# ifdef CONFIG_STM32F0L0G0_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -93,16 +93,16 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -117,19 +117,19 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 # define FDCAN1_DBRP 1 # define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ # if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX # error Invalid FDCAN1 DTSEG1 @@ -156,12 +156,12 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* Loopback mode */ #undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) # define STM32_FDCAN_LOOPBACK 1 #endif @@ -243,7 +243,7 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif /**************************************************************************** @@ -348,7 +348,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -364,7 +364,7 @@ struct stm32_fdcan_s static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -441,7 +441,7 @@ static const struct can_ops_s g_fdcanops = .co_txempty = fdcan_txempty, }; -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -451,7 +451,7 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -463,14 +463,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_0, .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -486,7 +486,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -508,7 +508,7 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; static struct can_dev_s g_fdcan1dev; -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /**************************************************************************** * Private Functions @@ -528,7 +528,7 @@ static struct can_dev_s g_fdcan1dev; * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -608,7 +608,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -648,7 +648,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -694,7 +694,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -737,7 +737,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -786,7 +786,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -3096,7 +3096,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; @@ -3185,7 +3185,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h index b96772738a2..83893b284ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h @@ -65,7 +65,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /**************************************************************************** * Name: stm32_fdcaninitialize @@ -84,7 +84,7 @@ extern "C" struct can_dev_s *stm32_fdcaninitialize(int port); #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /**************************************************************************** * Name: stm32_fdcansockinitialize diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c index 46464bec395..f17be5729df 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c @@ -93,7 +93,7 @@ # define FDCAN_MSGRAM_WORDS (212) # define STM32_CANRAM1_BASE (STM32_CANRAM_BASE + 0x0000) -# ifdef CONFIG_STM32F0L0G0_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -114,16 +114,16 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# define FDCAN1_NTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32F0L0G0_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -138,19 +138,19 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32F0L0G0_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32F0L0G0_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32F0L0G0_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32F0L0G0_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 # define FDCAN1_DBRP 1 # define FDCAN1_DSJW 1 -# endif /* CONFIG_STM32F0L0G0_FDCAN1_FD_BRS */ +# endif /* CONFIG_STM32_FDCAN1_FD_BRS */ # if FDCAN1_DTSEG1 > FDCAN_DBTP_DTSEG1_MAX # error Invalid FDCAN1 DTSEG1 @@ -177,12 +177,12 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* Loopback mode */ #undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK) +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) # define STM32_FDCAN_LOOPBACK 1 #endif @@ -259,7 +259,7 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif /**************************************************************************** @@ -362,7 +362,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -399,7 +399,7 @@ struct stm32_fdcan_s static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -489,7 +489,7 @@ static int fdcan_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -499,7 +499,7 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32F0L0G0_FDCAN1_BITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -511,14 +511,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_0, .irq1 = STM32_IRQ_FDCAN1_1, -#if defined(CONFIG_STM32F0L0G0_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32F0L0G0_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32F0L0G0_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -534,7 +534,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32F0L0G0_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -555,7 +555,7 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; -#endif /* CONFIG_STM32F0L0G0_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /**************************************************************************** * Private Functions @@ -575,7 +575,7 @@ static struct stm32_fdcan_s g_fdcan1priv; * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -655,7 +655,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -695,7 +695,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -741,7 +741,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -784,7 +784,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -833,7 +833,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -2567,7 +2567,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32F0L0G0_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; @@ -2916,7 +2916,7 @@ int stm32_fdcansockinitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ @@ -2984,7 +2984,7 @@ errout: #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F0L0G0_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_fdcansockinitialize(FDCAN1); #endif } diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/stm32f0l0g0/stm32_flash.c index 8e2d4b7dd59..010d5059c0c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ b/arch/arm/src/stm32f0l0g0/stm32_flash.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F0L0G0_STM32G0) || defined(CONFIG_STM32F0L0G0_STM32C0) +#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) # include "stm32g0c0_flash.c" #else # error "Flash driver unsupported on selected chip." diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/stm32f0l0g0/stm32_gpio.c index 19d50cf7637..7917ca44a79 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.c @@ -40,9 +40,9 @@ #include "chip.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # include "hardware/stm32_syscfg.h" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) # include "hardware/stm32_exti.h" #endif @@ -317,7 +317,7 @@ int stm32_configgpio(uint32_t cfgset) uint32_t regaddr; int shift; -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V1) +#if defined(CONFIG_STM32_HAVE_IP_EXTI_V1) /* Set the bits in the SYSCFG EXTICR register */ regaddr = STM32_SYSCFG_EXTICR(pin); @@ -327,7 +327,7 @@ int stm32_configgpio(uint32_t cfgset) regval |= (((uint32_t)port) << shift); putreg32(regval, regaddr); -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_EXTI_V2) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V2) /* Set the bits in the EXTI EXTICR register */ regaddr = STM32_EXTI_EXTICR(pin); diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/stm32f0l0g0/stm32_gpio.h index d4a90cc5712..0d6e7c881ac 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ b/arch/arm/src/stm32f0l0g0/stm32_gpio.h @@ -188,7 +188,7 @@ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ -#if defined (CONFIG_STM32F0L0G0_STM32F03X) +#if defined (CONFIG_STM32_STM32F03X) # define GPIO_PORTF (4 << GPIO_PORT_SHIFT) /* GPIOF */ #else # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h index 37a6981ff5d..216fce2501e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/stm32f0l0g0/stm32_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32F0L0G0_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32F0L0G0_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/stm32f0l0g0/stm32_i2c.c index 1991004a026..b2f689f9798 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.c @@ -153,24 +153,24 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32F0L0G0_I2C1 - * CONFIG_STM32F0L0G0_I2C2 - * CONFIG_STM32F0L0G0_I2C3 - * CONFIG_STM32F0L0G0_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F0L0G0_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F0L0G0_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F0L0G0_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F0L0G0_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -243,8 +243,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F0L0G0_I2C1) || defined(CONFIG_STM32F0L0G0_I2C2) || \ - defined(CONFIG_STM32F0L0G0_I2C3) || defined(CONFIG_STM32F0L0G0_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -260,25 +260,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) && !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOSEC) -# define CONFIG_STM32F0L0G0_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F0L0G0_I2CTIMEOMS) -# define CONFIG_STM32F0L0G0_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F0L0G0_I2CTIMEOTICKS -# define CONFIG_STM32F0L0G0_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F0L0G0_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F0L0G0_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -448,9 +448,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F0L0G0_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -490,7 +490,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -525,7 +525,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -595,7 +595,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -724,7 +724,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -741,7 +741,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -798,12 +798,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F0L0G0_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -841,10 +841,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F0L0G0_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F0L0G0_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2708,22 +2708,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F0L0G0_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2810,5 +2810,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F0L0G0_I2C1 || CONFIG_STM32F0L0G0_I2C2 || \ - * CONFIG_STM32F0L0G0_I2C3 || CONFIG_STM32F0L0G0_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h index 0a52455ba33..9d1d09b17a9 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ b/arch/arm/src/stm32f0l0g0/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F0L0G0_I2C_DYNTIMEO -# if CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F0L0G0_I2C_DYNTIMEO because of CONFIG_STM32F0L0G0_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F0L0G0_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/stm32f0l0g0/stm32_idle.c index e6f004d6099..1b971a961ca 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ b/arch/arm/src/stm32f0l0g0/stm32_idle.c @@ -83,7 +83,7 @@ void up_idle(void) * disabled in order to save power." */ -#ifdef CONFIG_STM32F0L0G0_GPDMA +#ifdef CONFIG_STM32_GPDMA if (g_dma_inprogress == 0) #endif { diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/stm32f0l0g0/stm32_irq.c index a6e21b8ca8e..c46388c2641 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/stm32f0l0g0/stm32_irq.c @@ -217,7 +217,7 @@ void up_irqinitialize(void) * configured pin interrupts. */ -#ifdef CONFIG_STM32F0L0G0_GPIOIRQ +#ifdef CONFIG_STM32_GPIOIRQ stm32_gpioirqinitialize(); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c index b15eb7eb39f..91bd0cfbeae 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc.c @@ -27,9 +27,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "stm32_lowputc_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c index 81bcd23faf2..2f3e87315b3 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c @@ -268,7 +268,7 @@ void stm32_lowsetup(void) /* Setup clocking and GPIO pins for all configured USARTs */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* Enable USART APB2 clock */ modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_USART1EN); @@ -284,7 +284,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART2EN); @@ -300,7 +300,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART3EN); @@ -316,7 +316,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART4EN); @@ -332,7 +332,7 @@ void stm32_lowsetup(void) #endif #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* Enable USART APB1 clock */ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_USART5EN); diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c index a60c576c4a5..e644f31003f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c @@ -45,7 +45,7 @@ /* This module only supports pulse count on advanced timers. */ -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT /**************************************************************************** * Pre-processor Definitions @@ -68,13 +68,13 @@ # define PULSECOUNT_TIM1_CLKIN STM32_APB1_TIM1_CLKIN #endif -#if CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 1 +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH1OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH2OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH3OUT -#elif CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 # define PULSECOUNT_TIM1_CHCFG GPIO_TIM1_CH4OUT #else # error Unsupported TIM1 pulse count channel @@ -180,14 +180,14 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = stm32pulsecount_ioctl, }; -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecounttimer_s g_pulsecount1dev = { .ops = &g_pulsecountops, .timid = 1, .channel = { - .channel = CONFIG_STM32F0L0G0_TIM1_PULSECOUNT_CHANNEL, + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, .pincfg = PULSECOUNT_TIM1_CHCFG, }, .timtype = TIMTYPE_TIM1, @@ -958,7 +958,7 @@ static void stm32pulsecount_setapbclock( switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; @@ -1166,7 +1166,7 @@ static int stm32pulsecount_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; @@ -1255,7 +1255,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: lower = &g_pulsecount1dev; @@ -1274,4 +1274,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) return (struct pulsecount_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F0L0G0_TIMx_PULSECOUNT */ +#endif /* CONFIG_STM32_TIMx_PULSECOUNT */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/stm32f0l0g0/stm32_pwm.c index df066d05163..0710973de1b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.c @@ -64,10 +64,10 @@ * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) /**************************************************************************** * Pre-processor Definitions @@ -98,15 +98,15 @@ /* Advanced timer */ -#if defined (CONFIG_STM32F0L0G0_TIM1_PWM) +#if defined (CONFIG_STM32_TIM1_PWM) # define HAVE_IP_TIMERS_V2 1 #endif -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM8_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || \ + defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -114,8 +114,8 @@ /* CCMR2 */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) # define HAVE_CCMR2 #else # undef HAVE_CCMR2 @@ -237,159 +237,159 @@ static const struct pwm_ops_s g_pwmops = .ioctl = stm32pwm_ioctl, }; -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, .timid = 1, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM1_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, .npincfg = PWM_TIM1_CH1NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM1_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH2MODE, + .mode = CONFIG_STM32_TIM1_CH2MODE, .npincfg = PWM_TIM1_CH2NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM1_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH3MODE, + .mode = CONFIG_STM32_TIM1_CH3MODE, .npincfg = PWM_TIM1_CH3NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM1_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM1_CH4MODE, + .mode = CONFIG_STM32_TIM1_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F0L0G0_TIM1_MODE, + .mode = CONFIG_STM32_TIM1_MODE, .base = STM32_TIM1_BASE, .pclk = STM32_APB2_TIM1_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, .timid = 2, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM2_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH1MODE, + .mode = CONFIG_STM32_TIM2_CH1MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM2_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH2MODE, + .mode = CONFIG_STM32_TIM2_CH2MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM2_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH3MODE, + .mode = CONFIG_STM32_TIM2_CH3MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM2_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM2_CH4MODE, + .mode = CONFIG_STM32_TIM2_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F0L0G0_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .base = STM32_TIM2_BASE, .pclk = STM32_APB1_TIM2_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, .timid = 3, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM3_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH1MODE, + .mode = CONFIG_STM32_TIM3_CH1MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM3_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH2MODE, + .mode = CONFIG_STM32_TIM3_CH2MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, .pincfg = PWM_TIM3_CH3CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH3MODE, + .mode = CONFIG_STM32_TIM3_CH3MODE, .npincfg = 0, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, .pincfg = PWM_TIM3_CH4CFG, - .mode = CONFIG_STM32F0L0G0_TIM3_CH4MODE, + .mode = CONFIG_STM32_TIM3_CH4MODE, .npincfg = 0, }, #endif }, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F0L0G0_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .base = STM32_TIM3_BASE, .pclk = STM32_APB1_TIM3_CLKIN, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, .timid = 14, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM14_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM14_CH1MODE, + .mode = CONFIG_STM32_TIM14_CH1MODE, .npincfg = PWM_TIM14_CH1NCFG, }, #endif @@ -401,26 +401,26 @@ static struct stm32_pwmtimer_s g_pwm14dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, .timid = 15, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM15_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, .npincfg = PWM_TIM15_CH1NCFG, }, #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, .pincfg = PWM_TIM15_CH2CFG, - .mode = CONFIG_STM32F0L0G0_TIM15_CH2MODE, + .mode = CONFIG_STM32_TIM15_CH2MODE, .npincfg = 0, }, #endif @@ -432,18 +432,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, .timid = 16, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM16_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, .npincfg = PWM_TIM16_CH1NCFG, }, #endif @@ -455,18 +455,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, .timid = 17, .channels = { -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, .pincfg = PWM_TIM17_CH1CFG, - .mode = CONFIG_STM32F0L0G0_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, .npincfg = PWM_TIM17_CH1NCFG, }, #endif @@ -689,7 +689,7 @@ static void stm32pwm_dumpregs(struct stm32_pwmtimer_s *priv, stm32pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), stm32pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), stm32pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -939,9 +939,9 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, * and TIMTYPE_BASIC */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype != TIMTYPE_BASIC && priv->timtype != TIMTYPE_COUNTUP16 && priv->timtype != TIMTYPE_COUNTUP16_N) @@ -1001,7 +1001,7 @@ static int stm32pwm_timer(struct stm32_pwmtimer_s *priv, /* Set the advanced timer's repetition counter */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { /* If a non-zero repetition count has been selected, then set the @@ -1394,43 +1394,43 @@ static void stm32pwm_setapbclock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: regaddr = STM32_RCC_APB1ENR; en_bit = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: regaddr = STM32_RCC_APB2ENR; en_bit = RCC_APB2ENR_TIM17EN; @@ -1683,70 +1683,70 @@ static int stm32pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM14RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM15RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; @@ -1834,7 +1834,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: lower = &g_pwm1dev; @@ -1843,31 +1843,31 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: lower = &g_pwm2dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: lower = &g_pwm3dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: lower = &g_pwm4dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: lower = &g_pwm5dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: lower = &g_pwm8dev; @@ -1876,25 +1876,25 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: lower = &g_pwm14dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: lower = &g_pwm15dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: lower = &g_pwm16dev; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: lower = &g_pwm17dev; break; @@ -1908,4 +1908,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/stm32f0l0g0/stm32_pwm.h index 88683b9b662..fc5beb4482c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwm.h @@ -64,56 +64,56 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM * must also be defined to indicate that timer "n" is intended to be used for * pulsed output signal generation. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM14 -# undef CONFIG_STM32F0L0G0_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM15 -# undef CONFIG_STM32F0L0G0_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM16 -# undef CONFIG_STM32F0L0G0_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32F0L0G0_TIM17 -# undef CONFIG_STM32F0L0G0_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) * are not capable of generating output pulses */ -#undef CONFIG_STM32F0L0G0_TIM6_PWM -#undef CONFIG_STM32F0L0G0_TIM7_PWM +#undef CONFIG_STM32_TIM6_PWM +#undef CONFIG_STM32_TIM7_PWM /* Check if PWM support for any channel is enabled. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_PWM) || \ - defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) -#ifdef CONFIG_STM32F0L0G0_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # else # define PWM_TIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 @@ -122,13 +122,13 @@ #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # else # define PWM_TIM1_CH2CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 @@ -137,13 +137,13 @@ #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # else # define PWM_TIM1_CH3CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 @@ -152,8 +152,8 @@ #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM1_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # define PWM_TIM1_CH4CFG 0 @@ -165,8 +165,8 @@ #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # else # define PWM_TIM2_CH1CFG 0 @@ -175,8 +175,8 @@ #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # else # define PWM_TIM2_CH2CFG 0 @@ -185,8 +185,8 @@ #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # else # define PWM_TIM2_CH3CFG 0 @@ -195,8 +195,8 @@ #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # define PWM_TIM2_CH4CFG 0 @@ -208,8 +208,8 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # else # define PWM_TIM3_CH1CFG 0 @@ -218,8 +218,8 @@ #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # else # define PWM_TIM3_CH2CFG 0 @@ -228,8 +228,8 @@ #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL3 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # else # define PWM_TIM3_CH3CFG 0 @@ -238,8 +238,8 @@ #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_CHANNEL4 -# ifdef CONFIG_STM32F0L0G0_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # define PWM_TIM3_CH4CFG 0 @@ -251,13 +251,13 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F0L0G0_TIM14_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT # else # define PWM_TIM14_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM14_CH1NOUT +# ifdef CONFIG_STM32_TIM14_CH1NOUT # define PWM_TIM14_CH1NCFG GPIO_TIM14_CH1NOUT # else # define PWM_TIM14_CH1NCFG 0 @@ -268,13 +268,13 @@ #endif #define PWM_TIM14_NCHANNELS PWM_TIM14_CHANNEL1 -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # else # define PWM_TIM15_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM15_CH1NOUT +# ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT # else # define PWM_TIM15_CH1NCFG 0 @@ -283,8 +283,8 @@ #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_CHANNEL2 -# ifdef CONFIG_STM32F0L0G0_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else # define PWM_TIM15_CH2CFG 0 @@ -295,13 +295,13 @@ #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32F0L0G0_TIM16_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # else # define PWM_TIM16_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM16_CH1NOUT +# ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT # else # define PWM_TIM16_CH1NCFG 0 @@ -312,13 +312,13 @@ #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32F0L0G0_TIM17_CHANNEL1 -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # else # define PWM_TIM17_CH1CFG 0 # endif -# ifdef CONFIG_STM32F0L0G0_TIM17_CH1NOUT +# ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT # else # define PWM_TIM17_CH1NCFG 0 @@ -337,178 +337,170 @@ MAX(PWM_TIM16_NCHANNELS, \ PWM_TIM17_NCHANNELS)))))) -#else /* !CONFIG_STM32F0L0G0_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32F0L0G0_TIMx_CHANNEL - Specifies the timer output channel - * {1,..,4} - * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. - * In the case where there are multiple pin selections, the correct - * setting must be provided in the arch/board/board.h file. + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel + * {1,..,4} PWM_TIMx_CHn - One of the values defined in + * chip/stm32*_pinmap.h. In the case where there are multiple pin + * selections, the correct setting must be provided in the arch/board/board.h + * file. * - * NOTE: - * The STM32 timers are each capable of generating different signals on - * each of the four channels with different duty cycles. That capability - * is not supported by this driver: Only one output channel per timer. + * NOTE: The STM32 timers are each capable of generating different signals on + * each of the four channels with different duty cycles. That capability is + * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM1_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM1_CH1MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT -# define PWM_TIM1_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM1_CH2MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT -# define PWM_TIM1_CH2NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM1_CH3MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT -# define PWM_TIM1_CH3NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM1_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM1_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM1_CH4MODE CONFIG_STM32F0L0G0_TIM1_CHMODE -# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# define PWM_TIM1_CH1NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# define PWM_TIM1_CH2NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# define PWM_TIM1_CH3NCFG 0 +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif -# define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM2_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM2_CH1MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM2_CH2MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM2_CH3MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM2_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM2_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM2_CH4MODE CONFIG_STM32F0L0G0_TIM2_CHMODE -# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE +# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif -# define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM3_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM3_CH1MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM3_CH2MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 3 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL3 1 -# define CONFIG_STM32F0L0G0_TIM3_CH3MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32F0L0G0_TIM3_CHANNEL == 4 -# define CONFIG_STM32F0L0G0_TIM3_CHANNEL4 1 -# define CONFIG_STM32F0L0G0_TIM3_CH4MODE CONFIG_STM32F0L0G0_TIM3_CHMODE -# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE +# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif -# define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM14_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM14_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM14_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM14_CH1MODE CONFIG_STM32F0L0G0_TIM14_CHMODE -# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT -# define PWM_TIM14_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE +# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# define PWM_TIM14_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif -# define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM15_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM15_CH1MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT -# define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32F0L0G0_TIM15_CHANNEL == 2 -# define CONFIG_STM32F0L0G0_TIM15_CHANNEL2 1 -# define CONFIG_STM32F0L0G0_TIM15_CH2MODE CONFIG_STM32F0L0G0_TIM15_CHMODE -# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# define PWM_TIM15_CH1NCFG 0 +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE +# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif -# define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM16_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM16_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM16_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM16_CH1MODE CONFIG_STM32F0L0G0_TIM16_CHMODE -# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT -# define PWM_TIM16_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE +# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# define PWM_TIM16_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif -# define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM -# if !defined(CONFIG_STM32F0L0G0_TIM17_CHANNEL) -# error "CONFIG_STM32F0L0G0_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32F0L0G0_TIM17_CHANNEL == 1 -# define CONFIG_STM32F0L0G0_TIM17_CHANNEL1 1 -# define CONFIG_STM32F0L0G0_TIM17_CH1MODE CONFIG_STM32F0L0G0_TIM17_CHMODE -# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT -# define PWM_TIM17_CH1NCFG 0 +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE +# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# define PWM_TIM17_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32F0L0G0_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif -# define PWM_TIM17_NCHANNELS 1 #endif #define PWM_NCHANNELS 1 -#endif /* CONFIG_STM32F0L0G0_PWM_MULTICHAN */ +#endif /* Complementary outputs support */ -#if defined(CONFIG_STM32F0L0G0_TIM1_CH1NOUT) || defined(CONFIG_STM32F0L0G0_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F0L0G0_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -566,6 +558,6 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0l0g0/stm32_pwr.c index 76f6b07bf9c..70c8df356ab 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.c @@ -31,9 +31,9 @@ * according to the selected MCU family. */ -#if defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_STM32G0) # include "stm32g0_pwr.c" -#elif defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#elif defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) # include "stm32f0l0_pwr.c" #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/stm32f0l0g0/stm32_pwr.h index 21673d02c3e..1562b607328 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/stm32f0l0g0/stm32_pwr.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_pwr.h" -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /**************************************************************************** * Pre-processor Definitions @@ -172,9 +172,9 @@ bool stm32_pwr_getwuf(void); * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) || defined(CONFIG_STM32F0L0G0_STM32G0) +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE || CONFIG_STM32F0L0G0_STM32G0 */ +#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */ /**************************************************************************** * Name: stm32_pwr_setpvd @@ -193,7 +193,7 @@ void stm32_pwr_setvos(uint16_t vos); * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_ENERGYLITE) +#if defined(CONFIG_STM32_ENERGYLITE) void stm32_pwr_setpvd(uint16_t pls); /**************************************************************************** @@ -216,7 +216,7 @@ void stm32_pwr_enablepvd(void); void stm32_pwr_disablepvd(void); -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ +#endif /* CONFIG_STM32_ENERGYLITE */ #undef EXTERN #if defined(__cplusplus) @@ -224,5 +224,5 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ #endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/stm32f0l0g0/stm32_qencoder.c index 8f09d5596fb..65cc9945546 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ b/arch/arm/src/stm32f0l0g0/stm32_qencoder.c @@ -51,13 +51,13 @@ /* Timers *******************************************************************/ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS # undef HAVE_32BIT_TIMERS # undef HAVE_16BIT_TIMERS /* If TIM2 is enabled and is 32-bit, then we have 32-bit timers */ -# if defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_32BIT) +# if defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_32BIT) # define HAVE_32BIT_TIMERS 1 # endif @@ -65,9 +65,9 @@ * 16-bit timers */ -# if defined(CONFIG_STM32F0L0G0_TIM1_QE) || defined(CONFIG_STM32F0L0G0_TIM3_QE) || \ - defined(CONFIG_STM32F0L0G0_TIM4_QE) || \ - (defined(CONFIG_STM32F0L0G0_TIM2_QE) && defined(HAVE_TIM2_16BIT)) +# if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || \ + (defined(CONFIG_STM32_TIM2_QE) && defined(HAVE_TIM2_16BIT)) # define HAVE_16BIT_TIMERS 1 # endif @@ -92,65 +92,65 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F0L0G0_QENCODER_FILTER -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_1) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_2) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_4) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_5) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_6) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F0L0G0_QENCODER_SAMPLE_EVENT_8) -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif -# ifndef STM32F0L0G0_QENCODER_ICF +# ifndef STM32_QENCODER_ICF # warning "Invalid encoder filter combination, filter disabled" # endif #endif -#ifndef STM32F0L0G0_QENCODER_ICF -# define STM32F0L0G0_QENCODER_ICF GTIM_CCMR_ICF_NOFILT +#ifndef STM32_QENCODER_ICF +# define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT #endif -#define STM32F0L0G0_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) +#define STM32_GPIO_INPUT_FLOAT (GPIO_INPUT | GPIO_FLOAT) /* Debug ********************************************************************/ @@ -207,13 +207,13 @@ struct stm32_lowerhalf_s bool inuse; /* True: The lower-half driver is in-use */ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN uint32_t index_pin; /* Index pin GPIO */ bool index_use; /* True: Index pin is configured */ int32_t index_offset; /* Index pin offset */ #endif -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS volatile int32_t position; /* The current position offset */ #endif spinlock_t lock; /* Spinlock */ @@ -243,11 +243,11 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN static int stm32_qe_index_irq(int irq, void *context, void *arg); #endif -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS static int stm32_interrupt(int irq, void *context, void *arg); #endif @@ -281,7 +281,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -290,7 +290,7 @@ static const struct stm32_qeconfig_s g_tim1config = .width = TIM1_BITWIDTH, #endif .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F0L0G0_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -305,7 +305,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -314,7 +314,7 @@ static const struct stm32_qeconfig_s g_tim2config = .width = TIM2_BITWIDTH, #endif .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F0L0G0_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -329,7 +329,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -338,7 +338,7 @@ static const struct stm32_qeconfig_s g_tim3config = .width = TIM3_BITWIDTH, #endif .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F0L0G0_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -353,7 +353,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -362,7 +362,7 @@ static const struct stm32_qeconfig_s g_tim4config = .width = TIM4_BITWIDTH, #endif .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F0L0G0_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -511,7 +511,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) +#if defined(CONFIG_STM32_TIM1_QE) if (priv->config->timid == 1) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -542,19 +542,19 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif @@ -571,7 +571,7 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN static int stm32_qe_index_irq(int irq, void *context, void *arg) { struct stm32_lowerhalf_s *priv; @@ -601,7 +601,7 @@ static int stm32_qe_index_irq(int irq, void *context, void *arg) * ****************************************************************************/ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS static int stm32_interrupt(int irq, void *context, void *arg) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)arg; @@ -656,7 +656,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) uint32_t ccmr1; uint16_t ccer; uint16_t cr1; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS uint16_t regval; int ret; #endif @@ -699,7 +699,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F0L0G0_TIM1_QE) +#if defined(CONFIG_STM32_TIM1_QE) if (priv->config->timid == 1) { /* Clear the Repetition Counter value */ @@ -741,7 +741,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC1S_MASK | GTIM_CCMR1_IC1F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC1S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC1F_SHIFT; /* Select the Polarity=rising and set the CC1E Bit */ @@ -777,7 +777,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) ccmr1 &= ~(GTIM_CCMR1_CC2S_MASK | GTIM_CCMR1_IC2F_MASK); ccmr1 |= GTIM_CCMR_CCS_CCIN1 << GTIM_CCMR1_CC2S_SHIFT; - ccmr1 |= STM32F0L0G0_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; + ccmr1 |= STM32_QENCODER_ICF << GTIM_CCMR1_IC2F_SHIFT; /* Select the Polarity=rising and set the CC2E Bit */ @@ -806,7 +806,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) /* There is no need for interrupts with 32-bit timers */ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS #ifdef HAVE_MIXEDWIDTH_TIMERS if (priv->config->width != 32) #endif @@ -839,7 +839,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) /* There is no need for interrupts with 32-bit timers */ -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS #ifdef HAVE_MIXEDWIDTH_TIMERS if (priv->config->width != 32) #endif @@ -857,7 +857,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) } #endif -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN priv->index_offset = 0; #endif @@ -913,25 +913,25 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F0L0G0_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; @@ -961,14 +961,14 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) /* Put the TI1 GPIO pin back to its default state */ pincfg = priv->config->ti1cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32_configgpio(pincfg); /* Put the TI2 GPIO pin back to its default state */ pincfg = priv->config->ti2cfg & (GPIO_PORT_MASK | GPIO_PIN_MASK); - pincfg |= STM32F0L0G0_GPIO_INPUT_FLOAT; + pincfg |= STM32_GPIO_INPUT_FLOAT; stm32_configgpio(pincfg); return OK; @@ -985,7 +985,7 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS irqstate_t flags; int32_t position; int32_t verify; @@ -1027,7 +1027,7 @@ static int stm32_position(struct qe_lowerhalf_s *lower, int32_t *pos) static int stm32_reset(struct qe_lowerhalf_s *lower) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; -#ifndef CONFIG_STM32F0L0G0_QENCODER_DISABLE_EXTEND16BTIMERS +#ifndef CONFIG_STM32_QENCODER_DISABLE_EXTEND16BTIMERS irqstate_t flags; sninfo("Resetting position to zero\n"); @@ -1094,7 +1094,7 @@ static int stm32_setposmax(struct qe_lowerhalf_s *lower, uint32_t pos) static int stm32_setindex(struct qe_lowerhalf_s *lower, uint32_t pos) { -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = OK; @@ -1201,7 +1201,7 @@ int stm32_qeinitialize(const char *devpath, int tim) return OK; } -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN /**************************************************************************** * Name: stm32_qe_index_init * diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h index b6f1c4c9d9c..c46fbdf9135 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h @@ -38,23 +38,23 @@ ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32F0L0G0_TIMn is - * defined then the CONFIG_STM32F0L0G0_TIMn_QE must also be defined to + * as a quadrature encoder input device. If CONFIG_STM32_TIMn is + * defined then the CONFIG_STM32_TIMn_QE must also be defined to * indicate that timer "n" is intended to be used for as a quadrature * encoder. */ -#ifndef CONFIG_STM32F0L0G0_TIM1 -# undef CONFIG_STM32F0L0G0_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM2 -# undef CONFIG_STM32F0L0G0_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM3 -# undef CONFIG_STM32F0L0G0_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F0L0G0_TIM4 -# undef CONFIG_STM32F0L0G0_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif /* Only timers 1-4 can be used as a quadrature encoder (timers with @@ -63,12 +63,12 @@ * capability. */ -#undef CONFIG_STM32F0L0G0_TIM6_QE -#undef CONFIG_STM32F0L0G0_TIM7_QE -#undef CONFIG_STM32F0L0G0_TIM14_QE -#undef CONFIG_STM32F0L0G0_TIM15_QE -#undef CONFIG_STM32F0L0G0_TIM16_QE -#undef CONFIG_STM32F0L0G0_TIM17_QE +#undef CONFIG_STM32_TIM6_QE +#undef CONFIG_STM32_TIM7_QE +#undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE /**************************************************************************** * Public Function Prototypes @@ -93,7 +93,7 @@ int stm32_qeinitialize(const char *devpath, int tim); -#ifdef CONFIG_STM32F0L0G0_QENCODER_INDEX_PIN +#ifdef CONFIG_STM32_QENCODER_INDEX_PIN /**************************************************************************** * Name: stm32_qe_index_init * diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32f0l0g0/stm32_rcc.c index 7e89c4b1e20..b227f714756 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rcc.c @@ -42,13 +42,13 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG # ifndef STM32_USE_CLK48 # error RNG requires CLK48 enabled # endif #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # ifndef STM32_USE_CLK48 # error USB requires CLK48 enabled # endif @@ -103,7 +103,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32F0L0G0_RTC) && defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) static inline void rcc_resetbkp(void) { uint32_t regval; @@ -144,7 +144,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ stm32_board_clockconfig(); @@ -198,7 +198,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -213,7 +213,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ stm32_board_clockconfig(); diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/stm32f0l0g0/stm32_rng.c index 49b43f2796e..2ccebb1060b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/stm32f0l0g0/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F0L0G0_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/stm32f0l0g0/stm32_serial.c index a0d8178b52f..5edb01036ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial.c @@ -33,9 +33,9 @@ * - STM32 UART IP version 2 - G0 */ -#if defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V1) +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) # include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32F0L0G0_HAVE_IP_USART_V2) +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) # include "stm32_serial_v2.c" #else # error "Unsupported STM32 M0 serial" diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 55f290837bf..444e4888721 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -84,14 +84,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA1 -# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32F0L0G0_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32F0 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_USART4_RXDMA) || defined(CONFIG_USART5_RXDMA) -# ifndef CONFIG_STM32F0L0G0_DMA2 -# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32F0L0G0_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32F0 USART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -160,8 +160,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -175,7 +175,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -348,7 +348,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -356,7 +356,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -364,7 +364,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -372,7 +372,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; # ifdef CONFIG_USART4_RXDMA @@ -380,7 +380,7 @@ static char g_usart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 static char g_usart5rxbuffer[CONFIG_USART5_RXBUFSIZE]; static char g_usart5txbuffer[CONFIG_USART5_TXBUFSIZE]; # ifdef CONFIG_USART5_RXDMA @@ -390,7 +390,7 @@ static char g_usart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static struct stm32_serial_s g_usart1priv = { .dev = @@ -452,7 +452,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static struct stm32_serial_s g_usart2priv = { .dev = @@ -514,7 +514,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static struct stm32_serial_s g_usart3priv = { .dev = @@ -576,7 +576,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static struct stm32_serial_s g_usart4priv = { .dev = @@ -642,7 +642,7 @@ static struct stm32_serial_s g_usart4priv = /* This describes the state of the STM32 USART5 port. */ -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 static struct stm32_serial_s g_usart5priv = { .dev = @@ -710,19 +710,19 @@ static struct stm32_serial_s g_usart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 [3] = &g_usart4priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 [4] = &g_usart5priv, #endif }; @@ -1005,7 +1005,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1047,31 +1047,31 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 case STM32_USART5_BASE: rcc_en = RCC_APB1ENR_USART5EN; regaddr = STM32_RCC_APB1ENR; @@ -1132,7 +1132,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1464,8 +1464,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1609,7 +1609,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE #warning please review the potential use of ALTERNATE_FUNCTION_OPENDRAIN case TIOCSSINGLEWIRE: { @@ -1747,8 +1747,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1967,7 +1967,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2218,7 +2218,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2471,7 +2471,7 @@ void arm_serialinit(void) #if CONSOLE_USART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console USART to ttyS0 and exclude * it from initializing it further down */ @@ -2500,7 +2500,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index d286bb036d5..0d9d208c67f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -68,8 +68,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -83,7 +83,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -93,9 +93,9 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif @@ -216,29 +216,29 @@ static const struct uart_ops_s g_uart_ops = /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static char g_usart4rxbuffer[CONFIG_USART4_RXBUFSIZE]; static char g_usart4txbuffer[CONFIG_USART4_TXBUFSIZE]; #endif /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -293,7 +293,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -348,7 +348,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -403,7 +403,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 USART4 port. */ -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 static struct up_dev_s g_usart4priv = { .dev = @@ -460,16 +460,16 @@ static struct up_dev_s g_usart4priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 [3] = &g_usart4priv #endif }; @@ -738,7 +738,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -782,25 +782,25 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 case STM32_USART4_BASE: rcc_en = RCC_APB1ENR_USART4EN; regaddr = STM32_RCC_APB1ENR; @@ -865,7 +865,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1093,8 +1093,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F0L0G0_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1207,14 +1207,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32F0L0G0_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -1237,7 +1237,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F0L0G0_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1390,8 +1390,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F0L0G0_USART_BREAKS -# ifdef CONFIG_STM32F0L0G0_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -1590,7 +1590,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F0L0G0_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1966,7 +1966,7 @@ void arm_serialinit(void) #if CONSOLE_USART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_USART - 1]->dev); -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1990,7 +1990,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F0L0G0_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/stm32f0l0g0/stm32_spi.c index c23914442ca..ae149747b08 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.c @@ -80,7 +80,7 @@ #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F0L0G0_SPI_INTERRUPTS) && defined(CONFIG_STM32F0L0G0_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -129,10 +129,10 @@ /* SPI clocks */ -#if defined(CONFIG_STM32F0L0G0_STM32F0) || defined(CONFIG_STM32F0L0G0_STM32L0) +#if defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) # define SPI1_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -#elif defined(CONFIG_STM32F0L0G0_STM32G0) +#elif defined(CONFIG_STM32_STM32G0) # define SPI1_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI2_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # define SPI3_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY @@ -157,10 +157,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -211,7 +211,7 @@ static void spi_modifycr(uint32_t addr, struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -247,7 +247,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords); -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange_nodma(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords); @@ -278,7 +278,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -318,10 +318,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F0L0G0_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -333,11 +333,11 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI1_COMMTYPE, + .config = CONFIG_STM32_SPI1_COMMTYPE, }; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -377,10 +377,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F0L0G0_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -390,11 +390,11 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI2_COMMTYPE, + .config = CONFIG_STM32_SPI2_COMMTYPE, }; #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -434,10 +434,10 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = SPI1_PCLK_FREQUENCY, -#ifdef CONFIG_STM32F0L0G0_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F0L0G0_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -447,7 +447,7 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif - .config = CONFIG_STM32F0L0G0_SPI3_COMMTYPE, + .config = CONFIG_STM32_SPI3_COMMTYPE, }; #endif @@ -754,7 +754,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -787,7 +787,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -820,7 +820,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -835,7 +835,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -850,7 +850,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -870,7 +870,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -890,7 +890,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -941,7 +941,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -992,7 +992,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1008,7 +1008,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1495,7 +1495,7 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F0L0G0_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1604,7 +1604,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1622,7 +1622,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F0L0G0_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1684,7 +1684,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32F0L0G0_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1705,7 +1705,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1969,7 +1969,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2032,7 +2032,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2056,7 +2056,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2080,7 +2080,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2110,7 +2110,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) goto errout; } -#ifdef CONFIG_STM32F0L0G0_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* SPI DMA supported only for full-duplex mode */ if (priv->rxch && priv->txch && priv->config != FULL_DUPLEX) @@ -2131,4 +2131,4 @@ errout: return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F0L0G0_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h index e6ea4bdc555..dd99c76575a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ b/arch/arm/src/stm32f0l0g0/stm32_spi.h @@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,17 +146,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/stm32f0l0g0/stm32_tim.c index f3c76fa97e2..48a549aa415 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim.c @@ -68,96 +68,96 @@ * include: * * - To generate modulated outputs for such things as motor control. If - * CONFIG_STM32F0L0G0_TIMn is defined then the CONFIG_STM32F0L0G0_TIMn_PWM + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM * may also be defined to indicate that the timer is intended to be used * for pulsed output modulation. * - * - To control periodic ADC input sampling. If CONFIG_STM32F0L0G0_TIMn is - * defined then CONFIG_STM32F0L0G0_TIMn_ADC may also be defined to indicate + * - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is + * defined then CONFIG_STM32_TIMn_ADC may also be defined to indicate * that timer "n" is intended to be used for that purpose. * - * - To control periodic DAC outputs. If CONFIG_STM32F0L0G0_TIMn is defined - * then CONFIG_STM32F0L0G0_TIMn_DAC may also be defined to indicate that + * - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined + * then CONFIG_STM32_TIMn_DAC may also be defined to indicate that * timer "n" is intended to be used for that purpose. * - * - To use a Quadrature Encoder. If CONFIG_STM32F0L0G0_TIMn is defined then - * CONFIG_STM32F0L0G0_TIMn_QE may also be defined to indicate that timer + * - To use a Quadrature Encoder. If CONFIG_STM32_TIMn is defined then + * CONFIG_STM32_TIMn_QE may also be defined to indicate that timer * "n" is intended to be used for that purpose. * * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) || defined(CONFIG_STM32F0L0G0_TIM1_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM1_DAC) || defined(CONFIG_STM32F0L0G0_TIM1_QE) -# undef CONFIG_STM32F0L0G0_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) || defined(CONFIG_STM32F0L0G0_TIM2_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM2_DAC) || defined(CONFIG_STM32F0L0G0_TIM2_QE) -# undef CONFIG_STM32F0L0G0_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined(CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) || defined(CONFIG_STM32F0L0G0_TIM3_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM3_DAC) || defined(CONFIG_STM32F0L0G0_TIM3_QE) -# undef CONFIG_STM32F0L0G0_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F0L0G0_TIM4_PWM) || defined(CONFIG_STM32F0L0G0_TIM4_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM4_DAC) || defined(CONFIG_STM32F0L0G0_TIM4_QE) -# undef CONFIG_STM32F0L0G0_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined(CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F0L0G0_TIM5_PWM) || defined(CONFIG_STM32F0L0G0_TIM5_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM5_DAC) || defined(CONFIG_STM32F0L0G0_TIM5_QE) -# undef CONFIG_STM32F0L0G0_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F0L0G0_TIM6_PWM) || defined(CONFIG_STM32F0L0G0_TIM6_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM6_DAC) || defined(CONFIG_STM32F0L0G0_TIM6_QE) -# undef CONFIG_STM32F0L0G0_TIM6 +#if defined(CONFIG_STM32_TIM6_PWM) || defined(CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif -#if defined(CONFIG_STM32F0L0G0_TIM7_PWM) || defined(CONFIG_STM32F0L0G0_TIM7_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM7_DAC) || defined(CONFIG_STM32F0L0G0_TIM7_QE) -# undef CONFIG_STM32F0L0G0_TIM7 +#if defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM7_ADC) || \ + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F0L0G0_TIM8_PWM) || defined(CONFIG_STM32F0L0G0_TIM8_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM8_DAC) || defined(CONFIG_STM32F0L0G0_TIM8_QE) -# undef CONFIG_STM32F0L0G0_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined(CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F0L0G0_TIM12_PWM) || defined(CONFIG_STM32F0L0G0_TIM12_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM12_DAC) || defined(CONFIG_STM32F0L0G0_TIM12_QE) -# undef CONFIG_STM32F0L0G0_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined(CONFIG_STM32_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F0L0G0_TIM13_PWM) || defined(CONFIG_STM32F0L0G0_TIM13_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM13_DAC) || defined(CONFIG_STM32F0L0G0_TIM13_QE) -# undef CONFIG_STM32F0L0G0_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) || defined(CONFIG_STM32F0L0G0_TIM14_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM14_DAC) || defined(CONFIG_STM32F0L0G0_TIM14_QE) -# undef CONFIG_STM32F0L0G0_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined(CONFIG_STM32_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) || defined(CONFIG_STM32F0L0G0_TIM15_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM15_DAC) || defined(CONFIG_STM32F0L0G0_TIM15_QE) -# undef CONFIG_STM32F0L0G0_TIM15 +#if defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM15_ADC) || \ + defined(CONFIG_STM32_TIM15_DAC) || defined(CONFIG_STM32_TIM15_QE) +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) || defined(CONFIG_STM32F0L0G0_TIM16_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM16_DAC) || defined(CONFIG_STM32F0L0G0_TIM16_QE) -# undef CONFIG_STM32F0L0G0_TIM16 +#if defined(CONFIG_STM32_TIM16_PWM) || defined(CONFIG_STM32_TIM16_ADC) || \ + defined(CONFIG_STM32_TIM16_DAC) || defined(CONFIG_STM32_TIM16_QE) +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) || defined(CONFIG_STM32F0L0G0_TIM17_ADC) || \ - defined(CONFIG_STM32F0L0G0_TIM17_DAC) || defined(CONFIG_STM32F0L0G0_TIM17_QE) -# undef CONFIG_STM32F0L0G0_TIM17 +#if defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_TIM17_ADC) || \ + defined(CONFIG_STM32_TIM17_DAC) || defined(CONFIG_STM32_TIM17_QE) +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32F0L0G0_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) || \ defined(GPIO_TIM1_CH5OUT) || defined(GPIO_TIM1_CH6OUT) @@ -165,35 +165,35 @@ # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) || defined(GPIO_TIM3_CH2OUT) || \ defined(GPIO_TIM3_CH3OUT) || defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) || defined(GPIO_TIM4_CH2OUT) || \ defined(GPIO_TIM4_CH3OUT) || defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) || defined(GPIO_TIM5_CH2OUT) || \ defined(GPIO_TIM5_CH3OUT) || defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) || defined(GPIO_TIM8_CH2OUT) || \ defined(GPIO_TIM8_CH3OUT) || defined(GPIO_TIM8_CH4OUT) || \ defined(GPIO_TIM8_CH5OUT) || defined(GPIO_TIM8_CH6OUT) @@ -201,37 +201,37 @@ # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) || defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) || defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32F0L0G0_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -241,13 +241,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -324,7 +324,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .ackint = &stm32_tim_ackint }; -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -332,7 +332,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -341,7 +341,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -350,7 +350,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -359,7 +359,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -368,7 +368,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -377,7 +377,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -386,7 +386,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -395,7 +395,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -404,7 +404,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -413,7 +413,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -422,7 +422,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -431,7 +431,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -440,7 +440,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -582,47 +582,47 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB2_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -680,47 +680,47 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB2_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -789,52 +789,52 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1_BRK; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -960,16 +960,16 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_putreg16(dev, STM32_GTIM_CR1_OFFSET, val); /* Advanced registers require Main Output Enable */ -#if defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM8) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM8) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE -# if defined(CONFIG_STM32F0L0G0_TIM8) +# if defined(CONFIG_STM32_TIM8) || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE # endif ) { stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); } -#endif /* CONFIG_STM32F0L0G0_TIM1 || CONFIG_STM32F0L0G0_TIM8 */ +#endif /* CONFIG_STM32_TIM1 || CONFIG_STM32_TIM8 */ return OK; } @@ -1065,7 +1065,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1099,7 +1099,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1159,7 +1159,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1174,7 +1174,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1189,7 +1189,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1209,7 +1209,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1224,7 +1224,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1308,85 +1308,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1418,72 +1418,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1499,4 +1499,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F0L0G0_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c index 25e82579604..dbb558fa81b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c @@ -61,13 +61,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F0L0G0_TIM1) || defined(CONFIG_STM32F0L0G0_TIM2) || \ - defined(CONFIG_STM32F0L0G0_TIM3) || defined(CONFIG_STM32F0L0G0_TIM4) || \ - defined(CONFIG_STM32F0L0G0_TIM5) || defined(CONFIG_STM32F0L0G0_TIM6) || \ - defined(CONFIG_STM32F0L0G0_TIM7) || defined(CONFIG_STM32F0L0G0_TIM8) || \ - defined(CONFIG_STM32F0L0G0_TIM12) || defined(CONFIG_STM32F0L0G0_TIM13) || \ - defined(CONFIG_STM32F0L0G0_TIM14) || defined(CONFIG_STM32F0L0G0_TIM15) || \ - defined(CONFIG_STM32F0L0G0_TIM16) || defined(CONFIG_STM32F0L0G0_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -143,7 +143,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -247,7 +247,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -559,72 +559,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c index 5a0737c4144..9a92038c401 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/stm32f0l0g0/stm32_timerisr.c @@ -47,9 +47,9 @@ * (when CLKSOURCE = 0). ..." */ -#if defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK) +#if defined(CONFIG_STM32_SYSTICK_CORECLK) # define SYSTICK_CLOCK STM32_SYSCLK_FREQUENCY /* Core clock */ -#elif defined(CONFIG_STM32F0L0G0_SYSTICK_CORECLK_DIV16) +#elif defined(CONFIG_STM32_SYSTICK_CORECLK_DIV16) # define SYSTICK_CLOCK (STM32_SYSCLK_FREQUENCY / 16) /* Core clock divided by 16 */ #endif @@ -137,7 +137,7 @@ void up_timer_initialize(void) * a divide-by-16 of the core clock (when CLKSOURCE = 0). ..." */ -#ifdef CONFIG_STM32F0L0G0_SYSTICK_CORECLK +#ifdef CONFIG_STM32_SYSTICK_CORECLK putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/stm32f0l0g0/stm32_uart.h index 92e2e7ceb77..9ebcefc8fc5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/stm32f0l0g0/stm32_uart.h @@ -41,29 +41,29 @@ * device. */ -#if STM32_NUSART < 8 || !defined(CONFIG_STM32F0L0G0_HAVE_USART8) -# undef CONFIG_STM32F0L0G0_USART8 +#if STM32_NUSART < 8 || !defined(CONFIG_STM32_HAVE_USART8) +# undef CONFIG_STM32_USART8 #endif -#if STM32_NUSART < 7 || !defined(CONFIG_STM32F0L0G0_HAVE_USART7) -# undef CONFIG_STM32F0L0G0_USART7 +#if STM32_NUSART < 7 || !defined(CONFIG_STM32_HAVE_USART7) +# undef CONFIG_STM32_USART7 #endif -#if STM32_NUSART < 6 || !defined(CONFIG_STM32F0L0G0_HAVE_USART6) -# undef CONFIG_STM32F0L0G0_USART6 +#if STM32_NUSART < 6 || !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 #endif -#if STM32_NUSART < 5 || !defined(CONFIG_STM32F0L0G0_HAVE_USART5) -# undef CONFIG_STM32F0L0G0_USART5 +#if STM32_NUSART < 5 || !defined(CONFIG_STM32_HAVE_USART5) +# undef CONFIG_STM32_USART5 #endif -#if STM32_NUSART < 4 || !defined(CONFIG_STM32F0L0G0_HAVE_USART4) -# undef CONFIG_STM32F0L0G0_USART4 +#if STM32_NUSART < 4 || !defined(CONFIG_STM32_HAVE_USART4) +# undef CONFIG_STM32_USART4 #endif -#if STM32_NUSART < 3 || !defined(CONFIG_STM32F0L0G0_HAVE_USART3) -# undef CONFIG_STM32F0L0G0_USART3 +#if STM32_NUSART < 3 || !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32F0L0G0_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32F0L0G0_USART1 +# undef CONFIG_STM32_USART1 #endif /* USART 3-8 are multiplexed to the same interrupt. Current interrupt @@ -72,128 +72,128 @@ * issue in the future. */ -#if defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART4 -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART5 -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART6 -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART7 -# undef CONFIG_STM32F0L0G0_USART8 -#elif defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART8 +#if defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART4 +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART5 +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART6 +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART7 +# undef CONFIG_STM32_USART8 +#elif defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART8 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F0L0G0_USART1) || defined(CONFIG_STM32F0L0G0_USART2) || \ - defined(CONFIG_STM32F0L0G0_USART3) || defined(CONFIG_STM32F0L0G0_USART4) || \ - defined(CONFIG_STM32F0L0G0_USART5) || defined(CONFIG_STM32F0L0G0_USART6) || \ - defined(CONFIG_STM32F0L0G0_USART7) || defined(CONFIG_STM32F0L0G0_USART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_USART4) || \ + defined(CONFIG_STM32_USART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_USART7) || defined(CONFIG_STM32_USART8) # define HAVE_USART 1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32F0L0G0_USART1) -# undef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART2) -# undef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART3) -# undef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART4) -# undef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER +#if !defined(CONFIG_STM32_USART4) +# undef CONFIG_STM32_USART4_SERIALDRIVER +# undef CONFIG_STM32_USART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART5) -# undef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER +#if !defined(CONFIG_STM32_USART5) +# undef CONFIG_STM32_USART5_SERIALDRIVER +# undef CONFIG_STM32_USART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART6) -# undef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART7) -# undef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER +#if !defined(CONFIG_STM32_USART7) +# undef CONFIG_STM32_USART7_SERIALDRIVER +# undef CONFIG_STM32_USART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32F0L0G0_USART8) -# undef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER +#if !defined(CONFIG_STM32_USART8) +# undef CONFIG_STM32_USART8_SERIALDRIVER +# undef CONFIG_STM32_USART8_1WIREDRIVER #endif /* Check 1-Wire and U(S)ART conflicts */ -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART1_1WIREDRIVER and CONFIG_STM32F0L0G0_USART1_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART1_1WIREDRIVER +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) && defined(CONFIG_STM32_USART1_SERIALDRIVER) +# error Both CONFIG_STM32_USART1_1WIREDRIVER and CONFIG_STM32_USART1_SERIALDRIVER defined +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART2_1WIREDRIVER and CONFIG_STM32F0L0G0_USART2_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART2_1WIREDRIVER +#if defined(CONFIG_STM32_USART2_1WIREDRIVER) && defined(CONFIG_STM32_USART2_SERIALDRIVER) +# error Both CONFIG_STM32_USART2_1WIREDRIVER and CONFIG_STM32_USART2_SERIALDRIVER defined +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART3_1WIREDRIVER and CONFIG_STM32F0L0G0_USART3_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART3_1WIREDRIVER +#if defined(CONFIG_STM32_USART3_1WIREDRIVER) && defined(CONFIG_STM32_USART3_SERIALDRIVER) +# error Both CONFIG_STM32_USART3_1WIREDRIVER and CONFIG_STM32_USART3_SERIALDRIVER defined +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART4_1WIREDRIVER and CONFIG_STM32F0L0G0_USART4_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART4_1WIREDRIVER +#if defined(CONFIG_STM32_USART4_1WIREDRIVER) && defined(CONFIG_STM32_USART4_SERIALDRIVER) +# error Both CONFIG_STM32_USART4_1WIREDRIVER and CONFIG_STM32_USART4_SERIALDRIVER defined +# undef CONFIG_STM32_USART4_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART5_1WIREDRIVER and CONFIG_STM32F0L0G0_USART5_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART5_1WIREDRIVER +#if defined(CONFIG_STM32_USART5_1WIREDRIVER) && defined(CONFIG_STM32_USART5_SERIALDRIVER) +# error Both CONFIG_STM32_USART5_1WIREDRIVER and CONFIG_STM32_USART5_SERIALDRIVER defined +# undef CONFIG_STM32_USART5_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART6_1WIREDRIVER and CONFIG_STM32F0L0G0_USART6_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART6_1WIREDRIVER +#if defined(CONFIG_STM32_USART6_1WIREDRIVER) && defined(CONFIG_STM32_USART6_SERIALDRIVER) +# error Both CONFIG_STM32_USART6_1WIREDRIVER and CONFIG_STM32_USART6_SERIALDRIVER defined +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART7_1WIREDRIVER and CONFIG_STM32F0L0G0_USART7_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART7_1WIREDRIVER +#if defined(CONFIG_STM32_USART7_1WIREDRIVER) && defined(CONFIG_STM32_USART7_SERIALDRIVER) +# error Both CONFIG_STM32_USART7_1WIREDRIVER and CONFIG_STM32_USART7_SERIALDRIVER defined +# undef CONFIG_STM32_USART7_1WIREDRIVER #endif -#if defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) -# error Both CONFIG_STM32F0L0G0_USART8_1WIREDRIVER and CONFIG_STM32F0L0G0_USART8_SERIALDRIVER defined -# undef CONFIG_STM32F0L0G0_USART8_1WIREDRIVER +#if defined(CONFIG_STM32_USART8_1WIREDRIVER) && defined(CONFIG_STM32_USART8_SERIALDRIVER) +# error Both CONFIG_STM32_USART8_1WIREDRIVER and CONFIG_STM32_USART8_SERIALDRIVER defined +# undef CONFIG_STM32_USART8_1WIREDRIVER #endif /* Is the serial driver enabled? */ -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) || defined(CONFIG_STM32_USART2_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART3_SERIALDRIVER) || defined(CONFIG_STM32_USART4_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART5_SERIALDRIVER) || defined(CONFIG_STM32_USART6_SERIALDRIVER) || \ + defined(CONFIG_STM32_USART7_SERIALDRIVER) || defined(CONFIG_STM32_USART8_SERIALDRIVER) # define HAVE_SERIALDRIVER 1 #endif /* Is the 1-Wire driver? */ -#if defined(CONFIG_STM32F0L0G0_USART1_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART2_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART3_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART4_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART5_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART6_1WIREDRIVER) || \ - defined(CONFIG_STM32F0L0G0_USART7_1WIREDRIVER) || defined(CONFIG_STM32F0L0G0_USART8_1WIREDRIVER) +#if defined(CONFIG_STM32_USART1_1WIREDRIVER) || defined(CONFIG_STM32_USART2_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART3_1WIREDRIVER) || defined(CONFIG_STM32_USART4_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART5_1WIREDRIVER) || defined(CONFIG_STM32_USART6_1WIREDRIVER) || \ + defined(CONFIG_STM32_USART7_1WIREDRIVER) || defined(CONFIG_STM32_USART8_1WIREDRIVER) # define HAVE_1WIREDRIVER 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -203,7 +203,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -213,7 +213,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART4_SERIAL_CONSOLE @@ -223,7 +223,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) +#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -233,7 +233,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) +#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -243,7 +243,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -253,7 +253,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) +#elif defined(CONFIG_USART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART7_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -264,7 +264,7 @@ # undef CONFIG_USART8_SERIAL_CONSOLE # define CONSOLE_USART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) +#elif defined(CONFIG_USART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART8_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -304,35 +304,35 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F0L0G0_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART4_SERIALDRIVER +#ifndef CONFIG_STM32_USART4_SERIALDRIVER # undef CONFIG_USART4_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART5_SERIALDRIVER +#ifndef CONFIG_STM32_USART5_SERIALDRIVER # undef CONFIG_USART5_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART6_SERIALDRIVER +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART7_SERIALDRIVER +#ifndef CONFIG_STM32_USART7_SERIALDRIVER # undef CONFIG_USART7_RXDMA #endif -#ifndef CONFIG_STM32F0L0G0_USART8_SERIALDRIVER +#ifndef CONFIG_STM32_USART8_SERIALDRIVER # undef CONFIG_USART8_RXDMA #endif @@ -370,21 +370,21 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32F0L0G0_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) +#elif defined(CONFIG_STM32_USART4_SERIALDRIVER) && !defined(CONFIG_USART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) +#elif defined(CONFIG_STM32_USART5_SERIALDRIVER) && !defined(CONFIG_USART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) +#elif defined(CONFIG_STM32_USART7_SERIALDRIVER) && !defined(CONFIG_USART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32F0L0G0_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) +#elif defined(CONFIG_STM32_USART8_SERIALDRIVER) && !defined(CONFIG_USART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c index 9cfd7df85bd..d98ef7274af 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/stm32f0l0g0/stm32_usbdev.c @@ -55,7 +55,7 @@ #include "stm32_gpio.h" #include "stm32_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32F0L0G0_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) /**************************************************************************** * Pre-processor Definitions @@ -76,7 +76,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +# undef CONFIG_STM32_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -350,7 +350,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_dumpep(int epno); @@ -598,7 +598,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -656,7 +656,7 @@ static uint16_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -673,7 +673,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -3885,4 +3885,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32F0L0G0_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/stm32f0l0g0/stm32_wdg.h index 1d688da6b38..96ce766df55 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ b/arch/arm/src/stm32f0l0g0/stm32_wdg.h @@ -69,7 +69,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -90,7 +90,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c index b483d8637d3..ec620d49538 100644 --- a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c @@ -114,31 +114,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -165,67 +165,67 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR_FDCANEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_APB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; @@ -252,55 +252,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -364,7 +364,7 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#ifdef CONFIG_STM32F0L0G0_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Configure FDCAN1 clock source */ regval = getreg32(STM32_RCC_CCIPR1); diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c index ff387fbe10a..018b81897df 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c @@ -44,7 +44,7 @@ /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CFGR3_CLK48_HSI48 # define STM32_USE_HSI48 # endif @@ -107,25 +107,25 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; @@ -152,121 +152,121 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM4 +#ifdef CONFIG_STM32_TIM4 /* Timer 4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* Timer 14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_CEC +#ifdef CONFIG_STM32_CEC /* CEC interface clock enable */ regval |= RCC_APB1ENR_CECEN; @@ -293,67 +293,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGCOMPEN; #endif -#ifdef CONFIG_STM32F0L0G0_USART6 +#ifdef CONFIG_STM32_USART6 /* USART 6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART7 +#ifdef CONFIG_STM32_USART7 /* USART 7 clock enable */ regval |= RCC_APB2ENR_USART7EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART8 +#ifdef CONFIG_STM32_USART8 /* USART 8 clock enable */ regval |= RCC_APB2ENR_USART8EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Timer 1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* Timer 15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* Timer 16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* Timer 17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; @@ -379,7 +379,7 @@ static inline void rcc_enableapb2(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c index ab65b569e96..6516b14f98c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data @@ -299,7 +299,7 @@ bool stm32_pwr_getwuf(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_ENERGYLITE +#ifdef CONFIG_STM32_ENERGYLITE void stm32_pwr_setvos(uint16_t vos) { uint16_t regval; @@ -391,6 +391,6 @@ void stm32_pwr_disablepvd(void) stm32_pwr_modifyreg32(STM32_PWR_CR_OFFSET, PWR_CR_PVDE, 0); } -#endif /* CONFIG_STM32F0L0G0_ENERGYLITE */ +#endif /* CONFIG_STM32_ENERGYLITE */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c index 162a715f142..0e8b03e12ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F0L0G0_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Functions @@ -93,4 +93,4 @@ void stm32_pwr_setvos(uint16_t vos) /* TODO Other stm32_pwr_* functions need to be implemented */ -#endif /* CONFIG_STM32F0L0G0_PWR */ +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c index b12d4ea61ba..8933230be5f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c @@ -124,37 +124,37 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA2EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; #endif -#ifdef CONFIG_STM32F0L0G0_AES +#ifdef CONFIG_STM32_AES /* AES modules clock enable */ regval |= RCC_AHBENR_AESEN; @@ -181,91 +181,91 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPUSART1 +#ifdef CONFIG_STM32_LPUSART1 /* USART 5 clock enable */ regval |= RCC_APB1ENR_LPUSART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* LPTIM2 clock enable */ regval |= RCC_APB1ENR_LPTIM2EN; @@ -292,55 +292,55 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 Timer clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 Timer clock enable */ regval |= RCC_APB2ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM5 Timer clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 Timer clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 Timer clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; @@ -407,14 +407,14 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR uint32_t pwr_vos; #endif uint32_t flash_ws; @@ -451,7 +451,7 @@ static void stm32_stdclockconfig(void) if (STM32_SYSCLK_FREQUENCY > 16000000) { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE1; #endif @@ -470,7 +470,7 @@ static void stm32_stdclockconfig(void) } else { -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR pwr_vos = PWR_CR1_VOS_RANGE2; #endif @@ -484,11 +484,11 @@ static void stm32_stdclockconfig(void) } } -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR stm32_pwr_setvos(pwr_vos); #endif -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -626,8 +626,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -638,7 +638,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c index 201619738e2..1acb1b4a597 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ b/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c @@ -63,55 +63,55 @@ #define FLASH_BLOCK_SIZE _K(2) #define FLASH_PAGE_SIZE 8 -#if !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE) +#if !defined(CONFIG_STM32_FLASH_CONFIG_4) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_6) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE) # error "No valid flash configuration was defined." #endif -#ifdef CONFIG_STM32F0L0G0_FLASH_OVERRIDE -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# undef CONFIG_STM32F0L0G0_FLASH_CONFIG_E -# if defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_4) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_4 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_6) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_6 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_8) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_B) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_B -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_C) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F0L0G0_FLASH_OVERRIDE_E) -# define CONFIG_STM32F0L0G0_FLASH_CONFIG_E +#ifdef CONFIG_STM32_FLASH_OVERRIDE +# undef CONFIG_STM32_FLASH_CONFIG_4 +# undef CONFIG_STM32_FLASH_CONFIG_6 +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_4) +# define CONFIG_STM32_FLASH_CONFIG_4 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_6) +# define CONFIG_STM32_FLASH_CONFIG_6 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # else # error "Invalid flash configuration override provided" # endif #endif -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_4) +#if defined(CONFIG_STM32_FLASH_CONFIG_4) # define FLASH_NBLOCKS 8 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_6) +#elif defined(CONFIG_STM32_FLASH_CONFIG_6) # define FLASH_NBLOCKS 16 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_8) +#elif defined(CONFIG_STM32_FLASH_CONFIG_8) # define FLASH_NBLOCKS 32 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_B) +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) # define FLASH_NBLOCKS 64 -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define FLASH_NBLOCKS 128 # ifdef CONFIG_ARCH_CHIP_STM32G0 # define FLASH_DUAL_BANK 1 # define FLASH_BANK2_BASE 0x08020000 # endif -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define FLASH_NBLOCKS 256 # ifdef CONFIG_ARCH_CHIP_STM32G0 # define FLASH_DUAL_BANK 1 @@ -421,12 +421,12 @@ static void flash_lock_opt(void) static int flash_verify_blocknum(size_t block) { #ifdef FLASH_DUAL_BANK -#if defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) if ((block < 0 || block > 63) && (block < 256 || block > 319)) { return -EFAULT; } -#elif defined(CONFIG_STM32F0L0G0_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) if ((block < 0 || block > 127) && (block < 256 || block > 383)) { return -EFAULT; diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c index 558ee7a2328..6e7b9a92f9d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c @@ -51,10 +51,10 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32F0L0G0_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 -# ifndef CONFIG_STM32F0L0G0_VREFINT +# ifndef CONFIG_STM32_VREFINT # error VREFINT must be enabled if HSI48 used # endif # endif @@ -133,31 +133,31 @@ static inline void rcc_enableahb(void) regval = getreg32(STM32_RCC_AHBENR); -#ifdef CONFIG_STM32F0L0G0_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHBENR_DMA1EN; #endif -#ifdef CONFIG_STM32F0L0G0_MIF +#ifdef CONFIG_STM32_MIF /* Memory interface clock enable */ regval |= RCC_AHBENR_MIFEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHBENR_CRCEN; #endif -#ifdef CONFIG_STM32F0L0G0_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHBENR_TSCEN; #endif -#ifdef CONFIG_STM32F0L0G0_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHBENR_RNGEN; @@ -184,115 +184,115 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F0L0G0_TIM2 +#ifdef CONFIG_STM32_TIM2 /* Timer 2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM3 +#ifdef CONFIG_STM32_TIM3 /* Timer 3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM6 +#ifdef CONFIG_STM32_TIM6 /* Timer 6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM7 +#ifdef CONFIG_STM32_TIM7 /* Timer 7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F0L0G0_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR_LCDEN; #endif -#ifdef CONFIG_STM32F0L0G0_WWDG +#ifdef CONFIG_STM32_WWDG /* Window Watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI 2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART3 +#ifdef CONFIG_STM32_USART3 /* USART 3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART4 +#ifdef CONFIG_STM32_USART4 /* USART 4 clock enable */ regval |= RCC_APB1ENR_USART4EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART5 +#ifdef CONFIG_STM32_USART5 /* USART 5 clock enable */ regval |= RCC_APB1ENR_USART5EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C 1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C 2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB /* USB clock enable */ regval |= RCC_APB1ENR_USBEN; #endif -#ifdef CONFIG_STM32F0L0G0_CRS +#ifdef CONFIG_STM32_CRS /* Clock recovery system clock enable */ regval |= RCC_APB1ENR_CRSEN; #endif -#ifdef CONFIG_STM32F0L0G0_PWR +#ifdef CONFIG_STM32_PWR /* Power interface clock enable */ regval |= RCC_APB1ENR_PWREN; #endif -#ifdef CONFIG_STM32F0L0G0_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC 1 interface clock enable */ regval |= RCC_APB1ENR_DAC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C 3 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F0L0G0_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* LPTIM1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; @@ -319,37 +319,37 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F0L0G0_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* SYSCFG clock */ regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM21 +#ifdef CONFIG_STM32_TIM21 /* TIM21 Timer clock enable */ regval |= RCC_APB2ENR_TIM21EN; #endif -#ifdef CONFIG_STM32F0L0G0_TIM22 +#ifdef CONFIG_STM32_TIM22 /* TIM22 Timer clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F0L0G0_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC 1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI 1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F0L0G0_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; @@ -448,11 +448,11 @@ static inline bool stm32_rcc_enablehse(void) * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32F0G0L0_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) uint16_t pwrcr; #endif uint32_t pwr_vos; @@ -504,7 +504,7 @@ static void stm32_stdclockconfig(void) stm32_pwr_setvos(pwr_vos); -#if defined(CONFIG_STM32F0L0G0_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) || defined(CONFIG_LCD_HSECLOCK) /* If RTC / LCD selects HSE as clock source, the RTC prescaler * needs to be set before HSEON bit is set. */ @@ -683,8 +683,8 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS); -#if defined(CONFIG_STM32F0L0G0_IWDG) || \ - defined(CONFIG_STM32F0L0G0_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || \ + defined(CONFIG_STM32_RTC_LSICLOCK) || defined(CONFIG_LCD_LSICLOCK) /* Low speed internal clock source LSI * * TODO: There is another case where the LSI needs to @@ -695,7 +695,7 @@ static void stm32_stdclockconfig(void) #endif -#if defined(CONFIG_STM32F0L0G0_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) || defined(CONFIG_LCD_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to @@ -722,7 +722,7 @@ static void stm32_stdclockconfig(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT static void vrefint_enable(void) { uint32_t regval = 0; @@ -759,7 +759,7 @@ static inline void rcc_enableperipherals(void) rcc_enableahb(); rcc_enableapb2(); rcc_enableapb1(); -#ifdef CONFIG_STM32F0L0G0_VREFINT +#ifdef CONFIG_STM32_VREFINT vrefint_enable(); #endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig index 29a75f21724..a9c565cda42 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig @@ -48,11 +48,11 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig index 5fd878ff4ff..6b40188837b 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index bd5efbbb3c5..d7167b38ab3 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -55,9 +55,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=1024 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig index 7ed1d73f338..c2004420019 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h index 7ce26a908b0..95e19a5a6c2 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h @@ -87,7 +87,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt index 133c3298bce..4770af26d5f 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs index c1646dd2d1c..55c1d27f870 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 04013570d18..81c81c06f1d 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -137,7 +137,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c index c28639ad262..36d2d48f60e 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c @@ -36,7 +36,7 @@ #include "stm32.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) /**************************************************************************** * Pre-processor Definitions @@ -130,4 +130,4 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32F0L0G0_ADC1 */ +#endif /* CONFIG_ADC && CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c index 3df42fb83cb..ce025e3b964 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c @@ -70,7 +70,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c index 9cd2d49b180..152c4cc463c 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c @@ -97,13 +97,13 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32F0L0G0_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif } diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c index 5e5040b0a86..7b42fb7e3ce 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-l072z-lrwan1.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -117,7 +117,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -168,9 +168,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -182,6 +182,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#endif /* CONFIG_STM32F0L0G0_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig index c2ff7098167..d7d1b1380ec 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig @@ -46,16 +46,16 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC1_SAMPLE_FREQUENCY=10 -CONFIG_STM32F0L0G0_ADC1_TIMTRIG=3 -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_ADC=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=10 +CONFIG_STM32_ADC1_TIMTRIG=3 +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_ADCSCOPE=y CONFIG_SYSTEM_ADCSCOPE_FETCH_INTERVAL=0 CONFIG_SYSTEM_ADCSCOPE_SERIAL_PATH="/dev/ttyS0" diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig index effe787fe75..6f04583925b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig @@ -72,20 +72,20 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=6 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART1=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXMBCLIENT=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig index af2948dd839..ede50792f32 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig @@ -38,7 +38,7 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c index b12a1c64a71..67acc29262f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c index 574a196b778..139d760fc25 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG # include #endif @@ -77,7 +77,7 @@ int stm32_bringup(void) { int ret; -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig index e8640c01a5c..af46d19b5c7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig @@ -42,10 +42,10 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig index 0be70e49195..9a9e901e2bd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig @@ -47,11 +47,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 CONFIG_START_MONTH=10 CONFIG_START_YEAR=2014 -CONFIG_STM32F0L0G0_FDCAN1=y -CONFIG_STM32F0L0G0_FDCAN1_BITRATE=250000 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG1=143 -CONFIG_STM32F0L0G0_FDCAN1_NTSEG2=48 -CONFIG_STM32F0L0G0_FDCAN_SOCKET=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_BITRATE=250000 +CONFIG_STM32_FDCAN1_NTSEG1=143 +CONFIG_STM32_FDCAN1_NTSEG2=48 +CONFIG_STM32_FDCAN_SOCKET=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig index c3a1f4f8b40..8728028d0dc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig @@ -69,21 +69,21 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC_MAX_SAMPLES=2 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_IWDG=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_PULSECOUNT=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_QE=y -CONFIG_STM32F0L0G0_USART2=y -CONFIG_STM32F0L0G0_WWDG=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC_MAX_SAMPLES=2 +CONFIG_STM32_DMA1=y +CONFIG_STM32_IWDG=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_PULSECOUNT=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART2=y +CONFIG_STM32_WWDG=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig index ed0012322cc..49856182e00 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig @@ -38,7 +38,7 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt index 163b6d6bb7c..eacf44fab25 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F0L0G0_FDCAN) - if(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN) + if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() - if(CONFIG_STM32F0L0G0_FDCAN_SOCKET) + if(CONFIG_STM32_FDCAN_SOCKET) list(APPEND SRCS stm32_cansock.c) endif() endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs index aa1ef146219..b6701ee29bf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN),y) -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F0L0G0_FDCAN_SOCKET),y) +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) CSRCS += stm32_cansock.c endif endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h index c802a74b017..f7ab2300b19 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h @@ -116,7 +116,7 @@ int stm32_adc_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(void); #endif @@ -128,7 +128,7 @@ int stm32_can_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET int stm32_cansock_setup(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c index ceb6af10047..29e95219a8e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c index ba1c4751664..eb5bb09a60f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c @@ -39,7 +39,7 @@ # include #endif -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG # include #endif @@ -85,7 +85,7 @@ int stm32_bringup(void) #endif int ret; -#ifdef CONFIG_STM32F0L0G0_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); @@ -150,7 +150,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /* Initialize CAN and register the CAN driver. */ ret = stm32_can_setup(); @@ -160,7 +160,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /* Initialize CAN socket interface */ ret = stm32_cansock_setup(); diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig index fe6bd5a96bc..b5de6c951e8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig @@ -50,8 +50,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h index fc01e4546cb..c8098bc38de 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h index 6fa9242000a..36016f917cc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F072RB GPIOs ******************************************************/ diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c index b742e7e62ec..dbb0d70b4b8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c @@ -40,7 +40,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32F0L0G0_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig index 039c992186b..10d566c6b7d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig @@ -52,8 +52,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig index 6637887a09c..aac6d738084 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h index 8c99f86513f..dd2355bc204 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt index bfafa31ee78..afd6342087a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs index b455d3605ef..82b838efb81 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h index d4798c5bd87..fadc808cd38 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-F091RC GPIOs ******************************************************/ @@ -126,7 +126,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c index 3c92121c7d1..57014d141df 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c index e94166da23c..0fc2cab2ae5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-f091rc.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_LPWAN_SX127X /* Configure the SPI-based SX127X chip select GPIO */ @@ -90,7 +90,7 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ } /**************************************************************************** @@ -119,7 +119,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -170,9 +170,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -184,6 +184,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) { return 0; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 2f5e5cf0859..9b43266c335 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -58,47 +58,47 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_I2C1=y -CONFIG_STM32F0L0G0_PWM_MULTICHAN=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_TIM14=y -CONFIG_STM32F0L0G0_TIM14_CH1OUT=y -CONFIG_STM32F0L0G0_TIM14_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM14_PWM=y -CONFIG_STM32F0L0G0_TIM15=y -CONFIG_STM32F0L0G0_TIM15_CH1OUT=y -CONFIG_STM32F0L0G0_TIM15_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM15_PWM=y -CONFIG_STM32F0L0G0_TIM16=y -CONFIG_STM32F0L0G0_TIM16_CH1OUT=y -CONFIG_STM32F0L0G0_TIM16_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM16_PWM=y -CONFIG_STM32F0L0G0_TIM17=y -CONFIG_STM32F0L0G0_TIM17_CH1OUT=y -CONFIG_STM32F0L0G0_TIM17_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM17_PWM=y -CONFIG_STM32F0L0G0_TIM1=y -CONFIG_STM32F0L0G0_TIM1_CH1OUT=y -CONFIG_STM32F0L0G0_TIM1_CH2OUT=y -CONFIG_STM32F0L0G0_TIM1_CH3OUT=y -CONFIG_STM32F0L0G0_TIM1_CH4OUT=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM1_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM1_PWM=y -CONFIG_STM32F0L0G0_TIM3=y -CONFIG_STM32F0L0G0_TIM3_CH1OUT=y -CONFIG_STM32F0L0G0_TIM3_CH2OUT=y -CONFIG_STM32F0L0G0_TIM3_CH3OUT=y -CONFIG_STM32F0L0G0_TIM3_CH4OUT=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL1=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL2=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL3=y -CONFIG_STM32F0L0G0_TIM3_CHANNEL4=y -CONFIG_STM32F0L0G0_TIM3_PWM=y -CONFIG_STM32F0L0G0_TIM6=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM14=y +CONFIG_STM32_TIM14_CH1OUT=y +CONFIG_STM32_TIM14_CHANNEL1=y +CONFIG_STM32_TIM14_PWM=y +CONFIG_STM32_TIM15=y +CONFIG_STM32_TIM15_CH1OUT=y +CONFIG_STM32_TIM15_CHANNEL1=y +CONFIG_STM32_TIM15_PWM=y +CONFIG_STM32_TIM16=y +CONFIG_STM32_TIM16_CH1OUT=y +CONFIG_STM32_TIM16_CHANNEL1=y +CONFIG_STM32_TIM16_PWM=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM17_CH1OUT=y +CONFIG_STM32_TIM17_CHANNEL1=y +CONFIG_STM32_TIM17_PWM=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CH3OUT=y +CONFIG_STM32_TIM3_CH4OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_CHANNEL3=y +CONFIG_STM32_TIM3_CHANNEL4=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c index 7783acec8ab..5fc389ad066 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c index 4d21f1918ae..975cd5aeb1c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c @@ -101,10 +101,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32F0L0G0_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32F0L0G0_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif } @@ -177,7 +177,7 @@ int stm32_bringup(void) #ifdef CONFIG_TIMER /* Initialize basic timers */ -#if defined(CONFIG_STM32F0L0G0_TIM6) +#if defined(CONFIG_STM32_TIM6) syslog(LOG_ERR, "Init timer\n"); ret = stm32_timer_driver_setup("/dev/timer0", 6); if (ret < 0) @@ -187,7 +187,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM7) +#if defined(CONFIG_STM32_TIM7) ret = stm32_timer_driver_setup("/dev/timer1", 7); if (ret < 0) { diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c index 939713a65cb..b81ff3aa9b6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F0L0G0_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -100,7 +100,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -116,7 +116,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -132,7 +132,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM14_PWM) +#if defined(CONFIG_STM32_TIM14_PWM) pwm = stm32_pwminitialize(14); if (!pwm) { @@ -148,7 +148,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32_pwminitialize(15); if (!pwm) { @@ -164,7 +164,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32_pwminitialize(16); if (!pwm) { @@ -180,7 +180,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F0L0G0_TIM17_PWM) +#if defined(CONFIG_STM32_TIM17_PWM) pwm = stm32_pwminitialize(17); if (!pwm) { diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig index ee39c1d2821..58d337a3690 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig @@ -42,8 +42,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c index a0104c3a648..14706cd0ce5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig index d56da04bd24..565ff0d9dd1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig @@ -48,9 +48,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig index e85080bc6dd..539f7b5141c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -50,18 +50,18 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_ADC1=y -CONFIG_STM32F0L0G0_ADC1_CONTINUOUS=y -CONFIG_STM32F0L0G0_ADC1_DMA=y -CONFIG_STM32F0L0G0_ADC1_DMA_CFG=1 -CONFIG_STM32F0L0G0_ADC_CHANGE_SAMPLETIME=y -CONFIG_STM32F0L0G0_ADC_LL_OPS=y -CONFIG_STM32F0L0G0_ADC_OVERSAMPLE=y -CONFIG_STM32F0L0G0_ADC_OVSR=7 -CONFIG_STM32F0L0G0_ADC_OVSS=4 -CONFIG_STM32F0L0G0_DMA1=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_CONTINUOUS=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC_CHANGE_SAMPLETIME=y +CONFIG_STM32_ADC_LL_OPS=y +CONFIG_STM32_ADC_OVERSAMPLE=y +CONFIG_STM32_ADC_OVSR=7 +CONFIG_STM32_ADC_OVSS=4 +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig index 5ac96442f86..5eea859d573 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig @@ -42,8 +42,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt index f6843c176e1..031e1fc9f43 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt @@ -32,6 +32,10 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/ld.script") diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c index 8d345718a06..b1f9be4fd72 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c @@ -36,7 +36,7 @@ #include "stm32.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F0L0G0_ADC1) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC1) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c index 97a7c428eba..e882e5d1617 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig index 3daccc627d5..c04c43cd46e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig @@ -44,8 +44,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig index 085ba16e7d1..fc8331e8670 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig @@ -53,9 +53,9 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_USART2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h index cd1539a76b3..d24c64eaaf4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h @@ -88,7 +88,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt index c14a6c35881..ac95ed5c073 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs index bd4f63065bd..ff5d2d230eb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h index 7e17a772c36..90410fded75 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h @@ -140,7 +140,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c index ce6e4324bde..a08ebff3930 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c @@ -70,7 +70,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c index eb49b422804..2481cdfb428 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "stm32_spi.h" #include "nucleo-l073rz.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32F0L0G0_SPI2) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI2) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c index e9d0a74aae1..a9495e3544c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-l073rz.h" #include -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Pre-processor Definitions @@ -79,7 +79,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 # ifdef CONFIG_WL_NRF24L01 /* Configure the SPI-based NRF24L01 chip select GPIO */ @@ -99,16 +99,16 @@ void stm32_spidev_initialize(void) stm32_gpiowrite(GPIO_SX127X_CS, true); # endif -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure the SPI-based MFRC522 chip select GPIO */ # ifdef CONFIG_CL_MFRC522 stm32_configgpio(GPIO_MFRC522_CS); # endif -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ } /**************************************************************************** @@ -137,7 +137,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,9 +209,9 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -256,6 +256,6 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) return status; } -#endif /* CONFIG_STM32F0L0G0_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ #endif diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig index 7539573f8be..22a9310041d 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig @@ -37,8 +37,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h index 4436101e931..0975e695619 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt index 185c0672fed..091c56d51df 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs index 520a4c8e891..b991bc06e47 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h index 42d17d21bc0..5c74903ff1f 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig index 476c53cd178..7fc5f309f92 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig @@ -37,8 +37,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_RXBUFSIZE=32 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h index 3ccd8972dfe..06932bb64ee 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h @@ -101,7 +101,7 @@ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC_HSId2 /* Source is HSI/2 */ #define STM32_PLLSRC_FREQUENCY (STM32_HSI_FREQUENCY/2) /* 8MHz / 2 = 4MHz */ -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # undef STM32_CFGR2_PREDIV /* Not used with source HSI/2 */ # define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx12 /* PLLMUL = 12 */ # define STM32_PLL_FREQUENCY (12*STM32_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */ @@ -117,7 +117,7 @@ #define STM32_SYSCLK_SW RCC_CFGR_SW_PLL /* Use the PLL as the SYSCLK */ #define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL -#ifdef CONFIG_STM32F0L0G0_USB +#ifdef CONFIG_STM32_USB # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ #else # define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */ diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt index 0475024980b..ac55fa30c74 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt @@ -32,7 +32,7 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32F0L0G0_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs index 2963ffd2ae2..b71427a7627 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs @@ -34,7 +34,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32F0L0G0_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h index f085bb693bd..db6fe74ca29 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h @@ -42,14 +42,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32F0L0G0_SPI1 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32F0L0G0_SPI2 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32F0L0G0_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* STM32F0Discovery GPIOs ***************************************************/ diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig index 38359008076..693e2684eb6 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig @@ -47,8 +47,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig index a5ed5ebad7a..727e0620e56 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig @@ -69,10 +69,10 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_SPI1=y -CONFIG_STM32F0L0G0_SPI1_COMMTYPE=1 -CONFIG_STM32F0L0G0_USART3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI1_COMMTYPE=1 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c index fbd8501ea9f..9fd6f2becdc 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F0L0G0_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c index 21acd958ab7..1dce5040dd3 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c @@ -39,7 +39,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F0L0G0_I2C1 +#ifndef CONFIG_STM32_I2C1 # error I2C1 must be enabled! #endif diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c index fcac1bef78e..07037ab3d6b 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c @@ -46,10 +46,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -68,7 +68,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -110,7 +110,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,7 +183,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F0L0G0_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #if defined(CONFIG_LCD_SSD1306_SPI) @@ -197,14 +197,14 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) } #endif -#ifdef CONFIG_STM32F0L0G0_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32F0L0G0_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig index 45109183938..f761d37e14e 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig @@ -41,8 +41,8 @@ CONFIG_START_DAY=19 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2013 CONFIG_STDIO_DISABLE_BUFFERING=y -CONFIG_STM32F0L0G0_PWR=y -CONFIG_STM32F0L0G0_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h index 59333f53c8c..5cc344752dc 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h @@ -83,7 +83,7 @@ /* 48MHz clock configuration */ -#if defined(CONFIG_STM32F0L0G0_USB) || defined(CONFIG_STM32F0L0G0_RNG) +#if defined(CONFIG_STM32_USB) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE From fa7d383206e19203e8926b696be4e7fd6bd2eb6b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 19:12:20 +0200 Subject: [PATCH 084/268] arch/stm32: move stm32 and stm32f0l0g0 shared Kconfig options to common Shared STM32 Kconfig option definitions from the stm32 (F1/F2/F3/F4/G4/L1) and stm32f0l0g0 (F0/L0/G0/C0) families moved into arch/arm/src/common/stm32. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig | 8282 ++++++++++++++++++++++++++++- arch/arm/src/stm32/Kconfig | 7112 +------------------------ arch/arm/src/stm32f0l0g0/Kconfig | 2201 +------- 3 files changed, 8328 insertions(+), 9267 deletions(-) diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 37c61bcc2c9..92853f2cf52 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -14,6 +14,72 @@ config STM32_1WIREDRIVER config STM32_HCIUART bool +config STM32_COMMON_LEGACY + bool + default y if ARCH_CHIP_STM32F1 + default y if ARCH_CHIP_STM32F2 + default y if ARCH_CHIP_STM32F3 + default y if ARCH_CHIP_STM32F4 + default y if ARCH_CHIP_STM32G4 + default y if ARCH_CHIP_STM32L1 + +config STM32_COMMON_F0_L0_G0_C0 + bool + default y if ARCH_CHIP_STM32F0 + default y if ARCH_CHIP_STM32L0 + default y if ARCH_CHIP_STM32G0 + default y if ARCH_CHIP_STM32C0 + +config STM32_COMMON_F7_H7 + bool + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_COMMON_H7_H5 + bool + default y if ARCH_CHIP_STM32H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_F7_H7_H5 + bool + default y if STM32_COMMON_F7_H7 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_L4_L5_U5 + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L5_U5 + bool + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 + +config STM32_COMMON_L4_H5_L5_U5 + bool + default y if STM32_COMMON_L4_L5_U5 + default y if ARCH_CHIP_STM32H5 + +config STM32_COMMON_FULL_FEATURED + bool + default y if STM32_COMMON_LEGACY + default y if STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_COMMON_SRAM2_OPTIONS + bool + default y if ARCH_CHIP_STM32L4 + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32L5 + default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 + +config STM32_COMMON_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + choice prompt "JTAG Configuration" default STM32_JTAG_DISABLE @@ -579,6 +645,190 @@ config STM32_LPUART1_1WIREDRIVER endchoice # LPUART1 Driver Configuration +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +choice + prompt "UART8 Driver Configuration" + depends on STM32_COMMON_LEGACY && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + choice prompt "RTC clock source" depends on STM32_RTC @@ -700,9 +950,10 @@ config STM32_FDCAN_SOCKET endchoice # FDCAN character driver or SocketCAN support +if STM32_FDCAN1 + choice prompt "FDCAN1 frame format" - depends on STM32_FDCAN1 default STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_ISO11898_1 @@ -713,13 +964,12 @@ config STM32_FDCAN1_ISO11898_1 config STM32_FDCAN1_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN1 frame format choice prompt "FDCAN1 mode" - depends on STM32_FDCAN1 default STM32_FDCAN1_CLASSIC config STM32_FDCAN1_CLASSIC @@ -737,13 +987,16 @@ config STM32_FDCAN1_FD_BRS bool "CAN FD with fast bit rate switching" depends on CAN_FD || NET_CAN_CANFD ---help--- - Enable CAN FD mode with fast bit rate switching mode. + Enable CAN FD mode with fast bit rate switching mode. endchoice # FDCAN1 mode +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + choice prompt "FDCAN2 frame format" - depends on STM32_FDCAN2 default STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_ISO11898_1 @@ -754,13 +1007,12 @@ config STM32_FDCAN2_ISO11898_1 config STM32_FDCAN2_NONISO_FORMAT bool "Non ISO" ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 + Enable Non ISO, Bosch CAN FD Specification V1.0 endchoice # FDCAN2 frame format choice prompt "FDCAN2 mode" - depends on STM32_FDCAN2 default STM32_FDCAN2_CLASSIC config STM32_FDCAN2_CLASSIC @@ -782,6 +1034,8 @@ config STM32_FDCAN2_FD_BRS endchoice # FDCAN2 mode +endif # STM32_FDCAN2 + choice prompt "Layer 1 color format" depends on STM32_LTDC @@ -1304,4 +1558,8018 @@ config STM32_LPTIM2_CLK_HSI bool "Clock LPTIM2 from HSI" endchoice + +config STM32_TIM_PWM_COMMON + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_TIM_PWM_NO_F0_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_TIM_PWM_ADVANCED_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_SINGLECHAN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_INTERNAL_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 + +config STM32_TIM_PWM_STM32PWM_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + bool + default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_TIM_PWM_CHMODE_LEGACY_COMMON + bool + default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 + +config STM32_TIM_PWM_CHMODE_LIMITED_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_ADC_TIMTRIG_TRGO2_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_ADC_TIMTRIG_TRGO_COMMON + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON + bool + default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_PWM_MULTICHAN_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_SPI_CORE_DMA_CAPABLE + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_RTC_MAGIC_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC + default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC + +config STM32_ADC1_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC1_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER + default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER + +config STM32_ADC2_TIMER_FREQ_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER + +config STM32_ADC2_TIMTRIG_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER + +config STM32_ADC3_TIMER_CAPABLE + bool + default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER + default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN_COMMON + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_QENCODER_MAIN + bool + default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_QENCODER_16BIT_CAPABLE + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_LPTIM1_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_CH1OUT_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_CH1NOUT_CAPABLE + bool + default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + +config STM32_ADC1_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP + +config STM32_ADC2_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_ADC3_OUTPUT_DFSDM_CAPABLE + bool + default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX + default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX + default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX + +config STM32_FLASH_CONFIG_4 + bool + +config STM32_FLASH_CONFIG_6 + bool + +config STM32_FLASH_CONFIG_8 + bool + +config STM32_FLASH_CONFIG_B + bool + +config STM32_FLASH_CONFIG_C + bool + +config STM32_FLASH_CONFIG_D + bool + +config STM32_FLASH_CONFIG_E + bool + +config STM32_FLASH_CONFIG_F + bool + +config STM32_FLASH_CONFIG_G + bool + +config STM32_FLASH_CONFIG_I + bool + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + +config STM32_VALUELINE + bool + select STM32_HAVE_USART3 if STM32_COMMON_LEGACY + select STM32_HAVE_UART4 if STM32_COMMON_LEGACY + select STM32_HAVE_UART5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY + select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY + select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY + select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 + select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +# These hidden settings determine whether a peripheral option is available +# for the selected MCU. Family Kconfigs select these from chip data. + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_SYSCFG + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TSC + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC1_DMA + bool + +config STM32_HAVE_ADC2_DMA + bool + +config STM32_HAVE_ADC3_DMA + bool + +config STM32_HAVE_ADC4_DMA + bool + +config STM32_HAVE_ADC5_DMA + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_ADC4_TIMER + bool + +config STM32_HAVE_ADC5_TIMER + bool + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_COMP1 + bool + +config STM32_HAVE_COMP2 + bool + +config STM32_HAVE_COMP3 + bool + +config STM32_HAVE_COMP4 + bool + +config STM32_HAVE_COMP5 + bool + +config STM32_HAVE_COMP6 + bool + +config STM32_HAVE_COMP7 + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_CEC + bool + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_JPEG + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_HRTIM1_PLLCLK + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_SDADC1_DMA + bool + +config STM32_HAVE_SDADC2_DMA + bool + +config STM32_HAVE_SDADC3_DMA + bool + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_DBGMCU_V1 + bool + +config STM32_HAVE_IP_DBGMCU_V2 + bool + +config STM32_HAVE_IP_DBGMCU_V3 + bool + +config STM32_HAVE_IP_I2C_V1 + bool + +config STM32_HAVE_IP_I2C_V2 + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_TIMERS_V1 + bool + +config STM32_HAVE_IP_TIMERS_V2 + bool + +config STM32_HAVE_IP_TIMERS_V3 + bool + +config STM32_HAVE_IP_ADC_V1 + bool + +config STM32_HAVE_IP_ADC_V1_BASIC + bool + select STM32_HAVE_IP_ADC_V1 + +config STM32_HAVE_IP_ADC_V2 + bool + +config STM32_HAVE_IP_ADC_V2_BASIC + bool + select STM32_HAVE_IP_ADC_V2 + +config STM32_HAVE_IP_COMP_V1 + bool + +config STM32_HAVE_IP_COMP_V2 + bool + +config STM32_HAVE_IP_DAC_V1 + bool + +config STM32_HAVE_IP_DAC_V2 + bool + +config STM32_HAVE_IP_USART_V1 + bool + +config STM32_HAVE_IP_USART_V2 + bool + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_DMA1_CHAN8 + bool + +config STM32_HAVE_DMA2_CHAN678 + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +config STM32_HAVE_QSPI + bool + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_OPAMP1 + bool + +config STM32_HAVE_OPAMP2 + bool + +config STM32_HAVE_OPAMP3 + bool + +config STM32_HAVE_OPAMP4 + bool + +config STM32_HAVE_OPAMP5 + bool + +config STM32_HAVE_OPAMP6 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +config STM32_HAVE_ICACHE + bool + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_LPUART + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_USB + bool + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_ADC1 + bool + default y if STM32_COMMON_LEGACY + +config STM32_ADC1 + bool "ADC1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC2 + bool "ADC2" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC3 + bool "ADC3" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 + +config STM32_ADC4 + bool "ADC4" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if STM32_COMMON_LEGACY + select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_COMP1 + bool "COMP1" + depends on STM32_HAVE_COMP1 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + depends on STM32_HAVE_COMP2 + select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 + +config STM32_BKP + bool "BKP" + depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN if !STM32_COMMON_LEGACY + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_AES + bool "128-bit AES" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CEC + bool "CEC" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 + +config STM32_CRC + bool "CRC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +config STM32_CRYP + bool "CRYP" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH + +config STM32_DMA1 + bool "DMA1" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +config STM32_RTC + bool "RTC" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB + select RTC if !ARCH_CHIP_STM32L5 + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_PWR + bool "PWR" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_IWDG + bool "IWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +config STM32_ADC + bool + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_SPI + bool + +config STM32_SPI_DMA + bool "SPI DMA" + depends on STM32_SPI_CORE_DMA_CAPABLE + ---help--- + Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_I2C + bool + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_TIM + bool + +config STM32_PWM + bool + +config STM32_COMP + bool "COMP" + depends on STM32_HAVE_COMP + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +config STM32_OPAMP + bool "OPAMP" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) + select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) + select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_TIM_PWM_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_TIM_PWM_NO_F0_COMMON + depends on !STM32_COMMON_LEGACY || STM32_TIM + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_TIM_PWM_ADVANCED_COMMON + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM_PWM_ADVANCED_COMMON + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_TIM_PWM_INTERNAL_COMMON + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_COMMON_F0_L0_G0_C0 + default 6 + range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 + range 0 1 if STM32_COMMON_F0_L0_G0_C0 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_TIM_PWM_SINGLECHAN_COMMON + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON + range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + default 6 + range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON + range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_PWM_MULTICHAN_CAPABLE + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_PULSECOUNT + bool + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_COMMON_F0_L0_G0_C0 + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_HAVE_ADC1_TIMER + bool + +config STM32_HAVE_ADC2_TIMER + bool + +config STM32_HAVE_ADC3_TIMER + bool + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_TIMER_FREQ_CAPABLE + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_TIMTRIG_CAPABLE + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_TIMER_CAPABLE + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON + range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_USART + bool + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +#if STM32_I2S + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_RTC_MAGIC_CAPABLE + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_RTC_MAGIC_CAPABLE + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + depends on STM32_CAN + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + depends on STM32_CAN + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on STM32_CAN && DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_QENCODER_16BIT_CAPABLE + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 + select STM32_ADC3_JEXTSEL + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_LCD + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_IO_CONFIG_R + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_V + bool + select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_I + bool + +config STM32_IO_CONFIG_Z + bool + +config STM32_IO_CONFIG_B + bool + +config STM32_IO_CONFIG_A + bool + +config STM32_HAVE_PHY_POLLED + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_HASH + bool + +config STM32_HAVE_DFSDM1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +config STM32_SAI + bool + +menu "SDIO Configuration" + depends on STM32_COMMON_LEGACY && STM32_SDIO + +config STM32_SDIO_CARD + bool "SDIO Card support" + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # SDIO Configuration + +config STM32_SDMMC + bool + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +config STM32_QUADSPI + bool "QuadSPI" + depends on STM32_COMMON_F7_H7 + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +endif # STM32_SDMMC + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + depends on STM32_COMMON_F7_H7 + ---help--- + Enables special, board-specific STM32 clock configuration. + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +config STM32_HAVE_SMPS + bool + +config STM32_HAVE_ETHERNET + bool + +config STM32_LPTIM + bool + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_IO_CONFIG_K + bool + +config STM32_IO_CONFIG_T + bool + +config STM32_IO_CONFIG_C + bool + select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB + +config STM32_IO_CONFIG_J + bool + +config STM32_IO_CONFIG_M + bool + +config STM32_IO_CONFIG_Q + bool + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_HAVE_COMP + bool + +config STM32_HAVE_USART1 + bool + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_CH1OUT_CAPABLE + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_CH1NOUT_CAPABLE + ---help--- + Enables channel 1 complementary output. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA + default 1 + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA + default 1 + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_IPCC + bool "IPCC" + depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 + endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index b0315f1a414..b8bcda25eee 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -5,6 +5,26 @@ comment "STM32 Configuration Options" +config STM32_COMMON_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 + select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX + select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) + select STM32_HAVE_DMA2D if STM32_STM32F429 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD if STM32_STM32L15XX + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX + select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX + select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX + select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "STM32 Chip Selection" default ARCH_CHIP_STM32F103ZE @@ -1210,40 +1230,9 @@ endchoice config STM32_FLASH_CONFIG_DEFAULT bool -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - config STM32_FLASH_CONFIG_Z bool -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - -# This is really 15XX/16XX, but we treat the two the same. config STM32_STM32L15XX bool default n @@ -1254,6 +1243,7 @@ config STM32_STM32L15XX select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM9 @@ -1269,12 +1259,6 @@ config STM32_STM32L15XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_ENERGYLITE - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - config STM32_STM32F10XX bool default n @@ -1282,6 +1266,7 @@ config STM32_STM32F10XX select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_IP_DBGMCU_V1 select STM32_HAVE_IP_TIMERS_V1 @@ -1290,25 +1275,6 @@ config STM32_STM32F10XX select STM32_HAVE_IP_DMA_V1 select STM32_HAVE_IP_I2C_V1 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - config STM32_CONNECTIVITYLINE bool default n @@ -1317,6 +1283,7 @@ config STM32_CONNECTIVITYLINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1335,6 +1302,7 @@ config STM32_PERFORMANCELINE select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1362,6 +1330,7 @@ config STM32_HIGHDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1377,6 +1346,7 @@ config STM32_MEDIUMDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1392,6 +1362,7 @@ config STM32_LOWDENSITY select STM32_HAVE_UART4 select STM32_HAVE_UART5 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 @@ -1413,6 +1384,7 @@ config STM32_STM32F20XX select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1462,6 +1434,7 @@ config STM32_STM32F30XX select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM6 select STM32_HAVE_TIM15 @@ -1507,6 +1480,7 @@ config STM32_STM32F33XX select STM32_HAVE_OPAMP2 select STM32_HAVE_CCM select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM6 select STM32_HAVE_TIM7 select STM32_HAVE_TIM15 @@ -1534,6 +1508,7 @@ config STM32_STM32F37XX select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1594,6 +1569,7 @@ config STM32_STM32F401 select STM32_STM32F4XXX select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1611,6 +1587,7 @@ config STM32_STM32F410 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM5 select STM32_HAVE_TIM6 select STM32_HAVE_TIM9 @@ -1623,6 +1600,7 @@ config STM32_STM32F411 default n select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1674,6 +1652,7 @@ config STM32_STM32F405 select STM32_HAVE_UART5 select STM32_HAVE_USART6 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1748,6 +1727,7 @@ config STM32_STM32F427 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -1793,6 +1773,7 @@ config STM32_STM32F429 select STM32_HAVE_UART7 select STM32_HAVE_UART8 select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 select STM32_HAVE_TIM4 select STM32_HAVE_TIM5 @@ -2119,554 +2100,10 @@ config STM32_STM32G474V select STM32_HAVE_UART4 select STM32_HAVE_UART5 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - menu "STM32 Peripheral Support" -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_FLASH_ICACHE - bool - default n - -config STM32_HAVE_FLASH_DCACHE - bool - default n - -config STM32_HAVE_OVERDRIVE - bool - default n - -config STM32_HAVE_AES - bool - default n - -config STM32_HAVE_CRYP - bool - default n - -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_DMA1_CHAN8 - bool - default n - -config STM32_HAVE_DMA2_CHAN678 - bool - default n - -config STM32_HAVE_DMAMUX - bool - default n - -config STM32_HAVE_UCPD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_USBFS - bool - default n - -config STM32_HAVE_OTGFS - bool - default n - -config STM32_HAVE_FMC - bool - default n - -config STM32_HAVE_FMAC - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - -config STM32_HAVE_FDCAN3 - bool - default n - -config STM32_HAVE_IOCOMPENSATION - bool - default n - -config STM32_HAVE_HRTIM1 - bool - default n - -config STM32_HAVE_HRTIM1_PLLCLK - bool - default n - -config STM32_HAVE_LTDC - bool - default n - -config STM32_HAVE_USART2 - bool - default n - -config STM32_HAVE_USART3 - bool - default n - -config STM32_HAVE_UART4 - bool - default n - -config STM32_HAVE_UART5 - bool - default n - -config STM32_HAVE_USART6 - bool - default n - -config STM32_HAVE_UART7 - bool - default n - -config STM32_HAVE_UART8 - bool - default n - -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 - bool - default n - -config STM32_HAVE_TIM3 - bool - default n - -config STM32_HAVE_TIM4 - bool - default n - -config STM32_HAVE_TIM5 - bool - default n - -config STM32_HAVE_TIM6 - bool - default n - -config STM32_HAVE_TIM7 - bool - default n - -config STM32_HAVE_TIM8 - bool - default n - -config STM32_HAVE_TIM9 - bool - default n - -config STM32_HAVE_TIM10 - bool - default n - -config STM32_HAVE_TIM11 - bool - default n - -config STM32_HAVE_TIM12 - bool - default n - -config STM32_HAVE_TIM13 - bool - default n - -config STM32_HAVE_TIM14 - bool - default n - -config STM32_HAVE_TIM15 - bool - default n - -config STM32_HAVE_TIM16 - bool - default n - -config STM32_HAVE_TIM17 - bool - default n - -config STM32_HAVE_TIM18 - bool - default n - -config STM32_HAVE_TIM19 - bool - default n - -config STM32_HAVE_TIM20 - bool - default n - -config STM32_HAVE_TSC - bool - default n - -config STM32_HAVE_ADC1 - bool - default y - -config STM32_HAVE_ADC2 - bool - default n - -config STM32_HAVE_ADC3 - bool - default n - -config STM32_HAVE_ADC4 - bool - default n - -config STM32_HAVE_ADC5 - bool - default n - -config STM32_HAVE_ADC1_DMA - bool - default n - -config STM32_HAVE_ADC2_DMA - bool - default n - -config STM32_HAVE_ADC3_DMA - bool - default n - -config STM32_HAVE_ADC4_DMA - bool - default n - -config STM32_HAVE_ADC5_DMA - bool - default n - -config STM32_HAVE_SDADC1 - bool - default n - -config STM32_HAVE_SDADC2 - bool - default n - -config STM32_HAVE_SDADC3 - bool - default n - -config STM32_HAVE_SDADC1_DMA - bool - default n - -config STM32_HAVE_SDADC2_DMA - bool - default n - -config STM32_HAVE_SDADC3_DMA - bool - default n - -config STM32_HAVE_CAN1 - bool - default n - -config STM32_HAVE_CAN2 - bool - default n - -config STM32_HAVE_COMP1 - bool - default n - -config STM32_HAVE_COMP2 - bool - default n - -config STM32_HAVE_COMP3 - bool - default n - -config STM32_HAVE_COMP4 - bool - default n - -config STM32_HAVE_COMP5 - bool - default n - -config STM32_HAVE_COMP6 - bool - default n - -config STM32_HAVE_COMP7 - bool - default n - -config STM32_HAVE_CORDIC - bool - default n - -config STM32_HAVE_CRS - bool - default n - -config STM32_HAVE_DAC1 - bool - default n - -config STM32_HAVE_DAC2 - bool - default n - -config STM32_HAVE_DAC3 - bool - default n - -config STM32_HAVE_DAC4 - bool - default n - -config STM32_HAVE_QSPI - bool - default n - -config STM32_HAVE_RNG - bool - default n - -config STM32_HAVE_ETHMAC - bool - default n - -config STM32_HAVE_I2C1 - bool - default n - -config STM32_HAVE_I2C2 - bool - default n - -config STM32_HAVE_I2C3 - bool - default n - -config STM32_HAVE_I2C4 - bool - default n - -config STM32_HAVE_LPTIM1 - bool - default n - -config STM32_HAVE_LPUART1 - bool - default n - -config STM32_HAVE_SPI1 - bool - default n - -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_I2S3 - bool - default n - -config STM32_HAVE_SPI4 - bool - default n - -config STM32_HAVE_SPI5 - bool - default n - -config STM32_HAVE_SPI6 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_OPAMP5 - bool - default n - -config STM32_HAVE_OPAMP6 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_DBGMCU_V1 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V2 - bool - default n - -config STM32_HAVE_IP_DBGMCU_V3 - bool - default n - -config STM32_HAVE_IP_I2C_V1 - bool - default n - -config STM32_HAVE_IP_I2C_V2 - bool - default n - -config STM32_HAVE_IP_DMA_V1 - bool - default n - -config STM32_HAVE_IP_DMA_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V1 - bool - default n - -config STM32_HAVE_IP_TIMERS_V2 - bool - default n - -config STM32_HAVE_IP_TIMERS_V3 - bool - default n - -config STM32_HAVE_IP_ADC_V1 - bool - default n - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - default n - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - default n - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - default n - -config STM32_HAVE_IP_COMP_V2 - bool - default n - -config STM32_HAVE_IP_DAC_V1 - bool - default n - -config STM32_HAVE_IP_DAC_V2 - bool - default n - # These are the peripheral selections proper -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - select STM32_HAVE_ADC1_DMA if STM32_STM32F10XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if STM32_STM32F37XX && STM32_DMA1 - select STM32_HAVE_ADC1_DMA if !STM32_STM32F10XX && STM32_DMA2 - select STM32_HAVE_ADC1_DMA if STM32_DMAMUX - -config STM32_ADC2 - bool "ADC2" - default n - select STM32_ADC - depends on STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA if STM32_DMA2 - select STM32_HAVE_ADC2_DMA if STM32_DMAMUX - -config STM32_ADC3 - bool "ADC3" - default n - select STM32_ADC - depends on STM32_HAVE_ADC3 - select STM32_HAVE_ADC3_DMA if STM32_DMA2 - select STM32_HAVE_ADC3_DMA if STM32_DMAMUX - -config STM32_ADC4 - bool "ADC4" - default n - select STM32_ADC - depends on STM32_HAVE_ADC4 - select STM32_HAVE_ADC4_DMA if STM32_DMA2 - select STM32_HAVE_ADC4_DMA if STM32_DMAMUX - config STM32_ADC5 bool "ADC5" default n @@ -2696,18 +2133,6 @@ config STM32_SDADC3 depends on STM32_HAVE_SDADC3 select STM32_HAVE_SDADC3_DMA if STM32_DMA2 -config STM32_COMP1 - bool "COMP1" - default n - select STM32_COMP - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - select STM32_COMP - depends on STM32_HAVE_COMP2 - config STM32_COMP3 bool "COMP3" default n @@ -2738,90 +2163,11 @@ config STM32_COMP7 select STM32_COMP depends on STM32_HAVE_COMP7 -config STM32_CORDIC - bool "CORDIC Accelerator" - default n - depends on STM32_HAVE_CORDIC - depends on MATH_CORDIC_USE_Q31 - -config STM32_BKP - bool "BKP" - default n - depends on STM32_STM32F10XX - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_CAN1 - bool "CAN1" - default n - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_CAN2 - bool "CAN2" - default n - select STM32_CAN - depends on STM32_HAVE_CAN2 - config STM32_CCMDATARAM bool "CMD/DATA RAM" default n depends on STM32_STM32F4XXX -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - default n - depends on STM32_VALUELINE - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRS - bool "CRS (Clock Recovery System)" - default n - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_CRYP - -config STM32_DMA1 - bool "DMA1" - default n - select STM32_DMA - select ARCH_DMA - -config STM32_DMA2 - bool "DMA2" - default n - select STM32_DMA - select ARCH_DMA - depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - -config STM32_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - if STM32_DAC1 config STM32_DAC1CH1 @@ -2834,12 +2180,6 @@ config STM32_DAC1CH2 endif #STM32_DAC1 -config STM32_DAC2 - bool "DAC2" - default n - depends on STM32_HAVE_DAC2 - select STM32_DAC - if STM32_DAC2 config STM32_DAC2CH1 @@ -2884,56 +2224,6 @@ config STM32_DAC4CH2 endif #STM32_DAC4 -config STM32_DCMI - bool "DCMI" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - -config STM32_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32_HAVE_ETHMAC - select NETDEVICES - select ARCH_HAVE_PHY - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FDCAN2 - bool "FDCAN2" - default n - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - default n - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - default n - depends on STM32_HAVE_FMC - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - default n - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - config STM32_HRTIM bool default n @@ -2984,23 +2274,6 @@ config STM32_HRTIM_TIME endif # STM32_HRTIM -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - config STM32_I2C1_SLAVE bool "I2C1 Slave" default n @@ -3019,38 +2292,6 @@ config STM32_I2C3_SLAVE depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE select STM32_I2C_SLAVE -config STM32_LPTIM1 - bool "LPTIM1" - default n - depends on STM32_HAVE_LPTIM1 - -config STM32_LPUART1 - bool "LPUART1" - default n - depends on STM32_HAVE_LPUART1 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - default n - select FB - depends on STM32_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32_STM32F429 - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - config STM32_OPAMP1 bool "OPAMP1" default n @@ -3075,280 +2316,12 @@ config STM32_OPAMP4 select STM32_OPAMP depends on STM32_HAVE_OPAMP4 -config STM32_RTC - bool "RTC" - default n - select RTC - -config STM32_OTGFS - bool "OTG FS" - default n - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_OTGHS - bool "OTG HS" - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - select USBHOST_HAVE_ASYNCH if STM32_USBHOST - -config STM32_PWR - bool "PWR" - default n - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -# REVISIT: There are some lower-end STM32F401 parts without SDIO too. Others? - -config STM32_SDIO - bool "SDIO" - default n - depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S3 - bool "I2S3" - default n - depends on STM32_HAVE_I2S3 - select I2S - select STM32_I2S - -config STM32_SPI4 - bool "SPI4" - default n - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - default n - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - default n - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - depends on STM32_STM32L15XX || STM32_STM32F30XX || STM32_STM32F33XX || STM32_STM32F37XX || STM32_STM32F20XX || STM32_STM32F4XXX || STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM4 - bool "TIM4" - default n - depends on STM32_HAVE_TIM4 - select STM32_TIM - -config STM32_TIM5 - bool "TIM5" - default n - depends on STM32_HAVE_TIM5 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM8 - bool "TIM8" - default n - depends on STM32_HAVE_TIM8 - select STM32_TIM - -config STM32_TIM9 - bool "TIM9" - default n - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - default n - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - default n - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - default n - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - default n - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - -config STM32_UART4 - bool "UART4" - default n - depends on STM32_HAVE_UART4 - select STM32_USART - -config STM32_UART5 - bool "UART5" - default n - depends on STM32_HAVE_UART5 - select STM32_USART - -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - -config STM32_UART7 - bool "UART7" - default n - depends on STM32_HAVE_UART7 - select STM32_USART - -config STM32_UART8 - bool "UART8" - default n - depends on STM32_HAVE_UART8 - select STM32_USART - -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - default n - depends on STM32_HAVE_USBFS - select USBDEV - config STM32_UCPD bool "UCPD (USB Type C Power Delivery)" default n depends on STM32_HAVE_UCPD select USBDEV -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_STM32L15XX - -# -# STM32 LCD Clock Selection -# - if STM32_LCD choice @@ -3367,88 +2340,20 @@ config LCD_HSECLOCK endchoice endif # STM32_LCD -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - endmenu -config STM32_ADC - bool - default n - config STM32_SDADC bool default n -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_DMAMUX - bool - default n - -config STM32_SPI - bool - default n - -config STM32_SPI_DMA - bool - default n - -config STM32_I2S - bool - default n - select STM32_SPI_DMA - -config STM32_I2C - bool - default n - config STM32_I2C_SLAVE bool default n -config STM32_CAN - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_TIM - bool - default n - -config STM32_PWM - bool - default n - config STM32_CAP bool default n -config STM32_COMP - bool - default n - depends on STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - -config STM32_OPAMP - bool - default n - config STM32_NOEXT_VECTORS bool "Disable the ARMv7-M EXT vectors" default n @@ -3456,19 +2361,6 @@ config STM32_NOEXT_VECTORS Sometimes you may not need any Vector support beyond SysTick and wish to save memory. This applies only to ARMv7-M architectures. -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - depends on STM32_HAVE_IOCOMPENSATION - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - menu "Alternate Pin Mapping" depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE @@ -3666,34 +2558,6 @@ config STM32_FLASH_DCACHE ---help--- Enable the FLASH data cache. -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 - default n - depends on STM32_STM32F20XX || STM32_STM32F4XXX - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - config STM32_FORCEPOWER bool "Force power" default n @@ -3744,2870 +2608,11 @@ config STM32_CCM_PROCFS will provide statistics about CCM memory use similar to what you would get from mallinfo() for the user heap. -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - default n - depends on STM32_FSMC || STM32_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - menu "Timer Configuration" depends on STM32_TIM -if SCHED_TICKLESS - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM1_CHANNEL5 - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM1_CHANNEL6 - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM1_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM1_CHANNEL = 1 - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 1 - -if STM32_TIM1_CHANNEL = 2 - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 2 - -if STM32_TIM1_CHANNEL = 3 - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM1_CHANNEL = 3 - -if STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL = 4 - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM2_CHANNEL = 1 - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL = 1 - -if STM32_TIM2_CHANNEL = 2 - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL = 2 - -if STM32_TIM2_CHANNEL = 3 - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL = 3 - -if STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL = 4 - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM3_CHANNEL = 1 - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL = 1 - -if STM32_TIM3_CHANNEL = 2 - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL = 2 - -if STM32_TIM3_CHANNEL = 3 - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL = 3 - -if STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL = 4 - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32_TIM4 - select STM32_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM4_PWM - -config STM32_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL1 - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL2 - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL3 - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM4_CHANNEL4 - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM4_CHANNEL = 1 - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM4_CHANNEL = 1 - -if STM32_TIM4_CHANNEL = 2 - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM4_CHANNEL = 2 - -if STM32_TIM4_CHANNEL = 3 - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM4_CHANNEL = 3 - -if STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM4_CHANNEL = 4 - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM4_PWM - -config STM32_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32_TIM5 - select STM32_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM5_PWM - -config STM32_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL1 - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL2 - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL3 - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM5_CHANNEL4 - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM5_CHANNEL = 1 - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM5_CHANNEL = 1 - -if STM32_TIM5_CHANNEL = 2 - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM5_CHANNEL = 2 - -if STM32_TIM5_CHANNEL = 3 - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM5_CHANNEL = 3 - -if STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM5_CHANNEL = 4 - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM5_PWM - -config STM32_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32_TIM8 - select STM32_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM8_PWM - -config STM32_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL1 - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL2 - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL3 - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL4 - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 5 (not available externally) - -if STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32_TIM8_CHANNEL5 - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - depends on STM32_HAVE_IP_TIMERS_V2 - ---help--- - Enables channel 6 (not available externally) - -if STM32_TIM8_CHANNEL6 - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32_TIM8_CHANNEL6 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32_TIM8_CHANNEL = 1 - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 1 - -if STM32_TIM8_CHANNEL = 2 - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 2 - -if STM32_TIM8_CHANNEL = 3 - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32_TIM8_CHANNEL = 3 - -if STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM8_CHANNEL = 4 - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM8_PWM - -config STM32_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32_TIM9 - select STM32_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM9_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL1 - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM9_CHANNEL2 - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM9_CHANNEL = 1 - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM9_CHANNEL = 1 - -if STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM9_CHANNEL = 2 - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM9_PWM - -config STM32_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32_TIM10 - select STM32_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM10_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM10_CHANNEL1 - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM10_CHANNEL = 1 - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM10_PWM - -config STM32_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32_TIM11 - select STM32_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM11_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM11_CHANNEL1 - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM11_CHANNEL = 1 - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM11_PWM - -config STM32_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32_TIM12 - select STM32_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM12_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL1 - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM12_CHANNEL2 - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM12_CHANNEL = 1 - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM12_CHANNEL = 1 - -if STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM12_CHANNEL = 2 - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM12_PWM - -config STM32_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32_TIM13 - select STM32_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM13_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM13_CHANNEL1 - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM13_CHANNEL = 1 - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM13_PWM - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL = 1 - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32_TIM15_CHANNEL = 1 - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 1 - -if STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32_TIM15_CHANNEL = 2 - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 if STM32_HAVE_IP_TIMERS_V2 - range 0 7 if !STM32_HAVE_IP_TIMERS_V2 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM16_CHANNEL = 1 - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM17_CHANNEL = 1 - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32_TIM8 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32_TIM4 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32_TIM5 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32_TIM8 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32_TIM9 && STM32_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32_TIM10 && STM32_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32_TIM11 && STM32_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32_TIM12 && STM32_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32_TIM13 && STM32_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32_TIM14 && STM32_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32_TIM1 - select STM32_CAP - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM1_CAP - -config STM32_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM1_CAP - -config STM32_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32_TIM2 - select STM32_CAP - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM2_CAP - -config STM32_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM2_CAP - -config STM32_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32_TIM3 - select STM32_CAP - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM3_CAP - -config STM32_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM3_CAP - -config STM32_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32_TIM4 - select STM32_CAP - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM4_CAP - -config STM32_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM4_CAP - -config STM32_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32_TIM5 - select STM32_CAP - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM5_CAP - -config STM32_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM5_CAP - -config STM32_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32_TIM8 - select STM32_CAP - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM8_CAP - -config STM32_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM8_CAP - -config STM32_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32_TIM9 - select STM32_CAP - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM9_CAP -config STM32_TIM9_CHANNEL - int "TIM9 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM9 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM9_CLOCK int "TIM9 work frequency for capture" default 1000000 @@ -6616,27 +2621,8 @@ config STM32_TIM9_CLOCK endif # STM32_TIM9_CAP -config STM32_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32_TIM10 - select STM32_CAP - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM10_CAP -config STM32_TIM10_CHANNEL - int "TIM10 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM10 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM10_CLOCK int "TIM10 work frequency for capture" default 1000000 @@ -6645,27 +2631,8 @@ config STM32_TIM10_CLOCK endif # STM32_TIM10_CAP -config STM32_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32_TIM11 - select STM32_CAP - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - if STM32_TIM11_CAP -config STM32_TIM11_CHANNEL - int "TIM11 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM11 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - config STM32_TIM11_CLOCK int "TIM11 work frequency for capture" default 1000000 @@ -6674,865 +2641,6 @@ config STM32_TIM11_CLOCK endif # STM32_TIM11_CAP -config STM32_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32_TIM12 - select STM32_CAP - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM12_CAP - -config STM32_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM12 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM12_CAP - -config STM32_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32_TIM13 - select STM32_CAP - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM13_CAP - -config STM32_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM13 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM13_CAP - -config STM32_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32_TIM14 - select STM32_CAP - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -if STM32_TIM14_CAP - -config STM32_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 4 - ---help--- - If TIM14 is enabled for capture usage, you also need specifies the timer input - channel {1,..,4} - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM14_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - endmenu # Timer Configuration menu "HRTIM Configuration" @@ -8119,30 +3227,6 @@ endmenu # "HRTIM Configuration" menu "ADC Configuration" depends on STM32_ADC -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - config STM32_ADC4_RESOLUTION int "ADC4 resolution" depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC @@ -8159,171 +3243,6 @@ config STM32_ADC5_RESOLUTION ---help--- ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32_ADC1 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC1_DMA - default n - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on STM32_ADC2 && STM32_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32_ADC2 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC2_DMA - default n - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on STM32_ADC3 && STM32_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32_ADC3 && STM32_HAVE_IP_ADC_V1 - default STM32_ADC3_DMA - default n - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - config STM32_ADC4_DMA bool "ADC4 DMA" depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA @@ -8388,30 +3307,6 @@ config STM32_ADC5_DMA_BATCH By default, this value is 1, which means that data is transferred after each group conversion. -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - config STM32_ADC4_INJECTED_CHAN int "ADC4 injected channels" depends on STM32_ADC4 @@ -8428,27 +3323,6 @@ config STM32_ADC5_INJECTED_CHAN ---help--- Support for ADC5 injected channels. -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32_ADC2 && !STM32_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32_ADC3 && !STM32_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - config STM32_ADC4_EXTSEL bool "ADC4 external trigger for regular group" depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER @@ -8463,27 +3337,6 @@ config STM32_ADC5_EXTSEL ---help--- Enable EXTSEL for ADC5. -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - config STM32_ADC4_JEXTSEL bool "ADC4 external trigger for injected group" depends on STM32_ADC4 @@ -9230,22 +4083,6 @@ endif endmenu -config STM32_USART - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -config STM32_HCIUART - bool - default n - config STM32_HCIUART_RXDMA bool default n @@ -9255,41 +4092,6 @@ menu "U[S]ART Configuration" comment "U[S]ART Device Configuration" -if STM32_USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART1_SERIALDRIVER - if STM32_USART1_HCIUART config STM32_HCIUART1_RXBUFSIZE @@ -9326,41 +4128,6 @@ config STM32_HCIUART1_RXDMA endif # STM32_USART1_HCIUART -if STM32_USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART2_SERIALDRIVER - if STM32_USART2_HCIUART config STM32_HCIUART2_RXBUFSIZE @@ -9397,41 +4164,6 @@ config STM32_HCIUART2_RXDMA endif # STM32_USART2_HCIUART -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART3_SERIALDRIVER - if STM32_USART3_HCIUART config STM32_HCIUART3_RXBUFSIZE @@ -9468,111 +4200,6 @@ config STM32_HCIUART3_RXDMA endif # STM32_USART3_HCIUART -if STM32_UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART4_SERIALDRIVER - -if STM32_UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART5_SERIALDRIVER - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_USART6_SERIALDRIVER - if STM32_USART6_HCIUART config STM32_HCIUART6_RXBUFSIZE @@ -9609,218 +4236,8 @@ config STM32_HCIUART6_RXDMA endif # STM32_USART6_HCIUART -choice - prompt "UART7 Driver Configuration" - default STM32_UART7_SERIALDRIVER - depends on STM32_UART7 - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART7_SERIALDRIVER - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - default STM32_UART8_SERIALDRIVER - depends on STM32_UART8 - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_UART8_SERIALDRIVER - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - if STM32_LPUART1_SERIALDRIVER -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - config LPUART1_TXDMA bool "LPUART1 Tx DMA" default n @@ -9830,73 +4247,6 @@ config LPUART1_TXDMA endif # STM32_LPUART1_SERIALDRIVER -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -endmenu # Serial Driver Configuration - menu "HCI UART Driver Configuration" depends on STM32_SERIALDRIVER @@ -9964,131 +4314,8 @@ config STM32_HCIUART_LOWER_WATERMARK endmenu # HCI UART Driver Configuration -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - endmenu # U[S]ART Configuration -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # SPI Configuration - menu "I2S Configuration" depends on STM32_I2S3 @@ -10098,55 +4325,8 @@ config STM32_I2S_MCK ---help--- TBD. -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - comment "I2S3 Configuration" -config STM32_I2S3_DATALEN - int "Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -#if STM32_I2S -config STM32_I2S3_RX - bool "Enable I2S receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - endmenu # I2S Configuration menu "I2C Configuration" @@ -10163,36 +4343,6 @@ config STM32_I2C_ALT because: (1) It has not yet been fully verified and (2) It is not certain that he scope of this workaround is needed only for the F103. -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - config STM32_I2C_DUTY16_9 bool "Frequency with Tlow/Thigh = 16/9" default n @@ -10234,429 +4384,8 @@ config STM32_I2C_SLAVE_RETRANSFER endmenu -menu "SDIO Configuration" - depends on STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu - -if STM32_BKPSRAM - -config STM32_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - -endif # STM32_BKPSRAM - -config STM32_HAVE_RTC_COUNTER - bool - default n - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default n - -menu "RTC Configuration" - depends on STM32_RTC - -config STM32_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 19 - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - depends on !STM32_HAVE_RTC_COUNTER - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -endmenu # RTC configuration - -menu "Ethernet MAC configuration" - depends on STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32_ETHFD - bool "Full duplex" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32_AUTONEG - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32_AUTONEG - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32_AUTONEG && !STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32_AUTONEG && STM32_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_OTGFS || STM32_OTGHS - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB HS Host Configuration" - depends on STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu - -menu "USB Host Debug Configuration" - depends on STM32_USBHOST - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - default n - depends on STM32_USBHOST && DEBUG_USB_INFO - ---help--- - Dump all incoming and outgoing USB packets. - -endmenu - comment "USB Device Configuration" -menu "USB Full Speed Debug Configuration" - depends on STM32_USBFS - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -menu "OTG Configuration" - depends on STM32_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - config STM32_USB_ITRMP bool "Re-map USB interrupt" default STM32_CAN1 @@ -10668,779 +4397,12 @@ config STM32_USB_ITRMP their own dedicated vectors. The option is available only for the F3 family and selects the use of the dedicated USB interrupts. -menu "CAN driver configuration" - depends on STM32_CAN - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu # "CAN driver configuration" - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32_FDCAN2 - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN2_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 device driver options - -menu "FDCAN3 device driver options" - depends on STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN3_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - depends on CAN_FD && STM32_FDCAN3_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN3 device driver options - -endmenu # "FDCAN driver configuration" - -if STM32_LTDC - -menu "LTDC Configuration" - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - default n - -config STM32_LTDC_DITHER_RED - depends on STM32_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - depends on STM32_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - depends on STM32_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level LTDC device debug information. -endmenu - -endif # STM32_LTDC - -if STM32_DMA2D - -menu "DMA2D Configuration" - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32_DMA2D_L8 - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32_DMA2D_AL44 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32_DMA2D_AL88 - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32_DMA2D - config STM32_QE bool default n -menu "STM32 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 || STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - -config STM32_TIM1_QE - bool "TIM1 QE" - default n - depends on STM32_TIM1 - select STM32_QE - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32_TIM1_QE - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM2_QE - bool "TIM2 QE" - default n - depends on STM32_TIM2 - select STM32_QE - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32_TIM2_QE - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM3_QE - bool "TIM3 QE" - default n - depends on STM32_TIM3 - select STM32_QE - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32_TIM3_QE - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM4_QE - bool "TIM4 QE" - default n - depends on STM32_TIM4 - select STM32_QE - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32_TIM4_QE - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM5_QE - bool "TIM5 QE" - default n - depends on STM32_TIM5 - select STM32_QE - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32_TIM5_QE - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_TIM8_QE - bool "TIM8 QE" - default n - depends on STM32_TIM8 - select STM32_QE - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32_TIM8_QE - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -endmenu - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - if STM32_FOC -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - depends on STM32_HAVE_TIM1 - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - depends on STM32_HAVE_TIM8 - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -if STM32_FOC_FOC0 - -endif # STM32_FOC_FOC0 - -if STM32_FOC_FOC1 - -endif # STM32_FOC_FOC1 - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - default n - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - default n - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - default n - select STM32_ADC1 - select STM32_ADC1_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - default n - select STM32_ADC2 - select STM32_ADC2_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - default n - select STM32_ADC3 - select STM32_ADC3_SCAN if STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - config STM32_FOC_USE_ADC4 bool default n diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 1ae81719d04..3680c9a8ac3 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -5,6 +5,17 @@ comment "STM32F0/L0/G0 Configuration Options" +config STM32_F0L0G0_PERIPHERALS + bool + default y + depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + select STM32_HAVE_COMP + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + choice prompt "ST STM32F0/L0/G0 Chip Selection" default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 @@ -643,86 +654,6 @@ config ARCH_CHIP_STM32G0B1VE select STM32_FLASH_CONFIG_E depends on ARCH_CHIP_STM32G0 -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32_STM32G0B1 - depends on ARCH_CHIP_STM32G0 - config ARCH_CHIP_STM32L053C8 bool "STM32L053C8" select ARCH_CHIP_STM32L053XX @@ -1115,46 +1046,6 @@ endchoice # ST STM32F0/L0/G0/C0 Chip Selection # Flash configurations -config STM32_FLASH_CONFIG_4 - bool - default n - -config STM32_FLASH_CONFIG_6 - bool - default n - -config STM32_FLASH_CONFIG_8 - bool - default n - -config STM32_FLASH_CONFIG_B - bool - default n - -config STM32_FLASH_CONFIG_C - bool - default n - -config STM32_FLASH_CONFIG_D - bool - default n - -config STM32_FLASH_CONFIG_E - bool - default n - -config STM32_FLASH_CONFIG_F - bool - default n - -config STM32_FLASH_CONFIG_G - bool - default n - -config STM32_FLASH_CONFIG_I - bool - default n - config STM32_FLASH_OVERRIDE bool "Override Flash Designator" default n @@ -1196,6 +1087,7 @@ config STM32_STM32L0 bool default n select STM32_ENERGYLITE + select STM32_HAVE_LCD select STM32_HAVE_VREFINT select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 @@ -1227,16 +1119,20 @@ config STM32_STM32F04X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 config STM32_STM32F05X bool default n select STM32_STM32F0 + select STM32_HAVE_DMA2 config STM32_STM32F07X bool default n select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 config STM32_STM32F09X bool @@ -1428,12 +1324,6 @@ config STM32_STM32G0C1 select STM32_HAVE_CEC select STM32_HAVE_HSI48 -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - config STM32_ACCESSLINE bool default n @@ -1456,10 +1346,6 @@ config STM32_USBLINE select STM32_HAVE_SPI2 select STM32_HAVE_USBDEV -config STM32_ENERGYLITE - bool - default n - config ARCH_CHIP_STM32L053XX bool select STM32_STM32L0 @@ -1516,24 +1402,6 @@ config ARCH_CHIP_STM32C092XX select STM32_HAVE_USART4 select STM32_HAVE_FDCAN1 -config STM32_DFU - bool "DFU bootloader" - default n - depends on !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -config STM32_PROGMEM - bool "Flash PROGMEM support" - default n - depends on ARCH_HAVE_PROGMEM - select MTD - select MTD_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - choice prompt "SysTick clock source" default STM32_SYSTICK_CORECLK @@ -1551,38 +1419,10 @@ menu "STM32 Peripheral Support" # These "hidden" settings determine whether a peripheral option is available # for the selected MCU -config STM32_HAVE_AES - bool - default n - config STM32_HAVE_VREFINT bool default n -config STM32_HAVE_CCM - bool - default n - -config STM32_HAVE_HSI48 - bool - default n - -config STM32_HAVE_LCD - bool - default n - -config STM32_HAVE_USBDEV - bool - default n - -config STM32_HAVE_FSMC - bool - default n - -config STM32_HAVE_USART3 - bool - default n - config STM32_HAVE_USART4 bool default n @@ -1591,10 +1431,6 @@ config STM32_HAVE_USART5 bool default n -config STM32_HAVE_USART6 - bool - default n - config STM32_HAVE_USART7 bool default n @@ -1603,62 +1439,10 @@ config STM32_HAVE_USART8 bool default n -config STM32_HAVE_LPUART1 - bool - default n - config STM32_HAVE_LPUART2 bool default n -config STM32_HAVE_TIM1 - bool - default n - -config STM32_HAVE_TIM2 - bool - default n - -config STM32_HAVE_TIM3 - bool - default n - -config STM32_HAVE_TIM4 - bool - default n - -config STM32_HAVE_TIM6 - bool - default n - -config STM32_HAVE_TIM7 - bool - default n - -config STM32_HAVE_TIM14 - bool - default n - -config STM32_HAVE_TIM15 - bool - default n - -config STM32_HAVE_TIM16 - bool - default n - -config STM32_HAVE_TIM17 - bool - default n - -config STM32_HAVE_TSC - bool - default n - -config STM32_HAVE_ADC1_DMA - bool - default n - config STM32_HAVE_ADC_OVERSAMPLE bool default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 @@ -1667,94 +1451,10 @@ config STM32_HAVE_CEC bool default n -config STM32_HAVE_CAN1 - bool - default n - -config STM32_HAVE_COMP1 - bool - default n - -config STM32_HAVE_COMP2 - bool - default n - -config STM32_HAVE_COMP3 - bool - default n - -config STM32_HAVE_DAC1 - bool - default n - -config STM32_HAVE_DMAMUX - bool - default n - -config STM32_HAVE_DMA2 - bool - default n - -config STM32_HAVE_RNG - bool - default n - -config STM32_HAVE_CRS - bool - default n - -config STM32_HAVE_I2C2 - bool - default n - -config STM32_HAVE_I2C3 - bool - default n - -config STM32_HAVE_SPI2 - bool - default n - -config STM32_HAVE_SPI3 - bool - default n - -config STM32_HAVE_SAIPLL - bool - default n - config STM32_HAVE_SDIO bool default n -config STM32_HAVE_I2SPLL - bool - default n - -config STM32_HAVE_OPAMP1 - bool - default n - -config STM32_HAVE_OPAMP2 - bool - default n - -config STM32_HAVE_OPAMP3 - bool - default n - -config STM32_HAVE_OPAMP4 - bool - default n - -config STM32_HAVE_FDCAN1 - bool - default n - -config STM32_HAVE_FDCAN2 - bool - default n - config STM32_HAVE_I2S2 bool default n @@ -1787,231 +1487,11 @@ config STM32_HAVE_IP_EXTI_V2 # These are the peripheral selections proper -config STM32_ADC1 - bool "ADC1" - default n - select STM32_ADC - -config STM32_COMP1 - bool "COMP1" - default n - depends on STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - default n - depends on STM32_HAVE_COMP2 - -config STM32_BKP - bool "BKP" - default n - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32_CAN1 - bool "CAN1" - default n - select CAN - select STM32_CAN - depends on STM32_HAVE_CAN1 - -config STM32_AES - bool "128-bit AES" - default n - depends on STM32_HAVE_AES - select CRYPTO_AES192_DISABLE if CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if CRYPTO_ALGTEST - config STM32_VREFINT bool "Enable VREFINT" default n depends on STM32_HAVE_VREFINT -config STM32_CEC - bool "CEC" - default n - depends on STM32_HAVE_CEC - -config STM32_CRC - bool "CRC" - default n - -config STM32_CRYP - bool "CRYP" - default n - depends on STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32_DMA - -config STM32_DMA2 - bool "DMA2" - default n - depends on STM32_HAVE_DMA2 - select ARCH_DMA - select STM32_DMA - -config STM32_DAC1 - bool "DAC1" - default n - depends on STM32_HAVE_DAC1 - select STM32_DAC - -config STM32_FDCAN1 - bool "FDCAN1" - default n - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - default n - depends on STM32_HAVE_FSMC - -config STM32_HASH - bool "HASH" - default n - depends on STM32_HAVE_HASH - -config STM32_I2C1 - bool "I2C1" - default n - select STM32_I2C - -config STM32_I2C2 - bool "I2C2" - default n - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - default n - depends on STM32_HAVE_I2C3 - select STM32_I2C - -config STM32_PWR - bool "PWR" - default n - -config STM32_RNG - bool "RNG" - default n - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32_SDIO - bool "SDIO" - default n - depends on STM32_HAVE_SDIO - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - default n - select SPI - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - default n - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - default n - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - default y - -config STM32_TIM1 - bool "TIM1" - default n - depends on STM32_HAVE_TIM1 - select STM32_TIM - -config STM32_TIM2 - bool "TIM2" - default n - depends on STM32_HAVE_TIM2 - select STM32_TIM - -config STM32_TIM3 - bool "TIM3" - default n - depends on STM32_HAVE_TIM3 - select STM32_TIM - -config STM32_TIM6 - bool "TIM6" - default n - depends on STM32_HAVE_TIM6 - select STM32_TIM - -config STM32_TIM7 - bool "TIM7" - default n - depends on STM32_HAVE_TIM7 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - default n - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - default n - depends on STM32_HAVE_TIM15 - select STM32_TIM - -config STM32_TIM16 - bool "TIM16" - default n - depends on STM32_HAVE_TIM16 - select STM32_TIM - -config STM32_TIM17 - bool "TIM17" - default n - depends on STM32_HAVE_TIM17 - select STM32_TIM - -config STM32_TSC - bool "TSC" - default n - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - default n - select STM32_USART - -config STM32_USART2 - bool "USART2" - default n - select STM32_USART - -config STM32_USART3 - bool "USART3" - default n - depends on STM32_HAVE_USART3 - select STM32_USART - config STM32_USART4 bool "USART4" default n @@ -2024,12 +1504,6 @@ config STM32_USART5 depends on STM32_HAVE_USART5 select STM32_USART -config STM32_USART6 - bool "USART6" - default n - depends on STM32_HAVE_USART6 - select STM32_USART - config STM32_USART7 bool "USART7" default n @@ -2042,1558 +1516,11 @@ config STM32_USART8 depends on STM32_HAVE_USART8 select STM32_USART -config STM32_USB - bool "USB Device" - default n - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_LCD - bool "Segment LCD" - default n - depends on STM32_HAVE_LCD - select USBDEV - -config STM32_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - default n - select WATCHDOG - endmenu # STM32 Peripheral Support -config STM32_COMP - bool - default n - -config STM32_ADC - bool - default n - -config STM32_DAC - bool - default n - -config STM32_DMA - bool - default n - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool - default n - -config STM32_I2C - bool - default n - -config STM32_CAN - bool - default n - -config STM32_PWM - bool - default n - -config STM32_USART - bool - default n - -config STM32_TIM - bool - default n - -config STM32_FDCAN - bool - default n - -config STM32_SERIALDRIVER - bool - default n - -config STM32_1WIREDRIVER - bool - default n - -menu "Timer Configuration" - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32_TIM1 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - ---help--- - Reserve timer 1 for use by the pulse count driver. - - Timer devices may be used for different purposes. If STM32_TIM1 - is defined then this option may also be defined to indicate that TIM1 is - intended to generate a fixed number of output pulses. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32_TIM1 && !STM32_TIM1_PULSECOUNT - select STM32_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM1 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM1_PWM - -config STM32_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM1_CHANNEL1 - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - depends on STM32_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32_TIM1_CHANNEL2 - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32_TIM1_CHANNEL3 - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM1_CHANNEL4 - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM1_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for output usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM1_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM1_PWM - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM1_QE - bool "TIM1 Quadrature Encoder" - default n - depends on STM32_TIM1 - ---help--- - Reserve TIM1 for use by Quadrature Encoder. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32_TIM2 - select STM32_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM2 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM2_PWM - -config STM32_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM2_CHANNEL1 - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM2_CHANNEL2 - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM2_CHANNEL3 - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM2_CHANNEL4 - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM2_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM2_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM2_PWM - -config STM32_TIM2_QE - bool "TIM2 Quadrature Encoder" - default n - depends on STM32_TIM2 - ---help--- - Reserve TIM2 for use by Quadrature Encoder. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32_TIM3 - select STM32_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If - STM32_TIM3 is defined then THIS option may also be defined to - indicate that the timer is intended to be used for pulsed output modulation. - - Valid channel modes: - - 0 -> PWM Mode 1 - 1 -> PWM Mode 2 - 2 -> Combined PWM mode 1 - 3 -> Combined PWM mode 2 - 4 -> Asymmetric PWM mode 1 - 5 -> Asymmetric PWM mode 2 - -if STM32_TIM3_PWM - -config STM32_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode: - - 0 -> Upcounting mode - 1 -> Downcounting mode - 2 -> Center-aligned mode 1 - 3 -> Center-aligned mode 2 - 4 -> Center-aligned mode 3 - -if STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM3_CHANNEL1 - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM3_CHANNEL2 - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32_TIM3_CHANNEL3 - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32_TIM3_CHANNEL4 - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32_TIM3_CHANNEL4 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. See STM32_TIM3_PWM description for available modes. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM3_PWM - -config STM32_TIM3_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM3 - ---help--- - Reserve TIM3 for use by Quadrature Encoder. - -config STM32_TIM4_QE - bool "TIM3 Quadrature Encoder" - default n - depends on STM32_TIM4 - ---help--- - Reserve TIM4 for use by Quadrature Encoder. - -menu "STM32F0L0G0 QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - default 1 - depends on STM32_TIM1_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - default 1 - depends on STM32_TIM2_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM3_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QEPSC - int "TIM3 QE pulse prescaler" - default 1 - depends on STM32_TIM4_QE - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - default n - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - default n - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32F0L0G0 QEncoder input" - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -endmenu # STM32F0L0G0 QEncoder Driver - -config STM32_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32_TIM14 - select STM32_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM14_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM14_CHANNEL1 - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32_TIM14_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM14_PWM - -config STM32_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32_TIM15 - select STM32_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM15_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM15_CHANNEL1 - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32_TIM15_CHANNEL2 - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32_TIM15_CHANNEL2 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM15_PWM - -config STM32_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32_TIM16 - select STM32_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM16_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM16_CHANNEL1 - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM16_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM16_PWM - -config STM32_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32_TIM17 - select STM32_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32_TIM17_PWM - -if STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32_TIM17_CHANNEL1 - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32_TIM17_CHANNEL1 - -endif # STM32_PWM_MULTICHAN - -if !STM32_PWM_MULTICHAN - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32_PWM_MULTICHAN - -endif # STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32_PWM - ---help--- - Specifies that the PWM driver supports multiple output channels per timer. - -config STM32_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32_TIM1 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32_TIM2 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32_TIM3 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2. - This option must match with the MCU's supported EXTSEL. - -endmenu # Timer Configuration - -menu "FDCAN driver configuration" - depends on STM32_FDCAN - -config STM32_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -comment "Nominal Bit Timing" - -config STM32_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32_FDCAN1_FD_BRS - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 device driver options - -endmenu # "FDCAN driver configuration" - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -if STM32_USART1_SERIALDRIVER - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART1_SERIALDRIVER - -if STM32_USART2_SERIALDRIVER - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - depends on STM32_HAVE_IP_USART_V2 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART2_SERIALDRIVER - -if STM32_USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART3_SERIALDRIVER - -choice - prompt "USART4 Driver Configuration" - default STM32_USART4_SERIALDRIVER - depends on STM32_USART4 - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -if STM32_USART4_SERIALDRIVER - -config USART4_RS485 - bool "RS-485 on USART4" - default n - ---help--- - Enable RS-485 interface on USART4. Your board config will have to - provide GPIO_USART4_RS485_DIR pin definition. - -config USART4_RS485_DIR_POLARITY - int "USART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART4_SERIALDRIVER - -choice - prompt "USART5 Driver Configuration" - default STM32_USART5_SERIALDRIVER - depends on STM32_USART5 - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -if STM32_USART5_SERIALDRIVER - -config USART5_RS485 - bool "RS-485 on USART5" - default n - ---help--- - Enable RS-485 interface on USART5. Your board config will have to - provide GPIO_USART5_RS485_DIR pin definition. - -config USART5_RS485_DIR_POLARITY - int "USART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART5_SERIALDRIVER - -if STM32_USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART6_SERIALDRIVER - -choice - prompt "USART7 Driver Configuration" - default STM32_USART7_SERIALDRIVER - depends on STM32_USART7 - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -if STM32_USART7_SERIALDRIVER - -config USART7_RS485 - bool "RS-485 on USART7" - default n - ---help--- - Enable RS-485 interface on USART7. Your board config will have to - provide GPIO_USART7_RS485_DIR pin definition. - -config USART7_RS485_DIR_POLARITY - int "USART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART7_SERIALDRIVER - -choice - prompt "USART8 Driver Configuration" - default STM32_USART8_SERIALDRIVER - depends on STM32_USART8 - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -if STM32_USART8_SERIALDRIVER - -config USART8_RS485 - bool "RS-485 on USART8" - default n - ---help--- - Enable RS-485 interface on USART8. Your board config will have to - provide GPIO_USART8_RS485_DIR pin definition. - -config USART8_RS485_DIR_POLARITY - int "USART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # STM32_USART8_SERIALDRIVER - -menu "Serial Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F0 serial driver. - -endmenu # Serial Driver Configuration - -if PM - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM - -endmenu # U[S]ART Configuration - menu "ADC Configuration" depends on STM32_ADC -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 if STM32_ADC1_DMA - default 1 if !STM32_ADC1_DMA - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on STM32_ADC1 && STM32_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - config STM32_ADC1_CONTINUOUS bool "Enable ADC1 Continuous Conversion Mode" default n @@ -3605,99 +1532,3 @@ config STM32_ADC1_CONTINUOUS the same time endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32_SPI - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32_SPI1 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32_SPI2 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32_SPI3 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # SPI Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32_I2C - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32_I2C && !STM32_I2C_DYNTIMEO - -endmenu #I2C Configuration From a704a9b8ea6a8e6540ddc47ec7a2c619706634d9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 21:05:28 +0200 Subject: [PATCH 085/268] arch/stm32: split common Kconfig into per-peripheral files STM32 common Kconfig into smaller files. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig | 9607 +---------------- arch/arm/src/common/stm32/Kconfig.adc | 964 ++ arch/arm/src/common/stm32/Kconfig.ble | 221 + arch/arm/src/common/stm32/Kconfig.cache | 238 + arch/arm/src/common/stm32/Kconfig.can | 58 + arch/arm/src/common/stm32/Kconfig.comp | 387 + arch/arm/src/common/stm32/Kconfig.dac | 363 + arch/arm/src/common/stm32/Kconfig.dfsdm | 46 + arch/arm/src/common/stm32/Kconfig.dma | 118 + arch/arm/src/common/stm32/Kconfig.dts | 99 + arch/arm/src/common/stm32/Kconfig.eth | 290 + arch/arm/src/common/stm32/Kconfig.fdcan | 518 + arch/arm/src/common/stm32/Kconfig.flash | 162 + arch/arm/src/common/stm32/Kconfig.foc | 197 + arch/arm/src/common/stm32/Kconfig.gpio | 9 + arch/arm/src/common/stm32/Kconfig.have | 1191 ++ arch/arm/src/common/stm32/Kconfig.hciuart | 292 + arch/arm/src/common/stm32/Kconfig.hrtim | 583 + arch/arm/src/common/stm32/Kconfig.i2c | 313 + arch/arm/src/common/stm32/Kconfig.ipcc | 91 + arch/arm/src/common/stm32/Kconfig.lpuart | 69 + arch/arm/src/common/stm32/Kconfig.ltdc | 233 + arch/arm/src/common/stm32/Kconfig.memory | 168 + arch/arm/src/common/stm32/Kconfig.periph | 1282 +++ arch/arm/src/common/stm32/Kconfig.qspi | 158 + arch/arm/src/common/stm32/Kconfig.rtc | 93 + arch/arm/src/common/stm32/Kconfig.sai | 88 + arch/arm/src/common/stm32/Kconfig.sdadc | 39 + arch/arm/src/common/stm32/Kconfig.sdio | 150 + arch/arm/src/common/stm32/Kconfig.spi | 300 + arch/arm/src/common/stm32/Kconfig.system | 107 + arch/arm/src/common/stm32/Kconfig.tim | 4205 ++++++++ arch/arm/src/common/stm32/Kconfig.uart | 1245 +++ arch/arm/src/common/stm32/Kconfig.usb | 249 + arch/arm/src/stm32/CMakeLists.txt | 4 +- arch/arm/src/stm32/Kconfig | 2631 +---- arch/arm/src/stm32/Make.defs | 4 +- arch/arm/src/stm32/hardware/stm32_adc.h | 8 +- arch/arm/src/stm32/hardware/stm32_adc_v1.h | 2 +- arch/arm/src/stm32/hardware/stm32_adc_v2.h | 2 +- arch/arm/src/stm32/hardware/stm32_comp.h | 4 +- arch/arm/src/stm32/hardware/stm32_dac.h | 8 +- arch/arm/src/stm32/hardware/stm32_dbgmcu.h | 16 +- arch/arm/src/stm32/hardware/stm32_i2c.h | 4 +- arch/arm/src/stm32/hardware/stm32_tim.h | 6 +- arch/arm/src/stm32/hardware/stm32_tim_v1v2.h | 4 +- arch/arm/src/stm32/stm32_adc.c | 8 +- arch/arm/src/stm32/stm32_comp.c | 4 +- arch/arm/src/stm32/stm32_comp.h | 4 +- arch/arm/src/stm32/stm32_foc.c | 48 +- arch/arm/src/stm32f0l0g0/Kconfig | 154 +- .../b-l072z-lrwan1/configs/adc/defconfig | 1 + .../b-l072z-lrwan1/configs/nsh/defconfig | 1 + .../configs/nxlines_oled/defconfig | 1 + .../b-l072z-lrwan1/configs/sx127x/defconfig | 1 + boards/arm/stm32f0l0g0/common/src/board_pwm.c | 14 +- .../nucleo-c071rb/configs/adcscope/defconfig | 1 + .../nucleo-c071rb/configs/jumbo/defconfig | 1 + .../nucleo-c071rb/configs/nsh/defconfig | 1 + .../nucleo-c092rc/configs/can/defconfig | 1 + .../nucleo-c092rc/configs/cansock/defconfig | 1 + .../nucleo-c092rc/configs/jumbo/defconfig | 1 + .../nucleo-c092rc/configs/nsh/defconfig | 1 + .../nucleo-f072rb/configs/nsh/defconfig | 1 + .../nucleo-f091rc/configs/nsh/defconfig | 1 + .../nucleo-f091rc/configs/sx127x/defconfig | 1 + .../nucleo-g070rb/configs/nsh/defconfig | 1 + .../nucleo-g071rb/configs/nsh/defconfig | 1 + .../nucleo-g0b1re/configs/adc/defconfig | 1 + .../nucleo-g0b1re/configs/adc_dma/defconfig | 1 + .../nucleo-g0b1re/configs/nsh/defconfig | 1 + .../nucleo-l073rz/configs/nsh/defconfig | 1 + .../nucleo-l073rz/configs/sx127x/defconfig | 1 + .../stm32f051-discovery/configs/nsh/defconfig | 1 + .../stm32f072-discovery/configs/nsh/defconfig | 1 + .../stm32g071b-disco/configs/nsh/defconfig | 1 + .../stm32g071b-disco/configs/oled/defconfig | 1 + .../stm32l0538-disco/configs/nsh/defconfig | 1 + 78 files changed, 15202 insertions(+), 11882 deletions(-) create mode 100644 arch/arm/src/common/stm32/Kconfig.adc create mode 100644 arch/arm/src/common/stm32/Kconfig.ble create mode 100644 arch/arm/src/common/stm32/Kconfig.cache create mode 100644 arch/arm/src/common/stm32/Kconfig.can create mode 100644 arch/arm/src/common/stm32/Kconfig.comp create mode 100644 arch/arm/src/common/stm32/Kconfig.dac create mode 100644 arch/arm/src/common/stm32/Kconfig.dfsdm create mode 100644 arch/arm/src/common/stm32/Kconfig.dma create mode 100644 arch/arm/src/common/stm32/Kconfig.dts create mode 100644 arch/arm/src/common/stm32/Kconfig.eth create mode 100644 arch/arm/src/common/stm32/Kconfig.fdcan create mode 100644 arch/arm/src/common/stm32/Kconfig.flash create mode 100644 arch/arm/src/common/stm32/Kconfig.foc create mode 100644 arch/arm/src/common/stm32/Kconfig.gpio create mode 100644 arch/arm/src/common/stm32/Kconfig.have create mode 100644 arch/arm/src/common/stm32/Kconfig.hciuart create mode 100644 arch/arm/src/common/stm32/Kconfig.hrtim create mode 100644 arch/arm/src/common/stm32/Kconfig.i2c create mode 100644 arch/arm/src/common/stm32/Kconfig.ipcc create mode 100644 arch/arm/src/common/stm32/Kconfig.lpuart create mode 100644 arch/arm/src/common/stm32/Kconfig.ltdc create mode 100644 arch/arm/src/common/stm32/Kconfig.memory create mode 100644 arch/arm/src/common/stm32/Kconfig.periph create mode 100644 arch/arm/src/common/stm32/Kconfig.qspi create mode 100644 arch/arm/src/common/stm32/Kconfig.rtc create mode 100644 arch/arm/src/common/stm32/Kconfig.sai create mode 100644 arch/arm/src/common/stm32/Kconfig.sdadc create mode 100644 arch/arm/src/common/stm32/Kconfig.sdio create mode 100644 arch/arm/src/common/stm32/Kconfig.spi create mode 100644 arch/arm/src/common/stm32/Kconfig.system create mode 100644 arch/arm/src/common/stm32/Kconfig.tim create mode 100644 arch/arm/src/common/stm32/Kconfig.uart create mode 100644 arch/arm/src/common/stm32/Kconfig.usb diff --git a/arch/arm/src/common/stm32/Kconfig b/arch/arm/src/common/stm32/Kconfig index 92853f2cf52..a21fdfa9fa8 100644 --- a/arch/arm/src/common/stm32/Kconfig +++ b/arch/arm/src/common/stm32/Kconfig @@ -2,18 +2,9 @@ # Common STM32 Kconfig options shared by STM32 families. # -menu "Common STM32 Configuration Options" +menu "STM32 Configuration Options" depends on ARCH_CHIP_STM32 -config STM32_SERIALDRIVER - bool - -config STM32_1WIREDRIVER - bool - -config STM32_HCIUART - bool - config STM32_COMMON_LEGACY bool default y if ARCH_CHIP_STM32F1 @@ -75,9501 +66,147 @@ config STM32_COMMON_SRAM2_OPTIONS default y if ARCH_CHIP_STM32L5 default y if ARCH_CHIP_STM32U5 && STM32_SRAM2 -config STM32_COMMON_USART_UNCONFIG_ON_CLOSE - bool - default y if ARCH_CHIP_STM32H5 - default y if ARCH_CHIP_STM32N6 +source "arch/arm/src/common/stm32/Kconfig.have" -choice - prompt "JTAG Configuration" - default STM32_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) +source "arch/arm/src/common/stm32/Kconfig.periph" -config STM32_JTAG_DISABLE - bool "Disable all JTAG clocking" +menu "ADC Configuration" + depends on STM32_ADC +source "arch/arm/src/common/stm32/Kconfig.adc" +endmenu # ADC Configuration -config STM32_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" +menu "SDADC Configuration" + depends on STM32_SDADC +source "arch/arm/src/common/stm32/Kconfig.sdadc" +endmenu # SDADC Configuration -config STM32_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" +menu "Cache Configuration" +source "arch/arm/src/common/stm32/Kconfig.cache" +endmenu # Cache Configuration -config STM32_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -choice - prompt "Select TIM1 ADC channel" - depends on STM32_TIM1_ADC - default STM32_TIM1_ADC1 - -config STM32_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM2 ADC channel" - depends on STM32_TIM2_ADC - default STM32_TIM2_ADC1 - -config STM32_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM3 ADC channel" - depends on STM32_TIM3_ADC - default STM32_TIM3_ADC1 - -config STM32_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM4 ADC channel" - depends on STM32_TIM4_ADC - default STM32_TIM4_ADC1 - -config STM32_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM5 ADC channel" - depends on STM32_TIM5_ADC - default STM32_TIM5_ADC1 - -config STM32_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM8 ADC channel" - depends on STM32_TIM8_ADC - default STM32_TIM8_ADC1 - -config STM32_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -choice - prompt "Select TIM1 DAC channel" - depends on STM32_TIM1_DAC - default STM32_TIM1_DAC1 - -config STM32_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM2 DAC channel" - depends on STM32_TIM2_DAC - default STM32_TIM2_DAC1 - -config STM32_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM3 DAC channel" - depends on STM32_TIM3_DAC - default STM32_TIM3_DAC1 - -config STM32_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM4 DAC channel" - depends on STM32_TIM4_DAC - default STM32_TIM4_DAC1 - -config STM32_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM5 DAC channel" - depends on STM32_TIM5_DAC - default STM32_TIM5_DAC1 - -config STM32_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM6 DAC channel" - depends on STM32_TIM6_DAC - default STM32_TIM6_DAC1 - -config STM32_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM7 DAC channel" - depends on STM32_TIM7_DAC - default STM32_TIM7_DAC1 - -config STM32_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM8 DAC channel" - depends on STM32_TIM8_DAC - default STM32_TIM8_DAC1 - -config STM32_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM9 DAC channel" - depends on STM32_TIM9_DAC - default STM32_TIM9_DAC1 - -config STM32_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM10 DAC channel" - depends on STM32_TIM10_DAC - default STM32_TIM10_DAC1 - -config STM32_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM11 DAC channel" - depends on STM32_TIM11_DAC - default STM32_TIM11_DAC1 - -config STM32_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM12 DAC channel" - depends on STM32_TIM12_DAC - default STM32_TIM12_DAC1 - -config STM32_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM13 DAC channel" - depends on STM32_TIM13_DAC - default STM32_TIM13_DAC1 - -config STM32_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -choice - prompt "Select TIM14 DAC channel" - depends on STM32_TIM14_DAC - default STM32_TIM14_DAC1 - -config STM32_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -choice - prompt "USART1 Driver Configuration" - depends on STM32_USART1 - default STM32_USART1_SERIALDRIVER - -config STM32_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART1_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART1 Driver Configuration - -choice - prompt "USART2 Driver Configuration" - depends on STM32_USART2 - default STM32_USART2_SERIALDRIVER - -config STM32_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART2_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART2 Driver Configuration - -choice - prompt "USART3 Driver Configuration" - depends on STM32_USART3 - default STM32_USART3_SERIALDRIVER - -config STM32_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART3_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART3 Driver Configuration - -choice - prompt "UART4 Driver Configuration" - depends on STM32_UART4 - default STM32_UART4_SERIALDRIVER - -config STM32_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART1 Driver Configuration - -choice - prompt "UART5 Driver Configuration" - depends on STM32_UART5 - default STM32_UART5_SERIALDRIVER - -config STM32_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -choice - prompt "USART6 Driver Configuration" - depends on STM32_USART6 - default STM32_USART6_SERIALDRIVER - -config STM32_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART6_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_USART6_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # USART6 Driver Configuration - -choice - prompt "LPUART1 Driver Configuration" - depends on STM32_LPUART1 - default STM32_LPUART1_SERIALDRIVER - -config STM32_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -choice - prompt "USART4 Driver Configuration" - depends on STM32_USART4 - default STM32_USART4_SERIALDRIVER - -config STM32_USART4_SERIALDRIVER - bool "Standard serial driver" - select USART4_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART4_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART4 Driver Configuration - -choice - prompt "USART5 Driver Configuration" - depends on STM32_USART5 - default STM32_USART5_SERIALDRIVER - -config STM32_USART5_SERIALDRIVER - bool "Standard serial driver" - select USART5_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART5_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART5 Driver Configuration - -choice - prompt "USART7 Driver Configuration" - depends on STM32_USART7 - default STM32_USART7_SERIALDRIVER - -config STM32_USART7_SERIALDRIVER - bool "Standard serial driver" - select USART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART7 Driver Configuration - -choice - prompt "USART8 Driver Configuration" - depends on STM32_USART8 - default STM32_USART8_SERIALDRIVER - -config STM32_USART8_SERIALDRIVER - bool "Standard serial driver" - select USART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_USART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -endchoice # USART8 Driver Configuration - -choice - prompt "UART7 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART7 - default STM32_UART7_SERIALDRIVER - -config STM32_UART7_SERIALDRIVER - bool "Standard serial driver" - select UART7_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART7_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART7_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART7 Driver Configuration - -if STM32_UART7_HCIUART - -config STM32_HCIUART7_RXBUFSIZE - int "HCI UART7 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART7_TXBUFSIZE - int "HCI UART7 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART7_BAUD - int "HCI UART7 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART7_RXDMA - bool "HCI UART7 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART7_HCIUART - -choice - prompt "UART8 Driver Configuration" - depends on STM32_COMMON_LEGACY && STM32_UART8 - default STM32_UART8_SERIALDRIVER - -config STM32_UART8_SERIALDRIVER - bool "Standard serial driver" - select UART8_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32_SERIALDRIVER - -config STM32_UART8_1WIREDRIVER - bool "1-Wire driver" - select STM32_1WIREDRIVER - -config STM32_UART8_HCIUART - bool "Bluetooth HCI-UART" - select STM32_HCIUART - depends on WIRELESS_BLUETOOTH - -endchoice # UART8 Driver Configuration - -if STM32_UART8_HCIUART - -config STM32_HCIUART8_RXBUFSIZE - int "HCI UART8 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART8_TXBUFSIZE - int "HCI UART8 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART8_BAUD - int "HCI UART8 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART8_RXDMA - bool "HCI UART8 Rx DMA" - default n - depends on STM32_DMA2 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_UART8_HCIUART - -choice - prompt "RTC clock source" - depends on STM32_RTC - default STM32_RTC_LSECLOCK - -config STM32_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice # RTC clock source - -choice - prompt "MII clock configuration" - depends on STM32_MII - default STM32_MII_MCO if STM32_STM32F10XX - default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_MII_EXTCLK - -config STM32_MII_MCO - bool "Use MC0 as MII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the MII interface. Default: Use MC0 - -config STM32_MII_MCO1 - bool "Use MC01 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the MII interface. Default: Use MC01 - -config STM32_MII_MCO2 - bool "Use MC02 as MII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the MII interface. Default: Use MC01 - -config STM32_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for MII - clock. Default: Use MC0[1] - -endchoice - -choice - prompt "RMII clock configuration" - depends on STM32_RMII - default STM32_RMII_MCO if STM32_STM32F10XX - default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX - default STM32_RMII_EXTCLK - -config STM32_RMII_MCO - bool "Use MC0 as RMII clock" - depends on STM32_STM32F10XX - ---help--- - Use MCO to clock the RMII interface. Default: Use MC0 - -config STM32_RMII_MCO1 - bool "Use MC01 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO1 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_MCO2 - bool "Use MC02 as RMII clock" - depends on (STM32_STM32F20XX || STM32_STM32F4XXX) - ---help--- - Use MCO2 to clock the RMII interface. Default: Use MC01 - -config STM32_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. Don't use MCO for RMII - clock. Default: Use MC0[1] - -endchoice - -choice - prompt "CAN character driver or SocketCAN support" +menu "CAN Configuration" depends on STM32_CAN - default STM32_CAN_CHARDRIVER +source "arch/arm/src/common/stm32/Kconfig.can" +endmenu # CAN Configuration -config STM32_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -choice - prompt "FDCAN character driver or SocketCAN support" +menu "FDCAN Configuration" depends on STM32_FDCAN - default STM32_FDCAN_CHARDRIVER +source "arch/arm/src/common/stm32/Kconfig.fdcan" +endmenu # FDCAN Configuration -config STM32_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN +menu "DAC Configuration" + depends on STM32_DAC +source "arch/arm/src/common/stm32/Kconfig.dac" +endmenu # DAC Configuration -config STM32_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD +menu "DFSDM Configuration" + depends on STM32_DFSDM1 || STM32_MDF1 || STM32_ADF1 +source "arch/arm/src/common/stm32/Kconfig.dfsdm" +endmenu # DFSDM Configuration -endchoice # FDCAN character driver or SocketCAN support +menu "DMA Configuration" + depends on STM32_DMA || STM32_DMA2D +source "arch/arm/src/common/stm32/Kconfig.dma" +endmenu # DMA Configuration -if STM32_FDCAN1 +menu "Ethernet Configuration" + depends on STM32_ETHMAC +source "arch/arm/src/common/stm32/Kconfig.eth" +endmenu # Ethernet Configuration -choice - prompt "FDCAN1 frame format" - default STM32_FDCAN1_ISO11898_1 +menu "Flash Configuration" +source "arch/arm/src/common/stm32/Kconfig.flash" +endmenu # Flash Configuration -config STM32_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format +menu "FOC Configuration" + depends on STM32_HAVE_COMMON_FOC +source "arch/arm/src/common/stm32/Kconfig.foc" +endmenu # FOC Configuration -config STM32_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 +menu "GPIO Configuration" +source "arch/arm/src/common/stm32/Kconfig.gpio" +endmenu # GPIO Configuration -endchoice # FDCAN1 frame format +menu "I2C Configuration" + depends on STM32_I2C +source "arch/arm/src/common/stm32/Kconfig.i2c" +endmenu # I2C Configuration -choice - prompt "FDCAN1 mode" - default STM32_FDCAN1_CLASSIC +menu "IPCC Configuration" + depends on STM32_IPCC || STM32_HAVE_HSEM +source "arch/arm/src/common/stm32/Kconfig.ipcc" +endmenu # IPCC Configuration -config STM32_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode +menu "BLE Configuration" + depends on STM32_BLE || STM32_MBOX +source "arch/arm/src/common/stm32/Kconfig.ble" +endmenu # BLE Configuration -config STM32_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32_FDCAN2_ISO11898_1 - -config STM32_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32_FDCAN2_CLASSIC - -config STM32_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -endif # STM32_FDCAN2 - -choice - prompt "Layer 1 color format" +menu "LTDC Configuration" depends on STM32_LTDC - default STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP - -config STM32_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32_FB_CMAP - -config STM32_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32_FB_CMAP - -endchoice # Layer 1 color format - -choice - prompt "Layer 2 (top layer) color format" - depends on STM32_LTDC && STM32_LTDC_L2 - default STM32_LTDC_L2_RGB565 - -config STM32_LTDC_L2_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_LTDC_L1_L8 - -config STM32_LTDC_L2_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_LTDC_L1_AL44 - -config STM32_LTDC_L2_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_LTDC_L1_AL88 - -config STM32_LTDC_L2_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - -config STM32_LTDC_L2_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - -config STM32_LTDC_L2_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB1555 - -config STM32_LTDC_L2_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - -config STM32_LTDC_L2_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - -endchoice # Layer 2 color format - -choice - prompt "Input channel sampling frequency" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_FDTS_4 - -config STM32_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - prompt "Input channel event count" - depends on STM32_QENCODER_FILTER - default STM32_QENCODER_SAMPLE_EVENT_6 - -config STM32_QENCODER_SAMPLE_EVENT_1 - bool "1" - depends on STM32_QENCODER_SAMPLE_FDTS - -config STM32_QENCODER_SAMPLE_EVENT_2 - bool "2" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_4 - bool "4" - depends on STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_5 - bool "5" - depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 - -config STM32_QENCODER_SAMPLE_EVENT_6 - bool "6" - depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT - -config STM32_QENCODER_SAMPLE_EVENT_8 - bool "8" - depends on !STM32_QENCODER_SAMPLE_FDTS - -endchoice - -choice - prompt "FOC ADC trigger selection" - depends on STM32_FOC - default STM32_FOC_ADC_TRGO - -config STM32_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on STM32_HAVE_IP_ADC_V2 || (STM32_HAVE_IP_ADC_V1 && !STM32_FOC_FOC1) - select STM32_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -choice - prompt "FOC0 device ADC selection" - depends on STM32_FOC_FOC0 - default STM32_FOC_FOC0_ADC1 - -config STM32_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC0_ADC4 - bool "FOC0 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -choice - prompt "FOC1 device ADC selection" - depends on STM32_FOC_FOC1 - default STM32_FOC_FOC1_ADC2 - -config STM32_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - depends on STM32_HAVE_ADC1 - select STM32_FOC_USE_ADC1 - -config STM32_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - depends on STM32_HAVE_ADC2 - select STM32_FOC_USE_ADC2 - -config STM32_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - depends on STM32_HAVE_ADC3 - select STM32_FOC_USE_ADC3 - -config STM32_FOC_FOC1_ADC4 - bool "FOC1 uses ADC4" - depends on STM32_HAVE_ADC4 - select STM32_FOC_USE_ADC4 - -endchoice # "FOC0 device ADC selection" - -choice - prompt "Override Flash Size Designator" - default STM32_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F series parts numbering (sans the package type) ends with a number or letter - that designates the FLASH size. - - Designator Size in KiB - 4 16 - 6 32 - 8 64 - B 128 - C 256 - D 384 - E 512 - F 768 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32G071RB is chosen, the Flash configuration would be 'B', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - -config STM32_FLASH_OVERRIDE_4 - bool "4 16KiB" - -config STM32_FLASH_OVERRIDE_6 - bool "6 32KiB" - -config STM32_FLASH_OVERRIDE_8 - bool "8 64KiB" - -config STM32_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32_FLASH_OVERRIDE_D - bool "D 384KiB" - -config STM32_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32_FLASH_OVERRIDE_F - bool "F 768KiB" - -config STM32_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32_FLASH_OVERRIDE_I - bool "I 2048KiB" - -config STM32_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # Override Flash Size Designator - -choice - prompt "Select TIM15 ADC channel" - depends on STM32_TIM15_ADC - default STM32_TIM15_ADC1 - -config STM32_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -choice - prompt "Transfer technique" - depends on STM32_QSPI - default STM32_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32_QSPI_DMA - bool "DMA" - depends on STM32_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - depends on STM32_QSPI - default STM32_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - depends on STM32_QSPI && STM32_QSPI_DMA && STM32_DMA - default STM32_QSPI_DMAPRIORITY_MEDIUM - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32_DMA - ---help--- - 'Highest' priority. - -config STM32_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32_DMA - ---help--- - 'High' priority. - -config STM32_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32_DMA - ---help--- - 'Medium' priority. - -config STM32_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32_DMA - ---help--- - 'Low' priority. - -endchoice - -choice - prompt "Operation mode" - depends on STM32_SAI - default STM32_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - depends on STM32_SAI1_A && STM32_SAI1_B - default STM32_SAI1_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - depends on STM32_SAI2_A && STM32_SAI2_B - default STM32_SAI2_BOTH_ASYNC - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -choice - prompt "Select ADC for use with TIM6" - depends on STM32_TIM6_ADC - default STM32_TIM6_ADC1 - -config STM32_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32_ADC1 - select STM32_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32_ADC2 - select STM32_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32_ADC3 - select STM32_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -choice - prompt "LPTIM1 clock source" - default STM32_LPTIM1_CLK_APB1 - -config STM32_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" - -endchoice - -choice - prompt "LPTIM2 clock source" - default STM32_LPTIM2_CLK_APB1 - -config STM32_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" - -endchoice - -config STM32_TIM_PWM_COMMON - bool - default y if STM32_COMMON_FULL_FEATURED - -config STM32_TIM_PWM_NO_F0_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_TIM_PWM_ADVANCED_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_SINGLECHAN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_INTERNAL_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 - -config STM32_TIM_PWM_STM32PWM_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - -config STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - bool - default y if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - -config STM32_TIM_PWM_CHMODE_LEGACY_COMMON - bool - default y if STM32_COMMON_LEGACY && !STM32_HAVE_IP_TIMERS_V2 - -config STM32_TIM_PWM_CHMODE_LIMITED_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - -config STM32_ADC_TIMTRIG_TRGO2_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 - -config STM32_ADC_TIMTRIG_TRGO_COMMON - bool - default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 - -config STM32_TIM_PWM_NOUT_REQUIRES_OUT_COMMON - bool - default y if STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5 - -config STM32_PWM_MULTICHAN_L5_TIMERS - bool - default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM - default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM - default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM - -config STM32_PWM_MULTICHAN_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_PWM - default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM - default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS - -config STM32_SPI_CORE_DMA_CAPABLE - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 - default y if STM32_COMMON_F7_H7_H5 - default y if ARCH_CHIP_STM32WL5 - default y if STM32_COMMON_L4_L5_U5 && STM32_SPI - default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA - -config STM32_SPI_DMA_FAMILY_WL5 - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 - -config STM32_SPI_DMA_FAMILY - bool - default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default y if STM32_COMMON_H7_H5 - -config STM32_RTC_MAGIC_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_RTC - default y if (STM32_COMMON_L5_U5 || ARCH_CHIP_STM32WB) && STM32_RTC - -config STM32_ADC1_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC1_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC1_TIMER - default y if (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7) && STM32_HAVE_ADC1_TIMER - default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_HAVE_ADC1_TIMER - -config STM32_ADC2_TIMER_FREQ_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_HAVE_ADC2_TIMER - -config STM32_ADC2_TIMTRIG_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC2_TIMER - default y if (STM32_COMMON_F7_H7_H5) && STM32_HAVE_ADC2_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC2_TIMER - -config STM32_ADC3_TIMER_CAPABLE - bool - default y if STM32_COMMON_LEGACY && STM32_TIM && STM32_HAVE_ADC3_TIMER - default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3_TIMER - default y if STM32_COMMON_L5_U5 && STM32_HAVE_ADC3_TIMER - -config STM32_QENCODER_TIMS_1_4 - bool - default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 - -config STM32_QENCODER_TIMS_1_8 - bool - default y if STM32_QENCODER_TIMS_1_4 - default y if STM32_TIM5 || STM32_TIM8 - -config STM32_QENCODER_MAIN_COMMON - bool - default y if STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 - default y if STM32_COMMON_L4_L5_U5 - -config STM32_QENCODER_MAIN - bool - default y if STM32_QENCODER_MAIN_COMMON && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_STM32 - bool - default y if STM32_COMMON_LEGACY && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 - -config STM32_QENCODER_F0 - bool - default y if STM32_COMMON_F0_L0_G0_C0 && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 - -config STM32_QENCODER_16BIT_CAPABLE - bool - default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 - -config STM32_LPTIM1_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM1_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM1_CH1OUT_CAPABLE && STM32_LPTIM1_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 - -config STM32_LPTIM2_CH1OUT_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_LPTIM2_CH1NOUT_CAPABLE - bool - default y if STM32_LPTIM2_CH1OUT_CAPABLE && STM32_LPTIM2_CH1OUT - default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 - -config STM32_ADC1_DFSDM_L4_CHIP - bool - default y if STM32_STM32L496XX || STM32_STM32L4XR - -config STM32_ADC1_DFSDM_L5_CHIP - bool - default y if STM32_STM32L596XX || STM32_STM32L5XR - -config STM32_ADC1_DFSDM_U5_CHIP - bool - default y if STM32_STM32U596XX || STM32_STM32U5XR - -config STM32_ADC1_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L4_CHIP - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_L5_CHIP - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC1 && STM32_DFSDM1 && STM32_ADC1_DFSDM_U5_CHIP - -config STM32_ADC2_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC2 && STM32_DFSDM1 && STM32_STM32U596XX - -config STM32_ADC3_OUTPUT_DFSDM_CAPABLE - bool - default y if ARCH_CHIP_STM32L4 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L496XX - default y if ARCH_CHIP_STM32L5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32L596XX - default y if ARCH_CHIP_STM32U5 && STM32_ADC && STM32_ADC3 && STM32_DFSDM1 && STM32_STM32U596XX - -config STM32_FLASH_CONFIG_4 - bool - -config STM32_FLASH_CONFIG_6 - bool - -config STM32_FLASH_CONFIG_8 - bool - -config STM32_FLASH_CONFIG_B - bool - -config STM32_FLASH_CONFIG_C - bool - -config STM32_FLASH_CONFIG_D - bool - -config STM32_FLASH_CONFIG_E - bool - -config STM32_FLASH_CONFIG_F - bool - -config STM32_FLASH_CONFIG_G - bool - -config STM32_FLASH_CONFIG_I - bool - -config STM32_ENERGYLITE - bool - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - -config STM32_VALUELINE - bool - select STM32_HAVE_USART3 if STM32_COMMON_LEGACY - select STM32_HAVE_UART4 if STM32_COMMON_LEGACY - select STM32_HAVE_UART5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM1 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM5 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM6 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM7 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM12 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM13 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM14 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM15 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM16 if STM32_COMMON_LEGACY - select STM32_HAVE_TIM17 if STM32_COMMON_LEGACY - select STM32_HAVE_SPI2 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_COMMON_LEGACY && STM32_HIGHDENSITY - select STM32_HAVE_USART5 if STM32_COMMON_F0_L0_G0_C0 - select STM32_HAVE_SPI2 if STM32_COMMON_F0_L0_G0_C0 - -config STM32_DFU - bool "DFU bootloader" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !STM32_VALUELINE - ---help--- - Configure and position code for use with the STMicro DFU bootloader. Do - not select this option if you will load code using JTAG/SWM. - -# These hidden settings determine whether a peripheral option is available -# for the selected MCU. Family Kconfigs select these from chip data. - -config STM32_HAVE_AES - bool - -config STM32_HAVE_CRYP - bool - -config STM32_HAVE_CCM - bool - -config STM32_HAVE_DMAMUX - bool - -config STM32_HAVE_USBDEV - bool - -config STM32_HAVE_USBFS - bool - -config STM32_HAVE_OTGFS - bool - -config STM32_HAVE_FMC - bool - -config STM32_HAVE_FSMC - bool - -config STM32_HAVE_SYSCFG - bool - -config STM32_HAVE_FDCAN1 - bool - -config STM32_HAVE_FDCAN2 - bool - -config STM32_HAVE_FDCAN3 - bool - -config STM32_HAVE_LTDC - bool - -config STM32_HAVE_USART2 - bool - -config STM32_HAVE_USART3 - bool - -config STM32_HAVE_UART4 - bool - -config STM32_HAVE_UART5 - bool - -config STM32_HAVE_USART6 - bool - -config STM32_HAVE_UART7 - bool - -config STM32_HAVE_UART8 - bool - -config STM32_HAVE_TIM1 - bool - -config STM32_HAVE_TIM2 - bool - -config STM32_HAVE_TIM3 - bool - -config STM32_HAVE_TIM4 - bool - -config STM32_HAVE_TIM5 - bool - -config STM32_HAVE_TIM6 - bool - -config STM32_HAVE_TIM7 - bool - -config STM32_HAVE_TIM8 - bool - -config STM32_HAVE_TIM9 - bool - -config STM32_HAVE_TIM10 - bool - -config STM32_HAVE_TIM11 - bool - -config STM32_HAVE_TIM12 - bool - -config STM32_HAVE_TIM13 - bool - -config STM32_HAVE_TIM14 - bool - -config STM32_HAVE_TIM15 - bool - -config STM32_HAVE_TIM16 - bool - -config STM32_HAVE_TIM17 - bool - -config STM32_HAVE_TSC - bool - -config STM32_HAVE_ADC2 - bool - -config STM32_HAVE_ADC3 - bool - -config STM32_HAVE_ADC4 - bool - -config STM32_HAVE_ADC5 - bool - -config STM32_HAVE_ADC1_DMA - bool - -config STM32_HAVE_ADC2_DMA - bool - -config STM32_HAVE_ADC3_DMA - bool - -config STM32_HAVE_ADC4_DMA - bool - -config STM32_HAVE_ADC5_DMA - bool - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_ADC4_TIMER - bool - -config STM32_HAVE_ADC5_TIMER - bool - -config STM32_HAVE_CAN1 - bool - -config STM32_HAVE_CAN2 - bool - -config STM32_HAVE_CAN3 - bool - -config STM32_HAVE_COMP1 - bool - -config STM32_HAVE_COMP2 - bool - -config STM32_HAVE_COMP3 - bool - -config STM32_HAVE_COMP4 - bool - -config STM32_HAVE_COMP5 - bool - -config STM32_HAVE_COMP6 - bool - -config STM32_HAVE_COMP7 - bool - -config STM32_HAVE_CRS - bool - -config STM32_HAVE_CEC - bool - -config STM32_HAVE_CORDIC - bool - -config STM32_HAVE_DSIHOST - bool - -config STM32_HAVE_JPEG - bool - -config STM32_HAVE_INTERNAL_ULPI - bool - -config STM32_HAVE_EXTERNAL_ULPI - bool - -config STM32_HAVE_HRTIM1 - bool - -config STM32_HAVE_HRTIM1_PLLCLK - bool - -config STM32_HAVE_TIM18 - bool - -config STM32_HAVE_TIM19 - bool - -config STM32_HAVE_TIM20 - bool - -config STM32_HAVE_SDADC1 - bool - -config STM32_HAVE_SDADC2 - bool - -config STM32_HAVE_SDADC3 - bool - -config STM32_HAVE_SDADC1_DMA - bool - -config STM32_HAVE_SDADC2_DMA - bool - -config STM32_HAVE_SDADC3_DMA - bool - -config STM32_HAVE_SDIO - bool - -config STM32_HAVE_UCPD1 - bool - -config STM32_HAVE_UCPD2 - bool - -config STM32_HAVE_RTC_COUNTER - bool - -config STM32_HAVE_IP_DBGMCU_V1 - bool - -config STM32_HAVE_IP_DBGMCU_V2 - bool - -config STM32_HAVE_IP_DBGMCU_V3 - bool - -config STM32_HAVE_IP_I2C_V1 - bool - -config STM32_HAVE_IP_I2C_V2 - bool - -config STM32_HAVE_IP_DMA_V1 - bool - -config STM32_HAVE_IP_DMA_V2 - bool - -config STM32_HAVE_IP_TIMERS_V1 - bool - -config STM32_HAVE_IP_TIMERS_V2 - bool - -config STM32_HAVE_IP_TIMERS_V3 - bool - -config STM32_HAVE_IP_ADC_V1 - bool - -config STM32_HAVE_IP_ADC_V1_BASIC - bool - select STM32_HAVE_IP_ADC_V1 - -config STM32_HAVE_IP_ADC_V2 - bool - -config STM32_HAVE_IP_ADC_V2_BASIC - bool - select STM32_HAVE_IP_ADC_V2 - -config STM32_HAVE_IP_COMP_V1 - bool - -config STM32_HAVE_IP_COMP_V2 - bool - -config STM32_HAVE_IP_DAC_V1 - bool - -config STM32_HAVE_IP_DAC_V2 - bool - -config STM32_HAVE_IP_USART_V1 - bool - -config STM32_HAVE_IP_USART_V2 - bool - -config STM32_HAVE_IP_EXTI_V1 - bool - -config STM32_HAVE_IP_EXTI_V2 - bool - -config STM32_HAVE_FMAC - bool - -config STM32_HAVE_FLASH_ICACHE - bool - -config STM32_HAVE_FLASH_DCACHE - bool - -config STM32_HAVE_OVERDRIVE - bool - -config STM32_HAVE_DMA1_CHAN8 - bool - -config STM32_HAVE_DMA2_CHAN678 - bool - -config STM32_HAVE_UCPD - bool - -config STM32_HAVE_DAC1 - bool - -config STM32_HAVE_DAC2 - bool - -config STM32_HAVE_DAC3 - bool - -config STM32_HAVE_DAC4 - bool - -config STM32_HAVE_QSPI - bool - -config STM32_HAVE_RNG - bool - -config STM32_HAVE_VREFINT - bool - -config STM32_HAVE_I2C1 - bool - -config STM32_HAVE_I2C2 - bool - -config STM32_HAVE_I2C3 - bool - -config STM32_HAVE_I2C4 - bool - -config STM32_HAVE_SDMMC1 - bool - -config STM32_HAVE_SDMMC2 - bool - -config STM32_HAVE_LPTIM1 - bool - -config STM32_HAVE_LPUART1 - bool - -config STM32_HAVE_LPUART2 - bool - -config STM32_HAVE_SPI1 - bool - -config STM32_HAVE_SPI2 - bool - -config STM32_HAVE_SPI3 - bool - -config STM32_HAVE_I2S3 - bool - -config STM32_HAVE_I2S2 - bool - -config STM32_HAVE_SPI2S2 - bool - -config STM32_HAVE_SPI4 - bool - -config STM32_HAVE_SPI5 - bool - -config STM32_HAVE_SPI6 - bool - -config STM32_HAVE_SAIPLL - bool - -config STM32_HAVE_I2SPLL - bool - -config STM32_HAVE_OPAMP1 - bool - -config STM32_HAVE_OPAMP2 - bool - -config STM32_HAVE_OPAMP3 - bool - -config STM32_HAVE_OPAMP4 - bool - -config STM32_HAVE_OPAMP5 - bool - -config STM32_HAVE_OPAMP6 - bool - -config STM32_HAVE_IOCOMPENSATION - bool - -config STM32_HAVE_ICACHE - bool - -config STM32_HAVE_ETHMAC - bool - -config STM32_HAVE_ETHRNET - bool - -config STM32_HAVE_LPUART - bool - -config STM32_HAVE_SAI - bool - -config STM32_HAVE_USB - bool - -config STM32_GPIO_HAVE_PORTD - bool - -config STM32_GPIO_HAVE_PORTE - bool - -config STM32_HAVE_GPIOF - bool - -config STM32_HAVE_GPIOG - bool - -config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - -config STM32_HAVE_OTA_PARTITION - bool - -config STM32_HAVE_CM4 - bool - -config STM32_HAVE_USART4 - bool - -config STM32_HAVE_USART5 - bool - -config STM32_HAVE_USART7 - bool - -config STM32_HAVE_USART8 - bool - -config STM32_HAVE_UART9 - bool - -config STM32_HAVE_USART10 - bool - -config STM32_HAVE_USART11 - bool - -config STM32_HAVE_UART12 - bool - -config STM32_HAVE_ADC1 - bool - default y if STM32_COMMON_LEGACY - -config STM32_ADC1 - bool "ADC1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 - select STM32_ADC if !ARCH_CHIP_STM32U5 - select STM32_HAVE_ADC1_DMA if STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC1_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC2 - bool "ADC2" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 - select STM32_ADC - select STM32_HAVE_ADC2_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC2_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC3 - bool "ADC3" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 - select STM32_ADC - select STM32_HAVE_ADC3_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) - select STM32_HAVE_ADC3_DMA if ARCH_CHIP_STM32F7 && STM32_DMA2 - -config STM32_ADC4 - bool "ADC4" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 - select STM32_ADC if STM32_COMMON_LEGACY - select STM32_HAVE_ADC4_DMA if STM32_COMMON_LEGACY && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) - -config STM32_COMP1 - bool "COMP1" - depends on STM32_HAVE_COMP1 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP1 - -config STM32_COMP2 - bool "COMP2" - depends on STM32_HAVE_COMP2 - select STM32_COMP if STM32_COMMON_LEGACY && STM32_HAVE_COMP2 - -config STM32_CORDIC - bool "CORDIC Accelerator" - depends on (STM32_COMMON_LEGACY && STM32_HAVE_CORDIC && MATH_CORDIC_USE_Q31) || ARCH_CHIP_STM32U5 - -config STM32_BKP - bool "BKP" - depends on (STM32_COMMON_LEGACY && STM32_STM32F10XX) || STM32_COMMON_F0_L0_G0_C0 - -config STM32_BKPSRAM - bool "Enable BKP RAM Domain" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select STM32_PWR if ARCH_CHIP_STM32H7 - -config STM32_CAN1 - bool "CAN1" - depends on STM32_HAVE_CAN1 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN2 - bool "CAN2" - depends on STM32_HAVE_CAN2 - select STM32_CAN - select CAN if !STM32_COMMON_LEGACY - -config STM32_CAN3 - bool "CAN3" - depends on STM32_HAVE_CAN3 - select STM32_CAN - select CAN - -config STM32_AES - bool "128-bit AES" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32L4) && STM32_HAVE_AES || ARCH_CHIP_STM32U5 - select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST - -config STM32_CEC - bool "CEC" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_VALUELINE || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_CEC || ARCH_CHIP_STM32F7 - -config STM32_CRC - bool "CRC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB - -config STM32_CRS - bool "CRS (Clock Recovery System)" - depends on STM32_HAVE_CRS - -config STM32_CRYP - bool "CRYP" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_HAVE_CRYP || STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_HASH - -config STM32_DMA1 - bool "DMA1" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32WB - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMA2 - bool "DMA2" - depends on STM32_HAVE_DMA2 - select STM32_DMA - select ARCH_DMA - select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - -config STM32_DMAMUX1 - bool "DMAMUX1" - depends on STM32_HAVE_DMAMUX - select STM32_DMAMUX - -config STM32_DAC1 - bool "DAC1" - depends on STM32_HAVE_DAC1 - select STM32_DAC if !ARCH_CHIP_STM32U5 - -config STM32_DAC2 - bool "DAC2" - depends on STM32_HAVE_DAC2 - select STM32_DAC - -config STM32_DCMI - bool "DCMI" - depends on STM32_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32_DSIHOST - bool "DSIHOST" - depends on STM32_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI DSI - compliant displays. - -config STM32_ETHMAC - bool "Ethernet MAC" - depends on STM32_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32_HAVE_PHY_POLLED if !STM32_COMMON_LEGACY - -config STM32_FDCAN1 - bool "FDCAN1" - depends on STM32_HAVE_FDCAN1 - select STM32_FDCAN if !ARCH_CHIP_STM32U5 - -config STM32_FDCAN2 - bool "FDCAN2" - depends on STM32_HAVE_FDCAN2 - select STM32_FDCAN - -config STM32_FDCAN3 - bool "FDCAN3" - depends on STM32_HAVE_FDCAN3 - select STM32_FDCAN - -config STM32_FSMC - bool "FSMC" - depends on STM32_HAVE_FSMC - -config STM32_FMC - bool "FMC" - depends on STM32_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32_FMAC - bool "FMAC (Filter Math Accelerator)" - depends on STM32_HAVE_FMAC - -config STM32_HASH - bool "HASH" - depends on STM32_HAVE_HASH - select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH - -config STM32_JPEG - bool "JPEG" - depends on STM32_HAVE_JPEG - ---help--- - The JPEG codec provides a hardware compressor and decompressor of JPEG - images with full management of JPEG headers. - -config STM32_I2C1 - bool "I2C1" - depends on STM32_HAVE_I2C1 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB - -config STM32_I2C2 - bool "I2C2" - depends on STM32_HAVE_I2C2 - select STM32_I2C - -config STM32_I2C3 - bool "I2C3" - depends on STM32_HAVE_I2C3 - select STM32_I2C - select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 - -config STM32_LPTIM1 - bool "LPTIM1" - depends on STM32_HAVE_LPTIM1 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPUART1 - bool "LPUART1" - depends on STM32_HAVE_LPUART1 - select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY - select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART - -config STM32_VREFINT - bool "Enable VREFINT" - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - depends on STM32_HAVE_USART8 - select STM32_USART - -config STM32_LTDC - bool "LTDC" - depends on STM32_HAVE_LTDC - select FB - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F429 and STM32F439 devices. It is a standard parallel - video interface (HSYNC, VSYNC, etc.) for controlling TFT - LCD displays. - -config STM32_DMA2D - bool "DMA2D" - depends on STM32_HAVE_DMA2D - select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32F429 and STM32F439 devices. - -config STM32_RTC - bool "RTC" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32L5 || ARCH_CHIP_STM32WB - select RTC if !ARCH_CHIP_STM32L5 - -config STM32_OTGFS - bool "OTG FS" - depends on STM32_HAVE_OTGFS - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGHS - bool "OTG HS" - depends on (STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX)) || (ARCH_CHIP_STM32H7 && EXPERIMENTAL) || (ARCH_CHIP_STM32U5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX)) - select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST - -config STM32_OTGFSHS - bool "OTG FS/HS" - depends on ARCH_CHIP_STM32F7 - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32_PWR - bool "PWR" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_L5_U5 || ARCH_CHIP_STM32WB - -config STM32_QSPI - bool "QSPI (QUADSPI)" - depends on STM32_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -config STM32_RNG - bool "RNG" - depends on STM32_HAVE_RNG - select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 - -config STM32_SDIO - bool "SDIO" - depends on (STM32_COMMON_LEGACY && !STM32_CONNECTIVITYLINE && !STM32_VALUELINE) || (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_SDIO) - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - -config STM32_SPI1 - bool "SPI1" - depends on STM32_HAVE_SPI1 - select SPI if !ARCH_CHIP_STM32WL5 - select STM32_SPI - -config STM32_SPI2 - bool "SPI2" - depends on STM32_HAVE_SPI2 - select SPI - select STM32_SPI - -config STM32_SPI3 - bool "SPI3" - depends on STM32_HAVE_SPI3 - select SPI - select STM32_SPI - -config STM32_I2S1 - bool "I2S1" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 - select STM32_I2S - -config STM32_I2S2 - bool "I2S2" - depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 - select STM32_I2S - -config STM32_I2S3 - bool "I2S3" - depends on STM32_HAVE_I2S3 - select I2S if STM32_COMMON_LEGACY - select STM32_I2S - -config STM32_SPI2S2 - bool "SPI2S2" - depends on STM32_HAVE_SPI2S2 - select STM32_SPI - -config STM32_SPDIFRX - bool "SPDIFRX" - depends on ARCH_CHIP_STM32F7 - -config STM32_SPI4 - bool "SPI4" - depends on STM32_HAVE_SPI4 - select SPI - select STM32_SPI - -config STM32_SPI5 - bool "SPI5" - depends on STM32_HAVE_SPI5 - select SPI - select STM32_SPI - -config STM32_SPI6 - bool "SPI6" - depends on STM32_HAVE_SPI6 - select SPI - select STM32_SPI - -config STM32_SYSCFG - bool "SYSCFG" - depends on STM32_HAVE_SYSCFG - default y - -config STM32_TIM1 - bool "TIM1" - depends on STM32_HAVE_TIM1 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM2 - bool "TIM2" - depends on STM32_HAVE_TIM2 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM3 - bool "TIM3" - depends on STM32_HAVE_TIM3 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM4 - bool "TIM4" - depends on STM32_HAVE_TIM4 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM5 - bool "TIM5" - depends on STM32_HAVE_TIM5 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM6 - bool "TIM6" - depends on STM32_HAVE_TIM6 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM7 - bool "TIM7" - depends on STM32_HAVE_TIM7 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM8 - bool "TIM8" - depends on STM32_HAVE_TIM8 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM9 - bool "TIM9" - depends on STM32_HAVE_TIM9 - select STM32_TIM - -config STM32_TIM10 - bool "TIM10" - depends on STM32_HAVE_TIM10 - select STM32_TIM - -config STM32_TIM11 - bool "TIM11" - depends on STM32_HAVE_TIM11 - select STM32_TIM - -config STM32_TIM12 - bool "TIM12" - depends on STM32_HAVE_TIM12 - select STM32_TIM - -config STM32_TIM13 - bool "TIM13" - depends on STM32_HAVE_TIM13 - select STM32_TIM - -config STM32_TIM14 - bool "TIM14" - depends on STM32_HAVE_TIM14 - select STM32_TIM - -config STM32_TIM15 - bool "TIM15" - depends on STM32_HAVE_TIM15 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5) - -config STM32_TIM16 - bool "TIM16" - depends on STM32_HAVE_TIM16 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TIM17 - bool "TIM17" - depends on STM32_HAVE_TIM17 - select STM32_TIM if !(ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB) - -config STM32_TSC - bool "TSC" - depends on STM32_HAVE_TSC - -config STM32_USART1 - bool "USART1" - depends on STM32_HAVE_USART1 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART2 - bool "USART2" - depends on STM32_HAVE_USART2 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART3 - bool "USART3" - depends on STM32_HAVE_USART3 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART4 - bool "UART4" - depends on STM32_HAVE_UART4 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART5 - bool "UART5" - depends on STM32_HAVE_UART5 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USART6 - bool "USART6" - depends on STM32_HAVE_USART6 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART7 - bool "UART7" - depends on STM32_HAVE_UART7 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_UART8 - bool "UART8" - depends on STM32_HAVE_UART8 - select STM32_USART - select ARCH_HAVE_SERIAL_TERMIOS if !STM32_COMMON_LEGACY && !STM32_COMMON_F0_L0_G0_C0 - select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 - -config STM32_USB - bool "USB Device" - depends on STM32_HAVE_USBDEV - select USBDEV - -config STM32_USBFS - bool "USB Full Speed Device" - depends on STM32_HAVE_USBFS - select USBDEV - select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 - -config STM32_LCD - bool "Segment LCD" - depends on STM32_HAVE_LCD - select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD - -config STM32_IWDG - bool "IWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 - select WATCHDOG - -config STM32_WWDG - bool "WWDG" - depends on STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - select WATCHDOG if !ARCH_CHIP_STM32U5 - -config STM32_ADC - bool - -config STM32_DAC - bool - -config STM32_DMA - bool - select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX - select STM32_DMAMUX if ARCH_CHIP_STM32WB - -config STM32_DMAMUX - bool - -config STM32_SPI - bool - -config STM32_SPI_DMA - bool "SPI DMA" - depends on STM32_SPI_CORE_DMA_CAPABLE - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_I2S - bool - select STM32_SPI_DMA if STM32_COMMON_LEGACY - select STM32_SPI_DMA if ARCH_CHIP_STM32F7 - -config STM32_I2C - bool - -config STM32_CAN - bool - -config STM32_FDCAN - bool - select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 - select NET_CAN_EXTID if ARCH_CHIP_STM32H7 - select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 - -config STM32_TIM - bool - -config STM32_PWM - bool - -config STM32_COMP - bool "COMP" - depends on STM32_HAVE_COMP - select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP - -config STM32_OPAMP - bool "OPAMP" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32U5 - -config STM32_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - depends on STM32_HAVE_IOCOMPENSATION - select STM32_CSI if ARCH_CHIP_STM32H7 - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - depends on (STM32_COMMON_LEGACY && ((STM32_STM32F20XX || STM32_STM32F4XXX) && STM32_FLASH_DCACHE)) || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR)) - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -config STM32_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - depends on STM32_COMMON_LEGACY && (STM32_STM32F20XX || STM32_STM32F4XXX) || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 if STM32_COMMON_LEGACY - default y - ---help--- - Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled - on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch - properly and enabling this option may interfere with ADC accuracy. - -config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config STM32_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA - default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32_EXTERNAL_RAM - bool "External RAM on FSMC/FMC" - depends on (STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC)) || (ARCH_CHIP_STM32F7 && STM32_FMC) - select ARCH_HAVE_HEAP2 if STM32_COMMON_LEGACY && (STM32_FSMC || STM32_FMC) - select ARCH_HAVE_HEAP2 if ARCH_CHIP_STM32F7 && STM32_FMC - ---help--- - In addition to internal SRAM, external RAM may be available through the FSMC/FMC. - -config STM32_TICKLESS_TIMER - int "Tickless hardware timer" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 2 - range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32_TICKLESS_CHANNEL - int "Tickless timer channel" - depends on SCHED_TICKLESS - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -config STM32_ONESHOT - bool "TIM one-shot wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32_FREERUN - bool "TIM free-running wrapper" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 - default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - depends on STM32_ONESHOT - depends on (STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB - default 1 - range 1 8 - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32_PWM_LL_OPS - bool "PWM low-level operations" - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - ---help--- - Enable low-level PWM ops. - -config STM32_TIM1_PWM - bool "TIM1 PWM" - depends on STM32_TIM1 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM1_MODE - int "TIM1 Mode" - depends on STM32_TIM1_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM1_LOCK - int "TIM1 Lock Level Configuration" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32_TIM1_TDTS - int "TIM1 t_DTS Division" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - depends on STM32_TIM1_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -config STM32_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - depends on STM32_TIM1_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - depends on STM32_TIM1_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM1_CHMODE - int "TIM1 Channel Mode" - depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_PWM - bool "TIM2 PWM" - depends on STM32_TIM2 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM2_MODE - int "TIM2 Mode" - depends on STM32_TIM2_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - depends on STM32_TIM2_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - depends on STM32_TIM2_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM2_CHMODE - int "TIM2 Channel Mode" - depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_PWM - bool "TIM3 PWM" - depends on STM32_TIM3 - depends on STM32_TIM_PWM_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM3_MODE - int "TIM3 Mode" - depends on STM32_TIM3_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - depends on STM32_TIM3_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - depends on STM32_TIM3_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM3_CHMODE - int "TIM3 Channel Mode" - depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_PWM - bool "TIM4 PWM" - depends on STM32_TIM4 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM4_MODE - int "TIM4 Mode" - depends on STM32_TIM4_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - depends on STM32_TIM4_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - depends on STM32_TIM4_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM4_CHMODE - int "TIM4 Channel Mode" - depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_PWM - bool "TIM5 PWM" - depends on STM32_TIM5 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM5_MODE - int "TIM5 Mode" - depends on STM32_TIM5_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - depends on STM32_TIM5_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - depends on STM32_TIM5_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM5_CHMODE - int "TIM5 Channel Mode" - depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_PWM - bool "TIM8 PWM" - depends on STM32_TIM8 - depends on STM32_TIM_PWM_NO_F0_COMMON - depends on !STM32_COMMON_LEGACY || STM32_TIM - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM8_MODE - int "TIM8 Mode" - depends on STM32_TIM8_PWM - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32_TIM8_LOCK - int "TIM8 Lock Level Configuration" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32_TIM8_TDTS - int "TIM8 t_DTS Division" - depends on STM32_TIM8_PWM - depends on STM32_TIM_PWM_ADVANCED_COMMON - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 3. - -config STM32_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 3 output. - -config STM32_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - depends on STM32_TIM8_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 3 Complementary Output. - -config STM32_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM_PWM_ADVANCED_COMMON - ---help--- - Enables channel 4. - -config STM32_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - depends on STM32_TIM8_PWM - depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) - ---help--- - Enables channel 4 output. - -config STM32_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 - ---help--- - Enables channel 5 (not available externally) - -config STM32_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 5 output. - -config STM32_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN - depends on (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_F7_H7_H5 - ---help--- - Enables channel 6 (not available externally) - -config STM32_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 - depends on STM32_TIM_PWM_INTERNAL_COMMON - ---help--- - Enables channel 6 output. - -config STM32_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32_TIM8_CHMODE - int "TIM8 Channel Mode" - depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if STM32_TIM_PWM_CHMODE_EXTENDED_COMMON - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 5 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_PWM - bool "TIM9 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 2. - -config STM32_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - depends on STM32_TIM9_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) - ---help--- - Enables channel 2 output. - -config STM32_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM9_CAP - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM9_CHMODE - int "TIM9 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_PWM - bool "TIM10 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - depends on STM32_TIM10_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM10_CAP - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM10_CHMODE - int "TIM10 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_PWM - bool "TIM11 PWM" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) - ---help--- - Enables channel 1. - -config STM32_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - depends on STM32_TIM11_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) - ---help--- - Enables channel 1 output. - -config STM32_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM11_CAP - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM11_CHMODE - int "TIM11 Channel Mode" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) - default 6 - range 0 11 if STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_PWM - bool "TIM12 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - depends on STM32_TIM12_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - range 1 2 if !STM32_COMMON_LEGACY || !STM32_TIM12_CAP - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM12_CHMODE - int "TIM12 Channel Mode" - depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 9 if ARCH_CHIP_STM32F7 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_PWM - bool "TIM13 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - depends on STM32_TIM13_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM13_CAP - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM13_CHMODE - int "TIM13 Channel Mode" - depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_PWM - bool "TIM14 PWM" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - depends on STM32_TIM14_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_TIM_PWM_INTERNAL_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_COMMON_LEGACY && STM32_TIM) || ARCH_CHIP_STM32H7)) - default 1 - range 1 4 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - range 1 1 if !STM32_COMMON_LEGACY || !STM32_TIM14_CAP - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM14_CHMODE - int "TIM14 Channel Mode" - depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_COMMON_F0_L0_G0_C0 - default 6 - range 0 11 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON || ARCH_CHIP_STM32F7 - range 0 1 if STM32_COMMON_F0_L0_G0_C0 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_PWM - bool "TIM15 PWM" - depends on STM32_TIM15 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM15_LOCK - int "TIM15 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32_TIM15_TDTS - int "TIM15 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -config STM32_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - depends on STM32_TIM_PWM_INTERNAL_COMMON || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN - ---help--- - Enables channel 1 Complementary Output. - -config STM32_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 2. - -config STM32_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 11 if ARCH_CHIP_STM32L4 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || STM32_COMMON_H7_H5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - depends on STM32_TIM15_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 2 output. - -config STM32_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 - depends on STM32_TIM_PWM_SINGLECHAN_COMMON - ---help--- - Enables channel 2 Complementary Output. - -config STM32_TIM15_CHMODE - int "TIM15 Channel Mode" - depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 9 if (STM32_COMMON_LEGACY && STM32_HAVE_IP_TIMERS_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 - range 0 7 if STM32_TIM_PWM_CHMODE_LEGACY_COMMON - range 0 3 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_PWM - bool "TIM16 PWM" - depends on STM32_TIM16 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM16_LOCK - int "TIM16 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32_TIM16_TDTS - int "TIM16 t_DTS division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -config STM32_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - depends on STM32_TIM16_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM16_CHMODE - int "TIM16 Channel Mode" - depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_PWM - bool "TIM17 PWM" - depends on STM32_TIM17 - depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 - select STM32_PWM if STM32_TIM_PWM_STM32PWM_COMMON - select PWM if ARCH_CHIP_STM32L5 - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_TIM17_LOCK - int "TIM17 Lock Level Configuration" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32_TIM17_TDTS - int "TIM17 t_DTS Division" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -config STM32_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 1. - -config STM32_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - depends on STM32_TIM17_PWM - depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_TIM_PWM_SINGLECHAN_COMMON) - ---help--- - Enables channel 1 output. - -config STM32_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32_TIM17_CHMODE - int "TIM17 Channel Mode" - depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN - default 0 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - default 6 - range 0 7 if STM32_TIM_PWM_CHMODE_TIM16_17_EXTENDED_COMMON - range 0 1 if STM32_TIM_PWM_CHMODE_LIMITED_COMMON - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - depends on STM32_PWM_MULTICHAN_CAPABLE - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32_PULSECOUNT - bool - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32_TIM1_PULSECOUNT - bool "TIM1 pulse count" - depends on STM32_TIM1 - depends on STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32_TIM1_PULSECOUNT - -config STM32_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -config STM32_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - depends on !STM32_COMMON_F0_L0_G0_C0 - -endif # STM32_TIM1_PULSECOUNT - -config STM32_TIM8_PULSECOUNT - bool "TIM8 pulse count" - depends on STM32_TIM8 - depends on STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 - select STM32_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32_TIM8_PULSECOUNT - -config STM32_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32_TIM8_PULSECOUNT - -config STM32_PWM_TRGO - bool "TIM PWM TRGO support" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) - ---help--- - Enable TRGO support for PWM driver - -config STM32_TIM1_ADC - bool "TIM1 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM1 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM2_ADC - bool "TIM2 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM2 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM3_ADC - bool "TIM3 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM3 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM4_ADC - bool "TIM4 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM4 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM5_ADC - bool "TIM5 ADC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_ADC) || (ARCH_CHIP_STM32F7 && STM32_TIM5 && STM32_ADC) - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIM8_ADC - bool "TIM8 ADC" - depends on ((STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC && STM32_TIM8 - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_HAVE_ADC1_TIMER - bool - -config STM32_HAVE_ADC2_TIMER - bool - -config STM32_HAVE_ADC3_TIMER - bool - -config STM32_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - depends on STM32_ADC1_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - depends on STM32_ADC1_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - depends on STM32_ADC2_TIMER_FREQ_CAPABLE - default 100 - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - depends on STM32_ADC2_TIMTRIG_CAPABLE - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - depends on STM32_ADC3_TIMER_CAPABLE - default 100 - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - depends on STM32_ADC3_TIMER_CAPABLE && !ARCH_CHIP_STM32L4 - default 0 - range 0 5 if STM32_ADC_TIMTRIG_TRGO2_COMMON - range 0 4 if STM32_ADC_TIMTRIG_TRGO_COMMON - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32_TIM1_DAC - bool "TIM1 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM1 && STM32_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM2_DAC - bool "TIM2 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM2 && STM32_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM3_DAC - bool "TIM3 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM3 && STM32_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM4_DAC - bool "TIM4 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM4 && STM32_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM5_DAC - bool "TIM5 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM5 && STM32_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM6_DAC - bool "TIM6 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM6 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM6 && STM32_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM7_DAC - bool "TIM7 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM7 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM7 && STM32_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM8_DAC - bool "TIM8 DAC" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 && STM32_DAC || (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_TIM8 && STM32_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM9_DAC - bool "TIM9 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM9 && STM32_DAC) - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM10_DAC - bool "TIM10 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM10 && STM32_DAC) - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM11_DAC - bool "TIM11 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM11 && STM32_DAC) - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM12_DAC - bool "TIM12 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM12 && STM32_DAC) - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM13_DAC - bool "TIM13 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM13 && STM32_DAC) - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM14_DAC - bool "TIM14 DAC" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 && STM32_DAC) || (ARCH_CHIP_STM32F7 && STM32_TIM14 && STM32_DAC) - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -config STM32_TIM1_CAP - bool "TIM1 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM1_CLOCK - int "TIM1 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM2_CAP - bool "TIM2 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM2_CLOCK - int "TIM2 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM3_CAP - bool "TIM3 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM3_CLOCK - int "TIM3 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM4_CAP - bool "TIM4 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM4_CLOCK - int "TIM4 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM5_CAP - bool "TIM5 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM5_CLOCK - int "TIM5 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM8_CAP - bool "TIM8 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM8_CLOCK - int "TIM8 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM9_CAP - bool "TIM9 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM10_CAP - bool "TIM10 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM11_CAP - bool "TIM11 Capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CAP - bool "TIM12 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM12_CLOCK - int "TIM12 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM13_CAP - bool "TIM13 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM13_CLOCK - int "TIM13 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM14_CAP - bool "TIM14 Capture" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 - select STM32_CAP if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32_TIM14_CLOCK - int "TIM14 work frequency for capture" - depends on (STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) - default 1000000 if STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CAP - default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -config STM32_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output polarity - -config STM32_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 output IDLE - -config STM32_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output polarity - -config STM32_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 output IDLE - -config STM32_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output polarity - -config STM32_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 output IDLE - -config STM32_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output polarity - -config STM32_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 4 output IDLE - -config STM32_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output polarity - -config STM32_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 5 output IDLE - -config STM32_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output polarity - -config STM32_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT - default 0 - range 0 1 - ---help--- - TIM1 Channel 6 output IDLE - -config STM32_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output polarity - -config STM32_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 1 output IDLE - -config STM32_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output polarity - -config STM32_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 2 output IDLE - -config STM32_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output polarity - -config STM32_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 3 output IDLE - -config STM32_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output polarity - -config STM32_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT - default 0 - range 0 1 - ---help--- - TIM2 Channel 4 output IDLE - -config STM32_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output polarity - -config STM32_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 1 output IDLE - -config STM32_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output polarity - -config STM32_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 2 output IDLE - -config STM32_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output polarity - -config STM32_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 3 output IDLE - -config STM32_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output polarity - -config STM32_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT - default 0 - range 0 1 - ---help--- - TIM3 Channel 4 output IDLE - -config STM32_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output polarity - -config STM32_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 1 output IDLE - -config STM32_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output polarity - -config STM32_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 2 output IDLE - -config STM32_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output polarity - -config STM32_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 3 output IDLE - -config STM32_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output polarity - -config STM32_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT - default 0 - range 0 1 - ---help--- - TIM4 Channel 4 output IDLE - -config STM32_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output polarity - -config STM32_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 1 output IDLE - -config STM32_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output polarity - -config STM32_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 2 output IDLE - -config STM32_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output polarity - -config STM32_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 3 output IDLE - -config STM32_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output polarity - -config STM32_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT - default 0 - range 0 1 - ---help--- - TIM5 Channel 4 output IDLE - -config STM32_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output polarity - -config STM32_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 output IDLE - -config STM32_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output polarity - -config STM32_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 output IDLE - -config STM32_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output polarity - -config STM32_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 output IDLE - -config STM32_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output polarity - -config STM32_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 4 output IDLE - -config STM32_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output polarity - -config STM32_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 5 output IDLE - -config STM32_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output polarity - -config STM32_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT - default 0 - range 0 1 - ---help--- - TIM8 Channel 6 output IDLE - -config STM32_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output polarity - -config STM32_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 1 output IDLE - -config STM32_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output polarity - -config STM32_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT - default 0 - range 0 1 - ---help--- - TIM9 Channel 2 output IDLE - -config STM32_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output polarity - -config STM32_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT - default 0 - range 0 1 - ---help--- - TIM10 Channel 1 output IDLE - -config STM32_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output polarity - -config STM32_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT - default 0 - range 0 1 - ---help--- - TIM11 Channel 1 output IDLE - -config STM32_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output polarity - -config STM32_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 1 output IDLE - -config STM32_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output polarity - -config STM32_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT - default 0 - range 0 1 - ---help--- - TIM12 Channel 2 output IDLE - -config STM32_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output polarity - -config STM32_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT - default 0 - range 0 1 - ---help--- - TIM13 Channel 1 output IDLE - -config STM32_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output polarity - -config STM32_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT - default 0 - range 0 1 - ---help--- - TIM14 Channel 1 output IDLE - -config STM32_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output polarity - -config STM32_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 output IDLE - -config STM32_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output polarity - -config STM32_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 output IDLE - -config STM32_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT - default 0 - range 0 1 - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output polarity - -config STM32_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT - default 0 - range 0 1 - ---help--- - TIM16 Channel 1 output IDLE - -config STM32_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output polarity - -config STM32_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - depends on STM32_COMMON_LEGACY && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT - default 0 - range 0 1 - ---help--- - TIM17 Channel 1 output IDLE - -config STM32_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_V1_BASIC || (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - depends on STM32_ADC - default 1 if STM32_COMMON_F0_L0_G0_C0 && !STM32_ADC1_DMA - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - depends on STM32_ADC - ---help--- - Do not start conversion when opening ADC device. - -config STM32_ADC_NOIRQ - bool "Do not use default ADC interrupts" - depends on STM32_ADC - ---help--- - Do not use default ADC interrupts handlers. - -config STM32_ADC_LL_OPS - bool "ADC low-level operations" - depends on STM32_ADC - ---help--- - Enable low-level ADC ops. - -config STM32_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32_ADC_OVERSAMPLE - bool "Enable ADC hardware oversampling support" - depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32_ADC_OVERSAMPLE - -config STM32_ADC_TOVS - bool "Enable triggered oversampling (CFGR2.TOVS)" - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32_ADC_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2x - 1 -> 4x - 2 -> 8x - ... - 7 -> 256x - -config STM32_ADC_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32_ADC_OVERSAMPLE - -config STM32_ADC1_DMA - bool "ADC1 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_HAVE_ADC1_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC1_SCAN - bool "ADC1 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) - default STM32_ADC1_DMA - -config STM32_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC1_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC2_DMA - bool "ADC2 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_HAVE_ADC2_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC2_SCAN - bool "ADC2 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) - default STM32_ADC2_DMA - -config STM32_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC3_DMA - bool "ADC3 DMA" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_HAVE_ADC3_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC3_SCAN - bool "ADC3 scan mode" - depends on (STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) - default STM32_ADC3_DMA - -config STM32_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32_COMMON_LEGACY && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA - default 1 if ARCH_CHIP_STM32L4 - default 0 - range 0 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 3 - range 1 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - default 0 - range 0 4 - ---help--- - Support for ADC1 injected channels. - -config STM32_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - default 0 - range 0 4 - ---help--- - Support for ADC2 injected channels. - -config STM32_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - default 0 - range 0 4 - ---help--- - Support for ADC3 injected channels. - -config STM32_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_ADC1_TIMER - ---help--- - Enable EXTSEL for ADC1. - -config STM32_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_HAVE_ADC2_TIMER - ---help--- - Enable EXTSEL for ADC2. - -config STM32_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_HAVE_ADC3_TIMER - ---help--- - Enable EXTSEL for ADC3. - -config STM32_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) - ---help--- - Enable JEXTSEL for ADC1. - -config STM32_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) - ---help--- - Enable JEXTSEL for ADC2. - -config STM32_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on ((STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) - ---help--- - Enable JEXTSEL for ADC3. - -config STM32_USART - bool - -config USART1_RS485 - bool "RS-485 on USART1" - depends on STM32_USART1 && USART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -if USART1_RS485 - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART1_RS485 - -config USART1_RXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool - depends on STM32_USART1 && USART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && ((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2) || ARCH_CHIP_STM32F7 && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART2_RS485 - bool "RS-485 on USART2" - depends on STM32_USART2 && USART2_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -if USART2_RS485 - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART2_RS485 - -config USART2_RXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool - depends on STM32_USART2 && USART2_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART3_RS485 - bool "RS-485 on USART3" - depends on STM32_USART3 && USART3_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -if USART3_RS485 - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART3_RS485 - -config USART3_RXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool - depends on STM32_USART3 && USART3_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART4_RS485 - bool "RS-485 on UART4" - depends on STM32_UART4 && UART4_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -if UART4_RS485 - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART4_RS485 - -config UART4_RXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool - depends on STM32_UART4 && UART4_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART5_RS485 - bool "RS-485 on UART5" - depends on STM32_UART5 && UART5_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -if UART5_RS485 - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART5_RS485 - -config UART5_RXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool - depends on STM32_UART5 && UART5_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config USART6_RS485 - bool "RS-485 on USART6" - depends on STM32_USART6 && USART6_SERIALDRIVER - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -if USART6_RS485 - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # USART6_RS485 - -config USART6_RXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool - depends on STM32_USART6 && USART6_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA2 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART7_RS485 - bool "RS-485 on UART7" - depends on STM32_UART7 && UART7_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -if UART7_RS485 - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART7_RS485 - -config UART7_RXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool - depends on STM32_UART7 && UART7_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config UART8_RS485 - bool "RS-485 on UART8" - depends on STM32_UART8 && UART8_SERIALDRIVER - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -if UART8_RS485 - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # UART8_RS485 - -config UART8_RXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool - depends on STM32_UART8 && UART8_SERIALDRIVER - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -if LPUART1_RS485 - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -endif # LPUART1_RS485 - -config LPUART1_RXDMA - bool - depends on STM32_LPUART1 && LPUART1_SERIALDRIVER - depends on STM32_COMMON_LEGACY && STM32_DMA1 || STM32_COMMON_L4_L5_U5 && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) || ARCH_CHIP_STM32H5 && (STM32_DMA1 || STM32_DMA2) || ARCH_CHIP_STM32WB && STM32_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config STM32_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - depends on STM32_USART && SERIAL_RXDMA - range 32 4096 - default 32 - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." +source "arch/arm/src/common/stm32/Kconfig.ltdc" +endmenu # LTDC Configuration + +menu "Memory Configuration" +source "arch/arm/src/common/stm32/Kconfig.memory" +endmenu # Memory Configuration + +menu "QSPI/OCTOSPI Configuration" + depends on STM32_QSPI || STM32_QSPI1 || STM32_OCTOSPI1 || STM32_OCTOSPI2 +source "arch/arm/src/common/stm32/Kconfig.qspi" +endmenu # QSPI/OCTOSPI Configuration + +menu "RTC Configuration" + depends on STM32_RTC +source "arch/arm/src/common/stm32/Kconfig.rtc" +endmenu # RTC Configuration + +menu "SAI Configuration" +source "arch/arm/src/common/stm32/Kconfig.sai" +endmenu # SAI Configuration + +menu "SDIO/SDMMC Configuration" + depends on STM32_SDIO || STM32_SDMMC +source "arch/arm/src/common/stm32/Kconfig.sdio" +endmenu # SDIO/SDMMC Configuration + +menu "COMP Configuration" + depends on STM32_COMP +source "arch/arm/src/common/stm32/Kconfig.comp" +endmenu # COMP Configuration + +menu "DTS Configuration" + depends on STM32_DTS +source "arch/arm/src/common/stm32/Kconfig.dts" +endmenu # DTS Configuration + +menu "U[S]ART Configuration" depends on STM32_USART - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32_USART - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32_USART - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32_USART_BREAKS - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32_USART_SINGLEWIRE - bool "Single Wire Support" - depends on STM32_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32 serial driver. - -config STM32_PM_SERIAL_ACTIVITY - int "PM serial activity" - depends on PM - depends on STM32_USART - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure LPUART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER - -config USART1_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART1 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER - -config USART2_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART2 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER - -config USART3_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART3 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER - -config UART4_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART4 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER - -config UART5_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART5 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER - -config USART6_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART6 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER - -config UART7_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART7 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER - -config UART8_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART8 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER - -config UART9_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART9 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER - -config USART10_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART10 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER - -config USART11_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure USART11 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER - -config UART12_UNCONFIG_DIR_ON_CLOSE - bool "Unconfigure UART12 DIR pin on close" - depends on STM32_COMMON_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 - -config STM32_SPI_INTERRUPTS - bool "Interrupt driver SPI" - depends on STM32_SPI - depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32_SPI1_DMA - bool "SPI1 DMA" - depends on STM32_SPI && STM32_SPI1 - depends on STM32_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32_SPI_DMATHRESHOLD - int "SPI DMA threshold" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA - default 4 - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32_SPI2_DMA - bool "SPI2 DMA" - depends on STM32_SPI && STM32_SPI2 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32_SPI3_DMA - bool "SPI3 DMA" - depends on STM32_SPI && STM32_SPI3 - depends on STM32_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32_SPI4_DMA - bool "SPI4 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32_SPI5_DMA - bool "SPI5 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32_SPI6_DMA - bool "SPI6 DMA" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA - bool "SPI2S2 DMA" - depends on STM32_SPI2 && !STM32_SPI_INTERRUPT - select STM32_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with - STM32_SPI_INTERRUPT. - -config STM32_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -config STM32_I2S_MAXINFLIGHT - int "I2S queue size" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -config STM32_I2S3_DATALEN - int "Data width (bits)" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -config STM32_I2S1_MCK - bool "I2S1_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - TBD. - -config STM32_I2S1_RX - bool "Enable I2S1 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S receipt logic - -config STM32_I2S1_TX - bool "Enable I2S1 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - ---help--- - Enable I2S transmission logic - -config STM32_I2S1_DATALEN - int "I2S1 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S1 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S2_MCK - bool "I2S2_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - TBD. - -config STM32_I2S2_RX - bool "Enable I2S2 receiver" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S receipt logic - -config STM32_I2S2_TX - bool "Enable I2S2 transmitter" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - ---help--- - Enable I2S transmission logic - -config STM32_I2S2_DATALEN - int "I2S2 Data width (bits)" - depends on ARCH_CHIP_STM32F7 && STM32_I2S2 - default 16 - ---help--- - Data width in bits. This is a default value and may be changed via - the I2S interface. - -config STM32_I2S3_MCK - bool "I2S3_MCK" - depends on ARCH_CHIP_STM32F7 && STM32_I2S3 - ---help--- - TBD. - -#if STM32_I2S - -config STM32_I2S3_RX - bool "Enable I2S receiver" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S receipt logic - -config STM32_I2S3_TX - bool "Enable I2S transmitter" - depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) - ---help--- - Enable I2S transmission logic - -config STM32_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -config STM32_I2C_DYNTIMEO - bool "Use dynamic timeouts" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - -config STM32_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && STM32_I2C_DYNTIMEO - default 1000 - -config STM32_I2CTIMEOSEC - int "Timeout seconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C - default 0 - -config STM32_I2CTIMEOMS - int "Timeout Milliseconds" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - depends on (STM32_COMMON_FULL_FEATURED) && STM32_I2C && !STM32_I2C_DYNTIMEO - default 500 - -config STM32_BBSRAM - bool "BBSRAM File Support" - depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM - select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM - -config STM32_BBSRAM_FILES - int "Max Files to support in BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - default 4 - -config STM32_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - depends on STM32_COMMON_LEGACY && STM32_BKPSRAM || STM32_COMMON_F7_H7 && STM32_BKPSRAM && STM32_BBSRAM - -config STM32_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - -config STM32_RTC_MAGIC_REG - int "BKP register" - depends on STM32_RTC_MAGIC_CAPABLE - default 0 - range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER - range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32_RTC_MAGIC - hex "RTC Magic 1" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - depends on STM32_RTC_MAGIC_CAPABLE - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -if STM32_ETHMAC - -config STM32_PHYADDR - int "PHY address" - default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32_PHYINIT - bool "Board-specific PHY Initialization" - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32_MII - bool "Use MII interface" - ---help--- - Support Ethernet MII interface. - -config STM32_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -if !STM32_AUTONEG - -config STM32_ETHFD - bool "Full duplex" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32_ETH100MBPS - bool "100 Mbps" - ---help--- - If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -endif # !STM32_AUTONEG - -if STM32_AUTONEG - -config STM32_PHYSR - int "PHY Status Register Address (decimal)" - ---help--- - This must be provided if STM32_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -if !STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_SPEED - hex "PHY Speed Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32_PHYSR_MODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -endif # !STM32_PHYSR_ALTCONFIG - -if STM32_PHYSR_ALTCONFIG - -config STM32_PHYSR_ALTMODE - hex "PHY Mode Mask" - ---help--- - This must be provided if STM32_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32_PHYSR_100HD - hex "100Base-T Half Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32_PHYSR_10FD - hex "10Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32_PHYSR_100FD - hex "100Base-T Full Duplex Value" - ---help--- - This must be provided if STM32_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -endif # STM32_PHYSR_ALTCONFIG - -endif # STM32_AUTONEG - -config STM32_ETH_PTP - bool "Precision Time Protocol (PTP)" - ---help--- - Enables Precision Time Protocol (PTP) hardware timer. - -config STM32_ETH_ENHANCEDDESC - bool "Enable enhanced RX/TX descriptors" - depends on STM32_COMMON_LEGACY - default n - ---help--- - Enables double-length DMA descriptors that have space for packet - timestamps and checksum offloading. - -config STM32_ETH_PTP_GPIO - bool "PTP pulse-per-second output signal" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Enables pulse-per-second output on GPIO pin. - -config STM32_ETH_PTP_RTC_HIRES - bool "Use PTP timer as system high-resolution RTC" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP - default n - ---help--- - Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. - This provides high resolution timestamps to clock_gettime(). - Note that PTP timer is disabled when Ethernet interface is down or - being reset. During this time g_rtc_enabled is set to false and system - uses the lower resolution system tick counter. - -config STM32_ETH_TIMESTAMP_RX - bool "Hardware timestamping of received packets" - depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC - select ARCH_HAVE_NETDEV_TIMESTAMP - default n - ---help--- - Timestamp all received Ethernet packets. - Timestamp is available to application through SO_TIMESTAMP socket option. - -config STM32_RMII - bool - default !STM32_MII - -config STM32_ETHMAC_REGDEBUG - bool "Register-Level Debug" - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. - -endif # STM32_ETHMAC - -config STM32_USBHOST_REGDEBUG - bool "Register-Level Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Enable very low-level register access debug. - -config STM32_USBHOST_PKTDUMP - bool "Packet Dump Debug" - depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST - ---help--- - Dump all incoming and outgoing USB packets. - -config STM32_USBFS_REGDEBUG - bool "Register-Level Debug" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -menu "STM32_OTG_HS Configuration" - depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32_NO_ULPI - -config STM32_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS - -endchoice # "ULPI Selection" - -endmenu # STM32_OTG_HS Configuration - -menu "OTG_HS Configuration" - depends on ARCH_CHIP_STM32H7 && STM32_OTGHS - -config STM32_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32_OTGHS_NO_ULPI - -config STM32_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means - the OTG_HS peripheral must use the internal full-speed PHY and will - be limited to full-speed mode. - -config STM32_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice # "ULPI Selection" - -endmenu # OTG_HS Configuration - -menu "OTG Configuration" - depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) - -choice - prompt "STM32H7 OTGFS role" - depends on STM32_OTGFS - default STM32_OTGFS_USBDEV if USBDEV - default STM32_OTGFS_HOST if !USBDEV && USBHOST - -config STM32_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32_OTGHS - default STM32_OTGHS_USBDEV if USBDEV - -config STM32_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -config STM32_USBHOST - bool "Enable USB Host Support" - depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) - default n - select USBHOST - -menu "USB FS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST - -config STM32_OTGFS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGFS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGFS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGFS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGFS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG FS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB FS Host Configuration - -menu "USB HS Host Configuration" - depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST - -config STM32_OTGHS_RXFIFO_SIZE - int "Rx Packet Size" - default 128 - ---help--- - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) - -config STM32_OTGHS_NPTXFIFO_SIZE - int "Non-periodic Tx FIFO Size" - default 96 - ---help--- - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_PTXFIFO_SIZE - int "Periodic Tx FIFO size" - default 128 - ---help--- - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) - -config STM32_OTGHS_DESCSIZE - int "Descriptor Size" - default 128 - ---help--- - Maximum size to allocate for descriptor memory descriptor. Default: 128 - -config STM32_OTGHS_SOFINTR - bool "Enable SOF interrupts" - default n - ---help--- - Enable SOF interrupts. Why would you ever want to do that? - -config STM32_OTGHS_VBUS_CONTROL - bool "Enable VBus Control" - default y - ---help--- - Enable VBus control. Used when the board has VBus sensing and - a power switch for the OTG HS USB port. Disable this config - if the board lacks this USB VBus control circuitry. - -endmenu # USB HS Host Configuration - -config STM32_CAN1_BAUD - int "CAN1 BAUD" - depends on STM32_CAN1 - default 250000 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. - -config STM32_CAN2_BAUD - int "CAN2 BAUD" - depends on STM32_CAN2 - default 250000 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. - -config STM32_CAN3_BAUD - int "CAN3 BAUD" - depends on STM32_CAN3 - default 250000 - ---help--- - CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. - -config STM32_CAN_TSEG1 - int "TSEG1 quanta" - depends on STM32_CAN - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32_CAN_TSEG2 - int "TSEG2 quanta" - depends on STM32_CAN - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32_CAN_REGDEBUG - bool "CAN Register level debug" - depends on STM32_CAN && DEBUG_CAN_INFO - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_REGDEBUG - bool "FDCAN register-level debug" - depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - depends on STM32_FDCAN - -config STM32_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - -choice - prompt "FDCAN Loopback Mode" - depends on STM32_FDCAN_LOOPBACK - default STM32_FDCAN_LOOPBACK_INTERNAL - -config STM32_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - depends on ARCH_CHIP_STM32H7 && STM32_FDCAN - default STM32_FDCAN_LPWORK - -config STM32_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -if STM32_FDCAN1 - -config STM32_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -config STM32_FDCAN1_BITRATE - int "FDCAN1 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. - -config STM32_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 nominal bit timing" - -config STM32_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN1_AUTO_BIT_TIMING - -config STM32_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - depends on CAN_FD && STM32_FDCAN1_FD_BRS - default 2000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -comment "FDCAN1 data bit timing" - -config STM32_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING - -endif # STM32_FDCAN1 - -if STM32_FDCAN2 - -config STM32_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -config STM32_FDCAN2_BITRATE - int "FDCAN2 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. - -config STM32_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 automatic bit timing" - depends on ARCH_CHIP_STM32H5 - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) - based on bitrate. - -if !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 nominal bit timing" - -config STM32_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -endif # !STM32_FDCAN2_AUTO_BIT_TIMING - -config STM32_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - depends on CAN_FD && STM32_FDCAN2_FD_BRS - default 2000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -comment "FDCAN2 data bit timing" - -config STM32_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING - -endif # STM32_FDCAN2 - -if STM32_FDCAN3 - -choice - prompt "FDCAN3 frame format" - default STM32_FDCAN3_ISO11898_1 - -config STM32_FDCAN3_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32_FDCAN3_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN3 frame format - -choice - prompt "FDCAN3 mode" - default STM32_FDCAN3_CLASSIC - -config STM32_FDCAN3_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32_FDCAN3_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32_FDCAN3_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN3 mode - -config STM32_FDCAN3_LOOPBACK - bool "Enable FDCAN3 loopback mode" - default n - ---help--- - Enable the FDCAN3 local loopback mode for testing purposes. - -config STM32_FDCAN3_BITRATE - int "FDCAN3 bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. - -comment "FDCAN3 nominal bit timing" - -config STM32_FDCAN3_NTSEG1 - int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NTSEG2 - int "FDCAN3 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_NSJW - int "FDCAN3 synchronization jump width" - default 1 - range 1 128 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DBITRATE - int "FDCAN3 data bitrate" - depends on CAN_FD && STM32_FDCAN3_FD_BRS - default 2000000 - ---help--- - FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -if CAN_FD && STM32_FDCAN3_FD_BRS - -comment "FDCAN3 data bit timing" - -config STM32_FDCAN3_DTSEG1 - int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DTSEG2 - int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 if STM32_STM32G4XXX - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32_FDCAN3_DSJW - int "FDCAN3 fast synchronization jump width" - default 2 - range 1 15 if STM32_STM32G4XXX - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endif # CAN_FD && STM32_FDCAN3_FD_BRS - -endif # STM32_FDCAN3 - -if STM32_LTDC - -config STM32_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value. - -config STM32_LTDC_DITHER - bool "Dither support" - -config STM32_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - depends on ARCH_CHIP_STM32H7 - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while - the display is being refreshed. This configuration requires two - framebuffers: one active and one inactive. When the display - refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -if STM32_LTDC_DITHER - -config STM32_LTDC_DITHER_RED - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32_LTDC_DITHER_GREEN - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32_LTDC_DITHER_BLUE - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -endif # STM32_LTDC_DITHER - -config STM32_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -config STM32_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32_LTDC_L2 - -config STM32_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -endif # STM32_LTDC_L2 - -config STM32_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - Enabling color map support is necessary for LTDC L8 format. - -config STM32_FB_TRANSPARENCY - bool "Transparency color map support" - depends on STM32_FB_CMAP - default y - select FB_TRANSPARENCY - ---help--- - Enabling transparency color map support is necessary for LTDC L8 format. - -config STM32_LTDC_REGDEBUG - bool "LTDC Register level debug" - depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 - ---help--- - Output detailed register-level LTDC device debug information. - -endif # STM32_LTDC - -if STM32_DMA2D - -config STM32_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC/FMC. - -config STM32_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -config STM32_DMA2D_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 - default y - -config STM32_DMA2D_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 - default y - -config STM32_DMA2D_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 - default y - -config STM32_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32_LTDC_L1_RGB565 - default y - -config STM32_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32_LTDC_L1_ARGB4444 - default y - -config STM32_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32_LTDC_L1_ARGB15555 - default y - -config STM32_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32_LTDC_L1_RGB888 - default y - -config STM32_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32_LTDC_L1_ARGB8888 - default y - -config STM32_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - ---help--- - Output detailed register-level DMA2D device debug information. - -endif # STM32_DMA2D - -config STM32_QENCODER_DISABLE_EXTEND16BTIMERS - bool "Disable QEncoder timers extension from 16-bit to 32-bit" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Disable the extension of 16-bit timers to 32-bit via interrupt-based - overflow tracking. When enabled, timers will use their native hardware - counter width (16-bit or 32-bit). This reduces interrupt overhead but - limits the position range for 16-bit timers. - -config STM32_QENCODER_INDEX_PIN - bool "Enable QEncoder timers support for index pin" - depends on STM32_QENCODER_16BIT_CAPABLE - ---help--- - Enable support for quadrature encoder index pin. The index pin can be - used to reset the encoder position to a known value when the index - pulse is detected. - -config STM32_TIM1_QE - bool "TIM1 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM1) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -config STM32_TIM1_QEPSC - int "TIM1 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM2_QE - bool "TIM2 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM2) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -config STM32_TIM2_QEPSC - int "TIM2 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM3_QE - bool "TIM3 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM3) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -config STM32_TIM3_QEPSC - int "TIM3 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM4_QE - bool "TIM4 QE" - depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_COMMON_F0_L0_G0_C0 && STM32_TIM4) - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -config STM32_TIM4_QEPSC - int "TIM4 QE pulse prescaler" - depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM5_QE - bool "TIM5 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM5 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -config STM32_TIM5_QEPSC - int "TIM5 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM5_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_TIM8_QE - bool "TIM8 QE" - depends on STM32_QENCODER_MAIN && STM32_TIM8 - select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -config STM32_TIM8_QEPSC - int "TIM8 QE pulse prescaler" - depends on STM32_QENCODER_MAIN && STM32_TIM8_QE - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -config STM32_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 - default y - ---help--- - Enable input filtering on quadrature encoder channels to reduce noise. - -menuconfig STM32_FOC - bool "STM32 lower-half FOC support" - depends on STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 - select ARCH_IRQPRIO - select STM32_ADC - select STM32_PWM_MULTICHAN - select STM32_PWM_LL_OPS - select STM32_ADC_LL_OPS - select STM32_ADC_CHANGE_SAMPLETIME - select STM32_ADC_NO_STARTUP_CONV - -config STM32_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM1) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - depends on (STM32_COMMON_LEGACY && STM32_FOC && STM32_HAVE_TIM8) || (ARCH_CHIP_STM32F7 && STM32_FOC) - select STM32_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -config STM32_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_FOC - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32_FOC_USE_TIM1 - bool - select STM32_TIM1 - select STM32_TIM1_PWM - select STM32_TIM1_CHANNEL1 - select STM32_TIM1_CHANNEL2 - select STM32_TIM1_CHANNEL3 - select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1OUT - select STM32_TIM1_CH2OUT - select STM32_TIM1_CH3OUT - select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32_FOC_USE_TIM8 - bool - select STM32_TIM8 - select STM32_TIM8_PWM - select STM32_TIM8_CHANNEL1 - select STM32_TIM8_CHANNEL2 - select STM32_TIM8_CHANNEL3 - select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1OUT - select STM32_TIM8_CH2OUT - select STM32_TIM8_CH3OUT - select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 - select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32_FOC_USE_ADC1 - bool - select STM32_ADC1 - select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC1_JEXTSEL - -config STM32_FOC_USE_ADC2 - bool - select STM32_ADC2 - select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC2_JEXTSEL - -config STM32_FOC_USE_ADC3 - bool - select STM32_ADC3 - select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_V1 - select STM32_ADC3_JEXTSEL - -config STM32_PROGMEM - bool "Flash PROGMEM support" - depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 - select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -config STM32_HAVE_HSI48 - bool - -config STM32_HAVE_LCD - bool - -config STM32_HAVE_DMA2 - bool - -config STM32_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -config STM32_TIM15_ADC - bool "TIM15 ADC" - depends on (STM32_COMMON_F0_L0_G0_C0 || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15 && STM32_ADC - ---help--- - Reserve timer 1 for use by ADC - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART1_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART1) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - depends on (STM32_COMMON_F0_L0_G0_C0 && STM32_USART && STM32_USART2_SERIALDRIVER && STM32_HAVE_IP_USART_V2) || (ARCH_CHIP_STM32H7 && STM32_USART && STM32_USART2) - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -config STM32_SPI1_COMMTYPE - int "SPI1 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI2_COMMTYPE - int "SPI2 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI3_COMMTYPE - int "SPI3 Operation mode" - depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_IO_CONFIG_R - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_V - bool - select STM32_GPIO_HAVE_PORTD if ARCH_CHIP_STM32WB - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_I - bool - -config STM32_IO_CONFIG_Z - bool - -config STM32_IO_CONFIG_B - bool - -config STM32_IO_CONFIG_A - bool - -config STM32_HAVE_PHY_POLLED - bool - -config STM32_HAVE_DCMI - bool - -config STM32_HAVE_DMA2D - bool - -config STM32_HAVE_HASH - bool - -config STM32_HAVE_DFSDM1 - bool - -config STM32_HAVE_SAI1 - bool - -config STM32_HAVE_SAI2 - bool - -config STM32_SAI - bool - -menu "SDIO Configuration" - depends on STM32_COMMON_LEGACY && STM32_SDIO - -config STM32_SDIO_CARD - bool "SDIO Card support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config STM32_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config STM32_SDIO_DMA - bool "Support DMA data transfers" - default STM32_DMA2 - select SDIO_DMA - depends on STM32_DMA2 - ---help--- - Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. - -config STM32_SDIO_DMAPRIO - hex "SDIO DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - ---help--- - Select SDIO DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_SDIO_WIDTH_D1_ONLY - bool "Use D1 only" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDIO Configuration - -config STM32_SDMMC - bool - -config STM32_DFSDM1 - bool "DFSDM1" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 - -config STM32_I2C4 - bool "I2C4" - depends on STM32_HAVE_I2C4 - select STM32_I2C - -config STM32_QUADSPI - bool "QuadSPI" - depends on STM32_COMMON_F7_H7 - -config STM32_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - depends on STM32_COMMON_F7_H7 && USBDEV - -config STM32_SAI1 - bool "SAI1" - depends on STM32_HAVE_SAI1 - -config STM32_SAI1_A - bool "SAI1 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI1_B - bool "SAI1 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2 - bool "SAI2" - depends on STM32_HAVE_SAI2 - -config STM32_SAI2_A - bool "SAI2 Block A" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SAI2_B - bool "SAI2 Block B" - depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 - select AUDIO - select I2S - select SCHED_HPWORK - select STM32_SAI - -config STM32_SDMMC1 - bool "SDMMC1" - depends on STM32_HAVE_SDMMC1 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 - select SCHED_HPWORK if ARCH_CHIP_STM32L4 - select STM32_SAI1PLL if ARCH_CHIP_STM32L4 - -config STM32_SDMMC2 - bool "SDMMC2" - depends on STM32_HAVE_SDMMC2 - select STM32_SDMMC if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 - select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 - select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 - -config STM32_SDMMC_IDMA - bool "Support IDMA data transfers" - depends on ARCH_CHIP_STM32H7 && STM32_SDMMC - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -config STM32_USART_INVERT - bool "Signal Invert Support" - depends on STM32_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32_USART_SWAP - bool "Swap RX/TX pins support" - depends on STM32_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -config STM32_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 16777216 - range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 4 - range 1 16 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - depends on STM32_QUADSPI || STM32_QSPI || STM32_QSPI1 - default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - default 1 - range 1 8 if STM32_COMMON_F7_H7 && STM32_QUADSPI || ARCH_CHIP_STM32L4 && STM32_QSPI - range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -config STM32_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA - default 4 - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on (STM32_QUADSPI || STM32_QSPI || STM32_QSPI1) && STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on STM32_COMMON_F7_H7 && STM32_QUADSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32L4 && STM32_QSPI && DEBUG_SPI_INFO || ARCH_CHIP_STM32H5 && STM32_QSPI1 && DEBUG_SPI_INFO - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -config STM32_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA - default 0 - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -if STM32_SDMMC - -config STM32_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32_SDMMC_DMA - bool "Support DMA data transfers" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA - select SDIO_DMA - ---help--- - Support DMA data transfers. - -config STM32_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 - default 0x00010000 if ARCH_CHIP_STM32F7 - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - depends on STM32_SDMMC1 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endif # STM32_SDMMC - -config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 - default 0 - range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - depends on STM32_COMMON_F7_H7 - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - depends on STM32_COMMON_F7_H7 && ARMV7M_HAVE_DTCM - default LIBC_ARCH_ELF - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - depends on STM32_COMMON_F7_H7 && ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -config STM32_PHY_POLLING - bool "Support network monitoring by polling the PHY" - depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32_LTDC_USE_DSI - bool "Use DSI as display connection" - depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32_HAVE_SMPS - bool - -config STM32_HAVE_ETHERNET - bool - -config STM32_LPTIM - bool - -config STM32_LPTIM2 - bool "LPTIM2" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 - select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB - -config STM32_LPTIM3 - bool "LPTIM3" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM4 - bool "LPTIM4" - depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 - select STM32_LPTIM if ARCH_CHIP_STM32H7 - -config STM32_LPTIM5 - bool "LPTIM5" - depends on ARCH_CHIP_STM32H7 - select STM32_LPTIM - -config STM32_SPI4_COMMTYPE - int "SPI4 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI5_COMMTYPE - int "SPI5 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_SPI6_COMMTYPE - int "SPI6 Operation mode" - depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 - default 0 - range 0 3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32_TIM6_ADC - bool "TIM6 ADC" - depends on (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM6 && STM32_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -config STM32_TIMX_CAP - bool "Helpers for Capture Drivers" - depends on ARCH_CHIP_STM32H7 - default n - -config STM32_TIM15_CAP - bool "TIM15 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM15 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -config STM32_TIM16_CAP - bool "TIM16 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM16 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -config STM32_TIM17_CAP - bool "TIM17 Capture" - depends on STM32_COMMON_H7_H5 && STM32_TIM17 - select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -config STM32_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CAP - bool "LPTIM1 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -config STM32_LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM2_CAP - bool "LPTIM2 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -config STM32_LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32_LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) - default 1 - range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP - range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32_LPTIM3_CAP - bool "LPTIM3 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -config STM32_LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32_LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM4_CAP - bool "LPTIM4 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -config STM32_LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32_LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_LPTIM5_CAP - bool "LPTIM5 Capture" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 - default n - select STM32_TIMX_CAP - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -config STM32_LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32_LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -config STM32_ETH_NRXDESC - int "Number of RX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32_ETH_NTXDESC - int "Number of TX descriptors" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32_NO_PHY - bool "MAC has no PHY" - depends on STM32_COMMON_H7_H5 && STM32_ETHMAC - -config STM32_IO_CONFIG_K - bool - -config STM32_IO_CONFIG_T - bool - -config STM32_IO_CONFIG_C - bool - select STM32_GPIO_HAVE_PORTE if ARCH_CHIP_STM32WB - -config STM32_IO_CONFIG_J - bool - -config STM32_IO_CONFIG_M - bool - -config STM32_IO_CONFIG_Q - bool - -config STM32_SRAM2_HEAP - bool "SRAM2 is used for heap" - depends on STM32_COMMON_SRAM2_OPTIONS - select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_SRAM2_INIT - bool "SRAM2 is initialized to zero" - depends on STM32_COMMON_SRAM2_OPTIONS - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on (ARCH_CHIP_STM32L4 && STM32_STM32L4XR) || (ARCH_CHIP_STM32U5 && STM32_SRAM3) - default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32_HAVE_COMP - bool - -config STM32_HAVE_USART1 - bool - -config STM32_SAI1PLL - bool "SAI1PLL" - depends on STM32_COMMON_L4_L5_U5 - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_SAI2PLL - bool "SAI2PLL" - depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT - default 2 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32_TICKLESS_FREERUN - int "Tickless free-running timer channel" - depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN - default 5 - range 1 8 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -config STM32_LPTIM1_PWM - bool "LPTIM1 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM2_PWM - bool "LPTIM2 PWM" - depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -config STM32_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - depends on STM32_LPTIM1_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - depends on STM32_LPTIM1_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - depends on STM32_LPTIM2_CH1OUT_CAPABLE - ---help--- - Enables channel 1 output. - -config STM32_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - depends on STM32_LPTIM2_CH1NOUT_CAPABLE - ---help--- - Enables channel 1 complementary output. - -config STM32_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32_ADC1_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32_ADC2_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32_ADC3_OUTPUT_DFSDM_CAPABLE - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -config STM32_DAC1_DMA - bool "DAC1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC1_TIMER - int "DAC1 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - range 2 8 - -config STM32_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1_DMA - default 1 - -config STM32_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32_DAC2_DMA - bool "DAC2 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -config STM32_DAC2_TIMER - int "DAC2 timer" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 0 - range 2 8 - -config STM32_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2_DMA - default 1 - -config STM32_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 - select STM32_DFSDM - -config STM32_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) - select STM32_DFSDM - -config STM32_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -config STM32_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN - ---help--- - Enables channel 4. - -config STM32_IPCC - bool "IPCC" - depends on ARCH_CHIP_STM32WB || ARCH_CHIP_STM32WL5 - select IPCC if ARCH_CHIP_STM32WL5 - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -config STM32_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the receive buffer. Another CPU will write to this buffer and - the currently running CPU will read from it. - -config STM32_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - depends on STM32_IPCC - ---help--- - Size of the send buffer. Another CPU will read from this buffer and - the currently running CPU will write to it. - -config STM32_IPCC_CHAN2 - bool "Enable channel 2" - depends on STM32_IPCC - -if STM32_IPCC_CHAN2 - -config STM32_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32_IPCC_CHAN3 - bool "Enable channel 3" - -if STM32_IPCC_CHAN3 - -config STM32_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32_IPCC_CHAN4 - bool "Enable channel 4" - -if STM32_IPCC_CHAN4 - -config STM32_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32_IPCC_CHAN5 - bool "Enable channel 5" - -if STM32_IPCC_CHAN5 - -config STM32_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32_IPCC_CHAN6 - bool "Enable channel 6" - -if STM32_IPCC_CHAN6 - -config STM32_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32_IPCC_CHAN2 -endif # STM32_IPCC_CHAN3 -endif # STM32_IPCC_CHAN4 -endif # STM32_IPCC_CHAN5 -endif # STM32_IPCC_CHAN6 +source "arch/arm/src/common/stm32/Kconfig.uart" +endmenu # U[S]ART Configuration + +menu "SPI/I2S Configuration" + depends on STM32_SPI || STM32_I2S +source "arch/arm/src/common/stm32/Kconfig.spi" +endmenu # SPI/I2S Configuration + +menu "System Configuration" +source "arch/arm/src/common/stm32/Kconfig.system" +endmenu # System Configuration + +menu "Timer Configuration" + depends on STM32_TIM || STM32_LPTIM +source "arch/arm/src/common/stm32/Kconfig.tim" +endmenu # Timer Configuration + +menu "HRTIM Configuration" + depends on STM32_HRTIM +source "arch/arm/src/common/stm32/Kconfig.hrtim" +endmenu # HRTIM Configuration + +menu "USB Configuration" + depends on STM32_USB || STM32_USBFS || STM32_OTGFS || STM32_OTGHS || STM32_OTGFSHS +source "arch/arm/src/common/stm32/Kconfig.usb" +endmenu # USB Configuration endmenu # Common STM32 Configuration Options diff --git a/arch/arm/src/common/stm32/Kconfig.adc b/arch/arm/src/common/stm32/Kconfig.adc new file mode 100644 index 00000000000..2c7040df2bb --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.adc @@ -0,0 +1,964 @@ +# +# STM32 ADC configuration options. +# + +# TODO: The options below are a special case for the legacy family-local +# stm32l4_adc.c driver (selected by STM32_HAVE_ADC_L4). They must be migrated +# to the common ADC interface used by stm32_adc_m3m4_v1v2.c (STM32_ADCx_EXTSEL / +# STM32_ADCx_JEXTSEL / STM32_ADCx_INJECTED_CHAN) and removed from here. + +config STM32_ADC1_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC1_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC1_HAVE_TIMER + default y if (STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7) && STM32_ADC1_HAVE_TIMER + default y if (ARCH_CHIP_STM32H5 || STM32_COMMON_L5_U5) && STM32_ADC1_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMER_FREQ + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_ADC2_HAVE_TIMER + +config STM32_ADC2_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC2_HAVE_TIMER + default y if (STM32_COMMON_F7_H7_H5) && STM32_ADC2_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC2_HAVE_TIMER + +config STM32_ADC3_HAVE_TIMTRIG + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_TIM && STM32_ADC3_HAVE_TIMER + default y if (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC3_HAVE_TIMER + default y if STM32_COMMON_L5_U5 && STM32_ADC3_HAVE_TIMER + +config STM32_ADC1_HAVE_DMA + bool + +config STM32_ADC2_HAVE_DMA + bool + +config STM32_ADC3_HAVE_DMA + bool + +config STM32_ADC4_HAVE_DMA + bool + +config STM32_ADC5_HAVE_DMA + bool + +config STM32_ADC4_HAVE_TIMER + bool + +config STM32_ADC5_HAVE_TIMER + bool + +config STM32_ADC1_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC2_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC3_HAVE_OUTPUT_DFSDM + bool + +config STM32_ADC1_HAVE_TIMER + bool + +config STM32_ADC2_HAVE_TIMER + bool + +config STM32_ADC3_HAVE_TIMER + bool + +menu "STM32L4 ADC Configuration" + depends on STM32_HAVE_ADC_L4 && STM32_ADC + +config STM32_ADC_SMPR + int "ADC sample time" + default 0 + range 0 7 + ---help--- + ADC sample time + 0 - 2.5 ADC clock cycles + 1 - 6.5 ADC clock cycles + 2 - 12.5 ADC clock cycles + 3 - 24.5 ADC clock cycles + 4 - 47.5 ADC clock cycles + 5 - 92.5 ADC clock cycles + 6 - 247.5 ADC clock cycles + 7 - 640.5 ADC clock cycles + +config STM32_ADC1_INJ_CHAN + int "ADC1 configured injected channels" + depends on STM32_ADC1 + range 0 4 + default 0 + ---help--- + Number of configured ADC1 injected channels. + +config STM32_ADC2_INJ_CHAN + int "ADC2 configured injected channels" + depends on STM32_ADC2 + range 0 4 + default 0 + ---help--- + Number of configured ADC2 injected channels. + +config STM32_ADC3_INJ_CHAN + int "ADC3 configured injected channels" + depends on STM32_ADC3 + range 0 4 + default 0 + ---help--- + Number of configured ADC3 injected channels. + +menu "STM32L4 ADCx triggering Configuration" + +config STM32_ADC1_EXTTRIG + int "ADC1 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_EXTTRIG > 0 + +config STM32_ADC_L4_ADC1_EXTSEL + int "ADC1 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC2_EXTTRIG + int "ADC2 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_EXTTRIG > 0 + +config STM32_ADC_L4_ADC2_EXTSEL + int "ADC2 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +config STM32_ADC3_EXTTRIG + int "ADC3 External trigger configuration for regular channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware trigger detection disabled + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_EXTTRIG > 0 + +config STM32_ADC_L4_ADC3_EXTSEL + int "ADC3 External trigger selection for regular group" + default 0 + range 0 15 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of + a regular group. See Reference Manual for more information. + +endif + +if STM32_ADC1_INJ_CHAN > 0 + +config STM32_ADC1_JEXTTRIG + int "ADC1 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC1 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC1_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC1_JEXTSEL + int "ADC1 External Trigger Selection for injected group" + default 0 + range 0 15 + depends on STM32_ADC1 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC2_INJ_CHAN > 0 + +config STM32_ADC2_JEXTTRIG + int "ADC2 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC2 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC2_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC2_JEXTSEL + int "ADC2 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC2 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +if STM32_ADC3_INJ_CHAN > 0 + +config STM32_ADC3_JEXTTRIG + int "ADC3 External Trigger Enable and Polarity Selection for injected channels" + default 0 + range 0 4 + depends on STM32_ADC3 + ---help--- + Values 0: Hardware and software trigger detection disabled, JQDIS=0 + (queue enabled) + 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) + 1: Hardware trigger detection on the rising edge + 2: Hardware trigger detection on the falling edge + 3: Hardware trigger detection on the rising and falling edges + +if STM32_ADC3_JEXTTRIG > 0 + +config STM32_ADC_L4_ADC3_JEXTSEL + int "ADC3 External Trigger Selection for injected group" + default 0 + range 0 5 + depends on STM32_ADC3 + ---help--- + Select the external event used to trigger the start of conversion of an + injected group + +endif + +endif + +endmenu #STM32L4 ADCx triggering Configuration + +endmenu + +menu "ADC Configuration" + depends on STM32_HAVE_ADC_H5 && STM32_ADC + +config STM32_ADC1_OVERSAMPLE + bool "Enable ADC1 hardware oversampling support" + depends on STM32_ADC1 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC1_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC1_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC1_OVERSAMPLE + +config STM32_ADC1_WDG1 + bool "Enable STM32H5 ADC1 Watchdog 1" + depends on STM32_ADC1 + default n + ---help--- + Enable STM32H5 ADC1 Watchdog 1. + +config STM32_ADC1_WDG1_FLT + int "Set ADC1 Watchdog 1 Filter" + depends on STM32_ADC1_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC1_WDG1_LOWTHRESH + int "Set ADC1 Watchdog 1 Low Threshold" + depends on STM32_ADC1_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC1_WDG1_HIGHTHRESH + int "Set ADC1 Watchdog 1 High Threshold" + depends on STM32_ADC1_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC1 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC1_WDG1_SGL + bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" + depends on STM32_ADC1_WDG1 + default n + ---help--- + This option determines if ADC1 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC1_WDG1_CHAN + int "STM32H5 ADC1 Watchdog 1 Channel Selection" + depends on STM32_ADC1_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC1 Watchdog 1. + +config STM32_ADC2_OVERSAMPLE + bool "Enable ADC2 hardware oversampling support" + depends on STM32_ADC2 + default n + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_TROVS + bool "Enable triggered oversampling (CFGR2.TROVS)" + default n + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC2_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2× + 1 -> 4× + 2 -> 8× + ... + 7 -> 256× + +config STM32_ADC2_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC2_OVERSAMPLE + +config STM32_ADC2_WDG1 + bool "Enable STM32H5 ADC2 Watchdog 1" + depends on STM32_ADC2 + default n + ---help--- + Enable STM32H5 ADC2 Watchdog 1. + +config STM32_ADC2_WDG1_FLT + int "Set ADC2 Watchdog 1 Filter" + depends on STM32_ADC2_WDG1 + default 0 + range 0 7 + ---help--- + N+1 watchdog events generates an interrupt. + Default: 0. + +config STM32_ADC2_WDG1_LOWTHRESH + int "Set ADC2 Watchdog 1 Low Threshold" + depends on STM32_ADC2_WDG1 + default 0 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 low threshold value. + Default: 0. + +config STM32_ADC2_WDG1_HIGHTHRESH + int "Set ADC2 Watchdog 1 High Threshold" + depends on STM32_ADC2_WDG1 + default 4095 + range 0 4095 + ---help--- + Set the ADC2 Watchdog 1 high threshold value. + Default: 4095. + +config STM32_ADC2_WDG1_SGL + bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" + depends on STM32_ADC2_WDG1 + default n + ---help--- + This option determines if ADC2 Watchdog 1 is enabled on all + channels or just a single channel. + +config STM32_ADC2_WDG1_CHAN + int "STM32H5 ADC2 Watchdog 1 Channel Selection" + depends on STM32_ADC2_WDG1_SGL + default 0 + range 0 19 + ---help--- + Select the channel to enable for ADC2 Watchdog 1. + +endmenu # ADC Configuration + +config STM32_ADC1_SAMPLE_FREQUENCY + int "ADC1 Sampling Frequency" + depends on STM32_ADC1_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC1 sampling frequency. Default: 100Hz + +config STM32_ADC1_TIMTRIG + int "ADC1 Timer Trigger" + depends on STM32_ADC1_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC2_SAMPLE_FREQUENCY + int "ADC2 Sampling Frequency" + depends on STM32_ADC2_HAVE_TIMER_FREQ + default 100 + ---help--- + ADC2 sampling frequency. Default: 100Hz + +config STM32_ADC2_TIMTRIG + int "ADC2 Timer Trigger" + depends on STM32_ADC2_HAVE_TIMTRIG + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC3_SAMPLE_FREQUENCY + int "ADC3 Sampling Frequency" + depends on STM32_ADC3_HAVE_TIMTRIG + default 100 + ---help--- + ADC3 sampling frequency. Default: 100Hz + +config STM32_ADC3_TIMTRIG + int "ADC3 Timer Trigger" + depends on STM32_ADC3_HAVE_TIMTRIG && !ARCH_CHIP_STM32L4 + default 0 + range 0 5 if STM32_HAVE_ADC_TIMTRIG_TRGO2 + range 0 4 if STM32_HAVE_ADC_TIMTRIG_TRGO + ---help--- + Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 + +config STM32_ADC1_RESOLUTION + int "ADC1 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 + default 0 + range 0 3 + ---help--- + ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC2_RESOLUTION + int "ADC2 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 + default 0 + range 0 3 + ---help--- + ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC3_RESOLUTION + int "ADC3 resolution" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 + default 0 + range 0 3 + ---help--- + ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC_MAX_SAMPLES + int "The maximum number of channels that can be sampled" + depends on STM32_ADC + default 1 if STM32_HAVE_IP_ADC_M0_V1 && !STM32_ADC1_DMA + default 16 + ---help--- + The maximum number of samples which can be handled without + overrun depends on various factors. This is the user's + responsibility to correctly select this value. + Since the interface to update the sampling time is available + for all supported devices, the user can change the default + values in the board initialization logic and avoid ADC overrun. + +config STM32_ADC_NO_STARTUP_CONV + bool "Do not start conversion when opening ADC device" + depends on STM32_ADC + ---help--- + Do not start conversion when opening ADC device. + +config STM32_ADC_NOIRQ + bool "Do not use default ADC interrupts" + depends on STM32_ADC + ---help--- + Do not use default ADC interrupts handlers. + +config STM32_ADC_LL_OPS + bool "ADC low-level operations" + depends on STM32_ADC + ---help--- + Enable low-level ADC ops. + +config STM32_ADC_CHANGE_SAMPLETIME + bool "ADC sample time configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC_LL_OPS + ---help--- + Enable ADC sample time configuration (SMPRx registers). + +config STM32_ADC_OVERSAMPLE + bool "Enable ADC hardware oversampling support" + depends on STM32_ADC1 && STM32_HAVE_ADC_OVERSAMPLE + ---help--- + Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). + Only STM32G0 and STM32L0 series include this hardware block. + +if STM32_ADC_OVERSAMPLE + +config STM32_ADC_TOVS + bool "Enable triggered oversampling (CFGR2.TOVS)" + ---help--- + If set, oversampling will only occur when a trigger event occurs. + If not set, oversampling occurs continuously (TOVS=0). + +config STM32_ADC_OVSR + int "Oversampling ratio (CFGR2.OVSR)" + default 0 + range 0 7 + ---help--- + Sets the oversampling ratio as 2^(OVSR+1). For example: + 0 -> 2x + 1 -> 4x + 2 -> 8x + ... + 7 -> 256x + +config STM32_ADC_OVSS + int "Oversampling right-shift bits (CFGR2.OVSS)" + default 0 + range 0 8 + ---help--- + Sets how many bits the accumulated result is right-shifted. + Max of 8-bits. + +endif # STM32_ADC_OVERSAMPLE + +config STM32_ADC1_DMA + bool "ADC1 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && STM32_ADC1_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC1 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC1 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC1 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC1_SCAN + bool "ADC1 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC1 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC1) + default STM32_ADC1_DMA + +config STM32_ADC1_DMA_CFG + int "ADC1 DMA configuration" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1) && STM32_ADC && STM32_ADC1_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode + +config STM32_ADC1_DMA_BATCH + int "ADC1 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC1 && STM32_ADC1_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC1_ANIOC_TRIGGER + int "ADC1 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC2_DMA + bool "ADC2 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2 && STM32_ADC2_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC2 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC2 || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2 && STM32_DMA + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC2_SCAN + bool "ADC2 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC2) + default STM32_ADC2_DMA + +config STM32_ADC2_DMA_CFG + int "ADC2 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC2_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC2_DMA || ARCH_CHIP_STM32H5 && STM32_ADC && STM32_ADC2_DMA && STM32_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode + +config STM32_ADC2_DMA_BATCH + int "ADC2 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_ADC && STM32_ADC2 && STM32_ADC2_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC2_ANIOC_TRIGGER + int "ADC2 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC3_DMA + bool "ADC3 DMA" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3 && STM32_ADC3_HAVE_DMA || ARCH_CHIP_STM32H7 && STM32_ADC && STM32_ADC3 && EXPERIMENTAL || STM32_COMMON_L4_L5_U5 && STM32_ADC && STM32_ADC3 + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC3_SCAN + bool "ADC3 scan mode" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3 && STM32_HAVE_IP_ADC_M3M4_V1) || (ARCH_CHIP_STM32F7 && STM32_ADC && STM32_ADC3) + default STM32_ADC3_DMA + +config STM32_ADC3_DMA_CFG + int "ADC3 DMA configuration" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_ADC && STM32_ADC3_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3_DMA + default 1 if ARCH_CHIP_STM32L4 + default 0 + range 0 1 + ---help--- + 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode + +config STM32_ADC3_DMA_BATCH + int "ADC3 DMA number of conversions" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4) && STM32_ADC && STM32_ADC3 && STM32_ADC3_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC3_ANIOC_TRIGGER + int "ADC3 software trigger (ANIOC_TRIGGER) configuration" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 3 + range 1 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC1_INJECTED_CHAN + int "ADC1 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + default 0 + range 0 4 + ---help--- + Support for ADC1 injected channels. + +config STM32_ADC2_INJECTED_CHAN + int "ADC2 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + default 0 + range 0 4 + ---help--- + Support for ADC2 injected channels. + +config STM32_ADC3_INJECTED_CHAN + int "ADC3 injected channels" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + default 0 + range 0 4 + ---help--- + Support for ADC3 injected channels. + +config STM32_ADC1_EXTSEL + bool "ADC1 external trigger for regular group" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1 && !STM32_ADC1_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC1. + +config STM32_ADC2_EXTSEL + bool "ADC2 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) && !STM32_ADC2_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC2. + +config STM32_ADC3_EXTSEL + bool "ADC3 external trigger for regular group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) && !STM32_ADC3_HAVE_TIMER + ---help--- + Enable EXTSEL for ADC3. + +config STM32_ADC1_JEXTSEL + bool "ADC1 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC1) + ---help--- + Enable JEXTSEL for ADC1. + +config STM32_ADC2_JEXTSEL + bool "ADC2 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC2) + ---help--- + Enable JEXTSEL for ADC2. + +config STM32_ADC3_JEXTSEL + bool "ADC3 external trigger for injected group" + depends on (((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7) && STM32_ADC && STM32_ADC3) + ---help--- + Enable JEXTSEL for ADC3. + +config STM32_DAC1_OUTPUT_ADC + bool "DAC1 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC1 + ---help--- + Route DAC1 output to ADC input instead of external pin. + +config STM32_DAC2_OUTPUT_ADC + bool "DAC2 output to ADC" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC && STM32_DAC2 + ---help--- + Route DAC2 output to ADC input instead of external pin. + +config STM32_ADC1_OUTPUT_DFSDM + bool "ADC1 output to DFSDM" + depends on STM32_ADC1_HAVE_OUTPUT_DFSDM && STM32_ADC1 && STM32_DFSDM1 + ---help--- + Route ADC1 output directly to DFSDM parallel inputs. + +config STM32_ADC2_OUTPUT_DFSDM + bool "ADC2 output to DFSDM" + depends on STM32_ADC2_HAVE_OUTPUT_DFSDM && STM32_ADC2 && STM32_DFSDM1 + ---help--- + Route ADC2 output directly to DFSDM parallel inputs. + +config STM32_ADC3_OUTPUT_DFSDM + bool "ADC3 output to DFSDM" + depends on STM32_ADC3_HAVE_OUTPUT_DFSDM && STM32_ADC3 && STM32_DFSDM1 + ---help--- + Route ADC3 output directly to DFSDM parallel inputs. + +config STM32_ADC4_RESOLUTION + int "ADC4 resolution" + depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC5_RESOLUTION + int "ADC5 resolution" + depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + default 0 + range 0 3 + ---help--- + ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit + +config STM32_ADC4_DMA + bool "ADC4 DMA" + depends on STM32_ADC4 && STM32_ADC4_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC4_DMA_CFG + int "ADC4 DMA configuration" + depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode + +config STM32_ADC4_DMA_BATCH + int "ADC4 DMA number of conversions" + depends on STM32_ADC4 && STM32_ADC4_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_ANIOC_TRIGGER + int "ADC4 software trigger (ANIOC_TRIGGER) configuration" + depends on STM32_ADC4 + range 1 3 + default 3 + ---help--- + 1 - ANIOC_TRIGGER only starts regular conversion + 2 - ANIOC_TRIGGER only starts injected conversion + 3 - ANIOC_TRIGGER starts both regular and injected conversions + +config STM32_ADC5_DMA + bool "ADC5 DMA" + depends on STM32_ADC5 && STM32_ADC5_HAVE_DMA + default n + ---help--- + If DMA is selected, then the ADC may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_ADC5_DMA_CFG + int "ADC5 DMA configuration" + depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_M3M4_V1_BASIC + range 0 1 + default 0 + ---help--- + 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode + +config STM32_ADC5_DMA_BATCH + int "ADC5 DMA number of conversions" + depends on STM32_ADC5 && STM32_ADC5_DMA + default 1 + ---help--- + This option allows you to select the number of regular group conversions + that will trigger a DMA callback transerring data to the upper-half driver. + By default, this value is 1, which means that data is transferred after + each group conversion. + +config STM32_ADC4_INJECTED_CHAN + int "ADC4 injected channels" + depends on STM32_ADC4 + range 0 4 + default 0 + ---help--- + Support for ADC4 injected channels. + +config STM32_ADC5_INJECTED_CHAN + int "ADC5 injected channels" + depends on STM32_ADC5 + range 0 4 + default 0 + ---help--- + Support for ADC5 injected channels. + +config STM32_ADC4_EXTSEL + bool "ADC4 external trigger for regular group" + depends on STM32_ADC4 && !STM32_ADC4_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC4. + +config STM32_ADC5_EXTSEL + bool "ADC5 external trigger for regular group" + depends on STM32_ADC5 && !STM32_ADC5_HAVE_TIMER + default n + ---help--- + Enable EXTSEL for ADC5. + +config STM32_ADC4_JEXTSEL + bool "ADC4 external trigger for injected group" + depends on STM32_ADC4 + default n + ---help--- + Enable JEXTSEL for ADC4. + +config STM32_ADC5_JEXTSEL + bool "ADC5 external trigger for injected group" + depends on STM32_ADC5 + default n + ---help--- + Enable JEXTSEL for ADC5. + +config STM32_ADC1_CONTINUOUS + bool "Enable ADC1 Continuous Conversion Mode" + default n + depends on STM32_ADC1 && STM32_HAVE_IP_ADC_M0_V1 + ---help--- + If enabled, the ADC will operate in continuous conversion mode. + Otherwise, it will perform single conversions. + Note: Continuous and discontinuous mode cannot be defined at + the same time diff --git a/arch/arm/src/common/stm32/Kconfig.ble b/arch/arm/src/common/stm32/Kconfig.ble new file mode 100644 index 00000000000..dd91f1fe662 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ble @@ -0,0 +1,221 @@ +# +# STM32 common BLE options. +# + +if STM32_BLE + +config STM32_BLE_C2HOST + bool "Enable CPU2 HOST stack" + default n + ---help--- + The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and + control it using vendor ACL protocol. However, it is not expected to enable + this option in the current implementation. + +config STM32_BLE_MAX_CONN + int "Maximum BLE simultaneous connections" + range 1 8 + default 2 + +config STM32_BLE_GATT_MAX_ATTR_NUM + int "GATT attributes max count" + range 9 255 + default 64 + +config STM32_BLE_GATT_MAX_SVC_NUM + int "GATT services max count" + range 2 64 + default 8 + +config STM32_BLE_GATT_ATTR_BUF_SIZE + int "GATT attributes storage buf size" + default 1344 + ---help--- + Size of the storage area for attribute values. Hardcoded in CPU2 firmware. + +config STM32_BLE_DLE + bool "Support Data Length Extension (DLE)" + default y + +config STM32_BLE_MAX_ATT_MTU + int "Maximum supported attribute MTU" + range 23 512 + default 156 + +config STM32_BLE_SLAVE_SCA + int "Sleep clock accuracy in slave mode [PPM]" + default 500 + ---help--- + Sleep clock accuracy (ppm value) in slave mode. + +choice + prompt "Sleep clock accuracy in master mode" + default STM32_BLE_MASTER_SCA_0 + ---help--- + Sleep clock accuracy in master mode. + +config STM32_BLE_MASTER_SCA_0 + bool "251-500 ppm" + +config STM32_BLE_MASTER_SCA_1 + bool "151-250 ppm" + +config STM32_BLE_MASTER_SCA_2 + bool "101-150 ppm" + +config STM32_BLE_MASTER_SCA_3 + bool "76-100 ppm" + +config STM32_BLE_MASTER_SCA_4 + bool "51-75 ppm" + +config STM32_BLE_MASTER_SCA_5 + bool "31-50 ppm" + +config STM32_BLE_MASTER_SCA_6 + bool "21-30 ppm" + +config STM32_BLE_MASTER_SCA_7 + bool "0-20 ppm" + +endchoice # Sleep clock accuracy in master mode + +config STM32_BLE_MASTER_SCA + int + default 7 if STM32_BLE_MASTER_SCA_7 + default 6 if STM32_BLE_MASTER_SCA_6 + default 5 if STM32_BLE_MASTER_SCA_5 + default 4 if STM32_BLE_MASTER_SCA_4 + default 3 if STM32_BLE_MASTER_SCA_3 + default 2 if STM32_BLE_MASTER_SCA_2 + default 1 if STM32_BLE_MASTER_SCA_1 + default 0 + +choice + prompt "Low speed clock source" + default STM32_BLE_LS_CLK_SRC_LSE + ---help--- + Low speed 32 kHz clock source. + +config STM32_BLE_LS_CLK_SRC_LSE + bool "LSE" + +config STM32_BLE_LS_CLK_SRC_HSE + bool "HSE" + +endchoice # Low speed clock source + +config STM32_BLE_LS_CLK_SRC + int + default 1 if STM32_BLE_LS_CLKSRC_HSE + default 0 + +config STM32_BLE_MAX_CONN_EVT_LENGTH + hex "Max connection event length" + default 0xffffffff + ---help--- + Maximum duration of a slave connection event in units of 625/256us (~2.44us). + +config STM32_BLE_HSE_STARTUP + hex "HSE startup time" + default 0x148 + ---help--- + HSE startup time in units of 625/256us (~2.44us). + +config STM32_BLE_VITERBI + bool "Enable Viterbi algorithm" + default y + ---help--- + Enable Viterbi algorithm implementation + +config STM32_BLE_MAX_INITOR_COC_NUM + int "Max number of connection-oriented channels" + range 0 64 + default 32 + ---help--- + Maximum number of connection-oriented channels in initiator mode. + +config STM32_BLE_SVC_CHANGED_CHAR + bool "Enable service changed characteristic" + default n + +config STM32_BLE_WRITABLE_DEVICE_NAME + bool "Writable device name" + default y + +config STM32_BLE_CHAN_SEL_ALG2 + bool "Enable channel selection algorithm 2" + default n + +choice + prompt "Power class" + default STM32_BLE_POWER_CLASS_2_3 + +config STM32_BLE_POWER_CLASS_2_3 + bool "Power Class 2-3" + +config STM32_BLE_POWER_CLASS_1 + bool "Power Class 1" + +endchoice # Power class + +config STM32_BLE_MIN_TX_POWER + int "Minimum transmit power [dBm]" + range -127 20 + default 0 + +config STM32_BLE_MAX_TX_POWER + int "Maximum transmit power [dBm]" + range -127 20 + default 0 + +choice + prompt "AGC RSSI model" + default STM32_BLE_AGC_RSSI_LEGACY + +config STM32_BLE_AGC_RSSI_LEGACY + bool "AGC RSSI Legacy" + +config STM32_BLE_AGC_RSSI_IMPROVED + bool "AGC RSSI Improved" + +endchoice # AGC RSSI model + +config STM32_BLE_ADVERTISING + bool "Support advertising" + default y + +config STM32_BLE_SCANNING + bool "Support scanning" + default y + +config STM32_BLE_LE_2M_PHY + bool "Support LE 2M PHY" + default y + +config STM32_BLE_LE_CODED_PHY + bool "Support LE Coded PHY" + default STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + depends on STM32_STM32WB15 || STM32_STM32WB35 || STM32_STM32WB55 + +config STM32_BLE_FICR_STATIC_ADDR + bool "Configure factory generated static random address" + default n + +config STM32_BLE_PUB_ADDR + hex "Configure BT public address" + default 0x0000000000 + +endif # STM32_BLE + +if STM32_MBOX + +config STM32_MBOX_TX_CMD_QUEUE_LEN + int "Mailbox TX command queue length" + default 2 + +config STM32_MBOX_RX_EVT_QUEUE_LEN + int "Mailbox RX event queue length" + default 5 + +endif # STM32_MBOX diff --git a/arch/arm/src/common/stm32/Kconfig.cache b/arch/arm/src/common/stm32/Kconfig.cache new file mode 100644 index 00000000000..ba13237abd0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.cache @@ -0,0 +1,238 @@ +# +# STM32 cache configuration options. +# + +menu "ICACHE Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_MONITOR_EN + bool "Enable ICACHE Hit/Miss Counters" + default n + +config STM32_ICACHE_DIRECT + bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" + default n + +menu "ICACHE Interrupt Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_INV_INT + bool "Enable interrupts on full invalidation completion." + default n + +config STM32_ICACHE_ERR_INT + bool "Enable interrupts on occurrences of cache errors." + default n + +endmenu # ICACHE Interrupt Configuration + +menu "ICACHE Region Configuration" + depends on STM32_ICACHE + +config STM32_ICACHE_REGION0 + bool "Enable Configuration of ICACHE Region 0" + default n + +config STM32_ICACHE_REGION1 + bool "Enable Configuration of ICACHE Region 1" + default n + +config STM32_ICACHE_REGION2 + bool "Enable Configuration of ICACHE Region 2" + default n + +config STM32_ICACHE_REGION3 + bool "Enable Configuration of ICACHE Region 3" + default n + +menu "Region 0 Configuration" + depends on STM32_ICACHE_REGION0 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION0_BADDR + hex "ICACHE Region 0 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 0. + +config STM32_ICACHE_REGION0_RSIZE + int "ICACHE Region 0 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION0 + ---help--- + Set the size of Region 0. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION0_REMAPADDR + hex "ICACHE Region 0 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION0 + ---help--- + Set bits [31:21] of ICACHE Region 0 Remap Address.. + +config STM32_ICACHE_REGION0_MSTSEL + int "ICACHE Region 0 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select ICACHE Region 0 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION0_HBURST + int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION0 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 0 Configuration + +menu "Region 1 Configuration" + depends on STM32_ICACHE_REGION1 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION1_BADDR + hex "ICACHE Region 1 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 1. + +config STM32_ICACHE_REGION1_RSIZE + int "ICACHE Region 1 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION1 + ---help--- + Set the size of Region 1. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION1_REMAPADDR + hex "ICACHE Region 1 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION1 + ---help--- + Set bits [31:21] of ICACHE Region 1 Remap Address.. + +config STM32_ICACHE_REGION1_MSTSEL + int "ICACHE Region 1 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select ICACHE Region 1 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION1_HBURST + int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION1 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 1 Configuration + +menu "Region 2 Configuration" + depends on STM32_ICACHE_REGION2 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION2_BADDR + hex "ICACHE Region 2 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 2. + +config STM32_ICACHE_REGION2_RSIZE + int "ICACHE Region 2 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION2 + ---help--- + Set the size of Region 2. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION2_REMAPADDR + hex "ICACHE Region 2 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION2 + ---help--- + Set bits [31:21] of ICACHE Region 2 Remap Address.. + +config STM32_ICACHE_REGION2_MSTSEL + int "ICACHE Region 2 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select ICACHE Region 2 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION2_HBURST + int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION2 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 2 Configuration + +menu "Region 3 Configuration" + depends on STM32_ICACHE_REGION3 && STM32_HAVE_ICACHE_REMAP + +config STM32_ICACHE_REGION3_BADDR + hex "ICACHE Region 3 Base Address Bits [28:21]" + default 0 + range 0 255 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [28:21] of the base address for ICACHE Region 3. + +config STM32_ICACHE_REGION3_RSIZE + int "ICACHE Region 3 Size" + default 1 + range 1 7 + depends on STM32_ICACHE_REGION3 + ---help--- + Set the size of Region 3. + 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, + 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. + +config STM32_ICACHE_REGION3_REMAPADDR + hex "ICACHE Region 3 Remap Address Bits [31:21]" + default 0 + range 0 2047 + depends on STM32_ICACHE_REGION3 + ---help--- + Set bits [31:21] of ICACHE Region 3 Remap Address.. + +config STM32_ICACHE_REGION3_MSTSEL + int "ICACHE Region 3 Master Select (0 or 1)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select ICACHE Region 3 Master 1 (0) or Master 2 (1). + +config STM32_ICACHE_REGION3_HBURST + int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" + default 0 + range 0 1 + depends on STM32_ICACHE_REGION3 + ---help--- + Select Wrap (0) or Increment (1) Output Burst Type. + +endmenu # Region 3 Configuration + +endmenu # ICACHE Region Configuration + +endmenu # ICACHE Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.can b/arch/arm/src/common/stm32/Kconfig.can new file mode 100644 index 00000000000..2bb08577c80 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.can @@ -0,0 +1,58 @@ +# +# STM32 CAN configuration options. +# + +choice + prompt "CAN character driver or SocketCAN support" + default STM32_CAN_CHARDRIVER + +config STM32_CAN_CHARDRIVER + bool "STM32 CAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_CAN_SOCKET + bool "STM32 CAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + +endchoice # CAN character driver or SocketCAN support + +config STM32_CAN1_BAUD + int "CAN1 BAUD" + depends on STM32_CAN1 + default 250000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_STM32_CAN1 is defined. + +config STM32_CAN2_BAUD + int "CAN2 BAUD" + depends on STM32_CAN2 + default 250000 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32_CAN2 is defined. + +config STM32_CAN3_BAUD + int "CAN3 BAUD" + depends on STM32_CAN3 + default 250000 + ---help--- + CAN3 BAUD rate. Required if CONFIG_STM32_CAN3 is defined. + +config STM32_CAN_TSEG1 + int "TSEG1 quanta" + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + +config STM32_CAN_TSEG2 + int "TSEG2 quanta" + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config STM32_CAN_REGDEBUG + bool "CAN Register level debug" + depends on DEBUG_CAN_INFO + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.comp b/arch/arm/src/common/stm32/Kconfig.comp new file mode 100644 index 00000000000..57c4c8a5d1a --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.comp @@ -0,0 +1,387 @@ +# +# STM32 analog comparator (COMP) configuration options. +# + +# COMP supported only for M3M4 for now + +if STM32_HAVE_IP_COMP_M3M4_V2 + +if STM32_COMP1 + +config STM32_COMP1_OUT + bool "COMP1 GPIO Output" + default n + ---help--- + Enables COMP1 output. + +config STM32_COMP1_INM + int "COMP1 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP1 inverting input pin. + +config STM32_COMP1_INP + int "COMP1 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP1 non-inverting input pin. + +config STM32_COMP1_POL + int "COMP1 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP1 output polarity. + +config STM32_COMP1_HYST + int "COMP1 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP1. + +config STM32_COMP1_BLANKSEL + int "COMP1 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP1. + +config STM32_COMP1_LOCK + int "COMP1 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP1 + +if STM32_COMP2 + +config STM32_COMP2_OUT + bool "COMP2 GPIO Output" + default n + ---help--- + Enables COMP2 output. + +config STM32_COMP2_INM + int "COMP2 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP2 inverting input pin. + +config STM32_COMP2_INP + int "COMP2 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP2 non-inverting input pin. + +config STM32_COMP2_POL + int "COMP2 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP2 output polarity. + +config STM32_COMP2_HYST + int "COMP2 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP2. + +config STM32_COMP2_BLANKSEL + int "COMP2 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP2. + +config STM32_COMP2_LOCK + int "COMP2 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP2 + +if STM32_COMP3 + +config STM32_COMP3_OUT + bool "COMP3 GPIO Output" + default n + ---help--- + Enables COMP3 output. + +config STM32_COMP3_INM + int "COMP3 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP3 inverting input pin. + +config STM32_COMP3_INP + int "COMP3 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP3 non-inverting input pin. + +config STM32_COMP3_POL + int "COMP3 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP3 output polarity. + +config STM32_COMP3_HYST + int "COMP3 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP3. + +config STM32_COMP3_BLANKSEL + int "COMP3 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP3. + +config STM32_COMP3_LOCK + int "COMP3 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP3 + +if STM32_COMP4 + +config STM32_COMP4_OUT + bool "COMP4 GPIO Output" + default n + ---help--- + Enables COMP4 output. + +config STM32_COMP4_INM + int "COMP4 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP4 inverting input pin. + +config STM32_COMP4_INP + int "COMP4 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP4 non-inverting input pin. + +config STM32_COMP4_POL + int "COMP4 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP4 output polarity. + +config STM32_COMP4_HYST + int "COMP4 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP4. + +config STM32_COMP4_BLANKSEL + int "COMP4 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP4. + +config STM32_COMP4_LOCK + int "COMP4 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP4 + +if STM32_COMP5 + +config STM32_COMP5_OUT + bool "COMP5 GPIO Output" + default n + ---help--- + Enables COMP5 output. + +config STM32_COMP5_INM + int "COMP5 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP5 inverting input pin. + +config STM32_COMP5_INP + int "COMP5 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP5 non-inverting input pin. + +config STM32_COMP5_POL + int "COMP5 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP5 output polarity. + +config STM32_COMP5_HYST + int "COMP5 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP5. + +config STM32_COMP5_BLANKSEL + int "COMP5 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP5. + +config STM32_COMP5_LOCK + int "COMP5 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP5 + +if STM32_COMP6 + +config STM32_COMP6_OUT + bool "COMP6 GPIO Output" + default n + ---help--- + Enables COMP6 output. + +config STM32_COMP6_INM + int "COMP6 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP6 inverting input pin. + +config STM32_COMP6_INP + int "COMP6 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP6 non-inverting input pin. + +config STM32_COMP6_POL + int "COMP6 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP6 output polarity. + +config STM32_COMP6_HYST + int "COMP6 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP6. + +config STM32_COMP6_BLANKSEL + int "COMP6 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP6. + +config STM32_COMP6_LOCK + int "COMP6 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP6 + +if STM32_COMP7 + +config STM32_COMP7_OUT + bool "COMP7 GPIO Output" + default n + ---help--- + Enables COMP7 output. + +config STM32_COMP7_INM + int "COMP7 inverting input assignment" + range 0 7 + default 0 + ---help--- + Selects COMP7 inverting input pin. + +config STM32_COMP7_INP + int "COMP7 non-inverting input assignment" + range 0 1 + default 0 + ---help--- + Selects COMP7 non-inverting input pin. + +config STM32_COMP7_POL + int "COMP7 polarity" + range 0 1 + default 0 + ---help--- + Selects COMP7 output polarity. + +config STM32_COMP7_HYST + int "COMP7 hysteresis" + depends on STM32_STM32G4XXX + range 0 7 + default 0 + ---help--- + Selects the hysteresis of the COMP7. + +config STM32_COMP7_BLANKSEL + int "COMP7 blanking signal select" + range 0 7 + default 0 + ---help--- + Selects the blanking signal for comparator COMP7. + +config STM32_COMP7_LOCK + int "COMP7 COMP_CxCSR register lock" + range 0 1 + default 0 + ---help--- + Locks COMP_CxCSR register. + 0 - Unlock 1 - Lock + +endif # STM32_COMP7 + +endif # STM32_HAVE_IP_COMP_M3M4_V2 diff --git a/arch/arm/src/common/stm32/Kconfig.dac b/arch/arm/src/common/stm32/Kconfig.dac new file mode 100644 index 00000000000..92a88c2e601 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dac @@ -0,0 +1,363 @@ +# +# STM32 DAC configuration options. +# + +config STM32_DAC_LL_OPS + bool "DAC low-level operations" + default n + ---help--- + Enable low-level DAC ops. + +config STM32_DAC1_DMA + bool "DAC1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC1_TIMER + int "DAC1 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + range 2 8 + +config STM32_DAC1_TIMER_FREQUENCY + int "DAC1 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + default 100 + ---help--- + DAC1 output frequency. Default: 100Hz + +config STM32_DAC1_DMA_BUFFER_SIZE + int "DAC1 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC1_DMA + default 1 + +config STM32_DAC2_DMA + bool "DAC2 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2 + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +config STM32_DAC2_TIMER + int "DAC2 timer" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 0 + range 2 8 + +config STM32_DAC2_TIMER_FREQUENCY + int "DAC2 timer frequency" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 100 + ---help--- + DAC2 output frequency. Default: 100Hz + +config STM32_DAC2_DMA_BUFFER_SIZE + int "DAC2 DMA buffer size" + depends on STM32_COMMON_L4_L5_U5 && STM32_DAC2_DMA + default 1 + +menu "DAC Configuration" + depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 + +config STM32_DAC1CH1_MODE + int "DAC1CH1 channel mode" + depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH1_DMA + bool "DAC1CH1 DMA" + depends on STM32_DAC1CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH1_DMA + +config STM32_DAC1CH1_DMA_BUFFER_SIZE + int "DAC1CH1 DMA buffer size" + default 256 + +config STM32_DAC1CH1_DMA_EXTERNAL + bool "DAC1CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH1_HRTIM_TRG1 + bool "DAC1CH1 HRTIM Trigger 1" + default n + +config STM32_DAC1CH1_HRTIM_TRG2 + bool "DAC1CH1 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH1_TIMER + int "DAC1CH1 timer" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH1_TIMER_FREQUENCY + int "DAC1CH1 timer frequency" + depends on !STM32_DAC1CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC1CH2_MODE + int "DAC1CH2 channel mode" + depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC1CH2_DMA + bool "DAC1CH2 DMA" + depends on STM32_DAC1CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC1CH2_DMA + +config STM32_DAC1CH2_DMA_BUFFER_SIZE + int "DAC1CH2 DMA buffer size" + default 256 + +config STM32_DAC1CH2_DMA_EXTERNAL + bool "DAC1CH2 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC1CH2_HRTIM_TRG1 + bool "DAC1CH2 HRTIM Trigger 1" + default n + +config STM32_DAC1CH2_HRTIM_TRG2 + bool "DAC1CH2 HRTIM Trigger 2" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC1CH2_TIMER + int "DAC1CH2 timer" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + range 2 8 + +config STM32_DAC1CH2_TIMER_FREQUENCY + int "DAC1CH2 timer frequency" + depends on !STM32_DAC1CH2_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC2CH1_MODE + int "DAC2CH1 channel mode" + depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC2CH1_DMA + bool "DAC2CH1 DMA" + depends on STM32_DAC2CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by and EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC2CH1_DMA + +config STM32_DAC2CH1_DMA_BUFFER_SIZE + int "DAC2CH1 DMA buffer size" + default 256 + +config STM32_DAC2CH1_DMA_EXTERNAL + bool "DAC2CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC2CH1_HRTIM_TRG3 + bool "DAC2CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC2CH1_TIMER + int "DAC2CH1 timer" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC2CH1_TIMER_FREQUENCY + int "DAC2CH1 timer frequency" + depends on !STM32_DAC2CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH1_MODE + int "DAC3CH1 channel mode" + depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH1_DMA + bool "DAC3CH1 DMA" + depends on STM32_DAC3CH1 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH1_DMA + +config STM32_DAC3CH1_DMA_BUFFER_SIZE + int "DAC3CH1 DMA buffer size" + default 256 + +config STM32_DAC3CH1_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH1_HRTIM_TRG3 + bool "DAC3CH1 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH1_TIMER + int "DAC3CH1 timer" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH1_TIMER_FREQUENCY + int "DAC3CH1 timer frequency" + depends on !STM32_DAC3CH1_DMA_EXTERNAL + default 0 + +endif + +config STM32_DAC3CH2_MODE + int "DAC3CH2 channel mode" + depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_M3M4_V2 + default 0 + range 0 7 + ---help--- + – DAC channel in Normal mode + 0: DAC channel is connected to external pin with Buffer enabled + 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled + 2: DAC channel2 is connected to external pin with buffer disabled + 3: DAC channel is connected to on chip peripherals with Buffer disabled + - DAC channel in Sample and hold mode + 4: DAC channel is connected to external pin with Buffer enabled + 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled + 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled + 7: DAC channel is connected to on chip peripherals with Buffer disabled + +config STM32_DAC3CH2_DMA + bool "DAC3CH2 DMA" + depends on STM32_DAC3CH2 + default n + ---help--- + If DMA is selected, then a timer and output frequency must also be + provided to support the DMA transfer. The DMA transfer could be + supported by an EXTI trigger, but this feature is not currently + supported by the driver. + +if STM32_DAC3CH2_DMA + +config STM32_DAC3CH2_DMA_BUFFER_SIZE + int "DAC3CH2 DMA buffer size" + default 256 + +config STM32_DAC3CH2_DMA_EXTERNAL + bool "DAC3CH1 DMA External Trigger" + default n + +if STM32_HRTIM_DAC + +config STM32_DAC3CH2_HRTIM_TRG3 + bool "DAC3CH2 HRTIM Trigger 3" + default n + +endif # STM32_HRTIM_DAC + +config STM32_DAC3CH2_TIMER + int "DAC3CH2 timer" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + range 2 8 + +config STM32_DAC3CH2_TIMER_FREQUENCY + int "DAC3CH2 timer frequency" + depends on !STM32_DAC3CH2_DMA_EXTERNAL + default 0 + +endif + +endmenu diff --git a/arch/arm/src/common/stm32/Kconfig.dfsdm b/arch/arm/src/common/stm32/Kconfig.dfsdm new file mode 100644 index 00000000000..49b02ad721d --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dfsdm @@ -0,0 +1,46 @@ +# +# STM32 digital filter configuration options. +# + +config STM32_ADC1_DFSDM_L4_CHIP + bool + default y if STM32_STM32L496XX || STM32_STM32L4XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_ADC1_DFSDM_L5_CHIP + bool + default y if STM32_STM32L596XX || STM32_STM32L5XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_ADC1_DFSDM_U5_CHIP + bool + default y if STM32_STM32U596XX || STM32_STM32U5XR + select STM32_ADC1_HAVE_OUTPUT_DFSDM + +config STM32_DFSDM1_FLT0 + bool "DFSDM1 Filter 0" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT1 + bool "DFSDM1 Filter 1" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 + select STM32_DFSDM + +config STM32_DFSDM1_FLT2 + bool "DFSDM1 Filter 2" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_FLT3 + bool "DFSDM1 Filter 3" + depends on (ARCH_CHIP_STM32L4 && STM32_DFSDM1 && !STM32_STM32L4X3) || (ARCH_CHIP_STM32L5 && STM32_DFSDM1 && !STM32_STM32L5X3) || (ARCH_CHIP_STM32U5 && STM32_DFSDM1 && !STM32_STM32U5X3) + select STM32_DFSDM + +config STM32_DFSDM1_DMA + bool "DFSDM1 DMA" + depends on STM32_COMMON_L4_L5_U5 && STM32_DFSDM1 && STM32_DFSDM + ---help--- + If DMA is selected, then the DFSDM may be configured to support + DMA transfer, which is necessary if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.dma b/arch/arm/src/common/stm32/Kconfig.dma new file mode 100644 index 00000000000..dcf96574021 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dma @@ -0,0 +1,118 @@ +# +# STM32 DMA configuration options. +# + +config STM32_DMA1_HAVE_CHAN8 + bool + default y if STM32_STM32G47XX + +config STM32_DMA2_HAVE_CHAN678 + bool + default y if STM32_STM32G47XX + +config STM32_DMACAPABLE + bool "Workaround non-DMA capable memory" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && ARCH_DMA + default STM32_STM32F4XXX && !STM32_CCMEXCLUDE if STM32_COMMON_LEGACY && ARCH_DMA + ---help--- + This option enables the DMA interface stm32_dmacapable that can be + used to check if it is possible to do DMA from the selected address. + Drivers then may use this information to determine if they should + attempt the DMA or fall back to a different transfer method. + +if STM32_DMA2D + +config STM32_DMA2D_NLAYERS + int "Number DMA2D overlays" + default 1 + range 1 256 + ---help--- + Number of supported DMA2D layer. + +config STM32_DMA2D_LAYER_SHARED + bool "Overlays shared memory region" + ---help--- + Several overlays can share the same memory region. + Setup a whole memory area (usually multiple size of the visible screen) + allows image preprocessing before they become visible by blit operation. + +config STM32_DMA2D_LAYER_PPLINE + int "Pixel per line" + default 1 + range 1 65535 + ---help--- + If you are using the DMA2D, then you must provide the pixel per line or + width of the overlay. + +config STM32_DMA2D_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the DMA2D, then you must provide the address + of the start of the DMA2D overlays framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_DMA2D_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of all DMA2D overlays. + +config STM32_DMA2D_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_L8 + default y + +config STM32_DMA2D_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL44 + default y + +config STM32_DMA2D_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP && STM32_LTDC_L1_AL88 + default y + +config STM32_DMA2D_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + default y + +config STM32_DMA2D_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + default y + +config STM32_DMA2D_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB15555 + default y + +config STM32_DMA2D_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + default y + +config STM32_DMA2D_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + default y + +config STM32_DMA2D_REGDEBUG + bool "DMA2D Register level debug" + depends on DEBUG_INFO && DEBUG_LCD + ---help--- + Output detailed register-level DMA2D device debug information. + +endif # STM32_DMA2D + +config STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED + bool "Do not disqualify DMA capability based on cache alignment" + depends on STM32_COMMON_F7_H7 && STM32_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH + ---help--- + This option configures the stm32_dmacapable to not disqualify + DMA operations on memory that is not dcache aligned based solely + on the starting address and byte count. + + Use this when ALL buffer extents are known to be aligned, but the + the count does not use the complete buffer. diff --git a/arch/arm/src/common/stm32/Kconfig.dts b/arch/arm/src/common/stm32/Kconfig.dts new file mode 100644 index 00000000000..eef17dd24d8 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.dts @@ -0,0 +1,99 @@ +# +# STM32 Digital Temperature Sensor (DTS) configuration options. +# + +config STM32_DTS_REFCLK_LSE + bool "Use LSE (32.768 kHz crystal) as DTS reference clock" + default n + ---help--- + Select the low-speed external (LSE) oscillator as the reference clock + for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will + measure FM(T) pulses over N LSE cycles. + + If disabled, the DTS will use the APB-bus clock (PCLK) as the reference + (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the + calibration prescaler ≤ 1 MHz. + +config STM32_DTS_SMP_TIME + int "DTS sampling time (TS1_SMP_TIME[3:0])" + default 1 + range 1 15 + ---help--- + Number of reference-clock cycles (PCLK or LSE) counted per + DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). + +config STM32_DTS_TRIGGER + int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" + default 0 + ---help--- + If non-zero, DTS will start measurements on the rising edge of + the selected hardware line. Values match RM0481 Table 275: + 0=Software Trigger, 1=LPTIM1_CH1, + 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. + +config STM32_DTS_LOW_THRESHOLD + int "DTS low-threshold (°C)" + default 0 + ---help--- + The temperature (in whole °C) below which the DTS window comparator will + assert the low-threshold flag (TS1_ITLF). To disable, set equal to 0. + +config STM32_DTS_HIGH_THRESHOLD + int "DTS high-threshold (°C)" + default 100 + ---help--- + The temperature (in whole °C) above which the DTS window comparator will + assert the high-threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. + +config STM32_DTS_ITEN_ITEF + bool "Enable DTS end-of-measurement interrupt (TS1_ITEF)" + default y + ---help--- + Enable the synchronous “end of measurement” interrupt for the + digital temperature sensor. When set, the driver will attach + and unmask TS1_ITEF and will call your ISR on every fresh sample. + +config STM32_DTS_ITEN_ITLF + bool "Enable DTS low-threshold interrupt (TS1_ITLF)" + default n + ---help--- + Enable the synchronous “low threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITLF so you can get notified whenever the measured value + drops below your programmed low-threshold. + +config STM32_DTS_ITEN_ITHF + bool "Enable DTS high-threshold interrupt (TS1_ITHF)" + default n + ---help--- + Enable the synchronous “high threshold crossed” interrupt for the + digital temperature sensor. When set, the driver will unmask + TS1_ITHF so you can get notified whenever the measured value + exceeds your programmed high-threshold. + +config STM32_DTS_AITEN_AITEF + bool "Enable DTS asynchronous end-of-measurement interrupt (TS1_AITEF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous end-of-measurement interrupt. This will + set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup + event when a conversion completes (in Stop/Sleep modes). + +config STM32_DTS_AITEN_AITLF + bool "Enable DTS asynchronous low-threshold interrupt (TS1_AITLF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous low-threshold comparator interrupt. This + will set TS1_AITLEN in DTS_ITENR and generate a wakeup event + when the measurement drops below your low threshold. + +config STM32_DTS_AITEN_AITHF + bool "Enable DTS asynchronous high-threshold interrupt (TS1_AITHF)" + depends on STM32_DTS_REFCLK_LSE + default n + ---help--- + Enable the asynchronous high-threshold comparator interrupt. This + will set TS1_AITHEN in DTS_ITENR and generate a wakeup event + when the measurement exceeds your high threshold. diff --git a/arch/arm/src/common/stm32/Kconfig.eth b/arch/arm/src/common/stm32/Kconfig.eth new file mode 100644 index 00000000000..e90f665e08d --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.eth @@ -0,0 +1,290 @@ +# +# STM32 common ETH options. +# + +config STM32_PHY_HAVE_POLLED + bool + +if STM32_ETHMAC + +config STM32_PHYADDR + int "PHY address" + default 1 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default 0 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config STM32_PHYINIT + bool "Board-specific PHY Initialization" + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + STM32_PHYINIT is defined in the configuration then the board specific logic must + provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function + one time before it first uses the PHY. + +config STM32_MII + bool "Use MII interface" + ---help--- + Support Ethernet MII interface. + +config STM32_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +if !STM32_AUTONEG + +config STM32_ETHFD + bool "Full duplex" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config STM32_ETH100MBPS + bool "100 Mbps" + ---help--- + If STM32_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +endif # !STM32_AUTONEG + +if STM32_AUTONEG + +config STM32_PHYSR + int "PHY Status Register Address (decimal)" + ---help--- + This must be provided if STM32_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config STM32_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if !STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config STM32_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config STM32_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the full or half duplex mode bits. + +config STM32_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !STM32_PHYSR_ALTCONFIG + +if STM32_PHYSR_ALTCONFIG + +config STM32_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if STM32_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config STM32_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config STM32_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config STM32_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config STM32_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if STM32_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # STM32_PHYSR_ALTCONFIG + +endif # STM32_AUTONEG + +config STM32_ETH_PTP + bool "Precision Time Protocol (PTP)" + ---help--- + Enables Precision Time Protocol (PTP) hardware timer. + +config STM32_ETH_ENHANCEDDESC + bool "Enable enhanced RX/TX descriptors" + depends on STM32_COMMON_LEGACY + default n + ---help--- + Enables double-length DMA descriptors that have space for packet + timestamps and checksum offloading. + +config STM32_ETH_PTP_GPIO + bool "PTP pulse-per-second output signal" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Enables pulse-per-second output on GPIO pin. + +config STM32_ETH_PTP_RTC_HIRES + bool "Use PTP timer as system high-resolution RTC" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP + default n + ---help--- + Uses the Ethernet peripheral PTP timer as the CONFIG_RTC_HIRES source. + This provides high resolution timestamps to clock_gettime(). + Note that PTP timer is disabled when Ethernet interface is down or + being reset. During this time g_rtc_enabled is set to false and system + uses the lower resolution system tick counter. + +config STM32_ETH_TIMESTAMP_RX + bool "Hardware timestamping of received packets" + depends on STM32_COMMON_LEGACY && STM32_ETH_PTP && NET_TIMESTAMP && STM32_ETH_ENHANCEDDESC + select ARCH_HAVE_NETDEV_TIMESTAMP + default n + ---help--- + Timestamp all received Ethernet packets. + Timestamp is available to application through SO_TIMESTAMP socket option. + +config STM32_RMII + bool + default !STM32_MII + +config STM32_ETHMAC_REGDEBUG + bool "Register-Level Debug" + depends on DEBUG_NET_INFO + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. + +endif # STM32_ETHMAC + +choice + prompt "MII clock configuration" + depends on STM32_MII + default STM32_MII_MCO if STM32_STM32F10XX + default STM32_MII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_MII_EXTCLK + +config STM32_MII_MCO + bool "Use MC0 as MII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the MII interface. Default: Use MC0 + +config STM32_MII_MCO1 + bool "Use MC01 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the MII interface. Default: Use MC01 + +config STM32_MII_MCO2 + bool "Use MC02 as MII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the MII interface. Default: Use MC01 + +config STM32_MII_EXTCLK + bool "External MII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for MII + clock. Default: Use MC0[1] + +endchoice + +choice + prompt "RMII clock configuration" + depends on STM32_RMII + default STM32_RMII_MCO if STM32_STM32F10XX + default STM32_RMII_MCO1 if STM32_STM32F20XX || STM32_STM32F4XXX + default STM32_RMII_EXTCLK + +config STM32_RMII_MCO + bool "Use MC0 as RMII clock" + depends on STM32_STM32F10XX + ---help--- + Use MCO to clock the RMII interface. Default: Use MC0 + +config STM32_RMII_MCO1 + bool "Use MC01 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO1 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_MCO2 + bool "Use MC02 as RMII clock" + depends on (STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_F7_H7_H5) + ---help--- + Use MCO2 to clock the RMII interface. Default: Use MC01 + +config STM32_RMII_EXTCLK + bool "External RMII clock" + ---help--- + Clocking is provided by external logic. Don't use MCO for RMII + clock. Default: Use MC0[1] + +endchoice + +config STM32_PHY_POLLING + bool "Support network monitoring by polling the PHY" + depends on (STM32_COMMON_F7_H7_H5) && STM32_ETHMAC && STM32_PHY_HAVE_POLLED + select ARCH_PHY_POLLED + ---help--- + Some boards may not have an interrupt connected to the PHY. + This option allows the network monitor to be used by polling the + the PHY for status. + +config STM32_ETH_HWCHECKSUM + bool "Enable ethernet hardware checksum" + depends on ARCH_CHIP_STM32H5 && STM32_ETHMAC + ---help--- + Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload + engine in the Ethernet MAC. + When enabled, hardware generates checksums for TX and checks RX frames. + Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, + NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid + redundant verification in the network stack. + +config STM32_NO_PHY + bool "MAC has no PHY" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + +config STM32_ETH_NRXDESC + int "Number of RX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 8 + ---help--- + Number of RX DMA descriptors to use. + +config STM32_ETH_NTXDESC + int "Number of TX descriptors" + depends on STM32_COMMON_H7_H5 && STM32_ETHMAC + default 4 + ---help--- + Number of TX DMA descriptors to use. diff --git a/arch/arm/src/common/stm32/Kconfig.fdcan b/arch/arm/src/common/stm32/Kconfig.fdcan new file mode 100644 index 00000000000..7910ef3b354 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.fdcan @@ -0,0 +1,518 @@ +# +# STM32 FDCAN configuration options. +# + +menu "FDCAN Driver Configuration" + depends on STM32_HAVE_FDCAN_H7 && (STM32_FDCAN1 || STM32_FDCAN2 || STM32_FDCAN3) + +menu "FDCAN1 Configuration" + depends on STM32_FDCAN1 + +config FDCAN1_BITRATE + int "FDCAN1 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN1_ARBI_BITRATE + int "FDCAN1 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN1_DATA_BITRATE + int "FDCAN1 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN1 + +menu "FDCAN2 Configuration" + depends on STM32_FDCAN2 + +config FDCAN2_BITRATE + int "FDCAN2 CAN bitrate" + depends on !NET_CAN_CANFD + default 100000 + +config FDCAN2_ARBI_BITRATE + int "FDCAN2 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 100000 + +config FDCAN2_DATA_BITRATE + int "FDCAN2 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN2 + +menu "FDCAN3 Configuration" + depends on STM32_FDCAN3 + +config FDCAN3_BITRATE + int "FDCAN3 CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config FDCAN3_ARBI_BITRATE + int "FDCAN3 CAN FD arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config FDCAN3_DATA_BITRATE + int "FDCAN3 CAN FD data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +endmenu # STM32_FDCAN3 + +endmenu # FDCAN Driver + +choice + prompt "FDCAN character driver or SocketCAN support" + depends on STM32_FDCAN + default STM32_FDCAN_CHARDRIVER + +config STM32_FDCAN_CHARDRIVER + bool "STM32 FDCAN character driver support" + select ARCH_HAVE_CAN_ERRORS + select CAN + +config STM32_FDCAN_SOCKET + bool "STM32 FDCAN SocketCAN support" + select NET_CAN_HAVE_ERRORS + select NET_CAN_HAVE_CANFD + +endchoice # FDCAN character driver or SocketCAN support + +if STM32_FDCAN1 + +choice + prompt "FDCAN1 frame format" + default STM32_FDCAN1_ISO11898_1 + +config STM32_FDCAN1_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN1_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN1 frame format + +choice + prompt "FDCAN1 mode" + default STM32_FDCAN1_CLASSIC + +config STM32_FDCAN1_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN1_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN1_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN1 mode + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +choice + prompt "FDCAN2 frame format" + default STM32_FDCAN2_ISO11898_1 + +config STM32_FDCAN2_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN2_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN2 frame format + +choice + prompt "FDCAN2 mode" + default STM32_FDCAN2_CLASSIC + +config STM32_FDCAN2_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN2_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN2_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN2 mode + +endif # STM32_FDCAN2 + +config STM32_FDCAN_REGDEBUG + bool "FDCAN register-level debug" + depends on STM32_FDCAN && (DEBUG_CAN_INFO || DEBUG_NET_INFO) + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +config STM32_FDCAN_QUEUE_MODE + bool "FDCAN QUEUE mode (vs FIFO mode)" + depends on STM32_FDCAN + +config STM32_FDCAN_LOOPBACK + bool "Enable FDCAN loopback mode" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default n + ---help--- + Enable the FDCAN local loopback mode for testing purposes. + Requires a further choice of internal or external loopback mode. + +choice + prompt "FDCAN Loopback Mode" + depends on STM32_FDCAN_LOOPBACK + default STM32_FDCAN_LOOPBACK_INTERNAL + +config STM32_FDCAN_LOOPBACK_INTERNAL + bool "Internal loopback mode" + ---help--- + Enable internal loopback mode, where both Tx and Rx are + disconnected from the CAN bus. This can be used for a "Hot Selftest", + meaning the FDCAN can be used without affecting a running CAN bus. + + All transmitted frames are treated as received frames and processed + accordingly. + +config STM32_FDCAN_LOOPBACK_EXTERNAL + bool "External loopback mode" + ---help--- + Enable external loopback mode, where the Rx pin is disconnected from + the CAN bus but the Tx pin remains connected. + + All transmitted frames are treated as received frames and processed + accordingly. + +endchoice # FDCAN Loopback Mode + +choice + prompt "FDCAN WorkQueue Selection" + depends on ARCH_CHIP_STM32H7 && STM32_FDCAN + default STM32_FDCAN_LPWORK + +config STM32_FDCAN_LPWORK + bool "Use LP work queue" + ---help--- + Use the low-priority (LP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +config STM32_FDCAN_HPWORK + bool "Use HP work queue" + ---help--- + Use the high-priority (HP) work queue for reception and transmission + of new frames and for processing of transmission timeouts. + +endchoice # FDCAN WorkQueue Selection + +if STM32_FDCAN1 + +config STM32_FDCAN1_LOOPBACK + bool "Enable FDCAN1 loopback mode" + ---help--- + Enable the FDCAN1 local loopback mode for testing purposes. + +config STM32_FDCAN1_BITRATE + int "FDCAN1 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if STM32_FDCAN1 is defined. + +config STM32_FDCAN1_AUTO_BIT_TIMING + bool "FDCAN1 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN1 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 nominal bit timing" + +config STM32_FDCAN1_NTSEG1 + int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NTSEG2 + int "FDCAN1 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_NSJW + int "FDCAN1 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN1_AUTO_BIT_TIMING + +config STM32_FDCAN1_DBITRATE + int "FDCAN1 data bitrate" + depends on CAN_FD && STM32_FDCAN1_FD_BRS + default 2000000 + ---help--- + FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +comment "FDCAN1 data bit timing" + +config STM32_FDCAN1_DTSEG1 + int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DTSEG2 + int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN1_DSJW + int "FDCAN1 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN1_FD_BRS && !STM32_FDCAN1_AUTO_BIT_TIMING + +endif # STM32_FDCAN1 + +if STM32_FDCAN2 + +config STM32_FDCAN2_LOOPBACK + bool "Enable FDCAN2 loopback mode" + ---help--- + Enable the FDCAN2 local loopback mode for testing purposes. + +config STM32_FDCAN2_BITRATE + int "FDCAN2 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if STM32_FDCAN2 is defined. + +config STM32_FDCAN2_AUTO_BIT_TIMING + bool "FDCAN2 automatic bit timing" + depends on ARCH_CHIP_STM32H5 + default y + ---help--- + Automatically determine FDCAN2 bit timing (nominal and data) + based on bitrate. + +if !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 nominal bit timing" + +config STM32_FDCAN2_NTSEG1 + int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NTSEG2 + int "FDCAN2 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_NSJW + int "FDCAN2 synchronization jump width" + default 1 + range 1 128 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +endif # !STM32_FDCAN2_AUTO_BIT_TIMING + +config STM32_FDCAN2_DBITRATE + int "FDCAN2 data bitrate" + depends on CAN_FD && STM32_FDCAN2_FD_BRS + default 2000000 + ---help--- + FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +comment "FDCAN2 data bit timing" + +config STM32_FDCAN2_DTSEG1 + int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DTSEG2 + int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN2_DSJW + int "FDCAN2 fast synchronization jump width" + default 2 + range 1 15 + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN2_FD_BRS && !STM32_FDCAN2_AUTO_BIT_TIMING + +endif # STM32_FDCAN2 + +if STM32_FDCAN3 + +choice + prompt "FDCAN3 frame format" + default STM32_FDCAN3_ISO11898_1 + +config STM32_FDCAN3_ISO11898_1 + bool "ISO11898-1" + ---help--- + Enable ISO11898-1 frame format + +config STM32_FDCAN3_NONISO_FORMAT + bool "Non ISO" + ---help--- + Enable Non ISO, Bosch CAN FD Specification V1.0 + +endchoice # FDCAN3 frame format + +choice + prompt "FDCAN3 mode" + default STM32_FDCAN3_CLASSIC + +config STM32_FDCAN3_CLASSIC + bool "Classic CAN" + ---help--- + Enable Classic CAN mode + +config STM32_FDCAN3_FD + bool "CAN FD" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode + +config STM32_FDCAN3_FD_BRS + bool "CAN FD with fast bit rate switching" + depends on CAN_FD || NET_CAN_CANFD + ---help--- + Enable CAN FD mode with fast bit rate switching mode. + +endchoice # FDCAN3 mode + +config STM32_FDCAN3_LOOPBACK + bool "Enable FDCAN3 loopback mode" + default n + ---help--- + Enable the FDCAN3 local loopback mode for testing purposes. + +config STM32_FDCAN3_BITRATE + int "FDCAN3 bitrate" + default 500000 + range 0 1000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if STM32_FDCAN3 is defined. + +comment "FDCAN3 nominal bit timing" + +config STM32_FDCAN3_NTSEG1 + int "FDCAN3 NTSEG1 (PropSeg + PhaseSeg1)" + default 6 + range 1 256 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NTSEG2 + int "FDCAN3 NTSEG2 (PhaseSeg2)" + default 7 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_NSJW + int "FDCAN3 synchronization jump width" + default 1 + range 1 128 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DBITRATE + int "FDCAN3 data bitrate" + depends on CAN_FD && STM32_FDCAN3_FD_BRS + default 2000000 + ---help--- + FDCAN3 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). + +if CAN_FD && STM32_FDCAN3_FD_BRS + +comment "FDCAN3 data bit timing" + +config STM32_FDCAN3_DTSEG1 + int "FDCAN3 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" + default 4 + range 1 31 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DTSEG2 + int "FDCAN3 DTSEG2 (PhaseSeg2 of data phase)" + default 4 + range 1 15 if STM32_STM32G4XXX + ---help--- + The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). + +config STM32_FDCAN3_DSJW + int "FDCAN3 fast synchronization jump width" + default 2 + range 1 15 if STM32_STM32G4XXX + ---help--- + The duration of a synchronization jump is Tcan_clk x DSJW. + +endif # CAN_FD && STM32_FDCAN3_FD_BRS + +endif # STM32_FDCAN3 diff --git a/arch/arm/src/common/stm32/Kconfig.flash b/arch/arm/src/common/stm32/Kconfig.flash new file mode 100644 index 00000000000..1dc3d64bae9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.flash @@ -0,0 +1,162 @@ +# +# STM32 flash configuration options. +# + +# Common STM32 flash size designator options. + +config STM32_FLASH_CONFIG_DEFAULT + bool "Default or device-derived flash size" + default n + +config STM32_FLASH_CONFIG_4 + bool "Flash size designator 4, 16 KiB" + default n + +config STM32_FLASH_CONFIG_6 + bool "Flash size designator 6, 32 KiB" + default n + +config STM32_FLASH_CONFIG_8 + bool "Flash size designator 8, 64 KiB" + default n + +config STM32_FLASH_CONFIG_B + bool "Flash size designator B, 128 KiB" + default n + +config STM32_FLASH_CONFIG_C + bool "Flash size designator C, 256 KiB" + default n + +config STM32_FLASH_CONFIG_C_320 + bool "STM32WB flash size designator C, 320 KiB variant" + default n + +config STM32_FLASH_CONFIG_D + bool "Flash size designator D, 384 KiB" + default n + +config STM32_FLASH_CONFIG_E + bool "Flash size designator E, 512 KiB" + default n + +config STM32_FLASH_CONFIG_F + bool "Flash size designator F, 768 KiB" + default n + +config STM32_FLASH_CONFIG_G + bool "Flash size designator G, 1024 KiB" + default n + +config STM32_FLASH_CONFIG_I + bool "Flash size designator I, 2048 KiB" + default n + +config STM32_FLASH_CONFIG_Y + bool "Flash size designator Y, 640 KiB" + default n + +config STM32_FLASH_CONFIG_Z + bool "Legacy STM32 flash size designator Z" + default n + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" if ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default y if ARCH_CHIP_STM32F7 || STM32_COMMON_F7_H7_H5 + default y if STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default y if ARCH_CHIP_STM32WL5 + default n + +choice + prompt "Override Flash Size Designator" + depends on STM32_FLASH_OVERRIDE + default STM32_FLASH_OVERRIDE_DEFAULT + ---help--- + STM32 parts numbering ends with a number or letter that designates + the internal FLASH size. Select "Default" to use the size from + the selected chip. Select another designator only when the part + variant differs from the listed chip selection. + +config STM32_FLASH_OVERRIDE_DEFAULT + bool "Default" + +config STM32_FLASH_OVERRIDE_6 + bool "6 32KiB" + +config STM32_FLASH_OVERRIDE_8 + bool "8 64KiB" + +config STM32_FLASH_OVERRIDE_B + bool "B 128KiB" + +config STM32_FLASH_OVERRIDE_C + bool "C 256KiB" + +config STM32_FLASH_OVERRIDE_C_320 + bool "C 320KiB" + +config STM32_FLASH_OVERRIDE_E + bool "E 512KiB" + +config STM32_FLASH_OVERRIDE_G + bool "G 1024KiB" + +config STM32_FLASH_OVERRIDE_I + bool "I 2048KiB" + +config STM32_FLASH_OVERRIDE_Y + bool "Y 640KiB" + +endchoice # Override Flash Size Designator + +config STM32_FLASH_ART_ACCELERATOR + bool "Flash ART Accelerator" + depends on STM32_HAVE_FLASH_ART_ACCELERATOR + default n + ---help--- + ART Accelerator on the flash memory ITCM interface accelerates code execution + with a system of instruction prefetch and cache lines. + + Enable if code and/or read-only data is accessed through ITCM bus instead of + AXIM bus. + +config STM32_FLASH_PREFETCH + bool "Enable FLASH Pre-fetch" + depends on STM32_STM32F20XX || STM32_STM32F4XXX || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default STM32_STM32F427 || STM32_STM32F429 || STM32_STM32F446 + default y + ---help--- + Enable FLASH prefetch in F2 and F4 parts (FLASH pre-fetch is always enabled + on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch + properly and enabling this option may interfere with ADC accuracy. + +config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW + bool "Workaround for FLASH data cache corruption" + depends on STM32_FLASH_DCACHE && (STM32_STM32F20XX || STM32_STM32F4XXX || (ARCH_CHIP_STM32L4 && (STM32_STM32L4X5 || STM32_STM32L4X6 || STM32_STM32L4XR))) + ---help--- + Enable the workaround to fix flash data cache corruption when reading + from one flash bank while writing on other flash bank. See your STM32 + errata to check if your STM32 is affected by this problem. + +config STM32_PROGMEM + bool "Flash PROGMEM support" + depends on STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM || STM32_COMMON_F7_H7_H5 + select MTD if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + select MTD_PROGMEM if STM32_COMMON_F0_L0_G0_C0 && ARCH_HAVE_PROGMEM + ---help--- + Add progmem support, start block and end block options are provided to + obtain a uniform flash memory mapping. + +config STM32_FLASH_ICACHE + bool "Enable FLASH Instruction Cache" + default y + depends on STM32_HAVE_FLASH_ICACHE + ---help--- + Enable the FLASH instruction cache. + +config STM32_FLASH_DCACHE + bool "Enable FLASH Data Cache" + default y + depends on STM32_HAVE_FLASH_DCACHE + ---help--- + Enable the FLASH data cache. diff --git a/arch/arm/src/common/stm32/Kconfig.foc b/arch/arm/src/common/stm32/Kconfig.foc new file mode 100644 index 00000000000..79e61e292e4 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.foc @@ -0,0 +1,197 @@ +# +# STM32 common FOC options. +# + +config STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + bool + +config STM32_FOC_USE_TIM1 + bool + select STM32_TIM1 + select STM32_TIM1_PWM + select STM32_TIM1_CHANNEL1 + select STM32_TIM1_CHANNEL2 + select STM32_TIM1_CHANNEL3 + select STM32_TIM1_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1OUT + select STM32_TIM1_CH2OUT + select STM32_TIM1_CH3OUT + select STM32_TIM1_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM1_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM1_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM1 generates PWM for the FOC + +config STM32_FOC_USE_TIM8 + bool + select STM32_TIM8 + select STM32_TIM8_PWM + select STM32_TIM8_CHANNEL1 + select STM32_TIM8_CHANNEL2 + select STM32_TIM8_CHANNEL3 + select STM32_TIM8_CHANNEL4 if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1OUT + select STM32_TIM8_CH2OUT + select STM32_TIM8_CH3OUT + select STM32_TIM8_CH4OUT if STM32_FOC_ADC_CCR4 + select STM32_TIM8_CH1NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH2NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + select STM32_TIM8_CH3NOUT if STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + The TIM8 generates PWM for the FOC + +config STM32_FOC_USE_ADC1 + bool + select STM32_ADC1 + select STM32_ADC1_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC1_JEXTSEL + +config STM32_FOC_USE_ADC2 + bool + select STM32_ADC2 + select STM32_ADC2_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC2_JEXTSEL + +config STM32_FOC_USE_ADC3 + bool + select STM32_ADC3 + select STM32_ADC3_SCAN if ARCH_CHIP_STM32F7 || STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_ADC3_JEXTSEL + +# +# + +choice + prompt "FOC ADC trigger selection" + depends on STM32_FOC + default STM32_FOC_ADC_TRGO + +config STM32_FOC_ADC_CCR4 + bool "FOC uses CCR4 as ADC trigger" + ---help--- + This option uses the software frequency prescaler and is + not possible for 4-phase output. + +config STM32_FOC_ADC_TRGO + bool "FOC uses TRGO as ADC trigger" + depends on STM32_HAVE_IP_ADC_M3M4_V2 || ARCH_CHIP_STM32F7 || (STM32_HAVE_IP_ADC_M3M4_V1 && !STM32_FOC_FOC1) + select STM32_PWM_TRGO + ---help--- + This option allows you to use higher PWM frequency and works for 4-phase output. + It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). + +endchoice # "FOC ADC trigger selection" + +choice + prompt "FOC0 device ADC selection" + depends on STM32_FOC_FOC0 + default STM32_FOC_FOC0_ADC1 + +config STM32_FOC_FOC0_ADC1 + bool "FOC0 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC0_ADC2 + bool "FOC0 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC0_ADC3 + bool "FOC0 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC0_ADC4 + bool "FOC0 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +choice + prompt "FOC1 device ADC selection" + depends on STM32_FOC_FOC1 + default STM32_FOC_FOC1_ADC2 + +config STM32_FOC_FOC1_ADC1 + bool "FOC1 uses ADC1" + depends on STM32_HAVE_ADC1 + select STM32_FOC_USE_ADC1 + +config STM32_FOC_FOC1_ADC2 + bool "FOC1 uses ADC2" + depends on STM32_HAVE_ADC2 + select STM32_FOC_USE_ADC2 + +config STM32_FOC_FOC1_ADC3 + bool "FOC1 uses ADC3" + depends on STM32_HAVE_ADC3 + select STM32_FOC_USE_ADC3 + +config STM32_FOC_FOC1_ADC4 + bool "FOC1 uses ADC4" + depends on STM32_HAVE_ADC4 + select STM32_FOC_USE_ADC4 + +endchoice # "FOC0 device ADC selection" + +menuconfig STM32_FOC + bool "STM32 lower-half FOC support" + depends on STM32_HAVE_COMMON_FOC || ARCH_CHIP_STM32F7 + select ARCH_IRQPRIO + select STM32_ADC + select STM32_PWM_MULTICHAN + select STM32_PWM_LL_OPS + select STM32_ADC_LL_OPS + select STM32_ADC_CHANGE_SAMPLETIME + select STM32_ADC_NO_STARTUP_CONV + +config STM32_FOC_FOC0 + bool "FOC0 device (TIM1 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM1 + select STM32_FOC_USE_TIM1 + ---help--- + Enable support for FOC0 device that uses TIM1 for PWM modulation + +config STM32_FOC_FOC1 + bool "FOC1 device (TIM8 for PWM modulation)" + depends on STM32_FOC && STM32_HAVE_TIM8 + select STM32_FOC_USE_TIM8 + ---help--- + Enable support for FOC1 device that uses TIM8 for PWM modulation + +config STM32_FOC_HAS_PWM_COMPLEMENTARY + bool "FOC PWM has complementary outputs" + depends on STM32_FOC + ---help--- + Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) + +# hidden variables and automatic configuration + +if STM32_FOC + +config STM32_FOC_USE_ADC4 + bool + default n + select STM32_ADC4 + select STM32_ADC3_JEXTSEL + +config STM32_FOC_G4_ADCCHAN0_WORKAROUND + bool "FOC G4 ADC channel 0 unwanted conversion workaround" + default n + depends on STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + ---help--- + Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 + conversion when a regular conversion is interrupted by an injected conversion. + This FOC implementation uses injected conversion to sample phase currents + and allows user to use regular conversion as an auxiliary analog conversion. + In this case, there is a certain probability that regular conversion will be + interrupted by an injected conversion that will lead to an incorrect reading + of phase currents. + + This workaround inserts a dummy conversion at the beginning of the injected + sequence. For more details look at the chip errata documents. + +endif #STM32_FOC diff --git a/arch/arm/src/common/stm32/Kconfig.gpio b/arch/arm/src/common/stm32/Kconfig.gpio new file mode 100644 index 00000000000..f7d3b676683 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.gpio @@ -0,0 +1,9 @@ +# +# STM32 GPIO configuration options. +# + +config STM32_GPIO_HAVE_PORTD + bool + +config STM32_GPIO_HAVE_PORTE + bool diff --git a/arch/arm/src/common/stm32/Kconfig.have b/arch/arm/src/common/stm32/Kconfig.have new file mode 100644 index 00000000000..2772bd7cd82 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.have @@ -0,0 +1,1191 @@ +# +# STM32 hidden hardware-capability flags (single source of truth). +# + +# All STM32_HAVE_* / STM32_HAVE_IP_* symbols are defined here. They are +# prompt-less bool selectors describing what hardware exists on a chip and +# which IP-core version a peripheral uses. Family Kconfig files +# (arch/arm/src/stm32/Kconfig) "select" these symbols to describe their +# silicon; never add a prompt here. User-visible peripheral selection lives +# in Kconfig.periph and per-peripheral options in Kconfig.. +# +# Naming: an STM32_HAVE_IP__V symbol names the IP-core VERSION only; +# it must NOT encode the CPU core, because a given IP version is the same +# silicon regardless of whether it sits next to a Cortex-M0 or M3/M4 core (e.g. +# SPI v2 is SPI v2 on both STM32F0 and STM32F4). When a core-specific driver +# .c file or register header has to be chosen, use the standard NuttX core +# symbols (CONFIG_ARCH_CORTEXM0 for M0, CONFIG_ARCH_CORTEXM3 / ARCH_CORTEXM4 +# otherwise) -- not an STM32_HAVE_IP_* symbol. +# +# Two-level selection is intentional and must NOT be "cleaned up" as a +# duplicate: some peripherals use a "register-set" symbol that picks the +# hardware header (e.g. STM32_HAVE_IP_FLASH_M3M4_V1 -> hardware/stm32_flash.h, +# STM32_HAVE_IP_DMA_V1/_V2 -> hardware/stm32_dma.h) AND a separate +# "driver-variant" symbol that picks the .c file in Make.defs (e.g. +# STM32_HAVE_IP_FLASH_M3M4_F2F4, STM32_HAVE_IP_DMA_V2_STREAM). A family +# legitimately selects one of each. +# +# Within a single mutually-exclusive group (the #elif dispatch in +# hardware/stm32_.h and the else-if chain in Make.defs), a family must +# select exactly one member; the dispatch headers carry #error guards that +# enforce this at build time. +# + +# ADC capabilities + +config STM32_HAVE_ADC_TIMTRIG_TRGO2 + bool + default y if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_ADC_TIMTRIG_TRGO + bool + default y if ARCH_CHIP_STM32H7 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_ADC_CHANNEL + bool + +config STM32_HAVE_ADC_L4 + bool + +config STM32_HAVE_ADC_H5 + bool + +config STM32_HAVE_ADC2 + bool + +config STM32_HAVE_ADC3 + bool + +config STM32_HAVE_ADC4 + bool + +config STM32_HAVE_ADC5 + bool + +config STM32_HAVE_ADC_OVERSAMPLE + bool + default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 + +config STM32_HAVE_SDADC1 + bool + +config STM32_HAVE_SDADC2 + bool + +config STM32_HAVE_SDADC3 + bool + +config STM32_HAVE_IP_SDADC_M3M4_V1 + bool + +config STM32_HAVE_IP_ADC_M3M4_V1 + bool + select STM32_HAVE_ADC1 + +config STM32_HAVE_IP_ADC_M3M4_V1_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V1 + +config STM32_HAVE_IP_ADC_M3M4_V2 + bool + select STM32_HAVE_ADC1 + +config STM32_HAVE_IP_ADC_M3M4_V2_BASIC + bool + select STM32_HAVE_IP_ADC_M3M4_V2 + +config STM32_HAVE_IP_ADC_M0_V1 + bool + +config STM32_HAVE_ADC1 + bool + +# BLE capabilities + +config STM32_HAVE_BLE + bool + +# CACHE capabilities + +config STM32_HAVE_DCACHE1 + bool + +config STM32_HAVE_ICACHE + bool + +# CAN capabilities + +config STM32_HAVE_CAN1 + bool + +config STM32_HAVE_CAN2 + bool + +config STM32_HAVE_CAN3 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M0_V1 + bool + +config STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + bool + +# CEC capabilities + +config STM32_HAVE_CEC + bool + +# CLOCK capabilities + +config STM32_HAVE_CSI + bool + +config STM32_HAVE_CRS + bool + +config STM32_HAVE_HSI48 + bool + +config STM32_HAVE_IP_HSI48_M0_V1 + bool + +# COMP capabilities + +config STM32_HAVE_COMP1 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP2 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP3 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP4 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP5 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP6 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_COMP7 + bool + select STM32_HAVE_COMP + +config STM32_HAVE_IP_COMP_M3M4_V1 + bool + +config STM32_HAVE_IP_COMP_M3M4_V2 + bool + +config STM32_HAVE_IP_COMP_M0_V1 + bool + +config STM32_HAVE_COMP + bool + select STM32_HAVE_SYSCFG + +# CORDIC capabilities + +config STM32_HAVE_CORDIC + bool + +config STM32_HAVE_FMAC + bool + +config STM32_HAVE_IP_CORDIC_M3M4_V1 + bool + +# DAC capabilities + +config STM32_HAVE_DAC_LL_OPS + bool + +config STM32_HAVE_IP_DAC_M3M4_V1 + bool + +config STM32_HAVE_IP_DAC_M3M4_V2 + bool + +config STM32_HAVE_IP_DAC_M0_V1 + bool + +config STM32_HAVE_DAC1 + bool + +config STM32_HAVE_DAC2 + bool + +config STM32_HAVE_DAC3 + bool + +config STM32_HAVE_DAC4 + bool + +# DBGMCU capabilities + +config STM32_HAVE_IP_DBGMCU_M0_V1 + bool + +config STM32_HAVE_IP_DBGMCU_M3M4_V1 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + +config STM32_HAVE_IP_DBGMCU_M3M4_V2 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +config STM32_HAVE_IP_DBGMCU_M3M4_V3 + bool + select STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + +# DCMI capabilities + +config STM32_HAVE_DCMI_PSSI + bool + +config STM32_HAVE_DCMI + bool + +config STM32_HAVE_IP_DCMI_V1 + bool + +# DFSDM capabilities + +config STM32_HAVE_MDF1 + bool + +config STM32_HAVE_ADF1 + bool + +config STM32_HAVE_DFSDM1 + bool + +# DMA capabilities + +config STM32_HAVE_MDMA + bool + +config STM32_HAVE_BDMA + bool + +config STM32_HAVE_GPADMA1 + bool + +config STM32_HAVE_LPDMA1 + bool + +config STM32_HAVE_DMA1 + bool + +config STM32_HAVE_DMA2 + bool + +config STM32_HAVE_DMA2D + bool + +config STM32_HAVE_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1 + bool + +config STM32_HAVE_IP_DMA_V2 + bool + +config STM32_HAVE_IP_DMA_V1_7CH + bool + +config STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V1_8CH + bool + +config STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + bool + +config STM32_HAVE_IP_DMA_V2_STREAM + bool + +config STM32_HAVE_IP_DMA2D_M3M4_V1 + bool + +# DTS capabilities + +config STM32_HAVE_DTS + bool + +# ETH capabilities + +config STM32_HAVE_ETHMAC + bool + +config STM32_HAVE_IP_ETHMAC_M3M4_V1 + bool + +config STM32_HAVE_ETHRNET + bool + +config STM32_HAVE_ETHERNET + bool + +# FDCAN capabilities + +config STM32_HAVE_FDCAN_H7 + bool + +config STM32_HAVE_FDCAN1 + bool + +config STM32_HAVE_FDCAN2 + bool + +config STM32_HAVE_FDCAN3 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + bool + +config STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + bool + +# FLASH capabilities + +config STM32_HAVE_FLASH_ART_ACCELERATOR + bool + +config STM32_HAVE_FLASH + bool + +config STM32_HAVE_OTA_PARTITION + bool + +config STM32_HAVE_IP_FLASH_M0_V1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_V1 + bool + +config STM32_HAVE_IP_FLASH_M0_G0C0 + bool + +config STM32_HAVE_IP_FLASH_M3M4_L1 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F1F3 + bool + +config STM32_HAVE_IP_FLASH_M3M4_F2F4 + bool + +config STM32_HAVE_IP_FLASH_M3M4_G4 + bool + +config STM32_HAVE_OTFDEC1 + bool + +config STM32_HAVE_OTFDEC2 + bool + +config STM32_HAVE_FLASH_ICACHE + bool + +config STM32_HAVE_FLASH_DCACHE + bool + +# FOC capabilities + +config STM32_HAVE_COMMON_FOC + bool + +# GPIO capabilities + +config STM32_HAVE_LPGPIO1 + bool + +config STM32_HAVE_GPIOF + bool + +config STM32_HAVE_GPIOG + bool + +# HRTIM capabilities + +config STM32_HAVE_HRTIM1 + bool + +config STM32_HAVE_IP_HRTIM_M3M4_V1 + bool + +# I2C capabilities + +config STM32_HAVE_I2C_H5 + bool + +config STM32_HAVE_I2C5 + bool + +config STM32_HAVE_I2C6 + bool + +config STM32_HAVE_IP_I2C_M3M4_V1 + bool + +config STM32_HAVE_IP_I2C_M3M4_V2 + bool + +config STM32_HAVE_IP_I2C_M0_V1 + bool + +config STM32_HAVE_I2C1 + bool + +config STM32_HAVE_I2C2 + bool + +config STM32_HAVE_I2C3 + bool + +config STM32_HAVE_I2C4 + bool + +# IPCC capabilities + +config STM32_HAVE_HSEM + bool + +config STM32_HAVE_CM4 + bool + +config STM32_HAVE_MBOX + bool + +config STM32_HAVE_IPCC + bool + +# JPEG capabilities + +config STM32_HAVE_JPEG + bool + +# LPUART capabilities + +config STM32_HAVE_LPUART1 + bool + +config STM32_HAVE_LPUART2 + bool + +config STM32_HAVE_LPUART + bool + +# LTDC capabilities + +config STM32_HAVE_LTDC + bool + +config STM32_HAVE_IP_LTDC_M3M4_V1 + bool + +config STM32_HAVE_DSIHOST + bool + +config STM32_HAVE_LCD + bool + +# MEMORY capabilities + +config STM32_HAVE_RAMCFG + bool + +config STM32_HAVE_SRAM1 + bool + +config STM32_HAVE_SRAM2 + bool + +config STM32_HAVE_SRAM3 + bool + +config STM32_HAVE_SRAM5 + bool + +config STM32_HAVE_CCM + bool + +config STM32_HAVE_FMC + bool + +config STM32_HAVE_FSMC + bool + +config STM32_HAVE_IP_CCM_M3M4_V1 + bool + +config STM32_HAVE_IP_FMC_M3M4_V1 + bool + +config STM32_HAVE_IP_FSMC_M3M4_V1 + bool + +config STM32_HAVE_IP_BBSRAM_M3M4_V1 + bool + +config STM32_HAVE_IP_BKP_M3M4_V1 + bool + +config STM32_HAVE_BKPSRAM + bool + +config STM32_HAVE_BKP + bool + +config STM32_HAVE_COMMON_WASTE + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_IP_DFUMODE_M3M4_V1 + bool + +config STM32_HAVE_SRAM2A + bool + +config STM32_HAVE_SRAM2B + bool + +# OPAMP capabilities + +config STM32_HAVE_OPAMP1 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP2 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP3 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP4 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP5 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_OPAMP6 + bool + select STM32_HAVE_SYSCFG + +config STM32_HAVE_IP_OPAMP_M3M4_V1 + bool + +# POWER capabilities + +config STM32_HAVE_PWR + bool + +config STM32_HAVE_OVERDRIVE + bool + +config STM32_HAVE_VREF + bool + +config STM32_HAVE_VREFINT + bool + +config STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY + bool + +config STM32_HAVE_IP_PWR_M0_V1 + bool + +config STM32_HAVE_IP_PWR_G0 + bool + +config STM32_HAVE_IP_PWR_M3M4_V1 + bool + +config STM32_HAVE_SMPS + bool + +# QSPI capabilities + +config STM32_HAVE_QSPI1 + bool + +config STM32_HAVE_OCTOSPIM + bool + +config STM32_HAVE_OCTOSPI1 + bool + +config STM32_HAVE_OCTOSPI2 + bool + +config STM32_HAVE_QSPI + bool + +# CRC capabilities + +config STM32_HAVE_CRC + bool + +# RNG capabilities + +config STM32_HAVE_RNG + bool + +config STM32_HAVE_IP_RNG_M0_V1 + bool + +config STM32_HAVE_IP_RNG_M3M4_V1 + bool + +# RTC capabilities + +config STM32_HAVE_RTC + bool + +config STM32_HAVE_RTC_MAGIC + bool + +config STM32_HAVE_RTCAPB + bool + +config STM32_HAVE_RTC_COUNTER + bool + +config STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M0_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_V1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_L1 + bool + +config STM32_HAVE_IP_RTCC_M3M4_F4 + bool + +config STM32_HAVE_IP_RTC_M3M4_V1 + bool + +config STM32_HAVE_RTC_SUBSECONDS + bool + select ARCH_HAVE_RTC_SUBSECONDS + +# SAI capabilities + +config STM32_HAVE_SAIPLL + bool + +config STM32_HAVE_SAI + bool + +config STM32_HAVE_I2S3 + bool + +config STM32_HAVE_I2S2 + bool + +config STM32_HAVE_SPI2S2 + bool + +config STM32_HAVE_I2SPLL + bool + +config STM32_HAVE_IP_I2S_M3M4_V1 + bool + +config STM32_HAVE_SAI1 + bool + +config STM32_HAVE_SAI2 + bool + +# SDIO capabilities + +config STM32_HAVE_SDIO + bool + +config STM32_HAVE_SDMMC1 + bool + +config STM32_HAVE_SDMMC2 + bool + +config STM32_HAVE_IP_SDIO_M3M4_V1 + bool + +# SECURITY capabilities + +config STM32_HAVE_FIREWALL + bool + +config STM32_HAVE_GTZC1 + bool + +config STM32_HAVE_GTZC2 + bool + +config STM32_HAVE_PKA + bool + +config STM32_HAVE_SAES + bool + +config STM32_HAVE_AES + bool + +config STM32_HAVE_CRYP + bool + +config STM32_HAVE_IP_AES_M0_V1 + bool + +config STM32_HAVE_IP_AES_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_M3M4_V1 + bool + +config STM32_HAVE_IP_CRYPTO_H7 + bool + +config STM32_HAVE_HASH + bool + +# SPI capabilities + +config STM32_HAVE_SPI_CORE_DMA + bool + default y if STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0 + default y if STM32_COMMON_F7_H7_H5 + default y if ARCH_CHIP_STM32WL5 + default y if STM32_COMMON_L4_L5_U5 && STM32_SPI + default y if ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) && STM32_DMA + +config STM32_HAVE_SPI_DMA_FAMILY_WL5 + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WL5 + +config STM32_HAVE_SPI_DMA_FAMILY + bool + default y if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + default y if STM32_COMMON_H7_H5 + +config STM32_HAVE_IP_SPI_V1 + bool + +config STM32_HAVE_IP_SPI_V2 + bool + +config STM32_HAVE_IP_SPI_V3 + bool + +config STM32_HAVE_IP_SPI_V4 + bool + +config STM32_HAVE_SPI1 + bool + +config STM32_HAVE_SPI2 + bool + +config STM32_HAVE_SPI3 + bool + +config STM32_HAVE_SPI4 + bool + +config STM32_HAVE_SPI5 + bool + +config STM32_HAVE_SPI6 + bool + +# SYSTEM capabilities + +config STM32_HAVE_IP_EXTI_V1 + bool + +config STM32_HAVE_IP_EXTI_V2 + bool + +config STM32_HAVE_IP_GPIO_M0_V1 + bool + +config STM32_HAVE_IP_GPIO_M3M4_V1 + bool + +config STM32_HAVE_SYSCFG + bool + +config STM32_HAVE_IP_SYSCFG_M3M4_V1 + bool + +config STM32_HAVE_IOCOMPENSATION + bool + +# TIM capabilities + +config STM32_HAVE_TIM_PWM + bool + default y if STM32_COMMON_FULL_FEATURED + +config STM32_HAVE_TIM_PWM_NO_F0 + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_ADVANCED + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_SINGLECHAN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_INTERNAL + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5 + +config STM32_HAVE_TIM_PWM_STM32PWM + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + +config STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + bool + default y if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + +config STM32_HAVE_TIM_PWM_CHMODE_LEGACY + bool + default y if STM32_HAVE_IP_TIMERS && !STM32_HAVE_IP_TIMERS_M3M4_V2 + +config STM32_HAVE_TIM_PWM_CHMODE_LIMITED + bool + default y if STM32_HAVE_IP_TIMERS_M0_V1 || STM32_COMMON_L5_U5 + +config STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + bool + default y if STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + +config STM32_HAVE_TIM_PWM_NOUT_REQUIRES_OUT + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_PWM_MULTICHAN + bool + default y if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM + default y if (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7) && STM32_PWM + default y if (ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5) && STM32_PWM + default y if ARCH_CHIP_STM32L5 && STM32_PWM_MULTICHAN_L5_TIMERS + +config STM32_HAVE_QENCODER_MAIN + bool + default y if STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_QENCODER_16BIT + bool + default y if STM32_QENCODER_STM32 || STM32_QENCODER_F0 + +config STM32_ENERGYLITE + bool + select STM32_HAVE_TIM6 if STM32_HAVE_IP_TIMERS + select STM32_HAVE_TIM7 if STM32_HAVE_IP_TIMERS + +config STM32_HAVE_LPTIM_CHANNEL + bool + +config STM32_HAVE_IP_TIMERS + bool + +config STM32_HAVE_IP_TIMERS_M3M4_V1 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M3M4_V2 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M3M4_V3 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_IP_TIMERS_M0_V1 + bool + select STM32_HAVE_IP_TIMERS + +config STM32_HAVE_TIM_ADC_TRIGGER + bool + default y if STM32_HAVE_IP_ADC_M3M4_V1 + default y if STM32_HAVE_IP_ADC_M3M4_V2 + default y if STM32_HAVE_IP_ADC_M0_V1 + default y if STM32_COMMON_F7_H7 + default y if STM32_COMMON_L4_H5_L5_U5 + default y if ARCH_CHIP_STM32F7 + default y if ARCH_CHIP_STM32H7 + +config STM32_HAVE_TIM_DAC_TRIGGER + bool + default y if STM32_COMMON_LEGACY + default y if ARCH_CHIP_STM32F7 + default y if STM32_COMMON_L4_L5_U5 + +config STM32_HAVE_TIM1 + bool + +config STM32_HAVE_TIM2 + bool + +config STM32_HAVE_TIM3 + bool + +config STM32_HAVE_TIM4 + bool + +config STM32_HAVE_TIM5 + bool + +config STM32_HAVE_TIM6 + bool + +config STM32_HAVE_TIM7 + bool + +config STM32_HAVE_TIM8 + bool + +config STM32_HAVE_TIM9 + bool + +config STM32_HAVE_TIM10 + bool + +config STM32_HAVE_TIM11 + bool + +config STM32_HAVE_TIM12 + bool + +config STM32_HAVE_TIM13 + bool + +config STM32_HAVE_TIM14 + bool + +config STM32_HAVE_TIM15 + bool + +config STM32_HAVE_TIM16 + bool + +config STM32_HAVE_TIM17 + bool + +config STM32_HAVE_TIM18 + bool + +config STM32_HAVE_TIM19 + bool + +config STM32_HAVE_TIM20 + bool + +config STM32_HAVE_LPTIM1 + bool + +config STM32_HAVE_LPTIM2 + bool + +config STM32_HAVE_LPTIM3 + bool + +config STM32_HAVE_LPTIM4 + bool + +config STM32_HAVE_IP_ONESHOT_M3M4_V1 + bool + +config STM32_HAVE_IP_FREERUN_M3M4_V1 + bool + +# TSC capabilities + +config STM32_HAVE_TSC + bool + +# UART capabilities + +config STM32_HAVE_SWPMI + bool + +config STM32_HAVE_USART_H5 + bool + +config STM32_HAVE_USART_RXFIFO_THRESHOLD + bool + +config STM32_HAVE_USART_UNCONFIG_ON_CLOSE + bool + default y if ARCH_CHIP_STM32H5 + default y if ARCH_CHIP_STM32N6 + +config STM32_HAVE_USART2 + bool + +config STM32_HAVE_USART3 + bool + +config STM32_HAVE_UART4 + bool + +config STM32_HAVE_UART5 + bool + +config STM32_HAVE_USART6 + bool + +config STM32_HAVE_UART7 + bool + +config STM32_HAVE_UART8 + bool + +config STM32_HAVE_IP_USART + bool + +config STM32_HAVE_IP_USART_V1 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V2 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V3 + bool + select STM32_HAVE_IP_USART + +config STM32_HAVE_IP_USART_V4 + bool + select STM32_HAVE_IP_USART + select STM32_HAVE_USART_RXFIFO_THRESHOLD + +config STM32_HAVE_USART4 + bool + +config STM32_HAVE_USART5 + bool + +config STM32_HAVE_USART7 + bool + +config STM32_HAVE_USART8 + bool + +config STM32_HAVE_UART9 + bool + +config STM32_HAVE_USART10 + bool + +config STM32_HAVE_USART11 + bool + +config STM32_HAVE_UART12 + bool + +config STM32_HAVE_USART1 + bool + +# UID capabilities + +config STM32_HAVE_IP_UID_M0_V1 + bool + +config STM32_HAVE_IP_UID_M3M4_V1 + bool + +# USB capabilities + +config STM32_HAVE_USBFS_MODE + bool + +config STM32_HAVE_USBDRD_HOST + bool + +config STM32_HAVE_OTG_H7 + bool + +config STM32_HAVE_INTERNAL_ULPI + bool + +config STM32_HAVE_EXTERNAL_ULPI + bool + +config STM32_HAVE_UCPD + bool + +config STM32_HAVE_UCPD1 + bool + +config STM32_HAVE_UCPD2 + bool + +config STM32_HAVE_USBDEV + bool + +config STM32_HAVE_IP_USBDEV_M0_V1 + bool + +config STM32_HAVE_IP_USBDEV_M3M4_V1 + bool + +config STM32_HAVE_USBFS + bool + +config STM32_HAVE_IP_USBFS_M3M4_V1 + bool + +config STM32_HAVE_OTGFS + bool + +config STM32_HAVE_OTGHS + bool + +config STM32_HAVE_IP_OTGFS_M3M4_V1 + bool + +config STM32_HAVE_IP_OTGHS_M3M4_V1 + bool + +config STM32_HAVE_COMMON_USBHOST_DEBUG + bool + default y if STM32_COMMON_LEGACY + +config STM32_HAVE_USB + bool + +# WDG capabilities + +config STM32_HAVE_IP_WDG_M0_V1 + bool + +config STM32_HAVE_IP_WDG_M3M4_V1 + bool diff --git a/arch/arm/src/common/stm32/Kconfig.hciuart b/arch/arm/src/common/stm32/Kconfig.hciuart new file mode 100644 index 00000000000..81fb4fcb448 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hciuart @@ -0,0 +1,292 @@ +# +# STM32 common HCI UART options. +# + +config STM32_HCIUART + bool + +config STM32_HCIUART_RXDMA + bool + +if STM32_USART1_HCIUART + +config STM32_HCIUART1_RXBUFSIZE + int "HCI UART1 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART1_TXBUFSIZE + int "HCI UART1 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART1_BAUD + int "HCI UART1 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART1_RXDMA + bool "HCI UART1 Rx DMA" + default n + depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART1_HCIUART + +if STM32_USART2_HCIUART + +config STM32_HCIUART2_RXBUFSIZE + int "HCI UART2 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART2_TXBUFSIZE + int "HCI UART2 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART2_BAUD + int "HCI UART2 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART2_RXDMA + bool "HCI UART2 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART2_HCIUART + +if STM32_USART3_HCIUART + +config STM32_HCIUART3_RXBUFSIZE + int "HCI UART3 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART3_TXBUFSIZE + int "HCI UART3 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART3_BAUD + int "HCI UART3 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART3_RXDMA + bool "HCI UART3 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART3_HCIUART + +if STM32_USART6_HCIUART + +config STM32_HCIUART6_RXBUFSIZE + int "HCI UART6 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART6_TXBUFSIZE + int "HCI UART6 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART6_BAUD + int "HCI UART6 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART6_RXDMA + bool "HCI UART6 Rx DMA" + default n + depends on STM32_DMA1 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_USART6_HCIUART + +if STM32_UART7_HCIUART + +config STM32_HCIUART7_RXBUFSIZE + int "HCI UART7 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART7_TXBUFSIZE + int "HCI UART7 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART7_BAUD + int "HCI UART7 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART7_RXDMA + bool "HCI UART7 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART7_HCIUART + +if STM32_UART8_HCIUART + +config STM32_HCIUART8_RXBUFSIZE + int "HCI UART8 Rx buffer size" + default 80 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. Ideally this should be at least + the size of the largest frame that can be received + +config STM32_HCIUART8_TXBUFSIZE + int "HCI UART8 Transmit buffer size" + default 80 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. Ideally this should be at least + the size of the largest frame that can be sent + +config STM32_HCIUART8_BAUD + int "HCI UART8 initial BAUD rate" + default 115200 + ---help--- + The configured initial BAUD of the HCIR USART used during bringup. + In most cases this initial rate can be increased by the upper half + HCI UART driver using vendor-specifi HCI UART commands. + +config STM32_HCIUART8_RXDMA + bool "HCI UART8 Rx DMA" + default n + depends on STM32_DMA2 + select STM32_HCIUART_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # STM32_UART8_HCIUART + +menu "HCI UART Driver Configuration" + depends on STM32_SERIALDRIVER + +config STM32_HCIUART_RXDMA_BUFSIZE + int "Rx DMA buffer size" + default 32 + range 32 4096 + depends on STM32_HCIUART_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_HCIUART_RXDMAPRIO + hex "HCI UART DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_HCIUART_RXDMA + ---help--- + Select HCI UART DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_HCIUART_SW_RXFLOW + bool "Use Software UART RTS flow control" + default n + ---help--- + Enable UART RTS flow control using Software. Current STM32 have + broken HW based RTS behavior (they assert nRTS after every byte + received) Enable this setting workaround this issue by using + software based management of RTS + + If HCI UART DMA is enabled, this is probably the better selection + as well. In that case, the Rx DMA buffer will avoid Rx overrun due + to short, bursty activity. Software RTS management will probably + result in overall better throughput and should still avoid Rx data + overrun conditions. + +config STM32_HCIUART_UPPER_WATERMARK + int "RTS flow control upper watermark (%)" + default 75 + range 2 100 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be asserted + when this amount of Rx data has been buffered. The amount is + expressed as a percentage of the Rx buffer size. + +config STM32_HCIUART_LOWER_WATERMARK + int "RTS flow control lower watermark (%)" + default 25 + range 1 99 + depends on STM32_HCIUART_SW_RXFLOW + ---help--- + If software RTS flow control is enable, then RTS will be de-asserted + when there is less than this amount ofdata in the Rx buffere. The + amount is expressed as a percentage of the Rx buffer size. + +endmenu # HCI UART Driver Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.hrtim b/arch/arm/src/common/stm32/Kconfig.hrtim new file mode 100644 index 00000000000..ec2378f35b7 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.hrtim @@ -0,0 +1,583 @@ +# +# STM32 HRTIM configuration options. +# + +config STM32_HRTIM1_HAVE_PLLCLK + bool + default y if STM32_STM32F33XX + +config STM32_HRTIM_DISABLE_CHARDRV + bool "HRTIM Disable Character Driver" + default n + ---help--- + In most cases we do not need HRTIM Character Driver, so we can disable it + and save some memory. + +config STM32_HRTIM_NO_ENABLE_TIMERS + bool "Do not enable HRTIM timers at startup" + default n + ---help--- + Do not enable HRTIM timers at startup + +menuconfig STM32_HRTIM_ADC + bool "HRTIM ADC Triggering" + default n + ---help--- + Enable HRTIM ADC Triggering support. + +if STM32_HRTIM_ADC + +config STM32_HRTIM_ADC1_TRG1 + bool "HRTIM ADC1 Trigger 1" + default n + +config STM32_HRTIM_ADC1_TRG2 + bool "HRTIM ADC1 Trigger 2" + default n + +config STM32_HRTIM_ADC1_TRG3 + bool "HRTIM ADC1 Trigger 3" + default n + +config STM32_HRTIM_ADC1_TRG4 + bool "HRTIM ADC1 Trigger 4" + default n + +config STM32_HRTIM_ADC2_TRG1 + bool "HRTIM ADC2 Trigger 1" + default n + +config STM32_HRTIM_ADC2_TRG2 + bool "HRTIM ADC2 Trigger 2" + default n + +config STM32_HRTIM_ADC2_TRG3 + bool "HRTIM ADC2 Trigger 3" + default n + +config STM32_HRTIM_ADC2_TRG4 + bool "HRTIM ADC2 Trigger 4" + default n + +endif # STM32_HRTIM_ADC + +config STM32_HRTIM_DAC + bool "HRTIM DAC Triggering" + default n + ---help--- + Enable HRTIM DAC Triggering support. + +config STM32_HRTIM_PWM + bool "HRTIM PWM Outputs" + default n + ---help--- + Enable HRTIM PWM Outputs support. + +config STM32_HRTIM_CAP + bool "HRTIM Capture" + default n + ---help--- + Enable HRTIM Capture support. + +config STM32_HRTIM_INTERRUPTS + bool "HRTIM Interrupts" + default n + ---help--- + Enable HRTIM Interrupts support. + +config STM32_HRTIM_BURST + bool "HRTIM Burst Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Burst Mode support for PWM outputs. + +config STM32_HRTIM_DEADTIME + bool "HRTIM Dead-time" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Deadtime support for PWM outputs. + +config STM32_HRTIM_PUSHPULL + bool "HRTIM Push-Pull Mode" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Push-Pull Mode support for PWM outputs. + +config STM32_HRTIM_CHOPPER + bool "HRTIM Chopper" + depends on STM32_HRTIM_PWM + default n + ---help--- + Enable HRTIM Chopper Mode for PWM outputs. + +config STM32_HRTIM_DMA + bool "HRTIM DMA" + default n + +config STM32_HRTIM_DMABURST + bool "HRTIM DMA Burst" + default n + +config STM32_HRTIM_AUTODELAY + bool "HRTIM Autodelay" + depends on STM32_HRTIM_PWM + default n + +menuconfig STM32_HRTIM_EVENTS + bool "HRTIM Events Configuration" + default n + ---help--- + Enable HRTIM Events support. + +if STM32_HRTIM_EVENTS + +config STM32_HRTIM_EEV1 + bool "HRTIM EEV1" + default n + +config STM32_HRTIM_EEV2 + bool "HRTIM EEV2" + default n + +config STM32_HRTIM_EEV3 + bool "HRTIM EEV3" + default n + +config STM32_HRTIM_EEV4 + bool "HRTIM EEV4" + default n + +config STM32_HRTIM_EEV5 + bool "HRTIM EEV5" + default n + +config STM32_HRTIM_EEV6 + bool "HRTIM EEV6" + default n + +config STM32_HRTIM_EEV7 + bool "HRTIM EEV7" + default n + +config STM32_HRTIM_EEV8 + bool "HRTIM EEV8" + default n + +config STM32_HRTIM_EEV9 + bool "HRTIM EEV9" + default n + +config STM32_HRTIM_EEV10 + bool "HRTIM EEV10" + default n + +endif # STM32_HRTIM_EVENTS + +menuconfig STM32_HRTIM_FAULTS + bool "HRTIM Faults Configuration" + default n + ---help--- + Enable HRTIM Faults support. + +if STM32_HRTIM_FAULTS + +config STM32_HRTIM_FAULT1 + bool "HRTIM Fault 1" + default n + +config STM32_HRTIM_FAULT2 + bool "HRTIM Fault 2" + default n + +config STM32_HRTIM_FAULT3 + bool "HRTIM Fault 3" + default n + +config STM32_HRTIM_FAULT4 + bool "HRTIM Fault 4" + default n + +endif # STM32_HRTIM_FAULTS + +config STM32_HRTIM_CLK_FROM_PLL + bool "HRTIM Clock from PLL" + default n + depends on STM32_HRTIM1_HAVE_PLLCLK + ---help--- + Set PLL as the clock source for HRTIM. + This configuration requires the following conditions: + 1) system clock is PLL, + 2) SYSCLK and PCLK2 ratio must be 1 o 2. + +menu "HRTIM Master Configuration" + depends on STM32_HRTIM_MASTER + +config STM32_HRTIM_MASTER_DAC + bool "HRTIM Master DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_MASTER_DMA + bool "HRTIM MASTER DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_MASTER_IRQ + bool "HRTIM MASTER Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +endmenu # "HRTIM Master Configuration" + +menu "HRTIM Timer A Configuration" + depends on STM32_HRTIM_TIMA + +config STM32_HRTIM_TIMA_CAP + bool "HRTIM TIMA Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMA_DAC + bool "HRTIM TIMA DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMA_DMA + bool "HRTIM TIMA DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMA_IRQ + bool "HRTIM TIMA Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMA_PWM + bool "HRTIM TIMA PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMA_PWM_CH1 + bool "HRTIM TIMA PWM Output 1" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_PWM_CH2 + bool "HRTIM TIMA PWM Output 2" + default n + depends on STM32_HRTIM_TIMA_PWM + +config STM32_HRTIM_TIMA_BURST + bool "HRTIM TIMA Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_BURST_CH1 + bool "HRTIM TIMA Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) + +config STM32_HRTIM_TIMA_BURST_CH2 + bool "HRTIM TIMA Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) + +config STM32_HRTIM_TIMA_CHOP + bool "HRTIM TIMA PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_DT + bool "HRTIM TIMA PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) + +config STM32_HRTIM_TIMA_PSHPLL + bool "HRTIM TIMA PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) + +endmenu # "HRTIM Timer A Configuration" + +menu "HRTIM Timer B Configuration" + depends on STM32_HRTIM_TIMB + +config STM32_HRTIM_TIMB_CAP + bool "HRTIM TIMB Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMB_DAC + bool "HRTIM TIMB DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMB_DMA + bool "HRTIM TIMB DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMB_IRQ + bool "HRTIM TIMB Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMB_PWM + bool "HRTIM TIMB PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMB_PWM_CH1 + bool "HRTIM TIMB PWM Output 1" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_PWM_CH2 + bool "HRTIM TIMB PWM Output 2" + default n + depends on STM32_HRTIM_TIMB_PWM + +config STM32_HRTIM_TIMB_BURST + bool "HRTIM TIMB Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_BURST_CH1 + bool "HRTIM TIMB Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) + +config STM32_HRTIM_TIMB_BURST_CH2 + bool "HRTIM TIMB Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) + +config STM32_HRTIM_TIMB_CHOP + bool "HRTIM TIMB PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_DT + bool "HRTIM TIMB PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) + +config STM32_HRTIM_TIMB_PSHPLL + bool "HRTIM TIMB PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) + +endmenu # "HRTIM Timer B Configuration" + +menu "HRTIM Timer C Configuration" + depends on STM32_HRTIM_TIMC + +config STM32_HRTIM_TIMC_CAP + bool "HRTIM TIMC Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMC_DAC + bool "HRTIM TIMC DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMC_DMA + bool "HRTIM TIMC DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMC_IRQ + bool "HRTIM TIMC Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMC_PWM + bool "HRTIM TIMC PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMC_PWM_CH1 + bool "HRTIM TIMC PWM Output 1" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_PWM_CH2 + bool "HRTIM TIMC PWM Output 2" + default n + depends on STM32_HRTIM_TIMC_PWM + +config STM32_HRTIM_TIMC_BURST + bool "HRTIM TIMC Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_BURST_CH1 + bool "HRTIM TIMC Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) + +config STM32_HRTIM_TIMC_BURST_CH2 + bool "HRTIM TIMC Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) + +config STM32_HRTIM_TIMC_CHOP + bool "HRTIM TIMC PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_DT + bool "HRTIM TIMC PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) + +config STM32_HRTIM_TIMC_PSHPLL + bool "HRTIM TIMC PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) + +endmenu # "HRTIM Timer C Configuration" + +menu "HRTIM Timer D Configuration" + depends on STM32_HRTIM_TIMD + +config STM32_HRTIM_TIMD_CAP + bool "HRTIM TIMD Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIMD_DAC + bool "HRTIM TIMD DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIMD_DMA + bool "HRTIM TIMD DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIMD_IRQ + bool "HRTIM TIMD Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIMD_PWM + bool "HRTIM TIMD PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIMD_PWM_CH1 + bool "HRTIM TIMD PWM Output 1" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_PWM_CH2 + bool "HRTIM TIMD PWM Output 2" + default n + depends on STM32_HRTIM_TIMD_PWM + +config STM32_HRTIM_TIMD_BURST + bool "HRTIM TIMD Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_BURST_CH1 + bool "HRTIM TIMD Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) + +config STM32_HRTIM_TIMD_BURST_CH2 + bool "HRTIM TIMD Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) + +config STM32_HRTIM_TIMD_CHOP + bool "HRTIM TIMD PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_DT + bool "HRTIM TIMD PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) + +config STM32_HRTIM_TIMD_PSHPLL + bool "HRTIM TIMD PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) + +endmenu # "HRTIM Timer D Configuration" + +menu "HRTIM Timer E Configuration" + depends on STM32_HRTIM_TIME + +config STM32_HRTIM_TIME_CAP + bool "HRTIM TIME Capture" + default n + depends on STM32_HRTIM_CAPTURE + +config STM32_HRTIM_TIME_DAC + bool "HRTIM TIME DAC Triggering" + default n + depends on STM32_HRTIM_DAC + +config STM32_HRTIM_TIME_DMA + bool "HRTIM TIME DMA" + default n + depends on STM32_HRTIM_DMA + +config STM32_HRTIM_TIME_IRQ + bool "HRTIM TIME Interrupts" + default n + depends on STM32_HRTIM_INTERRUPTS + +config STM32_HRTIM_TIME_PWM + bool "HRTIM TIME PWM Outputs" + default n + depends on STM32_HRTIM_PWM + +config STM32_HRTIM_TIME_PWM_CH1 + bool "HRTIM TIME PWM Output 1" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_PWM_CH2 + bool "HRTIM TIME PWM Output 2" + default n + depends on STM32_HRTIM_TIME_PWM + +config STM32_HRTIM_TIME_BURST + bool "HRTIM TIME Burst" + default n + depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_BURST_CH1 + bool "HRTIM TIME Output 1 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) + +config STM32_HRTIM_TIME_BURST_CH2 + bool "HRTIM TIME Output 2 Burst Mode" + default n + depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) + +config STM32_HRTIM_TIME_CHOP + bool "HRTIM TIME PWM Chopper" + default n + depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_DT + bool "HRTIM TIME PWM Dead-time" + default n + depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) + +config STM32_HRTIM_TIME_PSHPLL + bool "HRTIM TIME PWM Push-pull mode" + default n + depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) + +endmenu # "HRTIM Timer E Configuration" diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c new file mode 100644 index 00000000000..e3af19f3c7b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -0,0 +1,313 @@ +# +# STM32 I2C configuration options. +# + +# TODO: generalize H5 specific options ! + +config STM32_I2C_SLAVE + bool + default n + +menu "I2C Configuration H5-specific" + depends on STM32_HAVE_I2C_H5 + +menu "Clock Selection" + +choice + depends on STM32_I2C1 + prompt "I2C1 Input Clock Selection" + default STM32_I2C1_CLK_PCLK1 + +config STM32_I2C1_CLK_CSI + bool "CSI" + +config STM32_I2C1_CLK_HSI + bool "HSI" + +config STM32_I2C1_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C1_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C1 Input Clock Selection + +choice + depends on STM32_I2C2 + prompt "I2C2 Input Clock Selection" + default STM32_I2C2_CLK_PCLK1 + +config STM32_I2C2_CLK_CSI + bool "CSI" + +config STM32_I2C2_CLK_HSI + bool "HSI" + +config STM32_I2C2_CLK_PCLK1 + bool "PCLK1" + +config STM32_I2C2_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C2 Input Clock Selection + +choice + depends on STM32_I2C3 + prompt "I2C3 Input Clock Selection" + default STM32_I2C3_CLK_PCLK3 + +config STM32_I2C3_CLK_CSI + bool "CSI" + +config STM32_I2C3_CLK_HSI + bool "HSI" + +config STM32_I2C3_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C3_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C3 Input Clock Selection + +choice + depends on STM32_I2C4 + prompt "I2C4 Input Clock Selection" + default STM32_I2C4_CLK_PCLK3 + +config STM32_I2C4_CLK_CSI + bool "CSI" + +config STM32_I2C4_CLK_HSI + bool "HSI" + +config STM32_I2C4_CLK_PCLK3 + bool "PCLK3" + +config STM32_I2C4_CLK_PLL3R + bool "PLL3R" + +endchoice # I2C4 Input Clock Selection + +endmenu # Clock Selection + +menu "Rise/Fall Override" + +config STM32_I2C1_RF_OVERRIDE + bool "I2C1" + default n + depends on STM32_I2C1 + +config STM32_I2C2_RF_OVERRIDE + bool "I2C2" + default n + depends on STM32_I2C2 + +config STM32_I2C3_RF_OVERRIDE + bool "I2C3" + default n + depends on STM32_I2C3 + +config STM32_I2C4_RF_OVERRIDE + bool "I2C4" + default n + depends on STM32_I2C4 + +menu "Rise/Fall Values" + +config STM32_I2C1_RISE + int "I2C1 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C1_FALL + int "I2C1 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C1_RF_OVERRIDE + +config STM32_I2C2_RISE + int "I2C2 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C2_FALL + int "I2C2 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C2_RF_OVERRIDE + +config STM32_I2C3_RISE + int "I2C3 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C3_FALL + int "I2C3 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C3_RF_OVERRIDE + +config STM32_I2C4_RISE + int "I2C4 Rise Time (ns)" + range 0 1000 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +config STM32_I2C4_FALL + int "I2C4 Fall Time (ns)" + range 0 300 + default 20 + depends on STM32_I2C4_RF_OVERRIDE + +endmenu # Rise/Fall Values + +endmenu # Rise/Fall Override + +menu "Filtering" + +menu "Digital Filters" + +config STM32_I2C1_DNF + int "I2C1 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C1 + +config STM32_I2C2_DNF + int "I2C2 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C2 + +config STM32_I2C3_DNF + int "I2C3 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C3 + +config STM32_I2C4_DNF + int "I2C4 Digital Noise Filter" + range 0 15 + default 0 + depends on STM32_I2C4 + +endmenu # Digital Filters + +menu "Analog Filters" + +config STM32_I2C1_ANFOFF + int "Turn off I2C1 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C1 + +config STM32_I2C2_ANFOFF + int "Turn off I2C2 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C2 + +config STM32_I2C3_ANFOFF + int "Turn off I2C3 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C3 + +config STM32_I2C4_ANFOFF + int "Turn off I2C4 Analog Filter (0=on, 1=off)" + default 1 + range 0 1 + depends on STM32_I2C4 + +endmenu # Analog Filters + +endmenu # Filtering + +endmenu # "I2C Configuration" + +if !STM32_HAVE_I2C_H5 + +config STM32_I2C_DYNTIMEO + bool "Use dynamic timeouts" + depends on STM32_I2C + +config STM32_I2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + depends on STM32_I2C && STM32_I2C_DYNTIMEO + default 1000 + +config STM32_I2CTIMEOSEC + int "Timeout seconds" + depends on STM32_I2C + default 0 + +config STM32_I2CTIMEOMS + int "Timeout Milliseconds" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2CTIMEOTICKS + int "Timeout for Done and Stop (ticks)" + depends on STM32_I2C && !STM32_I2C_DYNTIMEO + default 500 + +config STM32_I2C_ALT + bool "Alternate I2C implementation" + default STM32F1_PERFORMANCELINE + depends on !STM32_STM32F30XX && STM32_COMMON_LEGACY + ---help--- + This selection enables an alternative I2C driver. This alternate + driver implements some rather complex workarounds for errata against + the STM32 F103 "Performance Line". This selection is an option + because: (1) It has not yet been fully verified and (2) It is not + certain that he scope of this workaround is needed only for the F103. + +config STM32_I2C_DUTY16_9 + bool "Frequency with Tlow/Thigh = 16/9" + default n + depends on STM32_I2C && STM32_COMMON_LEGACY + +config STM32_I2C_DMA + bool "I2C DMA Support" + default n + depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the + I2C dma streams, else the default priority level is set to medium. + +menu "I2C Slave Configuration" + depends on STM32_I2C_SLAVE + +config STM32_I2C_SLAVE_DEFAULT_TX + hex "Default TX byte to be sent when the TX buffer is empty" + default 0xFF + +config STM32_I2C_SLAVE_USEWQ + bool "Use work queue to delegate the isr completion status" + default n + ---help--- + With the current upperhalf I2C slave driver implementation, the user + should delegate the callback completion status using a work queue. + However, work queues introduce a delay, so in certain scenarios + it is better to use a custom driver without using a work queue. + +config STM32_I2C_SLAVE_RETRANSFER + bool "The frame is retransferred when stop is issued beforehand" + default n + ---help--- + If stop is issued before the whole frame is transferred, + the tx pointer is reset to 0. + +endmenu + +endif # !STM32_HAVE_I2C_H5 \ No newline at end of file diff --git a/arch/arm/src/common/stm32/Kconfig.ipcc b/arch/arm/src/common/stm32/Kconfig.ipcc new file mode 100644 index 00000000000..da34bba96d2 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ipcc @@ -0,0 +1,91 @@ +# +# STM32 common IPCC options. +# + +config STM32_IPCC_CHAN1_RX_SIZE + int "Channel 1 RX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the receive buffer. Another CPU will write to this buffer and + the currently running CPU will read from it. + +config STM32_IPCC_CHAN1_TX_SIZE + int "Channel 1 TX size" + default 256 + depends on STM32_IPCC + ---help--- + Size of the send buffer. Another CPU will read from this buffer and + the currently running CPU will write to it. + +config STM32_IPCC_CHAN2 + bool "Enable channel 2" + depends on STM32_IPCC + +if STM32_IPCC_CHAN2 + +config STM32_IPCC_CHAN2_RX_SIZE + int "Channel 2 RX size" + default 256 + +config STM32_IPCC_CHAN2_TX_SIZE + int "Channel 2 TX size" + default 256 + +config STM32_IPCC_CHAN3 + bool "Enable channel 3" + +if STM32_IPCC_CHAN3 + +config STM32_IPCC_CHAN3_RX_SIZE + int "Channel 3 RX size" + default 256 + +config STM32_IPCC_CHAN3_TX_SIZE + int "Channel 3 TX size" + default 256 + +config STM32_IPCC_CHAN4 + bool "Enable channel 4" + +if STM32_IPCC_CHAN4 + +config STM32_IPCC_CHAN4_RX_SIZE + int "Channel 4 RX size" + default 256 + +config STM32_IPCC_CHAN4_TX_SIZE + int "Channel 4 TX size" + default 256 + +config STM32_IPCC_CHAN5 + bool "Enable channel 5" + +if STM32_IPCC_CHAN5 + +config STM32_IPCC_CHAN5_RX_SIZE + int "Channel 5 RX size" + default 256 + +config STM32_IPCC_CHAN5_TX_SIZE + int "Channel 5 TX size" + default 256 + +config STM32_IPCC_CHAN6 + bool "Enable channel 6" + +if STM32_IPCC_CHAN6 + +config STM32_IPCC_CHAN6_RX_SIZE + int "Channel 6 RX size" + default 256 + +config STM32_IPCC_CHAN6_TX_SIZE + int "Channel 6 TX size" + default 256 + +endif # STM32_IPCC_CHAN2 +endif # STM32_IPCC_CHAN3 +endif # STM32_IPCC_CHAN4 +endif # STM32_IPCC_CHAN5 +endif # STM32_IPCC_CHAN6 diff --git a/arch/arm/src/common/stm32/Kconfig.lpuart b/arch/arm/src/common/stm32/Kconfig.lpuart new file mode 100644 index 00000000000..98f5c9f83ca --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.lpuart @@ -0,0 +1,69 @@ +# +# STM32 common LPUART options. +# + +config LPUART1_RXDMA + bool + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER && STM32_DMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +choice + prompt "LPUART1 Driver Configuration" + depends on STM32_LPUART1 + default STM32_LPUART1_SERIALDRIVER + +config STM32_LPUART1_SERIALDRIVER + bool "Standard serial driver" + select LPUART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_LPUART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # LPUART1 Driver Configuration + +config LPUART1_RS485 + bool "RS-485 on LPUART1" + depends on STM32_LPUART1 && LPUART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on LPUART1. Your board config will have to + provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be + used with LPUART1_RXDMA. + +if LPUART1_RS485 + +config LPUART1_RS485_DIR_POLARITY + int "LPUART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # LPUART1_RS485 + +if STM32_LPUART1_SERIALDRIVER + +config LPUART1_TXDMA + bool "LPUART1 Tx DMA" + default n + depends on STM32_DMA1 + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +endif # STM32_LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure LPUART1 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure LPUART1 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER + +config LPUART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure LPUART1 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && LPUART1_SERIALDRIVER && LPUART1_RS485 diff --git a/arch/arm/src/common/stm32/Kconfig.ltdc b/arch/arm/src/common/stm32/Kconfig.ltdc new file mode 100644 index 00000000000..27d3d9c1b76 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.ltdc @@ -0,0 +1,233 @@ +# +# STM32 common LTDC options. +# + +choice + prompt "Layer 1 color format" + depends on STM32_LTDC + default STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L1_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_FB_CMAP + +config STM32_LTDC_L1_RGB565 + bool "16 bpp RGB 565" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB4444 + bool "16 bpp ARGB 4444" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB1555 + bool "16 bpp ARGB 1555" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_RGB888 + bool "24 bpp RGB 888" + depends on !STM32_FB_CMAP + +config STM32_LTDC_L1_ARGB8888 + bool "32 bpp ARGB 8888" + depends on !STM32_FB_CMAP + +endchoice # Layer 1 color format + +choice + prompt "Layer 2 (top layer) color format" + depends on STM32_LTDC && STM32_LTDC_L2 + default STM32_LTDC_L2_RGB565 + +config STM32_LTDC_L2_L8 + bool "8 bpp L8 (8-bit CLUT)" + depends on STM32_LTDC_L1_L8 + +config STM32_LTDC_L2_AL44 + bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" + depends on STM32_LTDC_L1_AL44 + +config STM32_LTDC_L2_AL88 + bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" + depends on STM32_LTDC_L1_AL88 + +config STM32_LTDC_L2_RGB565 + bool "16 bpp RGB 565" + depends on STM32_LTDC_L1_RGB565 + +config STM32_LTDC_L2_ARGB4444 + bool "16 bpp ARGB 4444" + depends on STM32_LTDC_L1_ARGB4444 + +config STM32_LTDC_L2_ARGB1555 + bool "16 bpp ARGB 1555" + depends on STM32_LTDC_L1_ARGB1555 + +config STM32_LTDC_L2_RGB888 + bool "24 bpp RGB 888" + depends on STM32_LTDC_L1_RGB888 + +config STM32_LTDC_L2_ARGB8888 + bool "32 bpp ARGB 8888" + depends on STM32_LTDC_L1_ARGB8888 + +endchoice # Layer 2 color format + +if STM32_LTDC + +config STM32_LTDC_BACKLIGHT + bool "Backlight support" + default y + +config STM32_LTDC_DEFBACKLIGHT + hex "Default backlight level" + default 0xf0 + +config STM32_LTDC_BACKCOLOR + hex "Background color" + default 0x0 + ---help--- + This is the background color that will be used as the LTDC + background layer color. It is an RGB888 format value. + +config STM32_LTDC_DITHER + bool "Dither support" + +config STM32_LTDC_FB_DOUBLE_BUFFER + bool "Enable double buffering" + depends on ARCH_CHIP_STM32H7 + default n + ---help--- + Enable double buffering to allow updates to the framebuffer while + the display is being refreshed. This configuration requires two + framebuffers: one active and one inactive. When the display + refreshes, the active and inactive framebuffers are swapped, + enabling smooth and flicker-free updates. + +if STM32_LTDC_DITHER + +config STM32_LTDC_DITHER_RED + int "Dither red width" + range 0 7 + default 2 + ---help--- + This is the dither red width. + +config STM32_LTDC_DITHER_GREEN + int "Dither green width" + range 0 7 + default 2 + ---help--- + This is the dither green width. + +config STM32_LTDC_DITHER_BLUE + int "Dither blue width" + range 0 7 + default 2 + ---help--- + This is the dither blue width. + +endif # STM32_LTDC_DITHER + +config STM32_LTDC_FB_BASE + hex "Framebuffer memory start address" + default 0 + ---help--- + If you are using the LTDC, then you must provide the address + of the start of the framebuffer. This address will typically + be in the SRAM or SDRAM memory region of the FSMC/FMC. + +config STM32_LTDC_FB_SIZE + int "Framebuffer memory size (bytes)" + default 0 + ---help--- + Must be the whole size of the active LTDC layer. + +config STM32_LTDC_L1_CHROMAKEYEN + bool "Enable chromakey support for layer 1" + default y + +config STM32_LTDC_L1_CHROMAKEY + hex "Layer L1 initial chroma key" + default 0x00000000 + +config STM32_LTDC_L1_COLOR + hex "Layer L1 default color" + default 0x00000000 + +config STM32_LTDC_L2 + bool "Enable Layer 2 support" + default y + +if STM32_LTDC_L2 + +config STM32_LTDC_L2_COLOR + hex "Layer L2 default color" + default 0x00000000 + +config STM32_LTDC_L2_CHROMAKEYEN + bool "Enable chromakey support for layer 2" + default y + +config STM32_LTDC_L2_CHROMAKEY + hex "Layer L2 initial chroma key" + default 0x00000000 + +endif # STM32_LTDC_L2 + +config STM32_FB_CMAP + bool "Color map support" + default y + select FB_CMAP + ---help--- + Enabling color map support is necessary for LTDC L8 format. + +config STM32_FB_TRANSPARENCY + bool "Transparency color map support" + depends on STM32_FB_CMAP + default y + select FB_TRANSPARENCY + ---help--- + Enabling transparency color map support is necessary for LTDC L8 format. + +config STM32_LTDC_REGDEBUG + bool "LTDC Register level debug" + depends on (STM32_COMMON_LEGACY && DEBUG_INFO && DEBUG_LCD) || STM32_COMMON_F7_H7 + ---help--- + Output detailed register-level LTDC device debug information. + +endif # STM32_LTDC + +config STM32_LTDC_USE_DSI + bool "Use DSI as display connection" + depends on STM32_COMMON_F7_H7 && STM32_LTDC && STM32_DSIHOST + ---help--- + Select this if your display is connected via DSI. + Deselect option if your display is connected via digital + RGB+HSYNC+VSYNC + +if STM32_LCD + +choice + prompt "Segment LCD Clock Source" + default LCD_LSECLOCK + +config LCD_LSICLOCK + bool "Internal Low Speed Clock" + +config LCD_LSECLOCK + bool "External Low Speed Clock" + +config LCD_HSECLOCK + bool "External High Speed Clock" + +endchoice + +endif # STM32_LCD diff --git a/arch/arm/src/common/stm32/Kconfig.memory b/arch/arm/src/common/stm32/Kconfig.memory new file mode 100644 index 00000000000..7ab6138be10 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.memory @@ -0,0 +1,168 @@ +# +# STM32 memory configuration options. +# + +config STM32_SRAM5_HEAP + bool "SRAM5 is used for heap" + depends on STM32_SRAM5 + default n + +config STM32_EXTERNAL_RAM + bool "External RAM on FSMC/FMC" + depends on STM32_FSMC || STM32_FMC + select ARCH_HAVE_HEAP2 + ---help--- + In addition to internal SRAM, external RAM may be available through the FSMC/FMC. + +config STM32_BBSRAM_FILES + int "Max Files to support in BBSRAM" + depends on STM32_BBSRAM + default 4 + +config STM32_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + depends on STM32_BBSRAM + +config STM32_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + depends on ARMV7M_HAVE_DTCM + default LIBC_ARCH_ELF + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + +config STM32_DTCM_PROCFS + bool "DTCM SRAM PROCFS support" + depends on ARMV7M_DTCM && FS_PROCFS + ---help--- + Select to build in support for /proc/dtcm. Reading from /proc/dtcm + will provide statistics about DTCM memory use similar to what you + would get from mallinfo() for the user heap. + +config STM32_SRAM2_HEAP + bool "SRAM2 is used for heap" + depends on STM32_COMMON_SRAM2_OPTIONS + select STM32_SRAM2_INIT if !ARCH_CHIP_STM32U5 || STM32_SRAM2 + ---help--- + The STM32L4 SRAM2 region has special properties (power, protection, parity) + which may be used by the application for special purposes. But if these + special properties are not needed, it may be instead added to the heap for + use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_SRAM2_INIT + bool "SRAM2 is initialized to zero" + depends on STM32_COMMON_SRAM2_OPTIONS + ---help--- + The STM32L4 SRAM2 region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2 is being used for it's battery-backed capability, + this may be undesirable (because it will destroy the contents). In that + case, the board should handle the initialization itself at the appropriate + time. + +config STM32_SRAM3_HEAP + bool "SRAM3 is used for heap" + depends on STM32_SRAM3 + default y if ARCH_CHIP_STM32L4 && STM32_STM32L4XR + ---help--- + Add the STM32L4 SRAM3 to the heap for use by malloc(). + NOTE: you must also select an appropriate number of memory regions in the + 'Memory Management' section. + +config STM32_CCMEXCLUDE + bool "Exclude CCM SRAM from the heap" + default ARCH_DMA || LIBC_ARCH_ELF + depends on STM32_HAVE_CCM + ---help--- + Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA + and (2) it appears to be impossible to execute ELF modules from CCM + RAM. + +config STM32_CCM_PROCFS + bool "CCM PROCFS support" + default n + depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER + ---help--- + Select to build in support for /proc/ccm. Reading from /proc/ccm + will provide statistics about CCM memory use similar to what you + would get from mallinfo() for the user heap. + +comment "STM32WB SRAM2a and SRAM2b Options" + depends on STM32_HAVE_SRAM2A || STM32_HAVE_SRAM2B + +config STM32_SRAM2A_HEAP + bool "SRAM2a is used for heap" + depends on STM32_HAVE_SRAM2A + default n + +config STM32_SRAM2A_USER_BASE_OFFSET + int "SRAM2a user application base offset" + default 2048 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The beginning part of the SRAM2a memory can be used by RF stack. The + available space for the user application can be obtained from the + release notes for STM32WB coprocessor wireless binaries. + +config STM32_SRAM2A_USER_SIZE + int "SRAM2a user application size" + default 8192 + range 0 32768 + depends on STM32_SRAM2A_HEAP + ---help--- + The ending part of the SRAM2a memory contains a secure section, which + cannot be read nor written by CPU1. The secure start address for the + SRAM2a memory can be read from the SBRSA option byte. When CPU2 update + support required, there must be some free sectors just below the secure + memory to support CPU2 firmware updates requiring more sectors to be + secure. + +config STM32_SRAM2A_INIT + bool "SRAM2a is initialized to zero" + default y + depends on STM32_SRAM2A_HEAP + ---help--- + The STM32WB SRAM2a region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. + However, if the SRAM2a is being retained in Standby mode, this may be + undesirable (because it will destroy the contents). In that case, the board + should handle the initialization itself at the appropriate time. + +config STM32_SRAM2B_HEAP + bool "SRAM2b is used for heap" + depends on STM32_HAVE_SRAM2B + default n + +config STM32_SRAM2B_USER_SIZE + int "SRAM2b user application size" + default 32768 + range 0 32768 + depends on STM32_SRAM2B_HEAP + ---help--- + For any CPU2 firmware supporting the BLE protocol the ending part of + the SRAM2b memory contains a secure section, which cannot be read nor + written by CPU1. The secure start address for the SRAM2b memory can be + read from the SNBRSA option byte. When CPU2 update support required, + there must be some free sectors just below the secure memory to support + CPU2 firmware updates requiring more sectors to be secure. The SRAM2b + memory is all secure for any CPU2 firmware supporting the Thread protocol. + +config STM32_SRAM2B_INIT + bool "SRAM2b is initialized to zero" + default y + depends on STM32_SRAM2B_HEAP + ---help--- + The STM32WB SRAM2b region has parity checking. However, when the system + powers on, the memory is in an unknown state, and reads from uninitialized + memory can trigger parity faults from the random data. This can be + avoided by first writing to all locations to force the parity into a valid + state. diff --git a/arch/arm/src/common/stm32/Kconfig.periph b/arch/arm/src/common/stm32/Kconfig.periph new file mode 100644 index 00000000000..5df4ec848c8 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.periph @@ -0,0 +1,1282 @@ +# +# STM32 common peripheral selection options. +# + +menu "STM32 Peripheral Support" + +config STM32_OPAMP + bool + depends on STM32_HAVE_IP_OPAMP_M3M4_V1 + select STM32_SYSCFG + +config STM32_COMP + bool + depends on STM32_HAVE_COMP + select STM32_SYSCFG + select COMP if ARCH_CHIP_STM32L4 && STM32_HAVE_COMP + +config STM32_ADC + bool + +config STM32_SDADC + bool + default n + +config STM32_CAN + bool + +config STM32_FDCAN + bool + select NET_CAN_HAVE_ERRORS if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_CANFD if ARCH_CHIP_STM32H7 + select NET_CAN_EXTID if ARCH_CHIP_STM32H7 + select NET_CAN_HAVE_TX_DEADLINE if ARCH_CHIP_STM32H7 + +config STM32_DAC + bool + +config STM32_DMA + bool + select STM32_DMAMUX if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + select STM32_DMAMUX if ARCH_CHIP_STM32WB + +config STM32_DMAMUX + bool + +config STM32_I2C + bool + +config STM32_SPI + bool + +config STM32_TIM + bool + +config STM32_LPTIM + bool + +config STM32_HRTIM + bool + +config STM32_USART + bool + +config STM32_SERIALDRIVER + bool + +config STM32_SAI + bool + +config STM32_I2S + bool + select STM32_SPI_DMA if STM32_COMMON_LEGACY + select STM32_SPI_DMA if ARCH_CHIP_STM32F7 + +config STM32_SDMMC + bool + +config STM32_DFSDM + bool + default n + +config STM32_MBOX + bool + depends on STM32_HAVE_MBOX + default n + select STM32_IPCC + +# DMA peripherals + +config STM32_MDMA + bool "MDMA" + default n + depends on STM32_HAVE_MDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_BDMA + bool "BDMA" + default n + depends on STM32_HAVE_BDMA && EXPERIMENTAL + select STM32_DMA + select ARCH_DMA + +config STM32_GPADMA1 + depends on STM32_HAVE_GPADMA1 + bool "GPADMA1" + default n + +config STM32_LPDMA1 + depends on STM32_HAVE_LPDMA1 + bool "LPDMA1" + default n + +config STM32_DMA1 + bool "DMA1" + depends on STM32_HAVE_DMA1 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMA2 + bool "DMA2" + depends on STM32_HAVE_DMA2 + select STM32_DMA + select ARCH_DMA + select STM32_DMAMUX1 if ARCH_CHIP_STM32L4 && STM32_HAVE_DMAMUX + +config STM32_DMAMUX1 + bool "DMAMUX1" + depends on STM32_HAVE_DMAMUX + select STM32_DMAMUX + +config STM32_DMA2D + bool "DMA2D" + depends on STM32_HAVE_DMA2D + select FB if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + select FB_OVERLAY if STM32_COMMON_LEGACY && STM32_STM32F429 || ARCH_CHIP_STM32F7 && STM32_HAVE_DMA2D + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32F429 and STM32F439 devices. + +# CLOCK peripherals + +config STM32_CSI + bool "CSI Low-speed internal oscillator (4MHz)" + depends on STM32_HAVE_CSI + default n + +config STM32_HSI48 + bool "HSI48 High-speed 48MHz internal oscillator" + depends on STM32_HAVE_HSI48 + default n + +config STM32_CRS + bool "CRS (Clock Recovery System)" + depends on STM32_HAVE_CRS + +# POWER peripherals + +config STM32_VREF + depends on STM32_HAVE_VREF + bool "VREF" + default n + +config STM32_BKPSRAM + bool "Enable BKP RAM Domain" + depends on STM32_HAVE_BKPSRAM + select STM32_PWR if ARCH_CHIP_STM32H7 + +config STM32_VREFINT + bool "Enable VREFINT" + depends on STM32_HAVE_VREFINT + +config STM32_PWR + bool "PWR" + depends on STM32_HAVE_PWR + +# MEMORY peripherals + +config STM32_RAMCFG + depends on STM32_HAVE_RAMCFG + bool "RAMCFG" + default n + +config STM32_SRAM1 + depends on STM32_HAVE_SRAM1 + bool "SRAM1" + default y + +config STM32_SRAM2 + depends on STM32_HAVE_SRAM2 + bool "SRAM2" + default n + +config STM32_SRAM3 + bool "SRAM3" + default n + depends on STM32_HAVE_SRAM3 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_SRAM5 + bool "SRAM5" + default n + depends on STM32_HAVE_SRAM5 && (STM32_STM32U575XX || STM32_STM32U585XX || STM32_STM32U59XX || STM32_STM32U59AXX || \ + STM32_STM32U5A5XX || STM32_STM32U5A9XX) + +config STM32_BKP + bool "BKP" + depends on STM32_HAVE_BKP + +config STM32_FSMC + bool "FSMC" + depends on STM32_HAVE_FSMC + +config STM32_FMC + bool "FMC" + depends on STM32_HAVE_FMC + ---help--- + Enable Flexible Memory Controller. + To correctly configure FMC for your hardware, you will have to define + a number of macros in your board.h file. See stm32_fmc.c for directions. + +config STM32_BBSRAM + bool "BBSRAM File Support" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7) && STM32_BKPSRAM + select ARM_MPU if ARCH_CHIP_STM32H7 && STM32_BKPSRAM + +config STM32_CCMDATARAM + bool "CMD/DATA RAM" + default n + depends on STM32_STM32F4XXX + +# FLASH peripherals + +config STM32_FLASH + depends on STM32_HAVE_FLASH + bool "FLASH" + default n + +# GPIO peripherals + +config STM32_LPGPIO1 + depends on STM32_HAVE_LPGPIO1 + bool "LPGPIO1" + default n + +config STM32_SYSCFG + bool "SYSCFG" + depends on STM32_HAVE_SYSCFG + default y + +# SECURITY peripherals + +config STM32_FIREWALL + bool "FIREWALL" + default y + depends on STM32_HAVE_FIREWALL && STM32_SYSCFG + +config STM32_GTZC1 + depends on STM32_HAVE_GTZC1 + bool "GTZC1" + default n + +config STM32_GTZC2 + depends on STM32_HAVE_GTZC2 + bool "GTZC2" + default n + +config STM32_PKA + depends on STM32_HAVE_PKA + bool "PKA" + default n + +config STM32_SAES + depends on STM32_HAVE_SAES + bool "SAES" + default n + +config STM32_OTFDEC1 + depends on STM32_HAVE_OTFDEC1 + bool "OTFDEC1" + default n + +config STM32_OTFDEC2 + depends on STM32_HAVE_OTFDEC2 + bool "OTFDEC2" + default n + +config STM32_CRC + bool "CRC" + depends on STM32_HAVE_CRC + +config STM32_AES + bool "128-bit AES" + depends on STM32_HAVE_IP_AES_M0_V1 || STM32_HAVE_IP_AES_M3M4_V1 + select CRYPTO_AES192_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_LEGACY && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES192_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + select CRYPTO_AES256_DISABLE if (STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_AES) && CRYPTO_ALGTEST + +config STM32_CRYP + bool "CRYP" + depends on STM32_HAVE_CRYP + depends on STM32_HAVE_IP_CRYPTO_M3M4_V1 || STM32_HAVE_IP_CRYPTO_H7 + +config STM32_HASH + bool "HASH" + depends on STM32_HAVE_HASH + select ARCH_HAVE_HASH if ARCH_CHIP_STM32F7 && STM32_HAVE_HASH + +# BLE peripherals + +menuconfig STM32_BLE + bool "BLE" + depends on STM32_HAVE_BLE + default n + select STM32_MBOX + ---help--- + Enable BLE support. + +# CACHE peripherals + +config STM32_ICACHE + bool "ICACHE" + default n + depends on STM32_HAVE_ICACHE + +config STM32_DCACHE1 + depends on STM32_HAVE_DCACHE1 + bool "DCACHE1" + default n + +# RTC peripherals + +config STM32_RTCAPB + depends on STM32_HAVE_RTCAPB + bool "RTCAPB" + default n + +config STM32_RTC + bool "RTC" + depends on STM32_HAVE_RTC + select RTC if !ARCH_CHIP_STM32L5 + +# RNG peripherals + +config STM32_RNG + bool "RNG" + depends on STM32_HAVE_RNG + select ARCH_HAVE_RNG if !ARCH_CHIP_STM32U5 + +# WDG peripherals + +config STM32_IWDG + bool "IWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG + +config STM32_WWDG + bool "WWDG" + depends on STM32_HAVE_IP_WDG_M0_V1 || STM32_HAVE_IP_WDG_M3M4_V1 + select WATCHDOG if !ARCH_CHIP_STM32U5 + +# ADC peripherals + +config STM32_ADC1 + bool "ADC1" + depends on (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || STM32_HAVE_IP_ADC_M0_V1 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 || ARCH_CHIP_STM32U5 + select STM32_ADC if !ARCH_CHIP_STM32U5 + select STM32_ADC1_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && ((STM32_STM32F10XX || STM32_STM32F37XX) && STM32_DMA1 || !STM32_STM32F10XX && STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC1_HAVE_DMA if ARCH_CHIP_STM32F7 + select STM32_ADC1_HAVE_DMA if STM32_HAVE_IP_ADC_M0_V1 + select STM32_ADC1_HAVE_DMA if STM32_STM32F30XX || STM32_STM32F33XX + +config STM32_ADC2 + bool "ADC2" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC2 || STM32_COMMON_F7_H7_H5 + select STM32_ADC + select STM32_ADC2_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC2 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC2_HAVE_DMA if ARCH_CHIP_STM32F7 + select STM32_ADC2_HAVE_DMA if STM32_STM32F302 || STM32_STM32F303 || STM32_STM32F33XX + +config STM32_ADC3 + bool "ADC3" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32L4) && STM32_HAVE_ADC3 || STM32_COMMON_F7_H7 + select STM32_ADC + select STM32_ADC3_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC3 && (STM32_DMA2 || STM32_DMAMUX) + select STM32_ADC3_HAVE_DMA if ARCH_CHIP_STM32F7 + +config STM32_ADC4 + bool "ADC4" + depends on ((STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4) || ARCH_CHIP_STM32U5 + select STM32_ADC if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) + select STM32_ADC4_HAVE_DMA if (STM32_HAVE_IP_ADC_M3M4_V1 || STM32_HAVE_IP_ADC_M3M4_V2) && STM32_HAVE_ADC4 && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_ADC5 + bool "ADC5" + default n + select STM32_ADC + depends on STM32_HAVE_ADC5 + select STM32_ADC5_HAVE_DMA if STM32_DMA2 + select STM32_ADC5_HAVE_DMA if STM32_DMAMUX + +config STM32_SDADC1 + bool "SDADC1" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC1 + select STM32_SDADC1_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC2 + bool "SDADC2" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC2 + select STM32_SDADC2_HAVE_DMA if STM32_DMA2 + +config STM32_SDADC3 + bool "SDADC3" + default n + select STM32_SDADC + depends on STM32_HAVE_SDADC3 + select STM32_SDADC3_HAVE_DMA if STM32_DMA2 + +# DAC peripherals + +config STM32_DAC1 + bool "DAC1" + depends on STM32_HAVE_DAC1 + select STM32_DAC if !ARCH_CHIP_STM32U5 + +config STM32_DAC2 + bool "DAC2" + depends on STM32_HAVE_DAC2 + select STM32_DAC + +config STM32_DAC1CH1 + bool "DAC1CH1" + default n + depends on STM32_DAC1 + +config STM32_DAC1CH2 + bool "DAC1CH2" + default n + depends on STM32_DAC1 + +config STM32_DAC2CH1 + bool "DAC2CH1" + default n + depends on STM32_DAC2 + +config STM32_DAC3 + bool "DAC3" + default n + depends on STM32_HAVE_DAC3 + select STM32_DAC + +config STM32_DAC3CH1 + bool "DAC3CH1 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC3CH2 + bool "DAC3CH2 Internal" + default n + depends on STM32_DAC3 + +config STM32_DAC4 + bool "DAC4" + default n + depends on STM32_HAVE_DAC4 + select STM32_DAC + +config STM32_DAC4CH1 + bool "DAC4CH1 Internal" + default n + depends on STM32_DAC4 + +config STM32_DAC4CH2 + bool "DAC4CH2 Internal" + default n + depends on STM32_DAC4 + +# DFSDM peripherals + +config STM32_MDF1 + depends on STM32_HAVE_MDF1 + bool "MDF1" + default n + +config STM32_ADF1 + depends on STM32_HAVE_ADF1 + bool "ADF1" + default n + +config STM32_DFSDM1 + bool "DFSDM1" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_HAVE_DFSDM1 + select ARCH_HAVE_DFSDM1 if ARCH_CHIP_STM32F7 && STM32_HAVE_DFSDM1 + +# CAN peripherals + +config STM32_CAN1 + bool "CAN1" + depends on STM32_HAVE_CAN1 + select STM32_CAN + select CAN + +config STM32_CAN2 + bool "CAN2" + depends on STM32_HAVE_CAN2 + select STM32_CAN + select CAN + +config STM32_CAN3 + bool "CAN3" + depends on STM32_HAVE_CAN3 + select STM32_CAN + select CAN + +config STM32_FDCAN1 + bool "FDCAN1" + depends on STM32_HAVE_FDCAN1 + select STM32_FDCAN if !ARCH_CHIP_STM32U5 + +config STM32_FDCAN2 + bool "FDCAN2" + depends on STM32_HAVE_FDCAN2 + select STM32_FDCAN + +config STM32_FDCAN3 + bool "FDCAN3" + depends on STM32_HAVE_FDCAN3 + select STM32_FDCAN + +# I2C peripherals + +config STM32_I2C5 + bool "I2C5" + depends on STM32_HAVE_I2C5 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C6 + bool "I2C6" + depends on STM32_HAVE_I2C6 && (STM32_STM32U59XX || STM32_STM32U59AXX || STM32_STM32U5A5XX || STM32_STM32U5A9XX) + default n + select STM32_I2C + +config STM32_I2C1 + bool "I2C1" + depends on STM32_HAVE_I2C1 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB + +config STM32_I2C2 + bool "I2C2" + depends on STM32_HAVE_I2C2 + select STM32_I2C + +config STM32_I2C3 + bool "I2C3" + depends on STM32_HAVE_I2C3 + select STM32_I2C + select I2C if ARCH_CHIP_STM32WB && STM32_HAVE_I2C3 + +config STM32_I2C4 + bool "I2C4" + depends on STM32_HAVE_I2C4 + select STM32_I2C + +# +# + +config STM32_I2C1_SLAVE + bool "I2C1 Slave" + default n + depends on !STM32_I2C1 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C2_SLAVE + bool "I2C2 Slave" + default n + depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE + select STM32_I2C_SLAVE + +config STM32_I2C3_SLAVE + bool "I2C3 Slave" + default n + depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE + select STM32_I2C_SLAVE + +# SPI peripherals + +config STM32_SPI1 + bool "SPI1" + depends on STM32_HAVE_SPI1 + select SPI if !ARCH_CHIP_STM32WL5 + select STM32_SPI + +config STM32_SPI2 + bool "SPI2" + depends on STM32_HAVE_SPI2 + select SPI + select STM32_SPI + +config STM32_SPI3 + bool "SPI3" + depends on STM32_HAVE_SPI3 + select SPI + select STM32_SPI + +config STM32_SPI4 + bool "SPI4" + depends on STM32_HAVE_SPI4 + select SPI + select STM32_SPI + +config STM32_SPI5 + bool "SPI5" + depends on STM32_HAVE_SPI5 + select SPI + select STM32_SPI + +config STM32_SPI6 + bool "SPI6" + depends on STM32_HAVE_SPI6 + select SPI + select STM32_SPI + +# SERIAL peripherals + +config STM32_UART9 + bool "UART9" + default n + depends on STM32_HAVE_UART9 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_UART12 + bool "UART12" + default n + depends on STM32_HAVE_UART12 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART10 + bool "USART10" + default n + depends on STM32_HAVE_USART10 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_USART11 + bool "USART11" + default n + depends on STM32_HAVE_USART11 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_USART + +config STM32_SWPMI + bool "SWPMI" + depends on STM32_HAVE_SWPMI + default n + +config STM32_LPUART1 + bool "LPUART1" + depends on STM32_HAVE_LPUART1 + select LPUART1_SERIALDRIVER if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select ARCH_HAVE_LPUART1 if ARCH_CHIP_STM32L4 && STM32_HAVE_LPUART1 || ARCH_CHIP_STM32WB && STM32_HAVE_LPUART + +config STM32_USART4 + bool "USART4" + depends on STM32_HAVE_USART4 + select STM32_USART + +config STM32_USART5 + bool "USART5" + depends on STM32_HAVE_USART5 + select STM32_USART + +config STM32_USART7 + bool "USART7" + depends on STM32_HAVE_USART7 + select STM32_USART + +config STM32_USART8 + bool "USART8" + depends on STM32_HAVE_USART8 + select STM32_USART + +config STM32_USART1 + bool "USART1" + depends on STM32_HAVE_USART1 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART1_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART2 + bool "USART2" + depends on STM32_HAVE_USART2 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART2_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART3 + bool "USART3" + depends on STM32_HAVE_USART3 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART3_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART4 + bool "UART4" + depends on STM32_HAVE_UART4 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART4_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART5 + bool "UART5" + depends on STM32_HAVE_UART5 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART5_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_USART6 + bool "USART6" + depends on STM32_HAVE_USART6 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select USART6_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART7 + bool "UART7" + depends on STM32_HAVE_UART7 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART7_SERIALDRIVER if STM32_COMMON_F7_H7 + +config STM32_UART8 + bool "UART8" + depends on STM32_HAVE_UART8 + select STM32_USART + select ARCH_HAVE_SERIAL_TERMIOS if !STM32_HAVE_IP_USART + select UART8_SERIALDRIVER if STM32_COMMON_F7_H7 + +# TIM peripherals + +config STM32_LPTIM1 + bool "LPTIM1" + depends on STM32_HAVE_LPTIM1 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_TIM1 + bool "TIM1" + depends on STM32_HAVE_TIM1 + select STM32_TIM + +config STM32_TIM2 + bool "TIM2" + depends on STM32_HAVE_TIM2 + select STM32_TIM + +config STM32_TIM3 + bool "TIM3" + depends on STM32_HAVE_TIM3 + select STM32_TIM + +config STM32_TIM4 + bool "TIM4" + depends on STM32_HAVE_TIM4 + select STM32_TIM + +config STM32_TIM5 + bool "TIM5" + depends on STM32_HAVE_TIM5 + select STM32_TIM + +config STM32_TIM6 + bool "TIM6" + depends on STM32_HAVE_TIM6 + select STM32_TIM + +config STM32_TIM7 + bool "TIM7" + depends on STM32_HAVE_TIM7 + select STM32_TIM + +config STM32_TIM8 + bool "TIM8" + depends on STM32_HAVE_TIM8 + select STM32_TIM + +config STM32_TIM9 + bool "TIM9" + depends on STM32_HAVE_TIM9 + select STM32_TIM + +config STM32_TIM10 + bool "TIM10" + depends on STM32_HAVE_TIM10 + select STM32_TIM + +config STM32_TIM11 + bool "TIM11" + depends on STM32_HAVE_TIM11 + select STM32_TIM + +config STM32_TIM12 + bool "TIM12" + depends on STM32_HAVE_TIM12 + select STM32_TIM + +config STM32_TIM13 + bool "TIM13" + depends on STM32_HAVE_TIM13 + select STM32_TIM + +config STM32_TIM14 + bool "TIM14" + depends on STM32_HAVE_TIM14 + select STM32_TIM + +config STM32_TIM15 + bool "TIM15" + depends on STM32_HAVE_TIM15 + select STM32_TIM + +config STM32_TIM16 + bool "TIM16" + depends on STM32_HAVE_TIM16 + select STM32_TIM + +config STM32_TIM17 + bool "TIM17" + depends on STM32_HAVE_TIM17 + select STM32_TIM + +config STM32_LPTIM2 + bool "LPTIM2" + depends on ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32U5 || ARCH_CHIP_STM32WB || ARCH_CHIP_STM32L4 && STM32_HAVE_LPTIM2 + select STM32_LPTIM if ARCH_CHIP_STM32H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + +config STM32_LPTIM3 + bool "LPTIM3" + depends on STM32_HAVE_LPTIM3 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM4 + bool "LPTIM4" + depends on STM32_HAVE_LPTIM4 + select STM32_LPTIM if ARCH_CHIP_STM32H7 + +config STM32_LPTIM5 + bool "LPTIM5" + depends on ARCH_CHIP_STM32H7 + select STM32_LPTIM + +config STM32_HRTIM1 + bool "HRTIM1" + default n + depends on STM32_HAVE_HRTIM1 + select STM32_HRTIM + +config STM32_HRTIM_MASTER + bool "HRTIM MASTER" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Master Timer + +config STM32_HRTIM_TIMA + bool "HRTIM TIMA" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer A + +config STM32_HRTIM_TIMB + bool "HRTIM TIMB" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer B + +config STM32_HRTIM_TIMC + bool "HRTIM TIMC" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer C + +config STM32_HRTIM_TIMD + bool "HRTIM TIMD" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer D + +config STM32_HRTIM_TIME + bool "HRTIM TIME" + default n + depends on STM32_HRTIM1 + ---help--- + Enable HRTIM Timer E + +# USB peripherals + +choice STM32_USBFS_MODE + prompt "USB FS Mode" + depends on STM32_HAVE_USBFS_MODE && STM32_HAVE_USBFS + default STM32_USBFS_NONE + ---help--- + Select the operating mode for the USB_DRD_FS peripheral. + The hardware supports Device or Host, but not simultaneously. + +config STM32_USBFS_NONE + bool "Disabled" + +config STM32_USBFS_DEVICE + bool "USB Device" + select STM32_USBFS + select USBDEV + +config STM32_USBFS_HOST + bool "USB Host" + select USBHOST_HAVE_ASYNCH + select USBHOST + ---help--- + Enable USB host mode for USB_DRD_FS peripheral. + +endchoice + +config STM32_OTGFS + bool "OTG FS" + depends on STM32_HAVE_OTGFS + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGHS + bool "OTG HS" + depends on STM32_HAVE_OTGHS && (!ARCH_CHIP_STM32H7 || EXPERIMENTAL) + select USBHOST_HAVE_ASYNCH if !ARCH_CHIP_STM32U5 && USBHOST + +config STM32_OTGFSHS + bool "OTG FS/HS" + depends on ARCH_CHIP_STM32F7 + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32_USB + bool "USB Device" + depends on STM32_HAVE_USBDEV + select USBDEV + +config STM32_USBFS + bool "USB Full Speed Device" + depends on STM32_HAVE_USBFS + select USBDEV + select USBDEV if STM32_COMMON_LEGACY || ARCH_CHIP_STM32L4 + +config STM32_USBHOST + bool "Enable USB Host Support" + depends on STM32_COMMON_LEGACY && (STM32_OTGFS || STM32_OTGHS) + default n + select USBHOST + +config STM32_UCPD + bool "UCPD (USB Type C Power Delivery)" + default n + depends on STM32_HAVE_UCPD + select USBDEV + +config STM32_UCPD1 + depends on STM32_HAVE_UCPD1 + bool "UCPD1" + default n + +# CEC peripherals + +config STM32_CEC + bool "CEC" + depends on STM32_HAVE_CEC + +# SDIO peripherals + +config STM32_SDIO + bool "SDIO" + depends on (STM32_COMMON_LEGACY && !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE) + select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select ARCH_HAVE_SDIO_PREFLIGHT + +config STM32_SDMMC1 + bool "SDMMC1" + depends on STM32_HAVE_SDMMC1 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if STM32_COMMON_F7_H7 + select SCHED_HPWORK if ARCH_CHIP_STM32L4 + select STM32_SAI1PLL if ARCH_CHIP_STM32L4 + +config STM32_SDMMC2 + bool "SDMMC2" + depends on STM32_HAVE_SDMMC2 + select STM32_SDMMC if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE if !ARCH_CHIP_STM32U5 + select ARCH_HAVE_SDIO_PREFLIGHT if !ARCH_CHIP_STM32U5 + select SDIO_BLOCKSETUP if !ARCH_CHIP_STM32U5 + +# SAI peripherals + +config STM32_SPDIFRX + bool "SPDIFRX" + depends on ARCH_CHIP_STM32F7 + +config STM32_I2S1 + bool "I2S1" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI1 + select STM32_I2S + +config STM32_I2S2 + bool "I2S2" + depends on ARCH_CHIP_STM32F7 && !STM32_SPI2 + select STM32_I2S + +config STM32_I2S3 + bool "I2S3" + depends on STM32_HAVE_I2S3 + select I2S if STM32_COMMON_LEGACY + select STM32_I2S + +config STM32_SPI2S2 + bool "SPI2S2" + depends on STM32_HAVE_SPI2S2 + select STM32_SPI + +config STM32_SAI1 + bool "SAI1" + depends on STM32_HAVE_SAI1 + +config STM32_SAI1_A + bool "SAI1 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI1_B + bool "SAI1 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI1 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2 + bool "SAI2" + depends on STM32_HAVE_SAI2 + +config STM32_SAI2_A + bool "SAI2 Block A" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +config STM32_SAI2_B + bool "SAI2 Block B" + depends on (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_SAI2 + select AUDIO + select I2S + select SCHED_HPWORK + select STM32_SAI + +# QSPI peripherals + +config STM32_QSPI1 + bool "QSPI1" + depends on STM32_HAVE_QSPI1 + default n + +config STM32_OCTOSPIM + depends on STM32_HAVE_OCTOSPIM + bool "OCTOSPIM" + default n + +config STM32_OCTOSPI1 + depends on STM32_HAVE_OCTOSPI1 + bool "OCTOSPI1" + default n + +config STM32_OCTOSPI2 + depends on STM32_HAVE_OCTOSPI2 + bool "OCTOSPI2" + default n + +config STM32_QSPI + bool "QSPI (QUADSPI)" + depends on STM32_HAVE_QSPI || STM32_COMMON_F7_H7 + ---help--- + The STM32L4 QSPI block is intended to support one serial NOR flash device + +# ETH peripherals + +config STM32_ETHMAC + bool "Ethernet MAC" + depends on STM32_HAVE_ETHERNET + select NETDEVICES + select ARCH_HAVE_PHY + select STM32_PHY_HAVE_POLLED if !STM32_COMMON_LEGACY + +# CORDIC peripherals + +config STM32_CORDIC + bool "CORDIC Accelerator" + depends on STM32_HAVE_IP_CORDIC_M3M4_V1 && MATH_CORDIC_USE_Q31 + +config STM32_FMAC + bool "FMAC (Filter Math Accelerator)" + depends on STM32_HAVE_FMAC + +# SENSOR peripherals + +config STM32_DTS + bool "DTS" + depends on STM32_HAVE_DTS + default n + ---help--- + Enable support for the on‑die digital temperature sensor (DTS) + built into STM32H5 devices. When enabled, the driver will register + a `/dev/sensor_tempX` device using the common NuttX sensor framework. + +config STM32_DCMI_PSSI + depends on STM32_HAVE_DCMI_PSSI + bool "DCMI_PSSI" + default n + +config STM32_DCMI + bool "DCMI" + depends on STM32_HAVE_DCMI + ---help--- + The devices embed a camera interface that can connect with camera + modules and CMOS sensors through an 8-bit to 14-bit parallel interface, + to receive video data. + +config STM32_SYSCFG_IOCOMPENSATION + bool "SYSCFG I/O Compensation" + depends on STM32_HAVE_IOCOMPENSATION + select STM32_CSI if ARCH_CHIP_STM32H7 + ---help--- + By default the I/O compensation cell is not used. However when the I/O + output buffer speed is configured in 50 MHz or 100 MHz mode, it is + recommended to use the compensation cell for slew rate control on I/O + tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. + + The I/O compensation cell can be used only when the supply voltage ranges + from 2.4 to 3.6 V. + +config STM32_JPEG + bool "JPEG" + depends on STM32_HAVE_JPEG + ---help--- + The JPEG codec provides a hardware compressor and decompressor of JPEG + images with full management of JPEG headers. + +config STM32_TSC + bool "TSC" + depends on STM32_HAVE_TSC + +config STM32_COMP1 + bool "COMP1" + select STM32_COMP + depends on STM32_HAVE_COMP1 + +config STM32_COMP2 + bool "COMP2" + select STM32_COMP + depends on STM32_HAVE_COMP2 + +config STM32_COMP3 + bool "COMP3" + default n + select STM32_COMP + depends on STM32_HAVE_COMP3 + +config STM32_COMP4 + bool "COMP4" + default n + select STM32_COMP + depends on STM32_HAVE_COMP4 + +config STM32_COMP5 + bool "COMP5" + default n + select STM32_COMP + depends on STM32_HAVE_COMP5 + +config STM32_COMP6 + bool "COMP6" + default n + select STM32_COMP + depends on STM32_HAVE_COMP6 + +config STM32_COMP7 + bool "COMP7" + default n + select STM32_COMP + depends on STM32_HAVE_COMP7 + +config STM32_OPAMP1 + bool "OPAMP1" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP1 + +config STM32_OPAMP2 + bool "OPAMP2" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP2 + +config STM32_OPAMP3 + bool "OPAMP3" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP3 + +config STM32_OPAMP4 + bool "OPAMP4" + default n + select STM32_OPAMP + depends on STM32_HAVE_OPAMP4 + +# IPCC peripherals + +config STM32_IPCC + bool "IPCC" + depends on STM32_HAVE_IPCC + select IPCC if ARCH_CHIP_STM32WL5 + ---help--- + IPCC - Inter Processor Communication Controller. A very simple + character device stream driver to exchange data between + CM0 and CM4. + +config STM32_HSEM + bool "Hardware semaphore" + depends on STM32_HAVE_HSEM + default n + +# Display peripherals + +config STM32_LCD + bool "Segment LCD" + depends on STM32_HAVE_LCD + select USBDEV if STM32_COMMON_F0_L0_G0_C0 && STM32_HAVE_LCD + +config STM32_DSIHOST + bool "DSIHOST" + depends on STM32_HAVE_DSIHOST + ---help--- + The DSI Host is a dedicated peripheral for interfacing with MIPI DSI + compliant displays. + +config STM32_LTDC + bool "LTDC" + depends on STM32_HAVE_LTDC + select FB + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +endmenu # STM32 Peripheral Support diff --git a/arch/arm/src/common/stm32/Kconfig.qspi b/arch/arm/src/common/stm32/Kconfig.qspi new file mode 100644 index 00000000000..98344097cd5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.qspi @@ -0,0 +1,158 @@ +# +# STM32 QSPI/OCTOSPI configuration options. +# + +choice + prompt "DMA Channel" + default STM32_QSPI_DMA_CHAN_1_5 + depends on ARCH_CHIP_STM32L4 + ---help--- + You can choose between two DMA channels for use with QSPI: + either DMA1 channel 5, or DMA2 channel 7. + If you only see one choice here, it is probably because + you have not also enabled the associated DMA controller. + +config STM32_QSPI_DMA_CHAN_1_5 + bool "DMA1 Channel 5" + depends on STM32_DMA1 && !STM32_DMAMUX + ---help--- + Use DMA1 channel 5 for QSPI. + +config STM32_QSPI_DMA_CHAN_2_7 + bool "DMA2 Channel 7" + depends on STM32_DMA2 && !STM32_DMAMUX + ---help--- + Use DMA2 channel 7 for QSPI. + +endchoice + +choice + prompt "Transfer technique" + default STM32_QSPI_DMA + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_POLLING + bool "Polling" + ---help--- + Use conventional register I/O with status polling to transfer data. + +config STM32_QSPI_INTERRUPTS + bool "Interrupts" + ---help--- + User interrupt driven I/O transfers. + +config STM32_QSPI_DMA + bool "DMA" + depends on STM32_DMA + ---help--- + Use DMA to improve QSPI transfer performance. + +endchoice + +choice + prompt "Bank selection" + default STM32_QSPI_MODE_BANK1 + ---help--- + You can choose between using polling, interrupts, or DMA to transfer data + over the QSPI interface. + +config STM32_QSPI_MODE_BANK1 + bool "Bank 1" + +config STM32_QSPI_MODE_BANK2 + bool "Bank 2" + +config STM32_QSPI_MODE_DUAL + bool "Dual Bank" + +endchoice + +choice + prompt "DMA Priority" + depends on STM32_QSPI_DMA && STM32_DMA + default STM32_QSPI_DMAPRIORITY_MEDIUM + ---help--- + The DMA controller supports priority levels. You are probably fine + with the default of 'medium' except for special cases. In the event + of contention between to channels at the same priority, the lower + numbered channel has hardware priority over the higher numbered one. + +config STM32_QSPI_DMAPRIORITY_VERYHIGH + bool "Very High priority" + depends on STM32_DMA + ---help--- + 'Highest' priority. + +config STM32_QSPI_DMAPRIORITY_HIGH + bool "High priority" + depends on STM32_DMA + ---help--- + 'High' priority. + +config STM32_QSPI_DMAPRIORITY_MEDIUM + bool "Medium priority" + depends on STM32_DMA + ---help--- + 'Medium' priority. + +config STM32_QSPI_DMAPRIORITY_LOW + bool "Low priority" + depends on STM32_DMA + ---help--- + 'Low' priority. + +endchoice + +config STM32_QSPI_FLASH_SIZE + int "Size of attached serial flash, bytes" + default 16777216 + range 1 2147483647 if ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 2147483648 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires the size of the Flash be specified + +config STM32_QSPI_FIFO_THESHOLD + int "Number of bytes before asserting FIFO threshold flag" + default 4 + range 1 16 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 32 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that the FIFO threshold be specified + I would leave it at the default value of 4 unless you know what you are doing. + +config STM32_QSPI_CSHT + int "Number of cycles Chip Select must be inactive between transactions" + default 5 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + default 1 + range 1 8 if STM32_COMMON_F7_H7 && STM32_QSPI || ARCH_CHIP_STM32L4 && STM32_QSPI + range 1 64 if ARCH_CHIP_STM32H5 && STM32_QSPI1 + ---help--- + The STM32F7 QSPI peripheral requires that it be specified the minimum number + of AHB cycles that Chip Select be held inactive between transactions. + +config STM32_QSPI_DMATHRESHOLD + int "QSPI DMA threshold" + depends on STM32_QSPI_DMA + default 4 + ---help--- + When QSPI DMA is enabled, small DMA transfers will still be performed + by polling logic. This value is the threshold below which transfers + will still be performed by conventional register status polling. + +config STM32_QSPI_DMADEBUG + bool "QSPI DMA transfer debug" + depends on STM32_QSPI_DMA && DEBUG_SPI && DEBUG_DMA + ---help--- + Enable special debug instrumentation to analyze QSPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_QSPI_REGDEBUG + bool "QSPI Register level debug" + depends on DEBUG_SPI_INFO + ---help--- + Output detailed register-level QSPI device debug information. + Requires also CONFIG_DEBUG_SPI_INFO. diff --git a/arch/arm/src/common/stm32/Kconfig.rtc b/arch/arm/src/common/stm32/Kconfig.rtc new file mode 100644 index 00000000000..b81e7986007 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.rtc @@ -0,0 +1,93 @@ +# +# STM32 common RTC options. +# + +choice + prompt "RTC clock source" + depends on STM32_RTC + default STM32_RTC_LSECLOCK + +config STM32_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +config STM32_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +endchoice # RTC clock source + +config STM32_RTC_MAGIC_REG + int "BKP register" + depends on STM32_HAVE_RTC_MAGIC + default 0 + range 0 19 if STM32_COMMON_LEGACY && STM32_RTC && !STM32_HAVE_RTC_COUNTER + range 0 31 if STM32_HAVE_RTC_SUBSECONDS || ARCH_CHIP_STM32U5 + ---help--- + The BKP register used to store/check the Magic value to determine if + RTC is already setup + +config STM32_RTC_MAGIC + hex "RTC Magic 1" + depends on STM32_HAVE_RTC_MAGIC + default 0xfacefeed + ---help--- + Value used as Magic to determine if the RTC is already setup + +config STM32_RTC_MAGIC_TIME_SET + hex "RTC Magic 2" + depends on STM32_HAVE_RTC_MAGIC + default 0xf00dface + ---help--- + Value used as Magic to determine if the RTC has been setup and has + time set + +config STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + bool "Automatically boost the LSE oscillator drive capability level until it starts-up" + depends on (STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && STM32_RTC && STM32_RTC_LSECLOCK + ---help--- + This will cycle through the values from low to high. To avoid + damaging the crystal. We want to use the lowest setting that gets + the OSC running. See app note AN2867 + + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_START_DRV_CAPABILITY + int "LSE oscillator drive capability level at LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY + int "LSE oscillator drive capability level after LSE start-up" + depends on ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB) && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_COMMON_L5_U5 + default 0 + range 0 3 if ((STM32_COMMON_F7_H7 || STM32_COMMON_L5_U5) && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY) || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32WB + ---help--- + 0 = Low drive capability (default) + 1 = Medium high drive capability + 2 = Medium low drive capability + 3 = High drive capability + +config STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY + bool "Decrease LSE oscillator drive capability after LSE start-up" + depends on STM32_COMMON_L5_U5 && STM32_RTC && STM32_RTC_LSECLOCK && !STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY + ---help--- + The LSE oscillator drive capability can remain at the level used + during LSE start-up at run-time, or it can be reduced to the + 'Low drive capability' once the LSE started up successfully. diff --git a/arch/arm/src/common/stm32/Kconfig.sai b/arch/arm/src/common/stm32/Kconfig.sai new file mode 100644 index 00000000000..67a8c8ef710 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sai @@ -0,0 +1,88 @@ +# +# STM32 common SAI options. +# + +choice + prompt "Operation mode" + depends on STM32_SAI + default STM32_SAI_DMA + ---help--- + Select the operation mode the SAI driver should use. + +config STM32_SAI_POLLING + bool "Polling" + ---help--- + The SAI registers are polled for events. + +config STM32_SAI_INTERRUPTS + bool "Interrupt" + ---help--- + Select to enable interrupt driven SAI support. + +config STM32_SAI_DMA + bool "DMA" + ---help--- + Use DMA to improve SAI transfer performance. + +endchoice # Operation mode + +choice + prompt "SAI1 synchronization enable" + depends on STM32_SAI1_A && STM32_SAI1_B + default STM32_SAI1_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI1_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI1_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI1_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI1 synchronization enable + +choice + prompt "SAI2 synchronization enable" + depends on STM32_SAI2_A && STM32_SAI2_B + default STM32_SAI2_BOTH_ASYNC + ---help--- + Select the synchronization mode of the SAI sub-blocks + +config STM32_SAI2_BOTH_ASYNC + bool "Both asynchronous" + +config STM32_SAI2_A_SYNC_WITH_B + bool "Block A is synchronous with Block B" + +config STM32_SAI2_B_SYNC_WITH_A + bool "Block B is synchronous with Block A" + +endchoice # SAI2 synchronization enable + +config STM32_SAI1PLL + bool "SAI1PLL" + depends on STM32_COMMON_L4_L5_U5 + ---help--- + The STM32L4 has a separate PLL for the SAI1 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAI2PLL + bool "SAI2PLL" + depends on STM32_COMMON_L4_L5_U5 && STM32_HAVE_SAI2 + ---help--- + The STM32L4 has a separate PLL for the SAI2 block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_SAIPLL + bool "SAIPLL" + default n + depends on STM32_HAVE_SAIPLL + ---help--- + The STM32F446 has a separate PLL for the SAI block. + Set this true and provide configuration parameters in + board.h to use this PLL. diff --git a/arch/arm/src/common/stm32/Kconfig.sdadc b/arch/arm/src/common/stm32/Kconfig.sdadc new file mode 100644 index 00000000000..c2295fd5fe0 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdadc @@ -0,0 +1,39 @@ +# +# STM32 common SDADC options. +# + +config STM32_SDADC1_HAVE_DMA + bool + +config STM32_SDADC2_HAVE_DMA + bool + +config STM32_SDADC3_HAVE_DMA + bool + +config STM32_SDADC1_DMA + bool "SDADC1 DMA" + depends on STM32_SDADC1 && STM32_SDADC1_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC2_DMA + bool "SDADC2 DMA" + depends on STM32_SDADC2 && STM32_SDADC2_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. + +config STM32_SDADC3_DMA + bool "SDADC3 DMA" + depends on STM32_SDADC3 && STM32_SDADC3_HAVE_DMA + default n + ---help--- + If DMA is selected, then the SDADC may be configured to support + DMA transfer, which is advisable if multiple channels are read + or if very high trigger frequencies are used. diff --git a/arch/arm/src/common/stm32/Kconfig.sdio b/arch/arm/src/common/stm32/Kconfig.sdio new file mode 100644 index 00000000000..7e11939f9e5 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.sdio @@ -0,0 +1,150 @@ +# +# STM32 common SDIO options. +# + +config STM32_SDMMC2_HAVE_DMAPRIO + bool + default y if ARCH_CHIP_STM32F7 + +config STM32_SDIO_CARD + bool "SDIO Card support" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config STM32_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDIO_DMA + bool "Support DMA data transfers" + default STM32_DMA2 + select SDIO_DMA + depends on STM32_COMMON_LEGACY && STM32_SDIO + depends on STM32_DMA2 + ---help--- + Support DMA data transfers. Requires STM32_SDIO and config STM32_DMA2. + +config STM32_SDIO_DMAPRIO + hex "SDIO DMA priority" + default 0x00001000 if STM32_STM32F10XX + default 0x00010000 if !STM32_STM32F10XX + depends on STM32_COMMON_LEGACY && STM32_SDIO + ---help--- + Select SDIO DMA priority. + + For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, + 0x00002000 high, 0x00003000 very high. Default: medium. + + For other STM32's, options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config STM32_SDIO_WIDTH_D1_ONLY + bool "Use D1 only" + depends on STM32_COMMON_LEGACY && STM32_SDIO + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config STM32_SDMMC_IDMA + bool "Support IDMA data transfers" + depends on ARCH_CHIP_STM32H7 && STM32_SDMMC + default y + select SDIO_DMA + ---help--- + Support IDMA data transfers. + +if STM32_SDMMC + +config STM32_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +config STM32_SDMMC_DMA + bool "Support DMA data transfers" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC && STM32_DMA + select SDIO_DMA + ---help--- + Support DMA data transfers. + +config STM32_SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + depends on (ARCH_CHIP_STM32F7 || STM32_COMMON_L4_L5_U5) && STM32_SDMMC1 + default 0x00010000 if ARCH_CHIP_STM32F7 + default 0x00001000 + ---help--- + Select SDMMC1 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + depends on STM32_SDMMC1 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC1_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC1_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC1 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +config SDMMC2_SDIO_MODE + bool "SDIO Card Support" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + Build in additional support needed only for SDIO cards (vs. SD + memory cards) + +config SDMMC2_SDIO_PULLUP + bool "Enable internal Pull-Ups" + depends on STM32_COMMON_F7_H7 && STM32_SDMMC && STM32_SDMMC2 + ---help--- + If you are using an external SDCard module that does not have the + pull-up resistors for the SDIO interface (like the Gadgeteer SD Card + Module) then enable this option to activate the internal pull-up + resistors. + +config STM32_SDMMC2_DMAPRIO + hex "SDMMC2 DMA priority" + default 0x00010000 + depends on STM32_SDMMC2 && STM32_SDMMC2_HAVE_DMAPRIO + ---help--- + Select SDMMC2 DMA priority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +endif # STM32_SDMMC diff --git a/arch/arm/src/common/stm32/Kconfig.spi b/arch/arm/src/common/stm32/Kconfig.spi new file mode 100644 index 00000000000..cf360f805c9 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.spi @@ -0,0 +1,300 @@ +# +# STM32 common SPI options. +# + +config STM32_SPI_DMA + bool + depends on STM32_HAVE_SPI_CORE_DMA + +config STM32_SPI_INTERRUPTS + bool "Interrupt driver SPI" + depends on STM32_SPI + depends on STM32_COMMON_FULL_FEATURED || ARCH_CHIP_STM32WL5 || ARCH_CHIP_STM32WB && (STM32_SPI1 || STM32_SPI2) + ---help--- + Select to enable interrupt driven SPI support. Non-interrupt-driven, + poll-waiting is recommended if the interrupt rate would be to high in + the interrupt driven case. + +config STM32_SPI1_DMA + bool "SPI1 DMA" + depends on STM32_SPI && STM32_SPI1 + depends on STM32_HAVE_SPI_DMA_FAMILY_WL5 && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI1 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_DMA_BUFFER + int "SPI1 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI1_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI1. + +config STM32_SPI_DMATHRESHOLD + int "SPI DMA threshold" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WL5) && STM32_SPI_DMA + default 4 + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config STM32_SPI2_DMA + bool "SPI2 DMA" + depends on STM32_SPI && STM32_SPI2 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI2_DMA_BUFFER + int "SPI2 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI2_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2. + +config STM32_SPI3_DMA + bool "SPI3 DMA" + depends on STM32_SPI && STM32_SPI3 + depends on STM32_HAVE_SPI_DMA_FAMILY && !STM32_SPI_INTERRUPT || STM32_COMMON_F0_L0_G0_C0 && !STM32_SPI_INTERRUPTS + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI3 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI3_DMA_BUFFER + int "SPI3 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI3_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI3. + +config STM32_SPI4_DMA + bool "SPI4 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI4 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI4_DMA_BUFFER + int "SPI4 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI4_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI4. + +config STM32_SPI5_DMA + bool "SPI5 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI5 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI5_DMA_BUFFER + int "SPI5 DMA buffer size" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI5_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI5. + +config STM32_SPI6_DMA + bool "SPI6 DMA" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F7_H7_H5) && STM32_SPI && STM32_SPI6 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. Cannot be used with STM32_SPI_INTERRUPT. + +config STM32_SPI1_COMMTYPE + int "SPI1 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI1 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI2_COMMTYPE + int "SPI2 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI2 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI3_COMMTYPE + int "SPI3 Operation mode" + depends on (STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_H7_H5) && STM32_SPI && STM32_SPI3 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_DMA_BUFFER + int "SPI6 DMA buffer size" + depends on (STM32_COMMON_F7_H7_H5) && STM32_SPI6_DMA + default 0 + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI6. + +config STM32_SPI4_COMMTYPE + int "SPI4 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI4 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI5_COMMTYPE + int "SPI5 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI5 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +config STM32_SPI6_COMMTYPE + int "SPI6 Operation mode" + depends on STM32_COMMON_H7_H5 && STM32_SPI && STM32_SPI6 + default 0 + range 0 3 + ---help--- + Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) + +menu "I2S Configuration" + depends on STM32_I2S + +config STM32_SPI2S2_DMA + bool "SPI2S2 DMA" + depends on STM32_SPI2 && !STM32_SPI_INTERRUPT + select STM32_SPI_DMA + ---help--- + Use DMA to improve SPI2S2 transfer performance. Cannot be used with + STM32_SPI_INTERRUPT. + +config STM32_SPI2S2_DMA_BUFFER + int "SPI2S2 DMA buffer size" + default 0 + depends on STM32_SPI2S2_DMA + ---help--- + Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. + +config STM32_I2S_MAXINFLIGHT + int "I2S queue size" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S) + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +config STM32_I2S3_DATALEN + int "Data width (bits)" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +config STM32_I2S1_MCK + bool "I2S1_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + TBD. + +config STM32_I2S1_RX + bool "Enable I2S1 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S receipt logic + +config STM32_I2S1_TX + bool "Enable I2S1 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + ---help--- + Enable I2S transmission logic + +config STM32_I2S1_DATALEN + int "I2S1 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S1 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S2_MCK + bool "I2S2_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + TBD. + +config STM32_I2S2_RX + bool "Enable I2S2 receiver" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S receipt logic + +config STM32_I2S2_TX + bool "Enable I2S2 transmitter" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + ---help--- + Enable I2S transmission logic + +config STM32_I2S2_DATALEN + int "I2S2 Data width (bits)" + depends on ARCH_CHIP_STM32F7 && STM32_I2S2 + default 16 + ---help--- + Data width in bits. This is a default value and may be changed via + the I2S interface. + +config STM32_I2S3_MCK + bool "I2S3_MCK" + depends on ARCH_CHIP_STM32F7 && STM32_I2S3 + ---help--- + TBD. + +config STM32_I2S3_RX + bool "Enable I2S receiver" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S receipt logic + +config STM32_I2S3_TX + bool "Enable I2S transmitter" + depends on (STM32_COMMON_LEGACY && STM32_I2S3) || (ARCH_CHIP_STM32F7 && STM32_I2S && STM32_I2S3) + ---help--- + Enable I2S transmission logic + +config STM32_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG_DMA) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG_DMA) + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on (STM32_COMMON_LEGACY && STM32_I2S3 && DEBUG) || (ARCH_CHIP_STM32F7 && STM32_I2S && DEBUG) + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +config STM32_I2SPLL + bool "I2SPLL" + default n + depends on STM32_HAVE_I2SPLL + ---help--- + The STM32F446 has a separate PLL for the I2S block. + Set this true and provide configuration parameters in + board.h to use this PLL. + +config STM32_I2S_MCK + bool "I2S_MCK" + depends on STM32_I2S3 + default n + ---help--- + TBD. + +endmenu # I2S Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.system b/arch/arm/src/common/stm32/Kconfig.system new file mode 100644 index 00000000000..2398b1b534c --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.system @@ -0,0 +1,107 @@ +# +# STM32 common SYSTEM options. +# + +config STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG + bool "Disable IDLE Sleep (WFI) in debug mode" + depends on STM32_COMMON_LEGACY || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + ---help--- + In debug configuration, disables the WFI instruction in the IDLE loop + to prevent the JTAG from disconnecting. With some JTAG debuggers, such + as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI + instruction, the debugger will disconnect, terminating the debug session. + +choice + prompt "JTAG Configuration" + default STM32_JTAG_DISABLE + ---help--- + JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) + +config STM32_JTAG_DISABLE + bool "Disable all JTAG clocking" + +config STM32_JTAG_FULL_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP)" + +config STM32_JTAG_NOJNTRST_ENABLE + bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" + +config STM32_JTAG_SW_ENABLE + bool "Set JTAG-DP disabled and SW-DP enabled" + +endchoice + +config STM32_DFU + bool "DFU bootloader" + depends on (STM32_COMMON_LEGACY || STM32_COMMON_F0_L0_G0_C0) && !(STM32F1_VALUELINE || STM32F0_VALUELINE) + ---help--- + Configure and position code for use with the STMicro DFU bootloader. Do + not select this option if you will load code using JTAG/SWM. + +config STM32_TICKLESS_TIMER + int "Tickless hardware timer" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 2 + range 1 14 if STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7 + range 1 17 if STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provided the timer needed by the OS. + +config STM32_TICKLESS_CHANNEL + int "Tickless timer channel" + depends on SCHED_TICKLESS + depends on (STM32_COMMON_LEGACY && STM32_TIM) || STM32_COMMON_F7_H7_H5 || ARCH_CHIP_STM32WB + default 1 + range 1 4 + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS + and one channel on that clock is needed to handle intervals. + +config STM32_NOEXT_VECTORS + bool "Disable the ARMv7-M EXT vectors" + default n + ---help--- + Sometimes you may not need any Vector support beyond SysTick + and wish to save memory. This applies only to ARMv7-M architectures. + +# Clock options + +choice + prompt "SysTick clock source" + depends on STM32_COMMON_F0_L0_G0_C0 + default STM32_SYSTICK_CORECLK + +config STM32_SYSTICK_CORECLK + bool "Cortex-M0 core clock" + +config STM32_SYSTICK_CORECLK_DIV16 + bool "Cortex-M0 core clock divided by 16" + +endchoice + +config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + bool "Custom clock configuration" + default n + ---help--- + Enables special, board-specific STM32 clock configuration. + +# Power options + +config STM32_FORCEPOWER + bool "Force power" + default n + ---help--- + Timer and I2C devices may need to the following to force power to be applied + unconditionally at power up. (Otherwise, the device is powered when it is + initialized). + +# Debug MCU options + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_CR + bool + +config STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ + bool diff --git a/arch/arm/src/common/stm32/Kconfig.tim b/arch/arm/src/common/stm32/Kconfig.tim new file mode 100644 index 00000000000..c130c6b774b --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.tim @@ -0,0 +1,4205 @@ +# +# STM32 timer configuration options. +# + +config STM32_LPTIM1_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM1_HAVE_CH1NOUT + bool + default y if STM32_LPTIM1_HAVE_CH1OUT && STM32_LPTIM1_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM1_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1OUT + bool + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL1 + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_LPTIM2_HAVE_CH1NOUT + bool + default y if STM32_LPTIM2_HAVE_CH1OUT && STM32_LPTIM2_CH1OUT + default y if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN && STM32_LPTIM2_CHANNEL = 1 + +config STM32_CAP + bool + default n + +config STM32_PULSECOUNT + bool + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F0_L0_G0_C0 || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select ARCH_HAVE_PULSECOUNT + select PULSECOUNT + +config STM32_QE + bool + default n + +config STM32_PWM_MULTICHAN_L5_TIMERS + bool + default y if STM32_TIM1_PWM || STM32_TIM2_PWM || STM32_TIM3_PWM + default y if STM32_TIM4_PWM || STM32_TIM5_PWM || STM32_TIM8_PWM + default y if STM32_TIM15_PWM || STM32_TIM16_PWM || STM32_TIM17_PWM + +config STM32_QENCODER_TIMS_1_4 + bool + default y if STM32_TIM1 || STM32_TIM2 || STM32_TIM3 || STM32_TIM4 + +config STM32_QENCODER_TIMS_1_8 + bool + default y if STM32_QENCODER_TIMS_1_4 + default y if STM32_TIM5 || STM32_TIM8 + +config STM32_QENCODER_MAIN + bool + default y if STM32_HAVE_QENCODER_MAIN && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_STM32 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_8 + +config STM32_QENCODER_F0 + bool + default y if STM32_HAVE_IP_TIMERS && SENSORS_QENCODER && STM32_QENCODER_TIMS_1_4 + +config STM32_PWM + bool + +menu "Timer Configuration" + depends on STM32_HAVE_LPTIM_CHANNEL || STM32_HAVE_TIM_ADC_CHANNEL + +if STM32_LPTIM1_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM1_CHANNEL1 + bool "LPTIM1 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM1_PWM + +if STM32_LPTIM2_PWM + +if STM32_PWM_MULTICHAN + +config STM32_LPTIM2_CHANNEL1 + bool "LPTIM2 Channel 1" + depends on STM32_HAVE_LPTIM_CHANNEL + default n + ---help--- + Enables channel 1. + +endif # STM32_PWM_MULTICHAN + +endif # STM32_LPTIM2_PWM + +config STM32_TIM1_ADC_CHAN + int "TIM1 channel" + default 1 + range 1 4 + depends on STM32_TIM1_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM2_ADC_CHAN + int "TIM2 channel" + default 1 + range 1 4 + depends on STM32_TIM2_ADC + ---help--- + Values 1:CC1 2:CC2 3:CC3 4:CC4 + +config STM32_TIM3_ADC_CHAN + int "TIM3 channel" + default 1 + range 1 4 + depends on STM32_TIM3_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM4_ADC_CHAN + int "TIM4 channel" + default 1 + range 1 4 + depends on STM32_TIM4_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM6_ADC_CHAN + int "TIM6 channel" + default 1 + range 1 4 + depends on STM32_TIM6_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM8_ADC_CHAN + int "TIM8 channel" + default 1 + range 1 4 + depends on STM32_TIM8_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +config STM32_TIM15_ADC_CHAN + int "TIM15 channel" + default 1 + range 1 4 + depends on STM32_TIM15_ADC + ---help--- + Values 1:CC2 2:CC2 3:CC3 4:CC4 + +endmenu # Timer Configuration + +config STM32_TIMX_CAP + bool "Helpers for Capture Drivers" + depends on ARCH_CHIP_STM32H7 + default n + +choice + prompt "Select TIM1 ADC channel" + depends on STM32_TIM1_ADC + default STM32_TIM1_ADC1 + +config STM32_TIM1_ADC1 + bool "TIM1 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC1 + +config STM32_TIM1_ADC2 + bool "TIM1 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC2 + +config STM32_TIM1_ADC3 + bool "TIM1 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM1 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM2 ADC channel" + depends on STM32_TIM2_ADC + default STM32_TIM2_ADC1 + +config STM32_TIM2_ADC1 + bool "TIM2 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC1 + +config STM32_TIM2_ADC2 + bool "TIM2 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC2 + +config STM32_TIM2_ADC3 + bool "TIM2 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM2 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM3 ADC channel" + depends on STM32_TIM3_ADC + default STM32_TIM3_ADC1 + +config STM32_TIM3_ADC1 + bool "TIM3 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC1 + +config STM32_TIM3_ADC2 + bool "TIM3 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC2 + +config STM32_TIM3_ADC3 + bool "TIM3 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM3 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM4 ADC channel" + depends on STM32_TIM4_ADC + default STM32_TIM4_ADC1 + +config STM32_TIM4_ADC1 + bool "TIM4 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC1 + +config STM32_TIM4_ADC2 + bool "TIM4 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC2 + +config STM32_TIM4_ADC3 + bool "TIM4 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM4 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM5 ADC channel" + depends on STM32_TIM5_ADC + default STM32_TIM5_ADC1 + +config STM32_TIM5_ADC1 + bool "TIM5 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC1 + +config STM32_TIM5_ADC2 + bool "TIM5 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC2 + +config STM32_TIM5_ADC3 + bool "TIM5 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM5 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM8 ADC channel" + depends on STM32_TIM8_ADC + default STM32_TIM8_ADC1 + +config STM32_TIM8_ADC1 + bool "TIM8 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC1 + +config STM32_TIM8_ADC2 + bool "TIM8 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC2 + +config STM32_TIM8_ADC3 + bool "TIM8 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM8 to trigger ADC3 + +endchoice + +choice + prompt "Select TIM15 ADC channel" + depends on STM32_TIM15_ADC + default STM32_TIM15_ADC1 + +config STM32_TIM15_ADC1 + bool "TIM15 ADC channel 1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC1 + +config STM32_TIM15_ADC2 + bool "TIM15 ADC channel 2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC2 + +config STM32_TIM15_ADC3 + bool "TIM15 ADC channel 3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM15 to trigger ADC3 + +endchoice + +choice + prompt "Select ADC for use with TIM6" + depends on STM32_TIM6_ADC + default STM32_TIM6_ADC1 + +config STM32_TIM6_ADC1 + bool "Use TIM6 for ADC1" + depends on STM32_ADC1 + select STM32_ADC1_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC1 + +config STM32_TIM6_ADC2 + bool "Use TIM6 for ADC2" + depends on STM32_ADC2 + select STM32_ADC2_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC2 + +config STM32_TIM6_ADC3 + bool "Use TIM6 for ADC3" + depends on STM32_ADC3 + select STM32_ADC3_HAVE_TIMER + ---help--- + Reserve TIM6 to trigger ADC3 + +endchoice + +config STM32_TIM1_ADC + bool "TIM1 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM1 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM2_ADC + bool "TIM2 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM2 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM3_ADC + bool "TIM3 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM3 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM4_ADC + bool "TIM4 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM4 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM5_ADC + bool "TIM5 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM5 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM8_ADC + bool "TIM8 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_ADC && STM32_TIM8 + ---help--- + Reserve timer 1 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +config STM32_TIM15_ADC + bool "TIM15 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM15 && STM32_ADC + ---help--- + Reserve timer 1 for use by ADC + +config STM32_TIM6_ADC + bool "TIM6 ADC" + depends on STM32_HAVE_TIM_ADC_TRIGGER && STM32_TIM6 && STM32_ADC + ---help--- + Reserve timer 6 for use by ADC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for ADC conversion. Note that ADC usage + requires two definition: Not only do you have to assign the timer + for used by the ADC, but then you also have to configure which ADC + channel it is assigned to. + +choice + prompt "Select TIM1 DAC channel" + depends on STM32_TIM1_DAC + default STM32_TIM1_DAC1 + +config STM32_TIM1_DAC1 + bool "TIM1 DAC channel 1" + ---help--- + Reserve TIM1 to trigger DAC1 + +config STM32_TIM1_DAC2 + bool "TIM1 DAC channel 2" + ---help--- + Reserve TIM1 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM2 DAC channel" + depends on STM32_TIM2_DAC + default STM32_TIM2_DAC1 + +config STM32_TIM2_DAC1 + bool "TIM2 DAC channel 1" + ---help--- + Reserve TIM2 to trigger DAC1 + +config STM32_TIM2_DAC2 + bool "TIM2 DAC channel 2" + ---help--- + Reserve TIM2 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM3 DAC channel" + depends on STM32_TIM3_DAC + default STM32_TIM3_DAC1 + +config STM32_TIM3_DAC1 + bool "TIM3 DAC channel 1" + ---help--- + Reserve TIM3 to trigger DAC1 + +config STM32_TIM3_DAC2 + bool "TIM3 DAC channel 2" + ---help--- + Reserve TIM3 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM4 DAC channel" + depends on STM32_TIM4_DAC + default STM32_TIM4_DAC1 + +config STM32_TIM4_DAC1 + bool "TIM4 DAC channel 1" + ---help--- + Reserve TIM4 to trigger DAC1 + +config STM32_TIM4_DAC2 + bool "TIM4 DAC channel 2" + ---help--- + Reserve TIM4 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM5 DAC channel" + depends on STM32_TIM5_DAC + default STM32_TIM5_DAC1 + +config STM32_TIM5_DAC1 + bool "TIM5 DAC channel 1" + ---help--- + Reserve TIM5 to trigger DAC1 + +config STM32_TIM5_DAC2 + bool "TIM5 DAC channel 2" + ---help--- + Reserve TIM5 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM6 DAC channel" + depends on STM32_TIM6_DAC + default STM32_TIM6_DAC1 + +config STM32_TIM6_DAC1 + bool "TIM6 DAC channel 1" + ---help--- + Reserve TIM6 to trigger DAC1 + +config STM32_TIM6_DAC2 + bool "TIM6 DAC channel 2" + ---help--- + Reserve TIM6 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM7 DAC channel" + depends on STM32_TIM7_DAC + default STM32_TIM7_DAC1 + +config STM32_TIM7_DAC1 + bool "TIM7 DAC channel 1" + ---help--- + Reserve TIM7 to trigger DAC1 + +config STM32_TIM7_DAC2 + bool "TIM7 DAC channel 2" + ---help--- + Reserve TIM7 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM8 DAC channel" + depends on STM32_TIM8_DAC + default STM32_TIM8_DAC1 + +config STM32_TIM8_DAC1 + bool "TIM8 DAC channel 1" + ---help--- + Reserve TIM8 to trigger DAC1 + +config STM32_TIM8_DAC2 + bool "TIM8 DAC channel 2" + ---help--- + Reserve TIM8 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM9 DAC channel" + depends on STM32_TIM9_DAC + default STM32_TIM9_DAC1 + +config STM32_TIM9_DAC1 + bool "TIM9 DAC channel 1" + ---help--- + Reserve TIM9 to trigger DAC1 + +config STM32_TIM9_DAC2 + bool "TIM9 DAC channel 2" + ---help--- + Reserve TIM9 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM10 DAC channel" + depends on STM32_TIM10_DAC + default STM32_TIM10_DAC1 + +config STM32_TIM10_DAC1 + bool "TIM10 DAC channel 1" + ---help--- + Reserve TIM10 to trigger DAC1 + +config STM32_TIM10_DAC2 + bool "TIM10 DAC channel 2" + ---help--- + Reserve TIM10 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM11 DAC channel" + depends on STM32_TIM11_DAC + default STM32_TIM11_DAC1 + +config STM32_TIM11_DAC1 + bool "TIM11 DAC channel 1" + ---help--- + Reserve TIM11 to trigger DAC1 + +config STM32_TIM11_DAC2 + bool "TIM11 DAC channel 2" + ---help--- + Reserve TIM11 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM12 DAC channel" + depends on STM32_TIM12_DAC + default STM32_TIM12_DAC1 + +config STM32_TIM12_DAC1 + bool "TIM12 DAC channel 1" + ---help--- + Reserve TIM12 to trigger DAC1 + +config STM32_TIM12_DAC2 + bool "TIM12 DAC channel 2" + ---help--- + Reserve TIM12 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM13 DAC channel" + depends on STM32_TIM13_DAC + default STM32_TIM13_DAC1 + +config STM32_TIM13_DAC1 + bool "TIM13 DAC channel 1" + ---help--- + Reserve TIM13 to trigger DAC1 + +config STM32_TIM13_DAC2 + bool "TIM13 DAC channel 2" + ---help--- + Reserve TIM13 to trigger DAC2 + +endchoice + +choice + prompt "Select TIM14 DAC channel" + depends on STM32_TIM14_DAC + default STM32_TIM14_DAC1 + +config STM32_TIM14_DAC1 + bool "TIM14 DAC channel 1" + ---help--- + Reserve TIM14 to trigger DAC1 + +config STM32_TIM14_DAC2 + bool "TIM14 DAC channel 2" + ---help--- + Reserve TIM14 to trigger DAC2 + +endchoice + +config STM32_TIM1_DAC + bool "TIM1 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM1 && STM32_DAC + ---help--- + Reserve timer 1 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM1 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM2_DAC + bool "TIM2 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM2 && STM32_DAC + ---help--- + Reserve timer 2 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM2 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM3_DAC + bool "TIM3 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM3 && STM32_DAC + ---help--- + Reserve timer 3 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM3 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM4_DAC + bool "TIM4 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM4 && STM32_DAC + ---help--- + Reserve timer 4 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM4 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM5_DAC + bool "TIM5 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM5 && STM32_DAC + ---help--- + Reserve timer 5 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM5 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM6_DAC + bool "TIM6 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM6 && STM32_DAC + ---help--- + Reserve timer 6 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM6 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM7_DAC + bool "TIM7 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM7 && STM32_DAC + ---help--- + Reserve timer 7 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM7 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM8_DAC + bool "TIM8 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM8 && STM32_DAC + ---help--- + Reserve timer 8 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM8 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM9_DAC + bool "TIM9 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM9 && STM32_DAC + ---help--- + Reserve timer 9 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM9 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM10_DAC + bool "TIM10 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM10 && STM32_DAC + ---help--- + Reserve timer 10 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM10 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM11_DAC + bool "TIM11 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM11 && STM32_DAC + ---help--- + Reserve timer 11 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM11 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM12_DAC + bool "TIM12 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM12 && STM32_DAC + ---help--- + Reserve timer 12 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM12 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM13_DAC + bool "TIM13 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM13 && STM32_DAC + ---help--- + Reserve timer 13 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM13 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +config STM32_TIM14_DAC + bool "TIM14 DAC" + depends on STM32_HAVE_TIM_DAC_TRIGGER && STM32_TIM14 && STM32_DAC + ---help--- + Reserve timer 14 for use by DAC + + Timer devices may be used for different purposes. If STM32_TIM14 is + defined then the following may also be defined to indicate that the + timer is intended to be used for DAC conversion. Note that DAC usage + requires two definition: Not only do you have to assign the timer + for used by the DAC, but then you also have to configure which DAC + channel it is assigned to. + +choice + prompt "Input channel sampling frequency" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_FDTS_4 + +config STM32_QENCODER_SAMPLE_FDTS + bool "fDTS" + +config STM32_QENCODER_SAMPLE_CKINT + bool "fCK_INT" + +config STM32_QENCODER_SAMPLE_FDTS_2 + bool "fDTS/2" + +config STM32_QENCODER_SAMPLE_FDTS_4 + bool "fDTS/4" + +config STM32_QENCODER_SAMPLE_FDTS_8 + bool "fDTS/8" + +config STM32_QENCODER_SAMPLE_FDTS_16 + bool "fDTS/16" + +config STM32_QENCODER_SAMPLE_FDTS_32 + bool "fDTS/32" + +endchoice + +choice + prompt "Input channel event count" + depends on STM32_QENCODER_FILTER + default STM32_QENCODER_SAMPLE_EVENT_6 + +config STM32_QENCODER_SAMPLE_EVENT_1 + bool "1" + depends on STM32_QENCODER_SAMPLE_FDTS + +config STM32_QENCODER_SAMPLE_EVENT_2 + bool "2" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_4 + bool "4" + depends on STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_5 + bool "5" + depends on STM32_QENCODER_SAMPLE_FDTS_16 || STM32_QENCODER_SAMPLE_FDTS_32 + +config STM32_QENCODER_SAMPLE_EVENT_6 + bool "6" + depends on !STM32_QENCODER_SAMPLE_FDTS && !STM32_QENCODER_SAMPLE_CKINT + +config STM32_QENCODER_SAMPLE_EVENT_8 + bool "8" + depends on !STM32_QENCODER_SAMPLE_FDTS + +endchoice + +choice + prompt "LPTIM1 clock source" + default STM32_LPTIM1_CLK_APB1 + +config STM32_LPTIM1_CLK_APB1 + bool "Clock LPTIM1 from APB1" + +config STM32_LPTIM1_CLK_LSE + bool "Clock LPTIM1 from LSE" + +config STM32_LPTIM1_CLK_LSI + bool "Clock LPTIM1 from LSI" + +config STM32_LPTIM1_CLK_HSI + bool "Clock LPTIM1 from HSI" + +endchoice + +choice + prompt "LPTIM2 clock source" + default STM32_LPTIM2_CLK_APB1 + +config STM32_LPTIM2_CLK_APB1 + bool "Clock LPTIM2 from APB1" + +config STM32_LPTIM2_CLK_LSE + bool "Clock LPTIM2 from LSE" + +config STM32_LPTIM2_CLK_LSI + bool "Clock LPTIM2 from LSI" + +config STM32_LPTIM2_CLK_HSI + bool "Clock LPTIM2 from HSI" + +endchoice + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_H7_H5 || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32WB || STM32_COMMON_L4_L5_U5 + default y if STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +config STM32_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + depends on STM32_ONESHOT + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || ARCH_CHIP_STM32WB + default 1 + range 1 8 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. This setting pre-allocates some minimal support for each + of the timers and places an upper limit on the number of oneshot + timers that you can use. + +config STM32_PWM_LL_OPS + bool "PWM low-level operations" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + ---help--- + Enable low-level PWM ops. + +config STM32_TIM1_PWM + bool "TIM1 PWM" + depends on STM32_TIM1 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM1_MODE + int "TIM1 Mode" + depends on STM32_TIM1_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM1_LOCK + int "TIM1 Lock Level Configuration" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 1 lock level configuration + +config STM32_TIM1_TDTS + int "TIM1 t_DTS Division" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 1 dead-time and sampling clock (t_DTS) division + +config STM32_TIM1_DEADTIME + int "TIM1 Initial Dead-time" + depends on STM32_TIM1_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 1 initial dead-time + +config STM32_TIM1_CHANNEL1 + bool "TIM1 Channel 1" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM1_CH1MODE + int "TIM1 Channel 1 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH1OUT + bool "TIM1 Channel 1 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM1_CH1NOUT + bool "TIM1 Channel 1 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM1_CHANNEL2 + bool "TIM1 Channel 2" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM1_CH2MODE + int "TIM1 Channel 2 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH2OUT + bool "TIM1 Channel 2 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM1_CH2NOUT + bool "TIM1 Channel 2 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM1_CHANNEL3 + bool "TIM1 Channel 3" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM1_CH3MODE + int "TIM1 Channel 3 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH3OUT + bool "TIM1 Channel 3 Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM1_CH3NOUT + bool "TIM1 Channel 3 Complementary Output" + depends on STM32_TIM1_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM1_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM1_CHANNEL4 + bool "TIM1 Channel 4" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM1_CH4MODE + int "TIM1 Channel 4 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH4OUT + bool "TIM1 Channel 4 Output" + depends on STM32_TIM1_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM1_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM1_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM1_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM1_CHANNEL5 + bool "TIM1 Channel 5 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM1_CH5MODE + int "TIM1 Channel 5 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH5OUT + bool "TIM1 Channel 5 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM1_CHANNEL6 + bool "TIM1 Channel 6 (internal)" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM1_CH6MODE + int "TIM1 Channel 6 Mode" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM1_CH6OUT + bool "TIM1 Channel 6 Output" + depends on STM32_TIM1_PWM && STM32_PWM_MULTICHAN && STM32_TIM1_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM1_CHANNEL + int "TIM1 PWM Output Channel" + depends on (STM32_TIM1_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM1_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM1_CAP + ---help--- + If TIM1 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM1_CHMODE + int "TIM1 Channel Mode" + depends on STM32_TIM1_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_PWM + bool "TIM2 PWM" + depends on STM32_TIM2 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM2_MODE + int "TIM2 Mode" + depends on STM32_TIM2_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM2_CHANNEL1 + bool "TIM2 Channel 1" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM2_CH1MODE + int "TIM2 Channel 1 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH1OUT + bool "TIM2 Channel 1 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM2_CHANNEL2 + bool "TIM2 Channel 2" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM2_CH2MODE + int "TIM2 Channel 2 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH2OUT + bool "TIM2 Channel 2 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM2_CHANNEL3 + bool "TIM2 Channel 3" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM2_CH3MODE + int "TIM2 Channel 3 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH3OUT + bool "TIM2 Channel 3 Output" + depends on STM32_TIM2_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM2_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM2_CHANNEL4 + bool "TIM2 Channel 4" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM2_CH4MODE + int "TIM2 Channel 4 Mode" + depends on STM32_TIM2_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM2_CH4OUT + bool "TIM2 Channel 4 Output" + depends on STM32_TIM2_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM2_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM2_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM2_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM2_CHANNEL + int "TIM2 PWM Output Channel" + depends on (STM32_TIM2_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM2_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM2 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM2_CHMODE + int "TIM2 Channel Mode" + depends on STM32_TIM2_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_PWM + bool "TIM3 PWM" + depends on STM32_TIM3 + depends on STM32_HAVE_TIM_PWM + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 3 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM3 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM3_MODE + int "TIM3 Mode" + depends on STM32_TIM3_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM3_CHANNEL1 + bool "TIM3 Channel 1" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM3_CH1MODE + int "TIM3 Channel 1 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH1OUT + bool "TIM3 Channel 1 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM3_CHANNEL2 + bool "TIM3 Channel 2" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM3_CH2MODE + int "TIM3 Channel 2 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH2OUT + bool "TIM3 Channel 2 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM3_CHANNEL3 + bool "TIM3 Channel 3" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM3_CH3MODE + int "TIM3 Channel 3 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH3OUT + bool "TIM3 Channel 3 Output" + depends on STM32_TIM3_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM3_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM3_CHANNEL4 + bool "TIM3 Channel 4" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_IP_TIMERS || STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM3_CH4MODE + int "TIM3 Channel 4 Mode" + depends on STM32_TIM3_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM3_CH4OUT + bool "TIM3 Channel 4 Output" + depends on STM32_TIM3_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM3_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM3_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM3_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM3_CHANNEL + int "TIM3 PWM Output Channel" + depends on (STM32_TIM3_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM3_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM3 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM3_CHMODE + int "TIM3 Channel Mode" + depends on STM32_TIM3_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_PWM + bool "TIM4 PWM" + depends on STM32_TIM4 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 4 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM4 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM4_MODE + int "TIM4 Mode" + depends on STM32_TIM4_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM4_CHANNEL1 + bool "TIM4 Channel 1" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM4_CH1MODE + int "TIM4 Channel 1 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH1OUT + bool "TIM4 Channel 1 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM4_CHANNEL2 + bool "TIM4 Channel 2" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM4_CH2MODE + int "TIM4 Channel 2 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH2OUT + bool "TIM4 Channel 2 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM4_CHANNEL3 + bool "TIM4 Channel 3" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM4_CH3MODE + int "TIM4 Channel 3 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH3OUT + bool "TIM4 Channel 3 Output" + depends on STM32_TIM4_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM4_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM4_CHANNEL4 + bool "TIM4 Channel 4" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM4_CH4MODE + int "TIM4 Channel 4 Mode" + depends on STM32_TIM4_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM4_CH4OUT + bool "TIM4 Channel 4 Output" + depends on STM32_TIM4_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM4_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM4_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM4_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM4_CHANNEL + int "TIM4 PWM Output Channel" + depends on (STM32_TIM4_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM4_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM4 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM4_CHMODE + int "TIM4 Channel Mode" + depends on STM32_TIM4_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_PWM + bool "TIM5 PWM" + depends on STM32_TIM5 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 5 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM5 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM5_MODE + int "TIM5 Mode" + depends on STM32_TIM5_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM5_CHANNEL1 + bool "TIM5 Channel 1" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM5_CH1MODE + int "TIM5 Channel 1 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH1OUT + bool "TIM5 Channel 1 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM5_CHANNEL2 + bool "TIM5 Channel 2" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM5_CH2MODE + int "TIM5 Channel 2 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH2OUT + bool "TIM5 Channel 2 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM5_CHANNEL3 + bool "TIM5 Channel 3" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM5_CH3MODE + int "TIM5 Channel 3 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH3OUT + bool "TIM5 Channel 3 Output" + depends on STM32_TIM5_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM5_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM5_CHANNEL4 + bool "TIM5 Channel 4" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM5_CH4MODE + int "TIM5 Channel 4 Mode" + depends on STM32_TIM5_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM5_CH4OUT + bool "TIM5 Channel 4 Output" + depends on STM32_TIM5_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM5_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM5_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM5_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM5_CHANNEL + int "TIM5 PWM Output Channel" + depends on (STM32_TIM5_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM5_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 + ---help--- + If TIM5 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM5_CHMODE + int "TIM5 Channel Mode" + depends on STM32_TIM5_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_PWM + bool "TIM8 PWM" + depends on STM32_TIM8 + depends on STM32_HAVE_TIM_PWM_NO_F0 + depends on !STM32_HAVE_IP_TIMERS || STM32_TIM + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + select ARCH_HAVE_PWM_PULSECOUNT if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 8 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM8 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM8_MODE + int "TIM8 Mode" + depends on STM32_TIM8_PWM + default 0 + range 0 4 + ---help--- + Specifies the timer mode. + +config STM32_TIM8_LOCK + int "TIM8 Lock Level Configuration" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 3 + ---help--- + Timer 8 lock level configuration + +config STM32_TIM8_DEADTIME + int "TIM8 Initial Dead-time" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 255 + ---help--- + Timer 8 initial dead-time + +config STM32_TIM8_TDTS + int "TIM8 t_DTS Division" + depends on STM32_TIM8_PWM + depends on STM32_HAVE_TIM_PWM_ADVANCED + default 0 + range 0 2 + ---help--- + Timer 8 dead-time and sampling clock (t_DTS) division + +config STM32_TIM8_CHANNEL1 + bool "TIM8 Channel 1" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM8_CH1MODE + int "TIM8 Channel 1 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH1OUT + bool "TIM8 Channel 1 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM8_CH1NOUT + bool "TIM8 Channel 1 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM8_CHANNEL2 + bool "TIM8 Channel 2" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM8_CH2MODE + int "TIM8 Channel 2 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH2OUT + bool "TIM8 Channel 2 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM8_CH2NOUT + bool "TIM8 Channel 2 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH2OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM8_CHANNEL3 + bool "TIM8 Channel 3" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 3. + +config STM32_TIM8_CH3MODE + int "TIM8 Channel 3 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH3OUT + bool "TIM8 Channel 3 Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 3 output. + +config STM32_TIM8_CH3NOUT + bool "TIM8 Channel 3 Complementary Output" + depends on STM32_TIM8_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL3) || (!STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL = 3 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM8_CH3OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 3 Complementary Output. + +config STM32_TIM8_CHANNEL4 + bool "TIM8 Channel 4" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_HAVE_TIM_PWM_ADVANCED + ---help--- + Enables channel 4. + +config STM32_TIM8_CH4MODE + int "TIM8 Channel 4 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH4OUT + bool "TIM8 Channel 4 Output" + depends on STM32_TIM8_PWM + depends on STM32_PWM_MULTICHAN || (STM32_TIM8_CHANNEL = 4 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on !STM32_PWM_MULTICHAN || STM32_TIM8_CHANNEL4 || (STM32_COMMON_L5_U5 && STM32_TIM8_CHANNEL5) + ---help--- + Enables channel 4 output. + +config STM32_TIM8_CHANNEL5 + bool "TIM8 Channel 5 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 || STM32_COMMON_L5_U5 + ---help--- + Enables channel 5 (not available externally) + +config STM32_TIM8_CH5MODE + int "TIM8 Channel 5 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH5OUT + bool "TIM8 Channel 5 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL5 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 5 output. + +config STM32_TIM8_CHANNEL6 + bool "TIM8 Channel 6 (internal)" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN + depends on (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_F7_H7_H5 + ---help--- + Enables channel 6 (not available externally) + +config STM32_TIM8_CH6MODE + int "TIM8 Channel 6 Mode" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + default 6 + range 0 11 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM8_CH6OUT + bool "TIM8 Channel 6 Output" + depends on STM32_TIM8_PWM && STM32_PWM_MULTICHAN && STM32_TIM8_CHANNEL6 + depends on STM32_HAVE_TIM_PWM_INTERNAL + ---help--- + Enables channel 6 output. + +config STM32_TIM8_CHANNEL + int "TIM8 PWM Output Channel" + depends on (STM32_TIM8_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM8_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 6 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + range 1 4 if !ARCH_CHIP_STM32H7 || !STM32_TIM8_CAP + ---help--- + If TIM8 is enabled for PWM usage, you also need specifies the timer output + channel {1,..,4} + +config STM32_TIM8_CHMODE + int "TIM8 Channel Mode" + depends on STM32_TIM8_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if STM32_HAVE_TIM_PWM_CHMODE_EXTENDED + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 5 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_PWM + bool "TIM9 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 9 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM9 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM9_CHANNEL1 + bool "TIM9 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM9_CH1MODE + int "TIM9 Channel 1 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH1OUT + bool "TIM9 Channel 1 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM9_CHANNEL2 + bool "TIM9 Channel 2" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 2. + +config STM32_TIM9_CH2MODE + int "TIM9 Channel 2 Mode" + depends on STM32_TIM9_PWM && STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM9_CH2OUT + bool "TIM9 Channel 2 Output" + depends on STM32_TIM9_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM9_CHANNEL = 2) + ---help--- + Enables channel 2 output. + +config STM32_TIM9_CHANNEL + int "TIM9 PWM Output Channel" + depends on (STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM9_CAP + ---help--- + If TIM9 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM9_CHMODE + int "TIM9 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM9_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_PWM + bool "TIM10 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 10 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM10 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM10_CHANNEL1 + bool "TIM10 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM10_CH1MODE + int "TIM10 Channel 1 Mode" + depends on STM32_TIM10_PWM && STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM10_CH1OUT + bool "TIM10 Channel 1 Output" + depends on STM32_TIM10_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM10_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM10_CHANNEL + int "TIM10 PWM Output Channel" + depends on (STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM10_CAP + ---help--- + If TIM10 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM10_CHMODE + int "TIM10 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM10_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_PWM + bool "TIM11 PWM" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 11 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM11 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM11_CHANNEL1 + bool "TIM11 Channel 1" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && STM32_PWM_MULTICHAN) + ---help--- + Enables channel 1. + +config STM32_TIM11_CH1MODE + int "TIM11 Channel 1 Mode" + depends on STM32_TIM11_PWM && STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1 + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM11_CH1OUT + bool "TIM11 Channel 1 Output" + depends on STM32_TIM11_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM11_CHANNEL = 1) + ---help--- + Enables channel 1 output. + +config STM32_TIM11_CHANNEL + int "TIM11 PWM Output Channel" + depends on (STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM11_CAP + ---help--- + If TIM11 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM11_CHMODE + int "TIM11 Channel Mode" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32F7 && STM32_TIM11_PWM && !STM32_PWM_MULTICHAN) + default 6 + range 0 11 if STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_PWM + bool "TIM12 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 12 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM12 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM12_CHANNEL1 + bool "TIM12 Channel 1" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM12_CH1MODE + int "TIM12 Channel 1 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH1OUT + bool "TIM12 Channel 1 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM12_CHANNEL2 + bool "TIM12 Channel 2" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM12_CH2MODE + int "TIM12 Channel 2 Mode" + depends on STM32_TIM12_PWM && STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM12_CH2OUT + bool "TIM12 Channel 2 Output" + depends on STM32_TIM12_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM12_CHANNEL = 2 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 2 output. + +config STM32_TIM12_CHANNEL + int "TIM12 PWM Output Channel" + depends on (STM32_TIM12_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM12_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + range 1 2 if !STM32_HAVE_IP_TIMERS || !STM32_TIM12_CAP + ---help--- + If TIM12 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM12_CHMODE + int "TIM12 Channel Mode" + depends on STM32_TIM12_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 9 if ARCH_CHIP_STM32F7 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_PWM + bool "TIM13 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 13 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM13 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM13_CHANNEL1 + bool "TIM13 Channel 1" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM13_CH1MODE + int "TIM13 Channel 1 Mode" + depends on STM32_TIM13_PWM && STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1 + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM13_CH1OUT + bool "TIM13 Channel 1 Output" + depends on STM32_TIM13_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM13_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM13_CHANNEL + int "TIM13 PWM Output Channel" + depends on (STM32_TIM13_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM13_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM13_CAP + ---help--- + If TIM13 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM13_CHMODE + int "TIM13 Channel Mode" + depends on STM32_TIM13_PWM && !STM32_PWM_MULTICHAN + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_PWM + bool "TIM14 PWM" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + ---help--- + Reserve timer 14 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM14 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM14_CHANNEL1 + bool "TIM14 Channel 1" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM14_CH1MODE + int "TIM14 Channel 1 Mode" + depends on STM32_TIM14_PWM && STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1 + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM14_CH1OUT + bool "TIM14 Channel 1 Output" + depends on STM32_TIM14_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM14_CHANNEL = 1 && STM32_HAVE_TIM_PWM_INTERNAL) + ---help--- + Enables channel 1 output. + +config STM32_TIM14_CHANNEL + int "TIM14 PWM Output Channel" + depends on (STM32_TIM14_PWM && !STM32_PWM_MULTICHAN) || (STM32_TIM14_CAP && ((STM32_HAVE_IP_TIMERS && STM32_TIM) || ARCH_CHIP_STM32H7)) + default 1 + range 1 4 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + range 1 1 if !STM32_HAVE_IP_TIMERS || !STM32_TIM14_CAP + ---help--- + If TIM14 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM14_CHMODE + int "TIM14 Channel Mode" + depends on STM32_TIM14_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_IP_TIMERS + default 6 + range 0 11 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY || ARCH_CHIP_STM32F7 + range 0 1 if STM32_HAVE_IP_TIMERS + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_PWM + bool "TIM15 PWM" + depends on STM32_TIM15 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 15 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM15 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM15_LOCK + int "TIM15 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 3 + ---help--- + Timer 15 lock level configuration + +config STM32_TIM15_TDTS + int "TIM15 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 2 + ---help--- + Timer 15 dead-time and sampling clock (t_DTS) division + +config STM32_TIM15_DEADTIME + int "TIM15 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_PWM + default 0 + range 0 255 + ---help--- + Timer 15 initial dead-time + +config STM32_TIM15_CHANNEL1 + bool "TIM15 Channel 1" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM15_CH1MODE + int "TIM15 Channel 1 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH1OUT + bool "TIM15 Channel 1 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM15_CH1NOUT + bool "TIM15 Channel 1 Complementary Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + depends on STM32_HAVE_TIM_PWM_INTERNAL || STM32_TIM15_CH1OUT || !STM32_PWM_MULTICHAN + ---help--- + Enables channel 1 Complementary Output. + +config STM32_TIM15_CHANNEL2 + bool "TIM15 Channel 2" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 2. + +config STM32_TIM15_CH2MODE + int "TIM15 Channel 2 Mode" + depends on STM32_TIM15_PWM && STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 11 if ARCH_CHIP_STM32L4 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || STM32_COMMON_H7_H5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM15_CH2OUT + bool "TIM15 Channel 2 Output" + depends on STM32_TIM15_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL2) || (!STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 2 output. + +config STM32_TIM15_CHANNEL + int "TIM15 PWM Output Channel" + depends on (STM32_TIM15_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM15_CAP) + default 1 + range 1 2 + ---help--- + If TIM15 is enabled for PWM usage, you also need specifies the timer output + channel {1,2} + +config STM32_TIM15_CH2NOUT + bool "TIM15 Channel 2 Complementary Output" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN && STM32_TIM15_CHANNEL = 2 + depends on STM32_HAVE_TIM_PWM_SINGLECHAN + ---help--- + Enables channel 2 Complementary Output. + +config STM32_TIM15_CHMODE + int "TIM15 Channel Mode" + depends on STM32_TIM15_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 9 if (STM32_HAVE_IP_TIMERS && STM32_HAVE_IP_TIMERS_M3M4_V2) || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_LEGACY + range 0 3 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_PWM + bool "TIM16 PWM" + depends on STM32_TIM16 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 16 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM16 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM16_LOCK + int "TIM16 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 3 + ---help--- + Timer 16 lock level configuration + +config STM32_TIM16_TDTS + int "TIM16 t_DTS division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 2 + ---help--- + Timer 16 dead-time and sampling clock (t_DTS) division + +config STM32_TIM16_DEADTIME + int "TIM16 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_PWM + default 0 + range 0 255 + ---help--- + Timer 16 initial dead-time + +config STM32_TIM16_CHANNEL1 + bool "TIM16 Channel 1" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM16_CH1MODE + int "TIM16 Channel 1 Mode" + depends on STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM16_CH1OUT + bool "TIM16 Channel 1 Output" + depends on STM32_TIM16_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM16_CHANNEL + int "TIM16 PWM Output Channel" + depends on (STM32_TIM16_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM16_CAP) + default 1 + range 1 1 + ---help--- + If TIM16 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM16_CHMODE + int "TIM16 Channel Mode" + depends on STM32_TIM16_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_PWM + bool "TIM17 PWM" + depends on STM32_TIM17 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_HAVE_IP_TIMERS || ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5 || STM32_COMMON_L5_U5 + select STM32_PWM if STM32_HAVE_TIM_PWM_STM32PWM + select PWM if ARCH_CHIP_STM32L5 + ---help--- + Reserve timer 17 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_TIM17 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_TIM17_LOCK + int "TIM17 Lock Level Configuration" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 3 + ---help--- + Timer 17 lock level configuration + +config STM32_TIM17_TDTS + int "TIM17 t_DTS Division" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 2 + ---help--- + Timer 17 dead-time and sampling clock (t_DTS) division + +config STM32_TIM17_DEADTIME + int "TIM17 Initial Dead-time" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_PWM || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_PWM + default 0 + range 0 255 + ---help--- + Timer 17 initial dead-time + +config STM32_TIM17_CHANNEL1 + bool "TIM17 Channel 1" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 1. + +config STM32_TIM17_CH1MODE + int "TIM17 Channel 1 Mode" + depends on STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_TIM17_CH1OUT + bool "TIM17 Channel 1 Output" + depends on STM32_TIM17_PWM + depends on (STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1) || (!STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL = 1 && STM32_HAVE_TIM_PWM_SINGLECHAN) + ---help--- + Enables channel 1 output. + +config STM32_TIM17_CHANNEL + int "TIM17 PWM Output Channel" + depends on (STM32_TIM17_PWM && !STM32_PWM_MULTICHAN) || (ARCH_CHIP_STM32H7 && STM32_TIM17_CAP) + default 1 + range 1 1 + ---help--- + If TIM17 is enabled for PWM usage, you also need specifies the timer output + channel {1} + +config STM32_TIM17_CHMODE + int "TIM17 Channel Mode" + depends on STM32_TIM17_PWM && !STM32_PWM_MULTICHAN + default 0 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + default 6 + range 0 7 if STM32_HAVE_TIM_PWM_CHMODE_TIM16_17_EXTENDED + range 0 1 if STM32_HAVE_TIM_PWM_CHMODE_LIMITED + ---help--- + Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. + +config STM32_PWM_MULTICHAN + bool "PWM Multiple Output Channels" + depends on STM32_HAVE_PWM_MULTICHAN + ---help--- + Specifies that the PWM driver supports multiple output + channels per timer. + +config STM32_TIM1_PULSECOUNT + bool "TIM1 pulse count" + depends on STM32_TIM1 + depends on STM32_HAVE_IP_TIMERS || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 1 for pulse count output. + +if STM32_TIM1_PULSECOUNT + +config STM32_TIM1_PULSECOUNT_TDTS + int "TIM1 pulse count clock division" + default 0 + range 0 2 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_CHANNEL + int "TIM1 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM1_PULSECOUNT_POL + int "TIM1 pulse count output polarity" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +config STM32_TIM1_PULSECOUNT_IDLE + int "TIM1 pulse count idle state" + default 0 + range 0 1 + depends on !STM32_HAVE_IP_TIMERS + +endif # STM32_TIM1_PULSECOUNT + +config STM32_TIM8_PULSECOUNT + bool "TIM8 pulse count" + depends on STM32_TIM8 + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM) || STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5 + select STM32_PULSECOUNT + ---help--- + Reserve timer 8 for pulse count output. + +if STM32_TIM8_PULSECOUNT + +config STM32_TIM8_PULSECOUNT_TDTS + int "TIM8 pulse count clock division" + default 0 + range 0 2 + +config STM32_TIM8_PULSECOUNT_CHANNEL + int "TIM8 pulse count channel" + default 1 + range 1 4 + ---help--- + Specifies the timer channel {1,..,4}. + +config STM32_TIM8_PULSECOUNT_POL + int "TIM8 pulse count output polarity" + default 0 + range 0 1 + +config STM32_TIM8_PULSECOUNT_IDLE + int "TIM8 pulse count idle state" + default 0 + range 0 1 + +endif # STM32_TIM8_PULSECOUNT + +config STM32_PWM_TRGO + bool "TIM PWM TRGO support" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_PWM) || (ARCH_CHIP_STM32F7 && STM32_PWM) + ---help--- + Enable TRGO support for PWM driver + +config STM32_TIM1_CAP + bool "TIM1 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 || (STM32_COMMON_F7_H7_H5) && STM32_TIM1 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM1 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CLOCK + int "TIM1 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM1_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM1_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM2_CAP + bool "TIM2 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 || (STM32_COMMON_F7_H7_H5) && STM32_TIM2 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM2 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CLOCK + int "TIM2 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM2_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM2_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM3_CAP + bool "TIM3 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 || (STM32_COMMON_F7_H7_H5) && STM32_TIM3 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM3 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CLOCK + int "TIM3 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM3_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM3_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM4_CAP + bool "TIM4 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 || (STM32_COMMON_F7_H7_H5) && STM32_TIM4 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM4 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CLOCK + int "TIM4 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM4_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM4_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM5_CAP + bool "TIM5 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 || (STM32_COMMON_F7_H7_H5) && STM32_TIM5 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM5 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CLOCK + int "TIM5 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM5_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM5_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM8_CAP + bool "TIM8 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 || (STM32_COMMON_F7_H7_H5) && STM32_TIM8 || STM32_COMMON_L4_L5_U5 && STM32_HAVE_TIM8 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CLOCK + int "TIM8 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM8_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM8_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM9_CAP + bool "TIM9 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9) || (ARCH_CHIP_STM32F7 && STM32_TIM9) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10) || (ARCH_CHIP_STM32F7 && STM32_TIM10) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11) || (ARCH_CHIP_STM32F7 && STM32_TIM11) + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 || (STM32_COMMON_F7_H7_H5) && STM32_TIM12 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CLOCK + int "TIM12 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM12_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM12_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM13_CAP + bool "TIM13 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 || (STM32_COMMON_F7_H7_H5) && STM32_TIM13 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CLOCK + int "TIM13 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM13_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM13_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM14_CAP + bool "TIM14 Capture" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 || (STM32_COMMON_F7_H7_H5) && STM32_TIM14 + select STM32_CAP if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CLOCK + int "TIM14 work frequency for capture" + depends on (STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP) || (ARCH_CHIP_STM32H7 && STM32_TIM14_CAP) + default 1000000 if STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CAP + default 100000 if ARCH_CHIP_STM32H7 && STM32_TIM14_CAP + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +config STM32_TIM1_CH1POL + int "TIM1 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output polarity + +config STM32_TIM1_CH1IDLE + int "TIM1 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 output IDLE + +config STM32_TIM1_CH1NPOL + int "TIM1 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output polarity + +config STM32_TIM1_CH1NIDLE + int "TIM1 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 1 Complementary Output IDLE + +config STM32_TIM1_CH2POL + int "TIM1 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output polarity + +config STM32_TIM1_CH2IDLE + int "TIM1 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 output IDLE + +config STM32_TIM1_CH2NPOL + int "TIM1 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output polarity + +config STM32_TIM1_CH2NIDLE + int "TIM1 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 2 Complementary Output IDLE + +config STM32_TIM1_CH3POL + int "TIM1 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output polarity + +config STM32_TIM1_CH3IDLE + int "TIM1 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 output IDLE + +config STM32_TIM1_CH3NPOL + int "TIM1 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output polarity + +config STM32_TIM1_CH3NIDLE + int "TIM1 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 3 Complementary Output IDLE + +config STM32_TIM1_CH4POL + int "TIM1 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output polarity + +config STM32_TIM1_CH4IDLE + int "TIM1 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH4OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 4 output IDLE + +config STM32_TIM1_CH5POL + int "TIM1 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output polarity + +config STM32_TIM1_CH5IDLE + int "TIM1 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH5OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 5 output IDLE + +config STM32_TIM1_CH6POL + int "TIM1 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output polarity + +config STM32_TIM1_CH6IDLE + int "TIM1 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM1_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM1_CH6OUT + default 0 + range 0 1 + ---help--- + TIM1 Channel 6 output IDLE + +config STM32_TIM2_CH1POL + int "TIM2 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output polarity + +config STM32_TIM2_CH1IDLE + int "TIM2 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH1OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 1 output IDLE + +config STM32_TIM2_CH2POL + int "TIM2 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output polarity + +config STM32_TIM2_CH2IDLE + int "TIM2 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH2OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 2 output IDLE + +config STM32_TIM2_CH3POL + int "TIM2 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output polarity + +config STM32_TIM2_CH3IDLE + int "TIM2 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH3OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 3 output IDLE + +config STM32_TIM2_CH4POL + int "TIM2 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output polarity + +config STM32_TIM2_CH4IDLE + int "TIM2 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM2_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM2_CH4OUT + default 0 + range 0 1 + ---help--- + TIM2 Channel 4 output IDLE + +config STM32_TIM3_CH1POL + int "TIM3 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output polarity + +config STM32_TIM3_CH1IDLE + int "TIM3 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH1OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 1 output IDLE + +config STM32_TIM3_CH2POL + int "TIM3 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output polarity + +config STM32_TIM3_CH2IDLE + int "TIM3 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH2OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 2 output IDLE + +config STM32_TIM3_CH3POL + int "TIM3 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output polarity + +config STM32_TIM3_CH3IDLE + int "TIM3 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH3OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 3 output IDLE + +config STM32_TIM3_CH4POL + int "TIM3 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output polarity + +config STM32_TIM3_CH4IDLE + int "TIM3 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM3_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM3_CH4OUT + default 0 + range 0 1 + ---help--- + TIM3 Channel 4 output IDLE + +config STM32_TIM4_CH1POL + int "TIM4 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output polarity + +config STM32_TIM4_CH1IDLE + int "TIM4 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH1OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 1 output IDLE + +config STM32_TIM4_CH2POL + int "TIM4 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output polarity + +config STM32_TIM4_CH2IDLE + int "TIM4 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH2OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 2 output IDLE + +config STM32_TIM4_CH3POL + int "TIM4 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output polarity + +config STM32_TIM4_CH3IDLE + int "TIM4 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH3OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 3 output IDLE + +config STM32_TIM4_CH4POL + int "TIM4 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output polarity + +config STM32_TIM4_CH4IDLE + int "TIM4 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM4_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM4_CH4OUT + default 0 + range 0 1 + ---help--- + TIM4 Channel 4 output IDLE + +config STM32_TIM5_CH1POL + int "TIM5 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output polarity + +config STM32_TIM5_CH1IDLE + int "TIM5 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH1OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 1 output IDLE + +config STM32_TIM5_CH2POL + int "TIM5 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output polarity + +config STM32_TIM5_CH2IDLE + int "TIM5 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH2OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 2 output IDLE + +config STM32_TIM5_CH3POL + int "TIM5 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output polarity + +config STM32_TIM5_CH3IDLE + int "TIM5 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH3OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 3 output IDLE + +config STM32_TIM5_CH4POL + int "TIM5 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output polarity + +config STM32_TIM5_CH4IDLE + int "TIM5 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM5_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM5_CH4OUT + default 0 + range 0 1 + ---help--- + TIM5 Channel 4 output IDLE + +config STM32_TIM8_CH1POL + int "TIM8 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output polarity + +config STM32_TIM8_CH1IDLE + int "TIM8 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 output IDLE + +config STM32_TIM8_CH1NPOL + int "TIM8 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output polarity + +config STM32_TIM8_CH1NIDLE + int "TIM8 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH1NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 1 Complementary Output IDLE + +config STM32_TIM8_CH2POL + int "TIM8 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output polarity + +config STM32_TIM8_CH2IDLE + int "TIM8 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 output IDLE + +config STM32_TIM8_CH2NPOL + int "TIM8 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output polarity + +config STM32_TIM8_CH2NIDLE + int "TIM8 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH2NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 2 Complementary Output IDLE + +config STM32_TIM8_CH3POL + int "TIM8 Channel 3 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output polarity + +config STM32_TIM8_CH3IDLE + int "TIM8 Channel 3 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 output IDLE + +config STM32_TIM8_CH3NPOL + int "TIM8 Channel 3 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output polarity + +config STM32_TIM8_CH3NIDLE + int "TIM8 Channel 3 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH3NOUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH3NOUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 3 Complementary Output IDLE + +config STM32_TIM8_CH4POL + int "TIM8 Channel 4 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output polarity + +config STM32_TIM8_CH4IDLE + int "TIM8 Channel 4 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH4OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH4OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 4 output IDLE + +config STM32_TIM8_CH5POL + int "TIM8 Channel 5 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output polarity + +config STM32_TIM8_CH5IDLE + int "TIM8 Channel 5 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH5OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH5OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 5 output IDLE + +config STM32_TIM8_CH6POL + int "TIM8 Channel 6 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output polarity + +config STM32_TIM8_CH6IDLE + int "TIM8 Channel 6 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM8_CH6OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM8_CH6OUT + default 0 + range 0 1 + ---help--- + TIM8 Channel 6 output IDLE + +config STM32_TIM9_CH1POL + int "TIM9 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output polarity + +config STM32_TIM9_CH1IDLE + int "TIM9 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH1OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 1 output IDLE + +config STM32_TIM9_CH2POL + int "TIM9 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output polarity + +config STM32_TIM9_CH2IDLE + int "TIM9 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM9_CH2OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM9_CH2OUT + default 0 + range 0 1 + ---help--- + TIM9 Channel 2 output IDLE + +config STM32_TIM10_CH1POL + int "TIM10 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output polarity + +config STM32_TIM10_CH1IDLE + int "TIM10 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM10_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM10_CH1OUT + default 0 + range 0 1 + ---help--- + TIM10 Channel 1 output IDLE + +config STM32_TIM11_CH1POL + int "TIM11 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output polarity + +config STM32_TIM11_CH1IDLE + int "TIM11 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM11_CH1OUT || (ARCH_CHIP_STM32F7 || ARCH_CHIP_STM32L4) && STM32_TIM11_CH1OUT + default 0 + range 0 1 + ---help--- + TIM11 Channel 1 output IDLE + +config STM32_TIM12_CH1POL + int "TIM12 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output polarity + +config STM32_TIM12_CH1IDLE + int "TIM12 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH1OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 1 output IDLE + +config STM32_TIM12_CH2POL + int "TIM12 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output polarity + +config STM32_TIM12_CH2IDLE + int "TIM12 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM12_CH2OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM12_CH2OUT + default 0 + range 0 1 + ---help--- + TIM12 Channel 2 output IDLE + +config STM32_TIM13_CH1POL + int "TIM13 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output polarity + +config STM32_TIM13_CH1IDLE + int "TIM13 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM13_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM13_CH1OUT + default 0 + range 0 1 + ---help--- + TIM13 Channel 1 output IDLE + +config STM32_TIM14_CH1POL + int "TIM14 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output polarity + +config STM32_TIM14_CH1IDLE + int "TIM14 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM14_CH1OUT || (STM32_COMMON_F7_H7 || ARCH_CHIP_STM32L4 || ARCH_CHIP_STM32H5) && STM32_TIM14_CH1OUT + default 0 + range 0 1 + ---help--- + TIM14 Channel 1 output IDLE + +config STM32_TIM15_CH1POL + int "TIM15 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output polarity + +config STM32_TIM15_CH1IDLE + int "TIM15 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 output IDLE + +config STM32_TIM15_CH1NPOL + int "TIM15 Channel 1 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output polarity + +config STM32_TIM15_CH1NIDLE + int "TIM15 Channel 1 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH1NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH1NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 1 Complementary Output IDLE + +config STM32_TIM15_CH2POL + int "TIM15 Channel 2 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output polarity + +config STM32_TIM15_CH2IDLE + int "TIM15 Channel 2 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2OUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 output IDLE + +config STM32_TIM15_CH2NPOL + int "TIM15 Channel 2 Complementary Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output polarity + +config STM32_TIM15_CH2NIDLE + int "TIM15 Channel 2 Complementary Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM15_CH2NOUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM15_CH2NOUT + default 0 + range 0 1 + ---help--- + TIM15 Channel 2 Complementary Output IDLE + +config STM32_TIM16_CH1POL + int "TIM16 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output polarity + +config STM32_TIM16_CH1IDLE + int "TIM16 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM16_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM16_CH1OUT + default 0 + range 0 1 + ---help--- + TIM16 Channel 1 output IDLE + +config STM32_TIM17_CH1POL + int "TIM17 Channel 1 Output polarity" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output polarity + +config STM32_TIM17_CH1IDLE + int "TIM17 Channel 1 Output IDLE" + depends on STM32_HAVE_IP_TIMERS && STM32_TIM && STM32_TIM17_CH1OUT || (ARCH_CHIP_STM32H7 || STM32_COMMON_L4_H5_L5_U5) && STM32_TIM17_CH1OUT + default 0 + range 0 1 + ---help--- + TIM17 Channel 1 output IDLE + +config STM32_QENCODER_DISABLE_EXTEND16BTIMERS + bool "Disable QEncoder timers extension from 16-bit to 32-bit" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Disable the extension of 16-bit timers to 32-bit via interrupt-based + overflow tracking. When enabled, timers will use their native hardware + counter width (16-bit or 32-bit). This reduces interrupt overhead but + limits the position range for 16-bit timers. + +config STM32_QENCODER_INDEX_PIN + bool "Enable QEncoder timers support for index pin" + depends on STM32_HAVE_QENCODER_16BIT + ---help--- + Enable support for quadrature encoder index pin. The index pin can be + used to reset the encoder position to a known value when the index + pulse is detected. + +config STM32_TIM1_QE + bool "TIM1 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM1) || (STM32_HAVE_IP_TIMERS && STM32_TIM1) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM1 + ---help--- + Reserve TIM1 for use by QEncoder. + +config STM32_TIM1_QEPSC + int "TIM1 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM1_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM2_QE + bool "TIM2 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM2) || (STM32_HAVE_IP_TIMERS && STM32_TIM2) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM2 + ---help--- + Reserve TIM2 for use by QEncoder. + +config STM32_TIM2_QEPSC + int "TIM2 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM2_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM3_QE + bool "TIM3 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM3) || (STM32_HAVE_IP_TIMERS && STM32_TIM3) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM3 + ---help--- + Reserve TIM3 for use by QEncoder. + +config STM32_TIM3_QEPSC + int "TIM3 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM3_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM4_QE + bool "TIM4 QE" + depends on (STM32_QENCODER_MAIN && STM32_TIM4) || (STM32_HAVE_IP_TIMERS && STM32_TIM4) + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM4 + ---help--- + Reserve TIM4 for use by QEncoder. + +config STM32_TIM4_QEPSC + int "TIM4 QE pulse prescaler" + depends on (STM32_QENCODER_MAIN || STM32_QENCODER_F0) && STM32_TIM4_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM5_QE + bool "TIM5 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM5 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM5 + ---help--- + Reserve TIM5 for use by QEncoder. + +config STM32_TIM5_QEPSC + int "TIM5 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM5_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_TIM8_QE + bool "TIM8 QE" + depends on STM32_QENCODER_MAIN && STM32_TIM8 + select STM32_QE if STM32_QENCODER_STM32 && STM32_TIM8 + ---help--- + Reserve TIM8 for use by QEncoder. + +config STM32_TIM8_QEPSC + int "TIM8 QE pulse prescaler" + depends on STM32_QENCODER_MAIN && STM32_TIM8_QE + default 1 + ---help--- + This prescaler divides the number of recorded encoder pulses, + limiting the count rate at the expense of resolution. + +config STM32_QENCODER_FILTER + bool "Enable filtering on STM32 QEncoder input" + depends on STM32_QENCODER_MAIN || STM32_QENCODER_F0 + default y + ---help--- + Enable input filtering on quadrature encoder channels to reduce noise. + +config STM32_TIM16_CH1NOUT + bool "TIM16 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM16_PWM && STM32_PWM_MULTICHAN && STM32_TIM16_CHANNEL1 && STM32_TIM16_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM17_CH1NOUT + bool "TIM17 Channel 1 Complementary Output" + depends on (STM32_HAVE_IP_TIMERS || STM32_COMMON_L4_L5_U5) && STM32_TIM17_PWM && STM32_PWM_MULTICHAN && STM32_TIM17_CHANNEL1 && STM32_TIM17_CH1OUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM15_CAP + bool "TIM15 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM15 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM15 + ---help--- + Reserve timer 15 for use by the capture driver. + +config STM32_TIM16_CAP + bool "TIM16 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM16 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM16 + ---help--- + Reserve timer 16 for use by the capture driver. + +config STM32_TIM17_CAP + bool "TIM17 Capture" + depends on STM32_COMMON_H7_H5 && STM32_TIM17 + select STM32_TIMX_CAP if ARCH_CHIP_STM32H7 && STM32_TIM17 + ---help--- + Reserve timer 17 for use by the capture driver. + +config STM32_TIM15_CLOCK + int "TIM15 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM15_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM16_CLOCK + int "TIM16 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM16_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TIM17_CLOCK + int "TIM17 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_TIM17_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CAP + bool "LPTIM1 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 1 for use by the capture driver. + +config STM32_LPTIM1_CLOCK + int "LPTIM1 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM2_CAP + bool "LPTIM2 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 2 for use by the capture driver. + +config STM32_LPTIM2_CLOCK + int "LPTIM2 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM1_CHANNEL + int "LPTIM1 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM1_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM1_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM1. + +config STM32_LPTIM2_CHANNEL + int "LPTIM2 Capture Input Channel" + depends on (ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP) || (ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN) + default 1 + range 1 2 if ARCH_CHIP_STM32H7 && STM32_LPTIM2_CAP + range 1 1 if ARCH_CHIP_STM32L4 && STM32_LPTIM2_PWM && !STM32_PWM_MULTICHAN + ---help--- + Specifies the timer input channel {1,2} for LPTIM2. + +config STM32_LPTIM3_CAP + bool "LPTIM3 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 3 for use by the capture driver. + +config STM32_LPTIM3_CHANNEL + int "LPTIM3 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM3. + +config STM32_LPTIM3_CLOCK + int "LPTIM3 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM3_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM4_CAP + bool "LPTIM4 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 4 for use by the capture driver. + +config STM32_LPTIM4_CHANNEL + int "LPTIM4 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM4. + +config STM32_LPTIM4_CLOCK + int "LPTIM4 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM4_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_LPTIM5_CAP + bool "LPTIM5 Capture" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5 + default n + select STM32_TIMX_CAP + ---help--- + Reserve low-power timer 5 for use by the capture driver. + +config STM32_LPTIM5_CHANNEL + int "LPTIM5 Capture Input Channel" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 1 + range 1 2 + ---help--- + Specifies the timer input channel {1,2} for LPTIM5. + +config STM32_LPTIM5_CLOCK + int "LPTIM5 capture frequency (Hz)" + depends on ARCH_CHIP_STM32H7 && STM32_LPTIM5_CAP + default 100000 + ---help--- + This clock frequency determines the timer's counting rate. + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_ONESHOT + default 2 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + depends on STM32_COMMON_L4_L5_U5 && SCHED_TICKLESS && STM32_FREERUN + default 5 + range 1 8 + ---help--- + If the Tickless OS feature is enabled, then one clock must be + assigned to provide the free-running timer needed by the OS. + +config STM32_LPTIM1_PWM + bool "LPTIM1 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM1 + select PWM + ---help--- + Reserve low-power timer 1 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM1 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM2_PWM + bool "LPTIM2 PWM" + depends on STM32_COMMON_L4_L5_U5 && STM32_LPTIM2 + select PWM + ---help--- + Reserve low-power timer 2 for use by PWM + + Timer devices may be used for different purposes. One special purpose is + to generate modulated outputs for such things as motor control. If STM32_LPTIM2 + is defined then THIS following may also be defined to indicate that + the timer is intended to be used for pulsed output modulation. + +config STM32_LPTIM1_CH1OUT + bool "LPTIM1 Channel 1 Output" + depends on STM32_LPTIM1_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM1_CH1NOUT + bool "LPTIM1 Channel 1 Complementary Output" + depends on STM32_LPTIM1_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_LPTIM2_CH1OUT + bool "LPTIM2 Channel 1 Output" + depends on STM32_LPTIM2_HAVE_CH1OUT + ---help--- + Enables channel 1 output. + +config STM32_LPTIM2_CH1NOUT + bool "LPTIM2 Channel 1 Complementary Output" + depends on STM32_LPTIM2_HAVE_CH1NOUT + ---help--- + Enables channel 1 complementary output. + +config STM32_TIM2_CHANNEL5 + bool "TIM2 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM2_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM3_CHANNEL5 + bool "TIM3 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM3_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM4_CHANNEL5 + bool "TIM4 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM4_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +config STM32_TIM5_CHANNEL5 + bool "TIM5 Channel 4" + depends on STM32_COMMON_L5_U5 && STM32_TIM5_PWM && STM32_PWM_MULTICHAN + ---help--- + Enables channel 4. + +menu "Timer Configuration" + depends on STM32_TIM + +if STM32_TIM9_CAP + +config STM32_TIM9_CLOCK + int "TIM9 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM9_CAP + +if STM32_TIM10_CAP + +config STM32_TIM10_CLOCK + int "TIM10 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM10_CAP + +if STM32_TIM11_CAP + +config STM32_TIM11_CLOCK + int "TIM11 work frequency for capture" + default 1000000 + ---help--- + This clock frequency limiting the count rate at the expense of resolution. + +endif # STM32_TIM11_CAP + +endmenu # Timer Configuration diff --git a/arch/arm/src/common/stm32/Kconfig.uart b/arch/arm/src/common/stm32/Kconfig.uart new file mode 100644 index 00000000000..05836690894 --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.uart @@ -0,0 +1,1245 @@ +# +# STM32 USART/UART configuration options. +# + +config STM32_USART1_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMA2 || STM32_DMAMUX) + default y if ARCH_CHIP_STM32WB && (STM32_DMA) + +config STM32_USART1_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F37XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32G4XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART2_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART2_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART3_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA1 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA1 || STM32_DMAMUX) + +config STM32_USART3_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART4_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART4_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_UART5_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + default y if STM32_STM32L4S9XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32L562XX && (STM32_DMA2 || STM32_DMAMUX) + default y if STM32_STM32U585XX && (STM32_DMA2 || STM32_DMAMUX) + +config STM32_UART5_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F10XX && (STM32_DMA1) + default y if STM32_STM32F20XX && (STM32_DMA1) + default y if STM32_STM32F37XX && (STM32_DMA1) + default y if STM32_STM32F4XXX && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32G4XXX && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + default y if STM32_STM32L15XX && (STM32_DMA1) + +config STM32_USART6_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_USART6_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA2) + default y if STM32_STM32F0 && (STM32_DMA2) + default y if STM32_STM32F20XX && (STM32_DMA2) + default y if STM32_STM32F4XXX && (STM32_DMA2) + default y if STM32_STM32F779AX && (STM32_DMA2) + default y if STM32_STM32G0 && (STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA2) + +config STM32_UART7_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART7_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_RXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if STM32_STM32H56XXX && (STM32_DMA1 || STM32_DMA2) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1 || STM32_DMA2) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_UART8_HAVE_TXDMA + bool + default y if STM32_STM32C0 && (STM32_DMA1) + default y if STM32_STM32F0 && (STM32_DMA1) + default y if STM32_STM32F779AX && (STM32_DMA1) + default y if STM32_STM32G0 && (STM32_DMA1) + default y if ARCH_CHIP_STM32H755XI && (STM32_DMA1) + default y if STM32_STM32L0 && (STM32_DMA1) + +config STM32_1WIREDRIVER + bool + +config USART1_RXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART1_TXDMA + bool + depends on STM32_USART1 && USART1_SERIALDRIVER && STM32_USART1_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART2_RXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART2_TXDMA + bool + depends on STM32_USART2 && USART2_SERIALDRIVER && STM32_USART2_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART3_RXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART3_TXDMA + bool + depends on STM32_USART3 && USART3_SERIALDRIVER && STM32_USART3_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART4_RXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART4_TXDMA + bool + depends on STM32_UART4 && UART4_SERIALDRIVER && STM32_UART4_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART5_RXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART5_TXDMA + bool + depends on STM32_UART5 && UART5_SERIALDRIVER && STM32_UART5_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config USART6_RXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config USART6_TXDMA + bool + depends on STM32_USART6 && USART6_SERIALDRIVER && STM32_USART6_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART7_RXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART7_TXDMA + bool + depends on STM32_UART7 && UART7_SERIALDRIVER && STM32_UART7_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config UART8_RXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_RXDMA + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +config UART8_TXDMA + bool + depends on STM32_UART8 && UART8_SERIALDRIVER && STM32_UART8_HAVE_TXDMA + ---help--- + In high data rate usage, Tx DMA may reduce CPU load + +config STM32_SERIAL_DISABLE_REORDERING + bool "Disable reordering of ttySx devices." + depends on STM32_USART + ---help--- + NuttX per default reorders the serial ports (/dev/ttySx) so that the + console is always on /dev/ttyS0. If more than one UART is in use this + can, however, have the side-effect that all port mappings + (hardware USART1 -> /dev/ttyS0) change if the console is moved to another + UART. This is in particular relevant if a project uses the USB console + in some boards and a serial console in other boards, but does not + want the side effect of having all serial port names change when just + the console is moved from serial to USB. + +choice + prompt "USART1 Driver Configuration" + depends on STM32_USART1 + default STM32_USART1_SERIALDRIVER + +config STM32_USART1_SERIALDRIVER + bool "Standard serial driver" + select USART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART1_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART1_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART1 Driver Configuration + +choice + prompt "USART2 Driver Configuration" + depends on STM32_USART2 + default STM32_USART2_SERIALDRIVER + +config STM32_USART2_SERIALDRIVER + bool "Standard serial driver" + select USART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART2_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART2_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART2 Driver Configuration + +choice + prompt "USART3 Driver Configuration" + depends on STM32_USART3 + default STM32_USART3_SERIALDRIVER + +config STM32_USART3_SERIALDRIVER + bool "Standard serial driver" + select USART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART3_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART3_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART3 Driver Configuration + +choice + prompt "UART4 Driver Configuration" + depends on STM32_UART4 + default STM32_UART4_SERIALDRIVER + +config STM32_UART4_SERIALDRIVER + bool "Standard serial driver" + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART1 Driver Configuration + +choice + prompt "UART5 Driver Configuration" + depends on STM32_UART5 + default STM32_UART5_SERIALDRIVER + +config STM32_UART5_SERIALDRIVER + bool "Standard serial driver" + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # UART5 Driver Configuration + +choice + prompt "USART6 Driver Configuration" + depends on STM32_USART6 + default STM32_USART6_SERIALDRIVER + +config STM32_USART6_SERIALDRIVER + bool "Standard serial driver" + select USART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART6_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_USART6_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # USART6 Driver Configuration + +choice + prompt "USART4 Driver Configuration" + depends on STM32_USART4 + default STM32_USART4_SERIALDRIVER + +config STM32_USART4_SERIALDRIVER + bool "Standard serial driver" + select USART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART4_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART4 Driver Configuration + +choice + prompt "USART5 Driver Configuration" + depends on STM32_USART5 + default STM32_USART5_SERIALDRIVER + +config STM32_USART5_SERIALDRIVER + bool "Standard serial driver" + select USART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART5_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART5 Driver Configuration + +choice + prompt "USART7 Driver Configuration" + depends on STM32_USART7 + default STM32_USART7_SERIALDRIVER + +config STM32_USART7_SERIALDRIVER + bool "Standard serial driver" + select USART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART7 Driver Configuration + +choice + prompt "USART8 Driver Configuration" + depends on STM32_USART8 + default STM32_USART8_SERIALDRIVER + +config STM32_USART8_SERIALDRIVER + bool "Standard serial driver" + select USART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_USART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +endchoice # USART8 Driver Configuration + +choice + prompt "UART7 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART7 + default STM32_UART7_SERIALDRIVER + +config STM32_UART7_SERIALDRIVER + bool "Standard serial driver" + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART7_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART7_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART7 Driver Configuration + +choice + prompt "UART8 Driver Configuration" + depends on STM32_HAVE_IP_USART && STM32_UART8 + default STM32_UART8_SERIALDRIVER + +config STM32_UART8_SERIALDRIVER + bool "Standard serial driver" + select UART8_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select STM32_SERIALDRIVER + +config STM32_UART8_1WIREDRIVER + bool "1-Wire driver" + select STM32_1WIREDRIVER + +config STM32_UART8_HCIUART + bool "Bluetooth HCI-UART" + select STM32_HCIUART + depends on WIRELESS_BLUETOOTH + +endchoice # UART8 Driver Configuration + +config USART1_RS485 + bool "RS-485 on USART1" + depends on STM32_USART1 && USART1_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART1. Your board config will have to + provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be + used with USART1_RXDMA. + +if USART1_RS485 + +config USART1_RS485_DIR_POLARITY + int "USART1 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART1_RS485 + +config USART2_RS485 + bool "RS-485 on USART2" + depends on STM32_USART2 && USART2_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART2. Your board config will have to + provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be + used with USART2_RXDMA. + +if USART2_RS485 + +config USART2_RS485_DIR_POLARITY + int "USART2 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART2_RS485 + +config USART3_RS485 + bool "RS-485 on USART3" + depends on STM32_USART3 && USART3_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART3. Your board config will have to + provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be + used with USART3_RXDMA. + +if USART3_RS485 + +config USART3_RS485_DIR_POLARITY + int "USART3 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART3_RS485 + +config UART4_RS485 + bool "RS-485 on UART4" + depends on STM32_UART4 && UART4_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART4. Your board config will have to + provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be + used with UART4_RXDMA. + +if UART4_RS485 + +config UART4_RS485_DIR_POLARITY + int "UART4 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART4_RS485 + +config UART5_RS485 + bool "RS-485 on UART5" + depends on STM32_UART5 && UART5_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART5. Your board config will have to + provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be + used with UART5_RXDMA. + +if UART5_RS485 + +config UART5_RS485_DIR_POLARITY + int "UART5 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART5_RS485 + +config USART6_RS485 + bool "RS-485 on USART6" + depends on STM32_USART6 && USART6_SERIALDRIVER + ---help--- + Enable RS-485 interface on USART6. Your board config will have to + provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be + used with USART6_RXDMA. + +if USART6_RS485 + +config USART6_RS485_DIR_POLARITY + int "USART6 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # USART6_RS485 + +config UART7_RS485 + bool "RS-485 on UART7" + depends on STM32_UART7 && UART7_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART7. Your board config will have to + provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be + used with UART7_RXDMA. + +if UART7_RS485 + +config UART7_RS485_DIR_POLARITY + int "UART7 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART7_RS485 + +config UART8_RS485 + bool "RS-485 on UART8" + depends on STM32_UART8 && UART8_SERIALDRIVER + ---help--- + Enable RS-485 interface on UART8. Your board config will have to + provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be + used with UART8_RXDMA. + +if UART8_RS485 + +config UART8_RS485_DIR_POLARITY + int "UART8 RS-485 DIR pin polarity" + default 1 + range 0 1 + ---help--- + Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +endif # UART8_RS485 + +if UART9_SERIALDRIVER + +config UART9_RS485 + bool "RS-485 on UART9" + default n + depends on STM32_UART9 + ---help--- + Enable RS-485 interface on UART9. Your board config will have to + provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be + used with UART9_RXDMA. + +config UART9_RS485_DIR_POLARITY + int "UART9 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART9_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART9_RXDMA + bool "UART9 RX DMA" + default n + depends on STM32_UART9 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART9_SERIALDRIVER + +if USART10_SERIALDRIVER + +config USART10_RS485 + bool "RS-485 on USART10" + default n + depends on STM32_USART10 + ---help--- + Enable RS-485 interface on USART10. Your board config will have to + provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be + used with USART10_RXDMA. + +config USART10_RS485_DIR_POLARITY + int "USART10 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART10_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART10_RXDMA + bool "USART10 RX DMA" + default n + depends on STM32_USART10 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART10_SERIALDRIVER + +if USART11_SERIALDRIVER + +config USART11_RS485 + bool "RS-485 on USART11" + default n + depends on STM32_USART11 + ---help--- + Enable RS-485 interface on USART11. Your board config will have to + provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be + used with USART11_RXDMA. + +config USART11_RS485_DIR_POLARITY + int "USART11 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on USART11_RS485 + ---help--- + Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config USART11_RXDMA + bool "USART11 RX DMA" + default n + depends on STM32_USART11 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # USART11_SERIALDRIVER + +if UART12_SERIALDRIVER + +config UART12_RS485 + bool "RS-485 on UART12" + default n + depends on STM32_UART12 + ---help--- + Enable RS-485 interface on UART12. Your board config will have to + provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be + used with UART12_RXDMA. + +config UART12_RS485_DIR_POLARITY + int "UART12 RS-485 DIR pin polarity" + default 1 + range 0 1 + depends on UART12_RS485 + ---help--- + Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which + enables TX (0 - low / nTXEN, 1 - high / TXEN). + +config UART12_RXDMA + bool "UART12 RX DMA" + default n + depends on STM32_UART12 && (STM32_DMA1 || STM32_DMA2) + ---help--- + In high data rate usage, Rx DMA may eliminate Rx overrun errors + +endif # UART12_SERIALDRIVER + +config STM32_SERIAL_RXDMA_BUFFER_SIZE + int "Rx DMA buffer size" + depends on STM32_USART && SERIAL_RXDMA + range 32 4096 + default 32 + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half or this number of bytes. + + Value given here will be rounded up to next multiple of 4 bytes. + +config STM32_FLOWCONTROL_BROKEN + bool "Use Software UART RTS flow control" + depends on STM32_USART + ---help--- + Enable UART RTS flow control using Software. Because STM + Current STM32 have broken HW based RTS behavior (they assert + nRTS after every byte received) Enable this setting workaround + this issue by using software based management of RTS + +config STM32_USART_BREAKS + bool "Add TIOxSBRK to support sending Breaks" + depends on STM32_USART + ---help--- + Add TIOCxBRK routines to send a line break per the STM32 manual, the + break will be a pulse based on the value M. This is not a BSD compatible + break. + +config STM32_SERIALBRK_BSDCOMPAT + bool "Use GPIO To send Break" + depends on STM32_USART_BREAKS + ---help--- + Enable using GPIO on the TX pin to send a BSD compatible break: + TIOCSBRK will start the break and TIOCCBRK will end the break. + The current STM32 U[S]ARTS have no way to leave the break on + (TX=LOW) because software starts the break and then the hardware + automatically clears the break. This makes it difficult to send + a long break. + +config STM32_USART_SINGLEWIRE + bool "Single Wire Support" + depends on STM32_USART + ---help--- + Enable single wire UART support. The option enables support for the + TIOCSSINGLEWIRE ioctl in the STM32 serial driver. + +config STM32_PM_SERIAL_ACTIVITY + int "PM serial activity" + depends on PM + depends on STM32_USART + default 10 + ---help--- + PM activity reported to power management logic on every serial + interrupt. + +config USART1_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART1 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART1 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER + +config USART1_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART1 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART1_SERIALDRIVER && USART1_RS485 + +config USART2_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART2 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART2 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER + +config USART2_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART2 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART2_SERIALDRIVER && USART2_RS485 + +config USART3_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART3 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART3 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER + +config USART3_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART3 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART3_SERIALDRIVER && USART3_RS485 + +config UART4_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART4 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART4 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER + +config UART4_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART4 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART4_SERIALDRIVER && UART4_RS485 + +config UART5_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART5 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART5 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER + +config UART5_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART5 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART5_SERIALDRIVER && UART5_RS485 + +config USART6_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART6 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART6 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER + +config USART6_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART6 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART6_SERIALDRIVER && USART6_RS485 + +config UART7_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART7 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART7 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER + +config UART7_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART7 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART7_SERIALDRIVER && UART7_RS485 + +config UART8_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART8 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART8 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER + +config UART8_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART8 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART8_SERIALDRIVER && UART8_RS485 + +config UART9_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART9 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART9 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER + +config UART9_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART9 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART9_SERIALDRIVER && UART9_RS485 + +config USART10_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART10 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART10 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER + +config USART10_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART10 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART10_SERIALDRIVER && USART10_RS485 + +config USART11_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure USART11 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure USART11 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER + +config USART11_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure USART11 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && USART11_SERIALDRIVER && USART11_RS485 + +config UART12_UNCONFIG_RX_ON_CLOSE + bool "Unconfigure UART12 RX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_TX_ON_CLOSE + bool "Unconfigure UART12 TX pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER + +config UART12_UNCONFIG_DIR_ON_CLOSE + bool "Unconfigure UART12 DIR pin on close" + depends on STM32_HAVE_USART_UNCONFIG_ON_CLOSE && UART12_SERIALDRIVER && UART12_RS485 + +config USART1_RXFIFO_THRES + int "USART1 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART1_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +config USART2_RXFIFO_THRES + int "USART2 Rx FIFO Threshold" + depends on STM32_HAVE_USART_RXFIFO_THRESHOLD && STM32_USART && STM32_USART2_SERIALDRIVER + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +if STM32_USART3 + +config USART3_RXFIFO_THRES + int "USART3 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART3 + +if STM32_UART4 + +config UART4_RXFIFO_THRES + int "UART4 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART4 + +if STM32_UART5 + +config UART5_RXFIFO_THRES + int "UART5 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART5 + +if STM32_USART6 + +config USART6_RXFIFO_THRES + int "USART6 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_USART + +if STM32_UART7 + +config UART7_RXFIFO_THRES + int "UART7 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART7 + +if STM32_UART8 + +config UART8_RXFIFO_THRES + int "UART8 Rx FIFO Threshold" + default 3 + range 0 5 + ---help--- + Select the Rx FIFO threshold: + + 0 -> 1/8 full + 1 -> 1/4 full + 2 -> 1/2 full + 3 -> 3/4 full + 4 -> 7/8 full + 5 -> Full + + Higher values mean lower interrupt rates and better CPU performance. + Lower values may be needed at high BAUD rates to prevent Rx data + overrun errors. + +endif # STM32_UART8 + +config STM32_USART_INVERT + bool "Signal Invert Support" + depends on STM32_USART + ---help--- + Enable signal inversion UART support. The option enables support for the + TIOCSINVERT ioctl in the STM32F7 serial driver. + +config STM32_USART_SWAP + bool "Swap RX/TX pins support" + depends on STM32_USART + ---help--- + Enable RX/TX pin swapping support. The option enables support for the + TIOCSSWAP ioctl in the STM32F7 serial driver. + +source "arch/arm/src/common/stm32/Kconfig.lpuart" +source "arch/arm/src/common/stm32/Kconfig.hciuart" diff --git a/arch/arm/src/common/stm32/Kconfig.usb b/arch/arm/src/common/stm32/Kconfig.usb new file mode 100644 index 00000000000..7f4c969114e --- /dev/null +++ b/arch/arm/src/common/stm32/Kconfig.usb @@ -0,0 +1,249 @@ +# +# STM32 USB configuration options. +# + +menu "USB Full Speed Host Configuration" + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + +config STM32_USBDRD_NCHANNELS + int "Number of host channels" + default 8 + range 1 8 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Number of USB host channels to use. + +config STM32_USBDRD_DESCSIZE + int "Descriptor buffer size" + default 128 + depends on STM32_HAVE_USBDRD_HOST && STM32_USBFS_HOST + ---help--- + Size of descriptor/request buffers. + +endmenu + +config STM32_OTG_SOFOUTPUT + bool "OTG SOF output" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_OTG_USBREGEN + bool "Enable USB voltage regulator" + depends on STM32_HAVE_OTG_H7 + default n + +config STM32_USBHOST_REGDEBUG + bool "Register-Level Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Enable very low-level register access debug. + +config STM32_USBHOST_PKTDUMP + bool "Packet Dump Debug" + depends on STM32_COMMON_LEGACY && STM32_USBHOST && STM32_USBHOST && DEBUG_USB_INFO || STM32_COMMON_F7_H7 && USBHOST + ---help--- + Dump all incoming and outgoing USB packets. + +config STM32_USBFS_REGDEBUG + bool "Register-Level Debug" + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32H5) && STM32_USBFS && STM32_USBFS && DEBUG_USB_INFO + ---help--- + Enable very low-level register access debug. + +config OTG_ID_GPIO_DISABLE + bool "Disable the use of GPIO_OTG_ID pin." + depends on (STM32_COMMON_LEGACY || ARCH_CHIP_STM32F7) && STM32_OTGFS || ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + ---help--- + Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use + cases to reuse this GPIO pin and ensure it is not set incorrectlty + during OS boot. + +menu "STM32_OTG_HS Configuration" + depends on ARCH_CHIP_STM32F7 && STM32_OTGFSHS + +choice + prompt "ULPI Selection" + default STM32_NO_ULPI + +config STM32_NO_ULPI + bool "No External ULPI" + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_EXTERNAL_ULPI + bool "External ULPI" + depends on STM32_HAVE_EXTERNAL_ULPI + ---help--- + Select to enable the presence of an external ULPI PHY + +config STM32_INTERNAL_ULPI + bool "Internal ULPI PHY" + depends on STM32_HAVE_INTERNAL_ULPI + ---help--- + Select to enable the internal ULPI for USB HS + +endchoice # "ULPI Selection" + +endmenu # STM32_OTG_HS Configuration + +menu "OTG_HS Configuration" + depends on ARCH_CHIP_STM32H7 && STM32_OTGHS + +config STM32_OTGHS_FS + bool "OTGHS in FS mode" + default n + +choice + prompt "ULPI Selection" + default STM32_OTGHS_NO_ULPI + +config STM32_OTGHS_NO_ULPI + bool "No External ULPI on board." + ---help--- + Select to indicate that there is no external ULPI PHY. This means + the OTG_HS peripheral must use the internal full-speed PHY and will + be limited to full-speed mode. + +config STM32_OTGHS_EXTERNAL_ULPI + bool "External ULPI" + ---help--- + Select to indicate the presence of an external ULPI PHY and use it. + +endchoice # "ULPI Selection" + +endmenu # OTG_HS Configuration + +menu "OTG Configuration" + depends on ARCH_CHIP_STM32H7 && (STM32_OTGFS || STM32_OTGHS) + +choice + prompt "STM32H7 OTGFS role" + depends on STM32_OTGFS + default STM32_OTGFS_USBDEV if USBDEV + default STM32_OTGFS_HOST if !USBDEV && USBHOST + +config STM32_OTGFS_USBDEV + bool "OTGFS as USBDEV" + depends on USBDEV + +config STM32_OTGFS_HOST + bool "OTGFS as HOST" + depends on USBHOST + +endchoice # "STM32H7 OTGFS role" + +choice + prompt "STM32H7 OTGHS role (only USBDEV supported for now)" + depends on STM32_OTGHS + default STM32_OTGHS_USBDEV if USBDEV + +config STM32_OTGHS_USBDEV + bool "OTGHS as USBDEV" + depends on USBDEV + +endchoice # "STM32H7 OTGHS role" + +endmenu # OTG Configuration + +menu "USB FS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGFS && STM32_USBHOST + +config STM32_OTGFS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGFS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGFS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGFS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGFS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG FS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB FS Host Configuration + +menu "USB HS Host Configuration" + depends on STM32_COMMON_LEGACY && STM32_OTGHS && STM32_USBHOST + +config STM32_OTGHS_RXFIFO_SIZE + int "Rx Packet Size" + default 128 + ---help--- + Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) + +config STM32_OTGHS_NPTXFIFO_SIZE + int "Non-periodic Tx FIFO Size" + default 96 + ---help--- + Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_PTXFIFO_SIZE + int "Periodic Tx FIFO size" + default 128 + ---help--- + Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) + +config STM32_OTGHS_DESCSIZE + int "Descriptor Size" + default 128 + ---help--- + Maximum size to allocate for descriptor memory descriptor. Default: 128 + +config STM32_OTGHS_SOFINTR + bool "Enable SOF interrupts" + default n + ---help--- + Enable SOF interrupts. Why would you ever want to do that? + +config STM32_OTGHS_VBUS_CONTROL + bool "Enable VBus Control" + default y + ---help--- + Enable VBus control. Used when the board has VBus sensing and + a power switch for the OTG HS USB port. Disable this config + if the board lacks this USB VBus control circuitry. + +endmenu # USB HS Host Configuration + +config STM32_USBDEV_REGDEBUG + bool "OTG USBDEV REGDEBUG" + depends on STM32_COMMON_F7_H7 && USBDEV + +comment "USB Device Configuration" + +config STM32_USB_ITRMP + bool "Re-map USB interrupt" + default STM32_CAN1 + depends on STM32_USB && STM32_STM32F30XX + ---help--- + The legacy USB in the F1 series shared interrupt lines with USB + device and CAN1. In the F3 series, a hardware options was added to + either retain the legacy F1 behavior or to map the USB interrupts to + their own dedicated vectors. The option is available only for the + F3 family and selects the use of the dedicated USB interrupts. diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt index a725dcc6f90..6c370d70d10 100644 --- a/arch/arm/src/stm32/CMakeLists.txt +++ b/arch/arm/src/stm32/CMakeLists.txt @@ -75,7 +75,7 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() -if(CONFIG_STM32_HAVE_IP_I2C_V1) +if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) if(CONFIG_STM32_I2C_ALT) list(APPEND SRCS stm32_i2c_alt.c) elseif(CONFIG_STM32_STM32F4XXX) @@ -83,7 +83,7 @@ if(CONFIG_STM32_HAVE_IP_I2C_V1) else() list(APPEND SRCS stm32_i2c.c) endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_V2) +elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) list(APPEND SRCS stm32_i2c_v2.c) if(CONFIG_STM32_I2C_SLAVE) list(APPEND SRCS stm32_i2cslave_v2.c) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index b8bcda25eee..82d831fa087 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -1234,8 +1234,54 @@ config STM32_FLASH_CONFIG_Z bool config STM32_STM32L15XX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_ENERGYLITE select STM32_HAVE_USBDEV @@ -1252,28 +1298,71 @@ config STM32_STM32L15XX select STM32_HAVE_ADC2 select STM32_HAVE_USART3 select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F10XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKP + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY select STM32_HAVE_RTC_COUNTER select STM32_HAVE_TIM2 select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_V1 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_CONNECTIVITYLINE bool @@ -1371,8 +1460,58 @@ config STM32_LOWDENSITY select STM32_HAVE_CAN1 if !STM32_VALUELINE config STM32_STM32F20XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_DCMI + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM3 select STM32_HAVE_FLASH_ICACHE select STM32_HAVE_FLASH_DCACHE @@ -1408,12 +1547,12 @@ config STM32_STM32F20XX select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F205 bool @@ -1426,11 +1565,54 @@ config STM32_STM32F207 select STM32_HAVE_ETHMAC config STM32_STM32F30XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM4 select ARCH_HAVE_FPU - select STM32_HAVE_ADC1_DMA select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_TIM1 @@ -1441,18 +1623,17 @@ config STM32_STM32F30XX select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F302 bool default n select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA select STM32_HAVE_I2C2 select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 @@ -1463,17 +1644,60 @@ config STM32_STM32F303 bool default n select STM32_HAVE_ADC2 - select STM32_HAVE_ADC2_DMA select STM32_HAVE_CCM select STM32_HAVE_TIM7 config STM32_STM32F33XX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_HRTIM1 - select STM32_HAVE_HRTIM1_PLLCLK select STM32_HAVE_COMP2 select STM32_HAVE_COMP4 select STM32_HAVE_COMP6 @@ -1488,23 +1712,65 @@ config STM32_STM32F33XX select STM32_HAVE_TIM17 select STM32_HAVE_TSC select STM32_HAVE_ADC2 - select STM32_HAVE_ADC1_DMA - select STM32_HAVE_ADC2_DMA select STM32_HAVE_CAN1 select STM32_HAVE_DAC1 select STM32_HAVE_DAC2 select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V2 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F37XX + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_IP_SDADC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n + select STM32_HAVE_PWR select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_USBDEV @@ -1528,16 +1794,68 @@ config STM32_STM32F37XX select STM32_HAVE_SPI2 select STM32_HAVE_SPI3 select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1_BASIC - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 + select STM32_HAVE_IP_I2C_M3M4_V2 config STM32_STM32F4XXX + select STM32_HAVE_OTGHS + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_DCMI + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_F4 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 + select STM32_HAVE_PWR select ARCH_HAVE_FPU select STM32_HAVE_FLASH_ICACHE select STM32_HAVE_FLASH_DCACHE @@ -1545,12 +1863,12 @@ config STM32_STM32F4XXX select STM32_HAVE_SPI2 select STM32_HAVE_I2C2 select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_V2 - select STM32_HAVE_IP_TIMERS_V1 - select STM32_HAVE_IP_ADC_V1 - select STM32_HAVE_IP_DAC_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 config STM32_STM32F401xBC bool @@ -1760,6 +2078,8 @@ config STM32_STM32F427 # This is really 429/439, but we treat the two the same. config STM32_STM32F429 + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 bool default n select STM32_HAVE_OVERDRIVE @@ -1841,6 +2161,8 @@ config STM32_STM32F446 # This is really 469/479, but we treat the two the same. config STM32_STM32F469 + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 bool default n select STM32_HAVE_OVERDRIVE @@ -1884,18 +2206,68 @@ config STM32_STM32F469 select STM32_HAVE_I2C3 config STM32_STM32G4XXX + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_G4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_TIM2_32BITS + select STM32_HAVE_TIM5_32BITS + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 bool default n select ARCH_CORTEXM4 select ARCH_HAVE_FPU select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_V3 - select STM32_HAVE_IP_ADC_V2 - select STM32_HAVE_IP_COMP_V2 - select STM32_HAVE_IP_DAC_V2 + select STM32_HAVE_IP_DBGMCU_M3M4_V3 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V2 + select STM32_HAVE_IP_DAC_M3M4_V2 select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_V2 - select STM32_HAVE_IP_TIMERS_V3 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_TIMERS_M3M4_V3 config STM32_STM32G4_CAT2 bool @@ -2025,8 +2397,8 @@ config STM32_STM32G47XX select STM32_HAVE_DAC2 select STM32_HAVE_DAC3 select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1_CHAN8 - select STM32_HAVE_DMA2_CHAN678 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 select STM32_HAVE_FSMC select STM32_HAVE_FMAC select STM32_HAVE_FDCAN1 @@ -2100,269 +2472,27 @@ config STM32_STM32G474V select STM32_HAVE_UART4 select STM32_HAVE_UART5 -menu "STM32 Peripheral Support" +# --- restored family-specific symbols over-deleted by move-to-common (split recreates per-family) --- +if ARCH_CHIP_STM32 -# These are the peripheral selections proper - -config STM32_ADC5 - bool "ADC5" - default n - select STM32_ADC - depends on STM32_HAVE_ADC5 - select STM32_HAVE_ADC5_DMA if STM32_DMA2 - select STM32_HAVE_ADC5_DMA if STM32_DMAMUX - -config STM32_SDADC1 - bool "SDADC1" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC1_DMA if STM32_DMA2 - -config STM32_SDADC2 - bool "SDADC2" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC2_DMA if STM32_DMA2 - -config STM32_SDADC3 - bool "SDADC3" - default n - select STM32_SDADC - depends on STM32_HAVE_SDADC3 - select STM32_HAVE_SDADC3_DMA if STM32_DMA2 - -config STM32_COMP3 - bool "COMP3" - default n - select STM32_COMP - depends on STM32_HAVE_COMP3 - -config STM32_COMP4 - bool "COMP4" - default n - select STM32_COMP - depends on STM32_HAVE_COMP4 - -config STM32_COMP5 - bool "COMP5" - default n - select STM32_COMP - depends on STM32_HAVE_COMP5 - -config STM32_COMP6 - bool "COMP6" - default n - select STM32_COMP - depends on STM32_HAVE_COMP6 - -config STM32_COMP7 - bool "COMP7" - default n - select STM32_COMP - depends on STM32_HAVE_COMP7 - -config STM32_CCMDATARAM - bool "CMD/DATA RAM" - default n - depends on STM32_STM32F4XXX - -if STM32_DAC1 - -config STM32_DAC1CH1 - bool "DAC1CH1" - default n - -config STM32_DAC1CH2 - bool "DAC1CH2" - default n - -endif #STM32_DAC1 - -if STM32_DAC2 - -config STM32_DAC2CH1 - bool "DAC2CH1" - default n - -endif #STM32_DAC2 - -config STM32_DAC3 - bool "DAC3" - default n - depends on STM32_HAVE_DAC3 - select STM32_DAC - -if STM32_DAC3 - -config STM32_DAC3CH1 - bool "DAC3CH1 Internal" - default n - -config STM32_DAC3CH2 - bool "DAC3CH2 Internal" - default n - -endif #STM32_DAC3 - -config STM32_DAC4 - bool "DAC4" - default n - depends on STM32_HAVE_DAC4 - select STM32_DAC - -if STM32_DAC4 - -config STM32_DAC4CH1 - bool "DAC4CH1 Internal" - default n - -config STM32_DAC4CH2 - bool "DAC4CH2 Internal" - default n - -endif #STM32_DAC4 - -config STM32_HRTIM +config STM32_VALUELINE bool default n - -config STM32_HRTIM1 - bool "HRTIM1" - default n - depends on STM32_HAVE_HRTIM1 - select STM32_HRTIM - -if STM32_HRTIM1 - -config STM32_HRTIM_MASTER - bool "HRTIM MASTER" - default n - ---help--- - Enable HRTIM Master Timer - -config STM32_HRTIM_TIMA - bool "HRTIM TIMA" - default n - ---help--- - Enable HRTIM Timer A - -config STM32_HRTIM_TIMB - bool "HRTIM TIMB" - default n - ---help--- - Enable HRTIM Timer B - -config STM32_HRTIM_TIMC - bool "HRTIM TIMC" - default n - ---help--- - Enable HRTIM Timer C - -config STM32_HRTIM_TIMD - bool "HRTIM TIMD" - default n - ---help--- - Enable HRTIM Timer D - -config STM32_HRTIM_TIME - bool "HRTIM TIME" - default n - ---help--- - Enable HRTIM Timer E - -endif # STM32_HRTIM - -config STM32_I2C1_SLAVE - bool "I2C1 Slave" - default n - depends on !STM32_I2C1 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C2_SLAVE - bool "I2C2 Slave" - default n - depends on STM32_HAVE_I2C2 && !STM32_I2C2 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_I2C3_SLAVE - bool "I2C3 Slave" - default n - depends on STM32_HAVE_I2C3 && !STM32_I2C3 && I2C_SLAVE - select STM32_I2C_SLAVE - -config STM32_OPAMP1 - bool "OPAMP1" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP1 - -config STM32_OPAMP2 - bool "OPAMP2" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP2 - -config STM32_OPAMP3 - bool "OPAMP3" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP3 - -config STM32_OPAMP4 - bool "OPAMP4" - default n - select STM32_OPAMP - depends on STM32_HAVE_OPAMP4 - -config STM32_UCPD - bool "UCPD (USB Type C Power Delivery)" - default n - depends on STM32_HAVE_UCPD - select USBDEV - -if STM32_LCD - -choice - prompt "Segment LCD Clock Source" - default LCD_LSECLOCK - -config LCD_LSICLOCK - bool "Internal Low Speed Clock" - -config LCD_LSECLOCK - bool "External Low Speed Clock" - -config LCD_HSECLOCK - bool "External High Speed Clock" - -endchoice -endif # STM32_LCD - -endmenu - -config STM32_SDADC - bool - default n - -config STM32_I2C_SLAVE - bool - default n - -config STM32_CAP - bool - default n - -config STM32_NOEXT_VECTORS - bool "Disable the ARMv7-M EXT vectors" - default n - ---help--- - Sometimes you may not need any Vector support beyond SysTick - and wish to save memory. This applies only to ARMv7-M architectures. - -menu "Alternate Pin Mapping" - depends on STM32_STM32F10XX || STM32_CONNECTIVITYLINE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_SPI2 if STM32_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32_HIGHDENSITY choice prompt "CAN1 Alternate Pin Mappings" @@ -2542,1887 +2672,4 @@ config STM32_USART3_PARTIAL_REMAP endchoice -endmenu - -config STM32_FLASH_ICACHE - bool "Enable FLASH Instruction Cache" - default y - depends on STM32_HAVE_FLASH_ICACHE - ---help--- - Enable the FLASH instruction cache. - -config STM32_FLASH_DCACHE - bool "Enable FLASH Data Cache" - default y - depends on STM32_HAVE_FLASH_DCACHE - ---help--- - Enable the FLASH data cache. - -config STM32_FORCEPOWER - bool "Force power" - default n - ---help--- - Timer and I2C devices may need to the following to force power to be applied - unconditionally at power up. (Otherwise, the device is powered when it is - initialized). - -config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32_SAIPLL - bool "SAIPLL" - default n - depends on STM32_HAVE_SAIPLL - ---help--- - The STM32F446 has a separate PLL for the SAI block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_I2SPLL - bool "I2SPLL" - default n - depends on STM32_HAVE_I2SPLL - ---help--- - The STM32F446 has a separate PLL for the I2S block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32_CCMEXCLUDE - bool "Exclude CCM SRAM from the heap" - default ARCH_DMA || LIBC_ARCH_ELF - depends on STM32_HAVE_CCM - ---help--- - Exclude CCM SRAM from the HEAP because (1) it cannot be used for DMA - and (2) it appears to be impossible to execute ELF modules from CCM - RAM. - -config STM32_CCM_PROCFS - bool "CCM PROCFS support" - default n - depends on !DISABLE_MOUNTPOINT && FS_PROCFS && FS_PROCFS_REGISTER - ---help--- - Select to build in support for /proc/ccm. Reading from /proc/ccm - will provide statistics about CCM memory use similar to what you - would get from mallinfo() for the user heap. - -menu "Timer Configuration" - depends on STM32_TIM - -if STM32_TIM9_CAP - -config STM32_TIM9_CLOCK - int "TIM9 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM9_CAP - -if STM32_TIM10_CAP - -config STM32_TIM10_CLOCK - int "TIM10 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM10_CAP - -if STM32_TIM11_CAP - -config STM32_TIM11_CLOCK - int "TIM11 work frequency for capture" - default 1000000 - ---help--- - This clock frequency limiting the count rate at the expense of resolution. - -endif # STM32_TIM11_CAP - -endmenu # Timer Configuration - -menu "HRTIM Configuration" - depends on STM32_HRTIM - -config STM32_HRTIM_DISABLE_CHARDRV - bool "HRTIM Disable Character Driver" - default n - ---help--- - In most cases we do not need HRTIM Character Driver, so we can disable it - and save some memory. - -config STM32_HRTIM_NO_ENABLE_TIMERS - bool "Do not enable HRTIM timers at startup" - default n - ---help--- - Do not enable HRTIM timers at startup - -menuconfig STM32_HRTIM_ADC - bool "HRTIM ADC Triggering" - default n - ---help--- - Enable HRTIM ADC Triggering support. - -if STM32_HRTIM_ADC - -config STM32_HRTIM_ADC1_TRG1 - bool "HRTIM ADC1 Trigger 1" - default n - -config STM32_HRTIM_ADC1_TRG2 - bool "HRTIM ADC1 Trigger 2" - default n - -config STM32_HRTIM_ADC1_TRG3 - bool "HRTIM ADC1 Trigger 3" - default n - -config STM32_HRTIM_ADC1_TRG4 - bool "HRTIM ADC1 Trigger 4" - default n - -config STM32_HRTIM_ADC2_TRG1 - bool "HRTIM ADC2 Trigger 1" - default n - -config STM32_HRTIM_ADC2_TRG2 - bool "HRTIM ADC2 Trigger 2" - default n - -config STM32_HRTIM_ADC2_TRG3 - bool "HRTIM ADC2 Trigger 3" - default n - -config STM32_HRTIM_ADC2_TRG4 - bool "HRTIM ADC2 Trigger 4" - default n - -endif # STM32_HRTIM_ADC - -config STM32_HRTIM_DAC - bool "HRTIM DAC Triggering" - default n - ---help--- - Enable HRTIM DAC Triggering support. - -config STM32_HRTIM_PWM - bool "HRTIM PWM Outputs" - default n - ---help--- - Enable HRTIM PWM Outputs support. - -config STM32_HRTIM_CAP - bool "HRTIM Capture" - default n - ---help--- - Enable HRTIM Capture support. - -config STM32_HRTIM_INTERRUPTS - bool "HRTIM Interrupts" - default n - ---help--- - Enable HRTIM Interrupts support. - -config STM32_HRTIM_BURST - bool "HRTIM Burst Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Burst Mode support for PWM outputs. - -config STM32_HRTIM_DEADTIME - bool "HRTIM Dead-time" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Deadtime support for PWM outputs. - -config STM32_HRTIM_PUSHPULL - bool "HRTIM Push-Pull Mode" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Push-Pull Mode support for PWM outputs. - -config STM32_HRTIM_CHOPPER - bool "HRTIM Chopper" - depends on STM32_HRTIM_PWM - default n - ---help--- - Enable HRTIM Chopper Mode for PWM outputs. - -config STM32_HRTIM_DMA - bool "HRTIM DMA" - default n - -config STM32_HRTIM_DMABURST - bool "HRTIM DMA Burst" - default n - -config STM32_HRTIM_AUTODELAY - bool "HRTIM Autodelay" - depends on STM32_HRTIM_PWM - default n - -menuconfig STM32_HRTIM_EVENTS - bool "HRTIM Events Configuration" - default n - ---help--- - Enable HRTIM Events support. - -if STM32_HRTIM_EVENTS - -config STM32_HRTIM_EEV1 - bool "HRTIM EEV1" - default n - -config STM32_HRTIM_EEV2 - bool "HRTIM EEV2" - default n - -config STM32_HRTIM_EEV3 - bool "HRTIM EEV3" - default n - -config STM32_HRTIM_EEV4 - bool "HRTIM EEV4" - default n - -config STM32_HRTIM_EEV5 - bool "HRTIM EEV5" - default n - -config STM32_HRTIM_EEV6 - bool "HRTIM EEV6" - default n - -config STM32_HRTIM_EEV7 - bool "HRTIM EEV7" - default n - -config STM32_HRTIM_EEV8 - bool "HRTIM EEV8" - default n - -config STM32_HRTIM_EEV9 - bool "HRTIM EEV9" - default n - -config STM32_HRTIM_EEV10 - bool "HRTIM EEV10" - default n - -endif # STM32_HRTIM_EVENTS - -menuconfig STM32_HRTIM_FAULTS - bool "HRTIM Faults Configuration" - default n - ---help--- - Enable HRTIM Faults support. - -if STM32_HRTIM_FAULTS - -config STM32_HRTIM_FAULT1 - bool "HRTIM Fault 1" - default n - -config STM32_HRTIM_FAULT2 - bool "HRTIM Fault 2" - default n - -config STM32_HRTIM_FAULT3 - bool "HRTIM Fault 3" - default n - -config STM32_HRTIM_FAULT4 - bool "HRTIM Fault 4" - default n - -endif # STM32_HRTIM_FAULTS - -config STM32_HRTIM_CLK_FROM_PLL - bool "HRTIM Clock from PLL" - default n - depends on STM32_HAVE_HRTIM1_PLLCLK - ---help--- - Set PLL as the clock source for HRTIM. - This configuration requires the following conditions: - 1) system clock is PLL, - 2) SYSCLK and PCLK2 ratio must be 1 o 2. - -menu "HRTIM Master Configuration" - depends on STM32_HRTIM_MASTER - -config STM32_HRTIM_MASTER_DAC - bool "HRTIM Master DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_MASTER_DMA - bool "HRTIM MASTER DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_MASTER_IRQ - bool "HRTIM MASTER Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -endmenu # "HRTIM Master Configuration" - -menu "HRTIM Timer A Configuration" - depends on STM32_HRTIM_TIMA - -config STM32_HRTIM_TIMA_CAP - bool "HRTIM TIMA Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMA_DAC - bool "HRTIM TIMA DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMA_DMA - bool "HRTIM TIMA DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMA_IRQ - bool "HRTIM TIMA Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMA_PWM - bool "HRTIM TIMA PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMA_PWM_CH1 - bool "HRTIM TIMA PWM Output 1" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_PWM_CH2 - bool "HRTIM TIMA PWM Output 2" - default n - depends on STM32_HRTIM_TIMA_PWM - -config STM32_HRTIM_TIMA_BURST - bool "HRTIM TIMA Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_BURST_CH1 - bool "HRTIM TIMA Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH1) - -config STM32_HRTIM_TIMA_BURST_CH2 - bool "HRTIM TIMA Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMA_BURST && STM32_HRTIM_TIMA_PWM_CH2) - -config STM32_HRTIM_TIMA_CHOP - bool "HRTIM TIMA PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_DT - bool "HRTIM TIMA PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMA_PWM) - -config STM32_HRTIM_TIMA_PSHPLL - bool "HRTIM TIMA PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMA_PWM) - -endmenu # "HRTIM Timer A Configuration" - -menu "HRTIM Timer B Configuration" - depends on STM32_HRTIM_TIMB - -config STM32_HRTIM_TIMB_CAP - bool "HRTIM TIMB Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMB_DAC - bool "HRTIM TIMB DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMB_DMA - bool "HRTIM TIMB DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMB_IRQ - bool "HRTIM TIMB Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMB_PWM - bool "HRTIM TIMB PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMB_PWM_CH1 - bool "HRTIM TIMB PWM Output 1" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_PWM_CH2 - bool "HRTIM TIMB PWM Output 2" - default n - depends on STM32_HRTIM_TIMB_PWM - -config STM32_HRTIM_TIMB_BURST - bool "HRTIM TIMB Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_BURST_CH1 - bool "HRTIM TIMB Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH1) - -config STM32_HRTIM_TIMB_BURST_CH2 - bool "HRTIM TIMB Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMB_BURST && STM32_HRTIM_TIMB_PWM_CH2) - -config STM32_HRTIM_TIMB_CHOP - bool "HRTIM TIMB PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_DT - bool "HRTIM TIMB PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMB_PWM) - -config STM32_HRTIM_TIMB_PSHPLL - bool "HRTIM TIMB PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMB_PWM) - -endmenu # "HRTIM Timer B Configuration" - -menu "HRTIM Timer C Configuration" - depends on STM32_HRTIM_TIMC - -config STM32_HRTIM_TIMC_CAP - bool "HRTIM TIMC Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMC_DAC - bool "HRTIM TIMC DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMC_DMA - bool "HRTIM TIMC DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMC_IRQ - bool "HRTIM TIMC Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMC_PWM - bool "HRTIM TIMC PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMC_PWM_CH1 - bool "HRTIM TIMC PWM Output 1" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_PWM_CH2 - bool "HRTIM TIMC PWM Output 2" - default n - depends on STM32_HRTIM_TIMC_PWM - -config STM32_HRTIM_TIMC_BURST - bool "HRTIM TIMC Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_BURST_CH1 - bool "HRTIM TIMC Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH1) - -config STM32_HRTIM_TIMC_BURST_CH2 - bool "HRTIM TIMC Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMC_BURST && STM32_HRTIM_TIMC_PWM_CH2) - -config STM32_HRTIM_TIMC_CHOP - bool "HRTIM TIMC PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_DT - bool "HRTIM TIMC PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMC_PWM) - -config STM32_HRTIM_TIMC_PSHPLL - bool "HRTIM TIMC PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMC_PWM) - -endmenu # "HRTIM Timer C Configuration" - -menu "HRTIM Timer D Configuration" - depends on STM32_HRTIM_TIMD - -config STM32_HRTIM_TIMD_CAP - bool "HRTIM TIMD Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIMD_DAC - bool "HRTIM TIMD DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIMD_DMA - bool "HRTIM TIMD DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIMD_IRQ - bool "HRTIM TIMD Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIMD_PWM - bool "HRTIM TIMD PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIMD_PWM_CH1 - bool "HRTIM TIMD PWM Output 1" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_PWM_CH2 - bool "HRTIM TIMD PWM Output 2" - default n - depends on STM32_HRTIM_TIMD_PWM - -config STM32_HRTIM_TIMD_BURST - bool "HRTIM TIMD Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_BURST_CH1 - bool "HRTIM TIMD Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH1) - -config STM32_HRTIM_TIMD_BURST_CH2 - bool "HRTIM TIMD Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIMD_BURST && STM32_HRTIM_TIMD_PWM_CH2) - -config STM32_HRTIM_TIMD_CHOP - bool "HRTIM TIMD PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_DT - bool "HRTIM TIMD PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIMD_PWM) - -config STM32_HRTIM_TIMD_PSHPLL - bool "HRTIM TIMD PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIMD_PWM) - -endmenu # "HRTIM Timer D Configuration" - -menu "HRTIM Timer E Configuration" - depends on STM32_HRTIM_TIME - -config STM32_HRTIM_TIME_CAP - bool "HRTIM TIME Capture" - default n - depends on STM32_HRTIM_CAPTURE - -config STM32_HRTIM_TIME_DAC - bool "HRTIM TIME DAC Triggering" - default n - depends on STM32_HRTIM_DAC - -config STM32_HRTIM_TIME_DMA - bool "HRTIM TIME DMA" - default n - depends on STM32_HRTIM_DMA - -config STM32_HRTIM_TIME_IRQ - bool "HRTIM TIME Interrupts" - default n - depends on STM32_HRTIM_INTERRUPTS - -config STM32_HRTIM_TIME_PWM - bool "HRTIM TIME PWM Outputs" - default n - depends on STM32_HRTIM_PWM - -config STM32_HRTIM_TIME_PWM_CH1 - bool "HRTIM TIME PWM Output 1" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_PWM_CH2 - bool "HRTIM TIME PWM Output 2" - default n - depends on STM32_HRTIM_TIME_PWM - -config STM32_HRTIM_TIME_BURST - bool "HRTIM TIME Burst" - default n - depends on (STM32_HRTIM_BURST && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_BURST_CH1 - bool "HRTIM TIME Output 1 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH1) - -config STM32_HRTIM_TIME_BURST_CH2 - bool "HRTIM TIME Output 2 Burst Mode" - default n - depends on (STM32_HRTIM_TIME_BURST && STM32_HRTIM_TIME_PWM_CH2) - -config STM32_HRTIM_TIME_CHOP - bool "HRTIM TIME PWM Chopper" - default n - depends on (STM32_HRTIM_CHOPPER && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_DT - bool "HRTIM TIME PWM Dead-time" - default n - depends on (STM32_HRTIM_DEADTIME && STM32_HRTIM_TIME_PWM) - -config STM32_HRTIM_TIME_PSHPLL - bool "HRTIM TIME PWM Push-pull mode" - default n - depends on (STM32_HRTIM_PUSHPULL && STM32_HRTIM_TIME_PWM) - -endmenu # "HRTIM Timer E Configuration" - -endmenu # "HRTIM Configuration" - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC4_RESOLUTION - int "ADC4 resolution" - depends on STM32_ADC4 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC4 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC5_RESOLUTION - int "ADC5 resolution" - depends on STM32_ADC5 && !STM32_HAVE_IP_ADC_V1_BASIC - default 0 - range 0 3 - ---help--- - ADC5 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32_ADC4_DMA - bool "ADC4 DMA" - depends on STM32_ADC4 && STM32_HAVE_ADC4_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC4_DMA_CFG - int "ADC4 DMA configuration" - depends on STM32_ADC4_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC4 DMA in One Shot Mode, 1 - ADC4 DMA in Circular Mode - -config STM32_ADC4_DMA_BATCH - int "ADC4 DMA number of conversions" - depends on STM32_ADC4 && STM32_ADC4_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_ANIOC_TRIGGER - int "ADC4 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32_ADC4 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32_ADC5_DMA - bool "ADC5 DMA" - depends on STM32_ADC5 && STM32_HAVE_ADC5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_ADC5_DMA_CFG - int "ADC5 DMA configuration" - depends on STM32_ADC5_DMA && !STM32_HAVE_IP_ADC_V1_BASIC - range 0 1 - default 0 - ---help--- - 0 - ADC5 DMA in One Shot Mode, 1 - ADC5 DMA in Circular Mode - -config STM32_ADC5_DMA_BATCH - int "ADC5 DMA number of conversions" - depends on STM32_ADC5 && STM32_ADC5_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32_ADC4_INJECTED_CHAN - int "ADC4 injected channels" - depends on STM32_ADC4 - range 0 4 - default 0 - ---help--- - Support for ADC4 injected channels. - -config STM32_ADC5_INJECTED_CHAN - int "ADC5 injected channels" - depends on STM32_ADC5 - range 0 4 - default 0 - ---help--- - Support for ADC5 injected channels. - -config STM32_ADC4_EXTSEL - bool "ADC4 external trigger for regular group" - depends on STM32_ADC4 && !STM32_HAVE_ADC4_TIMER - default n - ---help--- - Enable EXTSEL for ADC4. - -config STM32_ADC5_EXTSEL - bool "ADC5 external trigger for regular group" - depends on STM32_ADC5 && !STM32_HAVE_ADC5_TIMER - default n - ---help--- - Enable EXTSEL for ADC5. - -config STM32_ADC4_JEXTSEL - bool "ADC4 external trigger for injected group" - depends on STM32_ADC4 - default n - ---help--- - Enable JEXTSEL for ADC4. - -config STM32_ADC5_JEXTSEL - bool "ADC5 external trigger for injected group" - depends on STM32_ADC5 - default n - ---help--- - Enable JEXTSEL for ADC5. - -endmenu - -menu "COMP Configuration" - depends on STM32_COMP && STM32_HAVE_IP_COMP_V2 - -config STM32_COMP1_OUT - bool "COMP1 GPIO Output" - depends on STM32_COMP1 - default n - ---help--- - Enables COMP1 output. - -config STM32_COMP1_INM - int "COMP1 inverting input assignment" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects COMP1 inverting input pin. - -config STM32_COMP1_INP - int "COMP1 non-inverting input assignment" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 non-inverting input pin. - -config STM32_COMP1_POL - int "COMP1 polarity" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Selects COMP1 output polarity. - -config STM32_COMP1_HYST - int "COMP1 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP1. - -config STM32_COMP1_BLANKSEL - int "COMP1 blanking signal select" - depends on STM32_COMP1 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP1. - -config STM32_COMP1_LOCK - int "COMP1 COMP_CxCSR register lock" - depends on STM32_COMP1 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP2_OUT - bool "COMP2 GPIO Output" - depends on STM32_COMP2 - default n - ---help--- - Enables COMP2 output. - -config STM32_COMP2_INM - int "COMP2 inverting input assignment" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects COMP2 inverting input pin. - -config STM32_COMP2_INP - int "COMP2 non-inverting input assignment" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 non-inverting input pin. - -config STM32_COMP2_POL - int "COMP2 polarity" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Selects COMP2 output polarity. - -config STM32_COMP2_HYST - int "COMP2 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP2. - -config STM32_COMP2_BLANKSEL - int "COMP2 blanking signal select" - depends on STM32_COMP2 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP2. - -config STM32_COMP2_LOCK - int "COMP2 COMP_CxCSR register lock" - depends on STM32_COMP2 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP3_OUT - bool "COMP3 GPIO Output" - depends on STM32_COMP3 - default n - ---help--- - Enables COMP3 output. - -config STM32_COMP3_INM - int "COMP3 inverting input assignment" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects COMP3 inverting input pin. - -config STM32_COMP3_INP - int "COMP3 non-inverting input assignment" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 non-inverting input pin. - -config STM32_COMP3_POL - int "COMP3 polarity" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Selects COMP3 output polarity. - -config STM32_COMP3_HYST - int "COMP3 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP3. - -config STM32_COMP3_BLANKSEL - int "COMP3 blanking signal select" - depends on STM32_COMP3 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP3. - -config STM32_COMP3_LOCK - int "COMP3 COMP_CxCSR register lock" - depends on STM32_COMP3 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP4_OUT - bool "COMP4 GPIO Output" - depends on STM32_COMP4 - default n - ---help--- - Enables COMP4 output. - -config STM32_COMP4_INM - int "COMP4 inverting input assignment" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects COMP4 inverting input pin. - -config STM32_COMP4_INP - int "COMP4 non-inverting input assignment" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 non-inverting input pin. - -config STM32_COMP4_POL - int "COMP4 polarity" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Selects COMP4 output polarity. - -config STM32_COMP4_HYST - int "COMP4 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP4. - -config STM32_COMP4_BLANKSEL - int "COMP4 blanking signal select" - depends on STM32_COMP4 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP4. - -config STM32_COMP4_LOCK - int "COMP4 COMP_CxCSR register lock" - depends on STM32_COMP4 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP5_OUT - bool "COMP5 GPIO Output" - depends on STM32_COMP5 - default n - ---help--- - Enables COMP5 output. - -config STM32_COMP5_INM - int "COMP5 inverting input assignment" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects COMP5 inverting input pin. - -config STM32_COMP5_INP - int "COMP5 non-inverting input assignment" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 non-inverting input pin. - -config STM32_COMP5_POL - int "COMP5 polarity" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Selects COMP5 output polarity. - -config STM32_COMP5_HYST - int "COMP5 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP5. - -config STM32_COMP5_BLANKSEL - int "COMP5 blanking signal select" - depends on STM32_COMP5 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP5. - -config STM32_COMP5_LOCK - int "COMP5 COMP_CxCSR register lock" - depends on STM32_COMP5 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP6_OUT - bool "COMP6 GPIO Output" - depends on STM32_COMP6 - default n - ---help--- - Enables COMP6 output. - -config STM32_COMP6_INM - int "COMP6 inverting input assignment" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects COMP6 inverting input pin. - -config STM32_COMP6_INP - int "COMP6 non-inverting input assignment" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 non-inverting input pin. - -config STM32_COMP6_POL - int "COMP6 polarity" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Selects COMP6 output polarity. - -config STM32_COMP6_HYST - int "COMP6 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP6. - -config STM32_COMP6_BLANKSEL - int "COMP6 blanking signal select" - depends on STM32_COMP6 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP6. - -config STM32_COMP6_LOCK - int "COMP6 COMP_CxCSR register lock" - depends on STM32_COMP6 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -config STM32_COMP7_OUT - bool "COMP7 GPIO Output" - depends on STM32_COMP7 - default n - ---help--- - Enables COMP7 output. - -config STM32_COMP7_INM - int "COMP7 inverting input assignment" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects COMP7 inverting input pin. - -config STM32_COMP7_INP - int "COMP7 non-inverting input assignment" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 non-inverting input pin. - -config STM32_COMP7_POL - int "COMP7 polarity" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Selects COMP7 output polarity. - -config STM32_COMP7_HYST - int "COMP7 hysteresis" - depends on STM32_STM32G4XXX && STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the hysteresis of the COMP7. - -config STM32_COMP7_BLANKSEL - int "COMP7 blanking signal select" - depends on STM32_COMP7 - range 0 7 - default 0 - ---help--- - Selects the blanking signal for comparator COMP7. - -config STM32_COMP7_LOCK - int "COMP7 COMP_CxCSR register lock" - depends on STM32_COMP7 - range 0 1 - default 0 - ---help--- - Locks COMP_CxCSR register. - 0 - Unlock 1 - Lock - -endmenu - -menu "SDADC Configuration" - depends on STM32_SDADC - -config STM32_SDADC1_DMA - bool "SDADC1 DMA" - depends on STM32_SDADC1 && STM32_HAVE_SDADC1_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC2_DMA - bool "SDADC2 DMA" - depends on STM32_SDADC2 && STM32_HAVE_SDADC2_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -config STM32_SDADC3_DMA - bool "SDADC3 DMA" - depends on STM32_SDADC3 && STM32_HAVE_SDADC3_DMA - default n - ---help--- - If DMA is selected, then the SDADC may be configured to support - DMA transfer, which is advisable if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -menu "DAC Configuration" - depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4 - -config STM32_DAC1CH1_MODE - int "DAC1CH1 channel mode" - depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH1_DMA - bool "DAC1CH1 DMA" - depends on STM32_DAC1CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH1_DMA - -config STM32_DAC1CH1_DMA_BUFFER_SIZE - int "DAC1CH1 DMA buffer size" - default 256 - -config STM32_DAC1CH1_DMA_EXTERNAL - bool "DAC1CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH1_HRTIM_TRG1 - bool "DAC1CH1 HRTIM Trigger 1" - default n - -config STM32_DAC1CH1_HRTIM_TRG2 - bool "DAC1CH1 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH1_TIMER - int "DAC1CH1 timer" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH1_TIMER_FREQUENCY - int "DAC1CH1 timer frequency" - depends on !STM32_DAC1CH1_DMA_EXTERNAL - default 0 - endif - -config STM32_DAC1CH2_MODE - int "DAC1CH2 channel mode" - depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC1CH2_DMA - bool "DAC1CH2 DMA" - depends on STM32_DAC1CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC1CH2_DMA - -config STM32_DAC1CH2_DMA_BUFFER_SIZE - int "DAC1CH2 DMA buffer size" - default 256 - -config STM32_DAC1CH2_DMA_EXTERNAL - bool "DAC1CH2 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC1CH2_HRTIM_TRG1 - bool "DAC1CH2 HRTIM Trigger 1" - default n - -config STM32_DAC1CH2_HRTIM_TRG2 - bool "DAC1CH2 HRTIM Trigger 2" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC1CH2_TIMER - int "DAC1CH2 timer" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - range 2 8 - -config STM32_DAC1CH2_TIMER_FREQUENCY - int "DAC1CH2 timer frequency" - depends on !STM32_DAC1CH2_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC2CH1_MODE - int "DAC2CH1 channel mode" - depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC2CH1_DMA - bool "DAC2CH1 DMA" - depends on STM32_DAC2CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by and EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC2CH1_DMA - -config STM32_DAC2CH1_DMA_BUFFER_SIZE - int "DAC2CH1 DMA buffer size" - default 256 - -config STM32_DAC2CH1_DMA_EXTERNAL - bool "DAC2CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC2CH1_HRTIM_TRG3 - bool "DAC2CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC2CH1_TIMER - int "DAC2CH1 timer" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC2CH1_TIMER_FREQUENCY - int "DAC2CH1 timer frequency" - depends on !STM32_DAC2CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH1_MODE - int "DAC3CH1 channel mode" - depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH1_DMA - bool "DAC3CH1 DMA" - depends on STM32_DAC3CH1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH1_DMA - -config STM32_DAC3CH1_DMA_BUFFER_SIZE - int "DAC3CH1 DMA buffer size" - default 256 - -config STM32_DAC3CH1_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH1_HRTIM_TRG3 - bool "DAC3CH1 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH1_TIMER - int "DAC3CH1 timer" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH1_TIMER_FREQUENCY - int "DAC3CH1 timer frequency" - depends on !STM32_DAC3CH1_DMA_EXTERNAL - default 0 - -endif - -config STM32_DAC3CH2_MODE - int "DAC3CH2 channel mode" - depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2 - default 0 - range 0 7 - ---help--- - – DAC channel in Normal mode - 0: DAC channel is connected to external pin with Buffer enabled - 1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled - 2: DAC channel2 is connected to external pin with buffer disabled - 3: DAC channel is connected to on chip peripherals with Buffer disabled - - DAC channel in Sample and hold mode - 4: DAC channel is connected to external pin with Buffer enabled - 5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled - 6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled - 7: DAC channel is connected to on chip peripherals with Buffer disabled - -config STM32_DAC3CH2_DMA - bool "DAC3CH2 DMA" - depends on STM32_DAC3CH2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32_DAC3CH2_DMA - -config STM32_DAC3CH2_DMA_BUFFER_SIZE - int "DAC3CH2 DMA buffer size" - default 256 - -config STM32_DAC3CH2_DMA_EXTERNAL - bool "DAC3CH1 DMA External Trigger" - default n - -if STM32_HRTIM_DAC - -config STM32_DAC3CH2_HRTIM_TRG3 - bool "DAC3CH2 HRTIM Trigger 3" - default n - -endif # STM32_HRTIM_DAC - -config STM32_DAC3CH2_TIMER - int "DAC3CH2 timer" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - range 2 8 - -config STM32_DAC3CH2_TIMER_FREQUENCY - int "DAC3CH2 timer frequency" - depends on !STM32_DAC3CH2_DMA_EXTERNAL - default 0 - -endif - -endmenu - -config STM32_HCIUART_RXDMA - bool - default n - -menu "U[S]ART Configuration" - depends on STM32_USART - -comment "U[S]ART Device Configuration" - -if STM32_USART1_HCIUART - -config STM32_HCIUART1_RXBUFSIZE - int "HCI UART1 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART1_TXBUFSIZE - int "HCI UART1 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART1_BAUD - int "HCI UART1 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART1_RXDMA - bool "HCI UART1 Rx DMA" - default n - depends on (((STM32_STM32F10XX || STM32_STM32L15XX) && STM32_DMA1) || (!STM32_STM32F10XX && STM32_DMA2)) - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART1_HCIUART - -if STM32_USART2_HCIUART - -config STM32_HCIUART2_RXBUFSIZE - int "HCI UART2 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART2_TXBUFSIZE - int "HCI UART2 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART2_BAUD - int "HCI UART2 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART2_RXDMA - bool "HCI UART2 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART2_HCIUART - -if STM32_USART3_HCIUART - -config STM32_HCIUART3_RXBUFSIZE - int "HCI UART3 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART3_TXBUFSIZE - int "HCI UART3 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART3_BAUD - int "HCI UART3 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART3_RXDMA - bool "HCI UART3 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART3_HCIUART - -if STM32_USART6_HCIUART - -config STM32_HCIUART6_RXBUFSIZE - int "HCI UART6 Rx buffer size" - default 80 - ---help--- - Characters are buffered as they are received. This specifies - the size of the receive buffer. Ideally this should be at least - the size of the largest frame that can be received - -config STM32_HCIUART6_TXBUFSIZE - int "HCI UART6 Transmit buffer size" - default 80 - ---help--- - Characters are buffered before being sent. This specifies - the size of the transmit buffer. Ideally this should be at least - the size of the largest frame that can be sent - -config STM32_HCIUART6_BAUD - int "HCI UART6 initial BAUD rate" - default 115200 - ---help--- - The configured initial BAUD of the HCIR USART used during bringup. - In most cases this initial rate can be increased by the upper half - HCI UART driver using vendor-specifi HCI UART commands. - -config STM32_HCIUART6_RXDMA - bool "HCI UART6 Rx DMA" - default n - depends on STM32_DMA1 - select STM32_HCIUART_RXDMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # STM32_USART6_HCIUART - -if STM32_LPUART1_SERIALDRIVER - -config LPUART1_TXDMA - bool "LPUART1 Tx DMA" - default n - depends on STM32_DMA1 - ---help--- - In high data rate usage, Tx DMA may reduce CPU load - -endif # STM32_LPUART1_SERIALDRIVER - -menu "HCI UART Driver Configuration" - depends on STM32_SERIALDRIVER - -config STM32_HCIUART_RXDMA_BUFSIZE - int "Rx DMA buffer size" - default 32 - range 32 4096 - depends on STM32_HCIUART_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half or this number of bytes. - - Value given here will be rounded up to next multiple of 4 bytes. - -config STM32_HCIUART_RXDMAPRIO - hex "HCI UART DMA priority" - default 0x00001000 if STM32_STM32F10XX - default 0x00010000 if !STM32_STM32F10XX - depends on STM32_HCIUART_RXDMA - ---help--- - Select HCI UART DMA priority. - - For STM32 F1 family, options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - - For other STM32's, options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config STM32_HCIUART_SW_RXFLOW - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable UART RTS flow control using Software. Current STM32 have - broken HW based RTS behavior (they assert nRTS after every byte - received) Enable this setting workaround this issue by using - software based management of RTS - - If HCI UART DMA is enabled, this is probably the better selection - as well. In that case, the Rx DMA buffer will avoid Rx overrun due - to short, bursty activity. Software RTS management will probably - result in overall better throughput and should still avoid Rx data - overrun conditions. - -config STM32_HCIUART_UPPER_WATERMARK - int "RTS flow control upper watermark (%)" - default 75 - range 2 100 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be asserted - when this amount of Rx data has been buffered. The amount is - expressed as a percentage of the Rx buffer size. - -config STM32_HCIUART_LOWER_WATERMARK - int "RTS flow control lower watermark (%)" - default 25 - range 1 99 - depends on STM32_HCIUART_SW_RXFLOW - ---help--- - If software RTS flow control is enable, then RTS will be de-asserted - when there is less than this amount ofdata in the Rx buffere. The - amount is expressed as a percentage of the Rx buffer size. - -endmenu # HCI UART Driver Configuration - -endmenu # U[S]ART Configuration - -menu "I2S Configuration" - depends on STM32_I2S3 - -config STM32_I2S_MCK - bool "I2S_MCK" - default n - ---help--- - TBD. - -comment "I2S3 Configuration" - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32_I2C - -config STM32_I2C_ALT - bool "Alternate I2C implementation" - default STM32_PERFORMANCELINE - depends on !STM32_STM32F30XX - ---help--- - This selection enables an alternative I2C driver. This alternate - driver implements some rather complex workarounds for errata against - the STM32 F103 "Performance Line". This selection is an option - because: (1) It has not yet been fully verified and (2) It is not - certain that he scope of this workaround is needed only for the F103. - -config STM32_I2C_DUTY16_9 - bool "Frequency with Tlow/Thigh = 16/9" - default n - depends on STM32_I2C - -config STM32_I2C_DMA - bool "I2C DMA Support" - default n - depends on STM32_I2C && STM32_STM32F4XXX && STM32_DMA1 && !I2C_POLLED - ---help--- - This option enables the DMA for I2C transfers. - Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value for the - I2C dma streams, else the default priority level is set to medium. - -endmenu - -menu "I2C Slave Configuration" - depends on STM32_I2C_SLAVE - -config STM32_I2C_SLAVE_DEFAULT_TX - hex "Default TX byte to be sent when the TX buffer is empty" - default 0xFF - -config STM32_I2C_SLAVE_USEWQ - bool "Use work queue to delegate the isr completion status" - default n - ---help--- - With the current upperhalf I2C slave driver implementation, the user - should delegate the callback completion status using a work queue. - However, work queues introduce a delay, so in certain scenarios - it is better to use a custom driver without using a work queue. - -config STM32_I2C_SLAVE_RETRANSFER - bool "The frame is retransferred when stop is issued beforehand" - default n - ---help--- - If stop is issued before the whole frame is transferred, - the tx pointer is reset to 0. - -endmenu - -comment "USB Device Configuration" - -config STM32_USB_ITRMP - bool "Re-map USB interrupt" - default STM32_CAN1 - depends on STM32_USB && STM32_STM32F30XX - ---help--- - The legacy USB in the F1 series shared interrupt lines with USB - device and CAN1. In the F3 series, a hardware options was added to - either retain the legacy F1 behavior or to map the USB interrupts to - their own dedicated vectors. The option is available only for the - F3 family and selects the use of the dedicated USB interrupts. - -config STM32_QE - bool - default n - -if STM32_FOC - -config STM32_FOC_USE_ADC4 - bool - default n - select STM32_ADC4 - select STM32_ADC3_JEXTSEL - -config STM32_FOC_G4_ADCCHAN0_WORKAROUND - bool "FOC G4 ADC channel 0 unwanted conversion workaround" - default n - depends on STM32_STM32G4XXX - ---help--- - Some STM32G4 family chips have an issue that causes unwanted ADC channel 0 - conversion when a regular conversion is interrupted by an injected conversion. - This FOC implementation uses injected conversion to sample phase currents - and allows user to use regular conversion as an auxiliary analog conversion. - In this case, there is a certain probability that regular conversion will be - interrupted by an injected conversion that will lead to an incorrect reading - of phase currents. - - This workaround inserts a dummy conversion at the beginning of the injected - sequence. For more details look at the chip errata documents. - -endif #STM32_FOC diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 32c30a76ee7..0f0b7e4cd0f 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -59,7 +59,7 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V1),y) +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) ifeq ($(CONFIG_STM32_I2C_ALT),y) CHIP_CSRCS += stm32_i2c_alt.c else ifeq ($(CONFIG_STM32_STM32F4XXX),y) @@ -67,7 +67,7 @@ CHIP_CSRCS += stm32f40xxx_i2c.c else CHIP_CSRCS += stm32_i2c.c endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_V2),y) +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) CHIP_CSRCS += stm32_i2c_v2.c ifeq ($(CONFIG_STM32_I2C_SLAVE),y) CHIP_CSRCS += stm32_i2cslave_v2.c diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/stm32/hardware/stm32_adc.h index 4bfee933c6e..49df6093b60 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/stm32/hardware/stm32_adc.h @@ -46,18 +46,18 @@ * too much to keep it in the same file as ADC IPv2. */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Only one STM32 ADC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # if defined(CONFIG_STM32_STM32L15XX) # include "stm32_adc_v1l1.h" /* Special case for L1 */ # else # include "stm32_adc_v1.h" # endif -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32_adc_v2g4.h" /* Special case for G4 */ # else diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/stm32/hardware/stm32_adc_v1.h index 2d4432ca128..d1ba76649c3 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v1.h @@ -54,7 +54,7 @@ * - ... */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1_BASIC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC) # define HAVE_BASIC_ADC #else # undef HAVE_BASIC_ADC diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/stm32/hardware/stm32_adc_v2.h index 09a83fa13bf..6e62bb59a74 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/stm32/hardware/stm32_adc_v2.h @@ -57,7 +57,7 @@ * TODO: definitions for basic STM32 ADC IPv2 (F0, L0) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2_BASIC # define HAVE_BASIC_ADC # error TODO #else diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/stm32/hardware/stm32_comp.h index 414f7e62739..b950d622b07 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/stm32/hardware/stm32_comp.h @@ -39,13 +39,13 @@ /* If more than one COMP IP ensure that only one is selected */ -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # if defined(CONFIG_STM32_STM32F33XX) # include "stm32f33xxx_comp.h" # else # error "Device not supported." # endif -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32g4xxxx_comp.h" # else diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/stm32/hardware/stm32_dac.h index b04b56b3d16..34aa92ce260 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ b/arch/arm/src/stm32/hardware/stm32_dac.h @@ -36,14 +36,14 @@ * 2. STM32 DAC IPv2: G4 */ -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) && \ - defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) && \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # error Only one STM32 DAC IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DAC_V1) +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # include "stm32_dac_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DAC_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) # include "stm32gxxxxx_dac.h" /* Special case for G4 */ # else diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h index d1b6946f8bd..ce905d218d7 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32/hardware/stm32_dbgmcu.h @@ -39,11 +39,11 @@ #define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ #define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 # define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ # define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ #endif -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 # define STM32_DBGMCU_APB1_FZ1 0xe0042008 /* Debug MCU APB1 freeze 1 register */ # define STM32_DBGMCU_APB1_FZ2 0xe004200c /* Debug MCU APB1 freeze 2 register */ # define STM32_DBGMCU_APB2_FZ 0xe0042010 /* Debug MCU APB2 freeze register */ @@ -72,7 +72,7 @@ # define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ # define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V1 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 # define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ # define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ # define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ @@ -87,9 +87,9 @@ # define DBGMCU_CR_TIM6STOP (1 << 19) /* Bit 19: TIM6 stopped when core is halted */ # define DBGMCU_CR_TIM7STOP (1 << 20) /* Bit 20: TIM7 stopped when core is halted */ # define DBGMCU_CR_CAN2STOP (1 << 21) /* Bit 21: CAN2 stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V1 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V2 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 /* Debug MCU APB1 freeze register */ @@ -147,9 +147,9 @@ # define DBGMCU_APB2_TIM10STOP (1 << 3) /* Bit 3: TIM10 stopped when core is halted */ # define DBGMCU_APB2_TIM11STOP (1 << 4) /* Bit 4: TIM11 stopped when core is halted */ #endif -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V2 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 */ -#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_V3 +#ifdef CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 /* Debug MCU APB1 freeze 1 register */ @@ -180,7 +180,7 @@ # define DBGMCU_APB2_TIM20STOP (1 << 20) /* Bit 20: TIM20 stopped when core is halted */ # define DBGMCU_APB2_HRTIMSTOP (1 << 26) /* Bit 20: HRTIM stopped when core is halted */ -#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_V3 */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3 */ /**************************************************************************** * Public Types diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/stm32/hardware/stm32_i2c.h index 18c5f75cfa5..dd0a6f68872 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32/hardware/stm32_i2c.h @@ -32,9 +32,9 @@ * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 */ -#if defined(CONFIG_STM32_HAVE_IP_I2C_V1) +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) # include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_V2) +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) # include "stm32_i2c_v2.h" #else # error STM32 I2C IP version not specified diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/stm32/hardware/stm32_tim.h index 7adb23e6567..3815bf402db 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/stm32/hardware/stm32_tim.h @@ -27,10 +27,10 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) || \ - defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # include "stm32_tim_v1v2.h" -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V3) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) # include "stm32_tim_v3.h" #else # error "STM32 TIMER IP version not specified" diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h index bc1408b4847..44b35d1140f 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h @@ -42,9 +42,9 @@ * - 4-bit SMS in SMCR register */ -#if defined(CONFIG_STM32_HAVE_IP_TIMERS_V2) +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # define HAVE_IP_TIMERS_V2 -#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_V1) +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) # define HAVE_IP_TIMERS_V1 #else # error diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/stm32/stm32_adc.c index cd53b780eb4..331b4f1b795 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/stm32/stm32_adc.c @@ -308,7 +308,7 @@ /* ADC resolution. Not supported for basic STM32 ADC IPv1 */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define HAVE_ADC_RESOLUTION #else # undef HAVE_ADC_RESOLUTION @@ -316,7 +316,7 @@ /* ADC have common registers for all cores except basic ADC IPv1 (F1, F37x) */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # undef HAVE_ADC_CMN_REGS #else # define HAVE_ADC_CMN_REGS @@ -333,7 +333,7 @@ /* ADC DMA configuration bit support */ -#ifndef CONFIG_STM32_HAVE_IP_ADC_V1_BASIC +#ifndef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1_BASIC # define ADC_HAVE_DMACFG 1 #else # undef ADC_HAVE_DMACFG @@ -341,7 +341,7 @@ /* ADC scan mode support - only for ADCv1 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 # define ADC_HAVE_SCAN 1 # ifndef CONFIG_STM32_ADC1_SCAN # define CONFIG_STM32_ADC1_SCAN 0 diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c index 2f25d07a5a3..b095de41efa 100644 --- a/arch/arm/src/stm32/stm32_comp.c +++ b/arch/arm/src/stm32/stm32_comp.c @@ -47,9 +47,9 @@ * - STM32 COMP IP version 2: SMT32G4XXX */ -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # include "stm32_comp_v2.c" #else # error "STM32 COMP IP version not supported." diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/stm32/stm32_comp.h index 5f3ae2c74e9..02e74e84972 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/stm32/stm32_comp.h @@ -33,9 +33,9 @@ #include "hardware/stm32_comp.h" -#if defined(CONFIG_STM32_HAVE_IP_COMP_V1) +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_V2) +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # include "stm32_comp_v2.h" #endif diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/stm32/stm32_foc.c index edced961d9a..4982a812b12 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/stm32/stm32_foc.c @@ -106,14 +106,14 @@ /* This is not for ADC IPv2 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) && defined(HAVE_BASIC_ADC) # error Not supported ADC IP core #endif /* Multi instances support tested only on IP_ADC_V1 */ #if CONFIG_MOTOR_FOC_INST > 1 -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # error Not tested yet # endif #endif @@ -141,10 +141,10 @@ /* Debug register for PWM timers */ -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) #endif @@ -154,10 +154,10 @@ # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) # endif # if CONFIG_STM32_TIM1_MODE != 2 @@ -171,10 +171,10 @@ # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_V3) +# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1) +# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) # define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) # endif # if CONFIG_STM32_TIM8_MODE != 2 @@ -248,14 +248,14 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC12_JSQR_JEXTSEL_T1CC4) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC12_JSQR_JEXTSEL_T8CC4) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) # endif @@ -314,14 +314,14 @@ * TIMx TRGO = (ARR) */ -# if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +# if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC12_JSQR_JEXTSEL_T1TRGO) # endif # ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8TRGO (ADC12_JSQR_JEXTSEL_T8TRGO) # endif -# elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +# elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) # endif @@ -470,11 +470,11 @@ /* Generalize ADC interrupt flags */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V2) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # define FOC_ADC_ISR_FOC ADC_ISR_JEOS # define FOC_ADC_IER_FOC ADC_IER_JEOS # define FOC_ADC_ISR_OVR ADC_INT_OVR -#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1) +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # define FOC_ADC_ISR_FOC ADC_ISR_JEOC # define FOC_ADC_IER_FOC ADC_IER_JEOC # define FOC_ADC_ISR_OVR ADC_SR_OVR @@ -515,7 +515,7 @@ /* Common for ADCv1 */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && !defined(HAVE_BASIC_ADC) # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn123) @@ -530,7 +530,7 @@ /* Common for ADCv1 basic */ -#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && defined(HAVE_BASIC_ADC) # undef FOC_ADC_HAVE_CMN # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (0) @@ -545,7 +545,7 @@ /* Common for ADCv2 */ -#ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +#ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # define FOC_ADC_HAVE_CMN (1) # ifdef CONFIG_STM32_FOC_USE_ADC1 # define FOC_ADC1_CMN (&g_stm32_foc_adccmn12) @@ -895,7 +895,7 @@ static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, ****************************************************************************/ #ifdef FOC_ADC_HAVE_CMN -# ifdef CONFIG_STM32_HAVE_IP_ADC_V1 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 /* Common for ADC123 */ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = @@ -903,9 +903,9 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 = .cntr = 0, .lock = NXMUTEX_INITIALIZER, }; -# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 */ -# ifdef CONFIG_STM32_HAVE_IP_ADC_V2 +# ifdef CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 # if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2) /* Common for ADC12 */ @@ -924,7 +924,7 @@ static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 = .lock = NXMUTEX_INITIALIZER, }; # endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */ -# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */ +# endif /* CONFIG_STM32_HAVE_IP_ADC_M3M4_V2 */ #endif /* FOC_ADC_HAVE_CMN */ /* STM32 specific FOC data */ diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig index 3680c9a8ac3..7ba32284fb0 100644 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ b/arch/arm/src/stm32f0l0g0/Kconfig @@ -1053,6 +1053,7 @@ config STM32_FLASH_OVERRIDE config STM32_STM32F0 bool default n + select STM32_HAVE_PWR select STM32_HAVE_USART3 select STM32_HAVE_USART4 select STM32_HAVE_TIM1 @@ -1064,14 +1065,19 @@ config STM32_STM32F0 select STM32_HAVE_TIM15 select STM32_HAVE_TIM16 select STM32_HAVE_TIM17 - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_EXTI_V1 config STM32_STM32G0 bool default n - select STM32_HAVE_ADC1_DMA + select STM32_HAVE_PWR + select STM32_HAVE_DMA1 + select STM32_HAVE_ADC1 + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_WDG_M0_V1 select STM32_HAVE_DMAMUX select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_EXTI_V2 @@ -1086,20 +1092,29 @@ config STM32_STM32G0 config STM32_STM32L0 bool default n + select STM32_HAVE_PWR + select STM32_HAVE_ADC1 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_DMA1 select STM32_ENERGYLITE select STM32_HAVE_LCD select STM32_HAVE_VREFINT - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V1 select STM32_HAVE_IP_EXTI_V1 config STM32_STM32C0 bool default n + select STM32_HAVE_PWR + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_DMA1 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_ADC1 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 select STM32_HAVE_SPI2 select STM32_HAVE_I2C2 select STM32_HAVE_DMAMUX - select STM32_HAVE_ADC1_DMA select STM32_HAVE_IP_USART_V2 select STM32_HAVE_IP_EXTI_V2 select STM32_HAVE_TIM1 @@ -1401,134 +1416,3 @@ config ARCH_CHIP_STM32C092XX select STM32_HAVE_USART3 select STM32_HAVE_USART4 select STM32_HAVE_FDCAN1 - -choice - prompt "SysTick clock source" - default STM32_SYSTICK_CORECLK - -config STM32_SYSTICK_CORECLK - bool "Cortex-M0 core clock" - -config STM32_SYSTICK_CORECLK_DIV16 - bool "Cortex-M0 core clock divided by 16" - -endchoice # SysTick clock source - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32_HAVE_VREFINT - bool - default n - -config STM32_HAVE_USART4 - bool - default n - -config STM32_HAVE_USART5 - bool - default n - -config STM32_HAVE_USART7 - bool - default n - -config STM32_HAVE_USART8 - bool - default n - -config STM32_HAVE_LPUART2 - bool - default n - -config STM32_HAVE_ADC_OVERSAMPLE - bool - default STM32_STM32L0 || STM32_STM32G0 || STM32_STM32C0 - -config STM32_HAVE_CEC - bool - default n - -config STM32_HAVE_SDIO - bool - default n - -config STM32_HAVE_I2S2 - bool - default n - -config STM32_HAVE_UCPD1 - bool - default n - -config STM32_HAVE_UCPD2 - bool - default n - -# These are STM32 peripherals IP blocks - -config STM32_HAVE_IP_USART_V1 - bool - default n - -config STM32_HAVE_IP_USART_V2 - bool - default n - -config STM32_HAVE_IP_EXTI_V1 - bool - default n - -config STM32_HAVE_IP_EXTI_V2 - bool - default n - -# These are the peripheral selections proper - -config STM32_VREFINT - bool "Enable VREFINT" - default n - depends on STM32_HAVE_VREFINT - -config STM32_USART4 - bool "USART4" - default n - depends on STM32_HAVE_USART4 - select STM32_USART - -config STM32_USART5 - bool "USART5" - default n - depends on STM32_HAVE_USART5 - select STM32_USART - -config STM32_USART7 - bool "USART7" - default n - depends on STM32_HAVE_USART7 - select STM32_USART - -config STM32_USART8 - bool "USART8" - default n - depends on STM32_HAVE_USART8 - select STM32_USART - -endmenu # STM32 Peripheral Support - -menu "ADC Configuration" - depends on STM32_ADC - -config STM32_ADC1_CONTINUOUS - bool "Enable ADC1 Continuous Conversion Mode" - default n - depends on STM32_ADC1 - ---help--- - If enabled, the ADC will operate in continuous conversion mode. - Otherwise, it will perform single conversions. - Note: Continuous and discontinuous mode cannot be defined at - the same time - -endmenu # ADC Configuration diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig index a9c565cda42..faac0bde227 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig index 6b40188837b..b51bbbb4f4a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index d7167b38ab3..6be6bf998c4 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig index c2004420019..cfe38151ba5 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/common/src/board_pwm.c b/boards/arm/stm32f0l0g0/common/src/board_pwm.c index 793b0398537..d26772a5dc1 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_pwm.c +++ b/boards/arm/stm32f0l0g0/common/src/board_pwm.c @@ -55,7 +55,7 @@ int stm32_pwm_setup(void) if (!initialized) { -#ifdef CONFIG_STM32F0L0G0_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM pwm = stm32_pwminitialize(1); if (pwm == NULL) { @@ -71,7 +71,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM pwm = stm32_pwminitialize(2); if (pwm == NULL) { @@ -87,7 +87,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM pwm = stm32_pwminitialize(3); if (pwm == NULL) { @@ -103,7 +103,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM pwm = stm32_pwminitialize(14); if (pwm == NULL) { @@ -119,7 +119,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM pwm = stm32_pwminitialize(15); if (pwm == NULL) { @@ -135,7 +135,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM pwm = stm32_pwminitialize(16); if (pwm == NULL) { @@ -151,7 +151,7 @@ int stm32_pwm_setup(void) } #endif -#ifdef CONFIG_STM32F0L0G0_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM pwm = stm32_pwminitialize(17); if (pwm == NULL) { diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig index d7d1b1380ec..3803bc20d69 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig index 6f04583925b..06f620204ed 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig index ede50792f32..105e69b35bd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig index af46d19b5c7..d9a948b94c4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig index 9a9e901e2bd..6a9589eea45 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig index 8728028d0dc..c135e688fcc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig index 49856182e00..665917285bf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y CONFIG_ARCH_CHIP_STM32C0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig index b5de6c951e8..e65551b343e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BOARD="nucleo-f072rb" CONFIG_ARCH_BOARD_NUCLEO_F072RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig index 10d566c6b7d..23fbeaa2d4d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig index aac6d738084..f38d694fe4b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig index 9b43266c335..5381c3dce05 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-g070rb" CONFIG_ARCH_BOARD_NUCLEO_G070RB=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G070RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_IRQBUTTONS=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig index 58d337a3690..8960d71e898 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g071rb" CONFIG_ARCH_BOARD_NUCLEO_G071RB=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig index 565ff0d9dd1..afc8179b09e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig index 539f7b5141c..2cffd2d94c1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig index 5eea859d573..e093b5b2a67 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig index c04c43cd46e..9633c3b48c0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig index fc8331e8670..38cc3a0d14e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y CONFIG_ARCH_CHIP_STM32L0=y diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig index 22a9310041d..cfea4a1858a 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f051-discovery" CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F051R8=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig index 7fc5f309f92..9a218ef1cc1 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f072-discovery" CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig index 693e2684eb6..2c85c18f603 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_STM32G071B_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig index 727e0620e56..a0e1eef8c5b 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32G071B_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig index f761d37e14e..ce9e752caa6 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l0538-disco" CONFIG_ARCH_BOARD_STM32L0538_DISCO=y CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L053C8=y CONFIG_ARCH_CHIP_STM32L053XX=y CONFIG_ARCH_CHIP_STM32L0=y From c306e4129dcacb753dd3f8d5301367b06cdce049 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 086/268] !arch/stm32f7: use common STM32 Kconfig symbols BREAKING CHANGE: STM32F7 Kconfig symbols were renamed from CONFIG_STM32F7_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_STM32F7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../guides/port_drivers_to_stm32f7.rst | 12 +- .../stm32f7/boards/nucleo-f722ze/index.rst | 4 +- .../stm32f7/boards/nucleo-f746zg/index.rst | 4 +- .../stm32f7/boards/nucleo-f767zi/index.rst | 4 +- .../stm32f7/boards/stm32f769i-disco/index.rst | 6 +- Documentation/platforms/arm/stm32f7/index.rst | 96 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32f7/chip.h | 40 +- arch/arm/include/stm32f7/irq.h | 6 +- arch/arm/src/stm32f7/CMakeLists.txt | 52 +- arch/arm/src/stm32f7/Kconfig | 7433 ++--------------- arch/arm/src/stm32f7/Make.defs | 50 +- arch/arm/src/stm32f7/hardware/stm32_adc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_can.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_dma.h | 6 +- .../arm/src/stm32f7/hardware/stm32_ethernet.h | 10 +- arch/arm/src/stm32f7/hardware/stm32_exti.h | 8 +- arch/arm/src/stm32f7/hardware/stm32_flash.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_gpio.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_i2c.h | 6 +- .../src/stm32f7/hardware/stm32_memorymap.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_pinmap.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_pwr.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_rcc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_sdmmc.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_spi.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_syscfg.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_tim.h | 6 +- arch/arm/src/stm32f7/hardware/stm32_uart.h | 6 +- .../src/stm32f7/hardware/stm32f72xx73xx_dma.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_flash.h | 34 +- .../stm32f7/hardware/stm32f72xx73xx_gpio.h | 4 +- .../hardware/stm32f72xx73xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_pinmap.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f72xx73xx_rcc.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_syscfg.h | 4 +- .../stm32f7/hardware/stm32f72xx73xx_uart.h | 4 +- .../src/stm32f7/hardware/stm32f74xx75xx_dma.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_flash.h | 32 +- .../stm32f7/hardware/stm32f74xx75xx_gpio.h | 4 +- .../hardware/stm32f74xx75xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_pinmap.h | 6 +- .../src/stm32f7/hardware/stm32f74xx75xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f74xx75xx_rcc.h | 4 +- .../stm32f7/hardware/stm32f74xx75xx_syscfg.h | 4 +- .../src/stm32f7/hardware/stm32f74xx77xx_spi.h | 4 +- .../stm32f7/hardware/stm32f74xx77xx_uart.h | 6 +- .../src/stm32f7/hardware/stm32f76xx77xx_dma.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_flash.h | 44 +- .../stm32f7/hardware/stm32f76xx77xx_gpio.h | 4 +- .../hardware/stm32f76xx77xx_memorymap.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_pinmap.h | 6 +- .../src/stm32f7/hardware/stm32f76xx77xx_pwr.h | 4 +- .../src/stm32f7/hardware/stm32f76xx77xx_rcc.h | 4 +- .../stm32f7/hardware/stm32f76xx77xx_syscfg.h | 4 +- arch/arm/src/stm32f7/stm32_adc.c | 176 +- arch/arm/src/stm32f7/stm32_adc.h | 486 +- arch/arm/src/stm32f7/stm32_allocateheap.c | 8 +- arch/arm/src/stm32f7/stm32_bbsram.c | 14 +- arch/arm/src/stm32f7/stm32_bbsram.h | 14 +- arch/arm/src/stm32f7/stm32_can.c | 36 +- arch/arm/src/stm32f7/stm32_can.h | 40 +- arch/arm/src/stm32f7/stm32_can_sock.c | 60 +- arch/arm/src/stm32f7/stm32_capture.c | 122 +- arch/arm/src/stm32f7/stm32_config.h | 42 +- arch/arm/src/stm32f7/stm32_dma.c | 14 +- arch/arm/src/stm32f7/stm32_dma.h | 2 +- arch/arm/src/stm32f7/stm32_dma2d.c | 42 +- arch/arm/src/stm32f7/stm32_dma2d.h | 2 +- arch/arm/src/stm32f7/stm32_dtcm.h | 8 +- arch/arm/src/stm32f7/stm32_dumpgpio.c | 8 +- arch/arm/src/stm32f7/stm32_ethernet.c | 242 +- arch/arm/src/stm32f7/stm32_ethernet.h | 4 +- arch/arm/src/stm32f7/stm32_exti_gpio.c | 8 +- arch/arm/src/stm32f7/stm32_fmc.c | 4 +- arch/arm/src/stm32f7/stm32_foc.c | 156 +- arch/arm/src/stm32f7/stm32_gpio.c | 8 +- arch/arm/src/stm32f7/stm32_i2c.c | 112 +- arch/arm/src/stm32f7/stm32_i2c.h | 8 +- arch/arm/src/stm32f7/stm32_i2s.c | 178 +- arch/arm/src/stm32f7/stm32_lse.c | 32 +- arch/arm/src/stm32f7/stm32_ltdc.c | 300 +- arch/arm/src/stm32f7/stm32_otg.h | 8 +- arch/arm/src/stm32f7/stm32_otgdev.c | 42 +- arch/arm/src/stm32f7/stm32_otghost.c | 34 +- arch/arm/src/stm32f7/stm32_pulsecount.c | 88 +- arch/arm/src/stm32f7/stm32_pwm.c | 564 +- arch/arm/src/stm32f7/stm32_pwm.h | 514 +- arch/arm/src/stm32f7/stm32_pwr.c | 2 +- arch/arm/src/stm32f7/stm32_qencoder.c | 106 +- arch/arm/src/stm32f7/stm32_qencoder.h | 24 +- arch/arm/src/stm32f7/stm32_qspi.c | 102 +- arch/arm/src/stm32f7/stm32_qspi.h | 4 +- arch/arm/src/stm32f7/stm32_rcc.c | 18 +- arch/arm/src/stm32f7/stm32_rcc.h | 16 +- arch/arm/src/stm32f7/stm32_rng.c | 4 +- arch/arm/src/stm32f7/stm32_rtc.c | 44 +- arch/arm/src/stm32f7/stm32_rtc.h | 20 +- arch/arm/src/stm32f7/stm32_sai.c | 72 +- arch/arm/src/stm32f7/stm32_sdmmc.c | 154 +- arch/arm/src/stm32f7/stm32_serial.c | 134 +- arch/arm/src/stm32f7/stm32_spi.c | 168 +- arch/arm/src/stm32f7/stm32_spi.h | 24 +- arch/arm/src/stm32f7/stm32_tickless.c | 60 +- arch/arm/src/stm32f7/stm32_tim.c | 290 +- arch/arm/src/stm32f7/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32f7/stm32_uart.h | 88 +- arch/arm/src/stm32f7/stm32_usbhost.h | 12 +- arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c | 162 +- arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c | 142 +- arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c | 148 +- boards/arm/stm32f7/common/Kconfig | 106 +- .../stm32f7/common/include/stm32_can_setup.h | 2 +- .../common/include/stm32_cansock_setup.h | 2 +- .../arm/stm32f7/common/include/stm32_romfs.h | 4 +- .../stm32f7/common/include/stm32_spitest.h | 2 +- boards/arm/stm32f7/common/src/CMakeLists.txt | 10 +- boards/arm/stm32f7/common/src/Make.defs | 10 +- .../arm/stm32f7/common/src/stm32_can_setup.c | 6 +- .../stm32f7/common/src/stm32_cansock_setup.c | 6 +- .../common/src/stm32_romfs_initialize.c | 28 +- boards/arm/stm32f7/common/src/stm32_spitest.c | 64 +- boards/arm/stm32f7/nucleo-f722ze/Kconfig | 10 +- .../nucleo-f722ze/configs/can/defconfig | 13 +- .../nucleo-f722ze/configs/cansock/defconfig | 15 +- .../nucleo-f722ze/configs/composite/defconfig | 9 +- .../nucleo-f722ze/configs/nsh/defconfig | 7 +- .../stm32f7/nucleo-f722ze/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f722ze/src/Make.defs | 4 +- .../stm32f7/nucleo-f722ze/src/nucleo-f722ze.h | 16 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_adc.c | 16 +- .../stm32f7/nucleo-f722ze/src/stm32_bbsram.c | 16 +- .../stm32f7/nucleo-f722ze/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f722ze/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f722ze/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f722ze/src/stm32_usb.c | 4 +- boards/arm/stm32f7/nucleo-f746zg/Kconfig | 10 +- .../nucleo-f746zg/configs/evalos/defconfig | 7 +- .../nucleo-f746zg/configs/note/defconfig | 81 +- .../nucleo-f746zg/configs/nsh/defconfig | 9 +- .../nucleo-f746zg/configs/pysim/defconfig | 83 +- .../stm32f7/nucleo-f746zg/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f746zg/src/Make.defs | 4 +- .../stm32f7/nucleo-f746zg/src/nucleo-f746zg.h | 16 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_adc.c | 16 +- .../stm32f7/nucleo-f746zg/src/stm32_bbsram.c | 16 +- .../stm32f7/nucleo-f746zg/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f746zg/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f746zg/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f746zg/src/stm32_usb.c | 4 +- boards/arm/stm32f7/nucleo-f767zi/Kconfig | 10 +- .../nucleo-f767zi/configs/evalos/defconfig | 9 +- .../nucleo-f767zi/configs/netnsh/defconfig | 19 +- .../nucleo-f767zi/configs/nsh/defconfig | 1 + .../stm32f7/nucleo-f767zi/src/CMakeLists.txt | 4 +- .../arm/stm32f7/nucleo-f767zi/src/Make.defs | 4 +- .../stm32f7/nucleo-f767zi/src/nucleo-f767zi.h | 16 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_adc.c | 16 +- .../stm32f7/nucleo-f767zi/src/stm32_bbsram.c | 16 +- .../stm32f7/nucleo-f767zi/src/stm32_boot.c | 2 +- .../stm32f7/nucleo-f767zi/src/stm32_bringup.c | 30 +- .../stm32f7/nucleo-f767zi/src/stm32_gpio.c | 4 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c | 8 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_spi.c | 36 +- .../arm/stm32f7/nucleo-f767zi/src/stm32_usb.c | 4 +- boards/arm/stm32f7/steval-eth001v1/Kconfig | 4 +- .../steval-eth001v1/configs/foc_b16/defconfig | 23 +- .../steval-eth001v1/configs/foc_f32/defconfig | 23 +- .../steval-eth001v1/configs/nsh/defconfig | 3 +- .../steval-eth001v1/src/CMakeLists.txt | 2 +- .../arm/stm32f7/steval-eth001v1/src/Make.defs | 2 +- .../steval-eth001v1/src/steval-eth001v1.h | 2 +- .../steval-eth001v1/src/stm32_bringup.c | 2 +- .../stm32f7/steval-eth001v1/src/stm32_foc.c | 28 +- .../stm32f746-ws/configs/nsh/defconfig | 19 +- .../stm32f7/stm32f746-ws/src/CMakeLists.txt | 4 +- boards/arm/stm32f7/stm32f746-ws/src/Make.defs | 4 +- .../arm/stm32f7/stm32f746-ws/src/stm32_boot.c | 8 +- .../arm/stm32f7/stm32f746-ws/src/stm32_spi.c | 32 +- .../arm/stm32f7/stm32f746-ws/src/stm32_usb.c | 8 +- .../stm32f7/stm32f746-ws/src/stm32f746-ws.h | 2 +- boards/arm/stm32f7/stm32f746g-disco/Kconfig | 2 +- .../stm32f746g-disco/configs/audio/defconfig | 15 +- .../stm32f746g-disco/configs/fb/defconfig | 15 +- .../stm32f746g-disco/configs/lvgl/defconfig | 19 +- .../stm32f746g-disco/configs/netnsh/defconfig | 21 +- .../stm32f746g-disco/configs/nsh/defconfig | 3 +- .../stm32f746g-disco/configs/nxdemo/defconfig | 15 +- .../stm32f746g-disco/configs/nxterm/defconfig | 15 +- .../stm32f7/stm32f746g-disco/include/board.h | 6 +- .../stm32f746g-disco/src/CMakeLists.txt | 10 +- .../stm32f7/stm32f746g-disco/src/Make.defs | 10 +- .../stm32f7/stm32f746g-disco/src/stm32_adc.c | 8 +- .../stm32f7/stm32f746g-disco/src/stm32_boot.c | 10 +- .../stm32f746g-disco/src/stm32_extmem.c | 2 +- .../stm32f7/stm32f746g-disco/src/stm32_lcd.c | 2 +- .../stm32f7/stm32f746g-disco/src/stm32_spi.c | 28 +- .../stm32f746g-disco/src/stm32_touchscreen.c | 4 +- .../stm32f7/stm32f746g-disco/src/stm32_usb.c | 8 +- .../stm32f746g-disco/src/stm32f746g-disco.h | 8 +- .../stm32f769i-disco/configs/netnsh/defconfig | 39 +- .../stm32f769i-disco/configs/nsh/defconfig | 3 +- .../stm32f7/stm32f769i-disco/include/board.h | 4 +- .../stm32f769i-disco/src/CMakeLists.txt | 2 +- .../stm32f7/stm32f769i-disco/src/Make.defs | 2 +- .../stm32f7/stm32f769i-disco/src/stm32_boot.c | 8 +- .../stm32f769i-disco/src/stm32_extmem.c | 2 +- .../stm32f7/stm32f769i-disco/src/stm32_spi.c | 28 +- .../stm32f769i-disco/src/stm32f769i-disco.h | 2 +- .../configs/dualcdcacm/defconfig | 5 +- .../configs/f7corecomp/defconfig | 17 +- .../configs/i2s/defconfig | 17 +- .../configs/meadow_os/defconfig | 5 +- .../configs/nsh/defconfig | 3 +- .../configs/projectlab/defconfig | 9 +- .../configs/sdram/defconfig | 7 +- .../configs/usbnsh/defconfig | 7 +- .../stm32f777zit6-meadow/include/board.h | 4 +- .../stm32f777zit6-meadow/src/CMakeLists.txt | 6 +- .../stm32f777zit6-meadow/src/Make.defs | 8 +- .../stm32f777zit6-meadow/src/stm32_boot.c | 12 +- .../stm32f777zit6-meadow/src/stm32_extmem.c | 2 +- .../stm32f777zit6-meadow/src/stm32_spi.c | 28 +- .../stm32f777zit6-meadow/src/stm32_usb.c | 8 +- .../src/stm32f777zit6-meadow.h | 6 +- 231 files changed, 4277 insertions(+), 10541 deletions(-) diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index 0d552320695..e7c04a2f3e3 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -262,7 +262,7 @@ the buffers to the Cortex-M7 D-Cache line size: #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) - #ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC + #ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -274,10 +274,10 @@ the buffers to the Cortex-M7 D-Cache line size: #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) - #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) - #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) + #define RXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NRXDESC) + #define TXTABLE_SIZE (STM32F7_NETHERNET * CONFIG_STM32_ETH_NTXDESC) - #define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) + #define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32F7_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -366,8 +366,8 @@ Here is an example where the RX descriptors are invalidated: for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { ... diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst index 7beb7bb52a0..0243fbc5dec 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f722ze/index.rst @@ -177,7 +177,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -213,7 +213,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst index f9ce45c6e3b..f010732432a 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f746zg/index.rst @@ -219,7 +219,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -255,7 +255,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst index ef64085ad76..addc01caee4 100644 --- a/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/nucleo-f767zi/index.rst @@ -221,7 +221,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART6 as the console:: - CONFIG_STM32F7_USART6=y + CONFIG_STM32_USART6=y CONFIG_USARTs_SERIALDRIVER=y CONFIG_USARTS_SERIAL_CONSOLE=y CONFIG_USART6_RXBUFSIZE=256 @@ -257,7 +257,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART8 as the console:: - CONFIG_STM32F7_UART8=y + CONFIG_STM32_UART8=y CONFIG_UART8_SERIALDRIVER=y CONFIG_UART8_SERIAL_CONSOLE=y CONFIG_UART8_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst index d510c3e4981..dbe20d4247b 100644 --- a/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst +++ b/Documentation/platforms/arm/stm32f7/boards/stm32f769i-disco/index.rst @@ -129,9 +129,9 @@ configuration no builtin applications are selected. And these for enabling the STM32 timer PWM channel: - CONFIG_STM32F7_TIM1=y - CONFIG_STM32F7_TIM1_PWM=y - CONFIG_STM32F7_TIM1_CHANNEL=4 + CONFIG_STM32_TIM1=y + CONFIG_STM32_TIM1_PWM=y + CONFIG_STM32_TIM1_CHANNEL=4 nsh-ehternet ------------ diff --git a/Documentation/platforms/arm/stm32f7/index.rst b/Documentation/platforms/arm/stm32f7/index.rst index 5669353e6a0..6f525e8e2fe 100644 --- a/Documentation/platforms/arm/stm32f7/index.rst +++ b/Documentation/platforms/arm/stm32f7/index.rst @@ -106,7 +106,7 @@ managed with dtcm_malloc(), dtcm_free(), etc. In order to use FMC SRAM, the following additional things need to be present in the NuttX configuration file: -- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the +- CONFIG_STM32_FMC_SRAM - Indicates that SRAM is available via the FMC (as opposed to an LCD or FLASH). - CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex) @@ -123,10 +123,10 @@ present in the NuttX configuration file: Clock ----- -- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock +- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock configuration features.:: - CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n + CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n - CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops @@ -134,23 +134,23 @@ Timers ------ Timer devices may be used for different purposes. One special purpose is -to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn +to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn is defined (as above) then the following may also be defined to indicate that the timer is intended to be used for pulsed output modulation, ADC conversion, or DAC conversion. Note that ADC/DAC require two definition: Not only do you have to assign the timer (n) for used by the ADC or DAC, but then you also have to configure which ADC or DAC (m) it is assigned to.: -- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 -- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 -- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 -- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 +- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14 +- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14 +- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3 +- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14 +- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2 For each timer that is enabled for PWM usage, we need the following additional configuration settings: -- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} +- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4} NOTE: The STM32 timers are each capable of generating different signals on each of the four channels with different duty cycles. That capability is @@ -206,11 +206,11 @@ CAN - CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined. -- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 +- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6 -- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 +- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7 -- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an +- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an dump of all CAN registers. CAN SocketCAN @@ -221,12 +221,12 @@ TODO SPI --- -- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI +- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI support. Non-interrupt-driven, poll-waiting is recommended if the interrupt rate would be to high in the interrupt driven case. -- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance. - Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT. +- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance. + Cannot be used with CONFIG_STM32_SPI_INTERRUPT. SDIO ---- @@ -238,41 +238,41 @@ ETH Options: -- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board +- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board -- CONFIG_STM32F7_MII - Support Ethernet MII interface +- CONFIG_STM32_MII - Support Ethernet MII interface -- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface +- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface -- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface +- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface -- CONFIG_STM32F7_RMII - Support Ethernet RMII interface +- CONFIG_STM32_RMII - Support Ethernet RMII interface -- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode +- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode -- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select full duplex mode. Default: half-duplex -- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this +- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this may be defined to select 100 MBps speed. Default: 10 Mbps -- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is defined. The PHY status register address may diff from PHY to PHY. This configuration sets the address of the PHY status register. -- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides bit mask indicating 10 or 100MBps speed. -- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the speed bit(s) indicating 100MBps speed. -- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is defined. This provide bit mask indicating full or half duplex modes. -- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is +- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is defined. This provides the value of the mode bits indicating full duplex mode. -- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported +- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported but some hooks are indicated with this condition. USB OTG FS @@ -284,30 +284,30 @@ Pre-requisites: - CONFIG_USBDEV - Enable USB device support - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block -- CONFIG_STM32F7_SYSCFG - Needed +- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block +- CONFIG_STM32_SYSCFG - Needed - CONFIG_SCHED_WORKQUEUE - Worker thread support is required Options: -- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. +- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. Default 128 (512 bytes) -- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO +- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit +- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes) -- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 +- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128 -- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever +- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever want to do that? -- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access +- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access debug. Depends on CONFIG_DEBUG_FEATURES. -- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB +- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB packets. Depends on CONFIG_DEBUG_FEATURES. USB OTG HS @@ -353,16 +353,16 @@ Available for some Nucleo boards. The builtin SPI test facility can be enabled with the following settings:: - +CONFIG_STM32F7_SPI=y - +CONFIG_STM32F7_SPI1=y - +CONFIG_STM32F7_SPI2=y - +CONFIG_STM32F7_SPI3=y + +CONFIG_STM32_SPI=y + +CONFIG_STM32_SPI1=y + +CONFIG_STM32_SPI2=y + +CONFIG_STM32_SPI3=y - +# CONFIG_STM32F7_SPI_INTERRUPTS is not set - +# CONFIG_STM32F7_SPI1_DMA is not set - +# CONFIG_STM32F7_SPI2_DMA is not set - +# CONFIG_STM32F7_SPI3_DMA is not set - # CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set + +# CONFIG_STM32_SPI_INTERRUPTS is not set + +# CONFIG_STM32_SPI1_DMA is not set + +# CONFIG_STM32_SPI2_DMA is not set + +# CONFIG_STM32_SPI3_DMA is not set + # CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +CONFIG_NUCLEO_SPI_TEST=y +CONFIG_NUCLEO_SPI_TEST_MESSAGE="Hello World" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d6d54a5fd26..2def7a21314 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -622,6 +622,7 @@ config ARCH_CHIP_STM32C0 config ARCH_CHIP_STM32F7 bool "STMicro STM32 F7" + select ARCH_CHIP_STM32 select ARCH_CORTEXM7 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 99047dd9757..9fe7f2cd2e0 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -264,7 +264,7 @@ /* Size SRAM */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # define STM32_SRAM1_SIZE (176*1024) /* 176Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -277,7 +277,7 @@ # else # define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -290,7 +290,7 @@ # else # define STM32_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */ # endif -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ # if defined(CONFIG_ARMV7M_HAVE_DTCM) @@ -309,7 +309,7 @@ /* Common to all Advanced (vs Foundation) Family members */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # define STM32_NSPDIFRX 0 /* Not supported */ # define STM32_NGPIO 9 /* 9 GPIO ports, GPIOA-I */ # define STM32_NI2C 3 /* I2C1-3 */ @@ -350,75 +350,75 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32F7_HAVE_FMC) +#if defined(CONFIG_STM32_HAVE_FMC) # define STM32_NFMC 1 /* Have FMC memory controller */ #else # define STM32_NFMC 0 /* No FMC memory controller */ #endif -#if defined(CONFIG_STM32F7_HAVE_ETHRNET) +#if defined(CONFIG_STM32_HAVE_ETHRNET) # define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else # define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32F7_HAVE_RNG) +#if defined(CONFIG_STM32_HAVE_RNG) # define STM32_NRNG 1 /* Random number generator (RNG) */ #else # define STM32_NRNG 0 /* No Random number generator (RNG) */ #endif -#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6) +#if defined(CONFIG_STM32_HAVE_SPI5) && defined(CONFIG_STM32_HAVE_SPI6) # define STM32_NSPI 6 /* SPI1-6 (Advanced Family Except V series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI5) +#elif defined(CONFIG_STM32_HAVE_SPI5) # define STM32_NSPI 5 /* SPI1-5 (Foundation Family Except V & R series) */ -#elif defined(CONFIG_STM32F7_HAVE_SPI4) +#elif defined(CONFIG_STM32_HAVE_SPI4) # define STM32_NSPI 4 /* SPI1-4 V series */ #else # define STM32_NSPI 3 /* SPI1-3 R series */ #endif -#if defined(CONFIG_STM32F7_HAVE_SDMMC2) +#if defined(CONFIG_STM32_HAVE_SDMMC2) # define STM32_NSDMMC 2 /* 2 SDMMC interfaces */ #else # define STM32_NSDMMC 1 /* 1 SDMMC interface */ #endif -#if defined(CONFIG_STM32F7_HAVE_CAN3) +#if defined(CONFIG_STM32_HAVE_CAN3) # define STM32_NCAN 3 /* CAN1-3 */ -#elif defined(CONFIG_STM32F7_HAVE_CAN2) +#elif defined(CONFIG_STM32_HAVE_CAN2) # define STM32_NCAN 2 /* CAN1-2 */ #else # define STM32_NCAN 1 /* CAN1 only */ #endif -#if defined(CONFIG_STM32F7_HAVE_DCMI) +#if defined(CONFIG_STM32_HAVE_DCMI) # define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ #else # define STM32_NDCMI 0 /* No Digital camera interface (DCMI) */ #endif -#if defined(CONFIG_STM32F7_HAVE_DSIHOST) +#if defined(CONFIG_STM32_HAVE_DSIHOST) # define STM32_NDSIHOST 1 /* Have MIPI DSI Host */ #else # define STM32_NDSIHOST 0 /* No MIPI DSI Host */ #endif -#if defined (CONFIG_STM32F7_HAVE_LTDC) +#if defined (CONFIG_STM32_HAVE_LTDC) # define STM32_NLCDTFT 1 /* One LCD-TFT */ #else # define STM32_NLCDTFT 0 /* No LCD-TFT */ #endif -#if defined(CONFIG_STM32F7_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ +#if defined(CONFIG_STM32_HAVE_DMA2D) /* bf20171107 Swapped defines they were reversed. */ # define STM32_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */ #else # define STM32_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */ #endif -#if defined(CONFIG_STM32F7_HAVE_JPEG) +#if defined(CONFIG_STM32_HAVE_JPEG) #define STM32_NJPEG 1 /* One JPEG Converter */ #else #define STM32_NJPEG 0 /* No JPEG Converter */ #endif -#if defined(CONFIG_STM32F7_HAVE_CRYP) +#if defined(CONFIG_STM32_HAVE_CRYP) #define STM32_NCRYP 1 /* One CRYP engine */ #else #define STM32_NCRYP 0 /* No CRYP engine */ #endif -#if defined(CONFIG_STM32F7_HAVE_HASH) +#if defined(CONFIG_STM32_HAVE_HASH) #define STM32_NHASH 1 /* One HASH engine */ #else #define STM32_NHASH 0 /* No HASH engine */ diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h index 3c786310d68..c755977dfdc 100644 --- a/arch/arm/include/stm32f7/irq.h +++ b/arch/arm/include/stm32f7/irq.h @@ -69,11 +69,11 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include #else # error "Unsupported STM32 F7 chip" diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index e7e7126cd17..265a7421098 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -37,13 +37,13 @@ list( stm32_uid.c stm32_waste.c) -if(CONFIG_STM32F7_TICKLESS_TIMER) +if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32F7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -55,7 +55,7 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32F7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() @@ -66,11 +66,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32F7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) endif() -if(CONFIG_STM32F7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -83,27 +83,31 @@ if(CONFIG_STM32F7_RTC) endif() endif() -if(CONFIG_STM32F7_IWDG OR CONFIG_STM32F7_RTC_LSICLOCK) +if(CONFIG_STM32_FMC) + list(APPEND SRCS stm32_fmc.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32F7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32F7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32F7_I2S) +if(CONFIG_STM32_I2S) list(APPEND SRCS stm32_i2s.c) endif() -if(CONFIG_STM32F7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -120,19 +124,19 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32F7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32F7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32F7_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32F7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -140,19 +144,19 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32_dumpgpio.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32F7_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() -if(CONFIG_STM32F7_DMA2D) +if(CONFIG_STM32_DMA2D) list(APPEND SRCS stm32_dma2d.c) endif() @@ -160,19 +164,19 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32_qencoder.c) endif() -if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32F7_CAN_SOCKET) +if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_can_sock.c) endif() -if(CONFIG_STM32F7_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32_sai.c) endif() -if(CONFIG_STM32F7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -180,7 +184,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 825e55ef277..539914fbe7c 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -7,6 +7,49 @@ if ARCH_CHIP_STM32F7 comment "STM32 F7 Configuration Options" +config STM32_F7_PERIPHERALS + bool + default ARCH_CHIP_STM32F7 + select STM32_HAVE_ADC1 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHRNET + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 if !STM32_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_CEC + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_FLASH_ART_ACCELERATOR + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 F7 Chip Selection" default ARCH_CHIP_STM32F746NG @@ -14,7494 +57,1150 @@ choice config ARCH_CHIP_STM32F722RC bool "STM32F722RC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722RE bool "STM32F722RE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VC bool "STM32F722VC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722VE bool "STM32F722VE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZC bool "STM32F722ZC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722ZE bool "STM32F722ZE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IC bool "STM32F722IC" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F722IE bool "STM32F722IE" - select STM32F7_STM32F722XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F722XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RC bool "STM32F723RC" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723RE bool "STM32F723RE" - select STM32F7_STM32F723XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_R ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VC bool "STM32F723VC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723VE bool "STM32F723VE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZC bool "STM32F723ZC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723ZE bool "STM32F723ZE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IC bool "STM32F723IC" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_C + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_C select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 256 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F723IE bool "STM32F723IE" - select STM32F7_STM32F723XX - select STM32F7_HAVE_INTERNAL_ULPI - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F723XX + select STM32_HAVE_INTERNAL_ULPI + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 256K (176+16+64) Kb SRAM config ARCH_CHIP_STM32F745VG bool "STM32F745VG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745VE bool "STM32F745VE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IG bool "STM32F745IG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745IE bool "STM32F745IE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZE bool "STM32F745ZE" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F745ZG bool "STM32F745ZG" - select STM32F7_STM32F745XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F745XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BG bool "STM32F746BG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VG bool "STM32F746VG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746VE bool "STM32F746VE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746BE bool "STM32F746BE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZG bool "STM32F746ZG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IE bool "STM32F746IE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NG bool "STM32F746NG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746NE bool "STM32F746NE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746ZE bool "STM32F746ZE" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_E + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_E select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 512 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F746IG bool "STM32F746IG" - select STM32F7_STM32F746XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F746XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756NG bool "STM32F756NG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756BG bool "STM32F756BG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756IG bool "STM32F756IG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756VG bool "STM32F756VG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F756ZG bool "STM32F756ZG" - select STM32F7_STM32F756XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F756XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 320K (240+16+64) Kb SRAM config ARCH_CHIP_STM32F765NI bool "STM32F765NI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VI bool "STM32F765VI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765VG bool "STM32F765VG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BI bool "STM32F765BI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765NG bool "STM32F765NG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZG bool "STM32F765ZG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765ZI bool "STM32F765ZI" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765IG bool "STM32F765IG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765BG bool "STM32F765BG" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F765II bool "STM32F765II" - select STM32F7_STM32F765XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F765XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NG bool "STM32F767NG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767IG bool "STM32F767IG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VG bool "STM32F767VG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZG bool "STM32F767ZG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767NI bool "STM32F767NI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767VI bool "STM32F767VI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767BG bool "STM32F767BG" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767ZI bool "STM32F767ZI" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F767II bool "STM32F767II" - select STM32F7_STM32F767XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F767XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BI bool "STM32F769BI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769II bool "STM32F769II" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769BG bool "STM32F769BG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NI bool "STM32F769NI" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769AI bool "STM32F769AI" - select STM32F7_STM32F769AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F769AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769NG bool "STM32F769NG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F769IG bool "STM32F769IG" - select STM32F7_STM32F769XX - select STM32F7_FLASH_CONFIG_G + select STM32_STM32F769XX + select STM32_FLASH_CONFIG_G select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 1024 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777ZI bool "STM32F777ZI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_Z ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777VI bool "STM32F777VI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_V ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777NI bool "STM32F777NI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777BI bool "STM32F777BI" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F777II bool "STM32F777II" - select STM32F7_STM32F777XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F777XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F778AI bool "STM32F778AI" - select STM32F7_STM32F778AX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F778AX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779II bool "STM32F779II" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_I ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779NI bool "STM32F779NI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_N ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779BI bool "STM32F779BI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_B ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM config ARCH_CHIP_STM32F779AI bool "STM32F779AI" - select STM32F7_STM32F779XX - select STM32F7_FLASH_CONFIG_I + select STM32_STM32F779XX + select STM32_FLASH_CONFIG_I select STM32F7_IO_CONFIG_A ---help--- STM32 F7 Cortex M7, 2048 FLASH, 512K (368+16+128) Kb SRAM endchoice # STM32 F7 Chip Selection -config STM32F7_STM32F72XX +config STM32_STM32F72XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F73XX +config STM32_STM32F73XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F74XX +config STM32_STM32F74XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F75XX +config STM32_STM32F75XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F76XX +config STM32_STM32F76XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 -config STM32F7_STM32F77XX +config STM32_STM32F77XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 config STM32F7_IO_CONFIG_R + # Package designator R bool default n config STM32F7_IO_CONFIG_V + # Package designator V bool default n config STM32F7_IO_CONFIG_I + # Package designator I bool default n config STM32F7_IO_CONFIG_Z + # Package designator Z bool default n config STM32F7_IO_CONFIG_N + # Package designator N bool default n config STM32F7_IO_CONFIG_B + # Package designator B bool default n config STM32F7_IO_CONFIG_A + # Package designator A bool default n -config STM32F7_STM32F722XX +config STM32_STM32F722XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_EXTERNAL_ULPI + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_EXTERNAL_ULPI -config STM32F7_STM32F723XX +config STM32_STM32F723XX bool default n - select STM32F7_STM32F72XX + select STM32_STM32F72XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI4 if !STM32F7_IO_CONFIG_R - select STM32F7_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI4 if !STM32F7_IO_CONFIG_R + select STM32_HAVE_SPI5 if !(STM32F7_IO_CONFIG_R || STM32F7_IO_CONFIG_V) + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_R -config STM32F7_STM32F745XX +config STM32_STM32F745XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F746XX +config STM32_STM32F746XX bool default n - select STM32F7_STM32F74XX + select STM32_STM32F74XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - select STM32F7_HAVE_EXTERNAL_ULPI - select STM32F7_HAVE_SAI1 - select STM32F7_HAVE_SAI2 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_DCMI + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 + select STM32_HAVE_EXTERNAL_ULPI + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 -config STM32F7_STM32F756XX +config STM32_STM32F756XX bool default n - select STM32F7_STM32F75XX + select STM32_STM32F75XX select ARCH_HAVE_FPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F765XX +config STM32_STM32F765XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG # data sheet says yes, Product matrix says no - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG # data sheet says yes, Product matrix says no + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F767XX +config STM32_STM32F767XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F768XX # Revisit When parts released +config STM32_STM32F768XX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F768AX # Revisit When parts released +config STM32_STM32F768AX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F769XX +config STM32_STM32F769XX bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F769AX # Revisit When parts released +config STM32_STM32F769AX # Revisit When parts released bool default n - select STM32F7_STM32F76XX + select STM32_STM32F76XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F777XX +config STM32_STM32F777XX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F778XX # Revisit when parts released +config STM32_STM32F778XX # Revisit when parts released bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F778AX +config STM32_STM32F778AX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 - select STM32F7_HAVE_SPI6 - select STM32F7_HAVE_SDMMC2 - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F779XX +config STM32_STM32F779XX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_ETHRNET - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 + select STM32_HAVE_FMC + select STM32_HAVE_ETHRNET + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 -config STM32F7_STM32F779AX +config STM32_STM32F779AX bool default n - select STM32F7_STM32F77XX + select STM32_STM32F77XX select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARMV7M_HAVE_ICACHE select ARMV7M_HAVE_DCACHE select ARMV7M_HAVE_ITCM select ARMV7M_HAVE_DTCM - select STM32F7_HAVE_FMC - select STM32F7_HAVE_RNG - select STM32F7_HAVE_SPI5 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SPI6 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V - select STM32F7_HAVE_CAN3 - select STM32F7_HAVE_DCMI - select STM32F7_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) - select STM32F7_HAVE_LTDC - select STM32F7_HAVE_DMA2D - select STM32F7_HAVE_JPEG - select STM32F7_HAVE_CRYP - select STM32F7_HAVE_HASH - select STM32F7_HAVE_DFSDM1 - select STM32F7_HAVE_CAN2 - select STM32F7_HAVE_SPI4 - -config STM32F7_FLASH_CONFIG_E - bool - default n - -config STM32F7_FLASH_CONFIG_G - bool - default n - -config STM32F7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32F7 - default STM32F7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32F7 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32F745VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32F7xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32F7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32F7_FLASH_OVERRIDE_C - bool "C 256KiB" - -config STM32F7_FLASH_OVERRIDE_E - bool "E 512KiB" - -config STM32F7_FLASH_OVERRIDE_G - bool "G 1024KiB" - -config STM32F7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32F7_FLASH_ART_ACCELERATOR - bool "Flash ART Accelerator" - default n - ---help--- - ART Accelerator on the flash memory ITCM interface accelerates code execution - with a system of instruction prefetch and cache lines. - - Enable if code and/or read-only data is accessed through ITCM bus instead of - AXIM bus. - -config STM32F7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - -menu "STM32 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_FMC - bool - default n - -config STM32F7_HAVE_ETHRNET - bool - default n - -config STM32F7_HAVE_PHY_POLLED - bool - default n - -config STM32F7_HAVE_RNG - bool - default n - -config STM32F7_HAVE_SPI4 - bool - default n - -config STM32F7_HAVE_SPI5 - bool - default n - -config STM32F7_HAVE_SPI6 - bool - default n - -config STM32F7_HAVE_SDMMC2 - bool - default n - -config STM32F7_HAVE_ADC1_DMA - bool - default n - -config STM32F7_HAVE_ADC2_DMA - bool - default n - -config STM32F7_HAVE_ADC3_DMA - bool - default n - -config STM32F7_HAVE_CAN2 - bool - default n - -config STM32F7_HAVE_CAN3 - bool - default n - -config STM32F7_HAVE_DCMI - bool - default n - -config STM32F7_HAVE_DSIHOST - bool - default n - -config STM32F7_HAVE_LTDC - bool - default n - -config STM32F7_HAVE_DMA2D - bool - default n - -config STM32F7_HAVE_JPEG - bool - default n - -config STM32F7_HAVE_CRYP - bool - default n - -config STM32F7_HAVE_HASH - bool - default n - -config STM32F7_HAVE_DFSDM1 - bool - default n - -config STM32F7_HAVE_INTERNAL_ULPI - bool - default n - -config STM32F7_HAVE_EXTERNAL_ULPI - bool - default n - -config STM32F7_I2S - bool - default n - select STM32F7_SPI_DMA - -config STM32F7_HAVE_SAI1 - bool - default n - -config STM32F7_HAVE_SAI2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32F7_ADC - bool - default n - -config STM32F7_CAN - bool - default n - -config STM32F7_DAC - bool - default n - -config STM32F7_DMA - bool - default n - -config STM32F7_I2C - bool - default n - -config STM32F7_SAI - bool - default n - -config STM32F7_SDMMC - bool - default n - -config STM32F7_SPI - bool - default n - -config STM32F7_SPI_DMA - bool - default n - -config STM32F7_TIM - bool - default n - -config STM32F7_PWM - bool - default n - -config STM32F7_USART - bool - default n - -# These are the peripheral selections proper - -config STM32F7_ADC1 - bool "ADC1" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC1_DMA if STM32F7_DMA2 - -config STM32F7_ADC2 - bool "ADC2" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC2_DMA if STM32F7_DMA2 - -config STM32F7_ADC3 - bool "ADC3" - default n - select STM32F7_ADC - select STM32F7_HAVE_ADC3_DMA if STM32F7_DMA2 - -config STM32F7_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32F7_CAN1 - bool "CAN1" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN2 - bool "CAN2" - default n - select CAN - select STM32F7_CAN - -config STM32F7_CAN3 - bool "CAN3" - default n - select CAN - select STM32F7_CAN - depends on STM32F7_HAVE_CAN3 - -config STM32F7_CEC - bool "CEC" - default n - depends on STM32F7_VALUELINE - -config STM32F7_CRC - bool "CRC" - default n - -config STM32F7_CRYP - bool "CRYP" - depends on STM32F7_HAVE_CRYP - default n - -config STM32F7_DFSDM1 - bool "DFSDM1" - default n - depends on STM32F7_HAVE_DFSDM1 - select ARCH_HAVE_DFSDM1 - -config STM32F7_DMA1 - bool "DMA1" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DMA2 - bool "DMA2" - default n - select STM32F7_DMA - select ARCH_DMA - -config STM32F7_DAC1 - bool "DAC1" - default n - select STM32F7_DAC - -config STM32F7_DAC2 - bool "DAC2" - default n - select STM32F7_DAC - -config STM32F7_DCMI - bool "DCMI" - default n - depends on STM32F7_HAVE_DCMI - ---help--- - The devices embed a camera interface that can connect with camera - modules and CMOS sensors through an 8-bit to 14-bit parallel interface, - to receive video data. - -config STM32F7_DSIHOST - bool "DSIHOST" - default n - depends on STM32F7_HAVE_DSIHOST - ---help--- - The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI - compliant displays. - -config STM32F7_DMA2D - bool "DMA2D" - default n - select FB - select FB_OVERLAY - depends on STM32F7_HAVE_DMA2D - ---help--- - The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation - available on the STM32 F7 devices. - -config STM32F7_JPEG - bool "JPEG" - default n - depends on STM32F7_HAVE_JPEG - ---help--- - The JPEG codec provides an fast and simple hardware compressor and - decompressor of JPEG images with full management of JPEG headers. - -config STM32F7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32F7_HAVE_ETHRNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32F7_HAVE_PHY_POLLED - -config STM32F7_FMC - bool "FMC" - depends on STM32F7_HAVE_FMC - default n - -config STM32F7_HASH - bool "HASH" - default n - depends on STM32F7_HAVE_HASH - select ARCH_HAVE_HASH - -config STM32F7_CEC - bool "HDMI-CEC" - default n - -config STM32F7_I2C1 - bool "I2C1" - default n - select STM32F7_I2C - -config STM32F7_I2C2 - bool "I2C2" - default n - select STM32F7_I2C - -config STM32F7_I2C3 - bool "I2C3" - default n - select STM32F7_I2C - -config STM32F7_I2C4 - bool "I2C4" - default n - select STM32F7_I2C - -config STM32F7_LPTIM1 - bool "Low-power timer 1" - default n - -config STM32F7_LTDC - bool "LTDC" - default n - select FB - depends on STM32F7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32F7x6, STM32F7x7, STM32F7x8 and STM32F7x9 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - With the STM32F7x8/9, the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32F7_DSIHOST and STM32F7_LTDC_USE_DSI. - -config STM32F7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_OTGFSHS - bool "OTG FS/HS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32F7_QSPI - bool "QuadSPI" - default n - -config STM32F7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32F7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32F7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32F7_RTC - bool "RTC" - default n - select RTC - -config STM32F7_PWR - bool "PWR" - default n - -config STM32F7_RNG - bool "RNG" - default n - depends on STM32F7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32F7_I2S1 - bool "I2S1" - default n - depends on !STM32F7_SPI1 - select STM32F7_I2S - -config STM32F7_I2S2 - bool "I2S2" - default n - depends on !STM32F7_SPI2 - select STM32F7_I2S - -config STM32F7_I2S3 - bool "I2S3" - default n - depends on !STM32F7_SPI3 - select STM32F7_I2S - -config STM32F7_SAI1 - bool "SAI1" - default n - depends on STM32F7_HAVE_SAI1 - -config STM32F7_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI1 - -config STM32F7_SAI2 - bool "SAI2" - default n - select STM32F7_HAVE_SAI2 - -config STM32F7_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32F7_SAI - depends on STM32F7_SAI2 - -config STM32F7_SDMMC1 - bool "SDMMC1" - default n - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SDMMC2 - bool "SDMMC2" - default n - depends on STM32F7_HAVE_SDMMC2 - select STM32F7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32F7_SPDIFRX - bool "SPDIFRX" - default n - -config STM32F7_SPI1 - bool "SPI1" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI2 - bool "SPI2" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI3 - bool "SPI3" - default n - select SPI - select STM32F7_SPI - -config STM32F7_SPI4 - bool "SPI4" - default n - depends on STM32F7_HAVE_SPI4 - select SPI - select STM32F7_SPI - -config STM32F7_SPI5 - bool "SPI5" - default n - depends on STM32F7_HAVE_SPI5 - select SPI - select STM32F7_SPI - -config STM32F7_SPI6 - bool "SPI6" - default n - depends on STM32F7_HAVE_SPI6 - select SPI - select STM32F7_SPI - -config STM32F7_SYSCFG - bool "SYSCFG" - default y - -config STM32F7_TIM1 - bool "TIM1" - default n - select STM32F7_TIM - -config STM32F7_TIM2 - bool "TIM2" - default n - select STM32F7_TIM - -config STM32F7_TIM3 - bool "TIM3" - default n - select STM32F7_TIM - -config STM32F7_TIM4 - bool "TIM4" - default n - select STM32F7_TIM - -config STM32F7_TIM5 - bool "TIM5" - default n - select STM32F7_TIM - -config STM32F7_TIM6 - bool "TIM6" - default n - select STM32F7_TIM - -config STM32F7_TIM7 - bool "TIM7" - default n - select STM32F7_TIM - -config STM32F7_TIM8 - bool "TIM8" - default n - select STM32F7_TIM - -config STM32F7_TIM9 - bool "TIM9" - default n - select STM32F7_TIM - -config STM32F7_TIM10 - bool "TIM10" - default n - select STM32F7_TIM - -config STM32F7_TIM11 - bool "TIM11" - default n - select STM32F7_TIM - -config STM32F7_TIM12 - bool "TIM12" - default n - select STM32F7_TIM - -config STM32F7_TIM13 - bool "TIM13" - default n - select STM32F7_TIM - -config STM32F7_TIM14 - bool "TIM14" - default n - select STM32F7_TIM - -config STM32F7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32F7_USART - -config STM32F7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32F7_USART - -config STM32F7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32F7_USART - -config STM32F7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32F7_USART - -config STM32F7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32F7_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32F7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V. - -menu "OTG Configuration" - depends on STM32F7_OTGFS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -endmenu - -menu "U[S]ART Configuration" - depends on STM32F7_USART - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32F7_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_TXDMA - bool "USART1 Tx DMA" - default n - depends on STM32F7_USART1 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32F7_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_TXDMA - bool "USART2 Tx DMA" - default n - depends on STM32F7_USART2 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32F7_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_TXDMA - bool "USART3 Tx DMA" - default n - depends on STM32F7_USART3 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32F7_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_TXDMA - bool "UART4 Tx DMA" - default n - depends on STM32F7_UART4 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32F7_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_TXDMA - bool "UART5 Tx DMA" - default n - depends on STM32F7_UART5 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32F7_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 Rx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_TXDMA - bool "USART6 Tx DMA" - default n - depends on STM32F7_USART6 && STM32F7_DMA2 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32F7_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 Rx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_TXDMA - bool "UART7 Tx DMA" - default n - depends on STM32F7_UART7 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32F7_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 Rx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_TXDMA - bool "UART8 Tx DMA" - default n - depends on STM32F7_UART8 && STM32F7_DMA1 - ---help--- - In high data rate usage, Rx DMA may reduce CPU Load - -config STM32F7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32F7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32F7_USART1 || STM32F7_USART2 || STM32F7_USART3 || STM32F7_UART4 || STM32F7_UART5 || STM32F7_USART6 || STM32F7_UART7 || STM32F7_UART8 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32F7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32F7_USART && SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32F7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32F7_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32F7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32F7_USART && STM32F7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32F7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32F7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32F7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32F7 serial driver. - -config STM32F7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32F7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32F7 serial driver. - -config STM32F7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32F7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32F7 serial driver. - -if PM - -config STM32F7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endmenu # U[S]ART Configuration - -menu "STM32F7_OTG_HS Configuration" - depends on STM32F7_OTGFSHS - -choice - prompt "ULPI Selection" - default STM32F7_NO_ULPI - -config STM32F7_NO_ULPI - bool "No External ULPI" - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_EXTERNAL_ULPI - bool "External ULPI" - depends on STM32F7_HAVE_EXTERNAL_ULPI - ---help--- - Select to enable the presence of an external ULPI PHY - -config STM32F7_INTERNAL_ULPI - bool "Internal ULPI PHY" - depends on STM32F7_HAVE_INTERNAL_ULPI - ---help--- - Select to enable the internal ULPI for USB HS -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -config STM32F7_EXTERNAL_RAM - bool "External RAM on FMC" - default n - depends on STM32F7_FMC - select ARCH_HAVE_HEAP2 - ---help--- - In addition to internal SDRAM, external RAM may be available through the FMC. - -menu "QuadSPI Configuration" - depends on STM32F7_QSPI - -config STM32F7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32F7 QSPI peripheral requires the size of the Flash be specified - -config STM32F7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32F7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32F7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32F7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32F7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32F7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32F7_QSPI_DMA - bool "DMA" - depends on STM32F7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32F7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32F7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32F7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32F7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32F7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32F7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32F7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32F7_DMA - ---help--- - 'Highest' priority. - -config STM32F7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32F7_DMA - ---help--- - 'High' priority. - -config STM32F7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32F7_DMA - ---help--- - 'Medium' priority. - -config STM32F7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32F7_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32F7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32F7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32F7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32F7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32F7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - -menu "SPI Configuration" - depends on STM32F7_SPI - -config STM32F7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32F7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32F7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32F7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32F7_SPI1 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32F7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32F7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32F7_SPI2 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32F7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32F7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32F7_SPI3 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32F7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32F7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32F7_SPI4 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32F7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32F7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32F7_SPI5 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32F7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32F7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32F7_SPI6 && !STM32F7_SPI_INTERRUPT - select STM32F7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT. - -config STM32F7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32F7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -endmenu # "SPI Configuration" - -menu "I2S Configuration" - depends on STM32F7_I2S - -config STM32F7_I2S_MAXINFLIGHT - int "I2S queue size" - default 16 - ---help--- - This is the total number of transfers, both RX and TX, that can be - enqueue before the caller is required to wait. This setting - determines the number certain queue data structures that will be - pre-allocated. - -if STM32F7_I2S1 - -comment "I2S1 Configuration" - -config STM32F7_I2S1_MCK - bool "I2S1_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S1_RX - bool "Enable I2S1 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S1_TX - bool "Enable I2S1 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S1_DATALEN - int "I2S1 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S1 - -if STM32F7_I2S2 - -comment "I2S2 Configuration" - -config STM32F7_I2S2_MCK - bool "I2S2_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S2_RX - bool "Enable I2S2 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S2_TX - bool "Enable I2S2 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32F7_I2S2_DATALEN - int "I2S2 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S2 - -if STM32F7_I2S3 - -comment "I2S3 Configuration" - -config STM32F7_I2S3_MCK - bool "I2S3_MCK" - default n - ---help--- - TBD. - -config STM32F7_I2S3_RX - bool "Enable I2S3 receiver" - default n - ---help--- - Enable I2S receipt logic - -config STM32F7_I2S3_TX - bool "Enable I2S3 transmitter" - default n - ---help--- - Enable I2S transmission logic - -config STM32_I2S3_DATALEN - int "I2S3 Data width (bits)" - default 16 - ---help--- - Data width in bits. This is a default value and may be change - via the I2S interface - -endif #STM32F7_I2S3 - -config STM32F7_I2S_DMADEBUG - bool "I2S DMA transfer debug" - depends on DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation analyze I2S DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32_I2S_REGDEBUG - bool "SSC Register level debug" - depends on DEBUG - default n - ---help--- - Output detailed register-level SSC device debug information. - Very invasive! Requires also DEBUG. - -endmenu # I2S Configuration - -menu "I2C Configuration" - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32F7_I2C - -config STM32F7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32F7_I2C - -config STM32F7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -config STM32F7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32F7_I2C && !STM32F7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "SD/MMC Configuration" - depends on STM32F7_SDMMC - -config STM32F7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32F7_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32F7_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32F7_SDMMC1 - -config STM32F7_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32F7_SDMMC2 - -config STM32F7_SDMMC2_DMAPRIO - hex "SDMMC2 DMA priority" - default 0x00010000 - ---help--- - Select SDMMC2 DMA priority. - - Options are: 0x00000000 low, 0x00010000 medium, - 0x00020000 high, 0x00030000 very high. Default: medium. - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32F7_BKPSRAM - -config STM32F7_BBSRAM - bool "BBSRAM File Support" - default n - -config STM32F7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32F7_BBSRAM - -config STM32F7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32F7_BBSRAM - -endif # STM32F7_BKPSRAM - -config STM32F7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32F7_RTC - -config STM32F7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32F7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32F7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32F7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32F7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32F7_RTC_LSECLOCK - -config STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -config STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium high drive capability - 2 = Medium low drive capability - 3 = High drive capability - -endif # STM32F7_RTC_LSECLOCK - -endmenu # RTC Configuration - -config STM32F7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32F7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32F7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32F7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32F7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32F7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 14 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32F7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32F7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32F7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32F7_TIM1 - select STM32F7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM1_PWM - -config STM32F7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32F7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32F7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL1 - -config STM32F7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL2 - -config STM32F7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL3 - -config STM32F7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL4 - -config STM32F7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM1_CHANNEL5 - -config STM32F7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM1_CHANNEL6 - -config STM32F7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM1_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM1_CHANNEL = 1 - -config STM32F7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 1 - -if STM32F7_TIM1_CHANNEL = 2 - -config STM32F7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 2 - -if STM32F7_TIM1_CHANNEL = 3 - -config STM32F7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM1_CHANNEL = 3 - -if STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM1_CHANNEL = 4 - -config STM32F7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM1_PWM - -config STM32F7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32F7_TIM2 - select STM32F7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM2_PWM - -config STM32F7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL1 - -config STM32F7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL2 - -config STM32F7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL3 - -config STM32F7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM2_CHANNEL4 - -config STM32F7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM2_CHANNEL = 1 - -config STM32F7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM2_CHANNEL = 1 - -if STM32F7_TIM2_CHANNEL = 2 - -config STM32F7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM2_CHANNEL = 2 - -if STM32F7_TIM2_CHANNEL = 3 - -config STM32F7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM2_CHANNEL = 3 - -if STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM2_CHANNEL = 4 - -config STM32F7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM2_PWM - -config STM32F7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32F7_TIM3 - select STM32F7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM3_PWM - -config STM32F7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL1 - -config STM32F7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL2 - -config STM32F7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL3 - -config STM32F7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM3_CHANNEL4 - -config STM32F7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM3_CHANNEL = 1 - -config STM32F7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM3_CHANNEL = 1 - -if STM32F7_TIM3_CHANNEL = 2 - -config STM32F7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM3_CHANNEL = 2 - -if STM32F7_TIM3_CHANNEL = 3 - -config STM32F7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM3_CHANNEL = 3 - -if STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM3_CHANNEL = 4 - -config STM32F7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM3_PWM - -config STM32F7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32F7_TIM4 - select STM32F7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM4_PWM - -config STM32F7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL1 - -config STM32F7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL2 - -config STM32F7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL3 - -config STM32F7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM4_CHANNEL4 - -config STM32F7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM4_CHANNEL = 1 - -config STM32F7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM4_CHANNEL = 1 - -if STM32F7_TIM4_CHANNEL = 2 - -config STM32F7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM4_CHANNEL = 2 - -if STM32F7_TIM4_CHANNEL = 3 - -config STM32F7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM4_CHANNEL = 3 - -if STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM4_CHANNEL = 4 - -config STM32F7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM4_PWM - -config STM32F7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32F7_TIM5 - select STM32F7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM5_PWM - -config STM32F7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL1 - -config STM32F7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL2 - -config STM32F7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL3 - -config STM32F7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM5_CHANNEL4 - -config STM32F7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL4 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM5_CHANNEL = 1 - -config STM32F7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM5_CHANNEL = 1 - -if STM32F7_TIM5_CHANNEL = 2 - -config STM32F7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM5_CHANNEL = 2 - -if STM32F7_TIM5_CHANNEL = 3 - -config STM32F7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32F7_TIM5_CHANNEL = 3 - -if STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM5_CHANNEL = 4 - -config STM32F7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM5_PWM - -config STM32F7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32F7_TIM8 - select STM32F7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM8_PWM - -config STM32F7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32F7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32F7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32F7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL1 - -config STM32F7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL2 - -config STM32F7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL3 - -config STM32F7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL4 - -config STM32F7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32F7_TIM8_CHANNEL5 - -config STM32F7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32F7_TIM8_CHANNEL6 - -config STM32F7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32F7_TIM8_CHANNEL6 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32F7_TIM8_CHANNEL = 1 - -config STM32F7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32F7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 1 - -if STM32F7_TIM8_CHANNEL = 2 - -config STM32F7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32F7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 2 - -if STM32F7_TIM8_CHANNEL = 3 - -config STM32F7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32F7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32F7_TIM8_CHANNEL = 3 - -if STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32F7_TIM8_CHANNEL = 4 - -config STM32F7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM8_PWM - -config STM32F7_TIM9_PWM - bool "TIM9 PWM" - default n - depends on STM32F7_TIM9 - select STM32F7_PWM - ---help--- - Reserve timer 9 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM9 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM9_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL1 - bool "TIM9 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CH1MODE - int "TIM9 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL1 - -config STM32F7_TIM9_CHANNEL2 - bool "TIM9 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM9_CHANNEL2 - -config STM32F7_TIM9_CH2MODE - int "TIM9 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM9_CHANNEL - int "TIM9 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM9 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM9_CHANNEL = 1 - -config STM32F7_TIM9_CH1OUT - bool "TIM9 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM9_CHANNEL = 1 - -if STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CH2OUT - bool "TIM9 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM9_CHANNEL = 2 - -config STM32F7_TIM9_CHMODE - int "TIM9 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM9_PWM - -config STM32F7_TIM10_PWM - bool "TIM10 PWM" - default n - depends on STM32F7_TIM10 - select STM32F7_PWM - ---help--- - Reserve timer 10 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM10 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM10_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL1 - bool "TIM10 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM10_CHANNEL1 - -config STM32F7_TIM10_CH1MODE - int "TIM10 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM10_CHANNEL - int "TIM10 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM10 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CH1OUT - bool "TIM10 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM10_CHANNEL = 1 - -config STM32F7_TIM10_CHMODE - int "TIM10 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM10_PWM - -config STM32F7_TIM11_PWM - bool "TIM11 PWM" - default n - depends on STM32F7_TIM11 - select STM32F7_PWM - ---help--- - Reserve timer 11 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM11 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM11_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL1 - bool "TIM11 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM11_CHANNEL1 - -config STM32F7_TIM11_CH1MODE - int "TIM11 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM11_CHANNEL - int "TIM11 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM11 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CH1OUT - bool "TIM11 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM11_CHANNEL = 1 - -config STM32F7_TIM11_CHMODE - int "TIM11 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM11_PWM - -config STM32F7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32F7_TIM12 - select STM32F7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM12_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL1 - -config STM32F7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM12_CHANNEL2 - -config STM32F7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32F7_TIM12_CHANNEL = 1 - -config STM32F7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM12_CHANNEL = 1 - -if STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM12_CHANNEL = 2 - -config STM32F7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM12_PWM - -config STM32F7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32F7_TIM13 - select STM32F7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM13_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM13_CHANNEL1 - -config STM32F7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM13_CHANNEL = 1 - -config STM32F7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM13_PWM - -config STM32F7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32F7_TIM14 - select STM32F7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM14_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM14_CHANNEL1 - -config STM32F7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM14_CHANNEL = 1 - -config STM32F7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM14_PWM - -config STM32F7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32F7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32F7_PWM_TRGO - bool "TIM PWM TRGO support" - default n - depends on STM32F7_PWM - ---help--- - Enable TRGO support for PWM driver - -config STM32F7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32F7_TIM1 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM1_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32F7_TIM8 - select STM32F7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32F7_TIM8_PULSECOUNT - -config STM32F7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32F7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32F7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32F7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32F7_TIM8_PULSECOUNT -config STM32F7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32F7_TIM1 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32F7_TIM1_ADC1 - depends on STM32F7_TIM1_ADC - -config STM32F7_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32F7_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32F7_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32F7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32F7_TIM2 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32F7_TIM2_ADC1 - depends on STM32F7_TIM2_ADC - -config STM32F7_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32F7_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32F7_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32F7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32F7_TIM3 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32F7_TIM3_ADC1 - depends on STM32F7_TIM3_ADC - -config STM32F7_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32F7_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32F7_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32F7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32F7_TIM4 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32F7_TIM4_ADC1 - depends on STM32F7_TIM4_ADC - -config STM32F7_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32F7_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32F7_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32F7_TIM5_ADC - bool "TIM5 ADC" - default n - depends on STM32F7_TIM5 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM5 ADC channel" - default STM32F7_TIM5_ADC1 - depends on STM32F7_TIM5_ADC - -config STM32F7_TIM5_ADC1 - bool "TIM5 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM5 to trigger ADC1 - -config STM32F7_TIM5_ADC2 - bool "TIM5 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM5 to trigger ADC2 - -config STM32F7_TIM5_ADC3 - bool "TIM5 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM5 to trigger ADC3 - -endchoice - -config STM32F7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32F7_TIM8 && STM32F7_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32F7_TIM8_ADC1 - depends on STM32F7_TIM8_ADC - -config STM32F7_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32F7_ADC1 - select STM32F7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32F7_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32F7_ADC2 - select STM32F7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32F7_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32F7_ADC3 - select STM32F7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32F7_HAVE_ADC1_TIMER - bool - -config STM32F7_HAVE_ADC2_TIMER - bool - -config STM32F7_HAVE_ADC3_TIMER - bool - -config STM32F7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32F7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32F7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32F7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 5 - depends on STM32F7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32F7_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32F7_TIM1 && STM32F7_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32F7_TIM1_DAC1 - depends on STM32F7_TIM1_DAC - -config STM32F7_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32F7_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32F7_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32F7_TIM2 && STM32F7_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32F7_TIM2_DAC1 - depends on STM32F7_TIM2_DAC - -config STM32F7_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32F7_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32F7_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32F7_TIM3 && STM32F7_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32F7_TIM3_DAC1 - depends on STM32F7_TIM3_DAC - -config STM32F7_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32F7_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32F7_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32F7_TIM4 && STM32F7_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32F7_TIM4_DAC1 - depends on STM32F7_TIM4_DAC - -config STM32F7_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32F7_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32F7_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32F7_TIM5 && STM32F7_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32F7_TIM5_DAC1 - depends on STM32F7_TIM5_DAC - -config STM32F7_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32F7_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32F7_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32F7_TIM6 && STM32F7_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32F7_TIM6_DAC1 - depends on STM32F7_TIM6_DAC - -config STM32F7_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32F7_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32F7_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32F7_TIM7 && STM32F7_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32F7_TIM7_DAC1 - depends on STM32F7_TIM7_DAC - -config STM32F7_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32F7_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32F7_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32F7_TIM8 && STM32F7_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32F7_TIM8_DAC1 - depends on STM32F7_TIM8_DAC - -config STM32F7_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32F7_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32F7_TIM9_DAC - bool "TIM9 DAC" - default n - depends on STM32F7_TIM9 && STM32F7_DAC - ---help--- - Reserve timer 9 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM9 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM9 DAC channel" - default STM32F7_TIM9_DAC1 - depends on STM32F7_TIM9_DAC - -config STM32F7_TIM9_DAC1 - bool "TIM9 DAC channel 1" - ---help--- - Reserve TIM9 to trigger DAC1 - -config STM32F7_TIM9_DAC2 - bool "TIM9 DAC channel 2" - ---help--- - Reserve TIM9 to trigger DAC2 - -endchoice - -config STM32F7_TIM10_DAC - bool "TIM10 DAC" - default n - depends on STM32F7_TIM10 && STM32F7_DAC - ---help--- - Reserve timer 10 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM10 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM10 DAC channel" - default STM32F7_TIM10_DAC1 - depends on STM32F7_TIM10_DAC - -config STM32F7_TIM10_DAC1 - bool "TIM10 DAC channel 1" - ---help--- - Reserve TIM10 to trigger DAC1 - -config STM32F7_TIM10_DAC2 - bool "TIM10 DAC channel 2" - ---help--- - Reserve TIM10 to trigger DAC2 - -endchoice - -config STM32F7_TIM11_DAC - bool "TIM11 DAC" - default n - depends on STM32F7_TIM11 && STM32F7_DAC - ---help--- - Reserve timer 11 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM11 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM11 DAC channel" - default STM32F7_TIM11_DAC1 - depends on STM32F7_TIM11_DAC - -config STM32F7_TIM11_DAC1 - bool "TIM11 DAC channel 1" - ---help--- - Reserve TIM11 to trigger DAC1 - -config STM32F7_TIM11_DAC2 - bool "TIM11 DAC channel 2" - ---help--- - Reserve TIM11 to trigger DAC2 - -endchoice - -config STM32F7_TIM12_DAC - bool "TIM12 DAC" - default n - depends on STM32F7_TIM12 && STM32F7_DAC - ---help--- - Reserve timer 12 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM12 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM12 DAC channel" - default STM32F7_TIM12_DAC1 - depends on STM32F7_TIM12_DAC - -config STM32F7_TIM12_DAC1 - bool "TIM12 DAC channel 1" - ---help--- - Reserve TIM12 to trigger DAC1 - -config STM32F7_TIM12_DAC2 - bool "TIM12 DAC channel 2" - ---help--- - Reserve TIM12 to trigger DAC2 - -endchoice - -config STM32F7_TIM13_DAC - bool "TIM13 DAC" - default n - depends on STM32F7_TIM13 && STM32F7_DAC - ---help--- - Reserve timer 13 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM13 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM13 DAC channel" - default STM32F7_TIM13_DAC1 - depends on STM32F7_TIM13_DAC - -config STM32F7_TIM13_DAC1 - bool "TIM13 DAC channel 1" - ---help--- - Reserve TIM13 to trigger DAC1 - -config STM32F7_TIM13_DAC2 - bool "TIM13 DAC channel 2" - ---help--- - Reserve TIM13 to trigger DAC2 - -endchoice - -config STM32F7_TIM14_DAC - bool "TIM14 DAC" - default n - depends on STM32F7_TIM14 && STM32F7_DAC - ---help--- - Reserve timer 14 for use by DAC - - Timer devices may be used for different purposes. If STM32F7_TIM14 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM14 DAC channel" - default STM32F7_TIM14_DAC1 - depends on STM32F7_TIM14_DAC - -config STM32F7_TIM14_DAC1 - bool "TIM14 DAC channel 1" - ---help--- - Reserve TIM14 to trigger DAC1 - -config STM32F7_TIM14_DAC2 - bool "TIM14 DAC channel 2" - ---help--- - Reserve TIM14 to trigger DAC2 - -endchoice - -config STM32F7_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM9_CAP - bool "TIM9 Capture" - default n - depends on STM32F7_TIM9 - ---help--- - Reserve timer 9 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM10_CAP - bool "TIM10 Capture" - default n - depends on STM32F7_TIM10 - ---help--- - Reserve timer 10 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM11_CAP - bool "TIM11 Capture" - default n - depends on STM32F7_TIM11 - ---help--- - Reserve timer 11 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32F7_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32F7_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32F7_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32F7_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32F7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32F7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32F7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32F7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32F7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32F7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32F7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32F7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32F7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32F7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32F7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32F7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32F7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32F7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32F7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32F7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32F7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32F7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32F7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32F7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32F7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32F7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32F7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32F7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32F7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32F7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32F7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32F7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32F7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32F7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32F7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32F7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32F7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32F7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32F7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32F7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32F7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32F7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32F7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32F7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32F7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32F7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32F7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32F7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32F7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32F7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32F7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32F7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32F7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32F7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32F7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32F7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32F7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32F7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32F7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32F7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32F7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32F7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32F7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32F7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32F7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32F7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32F7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32F7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32F7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32F7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32F7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32F7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32F7_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32F7_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32F7_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32F7_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32F7_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32F7_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32F7_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32F7_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32F7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32F7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32F7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32F7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32F7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32F7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32F7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32F7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32F7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "CAN driver configuration" - depends on STM32F7_CAN - -choice - prompt "CAN character driver or SocketCAN support" - default STM32F7_CAN_CHARDRIVER - -config STM32F7_CAN_CHARDRIVER - bool "STM32F7 CAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32F7_CAN_SOCKET - bool "STM32F7 CAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - -endchoice # CAN character driver or SocketCAN support - -config STM32F7_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32F7_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined. - -config STM32F7_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32F7_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN3_BAUD - int "CAN3 BAUD" - default 250000 - depends on STM32F7_CAN3 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined. - -config STM32F7_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32F7_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32F7_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "ADC Configuration" - depends on STM32F7_ADC - -config STM32F7_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32F7_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32F7_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32F7_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32F7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32F7_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32F7_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32F7_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32F7_ADC_CHANGE_SAMPLETIME - bool "ADC sample time configuration" - default n - depends on STM32F7_ADC_LL_OPS - ---help--- - Enable ADC sample time configuration (SMPRx registers). - -config STM32F7_ADC1_DMA - bool "ADC1 DMA" - depends on STM32F7_ADC1 && STM32F7_HAVE_ADC1_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC1_SCAN - bool "ADC1 scan mode" - depends on STM32F7_ADC1 - default STM32F7_ADC1_DMA - default n - -config STM32F7_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32F7_ADC1_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32F7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32F7_ADC1 && STM32F7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC1_ANIOC_TRIGGER - int "ADC1 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC1 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC2_DMA - bool "ADC2 DMA" - depends on STM32F7_ADC2 && STM32F7_HAVE_ADC2_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC2_SCAN - bool "ADC2 scan mode" - depends on STM32F7_ADC2 - default STM32F7_ADC2_DMA - -config STM32F7_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32F7_ADC2_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32F7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32F7_ADC2 && STM32F7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC2_ANIOC_TRIGGER - int "ADC2 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC2 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC3_DMA - bool "ADC3 DMA" - depends on STM32F7_ADC3 && STM32F7_HAVE_ADC3_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32F7_ADC3_SCAN - bool "ADC3 scan mode" - depends on STM32F7_ADC3 - default STM32F7_ADC3_DMA - -config STM32F7_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32F7_ADC3_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32F7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32F7_ADC3 && STM32F7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32F7_ADC3_ANIOC_TRIGGER - int "ADC3 software trigger (ANIOC_TRIGGER) configuration" - depends on STM32F7_ADC3 - range 1 3 - default 3 - ---help--- - 1 - ANIOC_TRIGGER only starts regular conversion - 2 - ANIOC_TRIGGER only starts injected conversion - 3 - ANIOC_TRIGGER starts both regular and injected conversions - -config STM32F7_ADC1_INJECTED_CHAN - int "ADC1 injected channels" - depends on STM32F7_ADC1 - range 0 4 - default 0 - ---help--- - Support for ADC1 injected channels. - -config STM32F7_ADC2_INJECTED_CHAN - int "ADC2 injected channels" - depends on STM32F7_ADC2 - range 0 4 - default 0 - ---help--- - Support for ADC2 injected channels. - -config STM32F7_ADC3_INJECTED_CHAN - int "ADC3 injected channels" - depends on STM32F7_ADC3 - range 0 4 - default 0 - ---help--- - Support for ADC3 injected channels. - -config STM32F7_ADC1_EXTSEL - bool "ADC1 external trigger for regular group" - depends on STM32F7_ADC1 && !STM32F7_HAVE_ADC1_TIMER - default n - ---help--- - Enable EXTSEL for ADC1. - -config STM32F7_ADC2_EXTSEL - bool "ADC2 external trigger for regular group" - depends on STM32F7_ADC2 && !STM32F7_HAVE_ADC2_TIMER - default n - ---help--- - Enable EXTSEL for ADC2. - -config STM32F7_ADC3_EXTSEL - bool "ADC3 external trigger for regular group" - depends on STM32F7_ADC3 && !STM32F7_HAVE_ADC3_TIMER - default n - ---help--- - Enable EXTSEL for ADC3. - -config STM32F7_ADC1_JEXTSEL - bool "ADC1 external trigger for injected group" - depends on STM32F7_ADC1 - default n - ---help--- - Enable JEXTSEL for ADC1. - -config STM32F7_ADC2_JEXTSEL - bool "ADC2 external trigger for injected group" - depends on STM32F7_ADC2 - default n - ---help--- - Enable JEXTSEL for ADC2. - -config STM32F7_ADC3_JEXTSEL - bool "ADC3 external trigger for injected group" - depends on STM32F7_ADC3 - default n - ---help--- - Enable JEXTSEL for ADC3. - -endmenu # "ADC Configuration" - -menu "Ethernet MAC configuration" - depends on STM32F7_ETHMAC - -config STM32F7_PHYADDR - int "PHY address" - default 1 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32F7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32F7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32F7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32F7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32F7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32F7_MII_EXTCLK - depends on STM32F7_MII - -config STM32F7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32F7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32F7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32F7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32F7_ETHFD - bool "Full duplex" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32F7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32F7_AUTONEG - ---help--- - If STM32F7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32F7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32F7_AUTONEG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32F7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32F7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32F7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32F7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32F7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32F7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32F7_AUTONEG && !STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32F7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32F7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32F7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32F7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32F7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32F7_AUTONEG && STM32F7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32F7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32F7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32F7_RMII - bool - default !STM32F7_MII - -choice - prompt "RMII clock configuration" - default STM32F7_RMII_EXTCLK - depends on STM32F7_RMII - -config STM32F7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32F7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32F7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32F7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -endmenu # Ethernet MAC configuration - -if STM32F7_LTDC - -menu "LTDC Configuration" - -config STM32F7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32F7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32F7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32F7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32F7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32F7_LTDC_DITHER - bool "Dither support" - default n - -config STM32F7_LTDC_DITHER_RED - depends on STM32F7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32F7_LTDC_DITHER_GREEN - depends on STM32F7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32F7_LTDC_DITHER_BLUE - depends on STM32F7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32F7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32F7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32F7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32F7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32F7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32F7_LTDC_L1_RGB565 - -config STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32F7_FB_CMAP - -config STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32F7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32F7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32F7_LTDC_L2 - -config STM32F7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32F7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32F7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32F7_LTDC_L2_RGB565 - -config STM32F7_LTDC_L2_L8 - depends on STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32F7_LTDC_L2_AL44 - depends on STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32F7_LTDC_L2_AL88 - depends on STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32F7_LTDC_L2_RGB565 - depends on STM32F7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32F7_LTDC_L2_ARGB4444 - depends on STM32F7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32F7_LTDC_L2_ARGB1555 - depends on STM32F7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32F7_LTDC_L2_RGB888 - depends on STM32F7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32F7_LTDC_L2_ARGB8888 - depends on STM32F7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32F7_LTDC_L2 - -config STM32F7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32F7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32F7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32F7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu - -endif # STM32F7_LTDC - -if STM32F7_DMA2D - -menu "DMA2D Configuration" - -config STM32F7_DMA2D_NLAYERS - int "Number DMA2D overlays" - default 1 - range 1 256 - ---help--- - Number of supported DMA2D layer. - -config STM32F7_DMA2D_LAYER_SHARED - bool "Overlays shared memory region" - default n - ---help--- - Several overlays can share the same memory region. - Setup a whole memory area (usually multiple size of the visible screen) - allows image preprocessing before they become visible by blit operation. - -config STM32F7_DMA2D_LAYER_PPLINE - int "Pixel per line" - default 1 - range 1 65535 - ---help--- - If you are using the DMA2D, then you must provide the pixel per line or - width of the overlay. - -config STM32F7_DMA2D_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the DMA2D, then you must provide the address - of the start of the DMA2D overlays framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FSMC. - -config STM32F7_DMA2D_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of all DMA2D overlays. - -menu "Supported pixel format" - -config STM32F7_DMA2D_L8 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - default y - -config STM32F7_DMA2D_AL44 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - default y - -config STM32F7_DMA2D_AL88 - depends on STM32F7_FB_CMAP && STM32F7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - default y - -config STM32F7_DMA2D_RGB565 - bool "16 bpp RGB 565" - depends on STM32F7_LTDC_L1_RGB565 - default y - -config STM32F7_DMA2D_ARGB4444 - bool "16 bpp ARGB 4444" - depends on STM32F7_LTDC_L1_ARGB4444 - default y - -config STM32F7_DMA2D_ARGB1555 - bool "16 bpp ARGB 1555" - depends on STM32F7_LTDC_L1_ARGB15555 - default y - -config STM32F7_DMA2D_RGB888 - bool "24 bpp RGB 888" - depends on STM32F7_LTDC_L1_RGB888 - default y - -config STM32F7_DMA2D_ARGB8888 - bool "32 bpp ARGB 8888" - depends on STM32F7_LTDC_L1_ARGB8888 - default y - -endmenu - -config STM32F7_DMA2D_REGDEBUG - bool "DMA2D Register level debug" - depends on DEBUG_INFO && DEBUG_LCD - default n - ---help--- - Output detailed register-level DMA2D device debug information. - -endmenu -endif # STM32F7_DMA2D - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32F7_TIM1 || STM32F7_TIM2 || STM32F7_TIM3 || STM32F7_TIM4 || STM32F7_TIM5 || STM32F7_TIM8 - -config STM32F7_TIM1_QE - bool "TIM1" - default n - depends on STM32F7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32F7_TIM1_QE - -config STM32F7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM2_QE - bool "TIM2" - default n - depends on STM32F7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32F7_TIM2_QE - -config STM32F7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM3_QE - bool "TIM3" - default n - depends on STM32F7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32F7_TIM3_QE - -config STM32F7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM4_QE - bool "TIM4" - default n - depends on STM32F7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32F7_TIM4_QE - -config STM32F7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM5_QE - bool "TIM5" - default n - depends on STM32F7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32F7_TIM5_QE - -config STM32F7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_TIM8_QE - bool "TIM8" - default n - depends on STM32F7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32F7_TIM8_QE - -config STM32F7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif - -config STM32F7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32F7_QENCODER_SAMPLE_FDTS_4 - -config STM32F7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32F7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32F7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32F7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32F7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32F7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32F7_QENCODER_FILTER - prompt "Input channel event count" - default STM32F7_QENCODER_SAMPLE_EVENT_6 - -config STM32F7_QENCODER_SAMPLE_EVENT_1 - depends on STM32F7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32F7_QENCODER_SAMPLE_EVENT_2 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32F7_QENCODER_SAMPLE_EVENT_4 - depends on STM32F7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32F7_QENCODER_SAMPLE_EVENT_5 - depends on STM32F7_QENCODER_SAMPLE_FDTS_16 || STM32F7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32F7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32F7_QENCODER_SAMPLE_FDTS && !STM32F7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32F7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32F7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32F7_SAI - -choice - prompt "Operation mode" - default STM32F7_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32F7_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32F7_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32F7_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32F7_SAI1_BOTH_ASYNC - depends on STM32F7_SAI1_A && STM32F7_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32F7_SAI2_BOTH_ASYNC - depends on STM32F7_SAI2_A && STM32F7_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32F7_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32F7_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32F7_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - -menuconfig STM32F7_FOC - bool "STM32 lower-half FOC support" - default n - select ARCH_IRQPRIO - select STM32F7_PWM_MULTICHAN - select STM32F7_PWM_LL_OPS - select STM32F7_ADC_LL_OPS - select STM32F7_ADC_CHANGE_SAMPLETIME - select STM32F7_ADC_NO_STARTUP_CONV - -if STM32F7_FOC - -config STM32F7_FOC_FOC0 - bool "FOC0 device (TIM1 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM1 - ---help--- - Enable support for FOC0 device that uses TIM1 for PWM modulation - -config STM32F7_FOC_FOC1 - bool "FOC1 device (TIM8 for PWM modulation)" - default n - select STM32F7_FOC_USE_TIM8 - ---help--- - Enable support for FOC1 device that uses TIM8 for PWM modulation - -choice - prompt "FOC ADC trigger selection" - default STM32F7_FOC_ADC_TRGO - -config STM32F7_FOC_ADC_CCR4 - bool "FOC uses CCR4 as ADC trigger" - ---help--- - This option uses the software frequency prescaler and is - not possible for 4-phase output. - -config STM32F7_FOC_ADC_TRGO - bool "FOC uses TRGO as ADC trigger" - depends on !STM32F7_FOC_FOC1 - select STM32F7_PWM_TRGO - ---help--- - This option allows you to use higher PWM frequency and works for 4-phase output. - It is not possible for ADC IPv1 if FOC1 enabled (no T8TRGO in JEXTSEL). - -endchoice # "FOC ADC trigger selection" - -if STM32F7_FOC_FOC0 - -choice - prompt "FOC0 device ADC selection" - default STM32F7_FOC_FOC0_ADC1 - -config STM32F7_FOC_FOC0_ADC1 - bool "FOC0 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC0_ADC2 - bool "FOC0 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC0_ADC3 - bool "FOC0 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC0 - -if STM32F7_FOC_FOC1 - -choice - prompt "FOC1 device ADC selection" - default STM32F7_FOC_FOC1_ADC2 - -config STM32F7_FOC_FOC1_ADC1 - bool "FOC1 uses ADC1" - select STM32F7_FOC_USE_ADC1 - -config STM32F7_FOC_FOC1_ADC2 - bool "FOC1 uses ADC2" - select STM32F7_FOC_USE_ADC2 - -config STM32F7_FOC_FOC1_ADC3 - bool "FOC1 uses ADC3" - select STM32F7_FOC_USE_ADC3 - -endchoice # "FOC0 device ADC selection" - -endif # STM32F7_FOC_FOC1 - -config STM32F7_FOC_HAS_PWM_COMPLEMENTARY - bool "FOC PWM has complementary outputs" - default n - ---help--- - Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode) - -# hidden variables and automatic configuration - -config STM32F7_FOC_USE_TIM1 - bool - default n - select STM32F7_TIM1 - select STM32F7_TIM1_PWM - select STM32F7_TIM1_CHANNEL1 - select STM32F7_TIM1_CHANNEL2 - select STM32F7_TIM1_CHANNEL3 - select STM32F7_TIM1_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1OUT - select STM32F7_TIM1_CH2OUT - select STM32F7_TIM1_CH3OUT - select STM32F7_TIM1_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM1_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM1_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM1 generates PWM for the FOC - -config STM32F7_FOC_USE_TIM8 - bool - default n - select STM32F7_TIM8 - select STM32F7_TIM8_PWM - select STM32F7_TIM8_CHANNEL1 - select STM32F7_TIM8_CHANNEL2 - select STM32F7_TIM8_CHANNEL3 - select STM32F7_TIM8_CHANNEL4 if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1OUT - select STM32F7_TIM8_CH2OUT - select STM32F7_TIM8_CH3OUT - select STM32F7_TIM8_CH4OUT if STM32F7_FOC_ADC_CCR4 - select STM32F7_TIM8_CH1NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH2NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - select STM32F7_TIM8_CH3NOUT if STM32F7_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - The TIM8 generates PWM for the FOC - -config STM32F7_FOC_USE_ADC1 - bool - default n - select STM32F7_ADC1 - select STM32F7_ADC1_SCAN - select STM32F7_ADC1_JEXTSEL - -config STM32F7_FOC_USE_ADC2 - bool - default n - select STM32F7_ADC2 - select STM32F7_ADC2_SCAN - select STM32F7_ADC2_JEXTSEL - -config STM32F7_FOC_USE_ADC3 - bool - default n - select STM32F7_ADC3 - select STM32F7_ADC3_SCAN - select STM32F7_ADC3_JEXTSEL - -endif #STM32F7_FOC + select STM32_HAVE_FMC + select STM32_HAVE_RNG + select STM32_HAVE_SPI5 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SPI6 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_SDMMC2 if !STM32F7_IO_CONFIG_V + select STM32_HAVE_CAN3 + select STM32_HAVE_DCMI + select STM32_HAVE_DSIHOST if !(STM32F7_IO_CONFIG_V || STM32F7_IO_CONFIG_Z) + select STM32_HAVE_LTDC + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_JPEG + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_HASH + select STM32_HAVE_DFSDM1 + select STM32_HAVE_CAN2 + select STM32_HAVE_SPI4 endif # ARCH_CHIP_STM32F7 diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 01e8d8c4408..b9b5fdb7467 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -39,7 +39,7 @@ else CHIP_CSRCS += stm32_tickless.c endif -ifeq ($(CONFIG_STM32F7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -51,11 +51,11 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32F7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif @@ -66,11 +66,11 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32F7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c endif -ifeq ($(CONFIG_STM32F7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -83,27 +83,27 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32F7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32F7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32F7_I2S),y) +ifeq ($(CONFIG_STM32_I2S),y) CHIP_CSRCS += stm32_i2s.c endif -ifeq ($(CONFIG_STM32F7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -122,19 +122,19 @@ endif endif endif -ifeq ($(CONFIG_STM32F7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32F7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32F7_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32F7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -142,19 +142,19 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32_dumpgpio.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32F7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif -ifeq ($(CONFIG_STM32F7_DMA2D),y) +ifeq ($(CONFIG_STM32_DMA2D),y) CHIP_CSRCS += stm32_dma2d.c endif @@ -162,26 +162,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32_qencoder.c endif -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CHIP_CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CHIP_CSRCS += stm32_can_sock.c endif -ifeq ($(CONFIG_STM32F7_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32_sai.c endif -ifeq ($(CONFIG_STM32F7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32F7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CHIP_CSRCS += stm32_foc.c endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_adc.h b/arch/arm/src/stm32f7/hardware/stm32_adc.h index cabbd5921ef..f8e8fb4423c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_adc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_adc.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_adc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_adc.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_can.h b/arch/arm/src/stm32f7/hardware/stm32_can.h index c5da101f134..8124ae8815f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_can.h +++ b/arch/arm/src/stm32f7/hardware/stm32_can.h @@ -123,7 +123,7 @@ /* Register Addresses *******************************************************/ -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) # define STM32_CAN1_MCR (STM32_CAN1_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN1_MSR (STM32_CAN1_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN1_TSR (STM32_CAN1_BASE+STM32_CAN_TSR_OFFSET) @@ -177,7 +177,7 @@ # define STM32_CAN1_FIR(b,i) (STM32_CAN1_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) # define STM32_CAN2_MCR (STM32_CAN2_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN2_MSR (STM32_CAN2_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN2_TSR (STM32_CAN2_BASE+STM32_CAN_TSR_OFFSET) @@ -231,7 +231,7 @@ # define STM32_CAN2_FIR(b,i) (STM32_CAN2_BASE+STM32_CAN_FIR_OFFSET(b,i)) #endif -#if defined(CONFIG_STM32F7_CAN3) +#if defined(CONFIG_STM32_CAN3) # define STM32_CAN3_MCR (STM32_CAN3_BASE+STM32_CAN_MCR_OFFSET) # define STM32_CAN3_MSR (STM32_CAN3_BASE+STM32_CAN_MSR_OFFSET) # define STM32_CAN3_TSR (STM32_CAN3_BASE+STM32_CAN_TSR_OFFSET) diff --git a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h index 4bc19f87b6d..2603a97063a 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dbgmcu.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dbgmcu.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dbgmcu.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_dma.h b/arch/arm/src/stm32f7/hardware/stm32_dma.h index 9df147e2704..1084640b378 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32_dma.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_dma.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_dma.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h index ff9a5be351c..b2e403ca83d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/hardware/stm32_ethernet.h @@ -33,8 +33,8 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -810,7 +810,7 @@ struct eth_txdesc_s /* Enhanced DMA descriptor words with time stamp */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t tdes4; /* Reserved */ volatile uint32_t tdes5; /* Reserved */ volatile uint32_t tdes6; /* Time Stamp Low value for transmit and receive */ @@ -829,7 +829,7 @@ struct eth_rxdesc_s /* Enhanced DMA descriptor words with time stamp and PTP support */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC volatile uint32_t rdes4; /* Extended status for PTP receive descriptor */ volatile uint32_t rdes5; /* Reserved */ volatile uint32_t rdes6; /* Time Stamp Low value for transmit and receive */ @@ -842,5 +842,5 @@ struct eth_rxdesc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_exti.h b/arch/arm/src/stm32f7/hardware/stm32_exti.h index b846f19c0f8..62fe35128bc 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32f7/hardware/stm32_exti.h @@ -34,9 +34,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -116,5 +116,5 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX || CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX || CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32_flash.h b/arch/arm/src/stm32f7/hardware/stm32_flash.h index 37551dde1b8..79050bf7c7b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32_flash.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_flash.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_flash.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_gpio.h b/arch/arm/src/stm32f7/hardware/stm32_gpio.h index 9449df0fa06..03f642dac61 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32_gpio.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_gpio.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_gpio.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_i2c.h b/arch/arm/src/stm32f7/hardware/stm32_i2c.h index 15456f503b3..bacc9e367e8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32f7/hardware/stm32_i2c.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_i2c.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h index fe51a5ccc24..57a9b1298f6 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_memorymap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_memorymap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_memorymap.h" #else # error "Unsupported STM32 F7 memory map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h index dad7c1251f8..5c10f75322c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pinmap.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pinmap.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pinmap.h" #else # error "Unsupported STM32 F7 Pin map" diff --git a/arch/arm/src/stm32f7/hardware/stm32_pwr.h b/arch/arm/src/stm32f7/hardware/stm32_pwr.h index 9eff00fa492..09792a2458d 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32_pwr.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_pwr.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_pwr.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_rcc.h b/arch/arm/src/stm32f7/hardware/stm32_rcc.h index bc41cad8beb..61a34dd8460 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_rcc.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_rcc.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_rcc.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h index 563818cc6c2..59f1f7ad3cb 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/hardware/stm32_sdmmc.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \ - defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) || \ + defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32_spi.h b/arch/arm/src/stm32f7/hardware/stm32_spi.h index 1411319566d..94fe7c794cf 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32_spi.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_spi.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_spi.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h index 5112e474130..18ff0709820 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32_syscfg.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_syscfg.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_syscfg.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32_tim.h b/arch/arm/src/stm32f7/hardware/stm32_tim.h index 46ffb0f4b11..6dfc200978c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_tim.h +++ b/arch/arm/src/stm32f7/hardware/stm32_tim.h @@ -30,11 +30,11 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "hardware/stm32f74xx75xx_tim.h" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f76xx77xx_tim.h" #else # error "Unsupported STM32 F7 sub family" diff --git a/arch/arm/src/stm32f7/hardware/stm32_uart.h b/arch/arm/src/stm32f7/hardware/stm32_uart.h index 4ef7a625794..0cd6b9c8d96 100644 --- a/arch/arm/src/stm32f7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32_uart.h @@ -30,10 +30,10 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "hardware/stm32f72xx73xx_uart.h" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "hardware/stm32f74xx77xx_uart.h" #else # error "Unsupported STM32 F7 part" diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h index 7347b6b06d2..e0b4f0d71fe 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -539,5 +539,5 @@ #define DMAMAP_SDMMC2_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h index a7596397397..c18724aa2e0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -44,38 +44,38 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_C) -# define CONFIG_STM32F7_FLASH_OVERRIDE_C +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) +# define CONFIG_STM32_FLASH_OVERRIDE_C # warning "Flash size not defined defaulting to 256KiB (C)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_C -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_C) -# define CONFIG_STM32F7_FLASH_CONFIG_C +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_C) +#if defined(CONFIG_STM32_FLASH_CONFIG_C) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (1 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ _K(64), _K(128)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h index bdb8128244c..3f961686b38 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h index 1e10e0c06b1..0ee93e4ee04 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -188,5 +188,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h index 51ef59e85ac..9e649c192ce 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -923,5 +923,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h index b712b40aa6f..206807751d1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h index a9dc161a5ae..c7e53682bdd 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -677,5 +677,5 @@ # define RCC_DCKCFGR2_SDMMC2SEL_48MHZ (0 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMC2SEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMC2SEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h index 6c206fcebfc..d777cdddb4c 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -145,5 +145,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h index 5c73674d3d0..997b6186303 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f72xx73xx_uart.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) /**************************************************************************** * Pre-processor Definitions @@ -354,5 +354,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F72XX || CONFIG_STM32F7_STM32F73XX */ +#endif /* CONFIG_STM32_STM32F72XX || CONFIG_STM32_STM32F73XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F72XX73XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h index d82ff66c0a2..58a50d908c9 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -545,5 +545,5 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h index 23ba0cc2f6b..e5bb26ef1d5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -42,39 +42,39 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h index eee436dc44f..a423e8c659f 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h index 350f17cc260..74f18438de7 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -199,5 +199,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XXX75XXX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h index 322f006d44d..4f355760b23 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -808,7 +808,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1171,5 +1171,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h index 45fda531bd7..984af74a998 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -144,5 +144,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h index 2af6d339720..ef250fe77ba 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -723,5 +723,5 @@ # define RCC_DCKCFGR2_SDMMCSEL_48MHZ (0 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* 48 MHz clock is selected as SDMMC clock */ # define RCC_DCKCFGR2_SDMMCSEL_SYSCLK (1 << RCC_DCKCFGR2_SDMMCSEL_SHIFT) /* System clock is selected as SDMMC clock */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h index 5072c16d681..e634ebdb7eb 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx75xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h index 946408d1916..c1bfd5b1339 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_spi.h @@ -38,9 +38,9 @@ * (both pclk1 and pclk2) */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define STM32_SPI_CLK_MAX 50000000UL -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_SPI_CLK_MAX 54000000UL #endif diff --git a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h index c996cd30768..bfefcbffcde 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h +++ b/arch/arm/src/stm32f7/hardware/stm32f74xx77xx_uart.h @@ -29,8 +29,8 @@ #include -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -356,5 +356,5 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ #define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX77XX_UART_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h index dbe7de5cf2f..208693831df 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_dma.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -585,5 +585,5 @@ #define DMAMAP_QUADSPI_1 STM32_DMA_MAP(DMA2,DMA_STREAM2,DMA_CHAN11) #define DMAMAP_SDMMC2_2 STM32_DMA_MAP(DMA2,DMA_STREAM5,DMA_CHAN11) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_DMA_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h index 84e638d078a..c98d3c72aa0 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_flash.h @@ -29,7 +29,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32F7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. * This value can be overridden with CONFIG_STM32F7_FLASH_OVERRIDE_x @@ -42,53 +42,53 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32F7_FLASH_CONFIG_I) -# define CONFIG_STM32F7_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif -#if !defined(CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32F7_FLASH_CONFIG_E -# undef CONFIG_STM32F7_FLASH_CONFIG_G -# undef CONFIG_STM32F7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32F7_FLASH_OVERRIDE_E) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_E) -# define CONFIG_STM32F7_FLASH_CONFIG_E +# define CONFIG_STM32_FLASH_CONFIG_E -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32F7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32F7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32F7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32F7_FLASH_CONFIG_E) +#if defined(CONFIG_STM32_FLASH_CONFIG_E) # define STM32_FLASH_NPAGES 6 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (1 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (3 * 256)) # define STM32_FLASH_SIZES {_K(32), _K(32), _K(32), _K(32), \ _K(128), _K(256), _K(256), _K(256)} -#elif defined(CONFIG_STM32F7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NPAGES 12 # define STM32_FLASH_SIZE _K((4 * 32) + (1 * 128) + (7 * 256)) diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h index 370b090abd1..a63ce45ffc1 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_gpio.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -386,5 +386,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_GPIO_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h index 1f9e1673df3..b60c2f882c5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_memorymap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -205,5 +205,5 @@ #define STM32_DEBUGMCU_BASE 0xe0042000 -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F74XX75XX_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h index 82d795a98c0..5ef7ae8ecde 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pinmap.h @@ -31,7 +31,7 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -916,7 +916,7 @@ * * Note that the below configures GPIO_SPEED_50MHz I/O, that means for using * the SDIO that you must enable I/O Compensation via the configuration - * option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y. + * option CONFIG_STM32_SYSCFG_IOCOMPENSATION=y. */ #define GPIO_SDMMC1_CK_0 (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12) @@ -1330,5 +1330,5 @@ #define GPIO_UART8_RX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN0) #define GPIO_UART8_TX_0 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN1) -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PINMAP_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h index 54afc5d9d3d..b6d554f765b 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_pwr.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -143,5 +143,5 @@ #define PWR_CSR2_EWUP5 (1 << 12) /* Bit 12: Enable wakeup pin for PI8 */ #define PWR_CSR2_EWUP6 (1 << 13) /* Bit 13: Enable wakeup pin for PI11 */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_PWR_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h index 7b72de0e625..6a56b4494b5 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -756,5 +756,5 @@ # define RCC_DCKCFGR2_DSISEL_PHY (0 << RCC_DCKCFGR2_DSISEL_SHIFT) /* DSI PHY sources DSI clock */ # define RCC_DCKCFGR2_DSISEL_SYSCLK (1 << RCC_DCKCFGR2_DSISEL_SHIFT) /* System clock is selected as DSI clock */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_RCC_H */ diff --git a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h index 11b42882cff..ef63b7dede8 100644 --- a/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h +++ b/arch/arm/src/stm32f7/hardware/stm32f76xx77xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -163,5 +163,5 @@ #define SYSCFG_CMPCR_CMPPD (1 << 0) /* Bit 0: Compensation cell power-down */ #define SYSCFG_CMPCR_READY (1 << 8) /* Bit 8: Compensation cell ready flag */ -#endif /* CONFIG_STM32F7_STM32F76XX || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F76XX || CONFIG_STM32_STM32F77XX */ #endif /* __ARCH_ARM_SRC_STM32F7_HARDWARE_STM32F76XX77XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32f7/stm32_adc.c b/arch/arm/src/stm32f7/stm32_adc.c index e875c19c71a..c47336e6df2 100644 --- a/arch/arm/src/stm32f7/stm32_adc.c +++ b/arch/arm/src/stm32f7/stm32_adc.c @@ -59,7 +59,7 @@ /* STM32 ADC "lower-half" support must be enabled */ -#ifdef CONFIG_STM32F7_ADC +#ifdef CONFIG_STM32_ADC /* This implementation is for the STM32 ADC IP version 1 */ @@ -121,21 +121,21 @@ /* ADC scan mode support */ -#ifndef CONFIG_STM32F7_ADC1_SCAN -# define CONFIG_STM32F7_ADC1_SCAN 0 +#ifndef CONFIG_STM32_ADC1_SCAN +# define CONFIG_STM32_ADC1_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC2_SCAN -# define CONFIG_STM32F7_ADC2_SCAN 0 +#ifndef CONFIG_STM32_ADC2_SCAN +# define CONFIG_STM32_ADC2_SCAN 0 #endif -#ifndef CONFIG_STM32F7_ADC3_SCAN -# define CONFIG_STM32F7_ADC3_SCAN 0 +#ifndef CONFIG_STM32_ADC3_SCAN +# define CONFIG_STM32_ADC3_SCAN 0 #endif /* We have to support ADC callbacks if default ADC interrupts or * DMA transfer are enabled */ -#if !defined(CONFIG_STM32F7_ADC_NOIRQ) || defined(ADC_HAVE_DMA) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_DMA) # define ADC_HAVE_CB #else # undef ADC_HAVE_CB @@ -184,7 +184,7 @@ struct adccmn_data_s struct stm32_dev_s { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ struct adc_dev_s *dev; /* Upper-half ADC reference */ #endif @@ -210,7 +210,7 @@ struct stm32_dev_s uint16_t dmabatch; /* Number of conversions for DMA batch */ #endif bool scan; /* True: Scan mode */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Sample time selection. These bits must be written only when ADON=0. * REVISIT: this takes too much space. We need only 3 bits per channel. */ @@ -252,7 +252,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32F7_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -293,10 +293,10 @@ static void adc_rccreset(struct stm32_dev_s *priv, bool reset); /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev); static int adc123_interrupt(int irq, void *context, void *arg); -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -321,7 +321,7 @@ static void adc_timstart(struct stm32_dev_s *priv, bool enable); static int adc_timinit(struct stm32_dev_s *priv); #endif -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -346,7 +346,7 @@ static int adc_jextcfg_set(struct stm32_dev_s *priv, uint32_t jextcfg); static void adc_dumpregs(struct stm32_dev_s *priv); -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static int adc_llops_setup(struct stm32_adc_dev_s *dev); static void adc_llops_shutdown(struct stm32_adc_dev_s *dev); static void adc_intack(struct stm32_adc_dev_s *dev, uint32_t source); @@ -375,7 +375,7 @@ static uint32_t adc_injget(struct stm32_adc_dev_s *dev, uint8_t chan); static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_set(struct stm32_adc_dev_s *dev, struct adc_sample_time_s *time_samples); static void adc_sampletime_write(struct stm32_adc_dev_s *dev); @@ -403,7 +403,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .setup = adc_llops_setup, @@ -428,7 +428,7 @@ static const struct stm32_adc_ops_s g_adc_llops = .inj_get = adc_injget, .inj_startconv = adc_llops_inj_startconv, # endif -# ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +# ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME .stime_set = adc_sampletime_set, .stime_write = adc_sampletime_write, # endif @@ -454,27 +454,27 @@ struct adccmn_data_s g_adc123_cmn = /* ADC1 state */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC1CMN_DATA, .intf = 1, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC1_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC1_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC1_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, #ifdef ADC1_HAVE_EXTCFG .extcfg = ADC1_EXTCFG_VALUE, @@ -483,19 +483,19 @@ static struct stm32_dev_s g_adcpriv1 = .jextcfg = ADC1_JEXTCFG_VALUE, #endif #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC1_SCAN, + .scan = CONFIG_STM32_ADC1_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -513,27 +513,27 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC2CMN_DATA, .intf = 2, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC2_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC2_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC2_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, #ifdef ADC2_HAVE_EXTCFG .extcfg = ADC2_EXTCFG_VALUE, @@ -542,19 +542,19 @@ static struct stm32_dev_s g_adcpriv2 = .jextcfg = ADC2_JEXTCFG_VALUE, #endif #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC2_SCAN, + .scan = CONFIG_STM32_ADC2_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -572,27 +572,27 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32F7_ADC_MAX_SAMPLES * - CONFIG_STM32F7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC, .isr = adc123_interrupt, -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .cmn = &ADC3CMN_DATA, .intf = 3, .initialized = 0, - .anioc_trg = CONFIG_STM32F7_ADC3_ANIOC_TRIGGER, - .resolution = CONFIG_STM32F7_ADC3_RESOLUTION, + .anioc_trg = CONFIG_STM32_ADC3_ANIOC_TRIGGER, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, .base = STM32_ADC3_BASE, #ifdef ADC3_HAVE_EXTCFG .extcfg = ADC3_EXTCFG_VALUE, @@ -601,19 +601,19 @@ static struct stm32_dev_s g_adcpriv3 = .jextcfg = ADC3_JEXTCFG_VALUE, #endif #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32F7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32F7_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32F7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif - .scan = CONFIG_STM32F7_ADC3_SCAN, + .scan = CONFIG_STM32_ADC3_SCAN, #ifdef CONFIG_PM .pm_callback = { @@ -1455,7 +1455,7 @@ static void adc_enable(struct stm32_dev_s *priv, bool enable) * ****************************************************************************/ -#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32F7_ADC_NOIRQ) +#if defined(ADC_HAVE_DMA) && !defined(CONFIG_STM32_ADC_NOIRQ) static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -1587,7 +1587,7 @@ static void adc_sampletime_cfg(struct adc_dev_s *dev) * During sample cycles channel selection bits must remain unchanged. */ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME adc_sampletime_write((struct stm32_adc_dev_s *)dev->ad_priv); #else struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1673,7 +1673,7 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Start DMA only if standard ADC interrupts used */ stm32_dmasetup(priv->dma, @@ -1853,7 +1853,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1885,7 +1885,7 @@ static int adc_setup(struct adc_dev_s *dev) /* As default conversion is started here */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ adc_reg_startconv(priv, true); @@ -1909,7 +1909,7 @@ static int adc_setup(struct adc_dev_s *dev) { /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1967,7 +1967,7 @@ static void adc_shutdown(struct adc_dev_s *dev) if (priv->cmn->refcount <= 1) { -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ up_disable_irq(priv->irq); @@ -2469,7 +2469,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32F7_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2570,23 +2570,23 @@ static int adc_interrupt(struct adc_dev_s *dev) static int adc123_interrupt(int irq, void *context, void *arg) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 adc_interrupt(&g_adcdev1); #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 adc_interrupt(&g_adcdev2); #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 adc_interrupt(&g_adcdev3); #endif return OK; } -#endif /* CONFIG_STM32F7_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_setup @@ -2821,7 +2821,7 @@ static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME static void adc_sampletime_write(struct stm32_adc_dev_s *dev) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; @@ -2911,7 +2911,7 @@ void adc_sampletime_set(struct stm32_adc_dev_s *dev, } } } -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /**************************************************************************** * Name: adc_llops_dumpregs @@ -3017,7 +3017,7 @@ static void adc_llops_enable(struct stm32_adc_dev_s *dev, bool enable) adc_enable(priv, enable); } -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -3085,12 +3085,12 @@ struct adc_dev_s *stm32_adc_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); dev = &g_adcdev1; - cj_channels = CONFIG_STM32F7_ADC1_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC1_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3100,14 +3100,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); dev = &g_adcdev2; - cj_channels = CONFIG_STM32F7_ADC2_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC2_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3117,14 +3117,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, # endif break; } -#endif /* CONFIG_STM32F7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); dev = &g_adcdev3; - cj_channels = CONFIG_STM32F7_ADC3_INJECTED_CHAN; + cj_channels = CONFIG_STM32_ADC3_INJECTED_CHAN; cr_channels = channels - cj_channels; # ifdef ADC_HAVE_INJECTED if (cj_channels > 0) @@ -3135,7 +3135,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, break; } -#endif /* CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC3 */ default: { @@ -3150,10 +3150,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, /* Configure regular channels */ - DEBUGASSERT(cr_channels <= CONFIG_STM32F7_ADC_MAX_SAMPLES); - if (cr_channels > CONFIG_STM32F7_ADC_MAX_SAMPLES) + DEBUGASSERT(cr_channels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cr_channels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cr_channels = CONFIG_STM32F7_ADC_MAX_SAMPLES; + cr_channels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cr_channels = cr_channels; @@ -3172,14 +3172,14 @@ struct adc_dev_s *stm32_adc_initialize(int intf, memcpy(priv->j_chanlist, j_chanlist, cj_channels); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Assign default values for the sample time table */ memset(priv->sample_rate, ADC_SMPR_DEFAULT, ADC_CHANNELS_NUMBER); priv->adc_channels = ADC_CHANNELS_NUMBER; #endif -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* Store reference to the upper-half ADC device */ priv->dev = dev; @@ -3195,4 +3195,4 @@ struct adc_dev_s *stm32_adc_initialize(int intf, return dev; } -#endif /* CONFIG_STM32F7_ADC */ +#endif /* CONFIG_STM32_ADC */ diff --git a/arch/arm/src/stm32f7/stm32_adc.h b/arch/arm/src/stm32f7/stm32_adc.h index b7e65e97588..39616944981 100644 --- a/arch/arm/src/stm32f7/stm32_adc.h +++ b/arch/arm/src/stm32f7/stm32_adc.h @@ -63,75 +63,75 @@ * is intended to be used for that purpose. Timers 1-6 and 8 may be used. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_ADC -# undef CONFIG_STM32F7_TIM1_ADC1 -# undef CONFIG_STM32F7_TIM1_ADC2 -# undef CONFIG_STM32F7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_ADC -# undef CONFIG_STM32F7_TIM2_ADC1 -# undef CONFIG_STM32F7_TIM2_ADC2 -# undef CONFIG_STM32F7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_ADC -# undef CONFIG_STM32F7_TIM3_ADC1 -# undef CONFIG_STM32F7_TIM3_ADC2 -# undef CONFIG_STM32F7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_ADC -# undef CONFIG_STM32F7_TIM4_ADC1 -# undef CONFIG_STM32F7_TIM4_ADC2 -# undef CONFIG_STM32F7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_ADC -# undef CONFIG_STM32F7_TIM5_ADC1 -# undef CONFIG_STM32F7_TIM5_ADC2 -# undef CONFIG_STM32F7_TIM5_ADC3 +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_ADC +# undef CONFIG_STM32_TIM5_ADC1 +# undef CONFIG_STM32_TIM5_ADC2 +# undef CONFIG_STM32_TIM5_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM6 -# undef CONFIG_STM32F7_TIM6_ADC -# undef CONFIG_STM32F7_TIM6_ADC1 -# undef CONFIG_STM32F7_TIM6_ADC2 -# undef CONFIG_STM32F7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_ADC -# undef CONFIG_STM32F7_TIM8_ADC1 -# undef CONFIG_STM32F7_TIM8_ADC2 -# undef CONFIG_STM32F7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || \ - defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32F7_ADC1_DMA) || defined(CONFIG_STM32F7_ADC2_DMA) || \ - defined(CONFIG_STM32F7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32F7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32F7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -139,9 +139,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32F7_ADC1) && (CONFIG_STM32F7_ADC1_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC2) && (CONFIG_STM32F7_ADC2_INJECTED_CHAN > 0)) || \ - (defined(CONFIG_STM32F7_ADC3) && (CONFIG_STM32F7_ADC3_INJECTED_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJECTED_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJECTED_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -149,31 +149,31 @@ * information about the timer. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC1) +#elif defined(CONFIG_STM32_TIM5_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM5_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -182,40 +182,40 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC1_TIMTRIG -# error "CONFIG_STM32F7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC2) +#elif defined(CONFIG_STM32_TIM5_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM5_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -224,36 +224,36 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC2_TIMTRIG -# error "CONFIG_STM32F7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -#elif defined(CONFIG_STM32F7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -#elif defined(CONFIG_STM32F7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -#elif defined(CONFIG_STM32F7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -#elif defined(CONFIG_STM32F7_TIM5_ADC3) +#elif defined(CONFIG_STM32_TIM5_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM5_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM5_CLKIN -#elif defined(CONFIG_STM32F7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN @@ -262,11 +262,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32F7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32F7_ADC3_TIMTRIG -# error "CONFIG_STM32F7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2" # endif #endif @@ -413,315 +413,315 @@ * CONFIG_STM32F7_ADCx_EXTSEL option. */ -#if defined(CONFIG_STM32F7_TIM1_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC1) -# if CONFIG_STM32F7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC2) -# if CONFIG_STM32F7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32F7_TIM1_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM2_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM3_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM4_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM5_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM5_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T5TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM6_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32F7_TIM8_ADC3) -# if CONFIG_STM32F7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32F7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32F7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -730,7 +730,7 @@ #ifdef ADC1_EXTSEL_VALUE # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE (ADC1_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_EXTSEL) +#elif defined(CONFIG_STM32_ADC1_EXTSEL) # define ADC1_HAVE_EXTCFG 1 # define ADC1_EXTCFG_VALUE 0 #else @@ -739,7 +739,7 @@ #ifdef ADC2_EXTSEL_VALUE # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE (ADC2_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_EXTSEL) +#elif defined(CONFIG_STM32_ADC2_EXTSEL) # define ADC2_HAVE_EXTCFG 1 # define ADC2_EXTCFG_VALUE 0 #else @@ -748,7 +748,7 @@ #ifdef ADC3_EXTSEL_VALUE # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE (ADC3_EXTSEL_VALUE | ADC_EXTREG_EXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_EXTSEL) +#elif defined(CONFIG_STM32_ADC3_EXTSEL) # define ADC3_HAVE_EXTCFG 1 # define ADC3_EXTCFG_VALUE 0 #else @@ -771,7 +771,7 @@ #ifdef ADC1_JEXTSEL_VALUE # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE (ADC1_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC1_JEXTSEL) +#elif defined(CONFIG_STM32_ADC1_JEXTSEL) # define ADC1_HAVE_JEXTCFG 1 # define ADC1_JEXTCFG_VALUE 0 #else @@ -780,7 +780,7 @@ #ifdef ADC2_JEXTSEL_VALUE # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE (ADC2_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC2_JEXTSEL) +#elif defined(CONFIG_STM32_ADC2_JEXTSEL) # define ADC2_HAVE_JEXTCFG 1 # define ADC2_JEXTCFG_VALUE 0 #else @@ -789,7 +789,7 @@ #ifdef ADC3_JEXTSEL_VALUE # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE (ADC3_JEXTSEL_VALUE | ADC_JEXTREG_JEXTEN_DEFAULT) -#elif defined(CONFIG_STM32F7_ADC3_JEXTSEL) +#elif defined(CONFIG_STM32_ADC3_JEXTSEL) # define ADC3_HAVE_JEXTCFG 1 # define ADC3_JEXTCFG_VALUE 0 #else @@ -914,9 +914,9 @@ enum stm32_adc_multimode_e ADC_MULTIMODE_ATM3 = 14, /* Triple alternate trigger mode only */ }; -#ifdef CONFIG_STM32F7_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Channel and sample time pair */ @@ -941,7 +941,7 @@ struct adc_sample_time_s * same value of the sample time */ uint8_t all_ch_sample_time:3; /* Sample time for all channels */ }; -#endif /* CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME */ +#endif /* CONFIG_STM32_ADC_CHANGE_SAMPLETIME */ /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -1024,7 +1024,7 @@ struct stm32_adc_ops_s void (*inj_startconv)(struct stm32_adc_dev_s *dev, bool state); #endif -#ifdef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifdef CONFIG_STM32_ADC_CHANGE_SAMPLETIME /* Set ADC sample time */ void (*stime_set)(struct stm32_adc_dev_s *dev, @@ -1046,7 +1046,7 @@ struct stm32_adc_ops_s void (*enable)(struct stm32_adc_dev_s *dev, bool enable); }; -#endif /* CONFIG_STM32F7_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -1088,7 +1088,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || - * CONFIG_STM32F7_ADC3 +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || + * CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 47ac51b14ed..024e37de43c 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -62,7 +62,7 @@ * the FMC. In order to use FMC RAM, the following additional things need * to be present in the NuttX configuration file: * - * CONFIG_STM32F7_FMC=y : Enables the FMC + * CONFIG_STM32_FMC=y : Enables the FMC * CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC. * Either of these autoselects * CONFIG_ARCH_HAVE_HEAP2 @@ -94,15 +94,15 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32F7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif /* We can't possibly have FMC external RAM if the FMC is not enabled */ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # ifdef CONFIG_ARCH_HAVE_HEAP2 -# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed? +# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32_FMC! Kconfig flawed? # endif # undef CONFIG_ARCH_HAVE_HEAP2 #endif diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c index bdf2060127c..65a5b0e510f 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.c +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -51,14 +51,14 @@ #include "stm32_pwr.h" #include "stm32_rtc.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32F7_BKPSRAM) -#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -147,7 +147,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -633,7 +633,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) int ret = -EFBIG; struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; - for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -784,7 +784,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -802,7 +802,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h index 0eff55b26e1..7d6e8e3608e 100644 --- a/arch/arm/src/stm32f7/stm32_bbsram.h +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -44,15 +44,15 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ - defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) || \ + defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define STM32_BBSRAM_SIZE 4096 #else # error "No backup SRAM on this STM32 Device" #endif -#if !defined(CONFIG_STM32F7_BBSRAM_FILES) -# define CONFIG_STM32F7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif /* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique @@ -110,8 +110,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES - * CONFIG_STM32F7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -140,7 +140,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index b51547ebe35..2d571c61b8d 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -48,8 +48,8 @@ #include "stm32_gpio.h" #if defined(CONFIG_CAN) && \ - (defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) || \ - defined(CONFIG_STM32F7_CAN3)) + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) || \ + defined(CONFIG_STM32_CAN3)) /**************************************************************************** * Pre-processor Definitions @@ -63,7 +63,7 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO # undef CONFIG_STM32_CAN_REGDEBUG @@ -179,7 +179,7 @@ static const struct can_ops_s g_canops = .co_txempty = stm32can_txempty, }; -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { .port = 1, @@ -192,7 +192,7 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -202,7 +202,7 @@ static struct can_dev_s g_can1dev = }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { .port = 2, @@ -215,7 +215,7 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; static struct can_dev_s g_can2dev = @@ -225,7 +225,7 @@ static struct can_dev_s g_can2dev = }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { .port = 3, @@ -238,7 +238,7 @@ static struct stm32_can_s g_can3priv = .filter = 0, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; static struct can_dev_s g_can3dev = @@ -582,21 +582,21 @@ static void stm32can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -1789,8 +1789,8 @@ static int stm32can_bittiming(struct stm32_can_s *priv) else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2038,7 +2038,7 @@ static int stm32can_filterinit(struct stm32_can_s *priv) regval |= CAN_FMR_FINIT; stm32can_putfreg(priv, STM32_CAN_FMR_OFFSET, regval); -#if defined(CONFIG_STM32F7_CAN1) || defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) if (priv->port == 1 || priv->port == 2) { /* Assign half the filters to CAN1, half to CAN2 */ @@ -2270,7 +2270,7 @@ struct can_dev_s *stm32_caninitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2286,7 +2286,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2302,7 +2302,7 @@ struct can_dev_s *stm32_caninitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ diff --git a/arch/arm/src/stm32f7/stm32_can.h b/arch/arm/src/stm32f7/stm32_can.h index b9377f43389..356500aafb8 100644 --- a/arch/arm/src/stm32f7/stm32_can.h +++ b/arch/arm/src/stm32f7/stm32_can.h @@ -40,45 +40,45 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32F7_CAN1) || \ - defined(CONFIG_STM32F7_CAN2) || defined(CONFIG_STM32F7_CAN3)) +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || \ + defined(CONFIG_STM32_CAN2) || defined(CONFIG_STM32_CAN3)) /* CAN BAUD */ -#if defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN1_BAUD) -# error "CONFIG_STM32F7_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN2) && !defined(CONFIG_STM32F7_CAN2_BAUD) -# error "CONFIG_STM32F7_CAN2_BAUD is not defined" +#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" #endif -#if defined(CONFIG_STM32F7_CAN3) && !defined(CONFIG_STM32F7_CAN3_BAUD) -# error "CONFIG_STM32F7_CAN3_BAUD is not defined" +#if defined(CONFIG_STM32_CAN3) && !defined(CONFIG_STM32_CAN3_BAUD) +# error "CONFIG_STM32_CAN3_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32F7_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32F7_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32F7_CAN_TSEG1 -# define CONFIG_STM32F7_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32F7_CAN_TSEG1 < 1 || \ - CONFIG_STM32F7_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +#if CONFIG_STM32_CAN_TSEG1 < 1 || \ + CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX # error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32F7_CAN_TSEG2 -# define CONFIG_STM32F7_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32F7_CAN_TSEG2 < 1 || \ - CONFIG_STM32F7_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +#if CONFIG_STM32_CAN_TSEG2 < 1 || \ + CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX # error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif @@ -105,7 +105,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -125,7 +125,7 @@ struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index e4e8f68da1d..14f9ccda020 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -63,10 +63,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32F7_CAN_TSEG1 + CONFIG_STM32F7_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32F7_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /* Pool configuration *******************************************************/ @@ -146,7 +146,7 @@ static void stm32can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); static void stm32can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); static void stm32can_dumpmbregs(struct stm32_can_s *priv, @@ -233,7 +233,7 @@ static int stm32can_netdev_ioctl(struct net_driver_s *dev, int cmd, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { @@ -250,12 +250,12 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 static struct stm32_can_s g_can2priv = { @@ -272,12 +272,12 @@ static struct stm32_can_s g_can2priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN2_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32F7_CAN2_BAUD, + .baud = CONFIG_STM32_CAN2_BAUD, }; #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 static struct stm32_can_s g_can3priv = { @@ -294,7 +294,7 @@ static struct stm32_can_s g_can3priv = .filter = CAN_NFILTERS / 2, .base = STM32_CAN3_BASE, .fbase = STM32_CAN3_BASE, - .baud = CONFIG_STM32F7_CAN3_BAUD, + .baud = CONFIG_STM32_CAN3_BAUD, }; #endif @@ -312,7 +312,7 @@ static struct stm32_can_s g_can3priv = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -398,7 +398,7 @@ static uint32_t stm32can_getfreg(struct stm32_can_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -451,7 +451,7 @@ static void stm32can_putfreg(struct stm32_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { @@ -497,7 +497,7 @@ static void stm32can_dumpctrlregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { @@ -564,7 +564,7 @@ static void stm32can_dumpmbregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { @@ -1860,15 +1860,15 @@ static int stm32can_bittiming(struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32F7_CAN_TSEG1, - * ts2 is CONFIG_STM32F7_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32F7_CAN_TSEG1; - ts2 = CONFIG_STM32F7_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2036,21 +2036,21 @@ static void stm32can_reset(struct stm32_can_s *priv) /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR_CAN1RST; } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (priv->port == 2) { regbit = RCC_APB1RSTR_CAN2RST; } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (priv->port == 3) { regbit = RCC_APB1RSTR_CAN3RST; @@ -2298,9 +2298,9 @@ static int stm32can_filterinit(struct stm32_can_s *priv) /* Assign half the filters to CAN1, half to CAN2 */ -#if defined(CONFIG_STM32F7_CONNECTIVITYLINE) || \ - defined(CONFIG_STM32F7_STM32F20XX) || \ - defined(CONFIG_STM32F7_STM32F4XXX) +#if defined(CONFIG_STM32_CONNECTIVITYLINE) || \ + defined(CONFIG_STM32_STM32F20XX) || \ + defined(CONFIG_STM32_STM32F4XXX) regval = stm32can_getfreg(priv, STM32_CAN_FMR_OFFSET); regval &= CAN_FMR_CAN2SB_MASK; regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN2SB_SHIFT; @@ -2432,7 +2432,7 @@ int stm32_cansockinitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2448,7 +2448,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 if (port == 2) { /* Select the CAN2 device structure */ @@ -2464,7 +2464,7 @@ int stm32_cansockinitialize(int port) } else #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 if (port == 3) { /* Select the CAN3 device structure */ @@ -2526,15 +2526,15 @@ errout: #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 stm32_cansockinitialize(1); #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 stm32_cansockinitialize(2); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 stm32_cansockinitialize(3); #endif } diff --git a/arch/arm/src/stm32f7/stm32_capture.c b/arch/arm/src/stm32f7/stm32_capture.c index 6e650a6e849..84efc445174 100644 --- a/arch/arm/src/stm32f7/stm32_capture.c +++ b/arch/arm/src/stm32f7/stm32_capture.c @@ -92,18 +92,18 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1_CAP) || \ - defined(CONFIG_STM32F7_TIM2_CAP) || \ - defined(CONFIG_STM32F7_TIM3_CAP) || \ - defined(CONFIG_STM32F7_TIM4_CAP) || \ - defined(CONFIG_STM32F7_TIM5_CAP) || \ - defined(CONFIG_STM32F7_TIM8_CAP) || \ - defined(CONFIG_STM32F7_TIM9_CAP) || \ - defined(CONFIG_STM32F7_TIM10_CAP) || \ - defined(CONFIG_STM32F7_TIM11_CAP) || \ - defined(CONFIG_STM32F7_TIM12_CAP) || \ - defined(CONFIG_STM32F7_TIM13_CAP) || \ - defined(CONFIG_STM32F7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || \ + defined(CONFIG_STM32_TIM2_CAP) || \ + defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || \ + defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || \ + defined(CONFIG_STM32_TIM10_CAP) || \ + defined(CONFIG_STM32_TIM11_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || \ + defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) /**************************************************************************** * Private Types @@ -182,7 +182,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) { switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -209,7 +209,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -236,7 +236,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -263,7 +263,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -290,7 +290,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) } break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -320,7 +320,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -348,7 +348,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -376,7 +376,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -404,7 +404,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -432,7 +432,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -460,7 +460,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -488,7 +488,7 @@ stm32_cap_gpio(const struct stm32_cap_priv_s *priv, int channel) break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -528,31 +528,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM5EN; @@ -561,43 +561,43 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM9EN; break; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM10EN; break; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM11EN; break; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1ENR; mask = RCC_APB1ENR_TIM14EN; @@ -1082,7 +1082,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1094,7 +1094,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1106,7 +1106,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1118,7 +1118,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1130,7 +1130,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1144,7 +1144,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1156,7 +1156,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1168,7 +1168,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1180,7 +1180,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1192,7 +1192,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1204,7 +1204,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1216,7 +1216,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1232,54 +1232,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32F7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32F7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32F7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32F7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32F7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32F7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32F7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32F7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32F7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32F7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32F7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1336,4 +1336,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32f7/stm32_config.h b/arch/arm/src/stm32f7/stm32_config.h index c5a0cee3b6d..f4894e9ec7f 100644 --- a/arch/arm/src/stm32f7/stm32_config.h +++ b/arch/arm/src/stm32f7/stm32_config.h @@ -71,21 +71,21 @@ # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 2 # undef CONFIG_STM32F7_UART1 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 3 # undef CONFIG_STM32F7_UART2 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 4 # undef CONFIG_STM32F7_UART3 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #elif STM32_NUART < 5 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #endif /* Are any UARTs enabled? */ @@ -93,7 +93,7 @@ #undef HAVE_UART_DEVICE #if defined(CONFIG_STM32F7_UART0) || defined(CONFIG_STM32F7_UART1) || \ defined(CONFIG_STM32F7_UART2) || defined(CONFIG_STM32F7_UART3) || \ - defined(CONFIG_STM32F7_UART4) + defined(CONFIG_STM32_UART4) # define HAVE_UART_DEVICE 1 #endif @@ -107,29 +107,29 @@ # undef CONFIG_STM32F7_USART0 #endif #ifndef CONFIG_USART1_SERIALDRIVER -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif #ifndef CONFIG_USART2_SERIALDRIVER -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Don't enable USARTs not supported by the chip. */ #if STM32_NUSART < 1 # undef CONFIG_STM32F7_USART0 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 #elif STM32_NUSART < 2 -# undef CONFIG_STM32F7_USART1 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART1 +# undef CONFIG_STM32_USART2 #elif STM32_NUSART < 3 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif /* Are any USARTs enabled? */ -#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32F7_USART1) || \ - defined(CONFIG_STM32F7_USART2) +#if defined(CONFIG_STM32F7_USART0) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # undef HAVE_UART_DEVICE # define HAVE_UART_DEVICE 1 #endif @@ -199,7 +199,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -217,7 +217,7 @@ # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -226,7 +226,7 @@ # undef CONFIG_USART0_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # define HAVE_SERIAL_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_UART0_SERIAL_CONSOLE # undef CONFIG_UART1_SERIAL_CONSOLE # undef CONFIG_UART2_SERIAL_CONSOLE @@ -252,14 +252,14 @@ #if CHIP_NSPI < 1 # undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #elif CHIP_NSPI < 2 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif #ifndef CONFIG_STM32F7_HAVE_SPI # undef CONFIG_STM32F7_SPI0 -# undef CONFIG_STM32F7_SPI1 +# undef CONFIG_STM32_SPI1 #endif /* Are any SPI peripherals enabled? */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 4b1df56c919..c56d8bdf7c5 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -46,9 +46,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32F7_STM33F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Pre-processor Definitions @@ -596,7 +596,7 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, " ntransfers: %zu scr: %08" PRIx32 "\n", paddr, maddr, ntransfers, scr); -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_dmacapable(maddr, ntransfers, scr)); #endif @@ -895,7 +895,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; @@ -958,7 +958,7 @@ bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr) dmawarn("stm32_dmacapable:" " dcache unaligned maddr:0x%08" PRIxPTR " mend:0x%08" PRIx32 "\n", maddr, mend); -#if !defined(CONFIG_STM32F7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1121,4 +1121,4 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, } #endif -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index d858a62c14f..7ad69cd3ec2 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -242,7 +242,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32f7/stm32_dma2d.c b/arch/arm/src/stm32f7/stm32_dma2d.c index f8cd2d298bb..cb8cdc15fe6 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.c +++ b/arch/arm/src/stm32f7/stm32_dma2d.c @@ -91,7 +91,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_DMA2D_REGDEBUG +#ifdef CONFIG_STM32_DMA2D_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -109,7 +109,7 @@ struct stm32_dma2d_s { struct dma2d_layer_s dma2d; /* Public dma2d interface */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint32_t *clut; /* Color lookup table */ #endif @@ -172,7 +172,7 @@ static const uintptr_t stm32_color_layer_t[DMA2D_NLAYERS] = STM32_DMA2D_OCOLR }; -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* DMA2D clut memory address register */ static const uintptr_t stm32_cmar_layer_t[DMA2D_NLAYERS - 1] = @@ -192,7 +192,7 @@ static void stm32_dma2d_control(uint32_t setbits, uint32_t clrbits); static int stm32_dma2dirq(int irq, void *context, void *arg); static int stm32_dma2d_waitforirq(void); static int stm32_dma2d_start(void); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_loadclut(uintptr_t reg); #endif static uint32_t @@ -212,7 +212,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Public Functions */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap); #endif static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, @@ -239,15 +239,15 @@ static bool g_initialized; /* Allocate clut */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static uint32_t g_clut[STM32_DMA2D_NCLUT * -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY 4 # else 3 # endif / 4]; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The DMA2D mutex that enforces mutually exclusive access */ @@ -270,14 +270,14 @@ static struct stm32_dma2d_s g_dma2ddev = { .dma2d = { -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .setclut = stm32_dma2d_setclut, #endif .fillcolor = stm32_dma2d_fillcolor, .blit = stm32_dma2d_blit, .blend = stm32_dma2d_blend }, -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .clut = g_clut, #endif .lock = &g_lock @@ -344,7 +344,7 @@ static int stm32_dma2dirq(int irq, void *context, void *arg) putreg32(DMA2D_IFCR_CTCIF, STM32_DMA2D_IFCR); priv->error = OK; } -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 else if (regval & DMA2D_ISR_CTCIF) { /* CLUT transfer complete interrupt */ @@ -461,7 +461,7 @@ static int stm32_dma2d_waitforirq(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D_L8 +#ifdef CONFIG_STM32_DMA2D_L8 static int stm32_dma2d_loadclut(uintptr_t pfcreg) { int ret; @@ -681,7 +681,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, pfccrreg = DMA2D_XGPFCCR_CM(fmt); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (fmt == DMA2D_PF_L8) { struct stm32_dma2d_s *layer = &g_dma2ddev; @@ -692,7 +692,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, /* Set the CLUT color mode */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY pfccrreg |= DMA2D_XGPFCCR_CCM; # endif @@ -708,7 +708,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, stm32_dma2d_loadclut(stm32_pfccr_layer_t[lid]); } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Set alpha blend mode */ @@ -744,7 +744,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) { int n; @@ -760,7 +760,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) * blit operation becomes active */ -# ifndef CONFIG_STM32F7_FB_TRANSPARENCY +# ifndef CONFIG_STM32_FB_TRANSPARENCY uint8_t *clut = (uint8_t *)g_dma2ddev.clut; uint16_t offset = 3 * n; @@ -789,7 +789,7 @@ static int stm32_dma2d_setclut(const struct fb_cmap_s *cmap) nxmutex_unlock(priv->lock); return OK; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_dma2d_fillcolor @@ -822,7 +822,7 @@ static int stm32_dma2d_fillcolor(struct stm32_dma2d_overlay_s *oinfo, lcdinfo("oinfo=%p, argb=%08" PRIx32 "\n", oinfo, argb); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (oinfo->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1006,7 +1006,7 @@ static int stm32_dma2d_blend(struct stm32_dma2d_overlay_s *doverlay, "barea.h=%d\n", doverlay, destxpos, destypos, foverlay, forexpos, foreypos, boverlay, barea, barea->x, barea->y, barea->w, barea->h); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP if (doverlay->fmt == DMA2D_PF_L8) { /* CLUT output not supported */ @@ -1095,7 +1095,7 @@ int stm32_dma2dinitialize(void) * arch/arm/src/stm32f7/stm32f7xxxx_rcc.c */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Enable dma2d transfer and clut loading interrupts only */ stm32_dma2d_control(DMA2D_CR_TCIE | DMA2D_CR_CTCIE, DMA2D_CR_TEIE | diff --git a/arch/arm/src/stm32f7/stm32_dma2d.h b/arch/arm/src/stm32f7/stm32_dma2d.h index 0f84a7732bf..06ace50a01d 100644 --- a/arch/arm/src/stm32f7/stm32_dma2d.h +++ b/arch/arm/src/stm32f7/stm32_dma2d.h @@ -65,7 +65,7 @@ struct dma2d_layer_s * On error - -EINVAL */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP int (*setclut)(const struct fb_cmap_s * cmap); #endif diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index 980add5f69f..42997245544 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -43,11 +43,11 @@ /* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20010000 -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # define DTCM_START 0x20000000 # define DTCM_END 0x20020000 #else @@ -58,7 +58,7 @@ * heap. */ -#ifndef CONFIG_STM32F7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32f7/stm32_dumpgpio.c b/arch/arm/src/stm32f7/stm32_dumpgpio.c index 45820a0adca..727ac68639a 100644 --- a/arch/arm/src/stm32f7/stm32_dumpgpio.c +++ b/arch/arm/src/stm32f7/stm32_dumpgpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -144,5 +144,5 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ #endif /* CONFIG_DEBUG_GPIO_INFO */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.c b/arch/arm/src/stm32f7/stm32_ethernet.c index 668418a15ca..8b281e2f31b 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.c +++ b/arch/arm/src/stm32f7/stm32_ethernet.c @@ -66,11 +66,11 @@ #include /* STM32_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32F7_ETHMAC will defined if + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32F7 Ethernet support is enabled in the configuration. */ -#if STM32_NETHERNET > 0 && defined(CONFIG_STM32F7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -101,76 +101,76 @@ #define ETHWORK LPWORK -#ifndef CONFIG_STM32F7_PHYADDR -# error "CONFIG_STM32F7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32F7_MII) && !defined(CONFIG_STM32F7_RMII) -# warning "Neither CONFIG_STM32F7_MII nor CONFIG_STM32F7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32F7_MII) && defined(CONFIG_STM32F7_RMII) -# error "Both CONFIG_STM32F7_MII and CONFIG_STM32F7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32F7_MII -# if !defined(CONFIG_STM32F7_MII_MCO1) && !defined(CONFIG_STM32F7_MII_MCO2) && \ - !defined(CONFIG_STM32F7_MII_EXTCLK) -# warning "Neither CONFIG_STM32F7_MII_MCO1, CONFIG_STM32F7_MII_MCO2, nor CONFIG_STM32F7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_MII_MCO1) && defined(CONFIG_STM32F7_MII_MCO2) -# error "Both CONFIG_STM32F7_MII_MCO1 and CONFIG_STM32F7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_RMII -# if !defined(CONFIG_STM32F7_RMII_MCO1) && !defined(CONFIG_STM32F7_RMII_MCO2) && \ - !defined(CONFIG_STM32F7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32F7_RMII_MCO1, CONFIG_STM32F7_RMII_MCO2, nor CONFIG_STM32F7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32F7_RMII_MCO1) && defined(CONFIG_STM32F7_RMII_MCO2) -# error "Both CONFIG_STM32F7_RMII_MCO1 and CONFIG_STM32F7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32F7_AUTONEG -# ifndef CONFIG_STM32F7_PHYSR -# error "CONFIG_STM32F7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32F7_PHYSR_ALTMODE -# error "CONFIG_STM32F7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10HD -# error "CONFIG_STM32F7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100HD -# error "CONFIG_STM32F7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_10FD -# error "CONFIG_STM32F7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100FD -# error "CONFIG_STM32F7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32F7_PHYSR_SPEED -# error "CONFIG_STM32F7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_100MBPS -# error "CONFIG_STM32F7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_MODE -# error "CONFIG_STM32F7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32F7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32F7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP -# warning "CONFIG_STM32F7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* This driver does not use enhanced descriptors. Enhanced descriptors must @@ -178,8 +178,8 @@ * supported. */ -#undef CONFIG_STM32F7_ETH_ENHANCEDDESC -#undef CONFIG_STM32F7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_ENHANCEDDESC +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -207,16 +207,16 @@ # warning "You using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32F7_ETH_NRXDESC -# define CONFIG_STM32F7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32F7_ETH_NTXDESC -# define CONFIG_STM32F7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32F7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers use for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -231,7 +231,7 @@ #define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK) #define DMA_ALIGN_DOWN(n) ((n) & ~DMA_BUFFER_MASK) -#ifndef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifndef CONFIG_STM32_ETH_ENHANCEDDESC # define RXDESC_SIZE 16 # define TXDESC_SIZE 16 #else @@ -243,10 +243,10 @@ #define TXDESC_PADSIZE DMA_ALIGN_UP(TXDESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32F7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32F7_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -257,7 +257,7 @@ */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32F7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -338,7 +338,7 @@ * ETH_MACCR_APCS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_RD Retry disable 1 (disabled) * ETH_MACCR_IPCO IPv4 checksum offload Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_ROD Receive own disable 0 (enabled) * ETH_MACCR_CSD Carrier sense disable 0 (enabled) @@ -353,7 +353,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_IFG(96)) #else @@ -471,13 +471,13 @@ * ETH_DMAOMR_TTC Transmit threshold control 0 (64 bytes) * ETH_DMAOMR_FTF Flush transmit FIFO 0 (no flush) * ETH_DMAOMR_TSF Transmit store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * ETH_DMAOMR_DFRF Disable flushing of 0 (enabled) * received frames * ETH_DMAOMR_RSF Receive store and forward Depends on - * CONFIG_STM32F7_ETH_HWCHECKSUM + * CONFIG_STM32_ETH_HWCHECKSUM * TH_DMAOMR_DTCEFD Dropping of TCP/IP checksum Depends on - * error frames disable CONFIG_STM32F7_ETH_HWCHECKSUM + * error frames disable CONFIG_STM32_ETH_HWCHECKSUM * * When the checksum offload feature is enabled, we need to enable the Store * and Forward mode: the store and forward guarantee that a whole frame is @@ -485,7 +485,7 @@ * checksum is OK the DMA can handle the frame otherwise the frame is dropped */ -#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define DMAOMR_SET_MASK \ (ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \ ETH_DMAOMR_TSF | ETH_DMAOMR_RSF) @@ -525,7 +525,7 @@ * ETH_DMABMR_DA DMA Arbitration 0 (round robin) * ETH_DMABMR_DSL Descriptor skip length 0 * ETH_DMABMR_EDFE Enhanced descriptor Depends on - * format enable CONFIG_STM32F7_ETH_ENHANCEDDESC + * format enable CONFIG_STM32_ETH_ENHANCEDDESC * ETH_DMABMR_PBL Programmable burst length 32 beats * ETH_DMABMR_RTPR RX TX priority ratio 2:1 * ETH_DMABMR_FB Fixed burst 1 (enabled) @@ -536,7 +536,7 @@ * ETH_DMABMR_MB Mixed burst 0 (disabled, F2/F4 only) */ -#ifdef CONFIG_STM32F7_ETH_ENHANCEDDESC +#ifdef CONFIG_STM32_ETH_ENHANCEDDESC # define DMABMR_SET_MASK \ (ETH_DMABMR_DSL(0) | ETH_DMABMR_PBL(32) | ETH_DMABMR_EDFE | ETH_DMABMR_RTPR_2TO1 | \ ETH_DMABMR_FB | ETH_DMABMR_RDP(32) | ETH_DMABMR_USP | ETH_DMABMR_AAB) @@ -667,7 +667,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -754,10 +754,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv); /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -787,7 +787,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -859,7 +859,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -886,7 +886,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1210,7 +1210,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * un-stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32F7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMAINT_RI); } @@ -1284,7 +1284,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) != 0 || @@ -1353,7 +1353,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES0_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32F7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0 && @@ -1582,8 +1582,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && - i < CONFIG_STM32F7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32F7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is the first segment in the frame */ @@ -2657,7 +2657,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].txdesc; @@ -2681,7 +2681,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NTXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NTXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2751,7 +2751,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32F7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].rxdesc; @@ -2773,7 +2773,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * the Next Descriptor Polling Enable */ - if (i < (CONFIG_STM32F7_ETH_NRXDESC - 1)) + if (i < (CONFIG_STM32_ETH_NRXDESC - 1)) { /* Set next descriptor address register with next descriptor base * address @@ -2863,7 +2863,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32F7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3070,7 +3070,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3090,7 +3090,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) /* Now check the "DAVICOM Specified Configuration Register (DSCR)"(16) */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3128,7 +3128,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3149,7 +3149,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_RESET); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3160,7 +3160,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform any necessary, board-specific PHY initialization */ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT ret = stm32_phy_boardinitialize(0); if (ret < 0) { @@ -3181,12 +3181,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32F7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3208,7 +3208,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3219,7 +3219,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3241,7 +3241,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32F7_PHYADDR, CONFIG_STM32F7_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3250,38 +3250,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32F7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. - * IF This CONFIG_STM32F7_PHYSR_ALTCONFIG is selected, this indicates that + * IF This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for example, * with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32F7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32F7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32F7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32F7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32F7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3294,13 +3294,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32F7_PHYSR_MODE) == - CONFIG_STM32F7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32F7_PHYSR_SPEED) == CONFIG_STM32F7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3309,14 +3309,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32F7_PHYADDR, MII_MCR, phyval); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3327,10 +3327,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32F7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32F7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3356,7 +3356,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3381,7 +3381,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3412,7 +3412,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32F7_MII) || defined(CONFIG_STM32F7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ @@ -3421,7 +3421,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the MII interface */ -# if defined(CONFIG_STM32F7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3436,7 +3436,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3444,7 +3444,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3452,7 +3452,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3483,7 +3483,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32F7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3498,7 +3498,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32F7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3506,7 +3506,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3514,7 +3514,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32F7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3538,7 +3538,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -3861,12 +3861,12 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list: Chain Mode */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32F7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list: Chain Mode */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32F7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Enable normal MAC operation */ @@ -3995,4 +3995,4 @@ void arm_netinitialize(void) } #endif -#endif /* STM32_NETHERNET > 0 && CONFIG_STM32F7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32f7/stm32_ethernet.h b/arch/arm/src/stm32f7/stm32_ethernet.h index b33dd2a646d..c23f2dcd217 100644 --- a/arch/arm/src/stm32f7/stm32_ethernet.h +++ b/arch/arm/src/stm32f7/stm32_ethernet.h @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32F7_PHYINIT is defined in the + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the * configuration then the board specific logic must provide * stm32_phyinitialize(); The STM32 Ethernet driver will call this * function one time before it first uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif diff --git a/arch/arm/src/stm32f7/stm32_exti_gpio.c b/arch/arm/src/stm32f7/stm32_exti_gpio.c index 39f3c0a943d..4081d9cba24 100644 --- a/arch/arm/src/stm32f7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32f7/stm32_exti_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Types @@ -376,4 +376,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */ +#endif /* CONFIG_STM32_STM32F74XX || CONFIG_STM32_STM32F75XX */ diff --git a/arch/arm/src/stm32f7/stm32_fmc.c b/arch/arm/src/stm32f7/stm32_fmc.c index 03eaea6826d..d5e955133a4 100644 --- a/arch/arm/src/stm32f7/stm32_fmc.c +++ b/arch/arm/src/stm32f7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32F7_FMC) +#if defined(CONFIG_STM32_FMC) #include #include @@ -234,4 +234,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(val, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32F7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index aeaea51aa19..5932b37c80d 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -89,22 +89,22 @@ /* PWM lower-half ops and ADC lower-half ops must be enabled */ -#ifndef CONFIG_STM32F7_PWM_LL_OPS +#ifndef CONFIG_STM32_PWM_LL_OPS # error PWM low-level operations interface must be enabled #endif -#ifndef CONFIG_STM32F7_ADC_LL_OPS +#ifndef CONFIG_STM32_ADC_LL_OPS # error ADC low-level operations interface must be enabled #endif /* We don't want start conversion during ADC setup */ -#ifndef CONFIG_STM32F7_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV # error ADC startup conversion must be disabled #endif /* We need interface to change ADC sample-time */ -#ifndef CONFIG_STM32F7_ADC_CHANGE_SAMPLETIME +#ifndef CONFIG_STM32_ADC_CHANGE_SAMPLETIME # error ADC sample-time configuration interface must be enabled #endif @@ -114,35 +114,35 @@ /* FOC0 always use TIMER1 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# if CONFIG_STM32F7_TIM1_MODE != 2 +# if CONFIG_STM32_TIM1_MODE != 2 # error TIM1 must be configured in center-aligned mode 1 # endif -#endif /* CONFIG_STM32F7_FOC_FOC0 */ +#endif /* CONFIG_STM32_FOC_FOC0 */ /* FOC1 always use TIMER8 for PWM */ -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# if CONFIG_STM32F7_TIM8_MODE != 2 +# if CONFIG_STM32_TIM8_MODE != 2 # error TIM8 must be configured in center-aligned mode 1 # endif #endif /* The maximum supported number of phases depends on the ADC trigger */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) # if CONFIG_MOTOR_FOC_PHASES > 3 # error max 3 phases supported # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) # if CONFIG_MOTOR_FOC_PHASES > 4 # error max 4 phases supported # endif @@ -158,7 +158,7 @@ /* Only one ADC trigger must be selected */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) && defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) && defined(CONFIG_STM32_FOC_ADC_TRGO) # error Invalid ADC trigger configuration #endif @@ -174,7 +174,7 @@ * V0 for CNTR = 0 */ -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* FOC ADC trigger on CCR4 **************************************************/ @@ -183,12 +183,12 @@ * - 1 channel for ADC injection sequence trigger (CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES + 1) # error Invalid channels configuration # endif @@ -202,10 +202,10 @@ * TIMx CCR4 = (ARR - trigger_offset) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1CC4 (ADC_CR2_JEXTSEL_T1CC4) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # define ADC_JEXTSEL_T8CC4 (ADC_CR2_JEXTSEL_T8CC4) #endif @@ -213,20 +213,20 @@ # define ADC_TRIGGER_OFFSET (1) -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1CC4) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8CC4) # endif -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* FOC ADC trigger on TRGO **************************************************/ /* PWM TRGO support must be enabled */ -# ifndef CONFIG_STM32F7_PWM_TRGO +# ifndef CONFIG_STM32_PWM_TRGO # error PWM TRGO support must be enabled # endif @@ -238,12 +238,12 @@ * - n channels for phases PWM (CCR1, CCR2, CCR3, CCR4) */ -# if defined(CONFIG_STM32F7_FOC_FOC0) +# if defined(CONFIG_STM32_FOC_FOC0) # if FOC0_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif # endif -# if defined(CONFIG_STM32F7_FOC_FOC1) +# if defined(CONFIG_STM32_FOC_FOC1) # if FOC1_PWM_NCHANNELS != (CONFIG_MOTOR_FOC_PHASES) # error Invalid channels configuration # endif @@ -257,17 +257,17 @@ * TIMx TRGO = (ARR) */ -#ifdef CONFIG_STM32F7_FOC_USE_TIM1 +#ifdef CONFIG_STM32_FOC_USE_TIM1 # define ADC_JEXTSEL_T1TRGO (ADC_CR2_JEXTSEL_T1TRGO) #endif -#ifdef CONFIG_STM32F7_FOC_USE_TIM8 +#ifdef CONFIG_STM32_FOC_USE_TIM8 # error TIM8 and TRGO trigger not supported for ADC IPv1 #endif -# ifdef CONFIG_STM32F7_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXTSEL (ADC_JEXTSEL_T1TRGO) # endif -# ifdef CONFIG_STM32F7_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXTSEL (ADC_JEXTSEL_T8TRGO) # endif @@ -280,28 +280,28 @@ /* Phase current samples for FOC0 */ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC 3 # endif #endif /* Phase current samples for FOC1 */ -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC 1 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC 2 # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC 3 # endif #endif @@ -316,55 +316,55 @@ * 3. ADC software trigger starts only regular conversion. */ -#ifdef CONFIG_STM32F7_FOC_USE_ADC1 -# ifndef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_FOC_USE_ADC1 +# ifndef CONFIG_STM32_ADC1 # error ADC1 not supported ! # endif # ifndef ADC1_HAVE_JEXTCFG # error ADC1 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC1_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC1_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC1_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC1_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC1_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC1 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC2 -# ifndef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_FOC_USE_ADC2 +# ifndef CONFIG_STM32_ADC2 # error ADC2 not supported ! # endif # ifndef ADC2_HAVE_JEXTCFG # error ADC2 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC2_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC2_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC2_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC2_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC2_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC2 injected channels # endif #endif -#ifdef CONFIG_STM32F7_FOC_USE_ADC3 -# ifndef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_FOC_USE_ADC3 +# ifndef CONFIG_STM32_ADC3 # error ADC3 not supported ! # endif # ifndef ADC3_HAVE_JEXTCFG # error ADC3 must support JEXTCFG # endif -# if CONFIG_STM32F7_ADC3_ANIOC_TRIGGER != 1 -# error CONFIG_STM32F7_ADC3_ANIOC_TRIGGER must be 1 +# if CONFIG_STM32_ADC3_ANIOC_TRIGGER != 1 +# error CONFIG_STM32_ADC3_ANIOC_TRIGGER must be 1 # endif -# if CONFIG_STM32F7_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED +# if CONFIG_STM32_ADC3_INJECTED_CHAN != FOC_ADC_INJ_CHAN_REQUIRED # error Invalid configuration for ADC3 injected channels # endif #endif /* Combine JEXTSEL with JEXTEN default */ -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 # define FOC0_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC0_ADC_JEXTSEL) #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 # define FOC1_ADC_JEXT (ADC_JEXTREG_JEXTEN_DEFAULT | FOC1_ADC_JEXTSEL) #endif @@ -390,39 +390,39 @@ /* FOC ADC configuration ****************************************************/ -#ifdef CONFIG_STM32F7_FOC_FOC0 -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC1 +#ifdef CONFIG_STM32_FOC_FOC0 +# ifdef CONFIG_STM32_FOC_FOC0_ADC1 # define FOC0_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC0_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC2 +# ifdef CONFIG_STM32_FOC_FOC0_ADC2 # define FOC0_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC0_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC3 +# ifdef CONFIG_STM32_FOC_FOC0_ADC3 # define FOC0_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC0_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC0_ADC4 +# ifdef CONFIG_STM32_FOC_FOC0_ADC4 # define FOC0_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC0_ADC_CMN FOC_ADC4_CMN # endif #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC1 +#ifdef CONFIG_STM32_FOC_FOC1 +# ifdef CONFIG_STM32_FOC_FOC1_ADC1 # define FOC1_ADC_IRQ STM32_IRQ_ADC1_FOC # define FOC1_ADC_CMN FOC_ADC1_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC2 +# ifdef CONFIG_STM32_FOC_FOC1_ADC2 # define FOC1_ADC_IRQ STM32_IRQ_ADC2_FOC # define FOC1_ADC_CMN FOC_ADC2_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC3 +# ifdef CONFIG_STM32_FOC_FOC1_ADC3 # define FOC1_ADC_IRQ STM32_IRQ_ADC3_FOC # define FOC1_ADC_CMN FOC_ADC3_CMN # endif -# ifdef CONFIG_STM32F7_FOC_FOC1_ADC4 +# ifdef CONFIG_STM32_FOC_FOC1_ADC4 # define FOC1_ADC_IRQ STM32_IRQ_ADC4_FOC # define FOC1_ADC_CMN FOC_ADC4_CMN # endif @@ -502,7 +502,7 @@ /* Define PWM all outputs */ -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # define PMW_OUTPUTS_ALL_COMP (STM32_PWM_OUT1N| \ STM32_PWM_OUT2N| \ STM32_PWM_OUT3N) @@ -510,7 +510,7 @@ # define PMW_OUTPUTS_ALL_COMP (0) #endif -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) || (CONFIG_MOTOR_FOC_PHASES > 3) # define PMW_OUTPUTS_ALL_OUT4 (STM32_PWM_OUT4) #else # define PMW_OUTPUTS_ALL_OUT4 (0) @@ -683,10 +683,10 @@ static int stm32_foc_adc_start(struct foc_dev_s *dev, bool state); static int stm32_foc_calibration_start(struct foc_dev_s *dev); static int stm32_foc_pwm_freq_set(struct foc_dev_s *dev, uint32_t freq); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, uint32_t offset); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) static void stm32_foc_adc_trgo_trg_set(struct foc_dev_s *dev, uint8_t rcr); #else @@ -813,7 +813,7 @@ static int stm32_foc_pwm_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#ifdef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifdef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY /* Configure deadtime */ PWM_DT_UPDATE(pwm, (uint8_t)board->data->pwm_dt); @@ -1015,7 +1015,7 @@ static int stm32_foc_adc_cfg(struct foc_dev_s *dev) return OK; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /**************************************************************************** * Name: stm32_foc_adc_ccr4_trg_set @@ -1047,7 +1047,7 @@ static void stm32_foc_adc_ccr4_trg_set(struct foc_dev_s *dev, PWM_CCR_UPDATE(pwm, STM32_PWM_CHAN4, offset); } -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /**************************************************************************** * Name: stm32_foc_adc_trgo_trg_set @@ -1140,9 +1140,9 @@ static int stm32_foc_configure(struct foc_dev_s *dev, DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, (dev->cfg.pwm_freq / priv->data.adc_freq) * 2); #else @@ -1156,7 +1156,7 @@ static int stm32_foc_configure(struct foc_dev_s *dev, /* REVISIT: synchronise instances if TRGO trigger selected */ #if (CONFIG_MOTOR_FOC_INST > 1) -# if defined(CONFIG_STM32F7_FOC_ADC_TRGO) +# if defined(CONFIG_STM32_FOC_ADC_TRGO) # error stm32_foc_sync_all breaks TRGO event on V0 vector # endif @@ -1704,9 +1704,9 @@ static int stm32_foc_calibration_start(struct foc_dev_s *dev) DEBUGASSERT(priv->data.per != 0); -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) stm32_foc_adc_ccr4_trg_set(dev, (priv->data.per - ADC_TRIGGER_OFFSET)); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) stm32_foc_adc_trgo_trg_set(dev, 1); #else # error Invalid FOC ADC trigger @@ -2039,7 +2039,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) goto errout; } -#if defined(CONFIG_STM32F7_FOC_ADC_CCR4) +#if defined(CONFIG_STM32_FOC_ADC_CCR4) /* ADC interrupts frequency is PWM frequency */ priv->data.adc_freq = dev->cfg.pwm_freq; @@ -2048,7 +2048,7 @@ static int stm32_foc_notifier_cfg(struct foc_dev_s *dev, uint32_t freq) priv->data.notifier_div = (dev->cfg.pwm_freq / freq); -#elif defined(CONFIG_STM32F7_FOC_ADC_TRGO) +#elif defined(CONFIG_STM32_FOC_ADC_TRGO) /* Call work on every ADC interrupt */ priv->data.notifier_div = 1; @@ -2250,7 +2250,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) switch (inst) { -#ifdef CONFIG_STM32F7_FOC_FOC0 +#ifdef CONFIG_STM32_FOC_FOC0 case 0: { pwm_inst = FOC0_PWM; @@ -2264,7 +2264,7 @@ stm32_foc_initialize(int inst, struct stm32_foc_board_s *board) } #endif -#ifdef CONFIG_STM32F7_FOC_FOC1 +#ifdef CONFIG_STM32_FOC_FOC1 case 1: { pwm_inst = FOC1_PWM; diff --git a/arch/arm/src/stm32f7/stm32_gpio.c b/arch/arm/src/stm32f7/stm32_gpio.c index 27455106e85..611cf9987fd 100644 --- a/arch/arm/src/stm32f7/stm32_gpio.c +++ b/arch/arm/src/stm32f7/stm32_gpio.c @@ -44,9 +44,9 @@ * families */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) \ - || defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) \ - || defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) \ + || defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) \ + || defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Private Data @@ -502,4 +502,4 @@ void stm32_iocompensation(void) } } -#endif /* CONFIG_STM32F7_STM32F72XX || ... || CONFIG_STM32F7_STM32F77XX */ +#endif /* CONFIG_STM32_STM32F72XX || ... || CONFIG_STM32_STM32F77XX */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.c b/arch/arm/src/stm32f7/stm32_i2c.c index e805129f8e8..4c3dc112a8b 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.c +++ b/arch/arm/src/stm32f7/stm32_i2c.c @@ -155,34 +155,34 @@ * * One of: * - * CONFIG_STM32F7_STM32F72XX - * CONFIG_STM32F7_STM32F73XX - * CONFIG_STM32F7_STM32F74XX - * CONFIG_STM32F7_STM32F75XX - * CONFIG_STM32F7_STM32F76XX - * CONFIG_STM32F7_STM32F77XX + * CONFIG_STM32_STM32F72XX + * CONFIG_STM32_STM32F73XX + * CONFIG_STM32_STM32F74XX + * CONFIG_STM32_STM32F75XX + * CONFIG_STM32_STM32F76XX + * CONFIG_STM32_STM32F77XX * * * and one or more interfaces: * - * CONFIG_STM32F7_I2C1 - * CONFIG_STM32F7_I2C2 - * CONFIG_STM32F7_I2C3 - * CONFIG_STM32F7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32F7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32F7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32F7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32F7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32F7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -256,8 +256,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32F7_I2C1) || defined(CONFIG_STM32F7_I2C2) || \ - defined(CONFIG_STM32F7_I2C3) || defined(CONFIG_STM32F7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -265,25 +265,25 @@ #undef INVALID_CLOCK_SOURCE -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 # if STM32_RCC_DCKCFGR2_I2C1SRC != RCC_DCKCFGR2_I2C1SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C1SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 # if STM32_RCC_DCKCFGR2_I2C2SRC != RCC_DCKCFGR2_I2C2SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C2SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 # if STM32_RCC_DCKCFGR2_I2C3SRC != RCC_DCKCFGR2_I2C3SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C3SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_DCKCFGR2_I2C4SRC != RCC_DCKCFGR2_I2C4SEL_HSI # warning "Clock Source STM32_RCC_DCKCFGR2_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -300,25 +300,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32F7_I2CTIMEOSEC) && !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 -# define CONFIG_STM32F7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32F7_I2CTIMEOSEC) -# define CONFIG_STM32F7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32F7_I2CTIMEOMS) -# define CONFIG_STM32F7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32F7_I2CTIMEOTICKS -# define CONFIG_STM32F7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32F7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32F7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32F7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -482,9 +482,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32F7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -534,7 +534,7 @@ static const struct i2c_ops_s stm32_i2c_ops = #endif }; -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -571,7 +571,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -608,7 +608,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -645,7 +645,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -766,7 +766,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -783,7 +783,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -839,12 +839,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32F7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -882,10 +882,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32F7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32F7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2740,22 +2740,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2827,5 +2827,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || \ - * CONFIG_STM32F7_I2C3 || CONFIG_STM32F7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32f7/stm32_i2c.h b/arch/arm/src/stm32f7/stm32_i2c.h index e9bb1656b29..4580980d9d4 100644 --- a/arch/arm/src/stm32f7/stm32_i2c.h +++ b/arch/arm/src/stm32f7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32F7_I2C_DYNTIMEO -# if CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32F7_I2C_DYNTIMEO because of CONFIG_STM32F7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32F7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c index 53b8e44da21..3bb12864f51 100644 --- a/arch/arm/src/stm32f7/stm32_i2s.c +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -76,7 +76,7 @@ #include "stm32_spi.h" #include "stm32_rcc.h" -#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_I2S1) || defined(CONFIG_STM32_I2S2) || defined(CONFIG_STM32_I2S3) /**************************************************************************** * Pre-processor Definitions @@ -92,8 +92,8 @@ # error CONFIG_AUDIO required by this driver #endif -#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT -# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16 +#ifndef CONFIG_STM32_I2S_MAXINFLIGHT +# define CONFIG_STM32_I2S_MAXINFLIGHT 16 #endif /* Assume no RX/TX support until we learn better */ @@ -103,28 +103,28 @@ /* Check for I2S RX support */ -# if defined(CONFIG_STM32F7_I2S1_RX) +# if defined(CONFIG_STM32_I2S1_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_RX) +# if defined(CONFIG_STM32_I2S2_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_RX) +# if defined(CONFIG_STM32_I2S3_RX) # define I2S_HAVE_RX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -132,28 +132,28 @@ /* Check for I2S3 TX support */ -# if defined(CONFIG_STM32F7_I2S1_TX) +# if defined(CONFIG_STM32_I2S1_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S1_MCK +# ifdef CONFIG_STM32_I2S1_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S2_TX) +# if defined(CONFIG_STM32_I2S2_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S2_MCK +# ifdef CONFIG_STM32_I2S2_MCK # define I2S_HAVE_MCK 1 # endif # endif -# if defined(CONFIG_STM32F7_I2S3_TX) +# if defined(CONFIG_STM32_I2S3_TX) # define I2S_HAVE_TX 1 -# ifdef CONFIG_STM32F7_I2S3_MCK +# ifdef CONFIG_STM32_I2S3_MCK # define I2S_HAVE_MCK 1 # endif @@ -163,19 +163,19 @@ /* I2S interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven I2S not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -200,7 +200,7 @@ # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /* Debug ********************************************************************/ @@ -209,8 +209,8 @@ */ #ifndef CONFIG_DEBUG_I2S_INFO -# undef CONFIG_STM32F7_I2S_DMADEBUG -# undef CONFIG_STM32F7_I2S_REGDEBUG +# undef CONFIG_STM32_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_REGDEBUG # undef CONFIG_STM32F7_I2S_QDEBUG # undef CONFIG_STM32F7_I2S_DUMPBUFFERS #endif @@ -219,46 +219,46 @@ * logic here is constrained to byte, half-word, and word sizes. */ -#ifndef CONFIG_STM32F7_I2S1_DATALEN -# define CONFIG_STM32F7_I2S1_DATALEN 16 +#ifndef CONFIG_STM32_I2S1_DATALEN +# define CONFIG_STM32_I2S1_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S2_DATALEN -# define CONFIG_STM32F7_I2S2_DATALEN 16 +#ifndef CONFIG_STM32_I2S2_DATALEN +# define CONFIG_STM32_I2S2_DATALEN 16 #endif -#ifndef CONFIG_STM32F7_I2S3_DATALEN -# define CONFIG_STM32F7_I2S3_DATALEN 16 +#ifndef CONFIG_STM32_I2S3_DATALEN +# define CONFIG_STM32_I2S3_DATALEN 16 #endif -#if CONFIG_STM32F7_I2S1_DATALEN == 8 +#if CONFIG_STM32_I2S1_DATALEN == 8 # define STM32_I2S1_DATAMASK 0 -#elif CONFIG_STM32F7_I2S1_DATALEN == 16 +#elif CONFIG_STM32_I2S1_DATALEN == 16 # define STM32_I2S1_DATAMASK 1 -#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN +#elif CONFIG_STM32_I2S1_DATALEN < 8 || CONFIG_STM32_I2S1_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S1_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S2_DATALEN == 8 +#if CONFIG_STM32_I2S2_DATALEN == 8 # define STM32_I2S2_DATAMASK 0 -#elif CONFIG_STM32F7_I2S2_DATALEN == 16 +#elif CONFIG_STM32_I2S2_DATALEN == 16 # define STM32_I2S2_DATAMASK 1 -#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN +#elif CONFIG_STM32_I2S2_DATALEN < 8 || CONFIG_STM32_I2S2_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S2_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S1_DATALEN #endif -#if CONFIG_STM32F7_I2S3_DATALEN == 8 +#if CONFIG_STM32_I2S3_DATALEN == 8 # define STM32_I2S3_DATAMASK 0 -#elif CONFIG_STM32F7_I2S3_DATALEN == 16 +#elif CONFIG_STM32_I2S3_DATALEN == 16 # define STM32_I2S3_DATAMASK 1 -#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 -# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN +#elif CONFIG_STM32_I2S3_DATALEN < 8 || CONFIG_STM32_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32_I2S3_DATALEN #else -# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN +# error Valid but supported value for CONFIG_STM32_I2S3_DATALEN #endif /* Check if we need to build RX and/or TX support */ @@ -266,7 +266,7 @@ #if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_I2S_DMADEBUG +# undef CONFIG_STM32_I2S_DMADEBUG #endif #define DMA_INITIAL 0 @@ -309,7 +309,7 @@ struct stm32_transport_s sq_queue_t done; /* A queue of completed transfers */ struct work_s work; /* Supports worker thread operations */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif }; @@ -344,11 +344,11 @@ struct stm32_i2s_s sem_t bufsem; /* Buffer wait semaphore */ struct stm32_buffer_s *freelist; /* A list a free buffer containers */ - struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT]; + struct stm32_buffer_s containers[CONFIG_STM32_I2S_MAXINFLIGHT]; /* Debug stuff */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG bool wr; /* Last was a write */ uint32_t regaddr; /* Last address */ uint16_t regval; /* Last value */ @@ -362,7 +362,7 @@ struct stm32_i2s_s /* Register helpers */ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr); #else @@ -397,12 +397,12 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) # define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) # define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -414,7 +414,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); #endif -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) # define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) # define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); @@ -467,15 +467,15 @@ static int i2s_dma_flags(struct stm32_i2s_s *priv); static int i2s_dma_allocate(struct stm32_i2s_s *priv); static void i2s_dma_free(struct stm32_i2s_s *priv); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv); #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv); #endif @@ -520,7 +520,7 @@ static const struct i2s_ops_s g_i2sops = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, uint32_t regaddr) { @@ -579,7 +579,7 @@ static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint32_t regaddr = priv->base + offset; uint16_t regval = getreg16(regaddr); -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, false, regval, regaddr)) { i2sinfo("%08" PRIx32 "->%04x\n", regaddr, regval); @@ -610,7 +610,7 @@ static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, { uint32_t regaddr = priv->base + offset; -#ifdef CONFIG_STM32F7_I2S_REGDEBUG +#ifdef CONFIG_STM32_I2S_REGDEBUG if (i2s_checkreg(priv, true, regval, regaddr)) { i2sinfo("%08" PRIx32 "<-%04x\n", regaddr, regval); @@ -759,9 +759,9 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) int i; priv->freelist = NULL; - nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT); + nxsem_init(&priv->bufsem, 0, CONFIG_STM32_I2S_MAXINFLIGHT); - for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++) + for (i = 0; i < CONFIG_STM32_I2S_MAXINFLIGHT; i++) { i2s_buf_free(priv, &priv->containers[i]); } @@ -771,7 +771,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * Name: i2s_dma_sampleinit * * Description: - * Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG) + * Initialize sampling of DMA registers (if CONFIG_STM32_I2S_DMADEBUG) * * Input Parameters: * priv - I2S state instance @@ -781,7 +781,7 @@ static void i2s_buf_initialize(struct stm32_i2s_s *priv) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) +#if defined(CONFIG_STM32_I2S_DMADEBUG) static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, struct stm32_transport_s *xpt) { @@ -809,7 +809,7 @@ static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_RX) static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -875,7 +875,7 @@ static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +#if defined(CONFIG_STM32_I2S_DMADEBUG) && defined(I2S_HAVE_TX) static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) { i2sinfo("result: %d\n", result); @@ -1145,7 +1145,7 @@ static void i2s_rx_worker(void *arg) if (sq_empty(&priv->rx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); if (bfcontainer) { @@ -1543,7 +1543,7 @@ static void i2s_tx_worker(void *arg) if (sq_empty(&priv->tx.act)) { -#ifdef CONFIG_STM32F7_I2S_DMADEBUG +#ifdef CONFIG_STM32_I2S_DMADEBUG bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); if (bfcontainer) { @@ -2441,7 +2441,7 @@ static void i2s_dma_free(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 static void i2s1_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2450,7 +2450,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S1_BASE; -#ifdef CONFIG_STM32F7_I2S1_RX +#ifdef CONFIG_STM32_I2S1_RX priv->rxenab = true; if (!priv->initialized) @@ -2463,9 +2463,9 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_RX */ +#endif /* CONFIG_STM32_I2S1_RX */ -#ifdef CONFIG_STM32F7_I2S1_TX +#ifdef CONFIG_STM32_I2S1_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2480,16 +2480,16 @@ static void i2s1_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S1_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S1_TX */ +#endif /* CONFIG_STM32_I2S1_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; + priv->datalen = CONFIG_STM32_I2S1_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S1 */ +#endif /* CONFIG_STM32_I2S1 */ /**************************************************************************** * Name: i2s2_configure @@ -2506,7 +2506,7 @@ static void i2s1_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 static void i2s2_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2515,7 +2515,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S2_BASE; -#ifdef CONFIG_STM32F7_I2S2_RX +#ifdef CONFIG_STM32_I2S2_RX priv->rxenab = true; if (!priv->initialized) @@ -2528,9 +2528,9 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_RX */ +#endif /* CONFIG_STM32_I2S2_RX */ -#ifdef CONFIG_STM32F7_I2S2_TX +#ifdef CONFIG_STM32_I2S2_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2545,16 +2545,16 @@ static void i2s2_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S2_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S2_TX */ +#endif /* CONFIG_STM32_I2S2_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; + priv->datalen = CONFIG_STM32_I2S2_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S2_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S2 */ +#endif /* CONFIG_STM32_I2S2 */ /**************************************************************************** * Name: i2s3_configure @@ -2571,7 +2571,7 @@ static void i2s2_configure(struct stm32_i2s_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 static void i2s3_configure(struct stm32_i2s_s *priv) { /* Configure multiplexed pins as connected on the board. Chip @@ -2580,7 +2580,7 @@ static void i2s3_configure(struct stm32_i2s_s *priv) priv->base = STM32_I2S3_BASE; -#ifdef CONFIG_STM32F7_I2S3_RX +#ifdef CONFIG_STM32_I2S3_RX priv->rxenab = true; if (!priv->initialized) @@ -2593,9 +2593,9 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_RX */ +#endif /* CONFIG_STM32_I2S3_RX */ -#ifdef CONFIG_STM32F7_I2S3_TX +#ifdef CONFIG_STM32_I2S3_TX priv->txenab = true; /* Only configure if the port is not already configured */ @@ -2610,16 +2610,16 @@ static void i2s3_configure(struct stm32_i2s_s *priv) stm32_configgpio(GPIO_I2S3_WS); priv->initialized = true; } -#endif /* CONFIG_STM32F7_I2S3_TX */ +#endif /* CONFIG_STM32_I2S3_TX */ /* Configure driver state specific to this I2S peripheral */ - priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; + priv->datalen = CONFIG_STM32_I2S3_DATALEN; #ifdef CONFIG_DEBUG priv->align = STM32_I2S3_DATAMASK; #endif } -#endif /* CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S3 */ /**************************************************************************** * Public Functions @@ -2677,7 +2677,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_I2S1 +#ifdef CONFIG_STM32_I2S1 if (port == 1) { /* Select I2S1 */ @@ -2686,7 +2686,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S2 +#ifdef CONFIG_STM32_I2S2 if (port == 2) { /* Select I2S2 */ @@ -2695,7 +2695,7 @@ struct i2s_dev_s *stm32_i2sbus_initialize(int port) } else #endif -#ifdef CONFIG_STM32F7_I2S3 +#ifdef CONFIG_STM32_I2S3 if (port == 3) { /* Select I2S3 */ @@ -2736,4 +2736,4 @@ errout_with_alloc: } #endif /* I2S_HAVE_RX || I2S_HAVE_TX */ -#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */ +#endif /* CONFIG_STM32_I2S1 || CONFIG_STM32_I2S2 || CONFIG_STM32_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_lse.c b/arch/arm/src/stm32f7/stm32_lse.c index 10846796bba..ecc5b01ca3d 100644 --- a/arch/arm/src/stm32f7/stm32_lse.c +++ b/arch/arm/src/stm32f7/stm32_lse.c @@ -41,16 +41,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -59,7 +59,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -85,7 +85,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -109,17 +109,17 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable on. */ regval &= ~(RCC_BDCR_LSEDRV_MASK); - regval |= CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32F7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -153,13 +153,13 @@ void stm32_rcc_enablelse(void) } while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32F7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32F7_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32f7/stm32_ltdc.c b/arch/arm/src/stm32f7/stm32_ltdc.c index c7f1aff78d6..2901e7ad46d 100644 --- a/arch/arm/src/stm32f7/stm32_ltdc.c +++ b/arch/arm/src/stm32f7/stm32_ltdc.c @@ -129,8 +129,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32F7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32F7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -138,23 +138,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32F7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32F7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -165,24 +165,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32F7_LTDC_L2 -# if defined(CONFIG_STM32F7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -190,7 +190,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -212,7 +212,7 @@ #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # ifndef CONFIG_STM32F7_LTDC_L2_WIDTH # define CONFIG_STM32F7_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif @@ -256,7 +256,7 @@ /* Debug option */ -#ifdef CONFIG_STM32F7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -271,10 +271,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32F7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32F7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -287,7 +287,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -297,7 +297,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -305,27 +305,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32F7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32F7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32F7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32F7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32F7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32F7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -333,63 +333,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32F7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32F7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32F7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32F7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32F7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32F7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32F7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32F7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32F7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32F7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32F7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32F7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32F7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32F7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32F7_LTDC_L2 -# ifdef CONFIG_STM32F7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32F7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -423,28 +423,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32F7_DMA2D -# if defined(CONFIG_STM32F7_LTDC_L1_L8) || \ - defined(CONFIG_STM32F7_LTDC_L2_L8) -# if !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32F7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32F7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32F7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32F7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32F7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32F7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -452,12 +452,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32F7_FB_CMAP -# if defined(CONFIG_STM32F7_DMA2D) && !defined(CONFIG_STM32F7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -465,7 +465,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -473,7 +473,7 @@ # endif #endif -#ifndef CONFIG_STM32F7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -510,9 +510,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32F7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -520,9 +520,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -530,34 +530,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32F7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -579,7 +579,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32F7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -612,7 +612,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -637,7 +637,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -645,7 +645,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -693,7 +693,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -702,7 +702,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -725,7 +725,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -795,16 +795,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC mutex that enforces mutually exclusive access */ @@ -836,7 +836,7 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -857,7 +857,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -895,9 +895,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32F7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -905,7 +905,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -941,7 +941,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -953,7 +953,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -985,7 +985,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1007,7 +1007,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1017,7 +1017,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1027,7 +1027,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1037,7 +1037,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1047,7 +1047,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1057,7 +1057,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1067,7 +1067,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1077,7 +1077,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1087,7 +1087,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1097,7 +1097,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1109,7 +1109,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1119,7 +1119,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1129,7 +1129,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1139,7 +1139,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1149,7 +1149,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1159,7 +1159,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1169,7 +1169,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1179,7 +1179,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1189,7 +1189,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1199,7 +1199,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1209,22 +1209,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1648,7 +1648,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32F7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1920,7 +1920,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -1990,7 +1990,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { @@ -2095,7 +2095,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2104,7 +2104,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2112,7 +2112,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2155,7 +2155,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32F7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2215,7 +2215,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2255,7 +2255,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2291,7 +2291,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32F7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2378,7 +2378,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2408,7 +2408,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32F7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2478,7 +2478,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2498,7 +2498,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2589,7 +2589,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2636,14 +2636,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32F7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32F7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2651,7 +2651,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxmutex_lock(layer->lock); -# ifdef CONFIG_STM32F7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2671,7 +2671,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxmutex_unlock(layer->lock); return ret; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2699,7 +2699,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2760,7 +2760,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2794,7 +2794,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = @@ -2830,7 +2830,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2892,7 +2892,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32F7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3006,7 +3006,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3022,26 +3022,26 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32F7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32F7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32F7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32F7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ @@ -3135,7 +3135,7 @@ void stm32_ltdcuninitialize(void) #ifdef CONFIG_STM32F7_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32F7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h index a0d54267278..9b146f21e61 100644 --- a/arch/arm/src/stm32f7/stm32_otg.h +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -34,7 +34,7 @@ #include "chip.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS) /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ # define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT #endif -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_USBOTGFS_BASE # define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ @@ -58,7 +58,7 @@ # define STM32_OTG_FIFO_SIZE 1280 #endif -#if defined(CONFIG_STM32F7_OTGFSHS) +#if defined(CONFIG_STM32_OTGFSHS) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_USBOTGHS_BASE # define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ @@ -135,5 +135,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c index 7a1fe72b80c..803438a0dd4 100644 --- a/arch/arm/src/stm32f7/stm32_otgdev.c +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -52,8 +52,8 @@ #include "stm32_rcc.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ - defined(CONFIG_STM32F7_OTGFSHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGFSHS)) /**************************************************************************** * Pre-processor Definitions @@ -254,7 +254,7 @@ * present */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define OTG_GINT_RESERVED OTG_GINT_RESERVED_HS # define OTG_GINT_RC_W1 OTG_GINT_RC_W1_HS # else @@ -373,7 +373,7 @@ /* Maximum packet sizes for full speed endpoints */ -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS # define STM32_MAXPACKET (512) /* Max packet size (1-512) */ # else # define STM32_MAXPACKET (64) /* Max packet size (1-64) */ @@ -573,7 +573,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); # else @@ -898,7 +898,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -961,7 +961,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -# if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +# if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2163,7 +2163,7 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; @@ -3461,7 +3461,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_GUSBCFG_TRDT(9); # else regval |= OTG_GUSBCFG_TRDT(6); @@ -5345,15 +5345,15 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS -# ifdef CONFIG_STM32F7_NO_ULPI +# ifdef CONFIG_STM32_NO_ULPI regval = stm32_getreg(STM32_OTG_GUSBCFG); regval |= OTG_GUSBCFG_PHYSEL; stm32_putreg(regval, STM32_OTG_GUSBCFG); -# else /* CONFIG_STM32F7_NO_ULPI */ +# else /* CONFIG_STM32_NO_ULPI */ /* Switch off FS transceiver */ @@ -5376,7 +5376,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= ~(OTG_GUSBCFG_ULPIEVBUSD | OTG_GUSBCFG_ULPIEVBUSI); stm32_putreg(regval, STM32_OTG_GUSBCFG); -# ifdef CONFIG_STM32F7_INTERNAL_ULPI +# ifdef CONFIG_STM32_INTERNAL_ULPI /* Select UTMI/ULPI Interface */ @@ -5421,9 +5421,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) up_udelay(2000); -# endif /* CONFIG_STM32F7_INTERNAL_ULPI */ -# endif /* CONFIG_STM32F7_NO_ULPI */ -# endif /* CONFIG_STM32F7_OTGFSHS */ +# endif /* CONFIG_STM32_INTERNAL_ULPI */ +# endif /* CONFIG_STM32_NO_ULPI */ +# endif /* CONFIG_STM32_OTGFSHS */ /* Common USB OTG core initialization */ @@ -5465,7 +5465,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -# if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_NO_ULPI)) +# if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_NO_ULPI)) regval |= OTG_GCCFG_PWRDWN; # endif @@ -5509,7 +5509,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -# ifdef CONFIG_STM32F7_OTGFSHS +# ifdef CONFIG_STM32_OTGFSHS regval |= OTG_DCFG_DSPD_HS; # else regval |= OTG_DCFG_DSPD_FS; @@ -5652,7 +5652,7 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -# if defined(CONFIG_STM32F7_OTGFSHS) && defined(CONFIG_STM32F7_NO_ULPI) +# if defined(CONFIG_STM32_OTGFSHS) && defined(CONFIG_STM32_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must be done * because if both the ULPI and the FS PHY clock enable bits are set at the * same time, the ARM never awakens from WFI due to some bug / errata in @@ -5747,7 +5747,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5919,7 +5919,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) */ stm32_pullup(&priv->usbdev, true); -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || defined(CONFIG_STM32F7_EXTERNAL_ULPI) +# if defined(CONFIG_STM32_INTERNAL_ULPI) || defined(CONFIG_STM32_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; # else priv->usbdev.speed = USB_SPEED_FULL; diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c index 69681d2479b..8d7565adf60 100644 --- a/arch/arm/src/stm32f7/stm32_otghost.c +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -73,8 +73,8 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32F7_SYSCFG_IOCOMPENSATION - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG_IOCOMPENSATION - Needed * * Options: * @@ -87,16 +87,16 @@ * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION -# error "CONFIG_STM32F7_SYSCFG_IOCOMPENSATION is required" +#ifndef CONFIG_STM32_SYSCFG_IOCOMPENSATION +# error "CONFIG_STM32_SYSCFG_IOCOMPENSATION is required" #endif /* Default RxFIFO size */ @@ -126,8 +126,8 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32F7_USBHOST_REGDEBUG -# undef CONFIG_STM32F7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -272,7 +272,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -285,7 +285,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -496,7 +496,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -511,7 +511,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -575,7 +575,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -597,7 +597,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -5407,7 +5407,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5433,4 +5433,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_pulsecount.c b/arch/arm/src/stm32f7/stm32_pulsecount.c index ed0a19ae079..664dd33dabd 100644 --- a/arch/arm/src/stm32f7/stm32_pulsecount.c +++ b/arch/arm/src/stm32f7/stm32_pulsecount.c @@ -173,10 +173,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -203,107 +203,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32F7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32F7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32F7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32F7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32F7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -314,7 +314,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -322,7 +322,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1303,21 +1303,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32F7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32F7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1390,7 +1390,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1399,7 +1399,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1717,7 +1717,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1727,7 +1727,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index 66f1f90ca68..689d741d4d6 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -42,7 +42,7 @@ #include "stm32_rcc.h" #include "stm32_gpio.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ /* Advanced Timer support */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined(CONFIG_STM32F7_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -157,7 +157,7 @@ /* TRGO/TRGO2 support */ -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -225,7 +225,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -298,10 +298,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_trgo_configure(struct pwm_lowerhalf_s *dev, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); static uint16_t pwm_rcr_get(struct pwm_lowerhalf_s *dev); #endif @@ -342,7 +342,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -372,16 +372,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -396,114 +396,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1POL, - .idle = CONFIG_STM32F7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH1NPOL, - .idle = CONFIG_STM32F7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM1_CH2MODE, -#ifdef CONFIG_STM32F7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2POL, - .idle = CONFIG_STM32F7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH2NPOL, - .idle = CONFIG_STM32F7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM1_CH3MODE, -#ifdef CONFIG_STM32F7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3POL, - .idle = CONFIG_STM32F7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH3NPOL, - .idle = CONFIG_STM32F7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM1_CH4MODE, -#ifdef CONFIG_STM32F7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH4POL, - .idle = CONFIG_STM32F7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM1_CH5MODE, -#ifdef CONFIG_STM32F7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH5POL, - .idle = CONFIG_STM32F7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM1_CH6MODE, -#ifdef CONFIG_STM32F7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM1_CH6POL, - .idle = CONFIG_STM32F7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -514,18 +514,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32F7_TIM1_MODE, - .lock = CONFIG_STM32F7_TIM1_LOCK, - .t_dts = CONFIG_STM32F7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -533,72 +533,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32F7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM2_CH1MODE, -#ifdef CONFIG_STM32F7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH1POL, - .idle = CONFIG_STM32F7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM2_CH2MODE, -#ifdef CONFIG_STM32F7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH2POL, - .idle = CONFIG_STM32F7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM2_CH3MODE, -#ifdef CONFIG_STM32F7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH3POL, - .idle = CONFIG_STM32F7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM2_CH4MODE, -#ifdef CONFIG_STM32F7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM2_CH4POL, - .idle = CONFIG_STM32F7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -610,14 +610,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32F7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -629,72 +629,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32F7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM3_CH1MODE, -#ifdef CONFIG_STM32F7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH1POL, - .idle = CONFIG_STM32F7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM3_CH2MODE, -#ifdef CONFIG_STM32F7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH2POL, - .idle = CONFIG_STM32F7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM3_CH3MODE, -#ifdef CONFIG_STM32F7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH3POL, - .idle = CONFIG_STM32F7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM3_CH4MODE, -#ifdef CONFIG_STM32F7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM3_CH4POL, - .idle = CONFIG_STM32F7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -706,14 +706,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32F7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -725,72 +725,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32F7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM4_CH1MODE, -#ifdef CONFIG_STM32F7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH1POL, - .idle = CONFIG_STM32F7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM4_CH2MODE, -#ifdef CONFIG_STM32F7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH2POL, - .idle = CONFIG_STM32F7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM4_CH3MODE, -#ifdef CONFIG_STM32F7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH3POL, - .idle = CONFIG_STM32F7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM4_CH4MODE, -#ifdef CONFIG_STM32F7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM4_CH4POL, - .idle = CONFIG_STM32F7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -802,14 +802,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32F7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -821,71 +821,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32F7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM5_CH1MODE, -#ifdef CONFIG_STM32F7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH1POL, - .idle = CONFIG_STM32F7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM5_CH2MODE, -#ifdef CONFIG_STM32F7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH2POL, - .idle = CONFIG_STM32F7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM5_CH3MODE, -#ifdef CONFIG_STM32F7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH3POL, - .idle = CONFIG_STM32F7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM5_CH4MODE, -#ifdef CONFIG_STM32F7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM5_CH4POL, - .idle = CONFIG_STM32F7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -896,14 +896,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32F7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -915,18 +915,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32F7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -941,114 +941,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1POL, - .idle = CONFIG_STM32F7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH1NPOL, - .idle = CONFIG_STM32F7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM8_CH2MODE, -#ifdef CONFIG_STM32F7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2POL, - .idle = CONFIG_STM32F7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH2NPOL, - .idle = CONFIG_STM32F7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32F7_TIM8_CH3MODE, -#ifdef CONFIG_STM32F7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3POL, - .idle = CONFIG_STM32F7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH3NPOL, - .idle = CONFIG_STM32F7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32F7_TIM8_CH4MODE, -#ifdef CONFIG_STM32F7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH4POL, - .idle = CONFIG_STM32F7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32F7_TIM8_CH5MODE, -#ifdef CONFIG_STM32F7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH5POL, - .idle = CONFIG_STM32F7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32F7_TIM8_CH6MODE, -#ifdef CONFIG_STM32F7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM8_CH6POL, - .idle = CONFIG_STM32F7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1059,18 +1059,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32F7_TIM8_MODE, - .lock = CONFIG_STM32F7_TIM8_LOCK, - .t_dts = CONFIG_STM32F7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32F7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1078,40 +1078,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32F7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM static struct stm32_pwmchan_s g_pwm9channels[] = { /* TIM9 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM9_CH1MODE, -#ifdef CONFIG_STM32F7_TIM9_CH1OUT + .mode = CONFIG_STM32_TIM9_CH1MODE, +#ifdef CONFIG_STM32_TIM9_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH1POL, - .idle = CONFIG_STM32F7_TIM9_CH1IDLE, + .pol = CONFIG_STM32_TIM9_CH1POL, + .idle = CONFIG_STM32_TIM9_CH1IDLE, .pincfg = PWM_TIM9_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM9_CH2MODE, -#ifdef CONFIG_STM32F7_TIM9_CH2OUT + .mode = CONFIG_STM32_TIM9_CH2MODE, +#ifdef CONFIG_STM32_TIM9_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM9_CH2POL, - .idle = CONFIG_STM32F7_TIM9_CH2IDLE, + .pol = CONFIG_STM32_TIM9_CH2POL, + .idle = CONFIG_STM32_TIM9_CH2IDLE, .pincfg = PWM_TIM9_CH2CFG, } #endif @@ -1123,7 +1123,7 @@ static struct stm32_pwmchan_s g_pwm9channels[] = static struct stm32_pwmtimer_s g_pwm9dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 9, @@ -1142,24 +1142,24 @@ static struct stm32_pwmtimer_s g_pwm9dev = .base = STM32_TIM9_BASE, .pclk = TIMCLK_TIM9, }; -#endif /* CONFIG_STM32F7_TIM9_PWM */ +#endif /* CONFIG_STM32_TIM9_PWM */ -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM static struct stm32_pwmchan_s g_pwm10channels[] = { /* TIM10 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM10_CH1MODE, -#ifdef CONFIG_STM32F7_TIM10_CH1OUT + .mode = CONFIG_STM32_TIM10_CH1MODE, +#ifdef CONFIG_STM32_TIM10_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM10_CH1POL, - .idle = CONFIG_STM32F7_TIM10_CH1IDLE, + .pol = CONFIG_STM32_TIM10_CH1POL, + .idle = CONFIG_STM32_TIM10_CH1IDLE, .pincfg = PWM_TIM10_CH1CFG, } #endif @@ -1171,7 +1171,7 @@ static struct stm32_pwmchan_s g_pwm10channels[] = static struct stm32_pwmtimer_s g_pwm10dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 10, @@ -1190,24 +1190,24 @@ static struct stm32_pwmtimer_s g_pwm10dev = .base = STM32_TIM10_BASE, .pclk = TIMCLK_TIM10, }; -#endif /* CONFIG_STM32F7_TIM10_PWM */ +#endif /* CONFIG_STM32_TIM10_PWM */ -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM static struct stm32_pwmchan_s g_pwm11channels[] = { /* TIM11 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM11_CH1MODE, -#ifdef CONFIG_STM32F7_TIM11_CH1OUT + .mode = CONFIG_STM32_TIM11_CH1MODE, +#ifdef CONFIG_STM32_TIM11_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM11_CH1POL, - .idle = CONFIG_STM32F7_TIM11_CH1IDLE, + .pol = CONFIG_STM32_TIM11_CH1POL, + .idle = CONFIG_STM32_TIM11_CH1IDLE, .pincfg = PWM_TIM11_CH1CFG, } #endif @@ -1219,7 +1219,7 @@ static struct stm32_pwmchan_s g_pwm11channels[] = static struct stm32_pwmtimer_s g_pwm11dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 11, @@ -1238,40 +1238,40 @@ static struct stm32_pwmtimer_s g_pwm11dev = .base = STM32_TIM11_BASE, .pclk = TIMCLK_TIM11, }; -#endif /* CONFIG_STM32F7_TIM11_PWM */ +#endif /* CONFIG_STM32_TIM11_PWM */ -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM12_CH1MODE, -#ifdef CONFIG_STM32F7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH1POL, - .idle = CONFIG_STM32F7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32F7_TIM12_CH2MODE, -#ifdef CONFIG_STM32F7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM12_CH2POL, - .idle = CONFIG_STM32F7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1283,7 +1283,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1302,24 +1302,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32F7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM13_CH1MODE, -#ifdef CONFIG_STM32F7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM13_CH1POL, - .idle = CONFIG_STM32F7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1331,7 +1331,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1350,24 +1350,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32F7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32F7_TIM14_CH1MODE, -#ifdef CONFIG_STM32F7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32F7_TIM14_CH1POL, - .idle = CONFIG_STM32F7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1379,7 +1379,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1398,7 +1398,7 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32F7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ /**************************************************************************** * Private Functions @@ -1698,7 +1698,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1753,7 +1753,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -1798,7 +1798,7 @@ static int pwm_rcr_update(struct pwm_lowerhalf_s *dev, uint16_t rcr) } #endif -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /**************************************************************************** * Name: pwm_rcr_get ****************************************************************************/ @@ -2486,7 +2486,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32F7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3033,7 +3033,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3042,7 +3042,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3051,7 +3051,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3060,7 +3060,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3069,7 +3069,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3078,7 +3078,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3087,7 +3087,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { regaddr = TIMRCCEN_TIM9; @@ -3096,7 +3096,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { regaddr = TIMRCCEN_TIM10; @@ -3105,7 +3105,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { regaddr = TIMRCCEN_TIM11; @@ -3114,7 +3114,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3123,7 +3123,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3132,7 +3132,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3520,7 +3520,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3531,7 +3531,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3539,7 +3539,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3547,7 +3547,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3555,7 +3555,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3563,7 +3563,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3574,7 +3574,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM9_PWM +#ifdef CONFIG_STM32_TIM9_PWM case 9: { lower = &g_pwm9dev; @@ -3582,7 +3582,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM10_PWM +#ifdef CONFIG_STM32_TIM10_PWM case 10: { lower = &g_pwm10dev; @@ -3591,7 +3591,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) #endif -#ifdef CONFIG_STM32F7_TIM11_PWM +#ifdef CONFIG_STM32_TIM11_PWM case 11: { lower = &g_pwm11dev; @@ -3599,7 +3599,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3607,7 +3607,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3615,7 +3615,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32F7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3635,4 +3635,4 @@ errout: return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.h b/arch/arm/src/stm32f7/stm32_pwm.h index 06a7671301a..637833554ea 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.h +++ b/arch/arm/src/stm32f7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -57,41 +57,41 @@ * pulsed output signal generation. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32F7_TIM9 -# undef CONFIG_STM32F7_TIM9_PWM +#ifndef CONFIG_STM32_TIM9 +# undef CONFIG_STM32_TIM9_PWM #endif -#ifndef CONFIG_STM32F7_TIM10 -# undef CONFIG_STM32F7_TIM10_PWM +#ifndef CONFIG_STM32_TIM10 +# undef CONFIG_STM32_TIM10_PWM #endif -#ifndef CONFIG_STM32F7_TIM11 -# undef CONFIG_STM32F7_TIM11_PWM +#ifndef CONFIG_STM32_TIM11 +# undef CONFIG_STM32_TIM11_PWM #endif -#ifndef CONFIG_STM32F7_TIM12 -# undef CONFIG_STM32F7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32F7_TIM13 -# undef CONFIG_STM32F7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32F7_TIM14 -# undef CONFIG_STM32F7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -103,38 +103,38 @@ /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32F7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32F7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32F7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32F7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,59 +269,59 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32F7_TIM9_CHANNEL1 +#ifdef CONFIG_STM32_TIM9_CHANNEL1 # define PWM_TIM9_CHANNEL1 1 #else # define PWM_TIM9_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CHANNEL2 +#ifdef CONFIG_STM32_TIM9_CHANNEL2 # define PWM_TIM9_CHANNEL2 1 #else # define PWM_TIM9_CHANNEL2 0 #endif #define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM10_CHANNEL1 +#ifdef CONFIG_STM32_TIM10_CHANNEL1 # define PWM_TIM10_CHANNEL1 1 #else # define PWM_TIM10_CHANNEL1 0 #endif #define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM11_CHANNEL1 +#ifdef CONFIG_STM32_TIM11_CHANNEL1 # define PWM_TIM11_CHANNEL1 1 #else # define PWM_TIM11_CHANNEL1 0 #endif #define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32F7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32F7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#else /* !CONFIG_STM32F7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: @@ -336,410 +336,410 @@ * not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32F7_TIM1_PWM -# if !defined(CONFIG_STM32F7_TIM1_CHANNEL) -# error "CONFIG_STM32F7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM1_CHANNEL == 1 -# define CONFIG_STM32F7_TIM1_CHANNEL1 1 -# define CONFIG_STM32F7_TIM1_CH1MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 2 -# define CONFIG_STM32F7_TIM1_CHANNEL2 1 -# define CONFIG_STM32F7_TIM1_CH2MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 3 -# define CONFIG_STM32F7_TIM1_CHANNEL3 1 -# define CONFIG_STM32F7_TIM1_CH3MODE CONFIG_STM32F7_TIM1_CHMODE -# elif CONFIG_STM32F7_TIM1_CHANNEL == 4 -# define CONFIG_STM32F7_TIM1_CHANNEL4 1 -# define CONFIG_STM32F7_TIM1_CH4MODE CONFIG_STM32F7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM2_PWM -# if !defined(CONFIG_STM32F7_TIM2_CHANNEL) -# error "CONFIG_STM32F7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM2_CHANNEL == 1 -# define CONFIG_STM32F7_TIM2_CHANNEL1 1 -# define CONFIG_STM32F7_TIM2_CH1MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 2 -# define CONFIG_STM32F7_TIM2_CHANNEL2 1 -# define CONFIG_STM32F7_TIM2_CH2MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 3 -# define CONFIG_STM32F7_TIM2_CHANNEL3 1 -# define CONFIG_STM32F7_TIM2_CH3MODE CONFIG_STM32F7_TIM2_CHMODE -# elif CONFIG_STM32F7_TIM2_CHANNEL == 4 -# define CONFIG_STM32F7_TIM2_CHANNEL4 1 -# define CONFIG_STM32F7_TIM2_CH4MODE CONFIG_STM32F7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM3_PWM -# if !defined(CONFIG_STM32F7_TIM3_CHANNEL) -# error "CONFIG_STM32F7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM3_CHANNEL == 1 -# define CONFIG_STM32F7_TIM3_CHANNEL1 1 -# define CONFIG_STM32F7_TIM3_CH1MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 2 -# define CONFIG_STM32F7_TIM3_CHANNEL2 1 -# define CONFIG_STM32F7_TIM3_CH2MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 3 -# define CONFIG_STM32F7_TIM3_CHANNEL3 1 -# define CONFIG_STM32F7_TIM3_CH3MODE CONFIG_STM32F7_TIM3_CHMODE -# elif CONFIG_STM32F7_TIM3_CHANNEL == 4 -# define CONFIG_STM32F7_TIM3_CHANNEL4 1 -# define CONFIG_STM32F7_TIM3_CH4MODE CONFIG_STM32F7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM4_PWM -# if !defined(CONFIG_STM32F7_TIM4_CHANNEL) -# error "CONFIG_STM32F7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM4_CHANNEL == 1 -# define CONFIG_STM32F7_TIM4_CHANNEL1 1 -# define CONFIG_STM32F7_TIM4_CH1MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 2 -# define CONFIG_STM32F7_TIM4_CHANNEL2 1 -# define CONFIG_STM32F7_TIM4_CH2MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 3 -# define CONFIG_STM32F7_TIM4_CHANNEL3 1 -# define CONFIG_STM32F7_TIM4_CH3MODE CONFIG_STM32F7_TIM4_CHMODE -# elif CONFIG_STM32F7_TIM4_CHANNEL == 4 -# define CONFIG_STM32F7_TIM4_CHANNEL4 1 -# define CONFIG_STM32F7_TIM4_CH4MODE CONFIG_STM32F7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM5_PWM -# if !defined(CONFIG_STM32F7_TIM5_CHANNEL) -# error "CONFIG_STM32F7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM5_CHANNEL == 1 -# define CONFIG_STM32F7_TIM5_CHANNEL1 1 -# define CONFIG_STM32F7_TIM5_CH1MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 2 -# define CONFIG_STM32F7_TIM5_CHANNEL2 1 -# define CONFIG_STM32F7_TIM5_CH2MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 3 -# define CONFIG_STM32F7_TIM5_CHANNEL3 1 -# define CONFIG_STM32F7_TIM5_CH3MODE CONFIG_STM32F7_TIM5_CHMODE -# elif CONFIG_STM32F7_TIM5_CHANNEL == 4 -# define CONFIG_STM32F7_TIM5_CHANNEL4 1 -# define CONFIG_STM32F7_TIM5_CH4MODE CONFIG_STM32F7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM8_PWM -# if !defined(CONFIG_STM32F7_TIM8_CHANNEL) -# error "CONFIG_STM32F7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM8_CHANNEL == 1 -# define CONFIG_STM32F7_TIM8_CHANNEL1 1 -# define CONFIG_STM32F7_TIM8_CH1MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 2 -# define CONFIG_STM32F7_TIM8_CHANNEL2 1 -# define CONFIG_STM32F7_TIM8_CH2MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 3 -# define CONFIG_STM32F7_TIM8_CHANNEL3 1 -# define CONFIG_STM32F7_TIM8_CH3MODE CONFIG_STM32F7_TIM8_CHMODE -# elif CONFIG_STM32F7_TIM8_CHANNEL == 4 -# define CONFIG_STM32F7_TIM8_CHANNEL4 1 -# define CONFIG_STM32F7_TIM8_CH4MODE CONFIG_STM32F7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM9_PWM -# if !defined(CONFIG_STM32F7_TIM9_CHANNEL) -# error "CONFIG_STM32F7_TIM9_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM9_CHANNEL == 1 -# define CONFIG_STM32F7_TIM9_CHANNEL1 1 -# define CONFIG_STM32F7_TIM9_CH1MODE CONFIG_STM32F7_TIM9_CHMODE -# elif CONFIG_STM32F7_TIM9_CHANNEL == 2 -# define CONFIG_STM32F7_TIM9_CHANNEL2 1 -# define CONFIG_STM32F7_TIM9_CH2MODE CONFIG_STM32F7_TIM9_CHMODE +#ifdef CONFIG_STM32_TIM9_PWM +# if !defined(CONFIG_STM32_TIM9_CHANNEL) +# error "CONFIG_STM32_TIM9_CHANNEL must be provided" +# elif CONFIG_STM32_TIM9_CHANNEL == 1 +# define CONFIG_STM32_TIM9_CHANNEL1 1 +# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE +# elif CONFIG_STM32_TIM9_CHANNEL == 2 +# define CONFIG_STM32_TIM9_CHANNEL2 1 +# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM9_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL" # endif # define PWM_TIM9_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM10_PWM -# if !defined(CONFIG_STM32F7_TIM10_CHANNEL) -# error "CONFIG_STM32F7_TIM10_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM10_CHANNEL == 1 -# define CONFIG_STM32F7_TIM10_CHANNEL1 1 -# define CONFIG_STM32F7_TIM10_CH1MODE CONFIG_STM32F7_TIM10_CHMODE +#ifdef CONFIG_STM32_TIM10_PWM +# if !defined(CONFIG_STM32_TIM10_CHANNEL) +# error "CONFIG_STM32_TIM10_CHANNEL must be provided" +# elif CONFIG_STM32_TIM10_CHANNEL == 1 +# define CONFIG_STM32_TIM10_CHANNEL1 1 +# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM10_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL" # endif # define PWM_TIM10_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM11_PWM -# if !defined(CONFIG_STM32F7_TIM11_CHANNEL) -# error "CONFIG_STM32F7_TIM11_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM11_CHANNEL == 1 -# define CONFIG_STM32F7_TIM11_CHANNEL1 1 -# define CONFIG_STM32F7_TIM11_CH1MODE CONFIG_STM32F7_TIM11_CHMODE +#ifdef CONFIG_STM32_TIM11_PWM +# if !defined(CONFIG_STM32_TIM11_CHANNEL) +# error "CONFIG_STM32_TIM11_CHANNEL must be provided" +# elif CONFIG_STM32_TIM11_CHANNEL == 1 +# define CONFIG_STM32_TIM11_CHANNEL1 1 +# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM11_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL" # endif # define PWM_TIM11_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM12_PWM -# if !defined(CONFIG_STM32F7_TIM12_CHANNEL) -# error "CONFIG_STM32F7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM12_CHANNEL == 1 -# define CONFIG_STM32F7_TIM12_CHANNEL1 1 -# define CONFIG_STM32F7_TIM12_CH1MODE CONFIG_STM32F7_TIM12_CHMODE -# elif CONFIG_STM32F7_TIM12_CHANNEL == 2 -# define CONFIG_STM32F7_TIM12_CHANNEL2 1 -# define CONFIG_STM32F7_TIM12_CH2MODE CONFIG_STM32F7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM13_PWM -# if !defined(CONFIG_STM32F7_TIM13_CHANNEL) -# error "CONFIG_STM32F7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM13_CHANNEL == 1 -# define CONFIG_STM32F7_TIM13_CHANNEL1 1 -# define CONFIG_STM32F7_TIM13_CH1MODE CONFIG_STM32F7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32F7_TIM14_PWM -# if !defined(CONFIG_STM32F7_TIM14_CHANNEL) -# error "CONFIG_STM32F7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32F7_TIM14_CHANNEL == 1 -# define CONFIG_STM32F7_TIM14_CHANNEL1 1 -# define CONFIG_STM32F7_TIM14_CH1MODE CONFIG_STM32F7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32F7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#endif /* CONFIG_STM32F7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32F7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32F7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH1OUT +#ifdef CONFIG_STM32_TIM9_CH1OUT # define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT #else # define PWM_TIM9_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM9_CH2OUT +#ifdef CONFIG_STM32_TIM9_CH2OUT # define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT #else # define PWM_TIM9_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM10_CH1OUT +#ifdef CONFIG_STM32_TIM10_CH1OUT # define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT #else # define PWM_TIM10_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM11_CH1OUT +#ifdef CONFIG_STM32_TIM11_CH1OUT # define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT #else # define PWM_TIM11_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32F7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 @@ -747,12 +747,12 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined(CONFIG_STM32F7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32F7_TIM8_CH1NOUT) || defined(CONFIG_STM32F7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32F7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) @@ -761,7 +761,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -786,7 +786,7 @@ (dev)->llops->rcr_update((struct pwm_lowerhalf_s *)dev, rcr) #define PWM_RCR_GET(dev) \ (dev)->llops->rcr_get((struct pwm_lowerhalf_s *)dev) -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define PWM_TRGO_SET(dev, trgo) \ (dev)->llops->trgo_set((struct pwm_lowerhalf_s *)dev, trgo) #endif @@ -898,7 +898,7 @@ enum stm32_pwm_output_e /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32F7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -954,7 +954,7 @@ struct stm32_pwm_ops_s uint16_t (*rcr_get)(struct pwm_lowerhalf_s *dev); -#ifdef CONFIG_STM32F7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO /* Set TRGO/TRGO2 register */ int (*trgo_set)(struct pwm_lowerhalf_s *dev, uint8_t trgo); @@ -998,7 +998,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32F7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1044,5 +1044,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c index c86b70a2474..5fac63ef025 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.c +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -35,7 +35,7 @@ #include "arm_internal.h" #include "stm32_pwr.h" -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /**************************************************************************** * Private Data diff --git a/arch/arm/src/stm32f7/stm32_qencoder.c b/arch/arm/src/stm32f7/stm32_qencoder.c index e3afc99eb67..fdf06b3bb0d 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.c +++ b/arch/arm/src/stm32f7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32F7_TIM2_QE) || defined(CONFIG_STM32F7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM3_QE) || \ - defined(CONFIG_STM32F7_TIM4_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32F7_QENCODER_FILTER -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32F7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32F7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32F7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32F7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32F7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1ENR, .enable = RCC_APB1ENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32F7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32F7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32F7_TIM1_QE) || defined(CONFIG_STM32F7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -943,37 +943,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32F7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32F7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1RSTR; resetbit = RCC_APB1RSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32f7/stm32_qencoder.h b/arch/arm/src/stm32f7/stm32_qencoder.h index 3531846389c..40b2f6f92e1 100644 --- a/arch/arm/src/stm32f7/stm32_qencoder.h +++ b/arch/arm/src/stm32f7/stm32_qencoder.h @@ -43,23 +43,23 @@ * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32F7_TIM1 -# undef CONFIG_STM32F7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32F7_TIM2 -# undef CONFIG_STM32F7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32F7_TIM3 -# undef CONFIG_STM32F7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32F7_TIM4 -# undef CONFIG_STM32F7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32F7_TIM5 -# undef CONFIG_STM32F7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32F7_TIM8 -# undef CONFIG_STM32F7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder diff --git a/arch/arm/src/stm32f7/stm32_qspi.c b/arch/arm/src/stm32f7/stm32_qspi.c index 65e52304863..e67a30f701a 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.c +++ b/arch/arm/src/stm32f7/stm32_qspi.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32F7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) && defined(CONFIG_STM32F7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,7 +92,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -104,26 +104,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32F7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32F7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32F7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32F7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32F7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -164,14 +164,14 @@ struct stm32f7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -181,11 +181,11 @@ struct stm32f7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32f7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -222,7 +222,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -235,7 +235,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -262,16 +262,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32F7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32f7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32f7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); @@ -281,8 +281,8 @@ static void qspi_dma_sampledone(struct stm32f7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32F7_QSPI_DMATHRESHOLD -# define CONFIG_STM32F7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -336,13 +336,13 @@ static struct stm32f7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -368,7 +368,7 @@ static struct stm32f7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32f7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -420,7 +420,7 @@ static inline uint32_t qspi_getreg(struct stm32f7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -443,7 +443,7 @@ static inline void qspi_putreg(struct stm32f7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32F7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -625,7 +625,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32F7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -831,7 +831,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -962,7 +962,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1086,7 +1086,7 @@ static void qspi_ccrconfig(struct stm32f7_qspidev_s *priv, } } -#if defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1313,7 +1313,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1579,7 +1579,7 @@ static int qspi_memory_dma(struct stm32f7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32F7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2011,7 +2011,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2192,7 +2192,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2253,11 +2253,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32F7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32F7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2419,18 +2419,18 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32F7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32F7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32F7_QSPI_FIFO_THESHOLD - 1) + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2451,10 +2451,10 @@ static int qspi_hw_initialize(struct stm32f7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32F7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32F7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32F7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2560,7 +2560,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2574,7 +2574,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2600,7 +2600,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2608,12 +2608,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32F7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2679,7 +2679,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2698,7 +2698,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32F7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2744,4 +2744,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32f7/stm32_qspi.h b/arch/arm/src/stm32f7/stm32_qspi.h index a82c3296e06..5485ac57384 100644 --- a/arch/arm/src/stm32f7/stm32_qspi.h +++ b/arch/arm/src/stm32f7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32F7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.c b/arch/arm/src/stm32f7/stm32_rcc.c index 92b4ec75fef..b0c35860a24 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.c +++ b/arch/arm/src/stm32f7/stm32_rcc.c @@ -63,11 +63,11 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) +#if defined(CONFIG_STM32_STM32F72XX) || defined(CONFIG_STM32_STM32F73XX) # include "stm32f72xx73xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +#elif defined(CONFIG_STM32_STM32F74XX) || defined(CONFIG_STM32_STM32F75XX) # include "stm32f74xx75xx_rcc.c" -#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#elif defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) # include "stm32f76xx77xx_rcc.c" #else # error "Unsupported STM32 F7 chip" @@ -86,7 +86,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configurationfile. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -104,14 +104,14 @@ void stm32_clockconfig(void) rcc_reset(); -#if defined(CONFIG_STM32F7_PWR) +#if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); #endif -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -131,7 +131,7 @@ void stm32_clockconfig(void) rcc_enableperipherals(); -#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -151,7 +151,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking * will be enabled by an externally provided, board-specific function * called stm32_board_clockconfig(). * @@ -166,7 +166,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32f7/stm32_rcc.h b/arch/arm/src/stm32f7/stm32_rcc.h index 9a1d166e96d..2bf57bb9855 100644 --- a/arch/arm/src/stm32f7/stm32_rcc.h +++ b/arch/arm/src/stm32f7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -147,7 +147,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,9 +164,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is defined, then clocking will - * be enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -216,7 +216,7 @@ void stm32_rcc_enablelsi(void); void stm32_rcc_disablelsi(void); -#if defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +#if defined(CONFIG_STM32_STM32F76XX) || defined(CONFIG_STM32_STM32F77XX) /**************************************************************************** * Name: stm32_rcc_dsisrcphy * diff --git a/arch/arm/src/stm32f7/stm32_rng.c b/arch/arm/src/stm32f7/stm32_rng.c index 7eeb2d4916c..10bad1e664e 100644 --- a/arch/arm/src/stm32f7/stm32_rng.c +++ b/arch/arm/src/stm32f7/stm32_rng.c @@ -40,7 +40,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32F7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -329,4 +329,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32F7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index c5d1cc56096..9e2deaff4a0 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32F7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32F7_PWR -# error "CONFIG_STM32F7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32F7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32F7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32F7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h index 91ce5049523..b6130256949 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.h +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32F7_RTC_MAGIC) -# define CONFIG_STM32F7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32F7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32F7_RTC_MAGIC_REG) -# define CONFIG_STM32F7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32F7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32F7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32F7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index c05e18fc7fe..75d8e998f4e 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -68,7 +68,7 @@ #include "stm32_sai.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32F7_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -86,11 +86,11 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32F7_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32F7_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif @@ -106,19 +106,19 @@ # define CONFIG_STM32F7_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 #ifndef STM32_SAI1_FREQUENCY # error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 #ifndef STM32_SAI2_FREQUENCY # error "Please define STM32_SAI1_FREQUENCY in board.h" #endif #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ # if defined(CONFIG_STM32F7_SAI_DMAPRIO) @@ -194,7 +194,7 @@ struct stm32f7_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -236,7 +236,7 @@ static void sai_buf_initialize(struct stm32f7_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32f7_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -274,19 +274,19 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32f7_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -295,19 +295,19 @@ static struct stm32f7_sai_s g_sai1a_priv = }; #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32f7_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -318,19 +318,19 @@ static struct stm32f7_sai_s g_sai1b_priv = /* SAI2 state */ -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32f7_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -339,19 +339,19 @@ static struct stm32f7_sai_s g_sai2a_priv = }; #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32f7_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_INTERNAL, #else .syncen = SAI_CR1_SYNCEN_ASYNCH, #endif -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif .datalen = CONFIG_STM32F7_SAI_DEFAULT_DATALEN, @@ -491,7 +491,7 @@ static void sai_dump_regs(struct stm32f7_sai_s *priv, const char *msg) #else /* GCR */ -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 uint32_t gcr = getreg32(STM32_SAI1_GCR); i2sinfo("GCR: *%08x = %08" PRIx32 "\n", STM32_SAI1_GCR, gcr); #else @@ -757,7 +757,7 @@ static void sai_timeout(wdparm_t arg) struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32_dmastop(priv->dma); @@ -787,7 +787,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32f7_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -959,7 +959,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -1071,7 +1071,7 @@ static void sai_schedule(struct stm32f7_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32f7_sai_s *priv = (struct stm32f7_sai_s *)arg; @@ -1268,7 +1268,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1368,7 +1368,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1522,7 +1522,7 @@ static void sai_portinitialize(struct stm32f7_sai_s *priv) sai_datawidth((struct i2s_dev_s *)priv, CONFIG_STM32F7_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32F7_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32_dmachannel(priv->dma_ch); @@ -1581,7 +1581,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, switch (intf) { -#ifdef CONFIG_STM32F7_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); @@ -1589,7 +1589,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32F7_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI1_FS_A); stm32_configgpio(GPIO_SAI1_SCK_A); stm32_configgpio(GPIO_SAI1_MCLK_A); @@ -1598,7 +1598,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); @@ -1606,7 +1606,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32F7_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI1_FS_B); stm32_configgpio(GPIO_SAI1_SCK_B); stm32_configgpio(GPIO_SAI1_MCLK_B); @@ -1615,7 +1615,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); @@ -1623,7 +1623,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32F7_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI2_FS_A); stm32_configgpio(GPIO_SAI2_SCK_A); stm32_configgpio(GPIO_SAI2_MCLK_A); @@ -1632,7 +1632,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, } #endif -#ifdef CONFIG_STM32F7_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); @@ -1640,7 +1640,7 @@ struct i2s_dev_s *stm32_sai_initialize(int intf, priv->sampleratecb = sampleratecb; stm32_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32F7_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI2_FS_B); stm32_configgpio(GPIO_SAI2_SCK_B); stm32_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 1bf6eac7baf..d82877095a1 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -53,7 +53,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -65,7 +65,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -74,15 +74,15 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally optional. * For most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32F7_SDMMC_DMA is enabled. - * CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output. This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * * CONFIG_SDMMC1/2_SDIO_MODE @@ -100,20 +100,20 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#ifndef CONFIG_STM32F7_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# ifndef CONFIG_STM32F7_DMA2 -# error "CONFIG_STM32F7_SDMMC_DMA support requires CONFIG_STM32F7_DMA2" +# ifndef CONFIG_STM32_DMA2 +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32F7_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -121,16 +121,16 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32F7_SDMMC1 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC1_DMAPRIO -# define CONFIG_STM32F7_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC1_CLK UINT32_C(48000000) @@ -139,16 +139,16 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC2 -# ifdef CONFIG_STM32F7_SDMMC_DMA -# ifndef CONFIG_STM32F7_SDMMC2_DMAPRIO -# define CONFIG_STM32F7_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32F7_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32F7_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32F7_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif # if STM32_RCC_DCKCFGR2_SDMMCSRC == RCC_DCKCFGR2_SDMMCSEL_48MHZ # define STM32_SDMMC2_CLK UINT32_C(48000000) @@ -163,7 +163,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32F7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -345,8 +345,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -379,7 +379,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -409,7 +409,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -433,7 +433,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -450,7 +450,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -473,7 +473,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -488,7 +488,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -563,7 +563,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -572,7 +572,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen); static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ /* Initialization/uninitialization/reset ************************************/ @@ -583,7 +583,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -615,7 +615,7 @@ struct stm32_dev_s g_sdmmcdev1 = .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -627,7 +627,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif .dmarecvsetup = stm32_recvsetup, .dmasendsetup = stm32_sendsetup, -#endif /* CONFIG_STM32F7_SDMMC_DMA */ +#endif /* CONFIG_STM32_SDMMC_DMA */ #endif /* CONFIG_SDIO_DMA*/ }, .base = STM32_SDMMC1_BASE, @@ -636,8 +636,8 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC1_SDIO_PULL(GPIO_SDMMC1_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -651,7 +651,7 @@ struct stm32_dev_s g_sdmmcdev1 = }; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -696,8 +696,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = SDMMC2_SDIO_PULL(GPIO_SDMMC2_D0), #endif -#ifdef CONFIG_STM32F7_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32F7_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), #ifdef HAVE_SDMMC_SDIO_MODE @@ -712,7 +712,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -859,7 +859,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -952,7 +952,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -968,7 +968,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -992,12 +992,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -1016,7 +1016,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -1046,12 +1046,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -1070,13 +1070,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -1089,7 +1089,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1107,7 +1107,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1515,7 +1515,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1625,7 +1625,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1664,7 +1664,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1884,7 +1884,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1903,7 +1903,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ priv->rxbuffer = 0; priv->rxend = 0; @@ -1944,7 +1944,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2241,7 +2241,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2298,7 +2298,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; priv->rxbuffer = 0; #endif @@ -2354,7 +2354,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2871,7 +2871,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2968,11 +2968,11 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32F7_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); @@ -3009,7 +3009,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3112,7 +3112,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3315,18 +3315,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; # endif @@ -3356,14 +3356,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -# ifdef CONFIG_STM32F7_SDMMC_DMA +# ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; # endif @@ -3398,7 +3398,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32F7_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32_dmachannel(dmachan); @@ -3499,7 +3499,7 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ #ifdef HAVE_SDMMC_SDIO_MODE void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index c04b5eca680..c73b64b0548 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -78,16 +78,16 @@ */ # if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART6_RXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 receive DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 receive DMA requires CONFIG_STM32_DMA2 # endif # endif # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) || \ defined(CONFIG_UART7_RXDMA) || defined(CONFIG_UART8_RXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -135,14 +135,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -172,16 +172,16 @@ */ #if defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART6_TXDMA) -# ifndef CONFIG_STM32F7_DMA2 -# error STM32 USART1/6 transmit DMA requires CONFIG_STM32F7_DMA2 +# ifndef CONFIG_STM32_DMA2 +# error STM32 USART1/6 transmit DMA requires CONFIG_STM32_DMA2 # endif #endif #if defined(CONFIG_USART2_TXDMA) || defined(CONFIG_USART3_TXDMA) || \ defined(CONFIG_UART4_TXDMA) || defined(CONFIG_UART5_TXDMA) || \ defined(CONFIG_UART7_TXDMA) || defined(CONFIG_UART8_TXDMA) -# ifndef CONFIG_STM32F7_DMA1 -# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32F7_DMA1 +# ifndef CONFIG_STM32_DMA1 +# error STM32 USART2/3/4/5/7/8 transmit DMA requires CONFIG_STM32_DMA1 # endif #endif @@ -228,7 +228,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32F7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -331,8 +331,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32F7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32F7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Since RX DMA or TX DMA or both may be enabled for a given U[S]ART. @@ -354,7 +354,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -364,13 +364,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32F7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -413,7 +413,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32F7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -720,49 +720,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -770,7 +770,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -839,7 +839,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -908,7 +908,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -977,7 +977,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1046,7 +1046,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1115,7 +1115,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1184,7 +1184,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1253,7 +1253,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1324,28 +1324,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1635,7 +1635,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1828,49 +1828,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1ENR_USART2EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1ENR_USART3EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1ENR_UART4EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1ENR_UART5EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1ENR_UART7EN; regaddr = STM32_RCC_APB1ENR; break; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1ENR_UART8EN; regaddr = STM32_RCC_APB1ENR; @@ -1938,7 +1938,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32F7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2291,8 +2291,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32F7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32F7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2405,11 +2405,11 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32F7_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2432,7 +2432,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2499,7 +2499,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2550,7 +2550,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32F7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2687,8 +2687,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32F7_USART_BREAKS -# ifdef CONFIG_STM32F7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2907,7 +2907,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32F7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3699,7 +3699,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3728,7 +3728,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32F7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32f7/stm32_spi.c b/arch/arm/src/stm32f7/stm32_spi.c index 4ddc01a5539..2b43927a3ec 100644 --- a/arch/arm/src/stm32f7/stm32_spi.c +++ b/arch/arm/src/stm32f7/stm32_spi.c @@ -73,9 +73,9 @@ #include "stm32_dma.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,39 +135,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32F7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32F7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32F7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32F7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,10 +182,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -231,7 +231,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -291,7 +291,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -336,11 +336,11 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # ifdef SPI1_DMABUFSIZE_ADJUSTED @@ -362,7 +362,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -407,11 +407,11 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -433,7 +433,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -478,11 +478,11 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI3_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # ifdef SPI3_DMABUFSIZE_ADJUSTED @@ -504,7 +504,7 @@ static struct stm32_spidev_s g_spi3dev = }; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -549,11 +549,11 @@ static struct stm32_spidev_s g_spi4dev = }, .spibase = STM32_SPI4_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI4, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI4_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # ifdef SPI4_DMABUFSIZE_ADJUSTED @@ -575,7 +575,7 @@ static struct stm32_spidev_s g_spi4dev = }; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -620,11 +620,11 @@ static struct stm32_spidev_s g_spi5dev = }, .spibase = STM32_SPI5_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI5, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI5_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # ifdef SPI5_DMABUFSIZE_ADJUSTED @@ -646,7 +646,7 @@ static struct stm32_spidev_s g_spi5dev = }; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -691,11 +691,11 @@ static struct stm32_spidev_s g_spi6dev = }, .spibase = STM32_SPI6_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI6, #endif -#ifdef CONFIG_STM32F7_SPI_DMA -# ifdef CONFIG_STM32F7_SPI6_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # ifdef SPI6_DMABUFSIZE_ADJUSTED @@ -916,7 +916,7 @@ static inline void spi_writebyte(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -949,7 +949,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -982,7 +982,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -997,7 +997,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -1012,7 +1012,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1032,7 +1032,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1052,7 +1052,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -1103,7 +1103,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -1154,7 +1154,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -1170,7 +1170,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1397,7 +1397,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; uint16_t setbits; uint16_t clrbits; -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA uint16_t cr2bits; #endif @@ -1440,7 +1440,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_modifycr1(priv, 0, SPI_CR1_SPE); spi_modifycr1(priv, setbits, clrbits); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Enabling SPI causes a spurious received character indication * which confuse the DMA controller so we disable DMA during that * enabling; and flush the SPI RX FIFO before re-enabling DMA. @@ -1461,7 +1461,7 @@ static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) spi_getreg(priv, STM32_SPI_DR_OFFSET); } -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Re-enable DMA (with SPI disabled) */ @@ -1691,9 +1691,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32F7_SPI_DMA) || defined(CONFIG_STM32F7_DMACAPABLE) || \ - defined(CONFIG_STM32F7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32F7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1777,8 +1777,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32F7_SPI_DMA || CONFIG_STM32F7_DMACAPABLE || - * CONFIG_STM32F7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1802,7 +1802,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1816,13 +1816,13 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32F7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() * do the work. */ - if (nbytes <= CONFIG_STM32F7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1840,7 +1840,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32F7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* If this bus uses a in driver DMA aligned buffers we can skip the test */ if ((txbuffer && priv->txbuf == 0 && @@ -1948,7 +1948,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, } } } -#endif /* CONFIG_STM32F7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1969,7 +1969,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2173,7 +2173,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32F7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the @@ -2235,7 +2235,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2260,7 +2260,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2285,7 +2285,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2310,7 +2310,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2335,7 +2335,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2360,7 +2360,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2393,6 +2393,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32F7_SPI1 || CONFIG_STM32F7_SPI2 || CONFIG_STM32F7_SPI3 || - * CONFIG_STM32F7_SPI4 || CONFIG_STM32F7_SPI5 || CONFIG_STM32F7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32f7/stm32_spi.h b/arch/arm/src/stm32f7/stm32_spi.h index f4adbac6a5e..346af668597 100644 --- a/arch/arm/src/stm32f7/stm32_spi.h +++ b/arch/arm/src/stm32f7/stm32_spi.h @@ -98,42 +98,42 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -161,32 +161,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32f7/stm32_tickless.c b/arch/arm/src/stm32f7/stm32_tickless.c index 52ddb0e04bd..d348d93cadb 100644 --- a/arch/arm/src/stm32f7/stm32_tickless.c +++ b/arch/arm/src/stm32f7/stm32_tickless.c @@ -107,18 +107,18 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32F7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32F7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if CONFIG_STM32F7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32F7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -426,43 +426,43 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32F7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM1STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM2STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM3STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM4STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM5STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: /* Basic timers not supported by this implementation */ @@ -471,7 +471,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: /* Basic timers not supported by this implementation */ @@ -480,52 +480,52 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM8STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM9STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM10STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; modifyreg32(STM32_DBGMCU_APB2_FZ, 0, DBGMCU_APB2_TIM11STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM12STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM13STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1_FZ, 0, DBGMCU_APB1_TIM14STOP); break; #endif -#ifdef CONFIG_STM32F7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; @@ -534,7 +534,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; @@ -543,7 +543,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32F7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; @@ -559,8 +559,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32F7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32F7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1027,10 +1027,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1047,7 +1047,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32F7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1068,7 +1068,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32F7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32f7/stm32_tim.c b/arch/arm/src/stm32f7/stm32_tim.c index e5ba5829719..622568201c1 100644 --- a/arch/arm/src/stm32f7/stm32_tim.c +++ b/arch/arm/src/stm32f7/stm32_tim.c @@ -72,140 +72,140 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32F7_TIM1_PWM) || defined (CONFIG_STM32F7_TIM1_ADC) || \ - defined(CONFIG_STM32F7_TIM1_DAC) || defined(CONFIG_STM32F7_TIM1_QE) -# undef CONFIG_STM32F7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) || defined (CONFIG_STM32F7_TIM2_ADC) || \ - defined(CONFIG_STM32F7_TIM2_DAC) || defined(CONFIG_STM32F7_TIM2_QE) -# undef CONFIG_STM32F7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) || defined (CONFIG_STM32F7_TIM3_ADC) || \ - defined(CONFIG_STM32F7_TIM3_DAC) || defined(CONFIG_STM32F7_TIM3_QE) -# undef CONFIG_STM32F7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) || defined (CONFIG_STM32F7_TIM4_ADC) || \ - defined(CONFIG_STM32F7_TIM4_DAC) || defined(CONFIG_STM32F7_TIM4_QE) -# undef CONFIG_STM32F7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32F7_TIM5_PWM) || defined (CONFIG_STM32F7_TIM5_ADC) || \ - defined(CONFIG_STM32F7_TIM5_DAC) || defined(CONFIG_STM32F7_TIM5_QE) -# undef CONFIG_STM32F7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32F7_TIM6_ADC) || \ - defined(CONFIG_STM32F7_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) -# undef CONFIG_STM32F7_TIM6 +#if defined(CONFIG_STM32F7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32F7_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32F7_TIM7_PWM) || defined (CONFIG_STM32F7_TIM7_ADC) || \ - defined(CONFIG_STM32F7_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) -# undef CONFIG_STM32F7_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32F7_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32F7_TIM8_PWM) || defined (CONFIG_STM32F7_TIM8_ADC) || \ - defined(CONFIG_STM32F7_TIM8_DAC) || defined(CONFIG_STM32F7_TIM8_QE) -# undef CONFIG_STM32F7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32F7_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ - defined(CONFIG_STM32F7_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) -# undef CONFIG_STM32F7_TIM9 +#if defined(CONFIG_STM32_TIM9_PWM) || defined (CONFIG_STM32F7_TIM9_ADC) || \ + defined(CONFIG_STM32_TIM9_DAC) || defined(CONFIG_STM32F7_TIM9_QE) +# undef CONFIG_STM32_TIM9 #endif -#if defined(CONFIG_STM32F7_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ - defined(CONFIG_STM32F7_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) -# undef CONFIG_STM32F7_TIM10 +#if defined(CONFIG_STM32_TIM10_PWM) || defined (CONFIG_STM32F7_TIM10_ADC) || \ + defined(CONFIG_STM32_TIM10_DAC) || defined(CONFIG_STM32F7_TIM10_QE) +# undef CONFIG_STM32_TIM10 #endif -#if defined(CONFIG_STM32F7_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ - defined(CONFIG_STM32F7_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) -# undef CONFIG_STM32F7_TIM11 +#if defined(CONFIG_STM32_TIM11_PWM) || defined (CONFIG_STM32F7_TIM11_ADC) || \ + defined(CONFIG_STM32_TIM11_DAC) || defined(CONFIG_STM32F7_TIM11_QE) +# undef CONFIG_STM32_TIM11 #endif -#if defined(CONFIG_STM32F7_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ - defined(CONFIG_STM32F7_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) -# undef CONFIG_STM32F7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32F7_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32F7_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32F7_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ - defined(CONFIG_STM32F7_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) -# undef CONFIG_STM32F7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32F7_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32F7_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32F7_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ - defined(CONFIG_STM32F7_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) -# undef CONFIG_STM32F7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32F7_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32F7_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32F7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM9) +#if defined(CONFIG_STM32_TIM9) # if defined(GPIO_TIM9_CH1OUT) ||defined(GPIO_TIM9_CH2OUT)||\ defined(GPIO_TIM9_CH3OUT) ||defined(GPIO_TIM9_CH4OUT) # define HAVE_TIM9_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM10) +#if defined(CONFIG_STM32_TIM10) # if defined(GPIO_TIM10_CH1OUT) ||defined(GPIO_TIM10_CH2OUT)||\ defined(GPIO_TIM10_CH3OUT) ||defined(GPIO_TIM10_CH4OUT) # define HAVE_TIM10_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM11) +#if defined(CONFIG_STM32_TIM11) # if defined(GPIO_TIM11_CH1OUT) ||defined(GPIO_TIM11_CH2OUT)||\ defined(GPIO_TIM11_CH3OUT) ||defined(GPIO_TIM11_CH4OUT) # define HAVE_TIM11_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT)||\ defined(GPIO_TIM12_CH3OUT) ||defined(GPIO_TIM12_CH4OUT) # define HAVE_TIM12_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) ||defined(GPIO_TIM13_CH2OUT)||\ defined(GPIO_TIM13_CH3OUT) ||defined(GPIO_TIM13_CH4OUT) # define HAVE_TIM13_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) ||defined(GPIO_TIM14_CH2OUT)||\ defined(GPIO_TIM14_CH3OUT) ||defined(GPIO_TIM14_CH4OUT) # define HAVE_TIM14_GPIOCONFIG 1 @@ -216,13 +216,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14) /**************************************************************************** * Private Types @@ -326,14 +326,14 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* TIM2 is 32-bits on all except F10x, L0x, and L1x lines */ -#if defined(CONFIG_STM32F7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif /* TIM5 is 32-bits on all except F10x lines */ -#if defined(CONFIG_STM32F7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -431,72 +431,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -550,72 +550,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: vectorno = STM32_IRQ_TIM9; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: vectorno = STM32_IRQ_TIM10; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: vectorno = STM32_IRQ_TIM11; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; @@ -818,7 +818,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -843,7 +843,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -872,7 +872,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -901,7 +901,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -930,7 +930,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -959,7 +959,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -984,7 +984,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -# ifdef CONFIG_STM32F7_TIM9 +# ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: switch (channel) { @@ -1013,7 +1013,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: switch (channel) { @@ -1042,7 +1042,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: switch (channel) { @@ -1071,7 +1071,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1100,7 +1100,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1129,7 +1129,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1240,7 +1240,7 @@ struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -1249,7 +1249,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -1258,7 +1258,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -1267,7 +1267,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -1276,7 +1276,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -1285,7 +1285,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -1294,7 +1294,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -1303,7 +1303,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -1312,7 +1312,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 struct stm32_tim_priv_s stm32_tim9_priv = { .ops = &stm32_tim_ops, @@ -1321,7 +1321,7 @@ struct stm32_tim_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 struct stm32_tim_priv_s stm32_tim10_priv = { .ops = &stm32_tim_ops, @@ -1330,7 +1330,7 @@ struct stm32_tim_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 struct stm32_tim_priv_s stm32_tim11_priv = { .ops = &stm32_tim_ops, @@ -1339,7 +1339,7 @@ struct stm32_tim_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -1348,7 +1348,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -1357,7 +1357,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -1378,85 +1378,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: dev = (struct stm32_tim_dev_s *)&stm32_tim9_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM9EN); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: dev = (struct stm32_tim_dev_s *)&stm32_tim10_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM10EN); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: dev = (struct stm32_tim_dev_s *)&stm32_tim11_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM11EN); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM14EN); @@ -1488,72 +1488,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM9EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM10EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM11EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM14EN, 0); break; @@ -1569,4 +1569,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32F7_TIM1 || ... || TIM8) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c index f0f5dda38f0..1005d174f75 100644 --- a/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32f7/stm32_tim_lowerhalf.c @@ -56,13 +56,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32F7_TIM1) || defined(CONFIG_STM32F7_TIM2) || \ - defined(CONFIG_STM32F7_TIM3) || defined(CONFIG_STM32F7_TIM4) || \ - defined(CONFIG_STM32F7_TIM5) || defined(CONFIG_STM32F7_TIM6) || \ - defined(CONFIG_STM32F7_TIM7) || defined(CONFIG_STM32F7_TIM8) || \ - defined(CONFIG_STM32F7_TIM9) || defined(CONFIG_STM32F7_TIM10) || \ - defined(CONFIG_STM32F7_TIM11) || defined(CONFIG_STM32F7_TIM12) || \ - defined(CONFIG_STM32F7_TIM13) || defined(CONFIG_STM32F7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -144,7 +144,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -152,7 +152,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -160,7 +160,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -168,7 +168,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -176,7 +176,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -184,7 +184,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -192,7 +192,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -200,7 +200,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -208,7 +208,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -216,7 +216,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -224,7 +224,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -232,7 +232,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -240,7 +240,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -248,7 +248,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -482,72 +482,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32f7/stm32_uart.h b/arch/arm/src/stm32f7/stm32_uart.h index d65dbe36b2f..e3f555f43ad 100644 --- a/arch/arm/src/stm32f7/stm32_uart.h +++ b/arch/arm/src/stm32f7/stm32_uart.h @@ -41,43 +41,43 @@ */ #if STM32_NUART < 4 -# undef CONFIG_STM32F7_UART8 +# undef CONFIG_STM32_UART8 #endif #if STM32_NUART < 3 -# undef CONFIG_STM32F7_UART7 +# undef CONFIG_STM32_UART7 #endif #if STM32_NUART < 2 -# undef CONFIG_STM32F7_UART5 +# undef CONFIG_STM32_UART5 #endif #if STM32_NUART < 1 -# undef CONFIG_STM32F7_UART4 +# undef CONFIG_STM32_UART4 #endif #if STM32_NUSART < 4 -# undef CONFIG_STM32F7_USART6 +# undef CONFIG_STM32_USART6 #endif #if STM32_NUSART < 3 -# undef CONFIG_STM32F7_USART3 +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32F7_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32F7_USART1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32F7_USART1) || defined(CONFIG_STM32F7_USART2) || \ - defined(CONFIG_STM32F7_USART3) || defined(CONFIG_STM32F7_UART4) || \ - defined(CONFIG_STM32F7_UART5) || defined(CONFIG_STM32F7_USART6) || \ - defined(CONFIG_STM32F7_UART7) || defined(CONFIG_STM32F7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32F7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -195,42 +195,42 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32F7_USART1 +#ifndef CONFIG_STM32_USART1 # undef CONFIG_USART1_RXDMA # undef CONFIG_USART1_TXDMA #endif -#ifndef CONFIG_STM32F7_USART2 +#ifndef CONFIG_STM32_USART2 # undef CONFIG_USART2_RXDMA # undef CONFIG_USART2_TXDMA #endif -#ifndef CONFIG_STM32F7_USART3 +#ifndef CONFIG_STM32_USART3 # undef CONFIG_USART3_RXDMA # undef CONFIG_USART3_TXDMA #endif -#ifndef CONFIG_STM32F7_UART4 +#ifndef CONFIG_STM32_UART4 # undef CONFIG_UART4_RXDMA # undef CONFIG_UART4_TXDMA #endif -#ifndef CONFIG_STM32F7_UART5 +#ifndef CONFIG_STM32_UART5 # undef CONFIG_UART5_RXDMA # undef CONFIG_UART5_TXDMA #endif -#ifndef CONFIG_STM32F7_USART6 +#ifndef CONFIG_STM32_USART6 # undef CONFIG_USART6_RXDMA # undef CONFIG_USART6_TXDMA #endif -#ifndef CONFIG_STM32F7_UART7 +#ifndef CONFIG_STM32_UART7 # undef CONFIG_UART7_RXDMA # undef CONFIG_UART7_TXDMA #endif -#ifndef CONFIG_STM32F7_UART8 +#ifndef CONFIG_STM32_UART8 # undef CONFIG_UART8_RXDMA # undef CONFIG_UART8_TXDMA #endif @@ -300,42 +300,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32F7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32F7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif diff --git a/arch/arm/src/stm32f7/stm32_usbhost.h b/arch/arm/src/stm32f7/stm32_usbhost.h index 7ae4f8e9d25..68eaee020a8 100644 --- a/arch/arm/src/stm32f7/stm32_usbhost.h +++ b/arch/arm/src/stm32f7/stm32_usbhost.h @@ -28,10 +28,10 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32F7_OTGFSHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32F7_SYSCFG - Needed + * CONFIG_STM32_OTGFSHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -44,7 +44,7 @@ * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGFSHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGFSHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32F7_OTGFS || CONFIG_STM32F7_OTGFSHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGFSHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32F7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c index 2633267d255..629881f1196 100644 --- a/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c @@ -167,13 +167,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -185,31 +185,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -217,9 +217,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -229,7 +229,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -252,31 +252,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -303,13 +303,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -336,151 +336,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -492,19 +492,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -531,67 +531,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -601,56 +601,56 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_OTGFSHS -#ifdef CONFIG_STM32F7_INTERNAL_ULPI +#ifdef CONFIG_STM32_OTGFSHS +#ifdef CONFIG_STM32_INTERNAL_ULPI regval |= RCC_APB2ENR_OTGPHYCEN; #endif @@ -669,7 +669,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -831,7 +831,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -857,7 +857,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -865,14 +865,14 @@ static void stm32_stdclockconfig(void) regval &= ~(RCC_PLLSAICFGR_PLLSAIN_MASK | RCC_PLLSAICFGR_PLLSAIP_MASK | RCC_PLLSAICFGR_PLLSAIQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_PLLSAICFGR_PLLSAIR_MASK # endif ); regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN | STM32_RCC_PLLSAICFGR_PLLSAIP | STM32_RCC_PLLSAICFGR_PLLSAIQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_PLLSAICFGR_PLLSAIR # endif ); @@ -881,7 +881,7 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_DCKCFGR1); regval &= ~(RCC_DCKCFGR1_PLLI2SDIVQ_MASK | RCC_DCKCFGR1_PLLSAIDIVQ_MASK -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | RCC_DCKCFGR1_PLLSAIDIVR_MASK # endif | RCC_DCKCFGR1_SAI1SEL_MASK @@ -890,7 +890,7 @@ static void stm32_stdclockconfig(void) regval |= (STM32_RCC_DCKCFGR1_PLLI2SDIVQ | STM32_RCC_DCKCFGR1_PLLSAIDIVQ -# if defined(CONFIG_STM32F7_LTDC) +# if defined(CONFIG_STM32_LTDC) | STM32_RCC_DCKCFGR1_PLLSAIDIVR # endif | STM32_RCC_DCKCFGR1_SAI1SRC @@ -919,13 +919,13 @@ static void stm32_stdclockconfig(void) regval = getreg32(STM32_RCC_PLLI2SCFGR); regval &= ~(RCC_PLLI2SCFGR_PLLI2SN_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_PLLI2SCFGR_PLLI2SP_MASK # endif | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_PLLI2SCFGR_PLLI2SP # endif | STM32_RCC_PLLI2SCFGR_PLLI2SQ @@ -956,7 +956,7 @@ static void stm32_stdclockconfig(void) | RCC_DCKCFGR2_I2C1SEL_MASK | RCC_DCKCFGR2_I2C2SEL_MASK | RCC_DCKCFGR2_I2C3SEL_MASK -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | RCC_DCKCFGR2_I2C4SEL_MASK | RCC_DCKCFGR2_CECSEL_MASK # endif @@ -975,7 +975,7 @@ static void stm32_stdclockconfig(void) | STM32_RCC_DCKCFGR2_I2C1SRC | STM32_RCC_DCKCFGR2_I2C2SRC | STM32_RCC_DCKCFGR2_I2C3SRC -# if !defined(CONFIG_STM32F7_STM32F72XX) && !defined(CONFIG_STM32F7_STM32F73XX) +# if !defined(CONFIG_STM32_STM32F72XX) && !defined(CONFIG_STM32_STM32F73XX) | STM32_RCC_DCKCFGR2_I2C4SRC | STM32_RCC_DCKCFGR2_CECSRC # endif @@ -986,13 +986,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index f2a51b9e306..fa7e56b6c6c 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -169,13 +169,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -187,31 +187,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -219,9 +219,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -231,7 +231,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -254,31 +254,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -305,13 +305,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -338,151 +338,151 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -494,19 +494,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -533,67 +533,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -603,49 +603,49 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; @@ -664,7 +664,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -759,7 +759,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -826,7 +826,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -852,7 +852,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -961,13 +961,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 070060097d5..e14d7017494 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 -/* If CONFIG_STM32F7_DSIHOST is defined in the board configuration, then +/* If CONFIG_STM32_DSIHOST is defined in the board configuration, then * STM32_RCC_DCKCFGR2_DSISRC must also be defined to select the clock * source. */ @@ -177,13 +177,13 @@ static inline void rcc_enableahb1(void) ); #endif -#ifdef CONFIG_STM32F7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32F7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB1ENR_BKPSRAMEN; @@ -195,31 +195,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DTCMRAMEN; #endif -#ifdef CONFIG_STM32F7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32F7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32F7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock */ regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32F7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Ethernet MAC clocking */ regval |= (RCC_AHB1ENR_ETHMACEN | RCC_AHB1ENR_ETHMACTXEN | \ RCC_AHB1ENR_ETHMACRXEN); -#ifdef CONFIG_STM32F7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Precision Time Protocol (PTP) */ regval |= RCC_AHB1ENR_ETHMACPTPEN; @@ -227,9 +227,9 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32F7_OTGFSHS -# if defined(CONFIG_STM32F7_INTERNAL_ULPI) || \ - defined(CONFIG_STM32F7_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGFSHS +# if defined(CONFIG_STM32_INTERNAL_ULPI) || \ + defined(CONFIG_STM32_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ @@ -239,7 +239,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_OTGHSEN; #endif -#endif /* CONFIG_STM32F7_OTGFSHS */ +#endif /* CONFIG_STM32_OTGFSHS */ putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ } @@ -262,31 +262,31 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32F7_DCMI +#ifdef CONFIG_STM32_DCMI /* Camera interface enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32F7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_CRYPEN; #endif -#ifdef CONFIG_STM32F7_HASH +#ifdef CONFIG_STM32_HASH /* Hash modules clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32F7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; @@ -313,13 +313,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI /* FQuad SPI memory controller clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -346,157 +346,157 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR); -#ifdef CONFIG_STM32F7_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR_TIM2EN; #endif -#ifdef CONFIG_STM32F7_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR_TIM3EN; #endif -#ifdef CONFIG_STM32F7_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR_TIM4EN; #endif -#ifdef CONFIG_STM32F7_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR_TIM5EN; #endif -#ifdef CONFIG_STM32F7_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR_TIM6EN; #endif -#ifdef CONFIG_STM32F7_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR_TIM7EN; #endif -#ifdef CONFIG_STM32F7_TIM12 +#ifdef CONFIG_STM32_TIM12 /* TIM12 clock enable */ regval |= RCC_APB1ENR_TIM12EN; #endif -#ifdef CONFIG_STM32F7_TIM13 +#ifdef CONFIG_STM32_TIM13 /* TIM13 clock enable */ regval |= RCC_APB1ENR_TIM13EN; #endif -#ifdef CONFIG_STM32F7_TIM14 +#ifdef CONFIG_STM32_TIM14 /* TIM14 clock enable */ regval |= RCC_APB1ENR_TIM14EN; #endif -#ifdef CONFIG_STM32F7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low-power timer 1 clock enable */ regval |= RCC_APB1ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32F7_WWDG +#ifdef CONFIG_STM32_WWDG /* Window watchdog clock enable */ regval |= RCC_APB1ENR_WWDGEN; #endif -#if defined(CONFIG_STM32F7_SPI2) || defined(CONFIG_STM32F7_I2S2) +#if defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_I2S2) /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#if defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_I2S3) +#if defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_I2S3) /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; #endif -#ifdef CONFIG_STM32F7_SPDIFRX +#ifdef CONFIG_STM32_SPDIFRX /* SPDIFRX clock enable */ regval |= RCC_APB1ENR_SPDIFRXEN; #endif -#ifdef CONFIG_STM32F7_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR_USART2EN; #endif -#ifdef CONFIG_STM32F7_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR_USART3EN; #endif -#ifdef CONFIG_STM32F7_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR_UART4EN; #endif -#ifdef CONFIG_STM32F7_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR_UART5EN; #endif -#ifdef CONFIG_STM32F7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR_I2C1EN; #endif -#ifdef CONFIG_STM32F7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR_I2C2EN; #endif -#ifdef CONFIG_STM32F7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR_I2C3EN; #endif -#ifdef CONFIG_STM32F7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR_I2C4EN; #endif -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR_CAN1EN; #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */ regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN); #endif -#ifdef CONFIG_STM32F7_CAN3 +#ifdef CONFIG_STM32_CAN3 /* CAN3 clock enable. */ regval |= (RCC_APB1ENR_CAN3EN); #endif -#ifdef CONFIG_STM32F7_CEC +#ifdef CONFIG_STM32_CEC /* CEC clock enable. */ regval |= RCC_APB1ENR_CECEN; @@ -508,19 +508,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_PWREN; -#if defined (CONFIG_STM32F7_DAC1) || defined(CONFIG_STM32F7_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR_DACEN; #endif -#ifdef CONFIG_STM32F7_UART7 +#ifdef CONFIG_STM32_UART7 /* UART7 clock enable */ regval |= RCC_APB1ENR_UART7EN; #endif -#ifdef CONFIG_STM32F7_UART8 +#ifdef CONFIG_STM32_UART8 /* UART8 clock enable */ regval |= RCC_APB1ENR_UART8EN; @@ -547,67 +547,67 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32F7_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32F7_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32F7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32F7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; #endif -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* ADC1 clock enable */ regval |= RCC_APB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32F7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* ADC2 clock enable */ regval |= RCC_APB2ENR_ADC2EN; #endif -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_APB2ENR_ADC3EN; #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDIO_1 clock enable */ regval |= RCC_APB2ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32F7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDIO_2 clock enable */ regval |= RCC_APB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; @@ -617,55 +617,55 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; -#ifdef CONFIG_STM32F7_TIM9 +#ifdef CONFIG_STM32_TIM9 /* TIM9 clock enable */ regval |= RCC_APB2ENR_TIM9EN; #endif -#ifdef CONFIG_STM32F7_TIM10 +#ifdef CONFIG_STM32_TIM10 /* TIM10 clock enable */ regval |= RCC_APB2ENR_TIM10EN; #endif -#ifdef CONFIG_STM32F7_TIM11 +#ifdef CONFIG_STM32_TIM11 /* TIM11 clock enable */ regval |= RCC_APB2ENR_TIM11EN; #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32F7_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32F7_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB2ENR_LTDCEN; #endif -#ifdef CONFIG_STM32F7_DSIHOST +#ifdef CONFIG_STM32_DSIHOST /* LTDC clock enable */ regval |= RCC_APB2ENR_DSIEN; @@ -684,7 +684,7 @@ static inline void rcc_enableapb2(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_STM32F7_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -779,7 +779,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32F7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -846,7 +846,7 @@ static void stm32_stdclockconfig(void) regval = FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); -#ifdef CONFIG_STM32F7_FLASH_ART_ACCELERATOR +#ifdef CONFIG_STM32_FLASH_ART_ACCELERATOR /* The Flash memory interface accelerates code execution with a system * of instruction prefetch and cache lines on ITCM interface (ART * Accelerator™). @@ -872,7 +872,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLSAI) +#if defined(CONFIG_STM32_LTDC) || defined(CONFIG_STM32F7_PLLSAI) /* Configure PLLSAI */ @@ -990,13 +990,13 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_DCKCFGR2); -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32F7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/boards/arm/stm32f7/common/Kconfig b/boards/arm/stm32f7/common/Kconfig index 2d926e6634d..8be75fe6173 100644 --- a/boards/arm/stm32f7/common/Kconfig +++ b/boards/arm/stm32f7/common/Kconfig @@ -3,178 +3,178 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config STM32F7_ROMFS +config STM32_ROMFS bool "Automount baked-in ROMFS image" default n depends on FS_ROMFS ---help--- - Select STM32F7_ROMFS_IMAGEFILE, STM32F7_ROMFS_DEV_MINOR, STM32F7_ROMFS_MOUNTPOINT + Select STM32_ROMFS_IMAGEFILE, STM32_ROMFS_DEV_MINOR, STM32_ROMFS_MOUNTPOINT -config STM32F7_ROMFS_DEV_MINOR +config STM32_ROMFS_DEV_MINOR int "Minor for the block device backing the data" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default 64 -config STM32F7_ROMFS_MOUNTPOINT +config STM32_ROMFS_MOUNTPOINT string "Mountpoint of the custom romfs image" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "/rom" -config STM32F7_ROMFS_IMAGEFILE +config STM32_ROMFS_IMAGEFILE string "ROMFS image file to include into build" - depends on STM32F7_ROMFS + depends on STM32_ROMFS default "../../../rom.img" -config STM32F7_SPI_TEST +config STM32_SPI_TEST bool "Enable SPI test" default n ---help--- Enable Spi test - initialize and configure SPI to send - STM32F7_SPI_TEST_MESSAGE text. The text is sent on the + STM32_SPI_TEST_MESSAGE text. The text is sent on the selected SPI Buses with the configured parameters. Note the CS lines will not be asserted. -if STM32F7_SPI_TEST +if STM32_SPI_TEST -config STM32F7_SPI_TEST_MESSAGE +config STM32_SPI_TEST_MESSAGE string "Text to Send on SPI Bus(es)" default "Hello World" - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Text to sent on SPI bus(es) -config STM32F7_SPI1_TEST +config STM32_SPI1_TEST bool "Test SPI bus 1" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 1 -if STM32F7_SPI1_TEST +if STM32_SPI1_TEST -config STM32F7_SPI1_TEST_FREQ +config STM32_SPI1_TEST_FREQ int "SPI 1 Clock Freq in Hz" default 1000000 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 Clock Freq -config STM32F7_SPI1_TEST_BITS +config STM32_SPI1_TEST_BITS int "SPI 1 number of bits" default 8 - depends on STM32F7_SPI1_TEST + depends on STM32_SPI1_TEST ---help--- Sets SPI 1 bit length choice prompt "SPI BUS 1 Clock Mode" - default STM32F7_SPI1_TEST_MODE3 + default STM32_SPI1_TEST_MODE3 ---help--- Sets SPI 1 clock mode -config STM32F7_SPI1_TEST_MODE0 +config STM32_SPI1_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI1_TEST_MODE1 +config STM32_SPI1_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI1_TEST_MODE2 +config STM32_SPI1_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI1_TEST_MODE3 +config STM32_SPI1_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 1 Clock Mode" -endif # STM32F7_SPI1_TEST +endif # STM32_SPI1_TEST -config STM32F7_SPI2_TEST +config STM32_SPI2_TEST bool "Test SPI bus 2" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 2 -if STM32F7_SPI2_TEST +if STM32_SPI2_TEST -config STM32F7_SPI2_TEST_FREQ +config STM32_SPI2_TEST_FREQ int "SPI 2 Clock Freq in Hz" default 12000000 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 Clock Freq -config STM32F7_SPI2_TEST_BITS +config STM32_SPI2_TEST_BITS int "SPI 2 number of bits" default 8 - depends on STM32F7_SPI2_TEST + depends on STM32_SPI2_TEST ---help--- Sets SPI 2 bit length choice prompt "SPI BUS 2 Clock Mode" - default STM32F7_SPI2_TEST_MODE3 + default STM32_SPI2_TEST_MODE3 ---help--- Sets SPI 2 clock mode -config STM32F7_SPI2_TEST_MODE0 +config STM32_SPI2_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI2_TEST_MODE1 +config STM32_SPI2_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI2_TEST_MODE2 +config STM32_SPI2_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI2_TEST_MODE3 +config STM32_SPI2_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 2 Clock Mode" -endif # STM32F7_SPI2_TEST +endif # STM32_SPI2_TEST -config STM32F7_SPI3_TEST +config STM32_SPI3_TEST bool "Test SPI bus 3" default n - depends on STM32F7_SPI_TEST + depends on STM32_SPI_TEST ---help--- Enable Spi test - on SPI BUS 3 -if STM32F7_SPI3_TEST +if STM32_SPI3_TEST -config STM32F7_SPI3_TEST_FREQ +config STM32_SPI3_TEST_FREQ int "SPI 3 Clock Freq in Hz" default 40000000 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 Clock Freq -config STM32F7_SPI3_TEST_BITS +config STM32_SPI3_TEST_BITS int "SPI 3 number of bits" default 8 - depends on STM32F7_SPI3_TEST + depends on STM32_SPI3_TEST ---help--- Sets SPI 3 bit length choice prompt "SPI BUS 3 Clock Mode" - default STM32F7_SPI3_TEST_MODE3 + default STM32_SPI3_TEST_MODE3 ---help--- Sets SPI 3 clock mode -config STM32F7_SPI3_TEST_MODE0 +config STM32_SPI3_TEST_MODE0 bool "CPOL=0 CPHA=0" -config STM32F7_SPI3_TEST_MODE1 +config STM32_SPI3_TEST_MODE1 bool "CPOL=0 CPHA=1" -config STM32F7_SPI3_TEST_MODE2 +config STM32_SPI3_TEST_MODE2 bool "CPOL=1 CPHA=0" -config STM32F7_SPI3_TEST_MODE3 +config STM32_SPI3_TEST_MODE3 bool "CPOL=1 CPHA=1" endchoice # "SPI BUS 3 Clock Mode" -endif # STM32F7_SPI3_TEST -endif # STM32F7_SPI_TEST +endif # STM32_SPI3_TEST +endif # STM32_SPI_TEST diff --git a/boards/arm/stm32f7/common/include/stm32_can_setup.h b/boards/arm/stm32f7/common/include/stm32_can_setup.h index 5361bfe204a..d0632d611df 100644 --- a/boards/arm/stm32f7/common/include/stm32_can_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_can_setup.h @@ -61,7 +61,7 @@ extern "C" * Name: stm32_can_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER int stm32_can_setup(void); #endif diff --git a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h index 971f2216dcb..5dcab9fd7b5 100644 --- a/boards/arm/stm32f7/common/include/stm32_cansock_setup.h +++ b/boards/arm/stm32f7/common/include/stm32_cansock_setup.h @@ -61,7 +61,7 @@ extern "C" * Name: stm32_cansock_setup ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET int stm32_cansock_setup(void); #endif diff --git a/boards/arm/stm32f7/common/include/stm32_romfs.h b/boards/arm/stm32f7/common/include/stm32_romfs.h index 3b52acfa36f..577b3a7f4ff 100644 --- a/boards/arm/stm32f7/common/include/stm32_romfs.h +++ b/boards/arm/stm32f7/common/include/stm32_romfs.h @@ -43,7 +43,7 @@ #include -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /**************************************************************************** * Pre-processor Definitions @@ -72,6 +72,6 @@ int stm32_romfs_initialize(void); -#endif /* CONFIG_STM32F7_ROMFS */ +#endif /* CONFIG_STM32_ROMFS */ #endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_ROMFS_H */ diff --git a/boards/arm/stm32f7/common/include/stm32_spitest.h b/boards/arm/stm32f7/common/include/stm32_spitest.h index 09605759e1e..860042f9469 100644 --- a/boards/arm/stm32f7/common/include/stm32_spitest.h +++ b/boards/arm/stm32f7/common/include/stm32_spitest.h @@ -62,7 +62,7 @@ extern "C" * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt index f653591bd15..d4b612a0f4b 100644 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ b/boards/arm/stm32f7/common/src/CMakeLists.txt @@ -34,16 +34,16 @@ if(CONFIG_AUDIO_CS4344) list(APPEND SRCS stm32_cs4344.c) endif() -if(CONFIG_STM32F7_CAN) - if(CONFIG_STM32F7_CAN_CHARDRIVER) +if(CONFIG_STM32_CAN) + if(CONFIG_STM32_CAN_CHARDRIVER) list(APPEND SRCS stm32_can_setup.c) endif() - if(CONFIG_STM32F7_CAN_SOCKET) + if(CONFIG_STM32_CAN_SOCKET) list(APPEND SRCS stm32_cansock_setup.c) endif() endif() -if(CONFIG_STM32F7_ROMFS) +if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() @@ -51,7 +51,7 @@ if(CONFIG_BOARDCTL_RESET) list(APPEND SRCS stm32_reset.c) endif() -if(CONFIG_STM32F7_SPI_TEST) +if(CONFIG_STM32_SPI_TEST) list(APPEND SRCS stm32_spitest.c) endif() diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs index 04321561a58..0a4f96c20c4 100644 --- a/boards/arm/stm32f7/common/src/Make.defs +++ b/boards/arm/stm32f7/common/src/Make.defs @@ -34,16 +34,16 @@ ifeq ($(CONFIG_AUDIO_CS4344),y) CSRCS += stm32_cs4344.c endif -ifeq ($(CONFIG_STM32F7_CAN),y) -ifeq ($(CONFIG_STM32F7_CAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_CAN),y) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) CSRCS += stm32_can_setup.c endif -ifeq ($(CONFIG_STM32F7_CAN_SOCKET),y) +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) CSRCS += stm32_cansock_setup.c endif endif -ifeq ($(CONFIG_STM32F7_ROMFS),y) +ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif @@ -51,7 +51,7 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += stm32_reset.c endif -ifeq ($(CONFIG_STM32F7_SPI_TEST),y) +ifeq ($(CONFIG_STM32_SPI_TEST),y) CSRCS += stm32_spitest.c endif diff --git a/boards/arm/stm32f7/common/src/stm32_can_setup.c b/boards/arm/stm32f7/common/src/stm32_can_setup.c index 5f62d6da00f..2eedf06992e 100644 --- a/boards/arm/stm32f7/common/src/stm32_can_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_can_setup.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #else # define CAN_PORT 2 @@ -60,7 +60,7 @@ int stm32_can_setup(void) { -#if defined(CONFIG_STM32F7_CAN1) +#if defined(CONFIG_STM32_CAN1) struct can_dev_s *can; int ret; @@ -85,7 +85,7 @@ int stm32_can_setup(void) return OK; #endif -#if defined(CONFIG_STM32F7_CAN2) +#if defined(CONFIG_STM32_CAN2) struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c index 2bb60d2b8bc..58dbf738cfe 100644 --- a/boards/arm/stm32f7/common/src/stm32_cansock_setup.c +++ b/boards/arm/stm32f7/common/src/stm32_cansock_setup.c @@ -36,7 +36,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32F7_CAN1) && !defined(CONFIG_STM32F7_CAN2) +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) # error "No CAN is enable. Please enable at least one CAN device" #endif @@ -58,7 +58,7 @@ int stm32_cansock_setup(void) UNUSED(ret); -#ifdef CONFIG_STM32F7_CAN1 +#ifdef CONFIG_STM32_CAN1 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(1); @@ -69,7 +69,7 @@ int stm32_cansock_setup(void) } #endif -#ifdef CONFIG_STM32F7_CAN2 +#ifdef CONFIG_STM32_CAN2 /* Call stm32_caninitialize() to get an instance of the CAN interface */ ret = stm32_cansockinitialize(2); diff --git a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c index 53fe0927d43..1d105e29b0e 100644 --- a/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f7/common/src/stm32_romfs_initialize.c @@ -54,20 +54,20 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_ROMFS -# error "CONFIG_STM32F7_ROMFS must be defined" +#ifndef CONFIG_STM32_ROMFS +# error "CONFIG_STM32_ROMFS must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_IMAGEFILE -# error "CONFIG_STM32F7_ROMFS_IMAGEFILE must be defined" +#ifndef CONFIG_STM32_ROMFS_IMAGEFILE +# error "CONFIG_STM32_ROMFS_IMAGEFILE must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_DEV_MINOR -# error "CONFIG_STM32F7_ROMFS_DEV_MINOR must be defined" +#ifndef CONFIG_STM32_ROMFS_DEV_MINOR +# error "CONFIG_STM32_ROMFS_DEV_MINOR must be defined" #endif -#ifndef CONFIG_STM32F7_ROMFS_MOUNTPOINT -# error "CONFIG_STM32F7_ROMFS_MOUNTPOINT must be defined" +#ifndef CONFIG_STM32_ROMFS_MOUNTPOINT +# error "CONFIG_STM32_ROMFS_MOUNTPOINT must be defined" #endif #define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) @@ -76,7 +76,7 @@ #define STR(m) STR2(m) #define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) -#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32F7_ROMFS_DEV_MINOR) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_STM32_ROMFS_DEV_MINOR) /**************************************************************************** * Private Data @@ -87,7 +87,7 @@ __asm__ ( ".balign 16\n" ".globl romfs_data_begin\n" "romfs_data_begin:\n" - ".incbin " STR(CONFIG_STM32F7_ROMFS_IMAGEFILE) "\n"\ + ".incbin " STR(CONFIG_STM32_ROMFS_IMAGEFILE) "\n"\ \ ".balign " STR(ROMFS_SECTOR_SIZE) "\n" ".globl romfs_data_end\n" @@ -125,7 +125,7 @@ int stm32_romfs_initialize(void) romfs_data_len = romfs_data_end - romfs_data_begin; - ret = romdisk_register(CONFIG_STM32F7_ROMFS_DEV_MINOR, romfs_data_begin, + ret = romdisk_register(CONFIG_STM32_ROMFS_DEV_MINOR, romfs_data_begin, NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); if (ret < 0) { @@ -136,14 +136,14 @@ int stm32_romfs_initialize(void) /* Mount the file system */ finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + CONFIG_STM32_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); - ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, + ret = nx_mount(MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, "romfs", MS_RDONLY, NULL); if (ret < 0) { ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", - MOUNT_DEVNAME, CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + MOUNT_DEVNAME, CONFIG_STM32_ROMFS_MOUNTPOINT, ret); return ret; } diff --git a/boards/arm/stm32f7/common/src/stm32_spitest.c b/boards/arm/stm32f7/common/src/stm32_spitest.c index 51bf2d63ca6..5ae8b71833a 100644 --- a/boards/arm/stm32f7/common/src/stm32_spitest.c +++ b/boards/arm/stm32f7/common/src/stm32_spitest.c @@ -43,42 +43,42 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1_TEST) -# if defined(CONFIG_STM32F7_SPI1_TEST_MODE0) +#if defined(CONFIG_STM32_SPI1_TEST) +# if defined(CONFIG_STM32_SPI1_TEST_MODE0) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE1) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE2) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI1_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI1_TEST_MODE3) # define CONFIG_STM32F7_SPI1_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI1_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) -# if defined(CONFIG_STM32F7_SPI2_TEST_MODE0) +#if defined(CONFIG_STM32_SPI2_TEST) +# if defined(CONFIG_STM32_SPI2_TEST_MODE0) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE1) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE2) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI2_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI2_TEST_MODE3) # define CONFIG_STM32F7_SPI2_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI2_TEST_MODEx defined" # endif #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) -# if defined(CONFIG_STM32F7_SPI3_TEST_MODE0) +#if defined(CONFIG_STM32_SPI3_TEST) +# if defined(CONFIG_STM32_SPI3_TEST_MODE0) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE0 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE1) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE1) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE1 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE2) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE2) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE2 -# elif defined(CONFIG_STM32F7_SPI3_TEST_MODE3) +# elif defined(CONFIG_STM32_SPI3_TEST_MODE3) # define CONFIG_STM32F7_SPI3_TEST_MODE SPIDEV_MODE3 # else # error "No CONFIG_STM32F7_SPI3_TEST_MODEx defined" @@ -89,13 +89,13 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) struct spi_dev_s *g_spi1; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) struct spi_dev_s *g_spi2; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) struct spi_dev_s *g_spi3; #endif @@ -108,7 +108,7 @@ struct spi_dev_s *g_spi3; * * Description: * Called to create the defined SPI buses and test them by initializing - * them and sending the CONFIG_STM32F7_SPI_TEST_MESSAGE (no chip select). + * them and sending the CONFIG_STM32_SPI_TEST_MESSAGE (no chip select). * ****************************************************************************/ @@ -116,9 +116,9 @@ int stm32_spidev_bus_test(void) { /* Configure and test SPI- */ - uint8_t *tx = (uint8_t *)CONFIG_STM32F7_SPI_TEST_MESSAGE; + uint8_t *tx = (uint8_t *)CONFIG_STM32_SPI_TEST_MESSAGE; -#if defined(CONFIG_STM32F7_SPI1_TEST) +#if defined(CONFIG_STM32_SPI1_TEST) g_spi1 = stm32_spibus_initialize(1); if (!g_spi1) @@ -129,14 +129,14 @@ int stm32_spidev_bus_test(void) /* Default SPI1 to STM32_SPI1_FREQ and mode */ - SPI_SETFREQUENCY(g_spi1, CONFIG_STM32F7_SPI1_TEST_FREQ); - SPI_SETBITS(g_spi1, CONFIG_STM32F7_SPI1_TEST_BITS); + SPI_SETFREQUENCY(g_spi1, CONFIG_STM32_SPI1_TEST_FREQ); + SPI_SETBITS(g_spi1, CONFIG_STM32_SPI1_TEST_BITS); SPI_SETMODE(g_spi1, CONFIG_STM32F7_SPI1_TEST_MODE); SPI_EXCHANGE(g_spi1, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI2_TEST) +#if defined(CONFIG_STM32_SPI2_TEST) g_spi2 = stm32_spibus_initialize(2); if (!g_spi2) @@ -147,14 +147,14 @@ int stm32_spidev_bus_test(void) /* Default SPI2 to STM32_SPI2_FREQ and mode */ - SPI_SETFREQUENCY(g_spi2, CONFIG_STM32F7_SPI2_TEST_FREQ); - SPI_SETBITS(g_spi2, CONFIG_STM32F7_SPI2_TEST_BITS); + SPI_SETFREQUENCY(g_spi2, CONFIG_STM32_SPI2_TEST_FREQ); + SPI_SETBITS(g_spi2, CONFIG_STM32_SPI2_TEST_BITS); SPI_SETMODE(g_spi2, CONFIG_STM32F7_SPI2_TEST_MODE); SPI_EXCHANGE(g_spi2, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif -#if defined(CONFIG_STM32F7_SPI3_TEST) +#if defined(CONFIG_STM32_SPI3_TEST) g_spi3 = stm32_spibus_initialize(3); if (!g_spi3) @@ -165,11 +165,11 @@ int stm32_spidev_bus_test(void) /* Default SPI3 to STM32_SPI3_FREQ and mode */ - SPI_SETFREQUENCY(g_spi3, CONFIG_STM32F7_SPI3_TEST_FREQ); - SPI_SETBITS(g_spi3, CONFIG_STM32F7_SPI3_TEST_BITS); + SPI_SETFREQUENCY(g_spi3, CONFIG_STM32_SPI3_TEST_FREQ); + SPI_SETBITS(g_spi3, CONFIG_STM32_SPI3_TEST_BITS); SPI_SETMODE(g_spi3, CONFIG_STM32F7_SPI3_TEST_MODE); SPI_EXCHANGE(g_spi3, tx, NULL, - nitems(CONFIG_STM32F7_SPI_TEST_MESSAGE)); + nitems(CONFIG_STM32_SPI_TEST_MESSAGE)); #endif return OK; diff --git a/boards/arm/stm32f7/nucleo-f722ze/Kconfig b/boards/arm/stm32f7/nucleo-f722ze/Kconfig index 60ec42530ca..884622e3a10 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/Kconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F722ZE_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F722ZE_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F722ZE_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F722ZE_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig index 59f5aaad34e..1cb4871af1a 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/can/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -46,12 +47,12 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig index c03ccde370c..59a299a0093 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/cansock/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN_SOCKET=y -CONFIG_STM32F7_CAN_TSEG1=15 -CONFIG_STM32F7_CAN_TSEG2=2 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN_SOCKET=y +CONFIG_STM32_CAN_TSEG1=15 +CONFIG_STM32_CAN_TSEG2=2 +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig index f856c740564..c5ade09840d 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -70,10 +71,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig index 2e7c9a4dabd..d1dd0b02677 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f722ze/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f722ze" CONFIG_ARCH_BOARD_NUCLEO_F722ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F722ZE=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -42,9 +43,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt index f8b17eb732e..030ab2e9850 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f722ze/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs index 084c954afc3..d39777f15f4 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f722ze/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h index 1db1e63552c..4b4039a3e9b 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h +++ b/boards/arm/stm32f7/nucleo-f722ze/src/nucleo-f722ze.h @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -263,7 +263,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -295,7 +295,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c index 96deea3ee98..6f66e59090f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c index 04b76397fdf..2ed57dfe5f3 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c index 82194ab10bf..16862f9ada7 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c index 7c848385d0c..6339b20c21f 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c index 2ab163679c5..20272a1dac8 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c index 1adc20c2cae..8614a43c515 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c index c38a390ca09..26f3bf756fd 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c index 57a304d3a3e..1a4e5d2f19e 100644 --- a/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f722ze/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f722ze.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f746zg/Kconfig b/boards/arm/stm32f7/nucleo-f746zg/Kconfig index c1d96afcf0b..d59a47ec85b 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/Kconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F746ZG_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F746ZG_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F746ZG_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F746ZG_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig index d32e6ac0e4c..95125cef760 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -52,9 +53,9 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig index 0112b71b52d..0997aceb7ed 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/note/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -95,46 +96,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NOTE=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig index ae9b97ca15c..c1b3531bf8a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f746zg" CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,10 +44,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_DTCMEXCLUDE=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig index 291c438c26c..fe194da3baf 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig +++ b/boards/arm/stm32f7/nucleo-f746zg/configs/pysim/defconfig @@ -6,7 +6,7 @@ # modifications. # # CONFIG_NDEBUG is not set -# CONFIG_STM32F7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ADC=y CONFIG_ADC_FIFOSIZE=16 CONFIG_ANALOG=y @@ -16,6 +16,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F746ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746ZG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_RAMVECTORS=y @@ -91,46 +92,46 @@ CONFIG_SPI=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32F7_ADC1_TIMTRIG=1 -CONFIG_STM32F7_CAN1=y -CONFIG_STM32F7_CAN1_BAUD=500000 -CONFIG_STM32F7_CAN_TSEG1=5 -CONFIG_STM32F7_CAN_TSEG2=6 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PWM_MULTICHAN=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_TIM1=y -CONFIG_STM32F7_TIM1_CH1NOUT=y -CONFIG_STM32F7_TIM1_CH1OUT=y -CONFIG_STM32F7_TIM1_CH2NOUT=y -CONFIG_STM32F7_TIM1_CH2OUT=y -CONFIG_STM32F7_TIM1_CHANNEL1=y -CONFIG_STM32F7_TIM1_CHANNEL2=y -CONFIG_STM32F7_TIM1_DEADTIME=10 -CONFIG_STM32F7_TIM1_PWM=y -CONFIG_STM32F7_TIM2=y -CONFIG_STM32F7_TIM2_ADC=y -CONFIG_STM32F7_TIM3=y -CONFIG_STM32F7_TIM3_QE=y -CONFIG_STM32F7_TIM4=y -CONFIG_STM32F7_TIM4_QE=y -CONFIG_STM32F7_TIM8=y -CONFIG_STM32F7_TIM8_QE=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_CAN1=y +CONFIG_STM32_CAN1_BAUD=500000 +CONFIG_STM32_CAN_TSEG1=5 +CONFIG_STM32_CAN_TSEG2=6 +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_DEADTIME=10 +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_QE=y +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_QE=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt index 73a308ecf1c..1c42f137288 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f746zg/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs index 92eaf789e58..78a75d54df0 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f746zg/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h index a71f98a2c34..2a1c8d883b7 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h +++ b/boards/arm/stm32f7/nucleo-f746zg/src/nucleo-f746zg.h @@ -100,7 +100,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -111,7 +111,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -153,9 +153,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -179,11 +179,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -276,7 +276,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -308,7 +308,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c index 7f79bebc84d..c1f68f20083 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c index 7834ac832df..ab415b60f99 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c index adab9af41bb..da3915eacc6 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c index 39d379e5c8d..f7cc0a58d81 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -97,14 +97,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -139,7 +139,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -152,7 +152,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -188,7 +188,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -200,7 +200,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -212,7 +212,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -224,7 +224,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -238,7 +238,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -247,7 +247,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -255,7 +255,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c index bb3c0cfae36..983a1bddb56 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c index a2de94884cc..8100783be19 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c index ee391eb04ad..417e00c2ae1 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c index 1e3c23c0ad7..fe457155c2a 100644 --- a/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f746zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f746zg.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/nucleo-f767zi/Kconfig b/boards/arm/stm32f7/nucleo-f767zi/Kconfig index e8eb80d5fab..e01d882951f 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/Kconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/Kconfig @@ -57,22 +57,22 @@ choice config NUCLEO_F767ZI_CONSOLE_ARDUINO bool "Arduino Connector" - select STM32F7_USART6 + select STM32_USART6 select USART6_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_VIRTUAL bool "Virtual Comport" - select STM32F7_USART3 + select STM32_USART3 select USART3_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO bool "Morpho Connector" - select STM32F7_UART8 + select STM32_UART8 select UART8_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_MORPHO_UART4 bool "Morpho Connector UART4" - select STM32F7_UART4 + select STM32_UART4 select UART4_SERIALDRIVER config NUCLEO_F767ZI_CONSOLE_NONE @@ -83,7 +83,7 @@ endchoice # "Select Console wiring" choice prompt "CAN1 pins selection" default NUCLEO_F767ZI_CAN1_MAP_PD0PD1 - depends on STM32F7_CAN1 + depends on STM32_CAN1 config NUCLEO_F767ZI_CAN1_MAP_D14D15 bool "CAN1_TX=D14 CAN1_RX=D15" diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig index 3baad155b05..93030ce7258 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/evalos/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -55,10 +56,10 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_SERIALBRK_BSDCOMPAT=y -CONFIG_STM32F7_SERIAL_DISABLE_REORDERING=y -CONFIG_STM32F7_USART_BREAKS=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_SERIALBRK_BSDCOMPAT=y +CONFIG_STM32_SERIAL_DISABLE_REORDERING=y +CONFIG_STM32_USART_BREAKS=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig index 6ddfdc06852..240cfc4a2e9 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,15 +63,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=30 CONFIG_START_MONTH=11 CONFIG_START_YEAR=2015 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig index bc43b47e6f8..c78a21c59fa 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig +++ b/boards/arm/stm32f7/nucleo-f767zi/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f767zi" CONFIG_ARCH_BOARD_NUCLEO_F767ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt index 28d7f560bef..b9e35dee705 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt +++ b/boards/arm/stm32f7/nucleo-f767zi/src/CMakeLists.txt @@ -52,11 +52,11 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs index b4c24d64fec..77197f80a79 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs +++ b/boards/arm/stm32f7/nucleo-f767zi/src/Make.defs @@ -54,11 +54,11 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CSRCS += stm32_bbsram.c endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h index 60c9ab458c9..2816cc143d2 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h +++ b/boards/arm/stm32f7/nucleo-f767zi/src/nucleo-f767zi.h @@ -126,7 +126,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -137,7 +137,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32F7_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -179,9 +179,9 @@ /* GPIO pins used by the GPIO Subsystem */ #define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ -#if defined(CONFIG_STM32F7_TIM1_CH1NOUT) && defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) && defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ -#elif defined(CONFIG_STM32F7_TIM1_CH1NOUT) || defined (CONFIG_STM32F7_TIM1_CH2NOUT) +#elif defined(CONFIG_STM32_TIM1_CH1NOUT) || defined (CONFIG_STM32_TIM1_CH2NOUT) #define BOARD_NGPIOOUT 9 /* Amount of GPIO Output pins */ #else #define BOARD_NGPIOOUT 10 /* Amount of GPIO Output pins */ @@ -205,11 +205,11 @@ GPIO_OUTPUT_SET | GPIO_PORTA |GPIO_PIN5) #define GPIO_OUT5 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN12) -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) #define GPIO_OUT6 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN8) #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) #define GPIO_OUT7 (GPIO_OUTPUT | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN10) #endif @@ -301,7 +301,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -333,7 +333,7 @@ int stm32_adc_setup(void); * Name: stm32_bbsram_int ****************************************************************************/ -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM int stm32_bbsram_int(void); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c index bf7d56c0c6b..7c871a67cd2 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_adc.c @@ -49,19 +49,19 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32F7_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32F7_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32F7_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32F7_ADC1) || defined(CONFIG_STM32F7_ADC2) || defined(CONFIG_STM32F7_ADC3) -#ifndef CONFIG_STM32F7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -79,7 +79,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist[ADC1_NCHANNELS] = { 3, 4, 10, 13 @@ -118,7 +118,7 @@ static const uint32_t g_pinlist[ADC1_NCHANNELS] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC1 +#ifdef CONFIG_STM32_ADC1 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -167,5 +167,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32F7_ADC1 || CONFIG_STM32F7_ADC2 || CONFIG_STM32F7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c index 31431f9d53d..f443aaca0aa 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bbsram.c @@ -47,7 +47,7 @@ #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions @@ -306,7 +306,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) * Name: copy_reverse ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) { while (size--) @@ -314,7 +314,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) *dest++ = *src--; } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ /**************************************************************************** * Public Functions @@ -326,7 +326,7 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) int stm32_bbsram_int(void) { - int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + int filesizes[CONFIG_STM32_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; char buf[HEADER_TIME_FMT_LEN + 1]; struct bbsramd_s desc; int rv; @@ -338,7 +338,7 @@ int stm32_bbsram_int(void) stm32_bbsraminitialize(BBSRAM_PATH, filesizes); -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) /* Panic Logging in Battery Backed Up Files */ /* Do we have an hard fault in BBSRAM? */ @@ -369,7 +369,7 @@ int stm32_bbsram_int(void) " [%s] (%d)\n", HARDFAULT_PATH, rv); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ return rv; } @@ -378,7 +378,7 @@ int stm32_bbsram_int(void) * Name: board_crashdump ****************************************************************************/ -#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) void board_crashdump(uintptr_t sp, struct tcb_s *tcb, const char *filename, int lineno, const char *msg, void *regs) @@ -518,6 +518,6 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, arm_lowputc('!'); } } -#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ +#endif /* CONFIG_STM32_SAVE_CRASHDUMP */ #endif /* CONFIG_STM32_BBSRAM */ diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c index c6bf11bbf24..b1bdae2f12b 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_boot.c @@ -57,7 +57,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c index 4213f82a5a2..8f705ee31e1 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_bringup.c @@ -40,19 +40,19 @@ #include "stm32_i2c.h" -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER # include "stm32_can_setup.h" #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET # include "stm32_cansock_setup.h" #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS # include "stm32_romfs.h" #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST # include "stm32_spitest.h" #endif @@ -112,14 +112,14 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_ROMFS +#ifdef CONFIG_STM32_ROMFS /* Mount the romfs partition */ ret = stm32_romfs_initialize(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_STM32F7_ROMFS_MOUNTPOINT, ret); + CONFIG_STM32_ROMFS_MOUNTPOINT, ret); } #endif @@ -154,7 +154,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /* Initialize battery-backed RAM */ stm32_bbsram_int(); @@ -167,7 +167,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_SPI_TEST +#ifdef CONFIG_STM32_SPI_TEST /* Create SPI interfaces */ ret = stm32_spidev_bus_test(); @@ -203,7 +203,7 @@ int stm32_bringup(void) #ifdef CONFIG_SENSORS_QENCODER char buf[9]; -#ifdef CONFIG_STM32F7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe0"); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -215,7 +215,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe2"); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -227,7 +227,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe3"); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -239,7 +239,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe4"); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) @@ -253,7 +253,7 @@ int stm32_bringup(void) #endif -#ifdef CONFIG_STM32F7_CAN_CHARDRIVER +#ifdef CONFIG_STM32_CAN_CHARDRIVER ret = stm32_can_setup(); if (ret < 0) { @@ -262,7 +262,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_CAN_SOCKET +#ifdef CONFIG_STM32_CAN_SOCKET ret = stm32_cansock_setup(); if (ret < 0) { @@ -270,7 +270,7 @@ int stm32_bringup(void) } #endif -#if defined(CONFIG_I2C) && defined(CONFIG_STM32F7_I2C1) +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) i2c_bus = 1; i2c = stm32_i2cbus_initialize(i2c_bus); if (i2c == NULL) diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c index 9ddb4938292..b6619c43310 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_gpio.c @@ -125,10 +125,10 @@ static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = GPIO_OUT3, GPIO_OUT4, GPIO_OUT5, -#if !defined(CONFIG_STM32F7_TIM1_CH1NOUT) +#if !defined(CONFIG_STM32_TIM1_CH1NOUT) GPIO_OUT6, #endif -#if !defined(CONFIG_STM32F7_TIM1_CH2NOUT) +#if !defined(CONFIG_STM32_TIM1_CH2NOUT) GPIO_OUT7, #endif }; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c index 800b70d45d0..9dbd545ea85 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_pwm.c @@ -73,7 +73,7 @@ int stm32_pwm_setup(void) { /* Call stm32_pwminitialize() to get an instance of the PWM interface */ -#if defined(CONFIG_STM32F7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -89,7 +89,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -121,7 +121,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32F7_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c index 3b19fd2fa66..788b0c1963c 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_spi.c @@ -53,7 +53,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -79,7 +79,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -105,7 +105,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32F7_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -158,7 +158,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -168,7 +168,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32F7_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -206,7 +206,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -248,7 +248,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -269,7 +269,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -283,7 +283,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -297,7 +297,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -335,42 +335,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c index 1e4c86e2623..f153ccd2c64 100644 --- a/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c +++ b/boards/arm/stm32f7/nucleo-f767zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-f767zi.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32f7/steval-eth001v1/Kconfig b/boards/arm/stm32f7/steval-eth001v1/Kconfig index 6d1513de7bc..64f4caa11eb 100644 --- a/boards/arm/stm32f7/steval-eth001v1/Kconfig +++ b/boards/arm/stm32f7/steval-eth001v1/Kconfig @@ -5,12 +5,12 @@ if ARCH_BOARD_STEVAL_ETH001V1 -if STM32F7_FOC +if STM32_FOC config BOARD_STM32F7_STEVALETH001V1_FOC_VBUS bool "STEVAL-ETH001V1 board VBUS sense" default n -endif # STM32F7_FOC +endif # STM32_FOC endif # ARCH_BOARD_STEVAL_ETH001V1 diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig index 89261567704..04b8ea48f2c 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_b16/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig index 2d3229bf10e..244c71c100b 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/foc_f32/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,17 +60,17 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1_ANIOC_TRIGGER=1 -CONFIG_STM32F7_ADC1_DMA=y -CONFIG_STM32F7_ADC1_DMA_CFG=1 -CONFIG_STM32F7_ADC1_INJECTED_CHAN=3 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_FOC=y -CONFIG_STM32F7_FOC_ADC_CCR4=y -CONFIG_STM32F7_FOC_FOC0=y -CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY=y -CONFIG_STM32F7_TIM1_MODE=2 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_ADC1_ANIOC_TRIGGER=1 +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_INJECTED_CHAN=3 +CONFIG_STM32_DMA2=y +CONFIG_STM32_FOC=y +CONFIG_STM32_FOC_ADC_CCR4=y +CONFIG_STM32_FOC_FOC0=y +CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY=y +CONFIG_STM32_TIM1_MODE=2 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig index cf898372ae8..4e4dea5daa4 100644 --- a/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig +++ b/boards/arm/stm32f7/steval-eth001v1/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-eth001v1" CONFIG_ARCH_BOARD_STEVAL_ETH001V1=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F767ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt index 0082f8f9499..fb3a6271dbe 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt +++ b/boards/arm/stm32f7/steval-eth001v1/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32F7_FOC) +if(CONFIG_STM32_FOC) list(APPEND SRCS stm32_foc.c) endif() diff --git a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs index ace68763fc4..6d4a16a40b5 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/Make.defs +++ b/boards/arm/stm32f7/steval-eth001v1/src/Make.defs @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32F7_FOC),y) +ifeq ($(CONFIG_STM32_FOC),y) CSRCS += stm32_foc.c endif diff --git a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h index 22026d5156f..caf25dc1ae0 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h +++ b/boards/arm/stm32f7/steval-eth001v1/src/steval-eth001v1.h @@ -72,7 +72,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC int stm32_foc_setup(void); #endif diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c index 1ef16e93ce0..b69d7f74819 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_bringup.c @@ -65,7 +65,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32F7_FOC +#ifdef CONFIG_STM32_FOC /* Initialize and register the FOC device - must be before ADC setup */ ret = stm32_foc_setup(); diff --git a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c index 9a27e7bc948..93d7ec8bd1e 100644 --- a/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c +++ b/boards/arm/stm32f7/steval-eth001v1/src/stm32_foc.c @@ -54,33 +54,33 @@ * 2. PWM complementary channels must have positive polarity */ -#ifndef CONFIG_STM32F7_FOC_HAS_PWM_COMPLEMENTARY +#ifndef CONFIG_STM32_FOC_HAS_PWM_COMPLEMENTARY # error #endif -#if CONFIG_STM32F7_TIM1_CH1POL != 0 +#if CONFIG_STM32_TIM1_CH1POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2POL != 0 +#if CONFIG_STM32_TIM1_CH2POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3POL != 0 +#if CONFIG_STM32_TIM1_CH3POL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH1NPOL != 0 +#if CONFIG_STM32_TIM1_CH1NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH2NPOL != 0 +#if CONFIG_STM32_TIM1_CH2NPOL != 0 # error #endif -#if CONFIG_STM32F7_TIM1_CH3NPOL != 0 +#if CONFIG_STM32_TIM1_CH3NPOL != 0 # error #endif /* Aux ADC needs DMA enabled */ #ifdef CONFIG_ADC -# ifndef CONFIG_STM32F7_ADC1_DMA +# ifndef CONFIG_STM32_ADC1_DMA # error # endif #endif @@ -122,7 +122,7 @@ #define ADC1_INJECTED (CONFIG_MOTOR_FOC_SHUNTS) -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS # define STEVALETH001V1_FOC_VBUS 1 #else # define STEVALETH001V1_FOC_VBUS 0 @@ -133,11 +133,11 @@ /* Check ADC1 configuration */ -#if ADC1_INJECTED != CONFIG_STM32F7_ADC1_INJECTED_CHAN +#if ADC1_INJECTED != CONFIG_STM32_ADC1_INJECTED_CHAN # error #endif -#if CONFIG_STM32F7_ADC1_RESOLUTION != 0 +#if CONFIG_STM32_ADC1_RESOLUTION != 0 # error #endif @@ -186,7 +186,7 @@ static void board_foc_trace(struct foc_dev_s *dev, int type, bool state); static uint8_t g_adc1_chan[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS 14, /* ADC1 REG - VBUS */ #endif 15, /* ADC1 INJ1 - PHASE 1 */ @@ -196,7 +196,7 @@ static uint8_t g_adc1_chan[] = static uint32_t g_adc1_pins[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS GPIO_ADC1_IN14, #endif GPIO_ADC1_IN15, @@ -208,7 +208,7 @@ static uint32_t g_adc1_pins[] = static adc_channel_t g_adc1_stime[] = { -#ifdef CONFIG_BOARD_STM32F7_STEVALETH001V1_FOC_VBUS +#ifdef CONFIG_BOARD_STM32_STEVALETH001V1_FOC_VBUS { .channel = 14, .sample_time = VBUS_SAMPLE_TIME diff --git a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig index 378ee084c7f..30bf96e0d37 100644 --- a/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746-ws/configs/nsh/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746-ws" CONFIG_ARCH_BOARD_STM32F746_WS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746IG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_INTERRUPTSTACK=2600 @@ -75,15 +76,15 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_ADC1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_DMACAPABLE=y -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_SDMMC1=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_SPI1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_DMACAPABLE=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt index 973faf1d304..00b881c28cf 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746-ws/src/CMakeLists.txt @@ -22,11 +22,11 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_dma_alloc.c) -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs index 80e52803544..67df23791a9 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746-ws/src/Make.defs @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_dma_alloc.c -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c index eb4801aefb4..16dc06038d0 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_boot.c @@ -86,9 +86,9 @@ static void stm32_i2ctool(void) void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -127,7 +127,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32F7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* Initialize the SDIO block driver */ int ret = OK; diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c index 9d86414318e..17ca34d8bfa 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746-ws.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -195,42 +195,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -238,4 +238,4 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI6 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI6 */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c index b4a9bf9f192..4625864a28b 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32_gpio.h" #include "stm32f746-ws.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -330,4 +330,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h index 80532801ade..bed84b94caf 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32f746-ws.h @@ -108,7 +108,7 @@ void weak_function stm32_spidev_initialize(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC1) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC1) int stm32_sdio_initialize(void); #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/Kconfig b/boards/arm/stm32f7/stm32f746g-disco/Kconfig index f43ffe7e876..15c51d8a03e 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/Kconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/Kconfig @@ -12,7 +12,7 @@ config STM32F746GDISCO_FLASH select MTD_N25QXXX select MTD_SMART select FS_SMARTFS - select STM32F7_QSPI + select STM32_QSPI select MTD_BYTE_WRITE ---help--- Configures an MTD device for use with the onboard flash diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig index 0205e65dc25..59a85748ed6 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/audio/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -59,13 +60,13 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_SAI2=y -CONFIG_STM32F7_SAI2_A=y -CONFIG_STM32F7_SAI2_B=y -CONFIG_STM32F7_SAI2_B_SYNC_WITH_A=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_SAI2=y +CONFIG_STM32_SAI2_A=y +CONFIG_STM32_SAI2_B=y +CONFIG_STM32_SAI2_B_SYNC_WITH_A=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_CHAR=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig index 1a6201d978f..f437e6b8e71 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/fb/defconfig @@ -8,13 +8,14 @@ # CONFIG_ARCH_FPU is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,11 +49,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index cb454fadbe6..4783972604f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -9,13 +9,14 @@ # CONFIG_LV_BUILD_EXAMPLES is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,13 +62,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STM32F746GDISCO_TOUCHSCREEN_SWAPXY=y -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_I2C3=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig index a72895966d0..ea305fd8164 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -61,16 +62,16 @@ CONFIG_RR_INTERVAL=20 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig index b7d6e8247b1..870f454c806 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig index bef22e03840..3ac4ed78996 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxdemo/defconfig @@ -9,13 +9,14 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,11 +58,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig index b1d0a835575..59395d2b919 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/nxterm/defconfig @@ -10,13 +10,14 @@ # CONFIG_NSH_DISABLE_PS is not set # CONFIG_NXFONTS_DISABLE_16BPP is not set # CONFIG_NX_DISABLE_16BPP is not set -# CONFIG_STM32F7_FB_CMAP is not set -# CONFIG_STM32F7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f746g-disco" CONFIG_ARCH_BOARD_STM32F746G_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F746NG=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -50,11 +51,11 @@ CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_LTDC=y -CONFIG_STM32F7_LTDC_FB_BASE=0xc0000000 -CONFIG_STM32F7_LTDC_FB_SIZE=261120 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xc0000000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index 0cd3f2c5624..35a9e14961f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -90,7 +90,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* Highest SYSCLK with USB OTG FS clock = 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_RNG) /* Highest SYSCLK with USB OTG FS clock <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz @@ -528,7 +528,7 @@ /* SAI2 pinset */ -#if defined(CONFIG_STM32F7_SAI2) && defined(CONFIG_STM32F7_SAI2_A) +#if defined(CONFIG_STM32_SAI2) && defined(CONFIG_STM32_SAI2_A) # define GPIO_SAI2_SD_A (GPIO_SAI2_SD_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_FS_A (GPIO_SAI2_FS_A_2|GPIO_SPEED_100MHz) # define GPIO_SAI2_SCK_A (GPIO_SAI2_SCK_A_2|GPIO_SPEED_100MHz) diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt index fa3921f051c..3b1baaf5cb3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() @@ -56,13 +56,13 @@ if(CONFIG_MTD_N25QXXX) list(APPEND SRCS stm32_n25q.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32F7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs index ddc33cdca5b..bfa456fb8a5 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f746g-disco/src/Make.defs @@ -42,11 +42,11 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif @@ -58,13 +58,13 @@ ifeq ($(CONFIG_MTD_N25QXXX),y) CSRCS += stm32_n25q.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32F7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c index db7cfae7827..374703bb0cb 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_adc.c @@ -36,11 +36,11 @@ #include "stm32_gpio.h" #include "stm32_adc.h" -#ifndef CONFIG_STM32F7_ADC3 +#ifndef CONFIG_STM32_ADC3 # error "Only ADC3 channels are available on the arduino header of the board" #endif -#if defined(CONFIG_ADC) && defined(CONFIG_STM32F7_ADC3) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -104,7 +104,7 @@ static const uint32_t g_pinlist[6] = int stm32_adc_setup(void) { -#ifdef CONFIG_STM32F7_ADC3 +#ifdef CONFIG_STM32_ADC3 static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -150,4 +150,4 @@ int stm32_adc_setup(void) #endif } -#endif /* (CONFIG_ADC) && (CONFIG_STM32F7_ADC3) */ +#endif /* (CONFIG_ADC) && (CONFIG_STM32_ADC3) */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c index 3992542c13f..32938e7d4c3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. @@ -81,13 +81,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32F7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_enablefmc(); #endif } diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c index 666181b3eb8..bd6e034d810 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_extmem.c @@ -57,7 +57,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c index cef610f4c3d..c353723e5d0 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_lcd.c @@ -40,7 +40,7 @@ #include "stm32_gpio.h" #include "stm32_ltdc.h" -#ifdef CONFIG_STM32F7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c index 66c889a5c92..9ebe6730adc 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f746g-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c index cb7c130d8cb..627dd0b399a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32F7_I2C3 -# error "FT5x06 support requires CONFIG_STM32F7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c index 8d556b459ec..7df40f874e3 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f746g-disco.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); #ifdef CONFIG_USBHOST @@ -334,4 +334,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h index 1bbf837dd78..fec4ada12bd 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h +++ b/boards/arm/stm32f7/stm32f746g-disco/src/stm32f746g-disco.h @@ -43,7 +43,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32F7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -84,7 +84,7 @@ # endif #endif -#ifdef CONFIG_STM32F7_SDMMC +#ifdef CONFIG_STM32_SDMMC #define HAVE_SDIO #else #undef HAVE_SDIO @@ -212,7 +212,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_enablefmc(void); #endif @@ -224,7 +224,7 @@ void stm32_enablefmc(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_disablefmc(void); #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig index 74e1fa7b568..a6feb52f19f 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/netnsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -57,25 +58,25 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_BKPSRAM=y -CONFIG_STM32F7_CEC=y -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_ETHMAC=y -CONFIG_STM32F7_I2C4=y -CONFIG_STM32F7_PHYADDR=0 -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_100FD=0x18 -CONFIG_STM32F7_PHYSR_100HD=0x8 -CONFIG_STM32F7_PHYSR_10FD=0x14 -CONFIG_STM32F7_PHYSR_10HD=0x4 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x1C -CONFIG_STM32F7_RNG=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y -CONFIG_STM32F7_USART6=y +CONFIG_STM32_BKPSRAM=y +CONFIG_STM32_CEC=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PHYADDR=0 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x18 +CONFIG_STM32_PHYSR_100HD=0x8 +CONFIG_STM32_PHYSR_10FD=0x14 +CONFIG_STM32_PHYSR_10HD=0x4 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x1C +CONFIG_STM32_RNG=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig index 0f40ae30525..df8d9cd8a84 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f769i-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32f769i-disco" CONFIG_ARCH_BOARD_STM32F769I_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F769NI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,7 +39,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f769i-disco/include/board.h b/boards/arm/stm32f7/stm32f769i-disco/include/board.h index 028b29b0023..ad56c12a473 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f769i-disco/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt index b41627ab518..1c726649844 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f769i-disco/src/CMakeLists.txt @@ -40,7 +40,7 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs index 82a79440d22..dacf581a7a2 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs +++ b/boards/arm/stm32f7/stm32f769i-disco/src/Make.defs @@ -42,7 +42,7 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c index 1ba49ec977e..42880e2706d 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_boot.c @@ -59,9 +59,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -87,7 +87,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c index f0c45df93e3..a74c94d43f0 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_extmem.c @@ -43,7 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c index 4f36938bb58..ef0f7aef17d 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f769i-disco.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -181,35 +181,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -217,4 +217,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h index 5c2ad841e97..5daf2597d97 100644 --- a/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h +++ b/boards/arm/stm32f7/stm32f769i-disco/src/stm32f769i-disco.h @@ -158,7 +158,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig index cf9cf1cb87d..104b3eec356 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/dualcdcacm/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -45,8 +46,8 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig index 23b69992c3e..5be0771023d 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/f7corecomp/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -62,14 +63,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_SDMMC2_SDIO_MODE=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_DMA2=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_SDMMC2=y -CONFIG_STM32F7_SDMMC_DMA=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_SDMMC2=y +CONFIG_STM32_SDMMC_DMA=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig index bd8641a4643..62cd75915ad 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -88,14 +89,14 @@ CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_DMA1=y -CONFIG_STM32F7_I2S2=y -CONFIG_STM32F7_I2S2_MCK=y -CONFIG_STM32F7_I2S2_TX=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_QSPI_POLLING=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2S2=y +CONFIG_STM32_I2S2_MCK=y +CONFIG_STM32_I2S2_TX=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_POLLING=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_DEFAULT=y CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" CONFIG_SYSLOG_MAX_CHANNELS=2 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig index 8f9a71be404..b5f1c6d5b17 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/meadow_os/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -48,8 +49,8 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 CONFIG_USBDEV=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig index b63aa4ec89f..290478e8ab3 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/nsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -36,7 +37,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig index 9df11e1e0fc..70331b5896e 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/projectlab/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -64,10 +65,10 @@ CONFIG_SENSORS_BMI270=y CONFIG_SENSORS_BMI270_I2C=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_I2C1=y -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig index 26e856613c8..aac213c9285 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -38,9 +39,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_EXTERNAL_RAM=y -CONFIG_STM32F7_FMC=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_EXTERNAL_RAM=y +CONFIG_STM32_FMC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig index 1b453b93181..e06beff8f4c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/usbnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH_BOARD="stm32f777zit6-meadow" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F777ZI=y CONFIG_ARCH_CHIP_STM32F7=y CONFIG_ARCH_STACKDUMP=y @@ -54,9 +55,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y CONFIG_START_DAY=14 -CONFIG_STM32F7_OTGFS=y -CONFIG_STM32F7_QSPI=y -CONFIG_STM32F7_USART1=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_FLASH_ERASEALL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=64 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 2b1cfc1a9f9..29719bff24c 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -88,7 +88,7 @@ * 2 <= PLLQ <= 15 */ -#if defined(CONFIG_STM32F7_OTGFS) +#if defined(CONFIG_STM32_OTGFS) /* USB OTG FS clock (= SDMMCCLK = RNGCLK) must be 48 MHz * * PLL_VCO = (25,000,000 / 25) * 384 = 384 MHz @@ -107,7 +107,7 @@ #define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2) #define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 8) -#elif defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) || defined(CONFIG_STM32F7_RNG) +#elif defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) || defined(CONFIG_STM32_RNG) /* SDMMCCLK (= USB OTG FS clock = RNGCLK) should be <= 48MHz * * PLL_VCO = (25,000,000 / 25) * 432 = 432 MHz diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt index a22e8a9afed..a1c6ad74cb7 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt @@ -44,13 +44,13 @@ if(CONFIG_SPORADIC_INSTRUMENTATION) list(APPEND SRCS stm32_sporadic.c) endif() -if(CONFIG_STM32F7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_extmem.c) endif() -if(CONFIG_STM32F7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) -elseif(CONFIG_STM32F7_OTGFSHS) +elseif(CONFIG_STM32_OTGFSHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs index 8d6ef41b3a6..8b662918a3f 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/Make.defs @@ -47,13 +47,13 @@ ifeq ($(CONFIG_SPORADIC_INSTRUMENTATION),y) CSRCS += stm32_sporadic.c endif -ifeq ($(CONFIG_STM32F7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CSRCS += stm32_extmem.c endif -ifeq ($(CONFIG_STM32F7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c -else ifeq ($(CONFIG_STM32F7_OTGFSHS),y) +else ifeq ($(CONFIG_STM32_OTGFSHS),y) CSRCS += stm32_usb.c endif @@ -65,7 +65,7 @@ ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32F7_SDMMC2),y) +ifeq ($(CONFIG_STM32_SDMMC2),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c index adae2fb2067..bbf5cd536c1 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_boot.c @@ -36,7 +36,7 @@ #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI # include "stm32_qspi.h" # ifdef CONFIG_FS_FAT @@ -74,9 +74,9 @@ extern struct qspi_dev_s *stm32_qspi_initialize(int intf); void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ @@ -102,7 +102,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC stm32_sdram_initialize(); #endif } @@ -124,7 +124,7 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#ifdef CONFIG_STM32F7_QSPI +#ifdef CONFIG_STM32_QSPI struct qspi_dev_s *qspi; struct mtd_dev_s *mtd; diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c index 25d4604116b..e2a62c396a9 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_extmem.c @@ -43,7 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32F7_FMC +#ifndef CONFIG_STM32_FMC # warning "FMC is not enabled" #endif diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c index fec4e8256a6..0d4fb153ceb 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_spi.c @@ -40,9 +40,9 @@ #include "stm32f777zit6-meadow.h" -#if defined(CONFIG_STM32F7_SPI1) || defined(CONFIG_STM32F7_SPI2) || \ - defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \ - defined(CONFIG_STM32F7_SPI5) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) /**************************************************************************** * Public Functions @@ -87,7 +87,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -101,7 +101,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -117,7 +117,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -131,7 +131,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -145,7 +145,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -183,35 +183,35 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32F7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32F7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -219,4 +219,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32F7_SPI1 || ... CONFIG_STM32F7_SPI5 */ +#endif /* CONFIG_STM32_SPI1 || ... CONFIG_STM32_SPI5 */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c index 49a5b7310f7..be5332f7f44 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c @@ -46,7 +46,7 @@ #include "stm32_gpio.h" #include "stm32f777zit6-meadow.h" -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -55,7 +55,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -139,7 +139,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32F7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); # ifdef CONFIG_USBHOST stm32_configgpio(GPIO_OTGFS_PWRON); @@ -339,4 +339,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h index 827959faa57..6fd24bd22f0 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32f777zit6-meadow.h @@ -47,7 +47,7 @@ /* SDCard validation */ -#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -165,7 +165,7 @@ void arch_sporadic_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32F7_FMC +#ifdef CONFIG_STM32_FMC void stm32_sdram_initialize(void); void stm32_disablefmc(void); #endif @@ -178,7 +178,7 @@ void stm32_disablefmc(void); * ****************************************************************************/ -#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32F7_SDMMC2) +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDMMC2) int stm32_sdio_initialize(void); #endif From ed0c96334cabc900f2176c0d2e71f4f280445641 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:38 +0200 Subject: [PATCH 087/268] !arch/stm32h5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32H5 Kconfig symbols were renamed from CONFIG_STM32H5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32h5/boards/nucleo-h563zi/index.rst | 8 +- Documentation/platforms/arm/stm32h5/index.rst | 2 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32h5/chip.h | 10 +- arch/arm/include/stm32h5/irq.h | 2 +- arch/arm/include/stm32h5/stm32h5xx_irq.h | 18 +- arch/arm/src/stm32h5/CMakeLists.txt | 34 +- arch/arm/src/stm32h5/Kconfig | 6238 +---------------- arch/arm/src/stm32h5/Make.defs | 36 +- .../arm/src/stm32h5/hardware/stm32_ethernet.h | 4 +- arch/arm/src/stm32h5/hardware/stm32_flash.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_gpdma.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_gpio.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_i2c.h | 2 +- .../src/stm32h5/hardware/stm32_memorymap.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_pinmap.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_pwr.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_rcc.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_sbs.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_uart.h | 2 +- arch/arm/src/stm32h5/hardware/stm32_usbfs.h | 4 +- .../src/stm32h5/hardware/stm32h56xxx_pinmap.h | 4 +- .../src/stm32h5/hardware/stm32h5xxx_flash.h | 14 +- .../arm/src/stm32h5/hardware/stm32h5xxx_rcc.h | 2 +- .../arm/src/stm32h5/hardware/stm32h5xxx_spi.h | 2 +- arch/arm/src/stm32h5/stm32_adc.c | 99 +- arch/arm/src/stm32h5/stm32_adc.h | 448 +- arch/arm/src/stm32h5/stm32_dbgmcu.h | 2 +- arch/arm/src/stm32h5/stm32_dma.c | 6 +- arch/arm/src/stm32h5/stm32_dma.h | 8 +- arch/arm/src/stm32h5/stm32_dts.c | 30 +- arch/arm/src/stm32h5/stm32_ethernet.c | 270 +- arch/arm/src/stm32h5/stm32_ethernet.h | 4 +- arch/arm/src/stm32h5/stm32_fdcan.c | 130 +- arch/arm/src/stm32h5/stm32_fdcan.h | 4 +- arch/arm/src/stm32h5/stm32_flash.c | 2 +- arch/arm/src/stm32h5/stm32_gpio.h | 2 +- arch/arm/src/stm32h5/stm32_hsi48.c | 4 +- arch/arm/src/stm32h5/stm32_hsi48.h | 4 +- arch/arm/src/stm32h5/stm32_i2c.c | 196 +- arch/arm/src/stm32h5/stm32_i2c.h | 8 +- arch/arm/src/stm32h5/stm32_icache.c | 70 +- arch/arm/src/stm32h5/stm32_idle.c | 2 +- arch/arm/src/stm32h5/stm32_lse.c | 20 +- arch/arm/src/stm32h5/stm32_pulsecount.c | 92 +- arch/arm/src/stm32h5/stm32_pwm.c | 614 +- arch/arm/src/stm32h5/stm32_pwm.h | 522 +- arch/arm/src/stm32h5/stm32_qspi.c | 108 +- arch/arm/src/stm32h5/stm32_qspi.h | 4 +- arch/arm/src/stm32h5/stm32_rcc.c | 18 +- arch/arm/src/stm32h5/stm32_rcc.h | 10 +- arch/arm/src/stm32h5/stm32_serial.c | 116 +- arch/arm/src/stm32h5/stm32_spi.c | 184 +- arch/arm/src/stm32h5/stm32_spi.h | 24 +- arch/arm/src/stm32h5/stm32_start.c | 4 +- arch/arm/src/stm32h5/stm32_tim.c | 284 +- arch/arm/src/stm32h5/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32h5/stm32_uart.h | 182 +- arch/arm/src/stm32h5/stm32_usbdrdhost.c | 18 +- arch/arm/src/stm32h5/stm32_usbdrdhost.h | 12 +- arch/arm/src/stm32h5/stm32_usbfs.c | 16 +- arch/arm/src/stm32h5/stm32h563xx_flash.c | 48 +- arch/arm/src/stm32h5/stm32h5xx_rcc.c | 128 +- boards/arm/stm32h5/nucleo-h563zi/Kconfig | 2 +- .../nucleo-h563zi/configs/adc/defconfig | 5 +- .../configs/adc_watchdog/defconfig | 15 +- .../nucleo-h563zi/configs/dts/defconfig | 7 +- .../nucleo-h563zi/configs/fdcan1/defconfig | 9 +- .../nucleo-h563zi/configs/nsh/defconfig | 3 +- .../nucleo-h563zi/configs/nshusbnet/defconfig | 7 +- .../nucleo-h563zi/configs/pwm/defconfig | 9 +- .../nucleo-h563zi/configs/usbmsc/defconfig | 7 +- .../nucleo-h563zi/configs/usbnsh/defconfig | 5 +- .../arm/stm32h5/nucleo-h563zi/include/board.h | 16 +- .../stm32h5/nucleo-h563zi/src/CMakeLists.txt | 6 +- boards/arm/stm32h5/nucleo-h563zi/src/Makefile | 8 +- .../stm32h5/nucleo-h563zi/src/nucleo-h563zi.h | 4 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_adc.c | 14 +- .../stm32h5/nucleo-h563zi/src/stm32_bringup.c | 8 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_can.c | 2 +- .../nucleo-h563zi/src/stm32_clockconfig.c | 4 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_dts.c | 2 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c | 4 +- .../arm/stm32h5/nucleo-h563zi/src/stm32_usb.c | 4 +- 84 files changed, 2117 insertions(+), 8186 deletions(-) diff --git a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst index b6e324ef32c..0ff9e56e127 100644 --- a/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst +++ b/Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst @@ -182,7 +182,7 @@ This configuration enables USB Host support with the Mass Storage Class USB mass-storage device (e.g. a USB flash drive) to the board's USB-C connector. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_MSC`` — USB Mass Storage Class host driver - ``CONFIG_USBHOST_HUB`` — USB hub support - ``CONFIG_FS_FAT`` — FAT filesystem for mounting the storage device @@ -196,7 +196,7 @@ configured in this build. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** @@ -214,7 +214,7 @@ full networking support and the CDC-ECM USB Ethernet host driver. It is intended to test USB Host operation with a USB-to-Ethernet adapter that uses the CDC-ECM (Ethernet Control Model) protocol. Key options enabled: -- ``CONFIG_STM32H5_USBFS_HOST`` — STM32H5 USB full-speed host controller +- ``CONFIG_STM32_USBFS_HOST`` — STM32H5 USB full-speed host controller - ``CONFIG_USBHOST_CDCECM`` — USB CDC-ECM Ethernet host driver - ``CONFIG_USBHOST_COMPOSITE`` — composite USB device support - ``CONFIG_USBHOST_HUB`` — USB hub support @@ -233,7 +233,7 @@ verify network connectivity. USB Host requires a stable 48 MHz clock. HSI48 is not accurate enough for reliable USB operation, so this configuration uses the external high-speed oscillator (HSE) as the USB clock source - (``CONFIG_STM32H5_USE_HSE=y``). On the Nucleo-H563ZI development board + (``CONFIG_STM32_USE_HSE=y``). On the Nucleo-H563ZI development board HSE is not connected by default; to enable it you must: - **Connect** solder bridges **SB3** and **SB4** diff --git a/Documentation/platforms/arm/stm32h5/index.rst b/Documentation/platforms/arm/stm32h5/index.rst index 882a75ea5e4..fb49d8558da 100644 --- a/Documentation/platforms/arm/stm32h5/index.rst +++ b/Documentation/platforms/arm/stm32h5/index.rst @@ -95,7 +95,7 @@ capable of operating as a device or host. Pre-requisites: - CONFIG_USBHOST - Enable USB host support -- CONFIG_STM32H5_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode +- CONFIG_STM32_USBFS_HOST - Enable the STM32 USB OTG FS block in host mode USB host requires a stable 48MHz clock. This should come from a PLL driven by the HSE. HSI48 cannot be reliably used in host mode due to drift. It can only be used in device mode. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2def7a21314..ea411453337 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -669,6 +669,7 @@ config ARCH_CHIP_STM32L4 config ARCH_CHIP_STM32H5 bool "STMicro STM32 H5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP diff --git a/arch/arm/include/stm32h5/chip.h b/arch/arm/include/stm32h5/chip.h index 88906a435a0..e4960644b72 100644 --- a/arch/arm/include/stm32h5/chip.h +++ b/arch/arm/include/stm32h5/chip.h @@ -37,7 +37,7 @@ # define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */ # define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#elif defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ # define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */ @@ -54,7 +54,7 @@ #define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */ #define STM32_NRNG (1) /* Random number generator (RNG) */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */ # define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) @@ -66,7 +66,7 @@ #define STM32_QSPI (0) /* No QuadSPI1 */ #define STM32_OCTOSPI (1) /* OCTOSPI1*/ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_NSPI (6) /* SPI1-SPI6 */ # define STM32_NI2C (4) /* I2C1-4 */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) @@ -80,7 +80,7 @@ #define STM32_NCAN (2) /* CAN1 */ #define STM32_NSAI (2) /* SAI1-2 */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_NSDMMC (2) /* SDMMC interface */ #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) # define STM32_NSDMMC (1) /* SDMMC interface */ @@ -103,7 +103,7 @@ #define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ #define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ -#if defined(CONFIG_STM32H5_HAVE_ETHERNET) +#if defined(CONFIG_STM32_HAVE_ETHERNET) # define STM32_NETHERNET 1 /* Ethernet MAC */ #else # define STM32_NETHERNET 0 /* No Ethernet MAC */ diff --git a/arch/arm/include/stm32h5/irq.h b/arch/arm/include/stm32h5/irq.h index 945ef81a9f2..aec185b9f9e 100644 --- a/arch/arm/include/stm32h5/irq.h +++ b/arch/arm/include/stm32h5/irq.h @@ -66,7 +66,7 @@ #define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/include/stm32h5/stm32h5xx_irq.h b/arch/arm/include/stm32h5/stm32h5xx_irq.h index 6c3746e1fcc..5550c7e5b99 100644 --- a/arch/arm/include/stm32h5/stm32h5xx_irq.h +++ b/arch/arm/include/stm32h5/stm32h5xx_irq.h @@ -119,7 +119,7 @@ # define STM32_IRQ_ADC2 (STM32_IRQ_FIRST + 69) /* 69: ADC2 global interrupt */ # define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 70) /* 70: LPTIM2 global interrupt */ # define STM32_IRQ_TIM15 (STM32_IRQ_FIRST + 71) /* 71: TIM15 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 72) /* 72: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 73) /* 73: TIM17 global interrupt */ #endif @@ -132,12 +132,12 @@ # define STM32_IRQ_I2C3_EV (STM32_IRQ_FIRST + 80) /* 80: I2C3_EV global interrupt */ # define STM32_IRQ_I2C3_ER (STM32_IRQ_FIRST + 81) /* 81: I2C3_ER global interrupt */ # define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 82) /* 82: SPI4 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 83) /* 83: SPI5 global interrupt */ # define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 84) /* 84: SPI6 global interrupt */ #endif # define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 85) /* 85: USART6 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 86) /* 86: USART10 global interrupt */ # define STM32_IRQ_USART11 (STM32_IRQ_FIRST + 87) /* 87: USART11 global interrupt */ # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 88) /* 88: SAI1 global interrupt */ @@ -151,7 +151,7 @@ # define STM32_IRQ_GPDMA2_CH5 (STM32_IRQ_FIRST + 95) /* 95: GPDMA2_CH5 global interrupt */ # define STM32_IRQ_GPDMA2_CH6 (STM32_IRQ_FIRST + 96) /* 96: GPDMA2_CH6 global interrupt */ # define STM32_IRQ_GPDMA2_CH7 (STM32_IRQ_FIRST + 97) /* 97: GPDMA2_CH7 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 98) /* 98: UART7 global interrupt */ # define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 99) /* 99: UART8 global interrupt */ # define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 100) /* 100: UART9 global interrupt */ @@ -161,14 +161,14 @@ # define STM32_IRQ_FPU (STM32_IRQ_FIRST + 103) /* 103: FPU global interrupt */ # define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 104) /* 104: ICACHE global interrupt */ # define STM32_IRQ_DCACHE (STM32_IRQ_FIRST + 105) /* 105: DCACHE global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_ETH (STM32_IRQ_FIRST + 106) /* 106: ETH global interrupt */ # define STM32_IRQ_ETH_WKUP (STM32_IRQ_FIRST + 107) /* 107: ETH_WKUP global interrupt */ #endif # define STM32_IRQ_DCMI_PSSI (STM32_IRQ_FIRST + 108) /* 108: DCMI PSSI global interrupt */ # define STM32_IRQ_FDCAN2_IT0 (STM32_IRQ_FIRST + 109) /* 109: FDCAN2_IT0 global interrupt */ # define STM32_IRQ_FDCAN2_IT1 (STM32_IRQ_FIRST + 110) /* 110: FDCAN2_IT1 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 111) /* 111: CORDIC global interrupt */ # define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 112) /* 112: FMAC global interrupt */ #endif @@ -180,13 +180,13 @@ # define STM32_IRQ_PKA (STM32_IRQ_FIRST + 118) /* 118: PKA global interrupt */ # define STM32_IRQ_CEC (STM32_IRQ_FIRST + 119) /* 119: CEC global interrupt */ # define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 120) /* 120: TIM12 global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 121) /* 121: TIM13 global interrupt */ # define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 122) /* 122: TIM14 global interrupt */ #endif # define STM32_IRQ_I3C1_EV (STM32_IRQ_FIRST + 123) /* 123: I3C1_EV global interrupt */ # define STM32_IRQ_I3C1_ER (STM32_IRQ_FIRST + 124) /* 124: I3C1_ER global interrupt */ -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_I2C4_EV (STM32_IRQ_FIRST + 125) /* 125: I2C4_EV global interrupt */ # define STM32_IRQ_I2C4_ER (STM32_IRQ_FIRST + 126) /* 126: I2C4_ER global interrupt */ # define STM32_IRQ_LPTIM3 (STM32_IRQ_FIRST + 127) /* 127: LPTIM3 global interrupt */ @@ -199,7 +199,7 @@ # define STM32_IRQ_I3C2_ER (STM32_IRQ_FIRST + 132) /* 132: I3C2_ER global interrupt */ #endif -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define STM32_IRQ_NEXTINTS 131 #elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) # define STM32_IRQ_NEXTINTS 133 diff --git a/arch/arm/src/stm32h5/CMakeLists.txt b/arch/arm/src/stm32h5/CMakeLists.txt index 37874fe58c9..854b2189968 100644 --- a/arch/arm/src/stm32h5/CMakeLists.txt +++ b/arch/arm/src/stm32h5/CMakeLists.txt @@ -24,7 +24,7 @@ set(SRCS) # Common ARM and Cortex-M33 files -if(CONFIG_STM32H5_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -44,7 +44,7 @@ list( stm32_lsi.c stm32_uid.c) -if(CONFIG_STM32H5_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() @@ -56,7 +56,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H5_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() @@ -64,55 +64,55 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_FDCAN_CHARDRIVER) +if(CONFIG_STM32_FDCAN_CHARDRIVER) list(APPEND SRCS stm32_fdcan.c) endif() -if(CONFIG_STM32H5_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32_rng.c) endif() -if(CONFIG_STM32H5_ICACHE) +if(CONFIG_STM32_ICACHE) list(APPEND SRCS stm32_icache.c) endif() -if(CONFIG_STM32H5_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H5_QSPI1) +if(CONFIG_STM32_QSPI1) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H5_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H5_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32_hsi48.c) endif() -if(CONFIG_STM32H5_USBFS) +if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32_usbfs.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usbdrdhost.c) endif() -if(CONFIG_STM32H5_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() -if(CONFIG_STM32H5_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -122,7 +122,7 @@ endif() # Required chip type specific files -if(CONFIG_STM32H5_STM32H5XXXX) +if(CONFIG_STM32_STM32H5XXXX) list(APPEND SRCS stm32h5xx_rcc.c) endif() diff --git a/arch/arm/src/stm32h5/Kconfig b/arch/arm/src/stm32h5/Kconfig index 14730b3b84e..cdddeae5840 100644 --- a/arch/arm/src/stm32h5/Kconfig +++ b/arch/arm/src/stm32h5/Kconfig @@ -7,6 +7,28 @@ if ARCH_CHIP_STM32H5 comment "STM32H5 Configuration Options" +config STM32_H5_PERIPHERALS + bool + default y + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_RNG + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_DTS + select STM32_HAVE_QSPI1 + select STM32_HAVE_USBFS_MODE + select STM32_HAVE_USBDRD_HOST + select STM32_HAVE_ADC_H5 + select STM32_HAVE_USART_H5 + select STM32_HAVE_I2C_H5 + choice prompt "STM32 H5 Chip Selection" default ARCH_CHIP_STM32H563ZI @@ -15,11 +37,11 @@ choice config ARCH_CHIP_STM32H563ZI bool "STM32H563ZI" select ARCH_CORTEXM33 - select STM32H5_STM32H5XXXX - select STM32H5_STM32H56XXX - select STM32H5_STM32H563XX - select STM32H5_STM32H5X3XX - select STM32H5_FLASH_CONFIG_I + select STM32_STM32H5XXXX + select STM32_STM32H56XXX + select STM32_STM32H563XX + select STM32_STM32H5X3XX + select STM32_FLASH_CONFIG_I select STM32H5_IO_CONFIG_Z ---help--- STM32 H5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -28,6212 +50,112 @@ endchoice # STM32 H5 Chip Selection # Chip families: -config STM32H5_STM32H5XXXX +config STM32_STM32H5XXXX bool default n select ARCH_HAVE_FPU - select STM32H5_HAVE_ICACHE + select STM32_HAVE_ICACHE -config STM32H5_STM32H56XXX +config STM32_STM32H56XXX bool default n - select STM32H5_HAVE_FDCAN1 - select STM32H5_HAVE_FDCAN2 - select STM32H5_HAVE_LPUART1 - select STM32H5_HAVE_USART1 - select STM32H5_HAVE_USART2 - select STM32H5_HAVE_USART3 - select STM32H5_HAVE_UART4 - select STM32H5_HAVE_UART5 - select STM32H5_HAVE_USART6 - select STM32H5_HAVE_UART7 - select STM32H5_HAVE_UART8 - select STM32H5_HAVE_UART9 - select STM32H5_HAVE_USART10 - select STM32H5_HAVE_USART11 - select STM32H5_HAVE_UART12 - select STM32H5_HAVE_SPI4 - select STM32H5_HAVE_SPI5 - select STM32H5_HAVE_SPI6 - select STM32H5_HAVE_I2C4 - select STM32H5_HAVE_USBFS - select STM32H5_HAVE_HSI48 - select STM32H5_HAVE_ICACHE_REMAP + select STM32_HAVE_CORDIC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_UART9 + select STM32_HAVE_USART10 + select STM32_HAVE_USART11 + select STM32_HAVE_UART12 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2C4 + select STM32_HAVE_USBFS + select STM32_HAVE_HSI48 + select STM32_HAVE_ICACHE_REMAP -config STM32H5_STM32H563XX +config STM32_STM32H563XX # STM32H552 and STM32H562 devices documented in RM0439 bool default n - select STM32H5_HAVE_ETHERNET - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H5 - default STM32H5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32H576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32H5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32H5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32H5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32H5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32H5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32H5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32H5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32H5_FLASH_CONFIG_B - bool - default n - depends on STM32H5_STM32H50XXX - -config STM32H5_FLASH_CONFIG_C - bool - default n - depends on STM32H5_STM32H52XXX - -config STM32H5_FLASH_CONFIG_E - bool - default n - depends on STM32H5_STM32H52XXX || STM32H5_STM32H53XXX - -config STM32H5_FLASH_CONFIG_G - bool - default n - depends on STM32H5_STM32H56XXX - -config STM32H5_FLASH_CONFIG_I - bool - default n - depends on STM32H5_STM32H56XXX || STM32H5_STM32H57XXX + select STM32_HAVE_ETHERNET # Pin/package configurations config STM32H5_IO_CONFIG_K + # Package designator K bool default n config STM32H5_IO_CONFIG_T + # Package designator T bool default n config STM32H5_IO_CONFIG_C + # Package designator C bool default n config STM32H5_IO_CONFIG_R + # Package designator R bool default n config STM32H5_IO_CONFIG_J + # Package designator J bool default n config STM32H5_IO_CONFIG_M + # Package designator M bool default n config STM32H5_IO_CONFIG_V + # Package designator V bool default n config STM32H5_IO_CONFIG_Q + # Package designator Q bool default n config STM32H5_IO_CONFIG_Z + # Package designator Z bool default n config STM32H5_IO_CONFIG_A + # Package designator A bool default n comment "STM32H5 SRAM2 Options" -config STM32H5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32H5_SRAM2_INIT - -config STM32H5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - If the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32H5_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain a uniform flash memory mapping. - -comment "STM32H5 Peripherals" - -menu "STM32H5 Peripheral Selection" - -# These "hidden" settings determine if a peripheral option is available -# for the selected MCU - -config STM32H5_HAVE_ETHERNET - bool - default n - -config STM32H5_HAVE_PHY_POLLED - bool - default n - -config STM32H5_HAVE_FDCAN1 - bool - default n - -config STM32H5_HAVE_FDCAN2 - bool - default n - -config STM32H5_HAVE_HSI48 - bool - default n - -config STM32H5_HAVE_ICACHE - bool - default n - -config STM32H5_HAVE_I2C4 - bool - default n - -config STM32H5_HAVE_LPUART1 - bool - default n - -config STM32H5_HAVE_SPI5 - bool - default n - -config STM32H5_HAVE_SPI6 - bool - default n - -config STM32H5_HAVE_USART1 - bool - default n - -config STM32H5_HAVE_USART2 - bool - default n - -config STM32H5_HAVE_USART3 - bool - default n - -config STM32H5_HAVE_UART4 - bool - default n - -config STM32H5_HAVE_UART5 - bool - default n - -config STM32H5_HAVE_USART6 - bool - default n - -config STM32H5_HAVE_UART7 - bool - default n - -config STM32H5_HAVE_UART8 - bool - default n - -config STM32H5_HAVE_UART9 - bool - default n - -config STM32H5_HAVE_USART10 - bool - default n - -config STM32H5_HAVE_USART11 - bool - default n - -config STM32H5_HAVE_UART12 - bool - default n - -config STM32H5_HAVE_USBFS - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H5_ADC - bool - default n - -config STM32H5_DMA - bool - default n - -config STM32H5_FDCAN - bool - default n - -config STM32H5_PWM - bool - default n - -config STM32H5_SPI - bool - default n - -config STM32H5_SPI_DMA - bool - default n - -config STM32H5_TIM - bool - default n - -config STM32H5_USART - bool - default n - -# These are the peripheral selections proper - -config STM32H5_ADC1 - bool "ADC1" - default n - select STM32H5_ADC - -config STM32H5_ADC2 - bool "ADC2" - default n - select STM32H5_ADC - -config STM32H5_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -config STM32H5_DMA1 - bool "DMA1" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DMA2 - bool "DMA2" - default n - select STM32H5_DMA - select ARCH_DMA - -config STM32H5_DTS - bool "DTS" - default n - ---help--- - Enable support for the on‑die digital temperature sensor (DTS) - built into STM32H5 devices. When enabled, the driver will register - a `/dev/sensor_tempX` device using the common NuttX sensor framework. - -config STM32H5_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H5_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H5_HAVE_PHY_POLLED - -config STM32H5_FDCAN1 - bool "FDCAN1" - default n - depends on STM32H5_HAVE_FDCAN1 - select STM32H5_FDCAN - -config STM32H5_FDCAN2 - bool "FDCAN2" - default n - depends on STM32H5_HAVE_FDCAN2 - select STM32H5_FDCAN - -config STM32H5_ICACHE - bool "ICACHE" - default n - depends on STM32H5_HAVE_ICACHE - -config STM32H5_QSPI1 - bool "QSPI1" - default n - -menu "U[S]ART/LPUART Selection" - -config STM32H5_UART4 - bool "UART4" - default n - depends on STM32H5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART5 - bool "UART5" - default n - depends on STM32H5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART7 - bool "UART7" - default n - depends on STM32H5_HAVE_UART7 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART8 - bool "UART8" - default n - depends on STM32H5_HAVE_UART8 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART9 - bool "UART9" - default n - depends on STM32H5_HAVE_UART9 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_UART12 - bool "UART12" - default n - depends on STM32H5_HAVE_UART12 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART1 - bool "USART1" - default n - depends on STM32H5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART2 - bool "USART2" - default n - depends on STM32H5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART3 - bool "USART3" - default n - depends on STM32H5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART6 - bool "USART6" - default n - depends on STM32H5_HAVE_USART6 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART10 - bool "USART10" - default n - depends on STM32H5_HAVE_USART10 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_USART11 - bool "USART11" - default n - depends on STM32H5_HAVE_USART11 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -config STM32H5_LPUART1 - bool "LPUART1" - default n - depends on STM32H5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H5_USART - -endmenu # U[S]ART/LPUART Selection - -menu "I2C Selection" - -config STM32H5_I2C - bool - default n - -config STM32H5_I2C1 - bool "I2C1" - default n - select STM32H5_I2C - -config STM32H5_I2C2 - bool "I2C2" - default n - select STM32H5_I2C - -config STM32H5_I2C3 - bool "I2C3" - default n - select STM32H5_I2C - -config STM32H5_I2C4 - bool "I2C4" - default n - depends on STM32H5_HAVE_I2C4 - select STM32H5_I2C - -endmenu # I2C Selection - -menu "SPI Selection" - -config STM32H5_SPI1 - bool "SPI1" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI2 - bool "SPI2" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI3 - bool "SPI3" - default n - select SPI - select STM32H5_SPI - -config STM32H5_SPI4 - bool "SPI4" - default n - depends on STM32H5_HAVE_SPI4 - select SPI - select STM32H5_SPI - -config STM32H5_SPI5 - bool "SPI5" - default n - depends on STM32H5_HAVE_SPI5 - select SPI - select STM32H5_SPI - -config STM32H5_SPI6 - bool "SPI6" - default n - depends on STM32H5_HAVE_SPI6 - select SPI - select STM32H5_SPI - -endmenu # SPI Selection - -menu "STM32H5 Timer Selection" - -config STM32H5_TIM1 - bool "TIM1" - default n - select STM32H5_TIM - -config STM32H5_TIM2 - bool "TIM2" - default n - select STM32H5_TIM - -config STM32H5_TIM3 - bool "TIM3" - default n - select STM32H5_TIM - -config STM32H5_TIM4 - bool "TIM4" - default n - select STM32H5_TIM - -config STM32H5_TIM5 - bool "TIM5" - default n - select STM32H5_TIM - -config STM32H5_TIM6 - bool "TIM6" - default n - select STM32H5_TIM - -config STM32H5_TIM7 - bool "TIM7" - default n - select STM32H5_TIM - -config STM32H5_TIM8 - bool "TIM8" - default n - select STM32H5_TIM - -config STM32H5_TIM12 - bool "TIM12" - default n - select STM32H5_TIM - -config STM32H5_TIM13 - bool "TIM13" - default n - select STM32H5_TIM - -config STM32H5_TIM14 - bool "TIM14" - default n - select STM32H5_TIM - -config STM32H5_TIM15 - bool "TIM15" - default n - select STM32H5_TIM - -config STM32H5_TIM16 - bool "TIM16" - default n - select STM32H5_TIM - -config STM32H5_TIM17 - bool "TIM17" - default n - select STM32H5_TIM - -endmenu # STM32H5 Timer Selection - -choice STM32H5_USBFS_MODE - prompt "USB FS Mode" - depends on STM32H5_HAVE_USBFS - default STM32H5_USBFS_NONE - ---help--- - Select the operating mode for the USB_DRD_FS peripheral. - The hardware supports Device or Host, but not simultaneously. - -config STM32H5_USBFS_NONE - bool "Disabled" - -config STM32H5_USBFS - bool "USB Device" - select USBDEV - -config STM32H5_USBFS_HOST - bool "USB Host" - select USBHOST_HAVE_ASYNCH - select USBHOST - ---help--- - Enable USB host mode for USB_DRD_FS peripheral. - -endchoice - -endmenu # STM32H5 Peripheral Selection - -menu "DTS Configuration" - depends on STM32H5_DTS - -config STM32H5_DTS_REFCLK_LSE - bool "Use LSE (32.768 kHz crystal) as DTS reference clock" - default n - ---help--- - Select the low‑speed external (LSE) oscillator as the reference clock - for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will - measure FM(T) pulses over N LSE cycles. - - If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference - (REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the - calibration prescaler ≤ 1 MHz. - -config STM32H5_DTS_SMP_TIME - int "DTS sampling time (TS1_SMP_TIME[3:0])" - default 1 - range 1 15 - ---help--- - Number of reference‑clock cycles (PCLK or LSE) counted per - DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles). - -config STM32H5_DTS_TRIGGER - int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])" - default 0 - ---help--- - If non‑zero, DTS will start measurements on the rising edge of - the selected hardware line. Values match RM0481 Table 275: - 0=Software Trigger, 1=LPTIM1_CH1,  - 2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved. - -config STM32H5_DTS_LOW_THRESHOLD - int "DTS low‑threshold (°C)" - default 0 - ---help--- - The temperature (in whole °C) below which the DTS window comparator will - assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0. - -config STM32H5_DTS_HIGH_THRESHOLD - int "DTS high‑threshold (°C)" - default 100 - ---help--- - The temperature (in whole °C) above which the DTS window comparator will - assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD. - -config STM32H5_DTS_ITEN_ITEF - bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)" - default y - ---help--- - Enable the synchronous “end of measurement” interrupt for the - digital temperature sensor. When set, the driver will attach - and unmask TS1_ITEF and will call your ISR on every fresh sample. - -config STM32H5_DTS_ITEN_ITLF - bool "Enable DTS low‑threshold interrupt (TS1_ITLF)" - default n - ---help--- - Enable the synchronous “low threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITLF so you can get notified whenever the measured value - drops below your programmed low‑threshold. - -config STM32H5_DTS_ITEN_ITHF - bool "Enable DTS high‑threshold interrupt (TS1_ITHF)" - default n - ---help--- - Enable the synchronous “high threshold crossed” interrupt for the - digital temperature sensor. When set, the driver will unmask - TS1_ITHF so you can get notified whenever the measured value - exceeds your programmed high‑threshold. - -config STM32H5_DTS_AITEN_AITEF - bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous end‑of‑measurement interrupt. This will - set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup - event when a conversion completes (in Stop/Sleep modes). - -config STM32H5_DTS_AITEN_AITLF - bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous low‑threshold comparator interrupt. This - will set TS1_AITLEN in DTS_ITENR and generate a wakeup event - when the measurement drops below your low threshold. - -config STM32H5_DTS_AITEN_AITHF - bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)" - depends on STM32H5_DTS_REFCLK_LSE - default n - ---help--- - Enable the asynchronous high‑threshold comparator interrupt. This - will set TS1_AITHEN in DTS_ITENR and generate a wakeup event - when the measurement exceeds your high threshold. - -endmenu # DTS Configuration - -config STM32H5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -menu "ICACHE Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_MONITOR_EN - bool "Enable ICACHE Hit/Miss Counters" - default n - -config STM32H5_ICACHE_DIRECT - bool "Enable 1-Way Direct Mapped Cache (N-Way = default)" - default n - -menu "ICACHE Interrupt Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_INV_INT - bool "Enable interrupts on full invalidation completion." - default n - -config STM32H5_ICACHE_ERR_INT - bool "Enable interrupts on occurrences of cache errors." - default n - -endmenu # ICACHE Interrupt Configuration - -menu "ICACHE Region Configuration" - depends on STM32H5_ICACHE - -config STM32H5_ICACHE_REGION0 - bool "Enable Configuration of ICACHE Region 0" - default n - -config STM32H5_ICACHE_REGION1 - bool "Enable Configuration of ICACHE Region 1" - default n - -config STM32H5_ICACHE_REGION2 - bool "Enable Configuration of ICACHE Region 2" - default n - -config STM32H5_ICACHE_REGION3 - bool "Enable Configuration of ICACHE Region 3" - default n - -menu "Region 0 Configuration" - depends on STM32H5_ICACHE_REGION0 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION0_BADDR - hex "ICACHE Region 0 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 0. - -config STM32H5_ICACHE_REGION0_RSIZE - int "ICACHE Region 0 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set the size of Region 0. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION0_REMAPADDR - hex "ICACHE Region 0 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Set bits [31:21] of ICACHE Region 0 Remap Address.. - -config STM32H5_ICACHE_REGION0_MSTSEL - int "ICACHE Region 0 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select ICACHE Region 0 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION0_HBURST - int "ICACHE Region 0 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION0 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 0 Configuration - -menu "Region 1 Configuration" - depends on STM32H5_ICACHE_REGION1 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION1_BADDR - hex "ICACHE Region 1 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 1. - -config STM32H5_ICACHE_REGION1_RSIZE - int "ICACHE Region 1 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set the size of Region 1. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION1_REMAPADDR - hex "ICACHE Region 1 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Set bits [31:21] of ICACHE Region 1 Remap Address.. - -config STM32H5_ICACHE_REGION1_MSTSEL - int "ICACHE Region 1 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select ICACHE Region 1 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION1_HBURST - int "ICACHE Region 1 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION1 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 1 Configuration - -menu "Region 2 Configuration" - depends on STM32H5_ICACHE_REGION2 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION2_BADDR - hex "ICACHE Region 2 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 2. - -config STM32H5_ICACHE_REGION2_RSIZE - int "ICACHE Region 2 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set the size of Region 2. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION2_REMAPADDR - hex "ICACHE Region 2 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Set bits [31:21] of ICACHE Region 2 Remap Address.. - -config STM32H5_ICACHE_REGION2_MSTSEL - int "ICACHE Region 2 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select ICACHE Region 2 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION2_HBURST - int "ICACHE Region 2 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION2 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 2 Configuration - -menu "Region 3 Configuration" - depends on STM32H5_ICACHE_REGION3 && STM32H5_HAVE_ICACHE_REMAP - -config STM32H5_ICACHE_REGION3_BADDR - hex "ICACHE Region 3 Base Address Bits [28:21]" - default 0 - range 0 255 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [28:21] of the base address for ICACHE Region 3. - -config STM32H5_ICACHE_REGION3_RSIZE - int "ICACHE Region 3 Size" - default 1 - range 1 7 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set the size of Region 3. - 1 = 2 Mbytes, 2 = 4 Mbytes, 3 = 8 Mbytes, 4 = 16 Mbytes, - 5 = 2 Mbytes, 6 = 64 Mbytes, 7 = 128 Mbytes. - -config STM32H5_ICACHE_REGION3_REMAPADDR - hex "ICACHE Region 3 Remap Address Bits [31:21]" - default 0 - range 0 2047 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Set bits [31:21] of ICACHE Region 3 Remap Address.. - -config STM32H5_ICACHE_REGION3_MSTSEL - int "ICACHE Region 3 Master Select (0 or 1)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select ICACHE Region 3 Master 1 (0) or Master 2 (1). - -config STM32H5_ICACHE_REGION3_HBURST - int "ICACHE Region 3 Output Burst Type (0 = Wrap, 1 = Incr)" - default 0 - range 0 1 - depends on STM32H5_ICACHE_REGION3 - ---help--- - Select Wrap (0) or Increment (1) Output Burst Type. - -endmenu # Region 3 Configuration - -endmenu # ICACHE Region Configuration - -endmenu # ICACHE Configuration - -config STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "ADC Configuration" - depends on STM32H5_ADC - -config STM32H5_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H5_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32H5_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC1_DMA - bool "ADC1 DMA Enable" - depends on STM32H5_ADC1 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC1_DMA_CFG - bool "ADC1 DMA configuration" - depends on STM32H5_ADC1 && STM32H5_ADC1_DMA - default n - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32H5_ADC1_OVERSAMPLE - bool "Enable ADC1 hardware oversampling support" - depends on STM32H5_ADC1 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC1_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC1_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC1_OVERSAMPLE - -config STM32H5_ADC1_WDG1 - bool "Enable STM32H5 ADC1 Watchdog 1" - depends on STM32H5_ADC1 - default n - ---help--- - Enable STM32H5 ADC1 Watchdog 1. - -config STM32H5_ADC1_WDG1_FLT - int "Set ADC1 Watchdog 1 Filter" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC1_WDG1_LOWTHRESH - int "Set ADC1 Watchdog 1 Low Threshold" - depends on STM32H5_ADC1_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC1_WDG1_HIGHTHRESH - int "Set ADC1 Watchdog 1 High Threshold" - depends on STM32H5_ADC1_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC1 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC1_WDG1_SGL - bool "Enable STM32H5 ADC1 Watchdog 1 on a single channel" - depends on STM32H5_ADC1_WDG1 - default n - ---help--- - This option determines if ADC1 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC1_WDG1_CHAN - int "STM32H5 ADC1 Watchdog 1 Channel Selection" - depends on STM32H5_ADC1_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC1 Watchdog 1. - -config STM32H5_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32H5_ADC2 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32H5_ADC2_DMA - bool "ADC2 DMA Enable" - depends on STM32H5_ADC2 && STM32H5_DMA - default n - ---help--- - If DMA is selected, then the ADC may be configured to support DMA - transfer, which is necessary if multiple channels are read or if - very high trigger frequencies are used. - -config STM32H5_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H5_ADC2 && STM32H5_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H5_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32H5_ADC2_DMA && STM32H5_DMA - range 0 1 - default 0 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32H5_ADC2_OVERSAMPLE - bool "Enable ADC2 hardware oversampling support" - depends on STM32H5_ADC2 - default n - ---help--- - Enable the on-chip ADC oversampling/accumulation block (CFGR2.OVSE). - Only STM32G0 and STM32L0 series include this hardware block. - -if STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_TROVS - bool "Enable triggered oversampling (CFGR2.TROVS)" - default n - ---help--- - If set, oversampling will only occur when a trigger event occurs. - If not set, oversampling occurs continuously (TOVS=0). - -config STM32H5_ADC2_OVSR - int "Oversampling ratio (CFGR2.OVSR)" - default 0 - range 0 7 - ---help--- - Sets the oversampling ratio as 2^(OVSR+1). For example: - 0 -> 2× - 1 -> 4× - 2 -> 8× - ... - 7 -> 256× - -config STM32H5_ADC2_OVSS - int "Oversampling right-shift bits (CFGR2.OVSS)" - default 0 - range 0 8 - ---help--- - Sets how many bits the accumulated result is right-shifted. - Max of 8-bits. - -endif # STM32H5_ADC2_OVERSAMPLE - -config STM32H5_ADC2_WDG1 - bool "Enable STM32H5 ADC2 Watchdog 1" - depends on STM32H5_ADC2 - default n - ---help--- - Enable STM32H5 ADC2 Watchdog 1. - -config STM32H5_ADC2_WDG1_FLT - int "Set ADC2 Watchdog 1 Filter" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 7 - ---help--- - N+1 watchdog events generates an interrupt. - Default: 0. - -config STM32H5_ADC2_WDG1_LOWTHRESH - int "Set ADC2 Watchdog 1 Low Threshold" - depends on STM32H5_ADC2_WDG1 - default 0 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 low threshold value. - Default: 0. - -config STM32H5_ADC2_WDG1_HIGHTHRESH - int "Set ADC2 Watchdog 1 High Threshold" - depends on STM32H5_ADC2_WDG1 - default 4095 - range 0 4095 - ---help--- - Set the ADC2 Watchdog 1 high threshold value. - Default: 4095. - -config STM32H5_ADC2_WDG1_SGL - bool "Enable STM32H5 ADC2 Watchdog 1 on a single channel" - depends on STM32H5_ADC2_WDG1 - default n - ---help--- - This option determines if ADC2 Watchdog 1 is enabled on all - channels or just a single channel. - -config STM32H5_ADC2_WDG1_CHAN - int "STM32H5 ADC2 Watchdog 1 Channel Selection" - depends on STM32H5_ADC2_WDG1_SGL - default 0 - range 0 19 - ---help--- - Select the channel to enable for ADC2 Watchdog 1. - -endmenu # ADC Configuration - -menu "SPI Configuration" - depends on STM32H5_SPI - -config STM32H5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be too high in - the interrupt driven case. - -config STM32H5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H5_SPI1 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H5_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H5_SPI2 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H5_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H5_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H5_SPI3 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H5_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H5_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H5_SPI4 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H5_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H5_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H5_SPI5 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H5_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H5_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H5_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H5_SPI6 && !STM32H5_SPI_INTERRUPT - select STM32H5_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H5_SPI_INTERRUPT - -config STM32H5_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H5_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H5_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H5_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H5_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H5_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H5_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H5_TIM1 - select STM32H5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM1_PWM - -config STM32H5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H5_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL1 - -config STM32H5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL2 - -config STM32H5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL3 - -config STM32H5_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL4 - -config STM32H5_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM1_CHANNEL5 - -config STM32H5_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM1_CHANNEL6 - -config STM32H5_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM1_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM1_CHANNEL = 1 - -config STM32H5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 1 - -if STM32H5_TIM1_CHANNEL = 2 - -config STM32H5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 2 - -if STM32H5_TIM1_CHANNEL = 3 - -config STM32H5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM1_CHANNEL = 3 - -if STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM1_CHANNEL = 4 - -config STM32H5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM1_PWM - -config STM32H5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H5_TIM2 - select STM32H5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM2_PWM - -config STM32H5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL1 - -config STM32H5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL2 - -config STM32H5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL3 - -config STM32H5_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM2_CHANNEL4 - -config STM32H5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM2_CHANNEL = 1 - -config STM32H5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM2_CHANNEL = 1 - -if STM32H5_TIM2_CHANNEL = 2 - -config STM32H5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM2_CHANNEL = 2 - -if STM32H5_TIM2_CHANNEL = 3 - -config STM32H5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM2_CHANNEL = 3 - -if STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM2_CHANNEL = 4 - -config STM32H5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM2_PWM - -config STM32H5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H5_TIM3 - select STM32H5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM3_PWM - -config STM32H5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL1 - -config STM32H5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL2 - -config STM32H5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL3 - -config STM32H5_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM3_CHANNEL4 - -config STM32H5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM3_CHANNEL = 1 - -config STM32H5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM3_CHANNEL = 1 - -if STM32H5_TIM3_CHANNEL = 2 - -config STM32H5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM3_CHANNEL = 2 - -if STM32H5_TIM3_CHANNEL = 3 - -config STM32H5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM3_CHANNEL = 3 - -if STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM3_CHANNEL = 4 - -config STM32H5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM3_PWM - -config STM32H5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H5_TIM4 - select STM32H5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM4_PWM - -config STM32H5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL1 - -config STM32H5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL2 - -config STM32H5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL3 - -config STM32H5_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM4_CHANNEL4 - -config STM32H5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM4_CHANNEL = 1 - -config STM32H5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM4_CHANNEL = 1 - -if STM32H5_TIM4_CHANNEL = 2 - -config STM32H5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM4_CHANNEL = 2 - -if STM32H5_TIM4_CHANNEL = 3 - -config STM32H5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM4_CHANNEL = 3 - -if STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM4_CHANNEL = 4 - -config STM32H5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM4_PWM - -config STM32H5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H5_TIM5 - select STM32H5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM5_PWM - -config STM32H5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL1 - -config STM32H5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL2 - -config STM32H5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL3 - -config STM32H5_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM5_CHANNEL4 - -config STM32H5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL4 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM5_CHANNEL = 1 - -config STM32H5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM5_CHANNEL = 1 - -if STM32H5_TIM5_CHANNEL = 2 - -config STM32H5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM5_CHANNEL = 2 - -if STM32H5_TIM5_CHANNEL = 3 - -config STM32H5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H5_TIM5_CHANNEL = 3 - -if STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM5_CHANNEL = 4 - -config STM32H5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM5_PWM - -config STM32H5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H5_TIM8 - select STM32H5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM8_PWM - -config STM32H5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H5_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H5_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H5_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL1 - -config STM32H5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL2 - -config STM32H5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL3 - -config STM32H5_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL4 - -config STM32H5_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H5_TIM8_CHANNEL5 - -config STM32H5_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H5_TIM8_CHANNEL6 - -config STM32H5_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H5_TIM8_CHANNEL6 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H5_TIM8_CHANNEL = 1 - -config STM32H5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 1 - -if STM32H5_TIM8_CHANNEL = 2 - -config STM32H5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 2 - -if STM32H5_TIM8_CHANNEL = 3 - -config STM32H5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H5_TIM8_CHANNEL = 3 - -if STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H5_TIM8_CHANNEL = 4 - -config STM32H5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM8_PWM - -config STM32H5_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H5_TIM12 - select STM32H5_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM12_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL1 - -config STM32H5_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM12_CHANNEL2 - -config STM32H5_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM12_CHANNEL = 1 - -config STM32H5_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM12_CHANNEL = 1 - -if STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM12_CHANNEL = 2 - -config STM32H5_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM12_PWM - -config STM32H5_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H5_TIM13 - select STM32H5_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM13_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM13_CHANNEL1 - -config STM32H5_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM13_CHANNEL = 1 - -config STM32H5_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM13_PWM - -config STM32H5_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H5_TIM14 - select STM32H5_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM14_PWM - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM14_CHANNEL1 - -config STM32H5_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM14_CHANNEL = 1 - -config STM32H5_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM14_PWM - -config STM32H5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H5_TIM15 - select STM32H5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM15_PWM - -config STM32H5_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H5_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL1 - -config STM32H5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H5_TIM15_CHANNEL2 - -config STM32H5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H5_TIM15_CHANNEL2 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H5_TIM15_CHANNEL = 1 - -config STM32H5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 1 - -if STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H5_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H5_TIM15_CHANNEL = 2 - -config STM32H5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM15_PWM - -config STM32H5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H5_TIM16 - select STM32H5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM16_PWM - -config STM32H5_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H5_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM16_CHANNEL1 - -config STM32H5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM16_CHANNEL = 1 - -config STM32H5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM16_PWM - -config STM32H5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H5_TIM17 - select STM32H5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H5_TIM17_PWM - -config STM32H5_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H5_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H5_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H5_TIM17_CHANNEL1 - -config STM32H5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL1 - -endif # STM32H5_PWM_MULTICHAN - -if !STM32H5_PWM_MULTICHAN - -config STM32H5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H5_TIM17_CHANNEL = 1 - -config STM32H5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H5_PWM_MULTICHAN - -endif # STM32H5_TIM17_PWM - -config STM32H5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H5_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H5_TIM1 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM1_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H5_TIM8 - select STM32H5_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H5_TIM8_PULSECOUNT - -config STM32H5_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H5_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H5_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H5_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H5_TIM8_PULSECOUNT -config STM32H5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H5_TIM1 && STM32H5_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H5_TIM1_ADC1 - depends on STM32H5_TIM1_ADC - -config STM32H5_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H5_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -endchoice - -config STM32H5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H5_TIM2 && STM32H5_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H5_TIM2_ADC1 - depends on STM32H5_TIM2_ADC - -config STM32H5_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H5_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -endchoice - -config STM32H5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H5_TIM3 && STM32H5_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H5_TIM3_ADC1 - depends on STM32H5_TIM3_ADC - -config STM32H5_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H5_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -endchoice - -config STM32H5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H5_TIM4 && STM32H5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H5_TIM4_ADC1 - depends on STM32H5_TIM4_ADC - -config STM32H5_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H5_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -endchoice - -config STM32H5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H5_TIM6 && STM32H5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H5_TIM6_ADC1 - depends on STM32H5_TIM6_ADC - -config STM32H5_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H5_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -endchoice - -config STM32H5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H5_TIM8 && STM32H5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H5_TIM8_ADC1 - depends on STM32H5_TIM8_ADC - -config STM32H5_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H5_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -endchoice - -config STM32H5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H5_TIM15 && STM32H5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H5_TIM15_ADC1 - depends on STM32H5_TIM15_ADC - -config STM32H5_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H5_ADC1 - select STM32H5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H5_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H5_ADC2 - select STM32H5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -endchoice - -config STM32H5_HAVE_ADC1_TIMER - bool - -config STM32H5_HAVE_ADC2_TIMER - bool - -config STM32H5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 5 - depends on STM32H5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO 5:TRGO2 - -config STM32H5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32H5_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32H5_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32H5_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32H5_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32H5_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32H5_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM12_CAP - bool "TIM12 Capture" - default n - depends on STM32H5_TIM12 - ---help--- - Reserve timer 12 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM13_CAP - bool "TIM13 Capture" - default n - depends on STM32H5_TIM13 - ---help--- - Reserve timer 13 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM14_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM14 - ---help--- - Reserve timer 14 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM15_CAP - bool "TIM15 Capture" - default n - depends on STM32H5_TIM15 - ---help--- - Reserve timer 15 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM16_CAP - bool "TIM16 Capture" - default n - depends on STM32H5_TIM16 - ---help--- - Reserve timer 16 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32H5_TIM17_CAP - bool "TIM14 Capture" - default n - depends on STM32H5_TIM17 - ---help--- - Reserve timer 17 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32 TIMx Outputs Configuration" - -config STM32H5_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H5_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H5_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H5_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H5_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H5_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H5_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H5_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H5_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H5_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H5_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H5_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H5_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H5_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H5_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H5_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H5_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H5_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H5_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H5_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H5_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H5_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H5_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H5_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H5_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H5_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H5_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H5_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H5_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H5_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H5_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H5_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H5_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H5_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H5_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H5_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H5_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H5_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H5_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H5_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H5_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H5_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H5_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H5_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H5_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H5_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H5_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H5_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H5_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H5_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H5_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H5_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H5_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H5_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H5_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H5_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H5_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H5_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H5_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H5_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H5_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H5_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H5_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H5_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H5_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H5_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H5_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H5_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H5_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H5_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H5_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H5_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H5_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H5_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H5_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H5_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H5_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H5_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H5_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H5_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H5_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H5_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H5_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H5_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H5_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H5_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H5_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H5_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H5_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -comment "USB Device Configuration" - -menu "USB Full Speed Device Configuration" - depends on STM32H5_USBFS - -config STM32H5_USBFS_REGDEBUG - bool "Register-Level Debug" - default n - depends on STM32H5_USBFS && DEBUG_USB_INFO - ---help--- - Enable very low-level register access debug. - -endmenu - -comment "USB Host Configuration" - -menu "USB Full Speed Host Configuration" - depends on STM32H5_USBFS_HOST - -config STM32H5_USBDRD_NCHANNELS - int "Number of host channels" - default 8 - range 1 8 - depends on STM32H5_USBFS_HOST - ---help--- - Number of USB host channels to use. - -config STM32H5_USBDRD_DESCSIZE - int "Descriptor buffer size" - default 128 - depends on STM32H5_USBFS_HOST - ---help--- - Size of descriptor/request buffers. - -endmenu - -config STM32H5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32H5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32H5_LPUART1_SERIALDRIVER - depends on STM32H5_LPUART1 - -config STM32H5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32H5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 RX DMA" - default n - depends on STM32H5_LPUART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config LPUART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure LPUART1 RX pin on close" - default n - -config LPUART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure LPUART1 TX pin on close" - default n - -config LPUART1_UNCONFIG_DIR_ON_CLOSE - depends on LPUART1_RS485 - bool "Unconfigure LPUART1 DIR pin on close" - default n - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32H5_USART1_SERIALDRIVER - depends on STM32H5_USART1 - -config STM32H5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32H5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 RX DMA" - default n - depends on STM32H5_USART1 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -config USART1_UNCONFIG_DIR_ON_CLOSE - depends on USART1_RS485 - bool "Unconfigure USART1 DIR pin on close" - default n - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32H5_USART2_SERIALDRIVER - depends on STM32H5_USART2 - -config STM32H5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32H5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 RX DMA" - default n - depends on STM32H5_USART2 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART2_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART2 RX pin on close" - default n - -config USART2_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART2 TX pin on close" - default n - -config USART2_UNCONFIG_DIR_ON_CLOSE - depends on USART2_RS485 - bool "Unconfigure USART2 DIR pin on close" - default n - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32H5_USART3_SERIALDRIVER - depends on STM32H5_USART3 - -config STM32H5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32H5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 RX DMA" - default n - depends on STM32H5_USART3 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART3_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART3 RX pin on close" - default n - -config USART3_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART3 TX pin on close" - default n - -config USART3_UNCONFIG_DIR_ON_CLOSE - depends on USART3_RS485 - bool "Unconfigure USART3 DIR pin on close" - default n - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32H5_UART4_SERIALDRIVER - depends on STM32H5_UART4 - -config STM32H5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32H5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 RX DMA" - default n - depends on STM32H5_UART4 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART4_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART4 RX pin on close" - default n - -config UART4_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART4 TX pin on close" - default n - -config UART4_UNCONFIG_DIR_ON_CLOSE - depends on UART4_RS485 - bool "Unconfigure UART4 DIR pin on close" - default n - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32H5_UART5_SERIALDRIVER - depends on STM32H5_UART5 - -config STM32H5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32H5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 RX DMA" - default n - depends on STM32H5_UART5 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART5_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART5 RX pin on close" - default n - -config UART5_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART5 TX pin on close" - default n - -config UART5_UNCONFIG_DIR_ON_CLOSE - depends on UART5_RS485 - bool "Unconfigure UART5 DIR pin on close" - default n - -endif # UART5_SERIALDRIVER - -choice - prompt "USART6 Driver Configuration" - default STM32H5_USART6_SERIALDRIVER - depends on STM32H5_USART6 - -config STM32H5_USART6_SERIALDRIVER - bool "Standard serial driver" - select USART6_SERIALDRIVER - select STM32H5_SERIALDRIVER - -endchoice # USART6 Driver Configuration - -if USART6_SERIALDRIVER - -config USART6_RS485 - bool "RS-485 on USART6" - default n - depends on STM32H5_USART6 - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. Currently it cannot be - used with USART6_RXDMA. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXDMA - bool "USART6 RX DMA" - default n - depends on STM32H5_USART6 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART6_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART6 RX pin on close" - default n - -config USART6_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART6 TX pin on close" - default n - -config USART6_UNCONFIG_DIR_ON_CLOSE - depends on USART6_RS485 - bool "Unconfigure USART6 DIR pin on close" - default n - -endif # USART6_SERIALDRIVER - -if UART7_SERIALDRIVER - -config UART7_RS485 - bool "RS-485 on UART7" - default n - depends on STM32H5_UART7 - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. Currently it cannot be - used with UART7_RXDMA. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXDMA - bool "UART7 RX DMA" - default n - depends on STM32H5_UART7 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART7_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART7 RX pin on close" - default n - -config UART7_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART7 TX pin on close" - default n - -config UART7_UNCONFIG_DIR_ON_CLOSE - depends on UART7_RS485 - bool "Unconfigure UART7 DIR pin on close" - default n - -endif # UART7_SERIALDRIVER - -if UART8_SERIALDRIVER - -config UART8_RS485 - bool "RS-485 on UART8" - default n - depends on STM32H5_UART8 - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. Currently it cannot be - used with UART8_RXDMA. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXDMA - bool "UART8 RX DMA" - default n - depends on STM32H5_UART8 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART8_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART8 RX pin on close" - default n - -config UART8_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART8 TX pin on close" - default n - -config UART8_UNCONFIG_DIR_ON_CLOSE - depends on UART8_RS485 - bool "Unconfigure UART8 DIR pin on close" - default n - -endif # UART8_SERIALDRIVER - -if UART9_SERIALDRIVER - -config UART9_RS485 - bool "RS-485 on UART9" - default n - depends on STM32H5_UART9 - ---help--- - Enable RS-485 interface on UART9. Your board config will have to - provide GPIO_UART9_RS485_DIR pin definition. Currently it cannot be - used with UART9_RXDMA. - -config UART9_RS485_DIR_POLARITY - int "UART9 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART9_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART9. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART9_RXDMA - bool "UART9 RX DMA" - default n - depends on STM32H5_UART9 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART9_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART9 RX pin on close" - default n - -config UART9_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART9 TX pin on close" - default n - -config UART9_UNCONFIG_DIR_ON_CLOSE - depends on UART9_RS485 - bool "Unconfigure UART9 DIR pin on close" - default n - -endif # UART9_SERIALDRIVER - -if USART10_SERIALDRIVER - -config USART10_RS485 - bool "RS-485 on USART10" - default n - depends on STM32H5_USART10 - ---help--- - Enable RS-485 interface on USART10. Your board config will have to - provide GPIO_USART10_RS485_DIR pin definition. Currently it cannot be - used with USART10_RXDMA. - -config USART10_RS485_DIR_POLARITY - int "USART10 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART10_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART10. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART10_RXDMA - bool "USART10 RX DMA" - default n - depends on STM32H5_USART10 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART10_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART10 RX pin on close" - default n - -config USART10_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART10 TX pin on close" - default n - -config USART10_UNCONFIG_DIR_ON_CLOSE - depends on USART10_RS485 - bool "Unconfigure USART10 DIR pin on close" - default n - -endif # USART10_SERIALDRIVER - -if USART11_SERIALDRIVER - -config USART11_RS485 - bool "RS-485 on USART11" - default n - depends on STM32H5_USART11 - ---help--- - Enable RS-485 interface on USART11. Your board config will have to - provide GPIO_USART11_RS485_DIR pin definition. Currently it cannot be - used with USART11_RXDMA. - -config USART11_RS485_DIR_POLARITY - int "USART11 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART11_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART11. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART11_RXDMA - bool "USART11 RX DMA" - default n - depends on STM32H5_USART11 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config USART11_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART11 RX pin on close" - default n - -config USART11_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART11 TX pin on close" - default n - -config USART11_UNCONFIG_DIR_ON_CLOSE - depends on USART11_RS485 - bool "Unconfigure USART11 DIR pin on close" - default n - -endif # USART11_SERIALDRIVER - -if UART12_SERIALDRIVER - -config UART12_RS485 - bool "RS-485 on UART12" - default n - depends on STM32H5_UART12 - ---help--- - Enable RS-485 interface on UART12. Your board config will have to - provide GPIO_UART12_RS485_DIR pin definition. Currently it cannot be - used with UART12_RXDMA. - -config UART12_RS485_DIR_POLARITY - int "UART12 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART12_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART12. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART12_RXDMA - bool "UART12 RX DMA" - default n - depends on STM32H5_UART12 && (STM32H5_DMA1 || STM32H5_DMA2) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -config UART12_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure UART12 RX pin on close" - default n - -config UART12_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure UART12 TX pin on close" - default n - -config UART12_UNCONFIG_DIR_ON_CLOSE - depends on UART12_RS485 - bool "Unconfigure UART12 DIR pin on close" - default n - -endif # UART12_SERIALDRIVER - -if STM32H5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32H5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || USART6_RXDMA || USART10_RXDMA || \ - USART11_RXDMA || UART4_RXDMA || UART5_RXDMA || UART7_RXDMA || UART8_RXDMA || \ - UART9_RXDMA || UART12_RXDMA || LPUART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32H5_USART1 || STM32H5_USART2 || STM32H5_USART3 || STM32H5_UART4 || STM32H5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32H5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32H5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H5_USART && STM32H5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H5 serial driver. - -config STM32H5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H5 serial driver. - -config STM32H5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H5 serial driver. - -if PM - -config STM32H5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32H5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "Ethernet MAC Configuration" - depends on STM32H5_ETHMAC - -config STM32H5_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 0 - -config STM32H5_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. - If STM32H5_PHYINIT is defined in the configuration then the board specific logic - must provide stm32_phyinitialize(); The STM32 Ethernet driver will call this - function one time before it first uses the PHY. - -config STM32H5_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H5_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the PHY for status. - -config STM32H5_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H5_MII_EXTCLK - depends on STM32H5_MII - -config STM32H5_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MC01 to clock the MII interface. - -config STM32H5_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MC02 to clock the MII interface. - -config STM32H5_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice - -config STM32H5_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H5_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H5_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H5_ETH_HWCHECKSUM - bool "Enable ethernet hardware checksum" - default n - ---help--- - Enable the IPv4/IPv6 header and TCP/UDP/ICMP payload checksum offload - engine in the Ethernet MAC. - When enabled, hardware generates checksums for TX and checks RX frames. - Be sure to disable software checksums (NET_TCP_CHECKSUMS, NET_UDP_CHECKSUMS, - NET_ICMP_CHECKSUMS, NET_IPV4_CHECKSUMS, NET_IPV6_CHECKSUMS) to avoid - redundant verification in the network stack. - -config STM32H5_ETHFD - bool "Full duplex" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H5_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H5_AUTONEG - ---help--- - If STM32H5_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H5_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H5_AUTONEG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H5_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H5_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H5_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H5_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H5_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H5_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H5_AUTONEG && !STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H5_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H5_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H5_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H5_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H5_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H5_AUTONEG && STM32H5_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H5_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H5_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H5_RMII - bool - default !STM32H5_MII - -choice - prompt "RMII clock configuration" - default STM32H5_RMII_EXTCLK - depends on STM32H5_RMII - -config STM32H5_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H5_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H5_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H5_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H5_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC Configuration - -menu "FDCAN driver configuration" - depends on STM32H5_FDCAN - -choice - prompt "FDCAN character driver or SocketCAN support" - default STM32H5_FDCAN_CHARDRIVER - -config STM32H5_FDCAN_CHARDRIVER - bool "STM32 FDCAN character driver support" - select ARCH_HAVE_CAN_ERRORS - select CAN - -config STM32H5_FDCAN_SOCKET - bool "STM32 FDCAN SocketCAN support" - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - -endchoice # FDCAN character driver or SocketCAN support - -config STM32H5_FDCAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -config STM32H5_FDCAN_QUEUE_MODE - bool "FDCAN QUEUE mode (vs FIFO mode)" - default n - -menu "FDCAN1 device driver options" - depends on STM32H5_FDCAN1 - -choice - prompt "FDCAN1 frame format" - default STM32H5_FDCAN1_ISO11898_1 - -config STM32H5_FDCAN1_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN1_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN1 frame format - -choice - prompt "FDCAN1 mode" - default STM32H5_FDCAN1_CLASSIC - -config STM32H5_FDCAN1_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN1_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN1_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN1 mode - -menu "FDCAN1 Bit Timing" - -config STM32H5_FDCAN1_AUTO_BIT_TIMING - bool "FDCAN1 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN1 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN1_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN1 bitrate in bits per second. Required if STM32H5_FDCAN1 is defined. - -config STM32H5_FDCAN1_NTSEG1 - int "FDCAN1 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NTSEG2 - int "FDCAN1 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_NSJW - int "FDCAN1 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - -config STM32H5_FDCAN1_DBITRATE - int "FDCAN1 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS - ---help--- - FDCAN1 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN1_DTSEG1 - int "FDCAN1 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DTSEG2 - int "FDCAN1 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN1_DSJW - int "FDCAN1 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN1_FD_BRS && !STM32H5_FDCAN1_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN1 Bit Timing - -config STM32H5_FDCAN1_LOOPBACK - bool "Enable FDCAN1 loopback mode" - default n - ---help--- - Enable the FDCAN1 local loopback mode for testing purposes. - -endmenu # FDCAN1 device driver options - -menu "FDCAN2 device driver options" - depends on STM32H5_FDCAN2 - -choice - prompt "FDCAN2 frame format" - default STM32H5_FDCAN2_ISO11898_1 - -config STM32H5_FDCAN2_ISO11898_1 - bool "ISO11898-1" - ---help--- - Enable ISO11898-1 frame format - -config STM32H5_FDCAN2_NONISO_FORMAT - bool "Non ISO" - ---help--- - Enable Non ISO, Bosch CAN FD Specification V1.0 - -endchoice # FDCAN2 frame format - -choice - prompt "FDCAN2 mode" - default STM32H5_FDCAN2_CLASSIC - -config STM32H5_FDCAN2_CLASSIC - bool "Classic CAN" - ---help--- - Enable Classic CAN mode - -config STM32H5_FDCAN2_FD - bool "CAN FD" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode - -config STM32H5_FDCAN2_FD_BRS - bool "CAN FD with fast bit rate switching" - depends on CAN_FD || NET_CAN_CANFD - ---help--- - Enable CAN FD mode with fast bit rate switching mode. - -endchoice # FDCAN2 mode - -menu "FDCAN2 Bit Timing" - -config STM32H5_FDCAN2_AUTO_BIT_TIMING - bool "FDCAN2 Automatic Bit Timing" - default y - ---help--- - Automatically determine FDCAN2 bit timing (nominal and data) based on bitrate. - -comment "Nominal Bit Timing" - -config STM32H5_FDCAN2_BITRATE - int "FDCAN bitrate" - default 500000 - range 0 1000000 - ---help--- - FDCAN2 bitrate in bits per second. Required if STM32H5_FDCAN2 is defined. - -config STM32H5_FDCAN2_NTSEG1 - int "FDCAN2 NTSEG1 (PropSeg + PhaseSeg1)" - default 6 - range 1 256 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NTSEG2 - int "FDCAN2 NTSEG2 (PhaseSeg2)" - default 7 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_NSJW - int "FDCAN2 synchronization jump width" - default 1 - range 1 128 - depends on !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -comment "Data Bit Timing" - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - -config STM32H5_FDCAN2_DBITRATE - int "FDCAN2 data bitrate" - default 2000000 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS - ---help--- - FDCAN2 bitrate in bits per second. Required if operating in FD mode with bit rate switching (BRS). - -config STM32H5_FDCAN2_DTSEG1 - int "FDCAN2 DTSEG1 (PropSeg + PhaseSeg1 of data phase)" - default 4 - range 1 31 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DTSEG2 - int "FDCAN2 DTSEG2 (PhaseSeg2 of data phase)" - default 4 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The length of the bit time is Tquanta * (SyncSeg + PropSeg + PhaseSeg1 + PhaseSeg2). - -config STM32H5_FDCAN2_DSJW - int "FDCAN2 fast synchronization jump width" - default 2 - range 1 15 - depends on CAN_FD && STM32H5_FDCAN2_FD_BRS && !STM32H5_FDCAN2_AUTO_BIT_TIMING - ---help--- - The duration of a synchronization jump is Tcan_clk x DSJW. - -endmenu # FDCAN2 Bit Timing - -config STM32H5_FDCAN2_LOOPBACK - bool "Enable FDCAN2 loopback mode" - default n - ---help--- - Enable the FDCAN2 local loopback mode for testing purposes. - -endmenu # FDCAN2 device driver options - -endmenu # "FDCAN driver configuration" - -menu "I2C Configuration" - depends on STM32H5_I2C - -menu "Clock Selection" - -choice - depends on STM32H5_I2C1 - prompt "I2C1 Input Clock Selection" - default STM32H5_I2C1_CLK_PCLK1 - -config STM32H5_I2C1_CLK_CSI - bool "CSI" - -config STM32H5_I2C1_CLK_HSI - bool "HSI" - -config STM32H5_I2C1_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C1_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C1 Input Clock Selection - -choice - depends on STM32H5_I2C2 - prompt "I2C2 Input Clock Selection" - default STM32H5_I2C2_CLK_PCLK1 - -config STM32H5_I2C2_CLK_CSI - bool "CSI" - -config STM32H5_I2C2_CLK_HSI - bool "HSI" - -config STM32H5_I2C2_CLK_PCLK1 - bool "PCLK1" - -config STM32H5_I2C2_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C2 Input Clock Selection - -choice - depends on STM32H5_I2C3 - prompt "I2C3 Input Clock Selection" - default STM32H5_I2C3_CLK_PCLK3 - -config STM32H5_I2C3_CLK_CSI - bool "CSI" - -config STM32H5_I2C3_CLK_HSI - bool "HSI" - -config STM32H5_I2C3_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C3_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C3 Input Clock Selection - -choice - depends on STM32H5_I2C4 - prompt "I2C4 Input Clock Selection" - default STM32H5_I2C4_CLK_PCLK3 - -config STM32H5_I2C4_CLK_CSI - bool "CSI" - -config STM32H5_I2C4_CLK_HSI - bool "HSI" - -config STM32H5_I2C4_CLK_PCLK3 - bool "PCLK3" - -config STM32H5_I2C4_CLK_PLL3R - bool "PLL3R" - -endchoice # I2C4 Input Clock Selection - -endmenu # Clock Selection - -menu "Rise/Fall Override" - -config STM32H5_I2C1_RF_OVERRIDE - bool "I2C1" - default n - depends on STM32H5_I2C1 - -config STM32H5_I2C2_RF_OVERRIDE - bool "I2C2" - default n - depends on STM32H5_I2C2 - -config STM32H5_I2C3_RF_OVERRIDE - bool "I2C3" - default n - depends on STM32H5_I2C3 - -config STM32H5_I2C4_RF_OVERRIDE - bool "I2C4" - default n - depends on STM32H5_I2C4 - -menu "Rise/Fall Values" - -config STM32H5_I2C1_RISE - int "I2C1 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C1_FALL - int "I2C1 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C1_RF_OVERRIDE - -config STM32H5_I2C2_RISE - int "I2C2 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C2_FALL - int "I2C2 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C2_RF_OVERRIDE - -config STM32H5_I2C3_RISE - int "I2C3 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C3_FALL - int "I2C3 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C3_RF_OVERRIDE - -config STM32H5_I2C4_RISE - int "I2C4 Rise Time (ns)" - range 0 1000 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -config STM32H5_I2C4_FALL - int "I2C4 Fall Time (ns)" - range 0 300 - default 20 - depends on STM32H5_I2C4_RF_OVERRIDE - -endmenu # Rise/Fall Values - -endmenu # Rise/Fall Override - -menu "Filtering" - -menu "Digital Filters" - -config STM32H5_I2C1_DNF - int "I2C1 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_DNF - int "I2C2 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_DNF - int "I2C3 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_DNF - int "I2C4 Digital Noise Filter" - range 0 15 - default 0 - depends on STM32H5_I2C4 - -endmenu # Digital Filters - -menu "Analog Filters" - -config STM32H5_I2C1_ANFOFF - int "Turn off I2C1 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C1 - -config STM32H5_I2C2_ANFOFF - int "Turn off I2C2 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C2 - -config STM32H5_I2C3_ANFOFF - int "Turn off I2C3 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C3 - -config STM32H5_I2C4_ANFOFF - int "Turn off I2C4 Analog Filter (0=on, 1=off)" - default 1 - range 0 1 - depends on STM32H5_I2C4 - -endmenu # Analog Filters - -endmenu # Filtering - -config STM32H5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H5_I2C - -config STM32H5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H5_I2C - -config STM32H5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -config STM32H5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H5_I2C && !STM32H5_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "QuadSPI Configuration" - depends on STM32H5_QSPI1 - -config STM32H5_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H5 QSPI peripheral requires the size of the Flash be specified - -config STM32H5_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 32 - ---help--- - The STM32H5 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H5_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 5 - range 1 64 - ---help--- - The STM32H5 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H5_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H5_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H5_QSPI_DMA - bool "DMA" - depends on STM32H5_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "Bank selection" - default STM32H5_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H5_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H5_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H5_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice - -choice - prompt "DMA Priority" - default STM32H5_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H5_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H5_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H5_DMA - ---help--- - 'Highest' priority. - -config STM32H5_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H5_DMA - ---help--- - 'High' priority. - -config STM32H5_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H5_DMA - ---help--- - 'Medium' priority. - -config STM32H5_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H5_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32H5_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H5_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H5_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H5_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H5_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu - endif # ARCH_CHIP_STM32H5 diff --git a/arch/arm/src/stm32h5/Make.defs b/arch/arm/src/stm32h5/Make.defs index ca7e9a79619..2b6cb685043 100644 --- a/arch/arm/src/stm32h5/Make.defs +++ b/arch/arm/src/stm32h5/Make.defs @@ -29,7 +29,7 @@ HEAD_ASRC = include armv8-m/Make.defs -ifeq ($(CONFIG_STM32H5_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -44,7 +44,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32H5_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif @@ -52,7 +52,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H5_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif @@ -60,64 +60,64 @@ ifeq ($(CONFIG_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H5_FDCAN_CHARDRIVER),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) CHIP_CSRCS += stm32_fdcan.c endif -ifeq ($(CONFIG_STM32H5_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H5_ICACHE),y) +ifeq ($(CONFIG_STM32_ICACHE),y) CHIP_CSRCS += stm32_icache.c endif -ifeq ($(CONFIG_STM32H5_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H5_QSPI1),y) +ifeq ($(CONFIG_STM32_QSPI1),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H5_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H5_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32_hsi48.c endif -ifeq ($(CONFIG_STM32H5_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32_usbfs.c endif -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) +ifeq ($(CONFIG_STM32_USBFS_HOST),y) CHIP_CSRCS += stm32_usbdrdhost.c endif -ifeq ($(CONFIG_STM32H5_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif -ifeq ($(CONFIG_STM32H5_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H5_DTS),y) +ifeq ($(CONFIG_STM32_DTS),y) CHIP_CSRCS += stm32_dts.c endif -ifeq ($(CONFIG_STM32H5_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H5_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif # Required chip type specific files -ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y) +ifeq ($(CONFIG_STM32_STM32H5XXXX),y) CHIP_CSRCS += stm32h5xx_rcc.c endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h index 420f624695c..b328ec952ce 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/hardware/stm32_ethernet.h @@ -33,7 +33,7 @@ /* Ethernet support only on STM32H563/573 chips. */ -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) /**************************************************************************** * Pre-processor Definitions @@ -681,5 +681,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_STM32H56XXX */ +#endif /* CONFIG_STM32_STM32H56XXX */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_ETHERNET_H */ \ No newline at end of file diff --git a/arch/arm/src/stm32h5/hardware/stm32_flash.h b/arch/arm/src/stm32h5/hardware/stm32_flash.h index f49c7d02d95..417c6fdabee 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32_flash.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h5xxx_flash.h" #else # error "Unsupported STM32 H5 flash" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h index 47125c3173d..cdee82e895b 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpdma.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpdma.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "stm32h56x_dmasigmap.h" #else # error "Unsupported STM32 H5 DMA map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_gpio.h b/arch/arm/src/stm32h5/hardware/stm32_gpio.h index 0218cb50429..8d271424a1d 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h5/hardware/stm32_gpio.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_gpio.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_i2c.h b/arch/arm/src/stm32h5/hardware/stm32_i2c.h index 0969c2732df..ce97ded64f2 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h5/hardware/stm32_i2c.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_i2c.h" #else # error "Unsupported STM32 H5 I2C" diff --git a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h index 2900aff29cc..72f4dec37be 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_memorymap.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_memorymap.h" #else # error "Unsupported STM32 H5 memory map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h index 40b57ccf9e5..555cf41bd49 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H56XXX) +#if defined(CONFIG_STM32_STM32H56XXX) # include "hardware/stm32h56xxx_pinmap.h" #else # error "Unsupported STM32 H5 pin map" diff --git a/arch/arm/src/stm32h5/hardware/stm32_pwr.h b/arch/arm/src/stm32h5/hardware/stm32_pwr.h index 1d4ec638697..269f5a3d9df 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h5/hardware/stm32_pwr.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_pwr.h" #else # error "Unsupported STM32 H5 PWR" diff --git a/arch/arm/src/stm32h5/hardware/stm32_rcc.h b/arch/arm/src/stm32h5/hardware/stm32_rcc.h index 239af8377fc..cf8cc1fd0bd 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32_rcc.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_rcc.h" #else # error "Unsupported STM32 H5 rcc" diff --git a/arch/arm/src/stm32h5/hardware/stm32_sbs.h b/arch/arm/src/stm32h5/hardware/stm32_sbs.h index 7ea88c87705..5d3655aa7ba 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_sbs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_sbs.h @@ -32,7 +32,7 @@ #if !defined(CONFIG_STM32H5_STM32H52XXX) && \ !defined(CONFIG_STM32H5_STM32H53XXX) && \ - !defined(CONFIG_STM32H5_STM32H56XXX) && \ + !defined(CONFIG_STM32_STM32H56XXX) && \ !defined(CONFIG_STM32H5_STM32H57XXX) # warning "SBS not verified on STM32H50x variants." #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32_uart.h b/arch/arm/src/stm32h5/hardware/stm32_uart.h index 9ee7d1e1379..96e87f40144 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h5/hardware/stm32_uart.h @@ -31,7 +31,7 @@ #include "chip.h" #if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX) || \ - defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) + defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # include "hardware/stm32h5xxx_uart.h" #else # error "Unsupported STM32 H5 uart" diff --git a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h index 2f90303f545..88bf401c4dc 100644 --- a/arch/arm/src/stm32h5/hardware/stm32_usbfs.h +++ b/arch/arm/src/stm32h5/hardware/stm32_usbfs.h @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_STM32H5_HAVE_USBFS +#ifdef CONFIG_STM32_HAVE_USBFS /**************************************************************************** * Pre-processor Definitions @@ -331,5 +331,5 @@ #define USB_COUNT_RX_SHIFT (16) /* Bits 25-16: Reception Byte Count */ #define USB_COUNT_RX_MASK (0x3ff << USB_COUNT_RX_SHIFT) -#endif /* CONFIG_STM32H5_HAVE_USBFS */ +#endif /* CONFIG_STM32_HAVE_USBFS */ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h index a388e2f69fd..3d709daa0c7 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h +++ b/arch/arm/src/stm32h5/hardware/stm32h56xxx_pinmap.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) || \ +#if defined(CONFIG_STM32_STM32H563XX) || \ defined(CONFIG_STM32H5_STM32H562XX) /**************************************************************************** * Pre-processor Definitions @@ -786,5 +786,5 @@ #define GPIO_ADC2_INN18_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC2_INP19_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) -#endif /* CONFIG_STM32H5_STM32H563XX*/ +#endif /* CONFIG_STM32_STM32H563XX*/ #endif /* __ARCH_ARM_SRC_STM32H5_HARDWARE_STM32H56XXX_PINMAP_H */ diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h index 0b93384d725..8aed24fcab6 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_flash.h @@ -481,7 +481,7 @@ #define FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_CUR_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_SECWM1R_CUR_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_CUR_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_CUR_SECWM1_END_SHIFT) #endif @@ -496,7 +496,7 @@ #define FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT (0) #define FLASH_SECWM1R_PRG_SECWM1_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_SECWM1R_PRG_SECWM1_STRT_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_STRT_SHIFT) # define FLASH_SECWM1R_PRG_SECWM1_END_MASK (0x7f << FLASH_SECWM1R_PRG_SECWM1_END_SHIFT) #endif @@ -527,7 +527,7 @@ #define FLASH_HDP1R_CUR_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_CUR_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_HDP1R_CUR_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_CUR_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -542,7 +542,7 @@ #define FLASH_HDP1R_PRG_HDP1_STRT_SHIFT (0) #define FLASH_HDP1R_PRG_HDP1_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_HDP1R_PRG_HDP1_STRT_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_STRT_SHIFT) # define FLASH_HDP1R_PRG_HDP1_END_MASK (0x7f << FLASH_HDP1R_PRG_HDP1_END_SHIFT) #endif @@ -587,7 +587,7 @@ #define FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT (0) #define FLASH_SECWM2R_PRG_SECWM2_END_SHIFT (16) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_SECWM2R_PRG_SECWM2_STRT_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_STRT_SHIFT) # define FLASH_SECWM2R_PRG_SECWM2_END_MASK (0x7f << FLASH_SECWM2R_PRG_SECWM2_END_SHIFT) #endif @@ -618,7 +618,7 @@ #define FLASH_HDP2R_CUR_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_CUR_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_HDP2R_CUR_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_CUR_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif @@ -633,7 +633,7 @@ #define FLASH_HDP2R_PRG_HDP2_STRT_SHIFT (0) #define FLASH_HDP2R_PRG_HDP2_END_SHIFT (0) -#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) +#if defined(CONFIG_STM32_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX) # define FLASH_HDP2R_PRG_HDP2_STRT_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_STRT_SHIFT) # define FLASH_HDP2R_PRG_HDP2_END_MASK (0x7f << FLASH_HDP2R_PRG_HDP2_END_SHIFT) #endif diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h index df393544945..eafd85eb2e3 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h index d81ead3491d..8c6abc212aa 100644 --- a/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h +++ b/arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index c6bee5ce1fc..a6036132faa 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -53,7 +53,7 @@ #ifdef CONFIG_ADC -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -168,7 +168,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H5_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -260,7 +260,7 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Double the size of the buffer in circular mode * Circular mode utilizes half-transfer DMA interrupts and a 2x buffer @@ -269,10 +269,10 @@ static const struct adc_ops_s g_adcops = */ #ifdef ADC1_HAVE_DMA -# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC1_DMA_BATCH) +# define ADC1_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC1_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG +# if CONFIG_STM32_ADC1_DMA_CFG == 1 # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE * 2) # else # define ADC1_DMA_BUFFER_SIZE (ADC1_CHAN_BUFFER_SIZE) @@ -290,18 +290,18 @@ static struct stm32_dev_s g_adcpriv1 = .irq = STM32_IRQ_ADC1, .isr = adc12_interrupt, .intf = 1, - .resolution = CONFIG_STM32H5_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, .base = STM32_ADC1_BASE, .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC1_DIFSEL @@ -326,8 +326,8 @@ static struct stm32_dev_s g_adcpriv1 = .hasdma = true, .r_chanbuffer = g_adc1_chanbuffer, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC1_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC1_DMA_CFG + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, +# if CONFIG_STM32_ADC1_DMA_CFG == 1 .circular = true, # else .circular = false, @@ -338,25 +338,25 @@ static struct stm32_dev_s g_adcpriv1 = #ifdef ADC1_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC1_TROVS +# ifdef CONFIG_STM32_ADC1_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC1_OVSR, - .ovss = CONFIG_STM32H5_ADC1_OVSS, + .ovsr = CONFIG_STM32_ADC1_OVSR, + .ovss = CONFIG_STM32_ADC1_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC1_WDG1 +#ifdef CONFIG_STM32_ADC1_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC1_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC1_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC1_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC1_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC1_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC1_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC1_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC1_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC1_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -375,13 +375,13 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32H5_ADC_MAX_SAMPLES *\ - CONFIG_STM32H5_ADC2_DMA_BATCH) +# define ADC2_CHAN_BUFFER_SIZE (CONFIG_STM32_ADC_MAX_SAMPLES *\ + CONFIG_STM32_ADC2_DMA_BATCH) -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG +# ifdef CONFIG_STM32_ADC2_DMA_CFG # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE * 2) # else # define ADC2_DMA_BUFFER_SIZE (ADC2_CHAN_BUFFER_SIZE) @@ -399,18 +399,18 @@ static struct stm32_dev_s g_adcpriv2 = .irq = STM32_IRQ_ADC2, .isr = adc12_interrupt, .intf = 2, - .resolution = CONFIG_STM32H5_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, .base = STM32_ADC2_BASE, .mbase = STM32_ADC2_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H5_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef BOARD_ADC2_DIFSEL @@ -435,8 +435,8 @@ static struct stm32_dev_s g_adcpriv2 = .hasdma = true, .r_chanbuffer = g_adc2_chanbuffer, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H5_ADC2_DMA_BATCH, -# ifdef CONFIG_STM32H5_ADC2_DMA_CFG + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, +# ifdef CONFIG_STM32_ADC2_DMA_CFG .circular = true, # else .circular = false, @@ -447,25 +447,25 @@ static struct stm32_dev_s g_adcpriv2 = #ifdef ADC2_HAVE_OVERSAMPLE .oversample = true, -# ifdef CONFIG_STM32H5_ADC2_TROVS +# ifdef CONFIG_STM32_ADC2_TROVS .trovs = true, # else .trovs = false, # endif - .ovsr = CONFIG_STM32H5_ADC2_OVSR, - .ovss = CONFIG_STM32H5_ADC2_OVSS, + .ovsr = CONFIG_STM32_ADC2_OVSR, + .ovss = CONFIG_STM32_ADC2_OVSS, #else .oversample = false, #endif -#ifdef CONFIG_STM32H5_ADC2_WDG1 +#ifdef CONFIG_STM32_ADC2_WDG1 .wdg1_enable = true, - .wdg1_flt = CONFIG_STM32H5_ADC2_WDG1_FLT, - .wdg1_low_thresh = CONFIG_STM32H5_ADC2_WDG1_LOWTHRESH, - .wdg1_high_thresh = CONFIG_STM32H5_ADC2_WDG1_HIGHTHRESH, -# ifdef CONFIG_STM32H5_ADC2_WDG1_SGL + .wdg1_flt = CONFIG_STM32_ADC2_WDG1_FLT, + .wdg1_low_thresh = CONFIG_STM32_ADC2_WDG1_LOWTHRESH, + .wdg1_high_thresh = CONFIG_STM32_ADC2_WDG1_HIGHTHRESH, +# ifdef CONFIG_STM32_ADC2_WDG1_SGL .wdg1_single_chan = true, - .wdg1_chan = CONFIG_STM32H5_ADC2_WDG1_CHAN, + .wdg1_chan = CONFIG_STM32_ADC2_WDG1_CHAN, # else .wdg1_single_chan = false, .wdg1_chan = 0, @@ -1409,7 +1409,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H5_ADC1) && defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1687,7 +1687,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2033,13 +2033,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2048,7 +2048,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2598,13 +2598,13 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; @@ -2620,10 +2620,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H5_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H5_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H5_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2639,6 +2639,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ - diff --git a/arch/arm/src/stm32h5/stm32_adc.h b/arch/arm/src/stm32h5/stm32_adc.h index cc4dff62400..89031e9bf06 100644 --- a/arch/arm/src/stm32h5/stm32_adc.h +++ b/arch/arm/src/stm32h5/stm32_adc.h @@ -36,7 +36,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* Configuration ************************************************************/ @@ -46,75 +46,75 @@ * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_ADC -# undef CONFIG_STM32H5_TIM1_ADC1 -# undef CONFIG_STM32H5_TIM1_ADC2 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_ADC -# undef CONFIG_STM32H5_TIM2_ADC1 -# undef CONFIG_STM32H5_TIM2_ADC2 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_ADC -# undef CONFIG_STM32H5_TIM3_ADC1 -# undef CONFIG_STM32H5_TIM3_ADC2 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_ADC -# undef CONFIG_STM32H5_TIM4_ADC1 -# undef CONFIG_STM32H5_TIM4_ADC2 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM6 -# undef CONFIG_STM32H5_TIM6_ADC -# undef CONFIG_STM32H5_TIM6_ADC1 -# undef CONFIG_STM32H5_TIM6_ADC2 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_ADC -# undef CONFIG_STM32H5_TIM8_ADC1 -# undef CONFIG_STM32H5_TIM8_ADC2 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_ADC -# undef CONFIG_STM32H5_TIM15_ADC1 -# undef CONFIG_STM32H5_TIM15_ADC2 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 #endif /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H5_ADC1_DMA) || defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) # define ADC_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC1_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) # define ADC1_HAVE_DMA 1 #endif -#if defined(CONFIG_STM32H5_ADC2_DMA) +#if defined(CONFIG_STM32_ADC2_DMA) # define ADC2_HAVE_DMA 1 #endif /* Oversampling support */ #undef ADC_HAVE_OVERSAMPLE -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) || \ - defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) || \ + defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC1_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC1_OVERSAMPLE) # define ADC1_HAVE_OVERSAMPLE 1 #endif -#if defined(CONFIG_STM32H5_ADC2_OVERSAMPLE) +#if defined(CONFIG_STM32_ADC2_OVERSAMPLE) # define ADC2_HAVE_OVERSAMPLE 1 #endif #undef ADC_HAVE_WDG1 -#if defined(CONFIG_STM32H5_ADC1_WDG1) || defined(CONFIG_STM32H5_ADC2_WDG1) +#if defined(CONFIG_STM32_ADC1_WDG1) || defined(CONFIG_STM32_ADC2_WDG1) # define ADC_HAVE_WDG1 1 #endif @@ -136,43 +136,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H5_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -183,52 +183,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC1_TIMTRIG -# error "CONFIG_STM32H5_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H5_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H5_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H5_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H5_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H5_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H5_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -239,11 +239,11 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H5_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H5_ADC2_TIMTRIG -# error "CONFIG_STM32H5_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -254,231 +254,231 @@ # undef ADC_HAVE_TIMER #endif -#if defined(CONFIG_STM32H5_TIM1_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC_CFGR__EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CRFT_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC1) -# if CONFIG_STM32H5_ADC1_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC1_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC1_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 +# error "CONFIG_STM32_ADC1_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC1_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range (TIM15)" # endif #endif -#if defined(CONFIG_STM32H5_TIM1_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC1 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC3 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM1)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM1)" # endif -#elif defined(CONFIG_STM32H5_TIM2_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2CC2 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T2TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM2)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM2)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM2)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM2)" # endif -#elif defined(CONFIG_STM32H5_TIM3_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T3TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM3)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM3)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM3)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM3)" # endif -#elif defined(CONFIG_STM32H5_TIM4_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4CC4 -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T4TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM4)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM4)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM4)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM4)" # endif -#elif defined(CONFIG_STM32H5_TIM6_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T6TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM6)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM6)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM6)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM6)" # endif -#elif defined(CONFIG_STM32H5_TIM8_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM8)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM8)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM8)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM8)" # endif -#elif defined(CONFIG_STM32H5_TIM15_ADC2) -# if CONFIG_STM32H5_ADC2_TIMTRIG == 0 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 1 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 2 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 3 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 4 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC_CFGR_EXTSEL_T15TRGO -# elif CONFIG_STM32H5_ADC2_TIMTRIG == 5 -# error "CONFIG_STM32H5_ADC2_TIMTRIG is invalid (TIM15)" +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 +# error "CONFIG_STM32_ADC2_TIMTRIG is invalid (TIM15)" # else -# error "CONFIG_STM32H5_ADC2_TIMTRIG is out of range (TIM15)" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range (TIM15)" # endif #endif @@ -524,5 +524,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2*/ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2*/ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h5/stm32_dbgmcu.h b/arch/arm/src/stm32h5/stm32_dbgmcu.h index 48d61c970b4..746fe869c2c 100644 --- a/arch/arm/src/stm32h5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32h5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_dbgmcu.h" #else # error "Unsupported STM32H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_dma.c b/arch/arm/src/stm32h5/stm32_dma.c index 3f53a85a8dd..67465bdb296 100644 --- a/arch/arm/src/stm32h5/stm32_dma.c +++ b/arch/arm/src/stm32h5/stm32_dma.c @@ -118,7 +118,7 @@ static int gpdma_dmainterrupt(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 static struct gpdma_ch_s g_chan[] = { { @@ -150,7 +150,7 @@ static struct gpdma_ch_s g_chan[] = .base = STM32_DMA1_BASE + CH_BASE_OFFSET(3) }, #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 { .dma_instance = 2, .channel = 0, @@ -703,7 +703,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) return (size_t)(br1 & GPDMA_CXBR1_BNDT_MASK); } -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /**************************************************************************** * Name: stm32_dmacapable * diff --git a/arch/arm/src/stm32h5/stm32_dma.h b/arch/arm/src/stm32h5/stm32_dma.h index 6c941507457..a9b336d6f81 100644 --- a/arch/arm/src/stm32h5/stm32_dma.h +++ b/arch/arm/src/stm32h5/stm32_dma.h @@ -39,9 +39,9 @@ # undef CONFIG_DEBUG_DMA_INFO #endif -#ifdef CONFIG_STM32H5_DMACAPABLE -# error "CONFIG_STM32H5_DMACAPABLE not yet implemented." -# undef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE +# error "CONFIG_STM32_DMACAPABLE not yet implemented." +# undef CONFIG_STM32_DMACAPABLE #endif /**************************************************************************** @@ -319,7 +319,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, struct stm32_gpdma_cfg_s *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h5/stm32_dts.c b/arch/arm/src/stm32h5/stm32_dts.c index 4719c59ce1c..b6d5067869f 100644 --- a/arch/arm/src/stm32h5/stm32_dts.c +++ b/arch/arm/src/stm32h5/stm32_dts.c @@ -59,7 +59,7 @@ static int stm32_dts_set_interval (struct sensor_lowerhalf_s *lower, struct file *filep, uint32_t *period_us); -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 static ssize_t stm32_dts_fetch (struct sensor_lowerhalf_s *lower, struct file *filep, char *buffer, size_t buflen); @@ -75,7 +75,7 @@ static int stm32_dts_isr (int irq, void *context, void *arg); * Pre-processor Definitions ****************************************************************************/ -#if CONFIG_STM32H5_DTS_TRIGGER != 0 +#if CONFIG_STM32_DTS_TRIGGER != 0 # error "Hardware triggers not implemented. Need LP Timers first." #endif @@ -112,7 +112,7 @@ static const struct sensor_ops_s g_dts_ops = .activate = stm32_dts_activate, .set_interval = stm32_dts_set_interval, .batch = NULL, -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 .fetch = stm32_dts_fetch, #else .fetch = NULL, @@ -230,7 +230,7 @@ static void dts_configure_cfgr1(void) { /* Compute PCLK prescaler <= 1MHz */ -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) uint32_t div = (STM32_PCLK1_FREQUENCY + 1000000 - 1) / 1000000; if (div > 127) @@ -245,13 +245,13 @@ static void dts_configure_cfgr1(void) uint32_t cfgr1 = DTS_CFGR1_TS1_EN - | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32H5_DTS_SMP_TIME) -#if !defined(CONFIG_STM32H5_DTS_REFCLK_LSE) + | DTS_CFGR1_TS1_SMP_TIME(CONFIG_STM32_DTS_SMP_TIME) +#if !defined(CONFIG_STM32_DTS_REFCLK_LSE) | DTS_CFGR1_HSREF_CLK_DIV_RATIO(div) #else | DTS_CFGR1_REFCLK_SEL #endif - | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32H5_DTS_TRIGGER); + | DTS_CFGR1_TS1_INTRIG(CONFIG_STM32_DTS_TRIGGER); putreg32(cfgr1, STM32_DTS_CFGR1); } @@ -295,7 +295,7 @@ static void dts_get_cfg_data(void) { uint32_t cfgr1 = getreg32(STM32_DTS_CFGR1); -#if defined(CONFIG_STM32H5_DTS_REFCLK_LSE) +#if defined(CONFIG_STM32_DTS_REFCLK_LSE) g_dts_cfg.lse = true; #else g_dts_cfg.lse = false; @@ -324,23 +324,23 @@ static void dts_configure_interrupts(struct sensor_lowerhalf_s *lower) { uint32_t itenr = 0; -#ifdef CONFIG_STM32H5_DTS_ITEN_ITEF +#ifdef CONFIG_STM32_DTS_ITEN_ITEF itenr |= DTS_ITENR_ITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITLF +#ifdef CONFIG_STM32_DTS_ITEN_ITLF itenr |= DTS_ITENR_ITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_ITEN_ITHF +#ifdef CONFIG_STM32_DTS_ITEN_ITHF itenr |= DTS_ITENR_ITHEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITEF +#ifdef CONFIG_STM32_DTS_AITEN_AITEF itenr |= DTS_ITENR_AITEEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITLF +#ifdef CONFIG_STM32_DTS_AITEN_AITLF itenr |= DTS_ITENR_AITLEN; #endif -#ifdef CONFIG_STM32H5_DTS_AITEN_AITHF +#ifdef CONFIG_STM32_DTS_AITEN_AITHF itenr |= DTS_ITENR_AITHEN; #endif @@ -392,7 +392,7 @@ static int stm32_dts_activate(struct sensor_lowerhalf_s *lower, return OK; } -#if CONFIG_STM32H5_DTS_TRIGGER == 0 +#if CONFIG_STM32_DTS_TRIGGER == 0 /**************************************************************************** * Name: stm32_dts_fetch * diff --git a/arch/arm/src/stm32h5/stm32_ethernet.c b/arch/arm/src/stm32h5/stm32_ethernet.c index 27a40cc3ec5..c8853e1aebb 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.c +++ b/arch/arm/src/stm32h5/stm32_ethernet.c @@ -67,11 +67,11 @@ #include /* STM32_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H5 Ethernet support is enabled in the configuration. */ -#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -102,76 +102,76 @@ # endif #endif -#ifndef CONFIG_STM32H5_PHYADDR -# error "CONFIG_STM32H5_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H5_MII) && !defined(CONFIG_STM32H5_RMII) -# warning "Neither CONFIG_STM32H5_MII nor CONFIG_STM32H5_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H5_MII) && defined(CONFIG_STM32H5_RMII) -# error "Both CONFIG_STM32H5_MII and CONFIG_STM32H5_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H5_MII -# if !defined(CONFIG_STM32H5_MII_MCO1) && !defined(CONFIG_STM32H5_MII_MCO2) && \ - !defined(CONFIG_STM32H5_MII_EXTCLK) -# warning "Neither CONFIG_STM32H5_MII_MCO1, CONFIG_STM32H5_MII_MCO2, nor CONFIG_STM32H5_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_MII_MCO1) && defined(CONFIG_STM32H5_MII_MCO2) -# error "Both CONFIG_STM32H5_MII_MCO1 and CONFIG_STM32H5_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_RMII -# if !defined(CONFIG_STM32H5_RMII_MCO1) && !defined(CONFIG_STM32H5_RMII_MCO2) && \ - !defined(CONFIG_STM32H5_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H5_RMII_MCO1, CONFIG_STM32H5_RMII_MCO2, nor CONFIG_STM32H5_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H5_RMII_MCO1) && defined(CONFIG_STM32H5_RMII_MCO2) -# error "Both CONFIG_STM32H5_RMII_MCO1 and CONFIG_STM32H5_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H5_AUTONEG -# ifndef CONFIG_STM32H5_PHYSR -# error "CONFIG_STM32H5_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H5_PHYSR_ALTMODE -# error "CONFIG_STM32H5_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10HD -# error "CONFIG_STM32H5_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100HD -# error "CONFIG_STM32H5_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_10FD -# error "CONFIG_STM32H5_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100FD -# error "CONFIG_STM32H5_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H5_PHYSR_SPEED -# error "CONFIG_STM32H5_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_100MBPS -# error "CONFIG_STM32H5_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_MODE -# error "CONFIG_STM32H5_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H5_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H5_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP -# warning "CONFIG_STM32H5_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif /* Add 4 to the configured buffer size to account for the 2 byte checksum @@ -200,16 +200,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H5_ETH_NRXDESC -# define CONFIG_STM32H5_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H5_ETH_NTXDESC -# define CONFIG_STM32H5_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H5_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -227,10 +227,10 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -241,7 +241,7 @@ */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H5_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -332,7 +332,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H5_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -347,7 +347,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -661,7 +661,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -733,7 +733,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -745,17 +745,17 @@ static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(void); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -785,7 +785,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -857,7 +857,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -884,7 +884,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1026,10 +1026,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC + - CONFIG_STM32H5_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1113,7 +1113,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL; #else txdesc->des3 = ETH_TDES3_RD_FD; @@ -1207,7 +1207,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * pseudo-header checksum will be computed. */ -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM txdesc->des3 = (ETH_TDES3_RD_OWN | ETH_TDES3_RD_LD | ETH_TDES3_RD_FD | ETH_TDES3_RD_CIC_ALL); #else @@ -1259,7 +1259,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H5_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1325,7 +1325,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1398,7 +1398,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H5_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1524,10 +1524,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC + - CONFIG_STM32H5_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1678,8 +1678,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H5_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H5_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -1724,7 +1724,7 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) ninfo("rxhead: %p rxcurr: %p segments: %d\n", priv->rxhead, priv->rxcurr, priv->segments); -#ifdef CONFIG_STM32H5_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* Check if any errors are reported in the frame. * If hardware checksum is enabled, check if: * - RDES1 is valid @@ -2796,7 +2796,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2832,7 +2832,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2885,7 +2885,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H5_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2918,7 +2918,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H5_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2926,7 +2926,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H5_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2962,7 +2962,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -2992,7 +2992,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H5_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3026,7 +3026,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H5_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3224,7 +3224,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * indication that check if the DM9161 PHY CHIP is not ready. */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_PHYID1, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3246,7 +3246,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * Register 16 */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, 16, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3280,7 +3280,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump() { uint16_t phyval; @@ -3289,7 +3289,7 @@ static void stm32_phyregdump() for (i = 0; i < 0x20; i++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, i, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3320,7 +3320,7 @@ static void stm32_phyregdump() static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3342,7 +3342,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_RESET, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET, MII_MCR_RESET); if (ret < 0) { @@ -3355,7 +3355,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) { up_mdelay(10); to -= 10; - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MCR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MCR, &phyval); } while (phyval & MII_MCR_RESET && to > 0); @@ -3369,7 +3369,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("Phy reset in %d ms\n", PHY_RESET_DELAY - to); } -#ifdef CONFIG_STM32H5_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(); #endif @@ -3385,12 +3385,12 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H5_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3412,7 +3412,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, MII_MCR_ANENABLE, + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE, MII_MCR_ANENABLE); if (ret < 0) { @@ -3424,7 +3424,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, MII_MSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3446,7 +3446,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ - ret = stm32_phyread(CONFIG_STM32H5_PHYADDR, CONFIG_STM32H5_PHYSR, &phyval); + ret = stm32_phyread(CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3455,38 +3455,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H5_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H5_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H5_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H5_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H5_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H5_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H5_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3499,13 +3499,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H5_PHYSR_MODE) == - CONFIG_STM32H5_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H5_PHYSR_SPEED) == CONFIG_STM32H5_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3514,14 +3514,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H5_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3532,10 +3532,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3563,7 +3563,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_MII +#ifdef CONFIG_STM32_MII #pragma message "If TrustZone is enabled, MII will fail to select." static inline void stm32_selectmii(void) { @@ -3590,7 +3590,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_RMII +#ifdef CONFIG_STM32_RMII #pragma message "If TrustZone is enabled, RMII will fail to select." static inline void stm32_selectrmii(void) { @@ -3623,17 +3623,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H5_MII) || defined(CONFIG_STM32H5_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H5_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H5_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3648,7 +3648,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3656,7 +3656,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3664,7 +3664,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3695,7 +3695,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H5_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3710,7 +3710,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H5_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3718,7 +3718,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3726,7 +3726,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H5_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3749,7 +3749,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H5_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4088,7 +4088,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4111,24 +4111,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H5_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H5_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H5_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H5_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H5_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4242,7 +4242,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4290,4 +4290,4 @@ void arm_netinitialize(void) } #endif -#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h5/stm32_ethernet.h b/arch/arm/src/stm32h5/stm32_ethernet.h index d337248893c..284d011894d 100644 --- a/arch/arm/src/stm32h5/stm32_ethernet.h +++ b/arch/arm/src/stm32h5/stm32_ethernet.h @@ -75,7 +75,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H5_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -90,7 +90,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 889a3af8149..639f0e7e1d9 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -75,7 +75,7 @@ # define STM32_CANRAM1_BASE (STM32_FDCAN_SRAM_BASE + 0x0000) # define STM32_CANRAM2_BASE (STM32_FDCAN_SRAM_BASE + 1*(FDCAN_MSGRAM_WORDS * 4)) -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 # define FDCAN1_STDFILTER_SIZE (28) # define FDCAN1_EXTFILTER_SIZE (8) # define FDCAN1_RXFIFO0_SIZE (3) @@ -90,7 +90,7 @@ # define FDCAN1_TXEVENTFIFO_WORDS (6) # define FDCAN1_TXFIFIOQ_WORDS (54) # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 # define FDCAN2_STDFILTER_SIZE (28) # define FDCAN2_EXTFILTER_SIZE (8) # define FDCAN2_RXFIFO0_SIZE (3) @@ -108,18 +108,18 @@ /* FDCAN1 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING -# define FDCAN1_NTSEG1 (CONFIG_STM32H5_FDCAN1_NTSEG1 - 1) -# define FDCAN1_NTSEG2 (CONFIG_STM32H5_FDCAN1_NTSEG2 - 1) +# define FDCAN1_NTSEG1 (CONFIG_STM32_FDCAN1_NTSEG1 - 1) +# define FDCAN1_NTSEG2 (CONFIG_STM32_FDCAN1_NTSEG2 - 1) # define FDCAN1_NBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_NTSEG1 + FDCAN1_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_BITRATE)) - 1) -# define FDCAN1_NSJW (CONFIG_STM32H5_FDCAN1_NSJW - 1) + CONFIG_STM32_FDCAN1_BITRATE)) - 1) +# define FDCAN1_NSJW (CONFIG_STM32_FDCAN1_NSJW - 1) # if FDCAN1_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN1 NTSEG1 @@ -134,13 +134,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN1_FD_BRS -# define FDCAN1_DTSEG1 (CONFIG_STM32H5_FDCAN1_DTSEG1 - 1) -# define FDCAN1_DTSEG2 (CONFIG_STM32H5_FDCAN1_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN1_FD_BRS +# define FDCAN1_DTSEG1 (CONFIG_STM32_FDCAN1_DTSEG1 - 1) +# define FDCAN1_DTSEG2 (CONFIG_STM32_FDCAN1_DTSEG2 - 1) # define FDCAN1_DBRP ((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN1_DTSEG1 + FDCAN1_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN1_DBITRATE)) - 1) -# define FDCAN1_DSJW (CONFIG_STM32H5_FDCAN1_DSJW - 1) + CONFIG_STM32_FDCAN1_DBITRATE)) - 1) +# define FDCAN1_DSJW (CONFIG_STM32_FDCAN1_DSJW - 1) # else # define FDCAN1_DTSEG1 1 # define FDCAN1_DTSEG2 1 @@ -174,22 +174,22 @@ # define FDCAN1_TXFIFOQ_INDEX (FDCAN1_TXEVENTFIFO_INDEX + FDCAN1_TXEVENTFIFO_WORDS) # define FDCAN1_MSGRAM_WORDS (FDCAN1_TXFIFOQ_INDEX + FDCAN1_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ /* FDCAN2 Configuration *****************************************************/ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* Bit timing */ -# ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +# ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING -# define FDCAN2_NTSEG1 (CONFIG_STM32H5_FDCAN2_NTSEG1 - 1) -# define FDCAN2_NTSEG2 (CONFIG_STM32H5_FDCAN2_NTSEG2 - 1) +# define FDCAN2_NTSEG1 (CONFIG_STM32_FDCAN2_NTSEG1 - 1) +# define FDCAN2_NTSEG2 (CONFIG_STM32_FDCAN2_NTSEG2 - 1) # define FDCAN2_NBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_NTSEG1 + FDCAN2_NTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_BITRATE)) - 1)) -# define FDCAN2_NSJW (CONFIG_STM32H5_FDCAN2_NSJW - 1) + CONFIG_STM32_FDCAN2_BITRATE)) - 1)) +# define FDCAN2_NSJW (CONFIG_STM32_FDCAN2_NSJW - 1) # if FDCAN2_NTSEG1 > FDCAN_NBTP_NTSEG1_MAX # error Invalid FDCAN2 NTSEG1 @@ -204,13 +204,13 @@ # error Invalid FDCAN1 NBRP # endif -# ifdef CONFIG_STM32H5_FDCAN2_FD_BRS -# define FDCAN2_DTSEG1 (CONFIG_STM32H5_FDCAN2_DTSEG1 - 1) -# define FDCAN2_DTSEG2 (CONFIG_STM32H5_FDCAN2_DTSEG2 - 1) +# ifdef CONFIG_STM32_FDCAN2_FD_BRS +# define FDCAN2_DTSEG1 (CONFIG_STM32_FDCAN2_DTSEG1 - 1) +# define FDCAN2_DTSEG2 (CONFIG_STM32_FDCAN2_DTSEG2 - 1) # define FDCAN2_DBRP (((STM32_FDCANCLK_FREQUENCY / \ ((FDCAN2_DTSEG1 + FDCAN2_DTSEG2 + 3) * \ - CONFIG_STM32H5_FDCAN2_DBITRATE)) - 1)) -# define FDCAN2_DSJW (CONFIG_STM32H5_FDCAN2_DSJW - 1) + CONFIG_STM32_FDCAN2_DBITRATE)) - 1)) +# define FDCAN2_DSJW (CONFIG_STM32_FDCAN2_DSJW - 1) # else # define FDCAN2_DTSEG1 1 # define FDCAN2_DTSEG2 1 @@ -245,7 +245,7 @@ # define FDCAN2_TXFIFOQ_INDEX (FDCAN2_TXEVENTFIFO_INDEX + FDCAN2_TXEVENTFIFO_WORDS) # define FDCAN2_MSGRAM_WORDS (FDCAN2_TXFIFOQ_INDEX + FDCAN2_TXFIFIOQ_WORDS) -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /* Interrupts ***************************************************************/ @@ -325,12 +325,12 @@ /* Debug configurations that may be enabled just for testing FDCAN */ #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32H5_FDCAN_REGDEBUG +# undef CONFIG_STM32_FDCAN_REGDEBUG #endif #undef STM32_FDCAN_LOOPBACK -#if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \ - defined(CONFIG_STM32H5_FDCAN2_LOOPBACK) +#if defined(CONFIG_STM32_FDCAN1_LOOPBACK) || \ + defined(CONFIG_STM32_FDCAN2_LOOPBACK) # define STM32_FDCAN_LOOPBACK 1 #endif @@ -435,7 +435,7 @@ struct stm32_fdcan_s #endif uint32_t stdfilters[4]; /* Standard filter bit allocator. 4*32=128 */ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG uintptr_t regaddr; /* Last register address read */ uint32_t regval; /* Last value read from the register */ unsigned int count; /* Number of times that the value was read */ @@ -460,7 +460,7 @@ struct fdcan_bitseg static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset); static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval); -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg); static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, @@ -537,7 +537,7 @@ static const struct can_ops_s g_fdcanops = .co_txempty = fdcan_txempty, }; -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* Message RAM allocation */ /* Constant configuration */ @@ -547,11 +547,11 @@ static const struct stm32_config_s g_fdcan1const = .rxpinset = GPIO_FDCAN1_RX, .txpinset = GPIO_FDCAN1_TX, .base = STM32_FDCAN1_BASE, - .baud = CONFIG_STM32H5_FDCAN1_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN1_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN1_DBITRATE, + .baud = CONFIG_STM32_FDCAN1_BITRATE, +#if defined(CONFIG_STM32_FDCAN1_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN1_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN1_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN1_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN1_NTSEG2) | @@ -564,14 +564,14 @@ static const struct stm32_config_s g_fdcan1const = .port = 1, .irq0 = STM32_IRQ_FDCAN1_IT0, .irq1 = STM32_IRQ_FDCAN1_IT1, -#if defined(CONFIG_STM32H5_FDCAN1_CLASSIC) +#if defined(CONFIG_STM32_FDCAN1_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN1_FD) +#elif defined(CONFIG_STM32_FDCAN1_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN1_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN1_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -587,7 +587,7 @@ static const struct stm32_config_s g_fdcan1const = .txeventesize = (FDCAN1_TXEVENTFIFO_WORDS / FDCAN1_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN1_TXFIFIOQ_WORDS / FDCAN1_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN1_LOOPBACK +#ifdef CONFIG_STM32_FDCAN1_LOOPBACK .loopback = true, #endif @@ -609,9 +609,9 @@ static const struct stm32_config_s g_fdcan1const = static struct stm32_fdcan_s g_fdcan1priv; static struct can_dev_s g_fdcan1dev; -#endif /* CONFIG_STM32H5_FDCAN1 */ +#endif /* CONFIG_STM32_FDCAN1 */ -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 /* FDCAN2 message RAM allocation */ /* FDCAN2 constant configuration */ @@ -621,11 +621,11 @@ static const struct stm32_config_s g_fdcan2const = .rxpinset = GPIO_FDCAN2_RX, .txpinset = GPIO_FDCAN2_TX, .base = STM32_FDCAN2_BASE, - .baud = CONFIG_STM32H5_FDCAN2_BITRATE, -#if defined(CONFIG_STM32H5_FDCAN2_FD_BRS) - .data_baud = CONFIG_STM32H5_FDCAN2_DBITRATE, + .baud = CONFIG_STM32_FDCAN2_BITRATE, +#if defined(CONFIG_STM32_FDCAN2_FD_BRS) + .data_baud = CONFIG_STM32_FDCAN2_DBITRATE, #endif -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING .nbtp = FDCAN_NBTP_NBRP(FDCAN2_NBRP) | FDCAN_NBTP_NTSEG1(FDCAN2_NTSEG1) | FDCAN_NBTP_NTSEG2(FDCAN2_NTSEG2) | @@ -638,14 +638,14 @@ static const struct stm32_config_s g_fdcan2const = .port = 2, .irq0 = STM32_IRQ_FDCAN2_IT0, .irq1 = STM32_IRQ_FDCAN2_IT1, -#if defined(CONFIG_STM32H5_FDCAN2_CLASSIC) +#if defined(CONFIG_STM32_FDCAN2_CLASSIC) .mode = FDCAN_CLASSIC_MODE, -#elif defined(CONFIG_STM32H5_FDCAN2_FD) +#elif defined(CONFIG_STM32_FDCAN2_FD) .mode = FDCAN_FD_MODE, #else .mode = FDCAN_FD_BRS_MODE, #endif -#if defined(CONFIG_STM32H5_FDCAN2_NONISO_FORMAT) +#if defined(CONFIG_STM32_FDCAN2_NONISO_FORMAT) .format = FDCAN_NONISO_BOSCH_V1_FORMAT, #else .format = FDCAN_ISO11898_1_FORMAT, @@ -661,7 +661,7 @@ static const struct stm32_config_s g_fdcan2const = .txeventesize = (FDCAN2_TXEVENTFIFO_WORDS / FDCAN2_TXEVENTFIFO_SIZE), .txbufferesize = (FDCAN2_TXFIFIOQ_WORDS / FDCAN2_TXFIFIOQ_SIZE), -#ifdef CONFIG_STM32H5_FDCAN2_LOOPBACK +#ifdef CONFIG_STM32_FDCAN2_LOOPBACK .loopback = true, #endif @@ -683,7 +683,7 @@ static const struct stm32_config_s g_fdcan2const = static struct stm32_fdcan_s g_fdcan2priv; static struct can_dev_s g_fdcan2dev; -#endif /* CONFIG_STM32H5_FDCAN2 */ +#endif /* CONFIG_STM32_FDCAN2 */ /**************************************************************************** * Private Functions @@ -703,7 +703,7 @@ static struct can_dev_s g_fdcan2dev; * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) { const struct stm32_config_s *config = priv->config; @@ -783,7 +783,7 @@ static uint32_t fdcan_getreg(struct stm32_fdcan_s *priv, int offset) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, uint32_t regval) { @@ -823,7 +823,7 @@ static void fdcan_putreg(struct stm32_fdcan_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -869,7 +869,7 @@ static void fdcan_dumpregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -912,7 +912,7 @@ static void fdcan_dumprxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, const char *msg) { @@ -961,7 +961,7 @@ static void fdcan_dumptxregs(struct stm32_fdcan_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpramlayout(struct stm32_fdcan_s *priv) { const struct stm32_config_s *config = priv->config; @@ -2406,7 +2406,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) { struct stm32_fdcan_s *priv = dev->cd_priv; uint32_t regval = 0; -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE int tffl = 0; bool empty = false; #endif @@ -2426,7 +2426,7 @@ static bool fdcan_txempty(struct can_dev_s *dev) /* Tx FIFO Free Level */ -#ifndef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifndef CONFIG_STM32_FDCAN_QUEUE_MODE tffl = (regval & FDCAN_TXFQS_TFFL_MASK) >> FDCAN_TXFQS_TFFL_SHIFT; empty = (tffl >= priv->config->ntxfifoq); return empty; @@ -3275,7 +3275,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv) /* Enable FIFO/Queue mode */ regval = fdcan_getreg(priv, STM32_FDCAN_TXBC_OFFSET); -#ifdef CONFIG_STM32H5_FDCAN_QUEUE_MODE +#ifdef CONFIG_STM32_FDCAN_QUEUE_MODE regval |= FDCAN_TXBC_TFQM; #else regval &= ~FDCAN_TXBC_TFQM; @@ -3461,7 +3461,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H5_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -3506,7 +3506,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) /* Select FDCAN peripheral to be initialized */ -#ifdef CONFIG_STM32H5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 if (port == FDCAN1) { /* Select the FDCAN1 device structure */ @@ -3514,13 +3514,13 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan1dev; priv = &g_fdcan1priv; config = &g_fdcan1const; -#ifndef CONFIG_STM32H5_FDCAN1_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN1_AUTO_BIT_TIMING auto_bit_timing = false; #endif } else #endif -#ifdef CONFIG_STM32H5_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 if (port == FDCAN2) { /* Select the FDCAN2 device structure */ @@ -3528,7 +3528,7 @@ struct can_dev_s *stm32_fdcaninitialize(int port) dev = &g_fdcan2dev; priv = &g_fdcan2priv; config = &g_fdcan2const; -#ifndef CONFIG_STM32H5_FDCAN2_AUTO_BIT_TIMING +#ifndef CONFIG_STM32_FDCAN2_AUTO_BIT_TIMING auto_bit_timing = false; #endif } diff --git a/arch/arm/src/stm32h5/stm32_fdcan.h b/arch/arm/src/stm32h5/stm32_fdcan.h index 5f770fc7a81..04207ad7985 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.h +++ b/arch/arm/src/stm32h5/stm32_fdcan.h @@ -64,7 +64,7 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /**************************************************************************** * Name: stm32_fdcaninitialize @@ -83,7 +83,7 @@ extern "C" struct can_dev_s *stm32_fdcaninitialize(int port); #endif -#ifdef CONFIG_STM32H5_FDCAN_SOCKET +#ifdef CONFIG_STM32_FDCAN_SOCKET /**************************************************************************** * Name: stm32_fdcansockinitialize diff --git a/arch/arm/src/stm32h5/stm32_flash.c b/arch/arm/src/stm32h5/stm32_flash.c index e9325741b66..feac762f165 100644 --- a/arch/arm/src/stm32h5/stm32_flash.c +++ b/arch/arm/src/stm32h5/stm32_flash.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H5_STM32H563XX) +#if defined(CONFIG_STM32_STM32H563XX) # include "stm32h563xx_flash.c" #else # error "Unsupported STM32 H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_gpio.h b/arch/arm/src/stm32h5/stm32_gpio.h index ab323a048ab..ec2caefa305 100644 --- a/arch/arm/src/stm32h5/stm32_gpio.h +++ b/arch/arm/src/stm32h5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32H5 chip" diff --git a/arch/arm/src/stm32h5/stm32_hsi48.c b/arch/arm/src/stm32h5/stm32_hsi48.c index 1cf72a2e56f..2825f722e9e 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.c +++ b/arch/arm/src/stm32h5/stm32_hsi48.c @@ -37,7 +37,7 @@ * Public Functions ****************************************************************************/ -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Name: stm32_enable_hsi48 * @@ -168,4 +168,4 @@ void stm32_disable_hsi48(void) putreg32(regval, STM32_CRS_CR); } -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ diff --git a/arch/arm/src/stm32h5/stm32_hsi48.h b/arch/arm/src/stm32h5/stm32_hsi48.h index a27e5458320..290bd4713f1 100644 --- a/arch/arm/src/stm32h5/stm32_hsi48.h +++ b/arch/arm/src/stm32h5/stm32_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32H5_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32H5_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.c b/arch/arm/src/stm32h5/stm32_i2c.c index 7b43fa8ed93..6ce61a550f4 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.c +++ b/arch/arm/src/stm32h5/stm32_i2c.c @@ -162,24 +162,24 @@ * * and one or more interfaces: * - * CONFIG_STM32H5_I2C1 - * CONFIG_STM32H5_I2C2 - * CONFIG_STM32H5_I2C3 - * CONFIG_STM32H5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -227,8 +227,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H5_I2C1) || defined(CONFIG_STM32H5_I2C2) || \ - defined(CONFIG_STM32H5_I2C3) || defined(CONFIG_STM32H5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -246,25 +246,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H5_I2CTIMEOSEC) && !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 -# define CONFIG_STM32H5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H5_I2CTIMEOSEC) -# define CONFIG_STM32H5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H5_I2CTIMEOMS) -# define CONFIG_STM32H5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H5_I2CTIMEOTICKS -# define CONFIG_STM32H5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -443,9 +443,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -485,7 +485,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -523,7 +523,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -561,7 +561,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -599,7 +599,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -731,7 +731,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -748,7 +748,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -804,12 +804,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -847,10 +847,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -988,10 +988,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -1283,82 +1283,82 @@ static void stm32_i2c_setclock(struct stm32_i2c_priv_s *priv, switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C1_ANFOFF; - dnf = CONFIG_STM32H5_I2C1_DNF; -# ifdef CONFIG_STM32H5_I2C1_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C1_RISE; - tf_max = CONFIG_STM32H5_I2C1_FALL; + anfoff = CONFIG_STM32_I2C1_ANFOFF; + dnf = CONFIG_STM32_I2C1_DNF; +# ifdef CONFIG_STM32_I2C1_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C1_RISE; + tf_max = CONFIG_STM32_I2C1_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) i2c_ker_ck = STM32_PCLK1_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C2_ANFOFF; - dnf = CONFIG_STM32H5_I2C2_DNF; -# ifdef CONFIG_STM32H5_I2C2_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C2_RISE; - tf_max = CONFIG_STM32H5_I2C2_FALL; + anfoff = CONFIG_STM32_I2C2_ANFOFF; + dnf = CONFIG_STM32_I2C2_DNF; +# ifdef CONFIG_STM32_I2C2_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C2_RISE; + tf_max = CONFIG_STM32_I2C2_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C3_ANFOFF; - dnf = CONFIG_STM32H5_I2C3_DNF; -# ifdef CONFIG_STM32H5_I2C3_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C3_RISE; - tf_max = CONFIG_STM32H5_I2C3_FALL; + anfoff = CONFIG_STM32_I2C3_ANFOFF; + dnf = CONFIG_STM32_I2C3_DNF; +# ifdef CONFIG_STM32_I2C3_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C3_RISE; + tf_max = CONFIG_STM32_I2C3_FALL; rf_override = true; # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) i2c_ker_ck = STM32_HSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) i2c_ker_ck = STM32_CSI_FREQUENCY; -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) i2c_ker_ck = STM32_PCLK3_FREQUENCY; # else i2c_ker_ck = STM32_PLL3R_FREQUENCY; # endif - anfoff = CONFIG_STM32H5_I2C4_ANFOFF; - dnf = CONFIG_STM32H5_I2C4_DNF; -# ifdef CONFIG_STM32H5_I2C4_RF_OVERRIDE - tr_max = CONFIG_STM32H5_I2C4_RISE; - tf_max = CONFIG_STM32H5_I2C4_FALL; + anfoff = CONFIG_STM32_I2C4_ANFOFF; + dnf = CONFIG_STM32_I2C4_DNF; +# ifdef CONFIG_STM32_I2C4_RF_OVERRIDE + tr_max = CONFIG_STM32_I2C4_RISE; + tf_max = CONFIG_STM32_I2C4_FALL; rf_override = true; # endif break; @@ -2387,17 +2387,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) switch (priv->config->base) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case STM32_I2C1_BASE: -# if defined(CONFIG_STM32H5_I2C1_CLK_HSI) +# if defined(CONFIG_STM32_I2C1_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_CSI) +# elif defined(CONFIG_STM32_I2C1_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C1_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C1_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C1SEL_MASK, RCC_CCIPR4_I2C1SEL_RCCPCLK1); @@ -2408,17 +2408,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case STM32_I2C2_BASE: -# if defined(CONFIG_STM32H5_I2C2_CLK_HSI) +# if defined(CONFIG_STM32_I2C2_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_CSI) +# elif defined(CONFIG_STM32_I2C2_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C2_CLK_PCLK1) +# elif defined(CONFIG_STM32_I2C2_CLK_PCLK1) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C2SEL_MASK, RCC_CCIPR4_I2C2SEL_PCLK1); @@ -2429,17 +2429,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case STM32_I2C3_BASE: -# if defined(CONFIG_STM32H5_I2C3_CLK_HSI) +# if defined(CONFIG_STM32_I2C3_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_CSI) +# elif defined(CONFIG_STM32_I2C3_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C3_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C3_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C3SEL_MASK, RCC_CCIPR4_I2C3SEL_PCLK3); @@ -2450,17 +2450,17 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) # endif break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case STM32_I2C4_BASE: -# if defined(CONFIG_STM32H5_I2C4_CLK_HSI) +# if defined(CONFIG_STM32_I2C4_CLK_HSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_HSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_CSI) +# elif defined(CONFIG_STM32_I2C4_CLK_CSI) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_CSIKERCK); -# elif defined(CONFIG_STM32H5_I2C4_CLK_PCLK3) +# elif defined(CONFIG_STM32_I2C4_CLK_PCLK3) modifyreg32(STM32_RCC_CCIPR4, RCC_CCIPR4_I2C4SEL_MASK, RCC_CCIPR4_I2C4SEL_PCLK3); @@ -3016,22 +3016,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3117,5 +3117,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H5_I2C1 || CONFIG_STM32H5_I2C2 || \ - * CONFIG_STM32H5_I2C3 || CONFIG_STM32H5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h5/stm32_i2c.h b/arch/arm/src/stm32h5/stm32_i2c.h index ceb6a7091cd..87c3f6a1b02 100644 --- a/arch/arm/src/stm32h5/stm32_i2c.h +++ b/arch/arm/src/stm32h5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H5_I2C_DYNTIMEO -# if CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H5_I2C_DYNTIMEO because of CONFIG_STM32H5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h5/stm32_icache.c b/arch/arm/src/stm32h5/stm32_icache.c index 8566734a1ae..2aa578d6723 100644 --- a/arch/arm/src/stm32h5/stm32_icache.c +++ b/arch/arm/src/stm32h5/stm32_icache.c @@ -40,8 +40,8 @@ * Pre-processor Definitions ****************************************************************************/ -#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\ - defined(CONFIG_STM32H5_ICACHE_ERR_INT)) +#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32_ICACHE_INV_INT) ||\ + defined(CONFIG_STM32_ICACHE_ERR_INT)) /**************************************************************************** * Private Types @@ -82,51 +82,51 @@ static struct stm32_icache_s icache1 = .lock = SP_UNLOCKED, }; -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 static struct stm32_icache_region region0 = { .num = 0, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION0_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION0_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION0_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION0_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION0_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION0_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION0_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION0_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION0_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION0_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 static struct stm32_icache_region region1 = { .num = 1, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION1_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION1_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION1_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION1_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION1_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION1_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION1_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION1_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION1_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION1_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 static struct stm32_icache_region region2 = { .num = 2, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION2_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION2_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION2_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION2_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION2_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION2_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION2_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION2_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION2_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION2_HBURST, }; #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 static struct stm32_icache_region region3 = { .num = 3, - .baseaddr = CONFIG_STM32H5_ICACHE_REGION3_BADDR, - .rsize = CONFIG_STM32H5_ICACHE_REGION3_RSIZE, - .remapaddr = CONFIG_STM32H5_ICACHE_REGION3_REMAPADDR, - .mstsel = CONFIG_STM32H5_ICACHE_REGION3_MSTSEL, - .hburst = CONFIG_STM32H5_ICACHE_REGION3_HBURST, + .baseaddr = CONFIG_STM32_ICACHE_REGION3_BADDR, + .rsize = CONFIG_STM32_ICACHE_REGION3_RSIZE, + .remapaddr = CONFIG_STM32_ICACHE_REGION3_REMAPADDR, + .mstsel = CONFIG_STM32_ICACHE_REGION3_MSTSEL, + .hburst = CONFIG_STM32_ICACHE_REGION3_HBURST, }; #endif @@ -235,7 +235,7 @@ void stm32_icache_initialize(void) /* Set associativity */ -#ifdef CONFIG_STM32H5_ICACHE_DIRECT +#ifdef CONFIG_STM32_ICACHE_DIRECT regval = getreg32(STM32_ICACHE_CR); regval &= ~(ICACHE_CR_WAYSEL); putreg32(regval, STM32_ICACHE_CR); @@ -246,23 +246,23 @@ void stm32_icache_initialize(void) * Reset Monitors on Initialization */ -#ifdef CONFIG_STM32H5_ICACHE_MONITOR_EN +#ifdef CONFIG_STM32_ICACHE_MONITOR_EN stm32_icache_enable_monitors(); stm32_icache_reset_monitors(); #endif /* Set up region configuration registers */ -#ifdef CONFIG_STM32H5_ICACHE_REGION0 +#ifdef CONFIG_STM32_ICACHE_REGION0 stm32_icache_setup_region(region0); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION1 +#ifdef CONFIG_STM32_ICACHE_REGION1 stm32_icache_setup_region(region1); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION2 +#ifdef CONFIG_STM32_ICACHE_REGION2 stm32_icache_setup_region(region2); #endif -#ifdef CONFIG_STM32H5_ICACHE_REGION3 +#ifdef CONFIG_STM32_ICACHE_REGION3 stm32_icache_setup_region(region3); #endif @@ -278,10 +278,10 @@ void stm32_icache_initialize(void) if (ret == OK) { regval = 0; -# ifdef CONFIG_STM32H5_ICACHE_INV_INT +# ifdef CONFIG_STM32_ICACHE_INV_INT regval |= ICACHE_IER_BSYENDIE; # endif -# ifdef CONFIG_STM32H5_ICACHE_ERR_INT +# ifdef CONFIG_STM32_ICACHE_ERR_INT regval |= ICACHE_IER_ERRIE; # endif stm32_icache_set_ier(regval); @@ -358,7 +358,7 @@ void stm32_invalidate_icache(void) regval |= ICACHE_CR_CACHEINV; putreg32(regval, STM32_ICACHE_CR); -#if defined(CONFIG_STM32H5_ICACHE_INV_INT) +#if defined(CONFIG_STM32_ICACHE_INV_INT) stm32_icache_invf_interrupt(); #else stm32_icache_invf_poll(); diff --git a/arch/arm/src/stm32h5/stm32_idle.c b/arch/arm/src/stm32h5/stm32_idle.c index fdde8d81b1f..5cc08c4759b 100644 --- a/arch/arm/src/stm32h5/stm32_idle.c +++ b/arch/arm/src/stm32h5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32h5/stm32_lse.c b/arch/arm/src/stm32h5/stm32_lse.c index d5c0db5e0f1..7bc65aa3a06 100644 --- a/arch/arm/src/stm32h5/stm32_lse.c +++ b/arch/arm/src/stm32h5/stm32_lse.c @@ -41,9 +41,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -52,7 +52,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -79,7 +79,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -105,19 +105,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -145,7 +145,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -154,7 +154,7 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives) / sizeof(drives[0])); #endif -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32h5/stm32_pulsecount.c b/arch/arm/src/stm32h5/stm32_pulsecount.c index 7bae9cc8cb7..d002444cd7a 100644 --- a/arch/arm/src/stm32h5/stm32_pulsecount.c +++ b/arch/arm/src/stm32h5/stm32_pulsecount.c @@ -182,10 +182,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -212,107 +212,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H5_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H5_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1_UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H5_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H5_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H5_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8_UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -323,7 +323,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -331,7 +331,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1321,21 +1321,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H5_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H5_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1408,7 +1408,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1417,7 +1417,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1600,7 +1600,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1609,7 +1609,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1761,7 +1761,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1771,7 +1771,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h5/stm32_pwm.c b/arch/arm/src/stm32h5/stm32_pwm.c index eadb42917b1..65ce199ce87 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.c +++ b/arch/arm/src/stm32h5/stm32_pwm.c @@ -159,9 +159,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined(CONFIG_STM32H5_TIM8_PWM) || \ - defined(CONFIG_STM32H5_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ - defined(CONFIG_STM32H5_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -169,7 +169,7 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H5_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -241,7 +241,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -314,10 +314,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -354,7 +354,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -377,16 +377,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -401,114 +401,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1POL, - .idle = CONFIG_STM32H5_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH1NPOL, - .idle = CONFIG_STM32H5_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM1_CH2MODE, -#ifdef CONFIG_STM32H5_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2POL, - .idle = CONFIG_STM32H5_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH2NPOL, - .idle = CONFIG_STM32H5_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM1_CH3MODE, -#ifdef CONFIG_STM32H5_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3POL, - .idle = CONFIG_STM32H5_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH3NPOL, - .idle = CONFIG_STM32H5_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM1_CH4MODE, -#ifdef CONFIG_STM32H5_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH4POL, - .idle = CONFIG_STM32H5_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM1_CH5MODE, -#ifdef CONFIG_STM32H5_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH5POL, - .idle = CONFIG_STM32H5_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM1_CH6MODE, -#ifdef CONFIG_STM32H5_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM1_CH6POL, - .idle = CONFIG_STM32H5_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -519,18 +519,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H5_TIM1_MODE, - .lock = CONFIG_STM32H5_TIM1_LOCK, - .t_dts = CONFIG_STM32H5_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -538,72 +538,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H5_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM2_CH1MODE, -#ifdef CONFIG_STM32H5_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH1POL, - .idle = CONFIG_STM32H5_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM2_CH2MODE, -#ifdef CONFIG_STM32H5_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH2POL, - .idle = CONFIG_STM32H5_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM2_CH3MODE, -#ifdef CONFIG_STM32H5_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH3POL, - .idle = CONFIG_STM32H5_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM2_CH4MODE, -#ifdef CONFIG_STM32H5_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM2_CH4POL, - .idle = CONFIG_STM32H5_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -615,14 +615,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H5_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -634,72 +634,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H5_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM3_CH1MODE, -#ifdef CONFIG_STM32H5_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH1POL, - .idle = CONFIG_STM32H5_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM3_CH2MODE, -#ifdef CONFIG_STM32H5_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH2POL, - .idle = CONFIG_STM32H5_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM3_CH3MODE, -#ifdef CONFIG_STM32H5_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH3POL, - .idle = CONFIG_STM32H5_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM3_CH4MODE, -#ifdef CONFIG_STM32H5_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM3_CH4POL, - .idle = CONFIG_STM32H5_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -711,14 +711,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H5_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -730,72 +730,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H5_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM4_CH1MODE, -#ifdef CONFIG_STM32H5_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH1POL, - .idle = CONFIG_STM32H5_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM4_CH2MODE, -#ifdef CONFIG_STM32H5_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH2POL, - .idle = CONFIG_STM32H5_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM4_CH3MODE, -#ifdef CONFIG_STM32H5_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH3POL, - .idle = CONFIG_STM32H5_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM4_CH4MODE, -#ifdef CONFIG_STM32H5_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM4_CH4POL, - .idle = CONFIG_STM32H5_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -807,14 +807,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H5_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -826,71 +826,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H5_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM5_CH1MODE, -#ifdef CONFIG_STM32H5_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH1POL, - .idle = CONFIG_STM32H5_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM5_CH2MODE, -#ifdef CONFIG_STM32H5_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH2POL, - .idle = CONFIG_STM32H5_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM5_CH3MODE, -#ifdef CONFIG_STM32H5_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH3POL, - .idle = CONFIG_STM32H5_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM5_CH4MODE, -#ifdef CONFIG_STM32H5_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM5_CH4POL, - .idle = CONFIG_STM32H5_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -901,14 +901,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H5_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -920,18 +920,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H5_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -946,114 +946,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1POL, - .idle = CONFIG_STM32H5_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH1NPOL, - .idle = CONFIG_STM32H5_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM8_CH2MODE, -#ifdef CONFIG_STM32H5_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2POL, - .idle = CONFIG_STM32H5_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH2NPOL, - .idle = CONFIG_STM32H5_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H5_TIM8_CH3MODE, -#ifdef CONFIG_STM32H5_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3POL, - .idle = CONFIG_STM32H5_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH3NPOL, - .idle = CONFIG_STM32H5_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H5_TIM8_CH4MODE, -#ifdef CONFIG_STM32H5_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH4POL, - .idle = CONFIG_STM32H5_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H5_TIM8_CH5MODE, -#ifdef CONFIG_STM32H5_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH5POL, - .idle = CONFIG_STM32H5_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H5_TIM8_CH6MODE, -#ifdef CONFIG_STM32H5_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM8_CH6POL, - .idle = CONFIG_STM32H5_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1064,18 +1064,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H5_TIM8_MODE, - .lock = CONFIG_STM32H5_TIM8_LOCK, - .t_dts = CONFIG_STM32H5_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1083,40 +1083,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H5_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM12_CH1MODE, -#ifdef CONFIG_STM32H5_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH1POL, - .idle = CONFIG_STM32H5_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM12_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM12_CH2POL, - .idle = CONFIG_STM32H5_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1128,7 +1128,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1147,24 +1147,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H5_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM13_CH1MODE, -#ifdef CONFIG_STM32H5_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM13_CH1POL, - .idle = CONFIG_STM32H5_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1176,7 +1176,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1195,24 +1195,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H5_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM14_CH1MODE, -#ifdef CONFIG_STM32H5_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM14_CH1POL, - .idle = CONFIG_STM32H5_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1224,7 +1224,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1243,18 +1243,18 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H5_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1265,36 +1265,36 @@ static struct stm32_pwmchan_s g_pwm15channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1POL, - .idle = CONFIG_STM32H5_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH1NPOL, - .idle = CONFIG_STM32H5_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H5_TIM15_CH2MODE, -#ifdef CONFIG_STM32H5_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM15_CH2POL, - .idle = CONFIG_STM32H5_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1306,7 +1306,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1314,10 +1314,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM15_LOCK, - .t_dts = CONFIG_STM32H5_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1325,18 +1325,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H5_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1347,16 +1347,16 @@ static struct stm32_pwmchan_s g_pwm16channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM16_CH1POL, - .idle = CONFIG_STM32H5_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, @@ -1372,7 +1372,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1380,10 +1380,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM16_LOCK, - .t_dts = CONFIG_STM32H5_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1391,18 +1391,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H5_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H5_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1413,16 +1413,16 @@ static struct stm32_pwmchan_s g_pwm17channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H5_TIM17_CH1POL, - .idle = CONFIG_STM32H5_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, @@ -1438,7 +1438,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1446,10 +1446,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H5_TIM17_LOCK, - .t_dts = CONFIG_STM32H5_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H5_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1457,7 +1457,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H5_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1792,7 +1792,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1849,7 +1849,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2577,7 +2577,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H5_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3130,7 +3130,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3139,7 +3139,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3148,7 +3148,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3157,7 +3157,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3166,7 +3166,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3175,7 +3175,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3184,7 +3184,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3193,7 +3193,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3202,7 +3202,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3211,7 +3211,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3220,7 +3220,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3229,7 +3229,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3527,7 +3527,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3536,7 +3536,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3545,7 +3545,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3554,7 +3554,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3563,7 +3563,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3572,7 +3572,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3581,7 +3581,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3590,7 +3590,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3599,7 +3599,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3608,7 +3608,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3617,7 +3617,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3626,7 +3626,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3743,7 +3743,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3754,7 +3754,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3762,7 +3762,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3770,7 +3770,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3778,7 +3778,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3786,7 +3786,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3797,7 +3797,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3805,7 +3805,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3813,7 +3813,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3821,7 +3821,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3829,7 +3829,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3837,7 +3837,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H5_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; diff --git a/arch/arm/src/stm32h5/stm32_pwm.h b/arch/arm/src/stm32h5/stm32_pwm.h index 149de56fec9..bfbe59529fa 100644 --- a/arch/arm/src/stm32h5/stm32_pwm.h +++ b/arch/arm/src/stm32h5/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -57,41 +57,41 @@ * pulsed output signal generation. */ -#ifndef CONFIG_STM32H5_TIM1 -# undef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H5_TIM2 -# undef CONFIG_STM32H5_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H5_TIM3 -# undef CONFIG_STM32H5_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H5_TIM4 -# undef CONFIG_STM32H5_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H5_TIM5 -# undef CONFIG_STM32H5_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H5_TIM8 -# undef CONFIG_STM32H5_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H5_TIM12 -# undef CONFIG_STM32H5_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H5_TIM13 -# undef CONFIG_STM32H5_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H5_TIM14 -# undef CONFIG_STM32H5_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H5_TIM15 -# undef CONFIG_STM32H5_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H5_TIM16 -# undef CONFIG_STM32H5_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H5_TIM17 -# undef CONFIG_STM32H5_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -103,38 +103,38 @@ /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H5_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H5_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H5_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H5_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,59 +269,59 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H5_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H5_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H5_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H5_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H5_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H5_TIM1_PWM -# if !defined(CONFIG_STM32H5_TIM1_CHANNEL) -# error "CONFIG_STM32H5_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM1_CHANNEL == 1 -# define CONFIG_STM32H5_TIM1_CHANNEL1 1 -# define CONFIG_STM32H5_TIM1_CH1MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 2 -# define CONFIG_STM32H5_TIM1_CHANNEL2 1 -# define CONFIG_STM32H5_TIM1_CH2MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 3 -# define CONFIG_STM32H5_TIM1_CHANNEL3 1 -# define CONFIG_STM32H5_TIM1_CH3MODE CONFIG_STM32H5_TIM1_CHMODE -# elif CONFIG_STM32H5_TIM1_CHANNEL == 4 -# define CONFIG_STM32H5_TIM1_CHANNEL4 1 -# define CONFIG_STM32H5_TIM1_CH4MODE CONFIG_STM32H5_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM2_PWM -# if !defined(CONFIG_STM32H5_TIM2_CHANNEL) -# error "CONFIG_STM32H5_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM2_CHANNEL == 1 -# define CONFIG_STM32H5_TIM2_CHANNEL1 1 -# define CONFIG_STM32H5_TIM2_CH1MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 2 -# define CONFIG_STM32H5_TIM2_CHANNEL2 1 -# define CONFIG_STM32H5_TIM2_CH2MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 3 -# define CONFIG_STM32H5_TIM2_CHANNEL3 1 -# define CONFIG_STM32H5_TIM2_CH3MODE CONFIG_STM32H5_TIM2_CHMODE -# elif CONFIG_STM32H5_TIM2_CHANNEL == 4 -# define CONFIG_STM32H5_TIM2_CHANNEL4 1 -# define CONFIG_STM32H5_TIM2_CH4MODE CONFIG_STM32H5_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM3_PWM -# if !defined(CONFIG_STM32H5_TIM3_CHANNEL) -# error "CONFIG_STM32H5_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM3_CHANNEL == 1 -# define CONFIG_STM32H5_TIM3_CHANNEL1 1 -# define CONFIG_STM32H5_TIM3_CH1MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 2 -# define CONFIG_STM32H5_TIM3_CHANNEL2 1 -# define CONFIG_STM32H5_TIM3_CH2MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 3 -# define CONFIG_STM32H5_TIM3_CHANNEL3 1 -# define CONFIG_STM32H5_TIM3_CH3MODE CONFIG_STM32H5_TIM3_CHMODE -# elif CONFIG_STM32H5_TIM3_CHANNEL == 4 -# define CONFIG_STM32H5_TIM3_CHANNEL4 1 -# define CONFIG_STM32H5_TIM3_CH4MODE CONFIG_STM32H5_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM4_PWM -# if !defined(CONFIG_STM32H5_TIM4_CHANNEL) -# error "CONFIG_STM32H5_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM4_CHANNEL == 1 -# define CONFIG_STM32H5_TIM4_CHANNEL1 1 -# define CONFIG_STM32H5_TIM4_CH1MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 2 -# define CONFIG_STM32H5_TIM4_CHANNEL2 1 -# define CONFIG_STM32H5_TIM4_CH2MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 3 -# define CONFIG_STM32H5_TIM4_CHANNEL3 1 -# define CONFIG_STM32H5_TIM4_CH3MODE CONFIG_STM32H5_TIM4_CHMODE -# elif CONFIG_STM32H5_TIM4_CHANNEL == 4 -# define CONFIG_STM32H5_TIM4_CHANNEL4 1 -# define CONFIG_STM32H5_TIM4_CH4MODE CONFIG_STM32H5_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM5_PWM -# if !defined(CONFIG_STM32H5_TIM5_CHANNEL) -# error "CONFIG_STM32H5_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM5_CHANNEL == 1 -# define CONFIG_STM32H5_TIM5_CHANNEL1 1 -# define CONFIG_STM32H5_TIM5_CH1MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 2 -# define CONFIG_STM32H5_TIM5_CHANNEL2 1 -# define CONFIG_STM32H5_TIM5_CH2MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 3 -# define CONFIG_STM32H5_TIM5_CHANNEL3 1 -# define CONFIG_STM32H5_TIM5_CH3MODE CONFIG_STM32H5_TIM5_CHMODE -# elif CONFIG_STM32H5_TIM5_CHANNEL == 4 -# define CONFIG_STM32H5_TIM5_CHANNEL4 1 -# define CONFIG_STM32H5_TIM5_CH4MODE CONFIG_STM32H5_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM8_PWM -# if !defined(CONFIG_STM32H5_TIM8_CHANNEL) -# error "CONFIG_STM32H5_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM8_CHANNEL == 1 -# define CONFIG_STM32H5_TIM8_CHANNEL1 1 -# define CONFIG_STM32H5_TIM8_CH1MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 2 -# define CONFIG_STM32H5_TIM8_CHANNEL2 1 -# define CONFIG_STM32H5_TIM8_CH2MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 3 -# define CONFIG_STM32H5_TIM8_CHANNEL3 1 -# define CONFIG_STM32H5_TIM8_CH3MODE CONFIG_STM32H5_TIM8_CHMODE -# elif CONFIG_STM32H5_TIM8_CHANNEL == 4 -# define CONFIG_STM32H5_TIM8_CHANNEL4 1 -# define CONFIG_STM32H5_TIM8_CH4MODE CONFIG_STM32H5_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM12_PWM -# if !defined(CONFIG_STM32H5_TIM12_CHANNEL) -# error "CONFIG_STM32H5_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM12_CHANNEL == 1 -# define CONFIG_STM32H5_TIM12_CHANNEL1 1 -# define CONFIG_STM32H5_TIM12_CH1MODE CONFIG_STM32H5_TIM12_CHMODE -# elif CONFIG_STM32H5_TIM12_CHANNEL == 2 -# define CONFIG_STM32H5_TIM12_CHANNEL2 1 -# define CONFIG_STM32H5_TIM12_CH2MODE CONFIG_STM32H5_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM13_PWM -# if !defined(CONFIG_STM32H5_TIM13_CHANNEL) -# error "CONFIG_STM32H5_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM13_CHANNEL == 1 -# define CONFIG_STM32H5_TIM13_CHANNEL1 1 -# define CONFIG_STM32H5_TIM13_CH1MODE CONFIG_STM32H5_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM14_PWM -# if !defined(CONFIG_STM32H5_TIM14_CHANNEL) -# error "CONFIG_STM32H5_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM14_CHANNEL == 1 -# define CONFIG_STM32H5_TIM14_CHANNEL1 1 -# define CONFIG_STM32H5_TIM14_CH1MODE CONFIG_STM32H5_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM15_PWM -# if !defined(CONFIG_STM32H5_TIM15_CHANNEL) -# error "CONFIG_STM32H5_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM15_CHANNEL == 1 -# define CONFIG_STM32H5_TIM15_CHANNEL1 1 -# define CONFIG_STM32H5_TIM15_CH1MODE CONFIG_STM32H5_TIM15_CHMODE -# elif CONFIG_STM32H5_TIM15_CHANNEL == 2 -# define CONFIG_STM32H5_TIM15_CHANNEL2 1 -# define CONFIG_STM32H5_TIM15_CH2MODE CONFIG_STM32H5_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM16_PWM -# if !defined(CONFIG_STM32H5_TIM16_CHANNEL) -# error "CONFIG_STM32H5_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM16_CHANNEL == 1 -# define CONFIG_STM32H5_TIM16_CHANNEL1 1 -# define CONFIG_STM32H5_TIM16_CH1MODE CONFIG_STM32H5_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H5_TIM17_PWM -# if !defined(CONFIG_STM32H5_TIM17_CHANNEL) -# error "CONFIG_STM32H5_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H5_TIM17_CHANNEL == 1 -# define CONFIG_STM32H5_TIM17_CHANNEL1 1 -# define CONFIG_STM32H5_TIM17_CH1MODE CONFIG_STM32H5_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H5_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H5_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H5_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H5_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H5_TIM1_CH1NOUT) || defined(CONFIG_STM32H5_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM8_CH1NOUT) || defined(CONFIG_STM32H5_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H5_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H5_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H5_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H5_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.c b/arch/arm/src/stm32h5/stm32_qspi.c index 2a15d2d19d9..fa0448187bd 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.c +++ b/arch/arm/src/stm32h5/stm32_qspi.c @@ -55,11 +55,11 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA #include "stm32_dma.h" #endif -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H5_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -83,7 +83,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) && defined(CONFIG_STM32H5_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -95,7 +95,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -107,26 +107,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H5_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H5_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H5_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H5_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H5_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -144,11 +144,11 @@ * QUADSPI clock defaults to HCLK. */ -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_RCC_CCIPR4_OCTOSPI1SEL) # error your board.h needs to define STM32_RCC_CCIPR4_OCTOSPI1SEL #endif -#if defined(CONFIG_STM32H5_QSPI1) && !defined(STM32_QSPI_FREQUENCY) +#if defined(CONFIG_STM32_QSPI1) && !defined(STM32_QSPI_FREQUENCY) # error your board.h needs to defined STM32_QSPI_FREQUENCY #else # define QSPI_CLK_FREQUENCY STM32_QSPI_FREQUENCY @@ -183,14 +183,14 @@ struct stm32_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -200,11 +200,11 @@ struct stm32_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -240,7 +240,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -253,7 +253,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -280,16 +280,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H5_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); @@ -299,8 +299,8 @@ static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H5_QSPI_DMATHRESHOLD -# define CONFIG_STM32H5_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -354,13 +354,13 @@ static struct stm32_qspidev_s g_qspi0dev = }, .base = STM32_OCTOSPI1_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_OCTOSPI1, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -386,7 +386,7 @@ static struct stm32_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -438,7 +438,7 @@ static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -461,7 +461,7 @@ static inline void qspi_putreg(struct stm32_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H5_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -583,7 +583,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H5_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -797,7 +797,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -936,7 +936,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CR_FMODE_INDWR : CR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1075,7 +1075,7 @@ static void qspi_ccrconfig(struct stm32_qspidev_s *priv, } } -#if defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1298,7 +1298,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1571,7 +1571,7 @@ static int qspi_memory_dma(struct stm32_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H5_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2017,7 +2017,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2198,7 +2198,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2257,11 +2257,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H5_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H5_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2423,18 +2423,18 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_MSEL | QSPI_CR_DMM); -#if defined(CONFIG_STM32H5_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_MSEL; #endif -#if defined(CONFIG_STM32H5_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DMM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H5_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2460,10 +2460,10 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) QSPI_DCR1_CSHT_MASK | QSPI_DCR1_DEVSIZE_MASK); - regval |= ((CONFIG_STM32H5_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); - if (0 != CONFIG_STM32H5_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR1_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H5_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2569,7 +2569,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2583,7 +2583,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2609,7 +2609,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2617,12 +2617,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H5_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2688,7 +2688,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2707,7 +2707,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H5_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2753,4 +2753,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h5/stm32_qspi.h b/arch/arm/src/stm32h5/stm32_qspi.h index e052df4c1d7..91485bfa9ba 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.h +++ b/arch/arm/src/stm32h5/stm32_qspi.h @@ -33,7 +33,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H5_QSPI1 +#ifdef CONFIG_STM32_QSPI1 /**************************************************************************** * Pre-processor Definitions @@ -125,5 +125,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H5_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H5_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.c b/arch/arm/src/stm32h5/stm32_rcc.c index 0b4dc0fad41..fa541ee24a1 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.c +++ b/arch/arm/src/stm32h5/stm32_rcc.c @@ -55,9 +55,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -66,7 +66,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -101,7 +101,7 @@ static const uint32_t drives[4] = * ****************************************************************************/ -#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -166,7 +166,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -189,7 +189,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -223,7 +223,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -238,7 +238,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h5/stm32_rcc.h b/arch/arm/src/stm32h5/stm32_rcc.h index 49ad30b7f13..8e0f56fb786 100644 --- a/arch/arm/src/stm32h5/stm32_rcc.h +++ b/arch/arm/src/stm32h5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_rcc.h" #else # error "Unsupported STM32H5 chip" @@ -126,7 +126,7 @@ static inline void stm32_mco2config(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -149,7 +149,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -164,7 +164,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -181,7 +181,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32h5/stm32_serial.c b/arch/arm/src/stm32h5/stm32_serial.c index d0a3152b478..b46d7944366 100644 --- a/arch/arm/src/stm32h5/stm32_serial.c +++ b/arch/arm/src/stm32h5/stm32_serial.c @@ -84,7 +84,7 @@ /* Verify that DMA has been enabled and the DMA channel has been defined. */ -#if !defined(CONFIG_STM32H5_DMA1) && !defined(CONFIG_STM32H5_DMA2) +#if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # error STM32H5 Serial DMA requires one of DMA1 or DMA2 to be enabled #endif @@ -110,19 +110,19 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif #endif /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -142,7 +142,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -331,7 +331,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -339,7 +339,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -347,7 +347,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -355,7 +355,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -363,7 +363,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -371,7 +371,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -379,7 +379,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[CONFIG_USART6_TXBUFSIZE]; # ifdef CONFIG_USART6_RXDMA @@ -387,7 +387,7 @@ static char g_usart6rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H7_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; # ifdef CONFIG_UART7_RXDMA @@ -419,7 +419,7 @@ static char g_usart11rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32H12_UART12_SERIALDRIVER +#ifdef CONFIG_STM32_UART12_SERIALDRIVER static char g_uart12rxbuffer[CONFIG_UART12_RXBUFSIZE]; static char g_uart12txbuffer[CONFIG_UART12_TXBUFSIZE]; # ifdef CONFIG_UART12_RXDMA @@ -429,7 +429,7 @@ static char g_uart12rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -504,7 +504,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -581,7 +581,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -658,7 +658,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -735,7 +735,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -812,7 +812,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -889,7 +889,7 @@ static struct stm32_serial_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER static struct stm32_serial_s g_usart6priv = { .dev = @@ -966,7 +966,7 @@ static struct stm32_serial_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER static struct stm32_serial_s g_uart7priv = { .dev = @@ -1043,7 +1043,7 @@ static struct stm32_serial_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER static struct stm32_serial_s g_uart8priv = { .dev = @@ -1431,31 +1431,31 @@ static struct stm32_serial_s g_uart12priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER [6] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER [7] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER [8] = &g_uart8priv, #endif #ifdef CONFIG_STM32H5_UART9_SERIALDRIVER @@ -1652,7 +1652,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) /* This first implementation is for U[S]ARTs that support oversampling * by 8 in additional to the standard oversampling by 16. */ -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 if (priv->islpuart == true) { /* LPUART BRR (19:00) = (256*apbclock_hz/baud_rate) */ @@ -1738,7 +1738,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) priv->baud; } else -#endif /* CONFIG_STM32H5_LPUART1 */ +#endif /* CONFIG_STM32_LPUART1 */ { uint32_t usartdiv8; @@ -1847,7 +1847,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -2051,55 +2051,55 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB3ENR_LPUART1EN ; regaddr = STM32_RCC_APB3ENR; break; #endif -#ifdef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN ; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifdef CONFIG_STM32_USART6_SERIALDRIVER case STM32_USART6_BASE: rcc_en = RCC_APB1LENR_USART6EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifdef CONFIG_STM32_UART7_SERIALDRIVER case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifdef CONFIG_STM32_UART8_SERIALDRIVER case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; @@ -2193,7 +2193,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2584,8 +2584,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -2834,7 +2834,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2912,7 +2912,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2963,7 +2963,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32H5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -3100,8 +3100,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H5_USART_BREAKS -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3343,7 +3343,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3699,7 +3699,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32H5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -4049,7 +4049,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -4078,7 +4078,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h5/stm32_spi.c b/arch/arm/src/stm32h5/stm32_spi.c index 3a66be2eb1d..fd0b621d7e9 100644 --- a/arch/arm/src/stm32h5/stm32_spi.c +++ b/arch/arm/src/stm32h5/stm32_spi.c @@ -72,7 +72,7 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32_dma.h" #endif @@ -82,9 +82,9 @@ # define SPI_MAX_KER_CK 125000000 #endif -#if defined(CONFIG_STM32H5_SPI1) || defined(CONFIG_STM32H5_SPI2) || \ - defined(CONFIG_STM32H5_SPI3) || defined(CONFIG_STM32H5_SPI4) || \ - defined(CONFIG_STM32H5_SPI5) || defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -94,18 +94,18 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H5_SPI_INTERRUPTS) && defined(CONFIG_STM32H5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -142,39 +142,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H5_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H5_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H5_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H5_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -182,7 +182,7 @@ /* Kernel clock configuration */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -195,7 +195,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI2) +#if defined(CONFIG_STM32_SPI2) # ifndef STM32_SPI2_FREQUENCY # error Must define STM32_SPI2_FREQUENCY in board.h # else @@ -208,7 +208,7 @@ # endif #endif /* SPI2 */ -#if defined(CONFIG_STM32H5_SPI3) +#if defined(CONFIG_STM32_SPI3) # ifndef STM32_SPI3_FREQUENCY # error Must define STM32_SPI3_FREQUENCY in board.h # else @@ -221,7 +221,7 @@ # endif #endif /* SPI3 */ -#if defined(CONFIG_STM32H5_SPI1) +#if defined(CONFIG_STM32_SPI1) # ifndef STM32_SPI1_FREQUENCY # error Must define STM32_SPI1_FREQUENCY in board.h # else @@ -234,7 +234,7 @@ # endif #endif /* SPI1 */ -#if defined(CONFIG_STM32H5_SPI5) +#if defined(CONFIG_STM32_SPI5) # ifndef STM32_SPI5_FREQUENCY # error Must define STM32_SPI5_FREQUENCY in board.h # else @@ -247,7 +247,7 @@ # endif #endif /* SPI5 */ -#if defined(CONFIG_STM32H5_SPI6) +#if defined(CONFIG_STM32_SPI6) # ifndef STM32_SPI6_FREQUENCY # error Must define STM32_SPI6_FREQUENCY in board.h # else @@ -278,7 +278,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -328,7 +328,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -394,7 +394,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -443,7 +443,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = STM32_SPI1_FREQUENCY, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -458,15 +458,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI1_COMMTYPE - .config = CONFIG_STM32H5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -515,7 +515,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = STM32_SPI2_FREQUENCY, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -530,15 +530,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI2_COMMTYPE - .config = CONFIG_STM32H5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -587,7 +587,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = STM32_SPI3_FREQUENCY, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -602,15 +602,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI3_COMMTYPE - .config = CONFIG_STM32H5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -659,7 +659,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = STM32_SPI4_FREQUENCY, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H5_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -674,15 +674,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI4_COMMTYPE - .config = CONFIG_STM32H5_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -731,7 +731,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = STM32_SPI5_FREQUENCY, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H5_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -746,15 +746,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI5_COMMTYPE - .config = CONFIG_STM32H5_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -804,7 +804,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = STM32_SPI6_FREQUENCY, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H5_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -819,13 +819,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H5_SPI6_COMMTYPE - .config = CONFIG_STM32H5_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H5_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1147,7 +1147,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1164,7 +1164,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1204,7 +1204,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1253,7 +1253,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1268,7 +1268,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1288,7 +1288,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1350,7 +1350,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1410,7 +1410,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1434,7 +1434,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1991,9 +1991,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H5_SPI_DMA) || defined(CONFIG_STM32H5_DMACAPABLE) || \ - defined(CONFIG_STM32H5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2082,8 +2082,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H5_SPI_DMA || CONFIG_STM32H5_DMACAPABLE || - * CONFIG_STM32H5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2107,7 +2107,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2125,12 +2125,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2194,7 +2194,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2324,7 +2324,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2345,7 +2345,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2579,7 +2579,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2661,7 +2661,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2686,7 +2686,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2711,7 +2711,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2736,7 +2736,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2761,7 +2761,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2786,7 +2786,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2819,6 +2819,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H5_SPI1 || CONFIG_STM32H5_SPI2 || CONFIG_STM32H5_SPI3 || - * CONFIG_STM32H5_SPI4 || CONFIG_STM32H5_SPI5 || CONFIG_STM32H5_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h5/stm32_spi.h b/arch/arm/src/stm32h5/stm32_spi.h index e1f25c88e49..42f7ea39e5d 100644 --- a/arch/arm/src/stm32h5/stm32_spi.h +++ b/arch/arm/src/stm32h5/stm32_spi.h @@ -112,42 +112,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -175,32 +175,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h5/stm32_start.c b/arch/arm/src/stm32h5/stm32_start.c index ec63b6dac10..f87eeb75b6e 100644 --- a/arch/arm/src/stm32h5/stm32_start.c +++ b/arch/arm/src/stm32h5/stm32_start.c @@ -176,7 +176,7 @@ void __start(void) *dest++ = *src++; } -#ifdef CONFIG_STM32H5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* NOTE: this is optional because this may be inappropriate, especially * if the memory is being used for it's battery backed purpose. In that * case, the first-time initialization needs to be performed by the board @@ -225,7 +225,7 @@ void __start(void) stm32_board_initialize(); showprogress('C'); -#ifdef CONFIG_STM32H5_ICACHE +#ifdef CONFIG_STM32_ICACHE stm32_enable_icache(); #endif showprogress('G'); diff --git a/arch/arm/src/stm32h5/stm32_tim.c b/arch/arm/src/stm32h5/stm32_tim.c index 0bb2b40fefe..af94fc20f87 100644 --- a/arch/arm/src/stm32h5/stm32_tim.c +++ b/arch/arm/src/stm32h5/stm32_tim.c @@ -72,77 +72,77 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H5_TIM1_PWM) || defined (CONFIG_STM32H5_TIM1_ADC) || \ - defined(CONFIG_STM32H5_TIM1_DAC) || defined(CONFIG_STM32H5_TIM1_QE) -# undef CONFIG_STM32H5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H5_TIM2_PWM) || defined (CONFIG_STM32H5_TIM2_ADC) || \ - defined(CONFIG_STM32H5_TIM2_DAC) || defined(CONFIG_STM32H5_TIM2_QE) -# undef CONFIG_STM32H5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H5_TIM3_PWM) || defined (CONFIG_STM32H5_TIM3_ADC) || \ - defined(CONFIG_STM32H5_TIM3_DAC) || defined(CONFIG_STM32H5_TIM3_QE) -# undef CONFIG_STM32H5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H5_TIM4_PWM) || defined (CONFIG_STM32H5_TIM4_ADC) || \ - defined(CONFIG_STM32H5_TIM4_DAC) || defined(CONFIG_STM32H5_TIM4_QE) -# undef CONFIG_STM32H5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H5_TIM5_PWM) || defined (CONFIG_STM32H5_TIM5_ADC) || \ - defined(CONFIG_STM32H5_TIM5_DAC) || defined(CONFIG_STM32H5_TIM5_QE) -# undef CONFIG_STM32H5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32H5_TIM6_ADC) || \ - defined(CONFIG_STM32H5_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) -# undef CONFIG_STM32H5_TIM6 +#if defined(CONFIG_STM32H5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H5_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32H5_TIM7_PWM) || defined (CONFIG_STM32H5_TIM7_ADC) || \ - defined(CONFIG_STM32H5_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) -# undef CONFIG_STM32H5_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H5_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H5_TIM8_PWM) || defined (CONFIG_STM32H5_TIM8_ADC) || \ - defined(CONFIG_STM32H5_TIM8_DAC) || defined(CONFIG_STM32H5_TIM8_QE) -# undef CONFIG_STM32H5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H5_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ - defined(CONFIG_STM32H5_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) -# undef CONFIG_STM32H5_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H5_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H5_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H5_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ - defined(CONFIG_STM32H5_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) -# undef CONFIG_STM32H5_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H5_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H5_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H5_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ - defined(CONFIG_STM32H5_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) -# undef CONFIG_STM32H5_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H5_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H5_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H5_TIM15_PWM) || defined (CONFIG_STM32H5_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32H5_TIM15_DAC) || defined(CONFIG_STM32H5_TIM15_QE) -# undef CONFIG_STM32H5_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H5_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H5_TIM16_ADC) || \ defined(CONFIG_STM32H5_TIM16_DAC) || defined(CONFIG_STM32H5_TIM16_QE) -# undef CONFIG_STM32H5_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H5_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H5_TIM17_ADC) || \ defined(CONFIG_STM32H5_TIM17_DAC) || defined(CONFIG_STM32H5_TIM17_QE) -# undef CONFIG_STM32H5_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H5_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -307,7 +307,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -315,7 +315,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -324,7 +324,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -333,7 +333,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -342,7 +342,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -351,7 +351,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -360,7 +360,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -369,7 +369,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -378,7 +378,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -387,7 +387,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -396,7 +396,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -405,7 +405,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -414,7 +414,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -423,7 +423,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -514,12 +514,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H5_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H5_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -621,72 +621,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -740,72 +740,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8_UP; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1011,7 +1011,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1044,7 +1044,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1073,7 +1073,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1102,7 +1102,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1131,7 +1131,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1160,7 +1160,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1194,7 +1194,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1213,7 +1213,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1227,7 +1227,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1242,7 +1242,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1261,7 +1261,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1275,7 +1275,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1359,85 +1359,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1469,72 +1469,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1550,4 +1550,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c index b31f6771216..d0a77244157 100644 --- a/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h5/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H5_TIM1) || defined(CONFIG_STM32H5_TIM2) || \ - defined(CONFIG_STM32H5_TIM3) || defined(CONFIG_STM32H5_TIM4) || \ - defined(CONFIG_STM32H5_TIM5) || defined(CONFIG_STM32H5_TIM6) || \ - defined(CONFIG_STM32H5_TIM7) || defined(CONFIG_STM32H5_TIM8) || \ - defined(CONFIG_STM32H5_TIM12) || defined(CONFIG_STM32H5_TIM13) || \ - defined(CONFIG_STM32H5_TIM14) || defined(CONFIG_STM32H5_TIM15) || \ - defined(CONFIG_STM32H5_TIM16) || defined(CONFIG_STM32H5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim14_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -473,75 +473,75 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32h5/stm32_uart.h b/arch/arm/src/stm32h5/stm32_uart.h index 93914500e76..2a9756b89b1 100644 --- a/arch/arm/src/stm32h5/stm32_uart.h +++ b/arch/arm/src/stm32h5/stm32_uart.h @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32H5_STM32H5XXXX) +#if defined(CONFIG_STM32_STM32H5XXXX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32H5 chip" @@ -46,116 +46,116 @@ * device. */ -#if !defined(CONFIG_STM32H5_HAVE_UART12) -# undef CONFIG_STM32H5_UART12 +#if !defined(CONFIG_STM32_HAVE_UART12) +# undef CONFIG_STM32_UART12 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART11) -# undef CONFIG_STM32H5_USART11 +#if !defined(CONFIG_STM32_HAVE_USART11) +# undef CONFIG_STM32_USART11 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART10) -# undef CONFIG_STM32H5_USART10 +#if !defined(CONFIG_STM32_HAVE_USART10) +# undef CONFIG_STM32_USART10 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART9) -# undef CONFIG_STM32H5_UART9 +#if !defined(CONFIG_STM32_HAVE_UART9) +# undef CONFIG_STM32_UART9 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART8) -# undef CONFIG_STM32H5_UART8 +#if !defined(CONFIG_STM32_HAVE_UART8) +# undef CONFIG_STM32_UART8 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART7) -# undef CONFIG_STM32H5_UART7 +#if !defined(CONFIG_STM32_HAVE_UART7) +# undef CONFIG_STM32_UART7 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART6) -# undef CONFIG_STM32H5_USART6 +#if !defined(CONFIG_STM32_HAVE_USART6) +# undef CONFIG_STM32_USART6 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART5) -# undef CONFIG_STM32H5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32H5_HAVE_UART4) -# undef CONFIG_STM32H5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART3) -# undef CONFIG_STM32H5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART2) -# undef CONFIG_STM32H5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32H5_HAVE_USART1) -# undef CONFIG_STM32H5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32H5_HAVE_LPUART1) -# undef CONFIG_STM32H5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32H5_LPUART1) -# undef CONFIG_STM32H5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32H5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART1) -# undef CONFIG_STM32H5_USART1_SERIALDRIVER -# undef CONFIG_STM32H5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART2) -# undef CONFIG_STM32H5_USART2_SERIALDRIVER -# undef CONFIG_STM32H5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART3) -# undef CONFIG_STM32H5_USART3_SERIALDRIVER -# undef CONFIG_STM32H5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART4) -# undef CONFIG_STM32H5_UART4_SERIALDRIVER -# undef CONFIG_STM32H5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART5) -# undef CONFIG_STM32H5_UART5_SERIALDRIVER -# undef CONFIG_STM32H5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART6) -# undef CONFIG_STM32H5_USART6_SERIALDRIVER -# undef CONFIG_STM32H5_USART6_1WIREDRIVER +#if !defined(CONFIG_STM32_USART6) +# undef CONFIG_STM32_USART6_SERIALDRIVER +# undef CONFIG_STM32_USART6_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART7) -# undef CONFIG_STM32H5_UART7_SERIALDRIVER -# undef CONFIG_STM32H5_UART7_1WIREDRIVER +#if !defined(CONFIG_STM32_UART7) +# undef CONFIG_STM32_UART7_SERIALDRIVER +# undef CONFIG_STM32_UART7_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART8) -# undef CONFIG_STM32H5_UART8_SERIALDRIVER -# undef CONFIG_STM32H5_UART8_1WIREDRIVER +#if !defined(CONFIG_STM32_UART8) +# undef CONFIG_STM32_UART8_SERIALDRIVER +# undef CONFIG_STM32_UART8_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART9) +#if !defined(CONFIG_STM32_UART9) # undef CONFIG_STM32H5_UART9_SERIALDRIVER # undef CONFIG_STM32H5_UART9_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART10) +#if !defined(CONFIG_STM32_USART10) # undef CONFIG_STM32H5_USART10_SERIALDRIVER # undef CONFIG_STM32H5_USART10_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_USART11) +#if !defined(CONFIG_STM32_USART11) # undef CONFIG_STM32H5_USART11_SERIALDRIVER # undef CONFIG_STM32H5_USART11_1WIREDRIVER #endif -#if !defined(CONFIG_STM32H5_UART12) +#if !defined(CONFIG_STM32_UART12) # undef CONFIG_STM32H5_UART12_SERIALDRIVER # undef CONFIG_STM32H5_UART12_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H5_LPUART1) || defined(CONFIG_STM32H5_USART1) || \ - defined(CONFIG_STM32H5_USART2) || defined(CONFIG_STM32H5_USART3) || \ - defined(CONFIG_STM32H5_UART4) || defined(CONFIG_STM32H5_UART5) || \ - defined(CONFIG_STM32H5_USART6) || defined(CONFIG_STM32H5_UART7) || \ - defined(CONFIG_STM32H5_UART8) || defined(CONFIG_STM32H5_UART9) || \ - defined(CONFIG_STM32H5_USART10) || defined(CONFIG_STM32H5_USART11) || \ +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) || \ + defined(CONFIG_STM32_USART6) || defined(CONFIG_STM32_UART7) || \ + defined(CONFIG_STM32_UART8) || defined(CONFIG_STM32_UART9) || \ + defined(CONFIG_STM32_USART10) || defined(CONFIG_STM32_USART11) || \ defined(CONFIG_STM32H5_USART12) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,7 +170,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -185,7 +185,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -200,7 +200,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -215,7 +215,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -230,7 +230,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -245,7 +245,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_USART6_SERIALDRIVER) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -260,7 +260,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART7_SERIALDRIVER) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -275,7 +275,7 @@ # undef CONFIG_UART12_SERIAL_CONSOLE # define CONSOLE_UART 8 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H5_UART8_SERIALDRIVER) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -381,39 +381,39 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32H5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32H5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32H5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32H5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32H5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif -#ifndef CONFIG_STM32H5_USART6_SERIALDRIVER +#ifndef CONFIG_STM32_USART6_SERIALDRIVER # undef CONFIG_USART6_RXDMA #endif -#ifndef CONFIG_STM32H5_UART7_SERIALDRIVER +#ifndef CONFIG_STM32_UART7_SERIALDRIVER # undef CONFIG_UART7_RXDMA #endif -#ifndef CONFIG_STM32H5_UART8_SERIALDRIVER +#ifndef CONFIG_STM32_UART8_SERIALDRIVER # undef CONFIG_UART8_RXDMA #endif @@ -480,23 +480,23 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32H5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6_SERIALDRIVER) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7_SERIALDRIVER) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32H5_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8_SERIALDRIVER) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #elif defined(CONFIG_STM32H5_UART9_SERIALDRIVER) && !defined(CONFIG_UART9_RXDMA) # undef SERIAL_HAVE_ONLY_DMA diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.c b/arch/arm/src/stm32h5/stm32_usbdrdhost.c index a9b9332eb21..e368b914107 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.c +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.c @@ -62,7 +62,7 @@ #include "hardware/stm32h5xxx_pwr.h" #include "stm32_usbdrdhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_USBFS_HOST) /**************************************************************************** * Pre-processor Definitions @@ -70,12 +70,12 @@ /* Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif #ifndef CONFIG_STM32H5_USBDRD_TRANSFER_TIMEOUT @@ -84,7 +84,7 @@ /* Hardware definitions */ -#define STM32_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS +#define STM32_NHOST_CHANNELS CONFIG_STM32_USBDRD_NCHANNELS #define STM32_EP0_MAX_PACKET_SIZE 64 #define STM32_RETRY_COUNT 3 /* Control transfer retries */ @@ -2176,14 +2176,14 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, DEBUGASSERT(drvr && buffer && maxlen); - alloc = kmm_malloc(CONFIG_STM32H5_USBDRD_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_USBDRD_DESCSIZE); if (!alloc) { return -ENOMEM; } *buffer = alloc; - *maxlen = CONFIG_STM32H5_USBDRD_DESCSIZE; + *maxlen = CONFIG_STM32_USBDRD_DESCSIZE; return OK; } @@ -2890,4 +2890,4 @@ void stm32_usbdrdhost_vbusdrive(int port, bool enable) uinfo("VBUS drive port=%d enable=%d (default - no-op)\n", port, enable); } -#endif /* CONFIG_USBHOST && CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_USBFS_HOST */ diff --git a/arch/arm/src/stm32h5/stm32_usbdrdhost.h b/arch/arm/src/stm32h5/stm32_usbdrdhost.h index 1cccbd78e31..a3f07b1be67 100644 --- a/arch/arm/src/stm32h5/stm32_usbdrdhost.h +++ b/arch/arm/src/stm32h5/stm32_usbdrdhost.h @@ -39,20 +39,20 @@ /* Pre-requisites */ -#if !defined(CONFIG_STM32H5_USBFS_HOST) -# error "CONFIG_STM32H5_USBFS_HOST is required" +#if !defined(CONFIG_STM32_USBFS_HOST) +# error "CONFIG_STM32_USBFS_HOST is required" #endif /* USB DRD Host Driver Configuration */ -#ifndef CONFIG_STM32H5_USBDRD_NCHANNELS -# define CONFIG_STM32H5_USBDRD_NCHANNELS 8 +#ifndef CONFIG_STM32_USBDRD_NCHANNELS +# define CONFIG_STM32_USBDRD_NCHANNELS 8 #endif /* Default descriptor buffer size */ -#ifndef CONFIG_STM32H5_USBDRD_DESCSIZE -# define CONFIG_STM32H5_USBDRD_DESCSIZE 128 +#ifndef CONFIG_STM32_USBDRD_DESCSIZE +# define CONFIG_STM32_USBDRD_DESCSIZE 128 #endif /**************************************************************************** diff --git a/arch/arm/src/stm32h5/stm32_usbfs.c b/arch/arm/src/stm32h5/stm32_usbfs.c index 2b44b014266..c4a69deb441 100644 --- a/arch/arm/src/stm32h5/stm32_usbfs.c +++ b/arch/arm/src/stm32h5/stm32_usbfs.c @@ -49,7 +49,7 @@ #include "stm32_gpio.h" #include "stm32_usbfs.h" -#if defined(CONFIG_STM32H5_USBFS) +#if defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32H5_USBFS_REGDEBUG +# undef CONFIG_STM32_USBFS_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -345,7 +345,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); @@ -609,7 +609,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -668,7 +668,7 @@ static uint32_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -685,7 +685,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -723,7 +723,7 @@ static void stm32_dumpep(int epno) * Name: stm32_checksetup ****************************************************************************/ -#ifdef CONFIG_STM32H5_USBFS_REGDEBUG +#ifdef CONFIG_STM32_USBFS_REGDEBUG static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); @@ -3950,4 +3950,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_STM32H5_USBFS */ +#endif /* CONFIG_STM32_USBFS */ diff --git a/arch/arm/src/stm32h5/stm32h563xx_flash.c b/arch/arm/src/stm32h5/stm32h563xx_flash.c index 11656e1212b..26c78a2778f 100644 --- a/arch/arm/src/stm32h5/stm32h563xx_flash.c +++ b/arch/arm/src/stm32h5/stm32h563xx_flash.c @@ -58,42 +58,42 @@ #define FLASH_BLOCK_SIZE _K(8) #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H5_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H5_FLASH_CONFIG_I) -# define CONFIG_STM32H5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32H5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H5_FLASH_CONFIG_C -# undef CONFIG_STM32H5_FLASH_CONFIG_E -# if defined(CONFIG_STM32H5_FLASH_OVERRIDE_C) -# define CONFIG_STM32H5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32H5_FLASH_OVERRIDE_E) -# define CONFIG_STM32H5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif -#if defined(CONFIG_STM32H5_FLASH_CONFIG_I) +#if defined(CONFIG_STM32_FLASH_CONFIG_I) # define H5_FLASH_BANK_NBLOCKS 128 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define H5_FLASH_BANK_NBLOCKS 64 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_E) +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) # define H5_FLASH_BANK_NBLOCKS 32 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_C) +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) # define H5_FLASH_BANK_NBLOCKS 16 -#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B) +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) # define H5_FLASH_BANK_NBLOCKS 8 #else # warning "No valid STM32_FLASH_CONFIG_x defined." diff --git a/arch/arm/src/stm32h5/stm32h5xx_rcc.c b/arch/arm/src/stm32h5/stm32h5xx_rcc.c index c26278872f2..31de43c0c94 100644 --- a/arch/arm/src/stm32h5/stm32h5xx_rcc.c +++ b/arch/arm/src/stm32h5/stm32h5xx_rcc.c @@ -62,7 +62,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if defined(STM32_CLKUSB_SEL) # if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK) # define STM32_USE_HSI48 1 @@ -101,13 +101,13 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32H5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32H5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_GPDMA2EN; @@ -119,31 +119,31 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32H5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32H5_CORDIC +#ifdef CONFIG_STM32_CORDIC /* CORDIC clock enable */ regval |= RCC_AHB1ENR_CORDICEN; #endif -#ifdef CONFIG_STM32H5_FMAC +#ifdef CONFIG_STM32_FMAC /* FMAC clock enable */ regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32H5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG /* RAMCFG clock enable */ regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32H5_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* ETH clock enable */ regval |= RCC_AHB1ENR_ETHEN; @@ -174,7 +174,7 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_DCACHEEN; #endif -#ifdef CONFIG_STM32H5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 /* ETH clock enable */ regval |= RCC_AHB1ENR_SRAM1EN; @@ -233,61 +233,61 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32H5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32H5_DAC1 +#ifdef CONFIG_STM32_DAC1 /* DAC1 clock enable */ regval |= RCC_AHB2ENR_DAC1EN; #endif -#ifdef CONFIG_STM32H5_DCMI_PSSI +#ifdef CONFIG_STM32_DCMI_PSSI /* Digital Camera Interface clock enable */ regval |= RCC_AHB2ENR_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32H5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32H5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32H5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H5_PKA +#ifdef CONFIG_STM32_PKA /* Public Key Accelerator clock enable */ regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32H5_SAES +#ifdef CONFIG_STM32_SAES /* Secure AES coprocessor clock enable */ regval |= RCC_AHB2ENR_SAESEN; #endif -#ifdef CONFIG_STM32H5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM2EN; #endif -#ifdef CONFIG_STM32H5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 /* SRAM2 clock enable */ regval |= RCC_AHB2ENR_SRAM3EN; @@ -320,25 +320,25 @@ static inline void rcc_enableahb4(void) regval |= RCC_AHB4ENR_OTFDEC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H5_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC1 clock enable */ regval |= RCC_AHB4ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB4ENR_FMCEN; #endif -#ifdef CONFIG_STM32H5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB4ENR_OSPI1EN; @@ -365,49 +365,49 @@ static inline void rcc_enableapb1l(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Bit 14: SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Bit 15: SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H5_USART2 +#ifdef CONFIG_STM32_USART2 /* Bit 17: USART2 clock enable */ regval |= RCC_APB1LENR_USART2EN; #endif -#ifdef CONFIG_STM32H5_USART3 +#ifdef CONFIG_STM32_USART3 /* Bit 18: USART3 clock enable */ regval |= RCC_APB1LENR_USART3EN; #endif -#ifdef CONFIG_STM32H5_UART4 +#ifdef CONFIG_STM32_UART4 /* Bit 19: UART4 clock enable */ regval |= RCC_APB1LENR_UART4EN; #endif -#ifdef CONFIG_STM32H5_UART5 +#ifdef CONFIG_STM32_UART5 /* Bit 20: UART5 clock enable */ regval |= RCC_APB1LENR_UART5EN; #endif -#ifdef CONFIG_STM32H5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Bit 21: I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Bit 22: I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; @@ -428,37 +428,37 @@ static inline void rcc_enableapb1l(void) } #endif -#ifdef CONFIG_STM32H5_USART6 +#ifdef CONFIG_STM32_USART6 /* Bit 25: USART6 clock enable */ regval |= RCC_APB1LENR_USART6EN; #endif -#ifdef CONFIG_STM32H5_USART10 +#ifdef CONFIG_STM32_USART10 /* Bit 26: USART10 clock enable */ regval |= RCC_APB1LENR_USART10EN; #endif -#ifdef CONFIG_STM32H5_USART11 +#ifdef CONFIG_STM32_USART11 /* Bit 27: USART11 clock enable */ regval |= RCC_APB1LENR_USART11EN; #endif -#ifdef CONFIG_STM32H5_CEC +#ifdef CONFIG_STM32_CEC /* Bit 28: CEC clock enable */ regval |= RCC_APB1LENR_CECEN; #endif -#ifdef CONFIG_STM32H5_UART7 +#ifdef CONFIG_STM32_UART7 /* Bit 30: UART7 clock enable */ regval |= RCC_APB1LENR_UART7EN; #endif -#ifdef CONFIG_STM32H5_UART8 +#ifdef CONFIG_STM32_UART8 /* Bit 31: UART8 clock enable */ regval |= RCC_APB1LENR_UART8EN; @@ -485,37 +485,37 @@ static inline void rcc_enableapb1h(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H5_UART9 +#ifdef CONFIG_STM32_UART9 /* Bit 0: UART9 clock enable */ regval |= RCC_APB1HENR_UART9EN; #endif -#ifdef CONFIG_STM32H5_UART12 +#ifdef CONFIG_STM32_UART12 /* Bit 1: UART12 clock enable */ regval |= RCC_APB1HENR_UART12EN; #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* Bit 3: DTS clock enable */ regval |= RCC_APB1HENR_DTSEN; #endif -#ifdef CONFIG_STM32H5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Bit 5: Low-power Timer 2 clock enable */ regval |= RCC_APB1HENR_LPTIM2EN; #endif -#ifdef CONFIG_STM32H5_FDCAN +#ifdef CONFIG_STM32_FDCAN /* Bit 9: FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; #endif -#ifdef CONFIG_STM32H5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* Bit 23: UCPD1 clock enable */ regval |= RCC_APB1HENR_UCPD1EN; @@ -544,43 +544,43 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H5_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H5_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB2ENR_SPI6EN; #endif -#ifdef CONFIG_STM32H5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32H5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_USBFS_HOST) /* USB clock enable */ regval |= RCC_APB2ENR_USBEN; @@ -607,31 +607,31 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32H5_ETHMAC) +#if defined(CONFIG_STM32H5_SBS) || defined(CONFIG_STM32_ETHMAC) /* Bit 1: SBS clock enable */ regval |= RCC_APB3ENR_SBSEN; #endif -#ifdef CONFIG_STM32H5_SPI5 +#ifdef CONFIG_STM32_SPI5 /* Bit 5: SPI5 clock enable */ regval |= RCC_APB3ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Bit 6: LPUART1 clock enable */ regval |= RCC_APB3ENR_LPUART1EN; #endif -#ifdef CONFIG_STM32H5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Bit 7: I2C3 clock enable */ regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32H5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* Bit 8: I2C4 clock enable */ regval |= RCC_APB3ENR_I2C4EN; @@ -643,25 +643,25 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_I3C2EN; #endif -#ifdef CONFIG_STM32H5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Bit 11: LPTIM1 clock enable */ regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32H5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Bit 12: LPTIM3 clock enable */ regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32H5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 /* Bit 13: LPTIM4 clock enable */ regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32H5_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 /* Bit 14: LPTIM5 clock enable */ regval |= RCC_APB3ENR_LPTIM5EN; @@ -673,13 +673,13 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_LPTIM6EN; #endif -#ifdef CONFIG_STM32H5_VREF +#ifdef CONFIG_STM32_VREF /* Bit 20: VREF clock enable */ regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32H5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB /* Bit 21: RTCABP clock enable */ regval |= RCC_APB3ENR_RTCAPBEN; @@ -859,7 +859,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -995,7 +995,7 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR2); -#ifdef CONFIG_STM32H5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR1); @@ -1096,7 +1096,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \ +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) || \ defined(STM32_USE_LSCO_LSI) /* Low speed internal clock source LSI */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/Kconfig b/boards/arm/stm32h5/nucleo-h563zi/Kconfig index e0838b56a45..875646f6c5c 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/Kconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/Kconfig @@ -5,7 +5,7 @@ if ARCH_BOARD_NUCLEO_H563ZI -config STM32H5_USE_HSE +config STM32_USE_HSE bool "Use on-board HSE" default n ---help--- diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig index 47aa7fb2cfe..0b0e405f950 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,8 +49,8 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig index f5fde0ba1a7..748044ad5fc 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/adc_watchdog/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,13 +50,13 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_ADC1=y -CONFIG_STM32H5_ADC1_DMA=y -CONFIG_STM32H5_ADC1_DMA_CFG=y -CONFIG_STM32H5_ADC1_WDG1=y -CONFIG_STM32H5_ADC1_WDG1_HIGHTHRESH=2048 -CONFIG_STM32H5_DMA1=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_DMA_CFG=1 +CONFIG_STM32_ADC1_WDG1=y +CONFIG_STM32_ADC1_WDG1_HIGHTHRESH=2048 +CONFIG_STM32_DMA1=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig index 23e83ae9177..343a7808946 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/dts/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -43,9 +44,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SENSORS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_DTS=y -CONFIG_STM32H5_DTS_SMP_TIME=15 -CONFIG_STM32H5_USART3=y +CONFIG_STM32_DTS=y +CONFIG_STM32_DTS_SMP_TIME=15 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SENSORTEST=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig index d6a00523dbb..dbd9341b0a6 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/fdcan1/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_FDCAN1=y -CONFIG_STM32H5_FDCAN1_FD=y -CONFIG_STM32H5_FDCAN1_LOOPBACK=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN1_FD=y +CONFIG_STM32_FDCAN1_LOOPBACK=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig index d2a59492c4b..70c92e44278 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -42,7 +43,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig index 1c47ce601a8..e4316e5ec38 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/nshusbnet/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -58,9 +59,9 @@ CONFIG_SCHED_LPWORK=y CONFIG_SCHED_LPWORKSTACKSIZE=4096 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig index 3b73e316f4e..7b29390dc44 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_TIM1=y -CONFIG_STM32H5_TIM1_CH1OUT=y -CONFIG_STM32H5_TIM1_PWM=y -CONFIG_STM32H5_USART3=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TIMER=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig index e2a645bc025..0e375794ff1 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbmsc/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,9 +48,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS_HOST=y -CONFIG_STM32H5_USE_HSE=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS_HOST=y +CONFIG_STM32_USE_HSE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig index 6772b433f1f..7d01dc6fdee 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h5/nucleo-h563zi/configs/usbnsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-h563zi" CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H563ZI=y CONFIG_ARCH_CHIP_STM32H5=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -48,7 +49,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32H5_USART3=y -CONFIG_STM32H5_USBFS=y +CONFIG_STM32_USART3=y +CONFIG_STM32_USBFS=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h5/nucleo-h563zi/include/board.h b/boards/arm/stm32h5/nucleo-h563zi/include/board.h index d68741a2620..167efe417ad 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/include/board.h +++ b/boards/arm/stm32h5/nucleo-h563zi/include/board.h @@ -36,7 +36,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H5_USBFS_HOST) && !defined(CONFIG_STM32H5_USE_HSE) +#if defined(CONFIG_STM32_USBFS_HOST) && !defined(CONFIG_STM32_USE_HSE) #error "This board config requires HSE to use the USB HOST." "HSI48 is not stable enough to use as a host." "To use HSE on the nucleo-H563ZI," @@ -65,7 +65,7 @@ #define STM32_LSI_FREQUENCY 32000 #define STM32_LSE_FREQUENCY 32768 -#ifdef CONFIG_STM32H5_USE_HSE +#ifdef CONFIG_STM32_USE_HSE #define STM32_HSE_FREQUENCY 25000000ul #define STM32_BOARD_USEHSE @@ -108,7 +108,7 @@ #define STM32_VCO2_FRQ ((STM32_HSE_FREQUENCY / 5) * 60) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#if defined(CONFIG_STM32H5_USBFS_HOST) +#if defined(CONFIG_STM32_USBFS_HOST) /* PLL3 config: Generate 48 MHz for USB from 25 MHz HSE. * VCO input = 25 MHz / 5 = 5 MHz * VCO output = 5 MHz * 96 = 480 MHz @@ -134,7 +134,7 @@ /* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */ #define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ #else @@ -181,22 +181,22 @@ #define STM32_VCO2_FRQ ((STM32_HSI_FREQUENCY / 8) * 75) #define STM32_PLL2R_FREQUENCY (STM32_VCO2_FRQ / 4) -#endif /* CONFIG_STM32H5_USE_HSE*/ +#endif /* CONFIG_STM32_USE_HSE*/ /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 #endif -#if defined(CONFIG_STM32H5_USBFS) +#if defined(CONFIG_STM32_USBFS) # define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK # define STM32_HSI48_SYNCSRC SYNCSRC_USB #else # define STM32_HSI48_SYNCSRC SYNCSRC_NONE #endif -#if defined(CONFIG_STM32H5_RNG) +#if defined(CONFIG_STM32_RNG) # define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt index 7dca629677e..7a979d50c30 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt +++ b/boards/arm/stm32h5/nucleo-h563zi/src/CMakeLists.txt @@ -36,15 +36,15 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H5_DTS) +if(CONFIG_STM32_DTS) list(APPEND SRCS stm32_dts.c) endif() -if(CONFIG_STM32H5_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_can.c) endif() -if(CONFIG_STM32H5_USBFS_HOST) +if(CONFIG_STM32_USBFS_HOST) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile index 015b4463999..bf97497b304 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/Makefile +++ b/boards/arm/stm32h5/nucleo-h563zi/src/Makefile @@ -39,19 +39,19 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H5_DTS),y) +ifeq ($(CONFIG_STM32_DTS),y) CSRCS += stm32_dts.c endif -ifeq ($(CONFIG_STM32H5_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CSRCS += stm32_can.c endif -ifeq ($(CONFIG_STM32H5_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H5_USBFS_HOST),y) +ifeq ($(CONFIG_STM32_USBFS_HOST),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h index 0d30bde00d7..1c609efc589 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h +++ b/boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h @@ -126,7 +126,7 @@ int stm32_bringup(void); int stm32_adc_setup(void); #endif -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS int stm32_dts_setup(int devno); #endif @@ -138,7 +138,7 @@ int stm32_dts_setup(int devno); * ****************************************************************************/ -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER int stm32_can_setup(uint8_t port); #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c index 9061382e463..08f0568ed24 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_adc.c @@ -37,7 +37,7 @@ #include "stm32.h" #if defined(CONFIG_ADC) -#if defined(CONFIG_STM32H5_ADC1) || defined(CONFIG_STM32H5_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Identifying number of each ADC channel (even if NCHANNELS is less ) */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist1[ADC1_NCHANNELS] = { @@ -101,10 +101,10 @@ static uint32_t g_pinlist1[ADC1_NPINS] = int stm32_adc_setup(void) { static bool initialized = false; -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 struct adc_dev_s *adc1; #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 struct adc_dev_s *adc2; #endif int ret; @@ -116,7 +116,7 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32H5_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { stm32_configgpio(g_pinlist1[i]); @@ -139,7 +139,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32H5_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { stm32_configgpio(g_pinlist2[i]); @@ -168,5 +168,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32H5_ADC1 || CONFIG_STM32H5_ADC2 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c index 1653b499626..4139cb487f9 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c @@ -107,7 +107,7 @@ int stm32_bringup(void) } #endif /* CONFIG_ADC*/ -#ifdef CONFIG_STM32H5_DTS +#ifdef CONFIG_STM32_DTS /* devno == 0 creates /dev/sensor_temp0 */ ret = stm32_dts_setup(0); @@ -117,9 +117,9 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H5_FDCAN_CHARDRIVER +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER /* Initialize CAN and register the CAN driver. */ -# ifdef CONFIG_STM32H5_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 ret = stm32_can_setup(1); if (ret < 0) { @@ -127,7 +127,7 @@ int stm32_bringup(void) } # endif -# ifdef CONFIG_STM32H5_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 ret = stm32_can_setup(2); if (ret < 0) { diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c index caa6709a4c3..d33b11c390b 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_can.c @@ -46,7 +46,7 @@ /* Configuration ************************************************************/ -#if !defined(CONFIG_STM32H5_FDCAN1) && !defined(CONFIG_STM32H5_FDCAN2) +#if !defined(CONFIG_STM32_FDCAN1) && !defined(CONFIG_STM32_FDCAN2) # error "No CAN device is enabled. Please enable at least one CAN device" #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c index e1b23b88046..03e7b8d1e70 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c @@ -37,13 +37,13 @@ * Currently the NUCLEO-H563ZI board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c index 8a0e6d61858..422b7a3ec5a 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_dts.c @@ -34,7 +34,7 @@ #include "stm32.h" -#if defined(CONFIG_STM32H5_DTS) +#if defined(CONFIG_STM32_DTS) /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c index 84c307b7181..ede1d26a5ba 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H5_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c index dcf5bae1cbd..f0d920a6ce6 100644 --- a/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c +++ b/boards/arm/stm32h5/nucleo-h563zi/src/stm32_usb.c @@ -42,7 +42,7 @@ #include "stm32.h" #include "stm32_usbdrdhost.h" -#ifdef CONFIG_STM32H5_USBFS_HOST +#ifdef CONFIG_STM32_USBFS_HOST /**************************************************************************** * Pre-processor Definitions @@ -265,4 +265,4 @@ int board_usbhost_select_configuration(FAR struct usbhost_hubport_s *hport, } #endif -#endif /* CONFIG_STM32H5_USBFS_HOST */ +#endif /* CONFIG_STM32_USBFS_HOST */ From 624b1cdc7ed0fe322c171c485b742dd75ab4e55f Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 088/268] !arch/stm32h7: use common STM32 Kconfig symbols BREAKING CHANGE: STM32H7 Kconfig symbols were renamed from CONFIG_STM32H7_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_STM32H7_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../drivers/character/timers/capture.rst | 2 +- Documentation/guides/renode.rst | 2 +- .../boards/linum-stm32h753bi/index.rst | 2 +- Documentation/platforms/arm/stm32h7/index.rst | 2 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32h7/chip.h | 12 +- arch/arm/include/stm32h7/irq.h | 10 +- arch/arm/src/stm32h7/CMakeLists.txt | 60 +- arch/arm/src/stm32h7/Kconfig | 6485 +---------------- arch/arm/src/stm32h7/Make.defs | 62 +- arch/arm/src/stm32h7/hardware/stm32_dmamux.h | 10 +- .../arm/src/stm32h7/hardware/stm32_ethernet.h | 12 +- arch/arm/src/stm32h7/hardware/stm32_exti.h | 12 +- arch/arm/src/stm32h7/hardware/stm32_flash.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_gpio.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_i2c.h | 10 +- .../src/stm32h7/hardware/stm32_memorymap.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_pinmap.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_pwr.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_rcc.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_sdmmc.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_spi.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_syscfg.h | 10 +- arch/arm/src/stm32h7/hardware/stm32_uart.h | 10 +- .../src/stm32h7/hardware/stm32h7x3xx_gpio.h | 16 +- .../stm32h7/hardware/stm32h7x3xx_memorymap.h | 2 +- .../src/stm32h7/hardware/stm32h7x3xx_pinmap.h | 12 +- .../src/stm32h7/hardware/stm32h7x3xx_pwr.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_rcc.h | 4 +- .../src/stm32h7/hardware/stm32h7x3xx_spi.h | 12 +- .../src/stm32h7/hardware/stm32h7x3xx_syscfg.h | 6 +- .../src/stm32h7/hardware/stm32h7x3xx_uart.h | 12 +- arch/arm/src/stm32h7/stm32_adc.c | 76 +- arch/arm/src/stm32h7/stm32_adc.h | 476 +- arch/arm/src/stm32h7/stm32_aes.h | 2 +- arch/arm/src/stm32h7/stm32_allocateheap.c | 12 +- arch/arm/src/stm32h7/stm32_bbsram.c | 14 +- arch/arm/src/stm32h7/stm32_bbsram.h | 10 +- arch/arm/src/stm32h7/stm32_capture.c | 160 +- .../arm/src/stm32h7/stm32_capture_lowerhalf.c | 96 +- arch/arm/src/stm32h7/stm32_dma.c | 88 +- arch/arm/src/stm32h7/stm32_dma.h | 2 +- arch/arm/src/stm32h7/stm32_dtcm.h | 2 +- arch/arm/src/stm32h7/stm32_dualcore.c | 8 +- arch/arm/src/stm32h7/stm32_dualcore.h | 2 +- arch/arm/src/stm32h7/stm32_ethernet.c | 274 +- arch/arm/src/stm32h7/stm32_ethernet.h | 4 +- arch/arm/src/stm32h7/stm32_exti_gpio.c | 12 +- arch/arm/src/stm32h7/stm32_fdcan_sock.c | 54 +- arch/arm/src/stm32h7/stm32_fdcan_sock.h | 4 +- arch/arm/src/stm32h7/stm32_flash.c | 10 +- arch/arm/src/stm32h7/stm32_fmc.c | 6 +- arch/arm/src/stm32h7/stm32_gpio.c | 18 +- arch/arm/src/stm32h7/stm32_gpio.h | 6 +- arch/arm/src/stm32h7/stm32_i2c.c | 100 +- arch/arm/src/stm32h7/stm32_i2c.h | 8 +- arch/arm/src/stm32h7/stm32_iwdg.c | 10 +- arch/arm/src/stm32h7/stm32_lptim.c | 52 +- arch/arm/src/stm32h7/stm32_lse.c | 30 +- arch/arm/src/stm32h7/stm32_ltdc.c | 312 +- arch/arm/src/stm32h7/stm32_ltdc.h | 4 +- arch/arm/src/stm32h7/stm32_mdio.c | 2 +- arch/arm/src/stm32h7/stm32_mpuinit.c | 2 +- arch/arm/src/stm32h7/stm32_oneshot.c | 12 +- arch/arm/src/stm32h7/stm32_oneshot.h | 20 +- arch/arm/src/stm32h7/stm32_otg.h | 16 +- arch/arm/src/stm32h7/stm32_otgdev.c | 64 +- arch/arm/src/stm32h7/stm32_otghost.c | 40 +- arch/arm/src/stm32h7/stm32_pulsecount.c | 94 +- arch/arm/src/stm32h7/stm32_pwm.c | 612 +- arch/arm/src/stm32h7/stm32_pwm.h | 522 +- arch/arm/src/stm32h7/stm32_pwr.c | 2 +- arch/arm/src/stm32h7/stm32_qencoder.c | 106 +- arch/arm/src/stm32h7/stm32_qencoder.h | 24 +- arch/arm/src/stm32h7/stm32_qspi.c | 102 +- arch/arm/src/stm32h7/stm32_qspi.h | 4 +- arch/arm/src/stm32h7/stm32_rcc.c | 34 +- arch/arm/src/stm32h7/stm32_rcc.h | 14 +- arch/arm/src/stm32h7/stm32_rng.c | 4 +- arch/arm/src/stm32h7/stm32_rptun.c | 2 +- arch/arm/src/stm32h7/stm32_rtc.c | 44 +- arch/arm/src/stm32h7/stm32_rtc.h | 20 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 94 +- arch/arm/src/stm32h7/stm32_serial.c | 250 +- arch/arm/src/stm32h7/stm32_spi.c | 178 +- arch/arm/src/stm32h7/stm32_spi.h | 24 +- arch/arm/src/stm32h7/stm32_spi_slave.c | 42 +- arch/arm/src/stm32h7/stm32_start.c | 2 +- arch/arm/src/stm32h7/stm32_tickless.c | 60 +- arch/arm/src/stm32h7/stm32_tim.c | 284 +- arch/arm/src/stm32h7/stm32_tim_lowerhalf.c | 70 +- arch/arm/src/stm32h7/stm32_uart.h | 88 +- arch/arm/src/stm32h7/stm32_usbhost.h | 12 +- arch/arm/src/stm32h7/stm32_wdg.h | 4 +- arch/arm/src/stm32h7/stm32_wwdg.c | 10 +- arch/arm/src/stm32h7/stm32h743xx_flash.c | 48 +- arch/arm/src/stm32h7/stm32h7b3xx_flash.c | 34 +- arch/arm/src/stm32h7/stm32h7x3xx_rcc.c | 96 +- arch/arm/src/stm32h7/stm32h7x7xx_rcc.c | 78 +- .../configs/buzzer/defconfig | 15 +- .../configs/eeprom/defconfig | 9 +- .../linum-stm32h753bi/configs/leds/defconfig | 7 +- .../configs/littlefs/defconfig | 11 +- .../linum-stm32h753bi/configs/lvgl/defconfig | 23 +- .../configs/mfrc522/defconfig | 9 +- .../configs/modbus_master/defconfig | 11 +- .../configs/modbus_slave/defconfig | 11 +- .../configs/netnsh/defconfig | 25 +- .../linum-stm32h753bi/configs/nsh/defconfig | 7 +- .../linum-stm32h753bi/configs/nxffs/defconfig | 11 +- .../configs/qencoder/defconfig | 11 +- .../linum-stm32h753bi/configs/rndis/defconfig | 11 +- .../configs/sdcard/defconfig | 11 +- .../linum-stm32h753bi/configs/sdram/defconfig | 9 +- .../configs/socketcan/defconfig | 7 +- .../linum-stm32h753bi/configs/tone/defconfig | 19 +- .../configs/usbmsc-sdcard/defconfig | 15 +- .../configs/usbnsh/defconfig | 11 +- .../configs/zmodem/defconfig | 13 +- .../stm32h7/linum-stm32h753bi/include/board.h | 4 +- .../linum-stm32h753bi/src/CMakeLists.txt | 6 +- .../stm32h7/linum-stm32h753bi/src/Makefile | 6 +- .../linum-stm32h753bi/src/linum-stm32h753bi.h | 6 +- .../linum-stm32h753bi/src/stm32_bringup.c | 12 +- .../stm32h7/linum-stm32h753bi/src/stm32_lcd.c | 2 +- .../linum-stm32h753bi/src/stm32_mfrc522.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_pwm.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_spi.c | 8 +- .../linum-stm32h753bi/src/stm32_touchscreen.c | 4 +- .../stm32h7/linum-stm32h753bi/src/stm32_usb.c | 4 +- .../nucleo-h723zg/configs/netnsh/defconfig | 27 +- .../nucleo-h723zg/configs/nsh/defconfig | 9 +- .../nucleo-h723zg/configs/oa_tc6/defconfig | 11 +- .../stm32h7/nucleo-h723zg/src/CMakeLists.txt | 4 +- boards/arm/stm32h7/nucleo-h723zg/src/Makefile | 4 +- .../stm32h7/nucleo-h723zg/src/nucleo-h723zg.h | 8 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_adc.c | 28 +- .../stm32h7/nucleo-h723zg/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h723zg/src/stm32_bringup.c | 8 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_spi.c | 30 +- .../arm/stm32h7/nucleo-h723zg/src/stm32_usb.c | 2 +- .../nucleo-h743zi/configs/capture/defconfig | 7 +- .../nucleo-h743zi/configs/composite/defconfig | 9 +- .../nucleo-h743zi/configs/elf/defconfig | 5 +- .../configs/mcuboot-app/defconfig | 21 +- .../configs/mcuboot-loader/defconfig | 5 +- .../nucleo-h743zi/configs/netnsh/defconfig | 23 +- .../nucleo-h743zi/configs/nsh/defconfig | 3 +- .../configs/nxboot-app/defconfig | 5 +- .../configs/nxboot-loader/defconfig | 5 +- .../configs/nxlines_oled/defconfig | 5 +- .../configs/otg_fs_host/defconfig | 7 +- .../nucleo-h743zi/configs/pwm/defconfig | 31 +- .../nucleo-h743zi/configs/rndis/defconfig | 7 +- .../stm32h7/nucleo-h743zi/src/CMakeLists.txt | 6 +- boards/arm/stm32h7/nucleo-h743zi/src/Makefile | 6 +- .../stm32h7/nucleo-h743zi/src/nucleo-h743zi.h | 10 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_adc.c | 28 +- .../stm32h7/nucleo-h743zi/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h743zi/src/stm32_bringup.c | 38 +- .../nucleo-h743zi/src/stm32_lsm303agr.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c | 6 +- .../stm32h7/nucleo-h743zi/src/stm32_mmcsd.c | 2 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_spi.c | 30 +- .../arm/stm32h7/nucleo-h743zi/src/stm32_usb.c | 4 +- .../nucleo-h743zi2/configs/jumbo/defconfig | 27 +- .../nucleo-h743zi2/configs/netnsh/defconfig | 23 +- .../nucleo-h743zi2/configs/nsh/defconfig | 3 +- .../nucleo-h743zi2/configs/pysim/defconfig | 53 +- .../configs/socketcan/defconfig | 7 +- .../stm32h7/nucleo-h743zi2/src/CMakeLists.txt | 2 +- .../arm/stm32h7/nucleo-h743zi2/src/Makefile | 2 +- .../nucleo-h743zi2/src/nucleo-h743zi2.h | 8 +- .../stm32h7/nucleo-h743zi2/src/stm32_adc.c | 20 +- .../stm32h7/nucleo-h743zi2/src/stm32_boot.c | 2 +- .../nucleo-h743zi2/src/stm32_bringup.c | 14 +- .../stm32h7/nucleo-h743zi2/src/stm32_pwm.c | 4 +- .../stm32h7/nucleo-h743zi2/src/stm32_usb.c | 4 +- boards/arm/stm32h7/nucleo-h745zi/Kconfig | 2 +- .../nucleo-h745zi/configs/nsh_cm4/defconfig | 3 +- .../configs/nsh_cm4_rptun/defconfig | 1 + .../nucleo-h745zi/configs/nsh_cm7/defconfig | 3 +- .../configs/nsh_cm7_rptun/defconfig | 3 +- .../nucleo-h745zi/configs/pysim_cm7/defconfig | 53 +- .../stm32h7/nucleo-h745zi/scripts/flash.ld | 4 +- .../stm32h7/nucleo-h745zi/scripts/flash_m4.ld | 6 +- boards/arm/stm32h7/nucleo-h745zi/src/Makefile | 2 +- .../stm32h7/nucleo-h745zi/src/nucleo-h745zi.h | 10 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_adc.c | 20 +- .../stm32h7/nucleo-h745zi/src/stm32_boot.c | 4 +- .../stm32h7/nucleo-h745zi/src/stm32_bringup.c | 14 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h745zi/src/stm32_usb.c | 4 +- .../nucleo-h753zi/configs/crypto/defconfig | 5 +- .../nucleo-h753zi/configs/jumbo/defconfig | 23 +- .../nucleo-h753zi/configs/netnsh/defconfig | 23 +- .../nucleo-h753zi/configs/nsh/defconfig | 3 +- .../nucleo-h753zi/configs/pysim/defconfig | 53 +- .../nucleo-h753zi/configs/socketcan/defconfig | 7 +- .../stm32h7/nucleo-h753zi/src/CMakeLists.txt | 2 +- boards/arm/stm32h7/nucleo-h753zi/src/Makefile | 2 +- .../stm32h7/nucleo-h753zi/src/nucleo-h753zi.h | 8 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_adc.c | 20 +- .../stm32h7/nucleo-h753zi/src/stm32_boot.c | 2 +- .../stm32h7/nucleo-h753zi/src/stm32_bringup.c | 14 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c | 4 +- .../arm/stm32h7/nucleo-h753zi/src/stm32_usb.c | 4 +- .../openh743i/configs/composite_fs/defconfig | 7 +- .../openh743i/configs/composite_hs/defconfig | 11 +- .../stm32h7/openh743i/configs/nsh/defconfig | 3 +- .../configs/usbdev_hs_host_fs/defconfig | 13 +- .../arm/stm32h7/openh743i/src/CMakeLists.txt | 2 +- boards/arm/stm32h7/openh743i/src/Makefile | 2 +- boards/arm/stm32h7/openh743i/src/openh743i.h | 4 +- boards/arm/stm32h7/openh743i/src/stm32_boot.c | 2 +- .../arm/stm32h7/openh743i/src/stm32_bringup.c | 4 +- .../arm/stm32h7/openh743i/src/stm32_sdmmc.c | 4 +- boards/arm/stm32h7/openh743i/src/stm32_usb.c | 6 +- .../portenta-h7/configs/jumbo_cm7/defconfig | 7 +- .../portenta-h7/configs/nsh_cm7/defconfig | 3 +- .../arm/stm32h7/portenta-h7/scripts/flash.ld | 4 +- .../stm32h7/portenta-h7/scripts/flash_m4.ld | 6 +- .../stm32h7/portenta-h7/src/stm32_bringup.c | 8 +- .../stm32h745i-disco/configs/lvgl/defconfig | 27 +- .../stm32h745i-disco/configs/netnsh/defconfig | 29 +- .../stm32h745i-disco/configs/nsh/defconfig | 9 +- .../configs/nsh_cm4/defconfig | 7 +- .../configs/nsh_cm4_rptun/defconfig | 5 +- .../configs/nsh_cm7/defconfig | 7 +- .../configs/nsh_cm7_rptun/defconfig | 7 +- .../configs/touchtest/defconfig | 11 +- .../stm32h7/stm32h745i-disco/include/board.h | 2 +- .../stm32h7/stm32h745i-disco/scripts/flash.ld | 6 +- .../stm32h745i-disco/scripts/flash_m4.ld | 6 +- .../stm32h745i-disco/src/CMakeLists.txt | 4 +- .../arm/stm32h7/stm32h745i-disco/src/Makefile | 4 +- .../stm32h7/stm32h745i-disco/src/stm32_boot.c | 2 +- .../stm32h745i-disco/src/stm32_bringup.c | 2 +- .../stm32h745i-disco/src/stm32_ft5x06.c | 4 +- .../stm32h7/stm32h745i-disco/src/stm32_lcd.c | 2 +- .../stm32h7/stm32h745i-disco/src/stm32_usb.c | 4 +- .../stm32h745i-disco/src/stm32h745i_disco.h | 6 +- .../stm32h747i-disco/configs/nsh/defconfig | 5 +- .../stm32h747i-disco/src/CMakeLists.txt | 6 +- .../arm/stm32h7/stm32h747i-disco/src/Makefile | 6 +- .../stm32h7/stm32h747i-disco/src/stm32_adc.c | 20 +- .../stm32h7/stm32h747i-disco/src/stm32_boot.c | 4 +- .../stm32h747i-disco/src/stm32_bringup.c | 8 +- .../stm32h7/stm32h747i-disco/src/stm32_spi.c | 28 +- .../stm32h7/stm32h747i-disco/src/stm32_usb.c | 6 +- .../stm32h747i-disco/src/stm32h747i-disco.h | 4 +- .../stm32h750b-dk/configs/lvgl/defconfig | 23 +- .../arm/stm32h7/stm32h750b-dk/include/board.h | 2 +- .../stm32h7/stm32h750b-dk/scripts/flash.ld | 6 +- .../stm32h7/stm32h750b-dk/scripts/flash_m4.ld | 6 +- .../stm32h7/stm32h750b-dk/src/CMakeLists.txt | 4 +- boards/arm/stm32h7/stm32h750b-dk/src/Makefile | 4 +- .../stm32h7/stm32h750b-dk/src/stm32_boot.c | 2 +- .../stm32h7/stm32h750b-dk/src/stm32_bringup.c | 2 +- .../stm32h7/stm32h750b-dk/src/stm32_ft5x06.c | 4 +- .../arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c | 2 +- .../arm/stm32h7/stm32h750b-dk/src/stm32_usb.c | 4 +- .../stm32h7/stm32h750b-dk/src/stm32h750b-dk.h | 6 +- .../weact-stm32h743/configs/nsh/defconfig | 3 +- .../weact-stm32h743/configs/sdcard/defconfig | 9 +- .../weact-stm32h743/configs/st7735/defconfig | 5 +- .../weact-stm32h743/configs/usbnsh/defconfig | 7 +- .../weact-stm32h743/src/CMakeLists.txt | 2 +- .../arm/stm32h7/weact-stm32h743/src/Makefile | 2 +- .../stm32h7/weact-stm32h743/src/stm32_boot.c | 6 +- .../stm32h7/weact-stm32h743/src/stm32_spi.c | 4 +- .../stm32h7/weact-stm32h743/src/stm32_usb.c | 2 +- .../weact-stm32h743/src/weact-stm32h743.h | 6 +- .../weact-stm32h750/configs/nsh/defconfig | 3 +- .../weact-stm32h750/configs/sdcard/defconfig | 9 +- .../weact-stm32h750/configs/st7735/defconfig | 5 +- .../weact-stm32h750/configs/usbnsh/defconfig | 7 +- .../weact-stm32h750/src/CMakeLists.txt | 6 +- .../arm/stm32h7/weact-stm32h750/src/Makefile | 2 +- .../stm32h7/weact-stm32h750/src/stm32_boot.c | 6 +- .../stm32h7/weact-stm32h750/src/stm32_spi.c | 4 +- .../stm32h7/weact-stm32h750/src/stm32_usb.c | 2 +- .../weact-stm32h750/src/weact-stm32h750.h | 6 +- 286 files changed, 3865 insertions(+), 9629 deletions(-) diff --git a/Documentation/components/drivers/character/timers/capture.rst b/Documentation/components/drivers/character/timers/capture.rst index 026174e83a1..50208b54f37 100644 --- a/Documentation/components/drivers/character/timers/capture.rst +++ b/Documentation/components/drivers/character/timers/capture.rst @@ -109,7 +109,7 @@ To enable the capture driver, enable the following configuration options: * ``CONFIG_CAPTURE`` - Enable the capture driver framework * ``CONFIG_CAPTURE_NOTIFY`` - Enable signal notification support for edge events * ``CONFIG_FAKE_CAPTURE`` - Enable fake capture driver for testing (generates 10Hz signal with 50% duty cycle) -* ``CONFIG_STM32H7_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) +* ``CONFIG_STM32_TIM4_CAP`` (for STM32H7 Timer 4, platform-specific) The ``CONFIG_CAPTURE`` option enables the lower-half driver and registers the ``/dev/capture`` device. diff --git a/Documentation/guides/renode.rst b/Documentation/guides/renode.rst index b3918d2e8ca..ccafddf944f 100644 --- a/Documentation/guides/renode.rst +++ b/Documentation/guides/renode.rst @@ -119,7 +119,7 @@ nucleo-h743zi ============= Renode doesn't support ``PWR_CSR1_ACTVOSRDY`` bit so we have to disable -it with ``CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY=y``. +it with ``CONFIG_STM32_PWR_IGNORE_ACTVOSRDY=y``. Renode script:: diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index bcba3e81df6..0adfaf55625 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -721,7 +721,7 @@ After that check if your PC recognized the usb driver:: [27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk [27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. -**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c +**OBS:** This example disable the macro CONFIG_STM32_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c netnsh ------ diff --git a/Documentation/platforms/arm/stm32h7/index.rst b/Documentation/platforms/arm/stm32h7/index.rst index b042e33c30c..61e1f4387be 100644 --- a/Documentation/platforms/arm/stm32h7/index.rst +++ b/Documentation/platforms/arm/stm32h7/index.rst @@ -114,7 +114,7 @@ The selection of the core for which the image is build is made using options: - ``CONFIG_ARCH_CHIP_STM32H7_CORTEXM4`` - selects Cortex-M4 core Support for the CM7 core is always enabled, support for the CM4 core is controlled -with the ``CONFIG_STM32H7_CORTEXM4_ENABLED`` option. +with the ``CONFIG_STM32_CORTEXM4_ENABLED`` option. Interprocessor communication between cores is realized with the NuttX RPTUN device based on the OpenAMP framework. ``HSEM`` is used for synchronization and diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ea411453337..b4c6ffbadf3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -639,6 +639,7 @@ config ARCH_CHIP_STM32F7 config ARCH_CHIP_STM32H7 bool "STMicro STM32 H7" + select ARCH_CHIP_STM32 select ARCH_HAVE_MPU select ARCH_HAVE_I2CRESET select ARCH_HAVE_PROGMEM diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index 2aa62e17e93..aab8d553109 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -91,10 +91,10 @@ /* Size SRAM */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || defined(CONFIG_STM32_STM32H7X3XX) || defined(CONFIG_STM32_STM32H7X5XX) /* Memory */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */ # define STM32_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */ @@ -152,7 +152,7 @@ # define STM32_NSAI (4) /* (4) SAI1-4*/ # define STM32_NCAN (2) /* (2) CAN1-2 */ # define STM32_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) /* Memory */ # define STM32_SRAM_SIZE (1024*1024) /* 1024Kb SRAM on AXI bus Matrix (D1) */ @@ -206,7 +206,7 @@ # define STM32_NSAI (4) /* (4) SAI1-4*/ # define STM32_NCAN (2) /* (2) CAN1-2 */ # define STM32_NSDIO (2) /* (2) SDIO */ -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) /* Memory */ # define STM32_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ @@ -259,13 +259,13 @@ /* Diversification based on Family and package */ -#if defined(CONFIG_STM32H7_HAVE_ETHERNET) +#if defined(CONFIG_STM32_HAVE_ETHERNET) # define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ #else # define STM32_NETHERNET 0 /* No 100/100 Ethernet MAC */ #endif -#if defined(CONFIG_STM32H7_HAVE_FMC) +#if defined(CONFIG_STM32_HAVE_FMC) # define STM32_NFMC 1 /* Have FMC memory controller */ #else # define STM32_NFMC 0 /* No FMC memory controller */ diff --git a/arch/arm/include/stm32h7/irq.h b/arch/arm/include/stm32h7/irq.h index 427d6b8c1f2..24cfc5f4add 100644 --- a/arch/arm/include/stm32h7/irq.h +++ b/arch/arm/include/stm32h7/irq.h @@ -69,19 +69,19 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # if CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # include # else # include # endif -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/CMakeLists.txt b/arch/arm/src/stm32h7/CMakeLists.txt index e1636a3fb8d..b226502c093 100644 --- a/arch/arm/src/stm32h7/CMakeLists.txt +++ b/arch/arm/src/stm32h7/CMakeLists.txt @@ -35,7 +35,7 @@ list( stm32_serial.c stm32_uid.c) -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_flash.c) endif() @@ -43,7 +43,7 @@ if(CONFIG_ARCH_STM32H7_DUALCORE) list(APPEND SRCS stm32_dualcore.c) endif() -if(CONFIG_STM32H7_HSEM) +if(CONFIG_STM32_HSEM) list(APPEND SRCS stm32_hsem.c) endif() @@ -57,7 +57,7 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32H7_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) endif() @@ -73,47 +73,51 @@ if(CONFIG_ARMV7M_DTCM) list(APPEND SRCS stm32_dtcm.c) endif() -if(CONFIG_STM32H7_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32H7_FDCAN) +if(CONFIG_STM32_FDCAN) list(APPEND SRCS stm32_fdcan_sock.c) endif() -if(CONFIG_STM32H7_BBSRAM) +if(CONFIG_STM32_BBSRAM) list(APPEND SRCS stm32_bbsram.c) endif() -if(CONFIG_STM32H7_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32_dma.c) endif() -if(CONFIG_STM32H7_FMC) +if(CONFIG_STM32_FMC) list(APPEND SRCS stm32_fmc.c) endif() -if(CONFIG_STM32H7_IWDG OR CONFIG_STM32H7_RTC_LSICLOCK) +if(CONFIG_STM32_RNG) + list(APPEND SRCS stm32_rng.c) +endif() + +if(CONFIG_STM32_IWDG OR CONFIG_STM32_RTC_LSICLOCK) list(APPEND SRCS stm32_lsi.c) endif() -if(CONFIG_STM32H7_RTC_LSECLOCK) +if(CONFIG_STM32_RTC_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32H7_I2C) +if(CONFIG_STM32_I2C) list(APPEND SRCS stm32_i2c.c) endif() -if(CONFIG_STM32H7_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() -if(CONFIG_STM32H7_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32_qspi.c) endif() -if(CONFIG_STM32H7_RTC) +if(CONFIG_STM32_RTC) list(APPEND SRCS stm32_rtc.c) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32_exti_alarm.c) @@ -126,7 +130,7 @@ if(CONFIG_STM32H7_RTC) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -134,7 +138,7 @@ if(CONFIG_SPI_SLAVE) list(APPEND SRCS stm32_spi_slave.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -142,7 +146,7 @@ if(CONFIG_TIMER) list(APPEND SRCS stm32_tim_lowerhalf.c) endif() -if(CONFIG_STM32H7_TIMX_CAP) +if(CONFIG_STM32_TIMX_CAP) list(APPEND SRCS stm32_capture.c) endif() @@ -150,7 +154,7 @@ if(CONFIG_CAPTURE) list(APPEND SRCS stm32_capture_lowerhalf.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_ltdc.c) endif() @@ -169,15 +173,15 @@ if(CONFIG_USBHOST) endif() endif() -if(CONFIG_STM32H7_TIM) +if(CONFIG_STM32_TIM) list(APPEND SRCS stm32_tim.c) endif() -if(CONFIG_STM32H7_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32_lptim.c) endif() -if(CONFIG_STM32H7_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32_pwm.c) endif() @@ -185,7 +189,7 @@ if(CONFIG_PULSECOUNT) list(APPEND SRCS stm32_pulsecount.c) endif() -if(CONFIG_STM32H7_ETHMAC) +if(CONFIG_STM32_ETHMAC) list(APPEND SRCS stm32_ethernet.c) endif() @@ -204,12 +208,20 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32H7_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32_iwdg.c) endif() -if(CONFIG_STM32H7_WWDG) +if(CONFIG_STM32_WWDG) list(APPEND SRCS stm32_wwdg.c) endif() +if(CONFIG_STM32_CRYP AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_aes.c) +endif() + +if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_H7) + list(APPEND SRCS stm32_crypto.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index bc7c0670d88..90ec8b7febf 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -7,6 +7,51 @@ if ARCH_CHIP_STM32H7 comment "STM32 H7 Configuration Options" +config STM32_H7_PERIPHERALS + bool + default ARCH_CHIP_STM32H7 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_OTGFS + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART6 + select STM32_HAVE_HSEM + select STM32_HAVE_CSI + select STM32_HAVE_HSI48 + select STM32_HAVE_MDMA + select STM32_HAVE_BDMA + select STM32_HAVE_OTG_H7 + select STM32_HAVE_OTGHS + select STM32_HAVE_USART_RXFIFO_THRESHOLD + select STM32_HAVE_FDCAN_H7 + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 H7 Chip Selection" default ARCH_CHIP_STM32H743ZI @@ -14,34 +59,34 @@ choice config ARCH_CHIP_STM32H723VG bool "STM32H723VG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H723ZG bool "STM32H723ZG" - select STM32H7_STM32H7X3XX - select STM32H7_STM32H72XXX_OR_STM32H73XXX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_STM32H72XXX_OR_STM32H73XXX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_FDCAN3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_FDCAN3 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM, LQFP144 config ARCH_CHIP_STM32H743AG bool "STM32H743AG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -49,8 +94,8 @@ config ARCH_CHIP_STM32H743AG config ARCH_CHIP_STM32H743AI bool "STM32H743AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -58,8 +103,8 @@ config ARCH_CHIP_STM32H743AI config ARCH_CHIP_STM32H743BG bool "STM32H743BG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -67,8 +112,8 @@ config ARCH_CHIP_STM32H743BG config ARCH_CHIP_STM32H743BI bool "STM32H743BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -76,8 +121,8 @@ config ARCH_CHIP_STM32H743BI config ARCH_CHIP_STM32H743IG bool "STM32H743IG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -85,8 +130,8 @@ config ARCH_CHIP_STM32H743IG config ARCH_CHIP_STM32H743II bool "STM32H743II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -94,8 +139,8 @@ config ARCH_CHIP_STM32H743II config ARCH_CHIP_STM32H743VG bool "STM32H743VG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -103,8 +148,8 @@ config ARCH_CHIP_STM32H743VG config ARCH_CHIP_STM32H743VI bool "STM32H743VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -112,8 +157,8 @@ config ARCH_CHIP_STM32H743VI config ARCH_CHIP_STM32H743XG bool "STM32H743XG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -121,8 +166,8 @@ config ARCH_CHIP_STM32H743XG config ARCH_CHIP_STM32H743XI bool "STM32H743XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -130,8 +175,8 @@ config ARCH_CHIP_STM32H743XI config ARCH_CHIP_STM32H743ZG bool "STM32H743ZG" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, @@ -139,8 +184,8 @@ config ARCH_CHIP_STM32H743ZG config ARCH_CHIP_STM32H743ZI bool "STM32H743ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, @@ -148,8 +193,8 @@ config ARCH_CHIP_STM32H743ZI config ARCH_CHIP_STM32H745BG bool "STM32H745BG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -157,8 +202,8 @@ config ARCH_CHIP_STM32H745BG config ARCH_CHIP_STM32H745BI bool "STM32H745BI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -166,8 +211,8 @@ config ARCH_CHIP_STM32H745BI config ARCH_CHIP_STM32H745IG bool "STM32H745IG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -175,8 +220,8 @@ config ARCH_CHIP_STM32H745IG config ARCH_CHIP_STM32H745II bool "STM32H745II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -184,8 +229,8 @@ config ARCH_CHIP_STM32H745II config ARCH_CHIP_STM32H745XG bool "STM32H745XG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -193,8 +238,8 @@ config ARCH_CHIP_STM32H745XG config ARCH_CHIP_STM32H745XI bool "STM32H745XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -202,8 +247,8 @@ config ARCH_CHIP_STM32H745XI config ARCH_CHIP_STM32H745ZG bool "STM32H745ZG" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_G + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 1024 Kb FLASH, 1024K Kb SRAM, @@ -211,8 +256,8 @@ config ARCH_CHIP_STM32H745ZG config ARCH_CHIP_STM32H745ZI bool "STM32H745ZI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM, @@ -220,165 +265,170 @@ config ARCH_CHIP_STM32H745ZI config ARCH_CHIP_STM32H747XI bool "STM32H747XI" - select STM32H7_STM32H7X7XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X7XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_SMPS + select STM32_HAVE_SMPS ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM TFBGA240 config ARCH_CHIP_STM32H750VB bool "STM32H750VB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100 config ARCH_CHIP_STM32H750ZB bool "STM32H750ZB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H750IB bool "STM32H750IB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176 or UFBGA176+25 config ARCH_CHIP_STM32H750XB bool "STM32H750XB" - select STM32H7_STM32H7X0XX - select STM32H7_FLASH_CONFIG_B + select STM32_STM32H7X0XX + select STM32_FLASH_CONFIG_B select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7+M4, 128 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240+25 config ARCH_CHIP_STM32H753AI bool "STM32H753AI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 config ARCH_CHIP_STM32H753BI bool "STM32H753BI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP208 config ARCH_CHIP_STM32H753II bool "STM32H753II" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H753VI bool "STM32H753VI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 config ARCH_CHIP_STM32H753XI bool "STM32H753XI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 config ARCH_CHIP_STM32H753ZI bool "STM32H753ZI" - select STM32H7_STM32H7X3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_CRYP + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 config ARCH_CHIP_STM32H7B3LI bool "STM32H7B3LI" - select STM32H7_STM32H7B3XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7B3XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_L - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_CRYP + select STM32_HAVE_SMPS + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1376 Kb SRAM, with cryptographic accelerator, TFBGA225 config ARCH_CHIP_STM32H755II bool "STM32H755II" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 config ARCH_CHIP_STM32H755XI bool "STM32H755XI" - select STM32H7_STM32H7X5XX - select STM32H7_FLASH_CONFIG_I + select STM32_STM32H7X5XX + select STM32_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 - select STM32H7_HAVE_CRYP + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CRYP + select STM32_HAVE_IP_CRYPTO_H7 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, TFBGA240 endchoice # STM32 H7 Chip Selection -config STM32H7_HAVE_SMPS - bool - default n - -config STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY - bool - default n - -config STM32H7_PWR_DIRECT_SMPS_SUPPLY +config STM32_PWR_DIRECT_SMPS_SUPPLY bool "Use direct SMPS supply mode" - depends on STM32H7_HAVE_SMPS + depends on STM32_HAVE_SMPS default n -config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY +config STM32_PWR_EXTERNAL_SOURCE_SUPPLY bool "Use external source as power supply" default n ---help--- @@ -386,8 +436,8 @@ config STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY choice prompt "STM32 H7 Power Supply Selection" - default STM32H7_PWR_DEFAULT_SUPPLY - depends on STM32H7_HAVE_SMPS && !STM32H7_HAVE_PWR_DIRECT_SMPS_SUPPLY + default STM32_PWR_DEFAULT_SUPPLY + depends on STM32_HAVE_SMPS && !STM32_HAVE_PWR_DIRECT_SMPS_SUPPLY ---help--- The STM32H7x5 and STM32H7x7 support power supply configurations for the VCORE core domain and an external supply, by configuring the SMPS step-down converter and voltage regulator. @@ -395,15 +445,15 @@ choice Currently the only supported modes are Direct SMPS supply and LDO supply. -config STM32H7_PWR_DEFAULT_SUPPLY +config STM32_PWR_DEFAULT_SUPPLY bool "Default" -config STM32H7_PWR_LDO_SUPPLY +config STM32_PWR_LDO_SUPPLY bool "Use LDO supply mode" endchoice # "STM32 H7 Power Supply Selection" -config STM32H7_PWR_IGNORE_ACTVOSRDY +config STM32_PWR_IGNORE_ACTVOSRDY bool "Ignore PWR_CSR1_ACTVOSRDY bit" default n ---help--- @@ -411,38 +461,45 @@ config STM32H7_PWR_IGNORE_ACTVOSRDY This is workaround for Renode simulation that doesn't implement this feature. config STM32H7_IO_CONFIG_A + # Package designator A bool default n config STM32H7_IO_CONFIG_B + # Package designator B bool default n config STM32H7_IO_CONFIG_I + # Package designator I bool default n config STM32H7_IO_CONFIG_L + # Package designator L bool default n config STM32H7_IO_CONFIG_V + # Package designator V bool default n config STM32H7_IO_CONFIG_X + # Package designator X bool default n config STM32H7_IO_CONFIG_Z + # Package designator Z bool default n config ARCH_STM32H7_DUALCORE bool default n - select STM32H7_HSEM if !STM32H7_CORTEXM4_DISABLED - select STM32H7_HAVE_CM4 + select STM32_HSEM if !STM32_CORTEXM4_DISABLED + select STM32_HAVE_CM4 choice prompt "STM32 H7 Core selection" @@ -463,141 +520,165 @@ config ARCH_CHIP_STM32H7_CORTEXM4 endchoice # STM32 H7 Core selection -config STM32H7_STM32H7X0XX +config STM32_STM32H7X0XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7X3XX +config STM32_STM32H7X3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7B3XX +config STM32_STM32H7B3XX bool default n select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG -config STM32H7_STM32H7X5XX +config STM32_STM32H7X5XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_GPIOG if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 if !STM32H7_IO_CONFIG_V - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_SMPS - select STM32H7_HAVE_RNG + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF if !STM32H7_IO_CONFIG_V + select STM32_HAVE_GPIOG if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 if !STM32H7_IO_CONFIG_V + select STM32_HAVE_SPI6 + select STM32_HAVE_SMPS + select STM32_HAVE_RNG -config STM32H7_STM32H7X7XX +config STM32_STM32H7X7XX bool default n select ARCH_STM32H7_DUALCORE select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU - select STM32H7_HAVE_LTDC - select STM32H7_HAVE_ETHERNET - select STM32H7_HAVE_FMC - select STM32H7_HAVE_GPIOF - select STM32H7_HAVE_GPIOG - select STM32H7_HAVE_SPI4 - select STM32H7_HAVE_SPI5 - select STM32H7_HAVE_SPI6 - select STM32H7_HAVE_RNG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_LTDC + select STM32_HAVE_ETHERNET + select STM32_HAVE_FMC + select STM32_HAVE_GPIOF + select STM32_HAVE_GPIOG + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_RNG # The reduced SRAM configuration STM32H72X and STM32H73X -config STM32H7_STM32H72XXX_OR_STM32H73XXX +config STM32_STM32H72XXX_OR_STM32H73XXX bool default n -config STM32H7_FLASH_CONFIG_B - bool - default n - -config STM32H7_FLASH_CONFIG_G - bool - default n - -config STM32H7_FLASH_CONFIG_I - bool - default n - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32H7 - default STM32H7_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32H7 series parts numbering (sans the package type) ends with a - letter that designates the FLASH size. - - Designator Size in KiB - B 128 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based - on that designator or the default smaller size if there is no last - character designator is present in the STM32 Chip Selection. - - Examples: - - If the STM32H743ZI is chosen, the Flash configuration would be - 'I', if a variant of the part is released in the future one - could simply select another designator here. - - If an STM32H7xxx Series parts is chosen the default Flash - configuration will be set herein and can be changed. - -config STM32H7_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32H7_FLASH_OVERRIDE_B - bool "B 128KiB" - -config STM32H7_FLASH_OVERRIDE_G - bool "G 1048KiB" - -config STM32H7_FLASH_OVERRIDE_I - bool "I 2048KiB" - -endchoice # "Override Flash Size Designator" - -config STM32H7_FLASH_CR_PSIZE +config STM32_FLASH_CR_PSIZE int "Flash program size width" depends on ARCH_CHIP_STM32H7 default 3 @@ -611,7 +692,7 @@ config STM32H7_FLASH_CR_PSIZE 2: 32 bits 3: 64 bits (default) -config STM32H7_AXI_SRAM_CORRUPTION_WAR +config STM32_AXI_SRAM_CORRUPTION_WAR bool "Errata 2.2.9 Reading from AXI SRAM data read corruption Workaround" default y ---help--- @@ -631,47 +712,36 @@ if ARCH_STM32H7_DUALCORE if ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM4_ENABLED +config STM32_CORTEXM4_ENABLED bool "Enable support for M4 core" default y -config STM32H7_CORTEXM7_BOOTM4 +config STM32_CORTEXM7_BOOTM4 bool "Boot M4 core" - select STM32H7_SYSCFG - default y if STM32H7_CORTEXM4_ENABLED + select STM32_SYSCFG + default y if STM32_CORTEXM4_ENABLED default n endif # ARCH_CHIP_STM32H7_CORTEXM7 -config STM32H7_CORTEXM7_FLASH_SIZE +config STM32_CORTEXM7_FLASH_SIZE int "Flash reserved for M7 core" - default 1048576 if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default 1048576 if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default 2097152 -config STM32H7_CORTEXM7_SHMEM +config STM32_CORTEXM7_SHMEM bool select ARM_MPU if ARCH_CHIP_STM32H7_CORTEXM7 - default y if STM32H7_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 + default y if STM32_CORTEXM4_ENABLED || ARCH_CHIP_STM32H7_CORTEXM4 default n -config STM32H7_SHMEM_SRAM3 +config STM32_SHMEM_SRAM3 bool "Use SRAM3 as shared memory" - depends on STM32H7_CORTEXM7_SHMEM + depends on STM32_CORTEXM7_SHMEM default y endif # ARCH_STM32H7_DUALCORE -config STM32_HAVE_OTA_PARTITION - bool - default n - -config STM32H7_PROGMEM - bool "Flash progmem support" - default n - ---help--- - Add progmem support, start block and end block options are provided to - obtain an uniform flash memory mapping. - menu "Application Image Configuration" choice prompt "Application Image Format" @@ -711,1650 +781,7 @@ endchoice # Application Image Format endmenu # Application Image Configuration -menu "STM32H7 Peripheral Selection" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32H7_HAVE_CM4 - bool - default n - -config STM32H7_HAVE_LTDC - bool - default n - -config STM32H7_HAVE_ETHERNET - bool - default n - -config STM32H7_HAVE_PHY_POLLED - bool - default n - -config STM32H7_HAVE_FMC - bool - default n - -config STM32H7_HAVE_GPIOF - bool - default n - -config STM32H7_HAVE_GPIOG - bool - default n - -config STM32H7_HAVE_SPI4 - bool - default n - -config STM32H7_HAVE_SPI5 - bool - default n - -config STM32H7_HAVE_SPI6 - bool - default n - -config STM32H7_HAVE_FDCAN1 - bool - default n - -config STM32H7_HAVE_FDCAN2 - bool - default n - -config STM32H7_HAVE_FDCAN3 - bool - default n - -config STM32H7_HAVE_RNG - bool - default n - -config STM32H7_HAVE_CRYP - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32H7_ADC - bool - default n - -config STM32H7_FDCAN - bool - select NET_CAN_HAVE_ERRORS - select NET_CAN_HAVE_CANFD - select NET_CAN_EXTID - select NET_CAN_HAVE_TX_DEADLINE - default n - -config STM32H7_DAC - bool - default n - -config STM32H7_DMA - bool - default n - -config STM32H7_I2C - bool - default n - -config STM32H7_SAI - bool - default n - -config STM32H7_SDMMC - bool - default n - -config STM32H7_SPI - bool - default n - -config STM32H7_SPI_DMA - bool - default n - -config STM32H7_TIM - bool - default n - -config STM32H7_LPTIM - bool - default n - -config STM32H7_HSEM - bool "Hardware semaphore" - default n - -config STM32H7_RTC - bool "RTC" - default n - select RTC - -config STM32H7_CSI - bool "CSI Low-speed internal oscillator (4MHz)" - default n - -config STM32H7_HSI48 - bool "HSI48 High-speed 48MHz internal oscillator" - default n - -config STM32H7_PWR - bool "PWR" - default n - -config STM32H7_PWM - bool - default n - -config STM32H7_USART - bool - default n - -# These are the peripheral selections proper -config STM32H7_ADC1 - bool "ADC1" - default n - select STM32H7_ADC - -config STM32H7_ADC2 - bool "ADC2" - default n - select STM32H7_ADC - -config STM32H7_ADC3 - bool "ADC3" - default n - select STM32H7_ADC - -config STM32H7_RNG - bool "RNG" - default n - depends on STM32H7_HAVE_RNG - select ARCH_HAVE_RNG - -config STM32H7_CRC - bool "CRC" - default n - -config STM32H7_CRYP - bool "CRYP" - default n - depends on STM32H7_HAVE_CRYP - -config STM32H7_BKPSRAM - bool "Enable BKP RAM Domain" - select STM32H7_PWR - default n - -config STM32H7_DMA1 - bool "DMA1" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_DMA2 - bool "DMA2" - default n - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_MDMA - bool "MDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_BDMA - bool "BDMA" - default n - depends on EXPERIMENTAL - select STM32H7_DMA - select ARCH_DMA - -config STM32H7_ETHMAC - bool "Ethernet MAC" - default n - depends on STM32H7_HAVE_ETHERNET - select NETDEVICES - select ARCH_HAVE_PHY - select STM32H7_HAVE_PHY_POLLED - -config STM32H7_FMC - bool "FMC" - default n - depends on STM32H7_HAVE_FMC - ---help--- - Enable Flexible Memory Controller. - To correctly configure FMC for your hardware, you will have to define - a number of macros in your board.h file. See stm32_fmc.c for directions. - -config STM32H7_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTGHS - bool "OTG FS/HS" - default n - depends on EXPERIMENTAL - select USBHOST_HAVE_ASYNCH if USBHOST - -config STM32H7_OTG_SOFOUTPUT - bool "OTG SOF output" - default n - -config STM32H7_OTG_USBREGEN - bool "Enable USB voltage regulator" - default n - -config STM32H7_QSPI - bool "QuadSPI" - default n - -config STM32H7_USBDEV_REGDEBUG - bool "OTG USBDEV REGDEBUG" - default n - depends on USBDEV - -config STM32H7_USBHOST_REGDEBUG - bool "OTG USBHOST REGDEBUG" - default n - depends on USBHOST - -config STM32H7_USBHOST_PKTDUMP - bool "OTG USBHOST PKTDUMP" - default n - depends on USBHOST - -config STM32H7_SDMMC1 - bool "SDMMC1" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_SDMMC2 - bool "SDMMC2" - default n - select STM32H7_SDMMC - select ARCH_HAVE_SDIO - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - select SDIO_BLOCKSETUP - -config STM32H7_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32H7_WWDG - bool "WWDG" - default n - select WATCHDOG - -menu "STM32H7 FDCAN Selection" - -config STM32H7_FDCAN1 - bool "FDCAN1" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN2 - bool "FDCAN2" - default n - select STM32H7_FDCAN - -config STM32H7_FDCAN3 - bool "FDCAN3" - default n - select STM32H7_FDCAN - -endmenu # STM32H7 FDCAN Selection - -menu "STM32H7 I2C Selection" - -config STM32H7_I2C1 - bool "I2C1" - default n - select STM32H7_I2C - -config STM32H7_I2C2 - bool "I2C2" - default n - select STM32H7_I2C - -config STM32H7_I2C3 - bool "I2C3" - default n - select STM32H7_I2C - -config STM32H7_I2C4 - bool "I2C4" - default n - select STM32H7_I2C - -endmenu # STM32H7 I2C Selection - -config STM32H7_LTDC - bool "LTDC" - default n - select FB - depends on STM32H7_HAVE_LTDC - ---help--- - The STM32 LTDC is an LCD-TFT Display Controller available on - the STM32H7 devices. - It features a standard RGB888 parallel video interface (along - with HSYNC, VSYNC, etc.) for controlling TFT LCD displays. - In some STM32H7 devices the graphics signals can optionally - be output via DSI instead of the parallel interface: - See config options STM32H7_DSIHOST and STM32H7_LTDC_USE_DSI. - -menu "STM32H7 SPI Selection" - -config STM32H7_SPI1 - bool "SPI1" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI2 - bool "SPI2" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI3 - bool "SPI3" - default n - select SPI - select STM32H7_SPI - -config STM32H7_SPI4 - bool "SPI4" - default n - depends on STM32H7_HAVE_SPI4 - select SPI - select STM32H7_SPI - -config STM32H7_SPI5 - bool "SPI5" - default n - depends on STM32H7_HAVE_SPI5 - select SPI - select STM32H7_SPI - -config STM32H7_SPI6 - bool "SPI6" - default n - depends on STM32H7_HAVE_SPI6 - select SPI - select STM32H7_SPI - -endmenu # STM32H7 SPI Selection - -config STM32H7_SYSCFG - bool "SYSCFG" - default y - -menu "STM32H7 Timer Selection" - -config STM32H7_TIM1 - bool "TIM1" - default n - select STM32H7_TIM - -config STM32H7_TIM2 - bool "TIM2" - default n - select STM32H7_TIM - -config STM32H7_TIM3 - bool "TIM3" - default n - select STM32H7_TIM - -config STM32H7_TIM4 - bool "TIM4" - default n - select STM32H7_TIM - -config STM32H7_TIM5 - bool "TIM5" - default n - select STM32H7_TIM - -config STM32H7_TIM6 - bool "TIM6" - default n - select STM32H7_TIM - -config STM32H7_TIM7 - bool "TIM7" - default n - select STM32H7_TIM - -config STM32H7_TIM8 - bool "TIM8" - default n - select STM32H7_TIM - -config STM32H7_TIM12 - bool "TIM12" - default n - select STM32H7_TIM - -config STM32H7_TIM13 - bool "TIM13" - default n - select STM32H7_TIM - -config STM32H7_TIM14 - bool "TIM14" - default n - select STM32H7_TIM - -config STM32H7_TIM15 - bool "TIM15" - default n - select STM32H7_TIM - -config STM32H7_TIM16 - bool "TIM16" - default n - select STM32H7_TIM - -config STM32H7_TIM17 - bool "TIM17" - default n - select STM32H7_TIM - -endmenu # STM32H7 Timer Selection - -menu "STM32H7 Low-power Timer Selection" - -config STM32H7_LPTIM1 - bool "LPTIM1" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM2 - bool "LPTIM2" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM3 - bool "LPTIM3" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM4 - bool "LPTIM4" - default n - select STM32H7_LPTIM - -config STM32H7_LPTIM5 - bool "LPTIM5" - default n - select STM32H7_LPTIM - -endmenu # STM32H7 Low-power Timer Selection - -menu "STM32H7 U[S]ART Selection" - -config STM32H7_USART1 - bool "USART1" - default n - select USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART2 - bool "USART2" - default n - select USART2_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select STM32H7_USART - -config STM32H7_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART3_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART4_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART5_SERIALDRIVER - select STM32H7_USART - -config STM32H7_USART6 - bool "USART6" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select USART6_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART7 - bool "UART7" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART7_SERIALDRIVER - select STM32H7_USART - -config STM32H7_UART8 - bool "UART8" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select UART8_SERIALDRIVER - select STM32H7_USART - -endmenu # STM32H7 U[S]ART Selection -endmenu # STM32H7 Peripheral Selection - -config STM32H7_SYSCFG_IOCOMPENSATION - bool "SYSCFG I/O Compensation" - default n - select STM32H7_CSI - ---help--- - By default the I/O compensation cell is not used. However when the I/O - output buffer speed is configured in 50 MHz or 100 MHz mode, it is - recommended to use the compensation cell for slew rate control on I/O - tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply. - - The I/O compensation cell can be used only when the supply voltage ranges - from 2.4 to 3.6 V - -menu "OTG_HS Configuration" - depends on STM32H7_OTGHS - -config STM32H7_OTGHS_FS - bool "OTGHS in FS mode" - default n - -choice - prompt "ULPI Selection" - default STM32H7_OTGHS_NO_ULPI - -config STM32H7_OTGHS_NO_ULPI - bool "No External ULPI on board." - ---help--- - Select to indicate that there is no external ULPI PHY. This means the OTG_HS - peripheral must use the internal full-speed PHY and will be limited to - full-speed mode. - -config STM32H7_OTGHS_EXTERNAL_ULPI - bool "External ULPI" - ---help--- - Select to indicate the presence of an external ULPI PHY and use it. - -endchoice #"ULPI Selection" - -endmenu # OTG_HS Config - -menu "I2C Configuration" - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32H7_I2C - -config STM32H7_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32H7_I2C - -config STM32H7_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -config STM32H7_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32H7_I2C && !STM32H7_I2C_DYNTIMEO - -endmenu # "I2C Configuration" - -menu "OTG Configuration" - depends on STM32H7_OTGFS || STM32H7_OTGHS - -config OTG_ID_GPIO_DISABLE - bool "Disable the use of GPIO_OTG_ID pin." - default n - ---help--- - Disables/Enables the use of GPIO_OTG_ID pin. This allows non OTG use - cases to reuse this GPIO pin and ensure it is not set incorrectlty - during OS boot. - -choice - prompt "STM32H7 OTGFS role" - depends on STM32H7_OTGFS - default STM32H7_OTGFS_USBDEV if USBDEV - default STM32H7_OTGFS_HOST if !USBDEV && USBHOST - -config STM32H7_OTGFS_USBDEV - bool "OTGFS as USBDEV" - depends on USBDEV - -config STM32H7_OTGFS_HOST - bool "OTGFS as HOST" - depends on USBHOST - -endchoice # "STM32H7 OTGFS role" - -choice - prompt "STM32H7 OTGHS role (only USBDEV supported for now)" - depends on STM32H7_OTGHS - default STM32H7_OTGHS_USBDEV if USBDEV - -config STM32H7_OTGHS_USBDEV - bool "OTGHS as USBDEV" - depends on USBDEV - -endchoice # "STM32H7 OTGHS role" - -endmenu # OTG Configuration - -menu "SPI Configuration" - depends on STM32H7_SPI - -config STM32H7_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32H7_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32H7_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32H7_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32H7_SPI1 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32H7_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32H7_SPI1_COMMTYPE - int "SPI1 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI1 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI2_DMA - bool "SPI2 DMA" - default n - depends on STM32H7_SPI2 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI2 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI2_DMA_BUFFER - int "SPI2 DMA buffer size" - default 0 - depends on STM32H7_SPI2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2. - -config STM32H7_SPI2_COMMTYPE - int "SPI2 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI2 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI3_DMA - bool "SPI3 DMA" - default n - depends on STM32H7_SPI3 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI3 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI3_DMA_BUFFER - int "SPI3 DMA buffer size" - default 0 - depends on STM32H7_SPI3_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI3. - -config STM32H7_SPI3_COMMTYPE - int "SPI3 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI3 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI4_DMA - bool "SPI4 DMA" - default n - depends on STM32H7_SPI4 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI4 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI4_DMA_BUFFER - int "SPI4 DMA buffer size" - default 0 - depends on STM32H7_SPI4_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI4. - -config STM32H7_SPI4_COMMTYPE - int "SPI4 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI4 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI5_DMA - bool "SPI5 DMA" - default n - depends on STM32H7_SPI5 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI5 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI5_DMA_BUFFER - int "SPI5 DMA buffer size" - default 0 - depends on STM32H7_SPI5_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI5. - -config STM32H7_SPI5_COMMTYPE - int "SPI5 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI5 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -config STM32H7_SPI6_DMA - bool "SPI6 DMA" - default n - depends on STM32H7_SPI6 && !STM32H7_SPI_INTERRUPT - select STM32H7_SPI_DMA - ---help--- - Use DMA to improve SPI6 transfer performance. Cannot be used with STM32H7_SPI_INTERRUPT - -config STM32H7_SPI6_DMA_BUFFER - int "SPI6 DMA buffer size" - default 0 - depends on STM32H7_SPI6_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI6. - -config STM32H7_SPI6_COMMTYPE - int "SPI6 Operation mode" - default 0 - range 0 3 - depends on STM32H7_SPI6 - ---help--- - Select full-duplex (0), simplex tx (1), simplex rx (2) or half-duplex (3) - -endmenu # "SPI Configuration" - -menu "U[S]ART Configuration" - depends on STM32H7_USART - -if STM32H7_USART1 - -config USART1_RS485 - bool "RS-485 on USART1" - default n - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXFIFO_THRES - int "USART1 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART1 - -if STM32H7_USART2 - -config USART2_RS485 - bool "RS-485 on USART2" - default n - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXFIFO_THRES - int "USART2 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART2 - -if STM32H7_USART3 - -config USART3_RS485 - bool "RS-485 on USART3" - default n - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXFIFO_THRES - int "USART3 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART3 - -if STM32H7_UART4 - -config UART4_RS485 - bool "RS-485 on UART4" - default n - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXFIFO_THRES - int "UART4 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART4 - -if STM32H7_UART5 - -config UART5_RS485 - bool "RS-485 on UART5" - default n - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXFIFO_THRES - int "UART5 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART5 - -if STM32H7_USART6 - -config USART6_RS485 - bool "RS-485 on USART6" - default n - ---help--- - Enable RS-485 interface on USART6. Your board config will have to - provide GPIO_USART6_RS485_DIR pin definition. - -config USART6_RS485_DIR_POLARITY - int "USART6 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART6_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART6. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART6_RXFIFO_THRES - int "USART6 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_USART - -if STM32H7_UART7 - -config UART7_RS485 - bool "RS-485 on UART7" - default n - ---help--- - Enable RS-485 interface on UART7. Your board config will have to - provide GPIO_UART7_RS485_DIR pin definition. - -config UART7_RS485_DIR_POLARITY - int "UART7 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART7_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART7. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART7_RXFIFO_THRES - int "UART7 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART7 - -if STM32H7_UART8 - -config UART8_RS485 - bool "RS-485 on UART8" - default n - ---help--- - Enable RS-485 interface on UART8. Your board config will have to - provide GPIO_UART8_RS485_DIR pin definition. - -config UART8_RS485_DIR_POLARITY - int "UART8 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART8_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART8. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART8_RXFIFO_THRES - int "UART8 Rx FIFO Threshold" - default 3 - range 0 5 - ---help--- - Select the Rx FIFO threshold: - - 0 -> 1/8 full - 1 -> 1/4 full - 2 -> 1/2 full - 3 -> 3/4 full - 4 -> 7/8 full - 5 -> Full - - Higher values mean lower interrupt rates and better CPU performance. - Lower values may be needed at high BAUD rates to prevent Rx data - overrun errors. - -endif # STM32H7_UART8 - -config STM32H7_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA || USART6_RXDMA || UART7_RXDMA || UART8_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32H7_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32H7_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on SERIAL_IFLOWCONTROL_WATERMARKS - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32H7_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32H7_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32H7_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32H7 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32H7_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32H7_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32H7 serial driver. - -config STM32H7_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32H7_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32H7 serial driver. - -config STM32H7_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32H7_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32H7 serial driver. - -if PM - -config STM32H7_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # PM -endmenu # U[S]ART Configuration - -menu "ADC Configuration" - depends on STM32H7_ADC - -config STM32H7_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32H7_ADC1_DMA - bool "ADC1 DMA (not supported yet)" - depends on STM32H7_ADC1 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32H7_ADC1 && STM32H7_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC2_DMA - bool "ADC2 DMA (not supported yet)" - depends on STM32H7_ADC2 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32H7_ADC2 && STM32H7_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32H7_ADC3_DMA - bool "ADC3 DMA (not supported yet)" - depends on STM32H7_ADC3 && EXPERIMENTAL - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32H7_ADC3_DMA_BATCH - int "ADC3 DMA number of conversions" - depends on STM32H7_ADC3 && STM32H7_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -endmenu # ADC Configuration - -menu "SD/MMC Configuration" - depends on STM32H7_SDMMC - -config STM32H7_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32H7_SDMMC_IDMA - bool "Support IDMA data transfers" - default y - select SDIO_DMA - ---help--- - Support IDMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32H7_SDMMC1 - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC1_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC1_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC1 Configuration" - -menu "SDMMC2 Configuration" - depends on STM32H7_SDMMC2 - -config SDMMC2_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC2" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -config SDMMC2_SDIO_MODE - bool "SDIO Card Support" - default n - ---help--- - Build in additional support needed only for SDIO cards (vs. SD - memory cards) - -config SDMMC2_SDIO_PULLUP - bool "Enable internal Pull-Ups" - default n - ---help--- - If you are using an external SDCard module that does not have the - pull-up resistors for the SDIO interface (like the Gadgeteer SD Card - Module) then enable this option to activate the internal pull-up - resistors. - -endmenu # "SDMMC2 Configuration" -endmenu # "SD/MMC Configuration" - -if STM32H7_BKPSRAM - -config STM32H7_BBSRAM - bool "BBSRAM File Support" - default n - select ARM_MPU - -config STM32H7_BBSRAM_FILES - int "Max Files to support in BBSRAM" - default 4 - depends on STM32H7_BBSRAM - -config STM32H7_SAVE_CRASHDUMP - bool "Enable Saving Panic to BBSRAM" - default n - depends on STM32H7_BBSRAM - -endif # STM32H7_BKPSRAM - -config STM32H7_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32H7_RTC - -config STM32H7_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32H7_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32H7_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -config STM32H7_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32H7_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -endchoice #"RTC clock source" - -if STM32H7_RTC_LSECLOCK - -config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the correct* values from low to high. To - avoid damaging the crystal, we want to use the lowest setting that - gets the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - *It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - -config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - depends on !STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - - It will take into account the revision of the silicon and use - the correct code points to achieve the drive strength. - See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability - selection bits are swapped. - - WARNING this RUN setting does not appear to work! It appears - that the LSEDRV bits cannot be changed once the OSC is running. - -endif # STM32H7_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "QuadSPI Configuration" - depends on STM32H7_QSPI - -config STM32H7_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483648 - ---help--- - The STM32H7 QSPI peripheral requires the size of the Flash be specified - -config STM32H7_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32H7 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32H7_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32H7 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32H7_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32H7_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32H7_QSPI_DMA - bool "DMA" - depends on STM32H7_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice # Transfer technique - -choice - prompt "Bank selection" - default STM32H7_QSPI_MODE_BANK1 - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32H7_QSPI_MODE_BANK1 - bool "Bank 1" - -config STM32H7_QSPI_MODE_BANK2 - bool "Bank 2" - -config STM32H7_QSPI_MODE_DUAL - bool "Dual Bank" - -endchoice # Bank selection - -choice - prompt "DMA Priority" - default STM32H7_QSPI_DMAPRIORITY_MEDIUM - depends on STM32H7_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32H7_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32H7_DMA - ---help--- - 'Highest' priority. - -config STM32H7_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32H7_DMA - ---help--- - 'High' priority. - -config STM32H7_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32H7_DMA - ---help--- - 'Medium' priority. - -config STM32H7_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32H7_DMA - ---help--- - 'Low' priority. - -endchoice # DMA Priority - -config STM32H7_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32H7_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32H7_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32H7_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32H7_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endmenu # QuadSPI Configuration - -config STM32H7_BYPASS_CLOCKCONFIG +config STM32_BYPASS_CLOCKCONFIG bool "Bypass clock configuration" depends on ARCH_STM32H7_DUALCORE default n if ARCH_CHIP_STM32H7_CORTEXM7 @@ -2363,13 +790,7 @@ config STM32H7_BYPASS_CLOCKCONFIG Bypass clock configuration. For dual core chips only one core should configure clocks -config STM32H7_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32H7_SRAM4EXCLUDE +config STM32_SRAM4EXCLUDE bool "Exclude SRAM4 from the heap" default y if RPTUN default n @@ -2377,4280 +798,6 @@ config STM32H7_SRAM4EXCLUDE Exclude SRAM4 from the HEAP in order to use this 64 KB region for other uses, such as DMA buffers, etc. -config STM32H7_DTCMEXCLUDE - bool "Exclude DTCM SRAM from the heap" - default LIBC_ARCH_ELF - depends on ARMV7M_HAVE_DTCM - ---help--- - Exclude DTCM SRAM from the HEAP because it appears to be impossible - to execute ELF modules from DTCM RAM (REVISIT!). - -config STM32H7_DTCM_PROCFS - bool "DTCM SRAM PROCFS support" - default n - depends on ARMV7M_DTCM && FS_PROCFS - ---help--- - Select to build in support for /proc/dtcm. Reading from /proc/dtcm - will provide statistics about DTCM memory use similar to what you - would get from mallinfo() for the user heap. - -config STM32H7_DMACAPABLE - bool "Workaround non-DMA capable memory" - depends on ARCH_DMA - default n - ---help--- - This option enables the DMA interface stm32_dmacapable that can be - used to check if it is possible to do DMA from the selected address. - Drivers then may use this information to determine if they should - attempt the DMA or fall back to a different transfer method. - -config STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED - bool "Do not disqualify DMA capability based on cache alignment" - depends on STM32H7_DMACAPABLE && ARMV7M_DCACHE && !ARMV7M_DCACHE_WRITETHROUGH - default n - ---help--- - This option configures the stm32_dmacapable to not disqualify - DMA operations on memory that is not dcache aligned based solely - on the starting address and byte count. - - Use this when ALL buffer extents are known to be aligned, but the - the count does not use the complete buffer. - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32H7_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32H7_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32H7_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32H7_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32H7_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32H7_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32H7_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32H7_TIM1 - select STM32H7_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM1_PWM - -config STM32H7_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32H7_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL1 - -config STM32H7_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL2 - -config STM32H7_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL3 - -config STM32H7_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL4 - -config STM32H7_TIM1_CHANNEL5 - bool "TIM1 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CH5MODE - int "TIM1 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH5OUT - bool "TIM1 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM1_CHANNEL5 - -config STM32H7_TIM1_CHANNEL6 - bool "TIM1 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM1_CHANNEL6 - -config STM32H7_TIM1_CH6MODE - int "TIM1 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM1_CH6OUT - bool "TIM1 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM1_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM1_CHANNEL = 1 - -config STM32H7_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 1 - -if STM32H7_TIM1_CHANNEL = 2 - -config STM32H7_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 2 - -if STM32H7_TIM1_CHANNEL = 3 - -config STM32H7_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM1_CHANNEL = 3 - -if STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM1_CHANNEL = 4 - -config STM32H7_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM1_PWM - -config STM32H7_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32H7_TIM2 - select STM32H7_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM2_PWM - -config STM32H7_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL1 - -config STM32H7_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL2 - -config STM32H7_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL3 - -config STM32H7_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM2_CHANNEL4 - -config STM32H7_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM2_CHANNEL = 1 - -config STM32H7_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM2_CHANNEL = 1 - -if STM32H7_TIM2_CHANNEL = 2 - -config STM32H7_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM2_CHANNEL = 2 - -if STM32H7_TIM2_CHANNEL = 3 - -config STM32H7_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM2_CHANNEL = 3 - -if STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM2_CHANNEL = 4 - -config STM32H7_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM2_PWM - -config STM32H7_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32H7_TIM3 - select STM32H7_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM3_PWM - -config STM32H7_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL1 - -config STM32H7_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL2 - -config STM32H7_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL3 - -config STM32H7_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM3_CHANNEL4 - -config STM32H7_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM3_CHANNEL = 1 - -config STM32H7_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM3_CHANNEL = 1 - -if STM32H7_TIM3_CHANNEL = 2 - -config STM32H7_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM3_CHANNEL = 2 - -if STM32H7_TIM3_CHANNEL = 3 - -config STM32H7_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM3_CHANNEL = 3 - -if STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM3_CHANNEL = 4 - -config STM32H7_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM3_PWM - -config STM32H7_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32H7_TIM4 - select STM32H7_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM4_PWM - -config STM32H7_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL1 - -config STM32H7_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL2 - -config STM32H7_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL3 - -config STM32H7_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM4_CHANNEL4 - -config STM32H7_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM4_CHANNEL = 1 - -config STM32H7_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM4_CHANNEL = 1 - -if STM32H7_TIM4_CHANNEL = 2 - -config STM32H7_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM4_CHANNEL = 2 - -if STM32H7_TIM4_CHANNEL = 3 - -config STM32H7_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM4_CHANNEL = 3 - -if STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM4_CHANNEL = 4 - -config STM32H7_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM4_PWM - -config STM32H7_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32H7_TIM5 - select STM32H7_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM5_PWM - -config STM32H7_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL1 - -config STM32H7_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL2 - -config STM32H7_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL3 - -config STM32H7_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM5_CHANNEL4 - -config STM32H7_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL4 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM5_CHANNEL = 1 - -config STM32H7_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM5_CHANNEL = 1 - -if STM32H7_TIM5_CHANNEL = 2 - -config STM32H7_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM5_CHANNEL = 2 - -if STM32H7_TIM5_CHANNEL = 3 - -config STM32H7_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32H7_TIM5_CHANNEL = 3 - -if STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM5_CHANNEL = 4 - -config STM32H7_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM5_PWM - -config STM32H7_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32H7_TIM8 - select STM32H7_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM8_PWM - -config STM32H7_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32H7_TIM8_LOCK - int "TIM8 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32H7_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -config STM32H7_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL1 - -config STM32H7_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL2 - -config STM32H7_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL3 - -config STM32H7_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL4 - -config STM32H7_TIM8_CHANNEL5 - bool "TIM8 Channel 5 (internal)" - default n - ---help--- - Enables channel 5 (not available externally) - -if STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CH5MODE - int "TIM8 Channel 5 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH5OUT - bool "TIM8 Channel 5 Output" - default n - ---help--- - Enables channel 5 output. - -endif # STM32H7_TIM8_CHANNEL5 - -config STM32H7_TIM8_CHANNEL6 - bool "TIM8 Channel 6 (internal)" - default n - ---help--- - Enables channel 6 (not available externally) - -if STM32H7_TIM8_CHANNEL6 - -config STM32H7_TIM8_CH6MODE - int "TIM8 Channel 6 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM8_CH6OUT - bool "TIM8 Channel 6 Output" - default n - ---help--- - Enables channel 6 output. - -endif # STM32H7_TIM8_CHANNEL6 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32H7_TIM8_CHANNEL = 1 - -config STM32H7_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 1 - -if STM32H7_TIM8_CHANNEL = 2 - -config STM32H7_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 2 - -if STM32H7_TIM8_CHANNEL = 3 - -config STM32H7_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32H7_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32H7_TIM8_CHANNEL = 3 - -if STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32H7_TIM8_CHANNEL = 4 - -config STM32H7_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM8_PWM - -config STM32H7_TIM12_PWM - bool "TIM12 PWM" - default n - depends on STM32H7_TIM12 - select STM32H7_PWM - ---help--- - Reserve timer 12 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM12 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM12_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL1 - bool "TIM12 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CH1MODE - int "TIM12 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL1 - -config STM32H7_TIM12_CHANNEL2 - bool "TIM12 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM12_CHANNEL2 - -config STM32H7_TIM12_CH2MODE - int "TIM12 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM12_CHANNEL - int "TIM12 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM12 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM12_CHANNEL = 1 - -config STM32H7_TIM12_CH1OUT - bool "TIM12 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM12_CHANNEL = 1 - -if STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CH2OUT - bool "TIM12 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM12_CHANNEL = 2 - -config STM32H7_TIM12_CHMODE - int "TIM12 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM12_PWM - -config STM32H7_TIM13_PWM - bool "TIM13 PWM" - default n - depends on STM32H7_TIM13 - select STM32H7_PWM - ---help--- - Reserve timer 13 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM13 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM13_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL1 - bool "TIM13 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM13_CHANNEL1 - -config STM32H7_TIM13_CH1MODE - int "TIM13 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM13_CHANNEL - int "TIM13 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM13 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CH1OUT - bool "TIM13 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM13_CHANNEL = 1 - -config STM32H7_TIM13_CHMODE - int "TIM13 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM13_PWM - -config STM32H7_TIM14_PWM - bool "TIM14 PWM" - default n - depends on STM32H7_TIM14 - select STM32H7_PWM - ---help--- - Reserve timer 14 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM14 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM14_PWM - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL1 - bool "TIM14 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM14_CHANNEL1 - -config STM32H7_TIM14_CH1MODE - int "TIM14 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM14_CHANNEL - int "TIM14 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM14 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CH1OUT - bool "TIM14 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM14_CHANNEL = 1 - -config STM32H7_TIM14_CHMODE - int "TIM14 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM14_PWM - -config STM32H7_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32H7_TIM15 - select STM32H7_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM15_PWM - -config STM32H7_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32H7_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL1 - -config STM32H7_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32H7_TIM15_CHANNEL2 - -config STM32H7_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32H7_TIM15_CHANNEL2 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32H7_TIM15_CHANNEL = 1 - -config STM32H7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32H7_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 1 - -if STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32H7_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32H7_TIM15_CHANNEL = 2 - -config STM32H7_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM15_PWM - -config STM32H7_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32H7_TIM16 - select STM32H7_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM16_PWM - -config STM32H7_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32H7_TIM16_TDTS - int "TIM16 t_DTS division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM16_CHANNEL1 - -config STM32H7_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM16_CHANNEL = 1 - -config STM32H7_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM16_PWM - -config STM32H7_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32H7_TIM17 - select STM32H7_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32H7_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32H7_TIM17_PWM - -config STM32H7_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32H7_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32H7_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32H7_TIM17_CHANNEL1 - -config STM32H7_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL1 - -endif # STM32H7_PWM_MULTICHAN - -if !STM32H7_PWM_MULTICHAN - -config STM32H7_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32H7_TIM17_CHANNEL = 1 - -config STM32H7_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32_pwm_chanmode_e in stm32_pwm.h. - -endif # !STM32H7_PWM_MULTICHAN - -endif # STM32H7_TIM17_PWM - -config STM32H7_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32H7_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32H7_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32H7_TIM1 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM1_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32H7_TIM8 - select STM32H7_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32H7_TIM8_PULSECOUNT - -config STM32H7_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32H7_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32H7_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32H7_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32H7_TIM8_PULSECOUNT -config STM32H7_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32H7_TIM1 && STM32H7_ADC - ---help--- - Reserve timer 1 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM1" - default STM32H7_TIM1_ADC1 - depends on STM32H7_TIM1_ADC - -config STM32H7_TIM1_ADC1 - bool "Use TIM1 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32H7_TIM1_ADC2 - bool "Use TIM1 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32H7_TIM1_ADC3 - bool "Use TIM1 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice # Select ADC for use with TIM1 - -config STM32H7_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32H7_TIM2 && STM32H7_ADC - ---help--- - Reserve timer 2 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM2" - default STM32H7_TIM2_ADC1 - depends on STM32H7_TIM2_ADC - -config STM32H7_TIM2_ADC1 - bool "Use TIM2 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32H7_TIM2_ADC2 - bool "Use TIM2 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32H7_TIM2_ADC3 - bool "Use TIM2 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice # Select ADC for use with TIM2 - -config STM32H7_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32H7_TIM3 && STM32H7_ADC - ---help--- - Reserve timer 3 for use by an ADC - - Timer devices may be used for different purposes. If STM32H7_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM3" - default STM32H7_TIM3_ADC1 - depends on STM32H7_TIM3_ADC - -config STM32H7_TIM3_ADC1 - bool "Use TIM3 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32H7_TIM3_ADC2 - bool "Use TIM3 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32H7_TIM3_ADC3 - bool "Use TIM3 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice # Select ADC for use with TIM3 - -config STM32H7_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32H7_TIM4 && STM32H7_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM4" - default STM32H7_TIM4_ADC1 - depends on STM32H7_TIM4_ADC - -config STM32H7_TIM4_ADC1 - bool "Use TIM4 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32H7_TIM4_ADC2 - bool "Use TIM4 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32H7_TIM4_ADC3 - bool "Use TIM4 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice # Select ADC for use with TIM4 - -config STM32H7_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32H7_TIM6 && STM32H7_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM6" - default STM32H7_TIM6_ADC1 - depends on STM32H7_TIM6_ADC - -config STM32H7_TIM6_ADC1 - bool "Use TIM6 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32H7_TIM6_ADC2 - bool "Use TIM6 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32H7_TIM6_ADC3 - bool "Use TIM6 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice # Select ADC for use with TIM6 - -config STM32H7_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32H7_TIM8 && STM32H7_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM8" - default STM32H7_TIM8_ADC1 - depends on STM32H7_TIM8_ADC - -config STM32H7_TIM8_ADC1 - bool "Use TIM8 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32H7_TIM8_ADC2 - bool "Use TIM8 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32H7_TIM8_ADC3 - bool "Use TIM8 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice # Select ADC for use with TIM8 - -config STM32H7_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32H7_TIM15 && STM32H7_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32H7_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC for use with TIM15" - default STM32H7_TIM15_ADC1 - depends on STM32H7_TIM15_ADC - -config STM32H7_TIM15_ADC1 - bool "Use TIM15 for ADC1" - depends on STM32H7_ADC1 - select STM32H7_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32H7_TIM15_ADC2 - bool "Use TIM15 for ADC2" - depends on STM32H7_ADC2 - select STM32H7_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32H7_TIM15_ADC3 - bool "Use TIM15 for ADC3" - depends on STM32H7_ADC3 - select STM32H7_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice # Select ADC for use with TIM15 - -config STM32H7_HAVE_ADC1_TIMER - bool - -config STM32H7_HAVE_ADC2_TIMER - bool - -config STM32H7_HAVE_ADC3_TIMER - bool - -config STM32H7_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32H7_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32H7_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32H7_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32H7_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32H7_TIMX_CAP - default n - bool "Helpers for Capture Drivers" - -config STM32H7_TIM1_CAP - bool "TIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM1 - ---help--- - Reserve timer 1 for use by the capture driver. - -if STM32H7_TIM1_CAP - -config STM32H7_TIM1_CHANNEL - int "TIM1 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM1. - -config STM32H7_TIM1_CLOCK - int "TIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM1_CAP - -config STM32H7_TIM8_CAP - bool "TIM8 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM8 - ---help--- - Reserve timer 8 for use by the capture driver. - -if STM32H7_TIM8_CAP - -config STM32H7_TIM8_CHANNEL - int "TIM8 Capture Input Channel" - default 1 - range 1 6 - ---help--- - Specifies the timer input channel {1..6} for TIM8. - -config STM32H7_TIM8_CLOCK - int "TIM8 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM8_CAP - -# -# General-Purpose Timers (4 Channels) -# - -config STM32H7_TIM2_CAP - bool "TIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM2 - ---help--- - Reserve timer 2 for use by the capture driver. - -if STM32H7_TIM2_CAP - -config STM32H7_TIM2_CHANNEL - int "TIM2 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM2. - -config STM32H7_TIM2_CLOCK - int "TIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM2_CAP - -config STM32H7_TIM3_CAP - bool "TIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM3 - ---help--- - Reserve timer 3 for use by the capture driver. - -if STM32H7_TIM3_CAP - -config STM32H7_TIM3_CHANNEL - int "TIM3 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM3. - -config STM32H7_TIM3_CLOCK - int "TIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM3_CAP - -config STM32H7_TIM4_CAP - bool "TIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM4 - ---help--- - Reserve timer 4 for use by the capture driver. - -if STM32H7_TIM4_CAP - -config STM32H7_TIM4_CHANNEL - int "TIM4 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM4. - -config STM32H7_TIM4_CLOCK - int "TIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM4_CAP - -config STM32H7_TIM5_CAP - bool "TIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM5 - ---help--- - Reserve timer 5 for use by the capture driver. - -if STM32H7_TIM5_CAP - -config STM32H7_TIM5_CHANNEL - int "TIM5 Capture Input Channel" - default 1 - range 1 4 - ---help--- - Specifies the timer input channel {1..4} for TIM5. - -config STM32H7_TIM5_CLOCK - int "TIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM5_CAP - -# -# General-Purpose Timers (2 Channels) -# - -config STM32H7_TIM12_CAP - bool "TIM12 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM12 - ---help--- - Reserve timer 12 for use by the capture driver. - -if STM32H7_TIM12_CAP - -config STM32H7_TIM12_CHANNEL - int "TIM12 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM12. - -config STM32H7_TIM12_CLOCK - int "TIM12 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM12_CAP - -config STM32H7_TIM15_CAP - bool "TIM15 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM15 - ---help--- - Reserve timer 15 for use by the capture driver. - -if STM32H7_TIM15_CAP - -config STM32H7_TIM15_CHANNEL - int "TIM15 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1..2} for TIM15. - -config STM32H7_TIM15_CLOCK - int "TIM15 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM15_CAP - -# -# General-Purpose Timers (1 Channel) -# - -config STM32H7_TIM13_CAP - bool "TIM13 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM13 - ---help--- - Reserve timer 13 for use by the capture driver. - -if STM32H7_TIM13_CAP - -config STM32H7_TIM13_CHANNEL - int "TIM13 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM13. - -config STM32H7_TIM13_CLOCK - int "TIM13 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM13_CAP - -config STM32H7_TIM14_CAP - bool "TIM14 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM14 - ---help--- - Reserve timer 14 for use by the capture driver. - -if STM32H7_TIM14_CAP - -config STM32H7_TIM14_CHANNEL - int "TIM14 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM14. - -config STM32H7_TIM14_CLOCK - int "TIM14 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM14_CAP - -config STM32H7_TIM16_CAP - bool "TIM16 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM16 - ---help--- - Reserve timer 16 for use by the capture driver. - -if STM32H7_TIM16_CAP - -config STM32H7_TIM16_CHANNEL - int "TIM16 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM16. - -config STM32H7_TIM16_CLOCK - int "TIM16 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM16_CAP - -config STM32H7_TIM17_CAP - bool "TIM17 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_TIM17 - ---help--- - Reserve timer 17 for use by the capture driver. - -if STM32H7_TIM17_CAP - -config STM32H7_TIM17_CHANNEL - int "TIM17 Capture Input Channel" - default 1 - range 1 1 - ---help--- - Specifies the timer input channel {1} for TIM17. - -config STM32H7_TIM17_CLOCK - int "TIM17 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_TIM17_CAP - -# -# Low-Power Timers -# - -config STM32H7_LPTIM1_CAP - bool "LPTIM1 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM1 - ---help--- - Reserve low-power timer 1 for use by the capture driver. - -if STM32H7_LPTIM1_CAP - -config STM32H7LPTIM1_CHANNEL - int "LPTIM1 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM1. - -config STM32H7LPTIM1_CLOCK - int "LPTIM1 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM1_CAP - -config STM32H7_LPTIM2_CAP - bool "LPTIM2 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM2 - ---help--- - Reserve low-power timer 2 for use by the capture driver. - -if STM32H7_LPTIM2_CAP - -config STM32H7LPTIM2_CHANNEL - int "LPTIM2 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM2. - -config STM32H7LPTIM2_CLOCK - int "LPTIM2 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM2_CAP - -config STM32H7_LPTIM3_CAP - bool "LPTIM3 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM3 - ---help--- - Reserve low-power timer 3 for use by the capture driver. - -if STM32H7_LPTIM3_CAP - -config STM32H7LPTIM3_CHANNEL - int "LPTIM3 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM3. - -config STM32H7LPTIM3_CLOCK - int "LPTIM3 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM3_CAP - -config STM32H7_LPTIM4_CAP - bool "LPTIM4 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM4 - ---help--- - Reserve low-power timer 4 for use by the capture driver. - -if STM32H7_LPTIM4_CAP - -config STM32H7LPTIM4_CHANNEL - int "LPTIM4 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM4. - -config STM32H7LPTIM4_CLOCK - int "LPTIM4 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM4_CAP - -config STM32H7_LPTIM5_CAP - bool "LPTIM5 Capture" - default n - select STM32H7_TIMX_CAP - depends on STM32H7_LPTIM5 - ---help--- - Reserve low-power timer 5 for use by the capture driver. - -if STM32H7_LPTIM5_CAP - -config STM32H7LPTIM5_CHANNEL - int "LPTIM5 Capture Input Channel" - default 1 - range 1 2 - ---help--- - Specifies the timer input channel {1,2} for LPTIM5. - -config STM32H7LPTIM5_CLOCK - int "LPTIM5 capture frequency (Hz)" - default 100000 - ---help--- - This clock frequency determines the timer's counting rate. - -endif # STM32H7_LPTIM5_CAP - -menu "STM32 TIMx Outputs Configuration" - -config STM32H7_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32H7_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32H7_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32H7_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32H7_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32H7_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32H7_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32H7_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32H7_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32H7_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32H7_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32H7_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32H7_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32H7_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32H7_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32H7_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32H7_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32H7_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32H7_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32H7_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32H7_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32H7_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32H7_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32H7_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32H7_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32H7_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32H7_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32H7_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32H7_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32H7_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32H7_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32H7_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32H7_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32H7_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32H7_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32H7_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32H7_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32H7_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32H7_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32H7_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32H7_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32H7_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32H7_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32H7_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32H7_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32H7_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32H7_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32H7_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32H7_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32H7_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32H7_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32H7_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32H7_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32H7_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32H7_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32H7_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32H7_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32H7_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32H7_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32H7_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32H7_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32H7_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32H7_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32H7_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32H7_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32H7_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32H7_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32H7_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32H7_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32H7_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32H7_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32H7_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32H7_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32H7_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32H7_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32H7_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32H7_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32H7_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32H7_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32H7_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32H7_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32H7_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32H7_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32H7_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32H7_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32H7_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32H7_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32H7_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32H7_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "Ethernet MAC configuration" - depends on STM32H7_ETHMAC - -config STM32H7_PHYADDR - int "PHY address" - default 0 - ---help--- - The 5-bit address of the PHY on the board. Default: 1 - -config STM32H7_PHYINIT - bool "Board-specific PHY Initialization" - default n - ---help--- - Some boards require specialized initialization of the PHY before it can be used. - This may include such things as configuring GPIOs, resetting the PHY, etc. If - STM32H7_PHYINIT is defined in the configuration then the board specific logic must - provide stm32_phyinitialize(); The STM32 Ethernet driver will call this function - one time before it first uses the PHY. - -config STM32H7_PHY_POLLING - bool "Support network monitoring by polling the PHY" - default n - depends on STM32H7_HAVE_PHY_POLLED - select ARCH_PHY_POLLED - ---help--- - Some boards may not have an interrupt connected to the PHY. - This option allows the network monitor to be used by polling the - the PHY for status. - -config STM32H7_MII - bool "Use MII interface" - default n - ---help--- - Support Ethernet MII interface. - -choice - prompt "MII clock configuration" - default STM32H7_MII_EXTCLK - depends on STM32H7_MII - -config STM32H7_MII_MCO1 - bool "Use MC01 as MII clock" - ---help--- - Use MCO1 to clock the MII interface. - -config STM32H7_MII_MCO2 - bool "Use MC02 as MII clock" - ---help--- - Use MCO2 to clock the MII interface. - -config STM32H7_MII_EXTCLK - bool "External MII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # MII clock configuration - -config STM32H7_AUTONEG - bool "Use autonegotiation" - default y - ---help--- - Use PHY autonegotiation to determine speed and mode - -config STM32H7_ETH_NRXDESC - int "Number of RX descriptors" - default 8 - ---help--- - Number of RX DMA descriptors to use. - -config STM32H7_ETH_NTXDESC - int "Number of TX descriptors" - default 4 - ---help--- - Number of TX DMA descriptors to use. - -config STM32H7_ETHFD - bool "Full duplex" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select full duplex - mode. Default: half-duplex - -config STM32H7_ETH100MBPS - bool "100 Mbps" - default n - depends on !STM32H7_AUTONEG - ---help--- - If STM32H7_AUTONEG is not defined, then this may be defined to select 100 MBps - speed. Default: 10 Mbps - -config STM32H7_PHYSR - int "PHY Status Register Address (decimal)" - depends on STM32H7_AUTONEG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. The PHY status register - address may diff from PHY to PHY. This configuration sets the address of - the PHY status register. - -config STM32H7_PHYSR_ALTCONFIG - bool "PHY Status Alternate Bit Layout" - default n - depends on STM32H7_AUTONEG - ---help--- - Different PHYs present speed and mode information in different ways. Some - will present separate information for speed and mode (this is the default). - Those PHYs, for example, may provide a 10/100 Mbps indication and a separate - full/half duplex indication. This options selects an alternative representation - where speed and mode information are combined. This might mean, for example, - separate bits for 10HD, 100HD, 10FD and 100FD. - -config STM32H7_PHYSR_SPEED - hex "PHY Speed Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides bit mask - for isolating the 10 or 100MBps speed indication. - -config STM32H7_PHYSR_100MBPS - hex "PHY 100Mbps Speed Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the value - of the speed bit(s) indicating 100MBps speed. - -config STM32H7_PHYSR_MODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the full or half duplex mode bits. - -config STM32H7_PHYSR_FULLDUPLEX - hex "PHY Full Duplex Mode Value" - depends on STM32H7_AUTONEG && !STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provides the - value of the mode bits indicating full duplex mode. - -config STM32H7_PHYSR_ALTMODE - hex "PHY Mode Mask" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This provide bit mask - for isolating the speed and full/half duplex mode bits. - -config STM32H7_PHYSR_10HD - hex "10MBase-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, half duplex setting. - -config STM32H7_PHYSR_100HD - hex "100Base-T Half Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, half duplex setting. - -config STM32H7_PHYSR_10FD - hex "10Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 10Mbps, full duplex setting. - -config STM32H7_PHYSR_100FD - hex "100Base-T Full Duplex Value" - depends on STM32H7_AUTONEG && STM32H7_PHYSR_ALTCONFIG - ---help--- - This must be provided if STM32H7_AUTONEG is defined. This is the value - under the bit mask that represents the 100Mbps, full duplex setting. - -config STM32H7_ETH_PTP - bool "Precision Time Protocol (PTP)" - default n - ---help--- - Precision Time Protocol (PTP). Not supported but some hooks are indicated - with this condition. - -config STM32H7_RMII - bool - default !STM32H7_MII - -choice - prompt "RMII clock configuration" - default STM32H7_RMII_EXTCLK - depends on STM32H7_RMII - -config STM32H7_RMII_MCO1 - bool "Use MC01 as RMII clock" - ---help--- - Use MCO1 to clock the RMII interface. - -config STM32H7_RMII_MCO2 - bool "Use MC02 as RMII clock" - ---help--- - Use MCO2 to clock the RMII interface. - -config STM32H7_RMII_EXTCLK - bool "External RMII clock" - ---help--- - Clocking is provided by external logic. - -endchoice # RMII clock configuration - -config STM32H7_ETHMAC_REGDEBUG - bool "Register-Level Debug" - default n - depends on DEBUG_NET_INFO - ---help--- - Enable very low-level register access debug. Depends on - CONFIG_DEBUG_FEATURES. - -config STM32H7_NO_PHY - bool "MAC has no PHY" - default n - -endmenu # Ethernet MAC configuration - -if STM32H7_LTDC - -menu "LTDC Configuration" - -config STM32H7_LTDC_USE_DSI - bool "Use DSI as display connection" - default n - depends on STM32H7_DSIHOST - ---help--- - Select this if your display is connected via DSI. - Deselect option if your display is connected via digital - RGB+HSYNC+VSYNC - -config STM32H7_LTDC_BACKLIGHT - bool "Backlight support" - default y - -config STM32H7_LTDC_DEFBACKLIGHT - hex "Default backlight level" - default 0xf0 - -config STM32H7_LTDC_BACKCOLOR - hex "Background color" - default 0x0 - ---help--- - This is the background color that will be used as the LTDC - background layer color. It is an RGB888 format value, - which gets written unmodified to register LTDC_BCCR. - -config STM32H7_LTDC_DITHER - bool "Dither support" - default n - -config STM32H7_LTDC_DITHER_RED - depends on STM32H7_LTDC_DITHER - int "Dither red width" - range 0 7 - default 2 - ---help--- - This is the dither red width. - -config STM32H7_LTDC_DITHER_GREEN - depends on STM32H7_LTDC_DITHER - int "Dither green width" - range 0 7 - default 2 - ---help--- - This is the dither green width. - -config STM32H7_LTDC_DITHER_BLUE - depends on STM32H7_LTDC_DITHER - int "Dither blue width" - range 0 7 - default 2 - ---help--- - This is the dither blue width. - -config STM32H7_LTDC_FB_BASE - hex "Framebuffer memory start address" - default 0 - ---help--- - If you are using the LTDC, then you must provide the address - of the start of the framebuffer. This address will typically - be in the SRAM or SDRAM memory region of the FMC. - -config STM32H7_LTDC_FB_SIZE - int "Framebuffer memory size (bytes)" - default 0 - ---help--- - Must be the whole size of the active LTDC layer. - -config STM32H7_LTDC_FB_DOUBLE_BUFFER - bool "Enable double buffering" - default n - ---help--- - Enable double buffering to allow updates to the framebuffer while the display is being refreshed. - This configuration requires two framebuffers: one active and one inactive. - When the display refreshes, the active and inactive framebuffers are swapped, - enabling smooth and flicker-free updates. - -config STM32H7_LTDC_L1_CHROMAKEYEN - bool "Enable chromakey support for layer 1" - default y - -config STM32H7_LTDC_L1_CHROMAKEY - hex "Layer L1 initial chroma key" - default 0x00000000 - -config STM32H7_LTDC_L1_COLOR - hex "Layer L1 default color" - default 0x00000000 - -choice - prompt "Layer 1 color format" - default STM32H7_LTDC_L1_RGB565 - -config STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - depends on STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - depends on !STM32H7_FB_CMAP - -config STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - depends on !STM32H7_FB_CMAP - -endchoice # Layer 1 color format - -config STM32H7_LTDC_L2 - bool "Enable Layer 2 support" - default y - -if STM32H7_LTDC_L2 - -config STM32H7_LTDC_L2_COLOR - hex "Layer L2 default color" - default 0x00000000 - -config STM32H7_LTDC_L2_CHROMAKEYEN - bool "Enable chromakey support for layer 2" - default y - -config STM32H7_LTDC_L2_CHROMAKEY - hex "Layer L2 initial chroma key" - default 0x00000000 - -choice - prompt "Layer 2 (top layer) color format" - default STM32H7_LTDC_L2_RGB565 - -config STM32H7_LTDC_L2_L8 - depends on STM32H7_LTDC_L1_L8 - bool "8 bpp L8 (8-bit CLUT)" - -config STM32H7_LTDC_L2_AL44 - depends on STM32H7_LTDC_L1_AL44 - bool "8 bpp AL44 (4-bit alpha + 4-bit CLUT)" - -config STM32H7_LTDC_L2_AL88 - depends on STM32H7_LTDC_L1_AL88 - bool "16 bpp AL88 (8-bit alpha + 8-bit CLUT)" - -config STM32H7_LTDC_L2_RGB565 - depends on STM32H7_LTDC_L1_RGB565 - bool "16 bpp RGB 565" - -config STM32H7_LTDC_L2_ARGB4444 - depends on STM32H7_LTDC_L1_ARGB4444 - bool "16 bpp ARGB 4444" - -config STM32H7_LTDC_L2_ARGB1555 - depends on STM32H7_LTDC_L1_ARGB1555 - bool "16 bpp ARGB 1555" - -config STM32H7_LTDC_L2_RGB888 - depends on STM32H7_LTDC_L1_RGB888 - bool "24 bpp RGB 888" - -config STM32H7_LTDC_L2_ARGB8888 - depends on STM32H7_LTDC_L1_ARGB8888 - bool "32 bpp ARGB 8888" - -endchoice # Layer 2 color format - -endif # STM32H7_LTDC_L2 - -config STM32H7_FB_CMAP - bool "Color map support" - default y - select FB_CMAP - ---help--- - EnablingEnablescolor map support is necessary for ltdc L8 format. - -config STM32H7_FB_TRANSPARENCY - bool "Transparency color map support" - default y - depends on STM32H7_FB_CMAP - select FB_TRANSPARENCY - ---help--- - Enables transparency color map support is necessary for ltdc L8 format. - -config STM32H7_LTDC_REGDEBUG - bool "Enable LTDC register value debug messages" - default n - ---help--- - This gives additional messages for LTDC related register values. - Additionally, you have to select "Low-level LCD Debug Features" - to enable the debug messages. - -endmenu # LTDC Configuration - -endif # STM32H7_LTDC - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32H7_TIM1 || STM32H7_TIM2 || STM32H7_TIM3 || STM32H7_TIM4 || STM32H7_TIM5 || STM32H7_TIM8 - -config STM32H7_TIM1_QE - bool "TIM1" - default n - depends on STM32H7_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32H7_TIM1_QE - -config STM32H7_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM1_QE - -config STM32H7_TIM2_QE - bool "TIM2" - default n - depends on STM32H7_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32H7_TIM2_QE - -config STM32H7_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM2_QE - -config STM32H7_TIM3_QE - bool "TIM3" - default n - depends on STM32H7_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32H7_TIM3_QE - -config STM32H7_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM3_QE - -config STM32H7_TIM4_QE - bool "TIM4" - default n - depends on STM32H7_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32H7_TIM4_QE - -config STM32H7_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM4_QE - -config STM32H7_TIM5_QE - bool "TIM5" - default n - depends on STM32H7_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32H7_TIM5_QE - -config STM32H7_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM5_QE - -config STM32H7_TIM8_QE - bool "TIM8" - default n - depends on STM32H7_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32H7_TIM8_QE - -config STM32H7_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, - limiting the count rate at the expense of resolution. - -endif # STM32H7_TIM8_QE - -config STM32H7_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32H7_QENCODER_SAMPLE_FDTS_4 - -config STM32H7_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32H7_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32H7_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32H7_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32H7_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32H7_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice # Input channel sampling frequency - -choice - depends on STM32H7_QENCODER_FILTER - prompt "Input channel event count" - default STM32H7_QENCODER_SAMPLE_EVENT_6 - -config STM32H7_QENCODER_SAMPLE_EVENT_1 - depends on STM32H7_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32H7_QENCODER_SAMPLE_EVENT_2 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32H7_QENCODER_SAMPLE_EVENT_4 - depends on STM32H7_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32H7_QENCODER_SAMPLE_EVENT_5 - depends on STM32H7_QENCODER_SAMPLE_FDTS_16 || STM32H7_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32H7_QENCODER_SAMPLE_EVENT_6 - depends on !STM32H7_QENCODER_SAMPLE_FDTS && !STM32H7_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32H7_QENCODER_SAMPLE_EVENT_8 - depends on !STM32H7_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice # Input channel event count - -endmenu # QEncoder Driver - -menu "FDCAN Driver Configuration" - depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3 - -menu "FDCAN1 Configuration" - depends on STM32H7_FDCAN1 - -config FDCAN1_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN1_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN1_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN1 - -menu "FDCAN2 Configuration" - depends on STM32H7_FDCAN2 - -config FDCAN2_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 100000 - -config FDCAN2_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 100000 - -config FDCAN2_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN2 - -menu "FDCAN3 Configuration" - depends on STM32H7_FDCAN3 - -config FDCAN3_BITRATE - int "CAN bitrate" - depends on !NET_CAN_CANFD - default 1000000 - -config FDCAN3_ARBI_BITRATE - int "CAN FD Arbitration phase bitrate" - depends on NET_CAN_CANFD - default 1000000 - -config FDCAN3_DATA_BITRATE - int "CAN FD Data phase bitrate" - depends on NET_CAN_CANFD - default 4000000 - -endmenu # STM32H7_FDCAN3 - -config STM32H7_FDCAN_REGDEBUG - bool "Enable register dump debugging" - depends on DEBUG_NET_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO and CONFIG_DEBUG_NET_INFO. - -config STM32H7_FDCAN_LOOPBACK - bool "Enable FDCAN loopback mode" - default n - ---help--- - Enable the FDCAN local loopback mode for testing purposes. - Requires a further choice of internal or external loopback mode. - - TODO: Enable separately for FDCAN1 and FDCAN2 - -choice - prompt "FDCAN Loopback Mode" - depends on STM32H7_FDCAN_LOOPBACK - default STM32H7_FDCAN_LOOPBACK_INTERNAL - -config STM32H7_FDCAN_LOOPBACK_INTERNAL - bool "Internal loopback mode" - ---help--- - Enable internal loopback mode, where both Tx and Rx are - disconnected from the CAN bus. This can be used for a "Hot Selftest", - meaning the FDCAN can be used without affecting a running CAN bus. - - All transmitted frames are treated as received frames and processed - accordingly. - -config STM32H7_FDCAN_LOOPBACK_EXTERNAL - bool "External loopback mode" - ---help--- - Enable external loopback mode, where the Rx pin is disconnected from - the CAN bus but the Tx pin remains connected. - - All transmitted frames are treated as received frames and processed - accordingly. - -endchoice # FDCAN Loopback Mode - -choice - prompt "FDCAN WorkQueue Selection" - default STM32H7_FDCAN_LPWORK - -config STM32H7_FDCAN_LPWORK - bool "Use LP work queue" - ---help--- - Use the low-priority (LP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -config STM32H7_FDCAN_HPWORK - bool "Use HP work queue" - ---help--- - Use the high-priority (HP) work queue for reception and transmission - of new frames and for processing of transmission timeouts. - -endchoice # FDCAN WorkQueue Selection - -endmenu # FDCAN Driver - menu "Progmem MTD configuration" if STM32_HAVE_OTA_PARTITION @@ -6665,7 +812,7 @@ config STM32_PROGMEM_OTA_PARTITION select MTD_BYTE_WRITE select MTD_PARTITION select MTD_PROGMEM - select STM32H7_PROGMEM + select STM32_PROGMEM ---help--- Initialize an MTD driver for the Flash, which will add an entry at /dev for application access from userspace. diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index 005c695adc8..e8fb7d38e3a 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -27,7 +27,7 @@ include armv7-m/Make.defs -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CHIP_CSRCS += stm32_flash.c endif @@ -35,7 +35,7 @@ ifeq ($(CONFIG_ARCH_STM32H7_DUALCORE),y) CHIP_CSRCS += stm32_dualcore.c endif -ifeq ($(CONFIG_STM32H7_HSEM),y) +ifeq ($(CONFIG_STM32_HSEM),y) CHIP_CSRCS += stm32_hsem.c endif @@ -55,7 +55,7 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32H7_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c endif @@ -71,51 +71,51 @@ ifeq ($(CONFIG_ARMV7M_DTCM),y) CHIP_CSRCS += stm32_dtcm.c endif -ifeq ($(CONFIG_STM32H7_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32H7_FDCAN),y) +ifeq ($(CONFIG_STM32_FDCAN),y) CHIP_CSRCS += stm32_fdcan_sock.c endif -ifeq ($(CONFIG_STM32H7_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32_rng.c endif -ifeq ($(CONFIG_STM32H7_BBSRAM),y) +ifeq ($(CONFIG_STM32_BBSRAM),y) CHIP_CSRCS += stm32_bbsram.c endif -ifeq ($(CONFIG_STM32H7_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32H7_FMC),y) +ifeq ($(CONFIG_STM32_FMC),y) CHIP_CSRCS += stm32_fmc.c endif -ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y) +ifeq ($(filter y,$(CONFIG_STM32_IWDG) $(CONFIG_STM32_RTC_LSICLOCK)),y) CHIP_CSRCS += stm32_lsi.c endif -ifeq ($(CONFIG_STM32H7_RTC_LSECLOCK),y) +ifeq ($(CONFIG_STM32_RTC_LSECLOCK),y) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32H7_I2C),y) +ifeq ($(CONFIG_STM32_I2C),y) CHIP_CSRCS += stm32_i2c.c endif -ifeq ($(CONFIG_STM32H7_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif -ifeq ($(CONFIG_STM32H7_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32_qspi.c endif -ifeq ($(CONFIG_STM32H7_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) CHIP_CSRCS += stm32_rtc.c ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32_exti_alarm.c @@ -128,7 +128,7 @@ CHIP_CSRCS += stm32_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CHIP_CSRCS += stm32_spi.c endif @@ -136,7 +136,7 @@ ifeq ($(CONFIG_SPI_SLAVE),y) CHIP_CSRCS += stm32_spi_slave.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CHIP_CSRCS += stm32_sdmmc.c endif @@ -144,7 +144,7 @@ ifeq ($(CONFIG_TIMER),y) CHIP_CSRCS += stm32_tim_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_TIMX_CAP),y) +ifeq ($(CONFIG_STM32_TIMX_CAP),y) CHIP_CSRCS += stm32_capture.c endif @@ -152,7 +152,7 @@ ifeq ($(CONFIG_CAPTURE),y) CHIP_CSRCS += stm32_capture_lowerhalf.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CHIP_CSRCS += stm32_ltdc.c endif @@ -171,23 +171,23 @@ endif endif endif -ifeq ($(CONFIG_STM32H7_TIM),y) +ifeq ($(CONFIG_STM32_TIM),y) CHIP_CSRCS += stm32_tim.c endif -ifeq ($(CONFIG_STM32H7_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32_lptim.c endif -ifeq ($(CONFIG_STM32H7_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32_pwm.c endif -ifeq ($(CONFIG_STM32H7_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32_pulsecount.c endif -ifeq ($(CONFIG_STM32H7_ETHMAC),y) +ifeq ($(CONFIG_STM32_ETHMAC),y) CHIP_CSRCS += stm32_ethernet.c endif @@ -206,22 +206,22 @@ CHIP_CSRCS += stm32_pminitialize.c endif endif -ifeq ($(CONFIG_STM32H7_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32_iwdg.c endif -ifeq ($(CONFIG_STM32H7_WWDG),y) +ifeq ($(CONFIG_STM32_WWDG),y) CHIP_CSRCS += stm32_wwdg.c endif -#ifeq ($(CONFIG_STM32H7_HASH),y) -#CHIP_CSRCS += stm32_hash.c -#endif - -ifeq ($(CONFIG_STM32H7_CRYP),y) +ifeq ($(CONFIG_STM32_CRYP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_aes.c endif +endif ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) +ifeq ($(CONFIG_STM32_HAVE_IP_CRYPTO_H7),y) CHIP_CSRCS += stm32_crypto.c endif +endif diff --git a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h index 74973a4004a..5ac1b4a0481 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_dmamux.h +++ b/arch/arm/src/stm32h7/hardware/stm32_dmamux.h @@ -203,15 +203,15 @@ /* Import DMAMUX map */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_dmamux.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_dmamux.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h index f22c76cd156..a65c2430761 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/hardware/stm32_ethernet.h @@ -33,11 +33,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -680,5 +680,5 @@ struct eth_desc_s ****************************************************************************/ #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_ETHERNET_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_exti.h b/arch/arm/src/stm32h7/hardware/stm32_exti.h index e197f4b6c42..bd5bf31c73e 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_exti.h +++ b/arch/arm/src/stm32h7/hardware/stm32_exti.h @@ -35,11 +35,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -243,5 +243,5 @@ #define EXTI_EVENT_ETHWKUP 86 /* Ethernet wakeup */ #define EXTI_EVENT_HSECSS 87 /* HSECSS interrupt */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32_flash.h b/arch/arm/src/stm32h7/hardware/stm32_flash.h index 399694f63f7..b24ccc58f70 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_flash.h +++ b/arch/arm/src/stm32h7/hardware/stm32_flash.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7b3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_flash.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_flash.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_gpio.h b/arch/arm/src/stm32h7/hardware/stm32_gpio.h index 83c989afaa2..68f682e41c9 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32_gpio.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_gpio.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_gpio.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_i2c.h b/arch/arm/src/stm32h7/hardware/stm32_i2c.h index 7b7efcd8549..e9b47c45689 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_i2c.h +++ b/arch/arm/src/stm32h7/hardware/stm32_i2c.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_i2c.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_i2c.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h index 18c199495ab..85b3d880ebd 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_memorymap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_memorymap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_memorymap.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h index db27991f33d..409bca78983 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pinmap.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pinmap.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pinmap.h" #else # error "Unsupported STM32 H7 Pin map" diff --git a/arch/arm/src/stm32h7/hardware/stm32_pwr.h b/arch/arm/src/stm32h7/hardware/stm32_pwr.h index 88f257e9a58..a3fe24507b8 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32_pwr.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_pwr.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_pwr.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_rcc.h b/arch/arm/src/stm32h7/hardware/stm32_rcc.h index 984f782d612..67ef3c5d180 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_rcc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_rcc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_rcc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h index 28bcba80b9a..b5d9bd01944 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h +++ b/arch/arm/src/stm32h7/hardware/stm32_sdmmc.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_sdmmc.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x3xx_sdmmc.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_spi.h b/arch/arm/src/stm32h7/hardware/stm32_spi.h index 44bae2e58fa..f342cc3ea35 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32_spi.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_spi.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_spi.h" #else # error "Unsupported STM32 H7 sub family" diff --git a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h index a48b13ff5d2..3403a0f6fd0 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32_syscfg.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_syscfg.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_syscfg.h" #else # error "Unsupported STM32 H7 part" diff --git a/arch/arm/src/stm32h7/hardware/stm32_uart.h b/arch/arm/src/stm32h7/hardware/stm32_uart.h index 9bc1408a9b4..0e6820748e3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32_uart.h @@ -30,15 +30,15 @@ #include #include "chip.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "hardware/stm32h7x3xx_uart.h" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "hardware/stm32h7x3xx_uart.h" #else # error "Unsupported STM32 H7 memory map" diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h index c38ff4666e2..310899214c3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_gpio.h @@ -30,11 +30,11 @@ #include #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -120,7 +120,7 @@ # define STM32_GPIOE_AFRH (STM32_GPIOE_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define STM32_GPIOF_MODER (STM32_GPIOF_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -133,7 +133,7 @@ # define STM32_GPIOF_AFRH (STM32_GPIOF_BASE+STM32_GPIO_AFRH_OFFSET) #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define STM32_GPIOG_MODER (STM32_GPIOG_BASE+STM32_GPIO_MODER_OFFSET) # define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE+STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE+STM32_GPIO_OSPEED_OFFSET) @@ -390,5 +390,5 @@ #define GPIO_AFRH15_SHIFT (28) #define GPIO_AFRH15_MASK (15 << GPIO_AFRH15_SHIFT) -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_GPIO_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h index 215c7be0ed8..1e3737d13e3 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h @@ -65,7 +65,7 @@ #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */ -# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX +# ifdef CONFIG_STM32_STM32H72XXX_OR_STM32H73XXX # define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */ # else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */ # define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h index 46b114c3e67..3974629f516 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pinmap.h @@ -31,11 +31,11 @@ #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -1538,5 +1538,5 @@ #define GPIO_UART8_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN1) #define GPIO_UART8_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTJ|GPIO_PIN8) -#endif /* CONFIG_STM32H7_STM32H7X0XX CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X0XX CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_PINMAP_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h index 977f1c41350..6643ce2452f 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_pwr.h @@ -131,10 +131,10 @@ #define STM32_PWR_CR3_BYPASS (1 << 0) /* Bit 0: Power management unit bypass */ #define STM32_PWR_CR3_LDOEN (1 << 1) /* Bit 1: Low drop-out regulator enable */ -#ifndef CONFIG_STM32H7_HAVE_SMPS +#ifndef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SCUEN (1 << 2) /* Bit 2: Supply configuration update enable */ #endif -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_SDEN (1 << 2) /* Bit 2: SMPS step-down converter enable */ # define STM32_PWR_CR3_SMPSEXTHP (1 << 3) /* Bit 3: SMPS step-down converter external power delivery selection */ # define STM32_PWR_CR3_SMPSLEVEL_SHIFT (4) /* BitS 4-5: SMPS step-down converter voltage output level selection */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h index 8124fbd9c7b..308dc30f621 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_rcc.h @@ -827,10 +827,10 @@ /* RCC Global Control register */ #define RCC_GCR_WW1RSC (1 << 0) /* Bit 0: WWDG1 reset scope control */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_WW2RSC (1 << 1) /* Bit 1: WWDG2 reset scope control */ #endif -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define RCC_GCR_BOOT_C1 (1 << 2) /* Bit 2: Allows CPU1 to boot */ # define RCC_GCR_BOOT_C2 (1 << 3) /* Bit 3: Allows CPU2 to boot */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h index fa7c71d92bf..2cfb71ca647 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_spi.h @@ -29,11 +29,11 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -466,5 +466,5 @@ /* TODO: SPI/I2S configuration register */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_SPI_H */ diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h index e259beff596..e5c6fe8e3ce 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_syscfg.h @@ -56,7 +56,7 @@ #define STM32_SYSCFG_UR_OFFSET(n) (0x0300 + ((n) << 2)) #define STM32_SYSCFG_UR0_OFFSET 0x0300 /* User register 0 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1_OFFSET 0x0304 /* User register 2 */ #endif #define STM32_SYSCFG_UR2_OFFSET 0x0308 /* User register 2 */ @@ -92,7 +92,7 @@ #define STM32_SYSCFG_PWRCR (STM32_SYSCFG_BASE + STM32_SYSCFG_PWRCR_OFFSET) #define STM32_SYSCFG_UR0 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR0_OFFSET) -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define STM32_SYSCFG_UR1 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR1_OFFSET) #endif #define STM32_SYSCFG_UR2 (STM32_SYSCFG_BASE + STM32_SYSCFG_UR2_OFFSET) @@ -220,7 +220,7 @@ /* User register 1 */ -#ifdef CONFIG_STM32H7_HAVE_CM4 +#ifdef CONFIG_STM32_HAVE_CM4 # define SYSCFG_UR1_BCM4 (1 << 0) /* Bit 0: Boot Cortex-M4 */ # define SYSCFG_UR1_BCM7 (1 << 16) /* Bit 16: Boot Cortex-M7 */ #endif diff --git a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h index 7bab6c142c4..84a46958e43 100644 --- a/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h +++ b/arch/arm/src/stm32h7/hardware/stm32h7x3xx_uart.h @@ -31,11 +31,11 @@ #include "chip.h" #include "hardware/stm32_memorymap.h" -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Pre-processor Definitions @@ -415,5 +415,5 @@ # define USART_PRESC_DIV64 (9 << USART_PRESC_SHIFT) /* Input clock divided by 64 */ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ #endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32H7X3XX_UART_H */ diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 1db742bb688..da606d9df3e 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -77,8 +77,8 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /**************************************************************************** * Pre-processor Definitions @@ -92,9 +92,9 @@ /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32H7_DMA1) && !defined(CONFIG_STM32H7_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32H7 ADC DMA support requires CONFIG_STM32H7_DMA1 or CONFIG_STM32H7_DMA2" +# error "STM32H7 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -191,7 +191,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t chanlist[CONFIG_STM32H7_ADC_MAX_SAMPLES]; + uint8_t chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; }; /**************************************************************************** @@ -254,10 +254,10 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, /* ADC Interrupt Handler */ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); #endif @@ -289,11 +289,11 @@ static const struct adc_ops_s g_adcops = /* ADC1 state */ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = @@ -305,19 +305,19 @@ static struct stm32_dev_s g_adcpriv1 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC1_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC1_TIMTRIG, + .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, .trcc_enr = ADC1_TIMER_RCC_ENR, .trcc_en = ADC1_TIMER_RCC_EN, .extsel = ADC1_EXTSEL_VALUE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC1_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH, #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -339,11 +339,11 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = @@ -355,19 +355,19 @@ static struct stm32_dev_s g_adcpriv2 = .mbase = STM32_ADC1_BASE, .initialized = false, #ifdef ADC2_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC2_TIMTRIG, + .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, .trcc_enr = ADC2_TIMER_RCC_ENR, .trcc_en = ADC2_TIMER_RCC_EN, .extsel = ADC2_EXTSEL_VALUE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC2_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH, #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -389,11 +389,11 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32H7_ADC_MAX_SAMPLES * - CONFIG_STM32H7_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = @@ -405,19 +405,19 @@ static struct stm32_dev_s g_adcpriv3 = .mbase = STM32_ADC3_BASE, .initialized = false, #ifdef ADC3_HAVE_TIMER - .trigger = CONFIG_STM32H7_ADC3_TIMTRIG, + .trigger = CONFIG_STM32_ADC3_TIMTRIG, .tbase = ADC3_TIMER_BASE, .trcc_enr = ADC3_TIMER_RCC_ENR, .trcc_en = ADC3_TIMER_RCC_EN, .extsel = ADC3_EXTSEL_VALUE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32H7_ADC3_DMA_BATCH, + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH, #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -1381,7 +1381,7 @@ static int adc_setup(struct adc_dev_s *dev) * ADC1 and ADC2 are enabled.) */ -#if defined(CONFIG_STM32H7_ADC1) && defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) && defined(CONFIG_STM32_ADC2) if ((dev == &g_adcdev1 && !((struct stm32_dev_s *)g_adcdev2.ad_priv)->initialized) || (dev == &g_adcdev2 && @@ -1880,7 +1880,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2163,13 +2163,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2178,7 +2178,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2203,7 +2203,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -2312,19 +2312,19 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: ainfo("ADC1 selected\n"); dev = &g_adcdev1; break; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: ainfo("ADC2 selected\n"); dev = &g_adcdev2; break; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: ainfo("ADC3 selected\n"); dev = &g_adcdev3; @@ -2340,10 +2340,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; priv->cb = NULL; - DEBUGASSERT(cchannels <= CONFIG_STM32H7_ADC_MAX_SAMPLES); - if (cchannels > CONFIG_STM32H7_ADC_MAX_SAMPLES) + DEBUGASSERT(cchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (cchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - cchannels = CONFIG_STM32H7_ADC_MAX_SAMPLES; + cchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = cchannels; @@ -2360,5 +2360,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32h7/stm32_adc.h b/arch/arm/src/stm32h7/stm32_adc.h index ce6a460ca92..174d6739e00 100644 --- a/arch/arm/src/stm32h7/stm32_adc.h +++ b/arch/arm/src/stm32h7/stm32_adc.h @@ -46,80 +46,80 @@ * well. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_ADC -# undef CONFIG_STM32H7_TIM1_ADC1 -# undef CONFIG_STM32H7_TIM1_ADC2 -# undef CONFIG_STM32H7_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_ADC -# undef CONFIG_STM32H7_TIM2_ADC1 -# undef CONFIG_STM32H7_TIM2_ADC2 -# undef CONFIG_STM32H7_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_ADC -# undef CONFIG_STM32H7_TIM3_ADC1 -# undef CONFIG_STM32H7_TIM3_ADC2 -# undef CONFIG_STM32H7_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_ADC -# undef CONFIG_STM32H7_TIM4_ADC1 -# undef CONFIG_STM32H7_TIM4_ADC2 -# undef CONFIG_STM32H7_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM6 -# undef CONFIG_STM32H7_TIM6_ADC -# undef CONFIG_STM32H7_TIM6_ADC1 -# undef CONFIG_STM32H7_TIM6_ADC2 -# undef CONFIG_STM32H7_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_ADC -# undef CONFIG_STM32H7_TIM8_ADC1 -# undef CONFIG_STM32H7_TIM8_ADC2 -# undef CONFIG_STM32H7_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_ADC -# undef CONFIG_STM32H7_TIM15_ADC1 -# undef CONFIG_STM32H7_TIM15_ADC2 -# undef CONFIG_STM32H7_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32H7_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32H7_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -127,24 +127,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32H7_ADC1_DMA) || defined(CONFIG_STM32H7_ADC2_DMA) || \ - defined(CONFIG_STM32H7_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32H7_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32H7_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -154,43 +154,43 @@ * information about the timer. */ -#if defined(CONFIG_STM32H7_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC1) +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC1) +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC1) +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC1) +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC1_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC1) +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC1_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC1_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC1) +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -201,52 +201,52 @@ #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC1_TIMTRIG -# error "CONFIG_STM32H7_ADC1_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC1_TIMTRIG +# error "CONFIG_STM32_ADC1_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC2) +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC2) +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC2) +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC2) +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC2_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC2) +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC2_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC2_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC2) +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -257,52 +257,52 @@ #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC2_TIMTRIG -# error "CONFIG_STM32H7_ADC2_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC2_TIMTRIG +# error "CONFIG_STM32_ADC2_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM1EN -#elif defined(CONFIG_STM32H7_TIM2_ADC3) +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM2EN -#elif defined(CONFIG_STM32H7_TIM3_ADC3) +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM3EN -#elif defined(CONFIG_STM32H7_TIM4_ADC3) +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM4EN -#elif defined(CONFIG_STM32H7_TIM6_ADC3) +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB1LENR # define ADC3_TIMER_RCC_EN RCC_APB1LENR_TIM6EN -#elif defined(CONFIG_STM32H7_TIM8_ADC3) +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN # define ADC3_TIMER_RCC_ENR STM32_RCC_APB2ENR # define ADC3_TIMER_RCC_EN RCC_APB2ENR_TIM8EN -#elif defined(CONFIG_STM32H7_TIM15_ADC3) +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN @@ -313,11 +313,11 @@ #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32H7_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# ifndef CONFIG_STM32H7_ADC3_TIMTRIG -# error "CONFIG_STM32H7_ADC3_TIMTRIG not defined" +# ifndef CONFIG_STM32_ADC3_TIMTRIG +# error "CONFIG_STM32_ADC3_TIMTRIG not defined" # warning "Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO" # endif #endif @@ -455,315 +455,315 @@ #define ADC3_EXTSEL_T15CC4 ADC_CFGR_EXTSEL_T15CC4 #define ADC3_EXTSEL_T15TRGO ADC_CFGR_EXTSEL_T15TRGO -#if defined(CONFIG_STM32H7_TIM1_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 5 +# elif CONFIG_STM32_ADC1_TIMTRIG == 5 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC1) -# if CONFIG_STM32H7_ADC1_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC1) +# if CONFIG_STM32_ADC1_TIMTRIG == 0 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 1 +# elif CONFIG_STM32_ADC1_TIMTRIG == 1 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 2 +# elif CONFIG_STM32_ADC1_TIMTRIG == 2 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 3 +# elif CONFIG_STM32_ADC1_TIMTRIG == 3 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC1_TIMTRIG == 4 +# elif CONFIG_STM32_ADC1_TIMTRIG == 4 # define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC1_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC1_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 5 +# elif CONFIG_STM32_ADC2_TIMTRIG == 5 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC2) -# if CONFIG_STM32H7_ADC2_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC2) +# if CONFIG_STM32_ADC2_TIMTRIG == 0 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 1 +# elif CONFIG_STM32_ADC2_TIMTRIG == 1 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 2 +# elif CONFIG_STM32_ADC2_TIMTRIG == 2 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 3 +# elif CONFIG_STM32_ADC2_TIMTRIG == 3 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC2_TIMTRIG == 4 +# elif CONFIG_STM32_ADC2_TIMTRIG == 4 # define ADC2_EXTSEL_VALUE ADC2_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC2_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC2_TIMTRIG is out of range" # endif #endif -#if defined(CONFIG_STM32H7_TIM1_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#if defined(CONFIG_STM32_TIM1_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T1TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM2_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM2_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T2TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM3_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM3_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T3TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM4_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM4_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T4TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM6_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM6_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T6TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM8_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM8_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 5 +# elif CONFIG_STM32_ADC3_TIMTRIG == 5 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T8TRGO2 # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif -#elif defined(CONFIG_STM32H7_TIM15_ADC3) -# if CONFIG_STM32H7_ADC3_TIMTRIG == 0 +#elif defined(CONFIG_STM32_TIM15_ADC3) +# if CONFIG_STM32_ADC3_TIMTRIG == 0 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC1 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 1 +# elif CONFIG_STM32_ADC3_TIMTRIG == 1 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC2 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 2 +# elif CONFIG_STM32_ADC3_TIMTRIG == 2 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC3 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 3 +# elif CONFIG_STM32_ADC3_TIMTRIG == 3 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15CC4 -# elif CONFIG_STM32H7_ADC3_TIMTRIG == 4 +# elif CONFIG_STM32_ADC3_TIMTRIG == 4 # define ADC3_EXTSEL_VALUE ADC3_EXTSEL_T15TRGO # else -# error "CONFIG_STM32H7_ADC3_TIMTRIG is out of range" +# error "CONFIG_STM32_ADC3_TIMTRIG is out of range" # endif #endif @@ -809,5 +809,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ADC_H */ diff --git a/arch/arm/src/stm32h7/stm32_aes.h b/arch/arm/src/stm32h7/stm32_aes.h index ad9595d946a..207bcad7262 100644 --- a/arch/arm/src/stm32h7/stm32_aes.h +++ b/arch/arm/src/stm32h7/stm32_aes.h @@ -37,7 +37,7 @@ * variants include CRYP */ -#ifdef CONFIG_STM32H7_HAVE_CRYP +#ifdef CONFIG_STM32_HAVE_CRYP # include "hardware/stm32h7xxxx_cryp.h" #else # error "Unknown chip for AES" diff --git a/arch/arm/src/stm32h7/stm32_allocateheap.c b/arch/arm/src/stm32h7/stm32_allocateheap.c index 3b64acba794..ab77f78604d 100644 --- a/arch/arm/src/stm32h7/stm32_allocateheap.c +++ b/arch/arm/src/stm32h7/stm32_allocateheap.c @@ -57,7 +57,7 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - !defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + !defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support disabled */ @@ -84,7 +84,7 @@ * - Tightly Coupled Memory (TCM RAM), we can use Data TCM (DTCM) for system * heap. Note that DTCM has a number of limitations, for example DMA * transfers to/from DTCM are limited. - * Define CONFIG_STM32H7_DTCMEXCLUDE to exclude the DTCM from heap. + * Define CONFIG_STM32_DTCMEXCLUDE to exclude the DTCM from heap. * +1 to CONFIG_MM_REGIONS if you want to use DTCM. * * - External SDRAM can be connected to the FMC peripheral. Initialization @@ -117,7 +117,7 @@ # define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) #elif defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Configuration for M7 core when M4 core support enabled */ @@ -139,7 +139,7 @@ #endif #undef HAVE_SRAM4 -#if !defined(CONFIG_STM32H7_SRAM4EXCLUDE) +#if !defined(CONFIG_STM32_SRAM4EXCLUDE) # define HAVE_SRAM4 1 # define SRAM4_START ((uint32_t)(STM32_SRAM4_BASE)) @@ -158,7 +158,7 @@ /* DTCM to be excluded from the main heap. */ -#ifdef CONFIG_STM32H7_DTCMEXCLUDE +#ifdef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM #endif @@ -410,7 +410,7 @@ void arm_addregion(void) } #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC stm32_fmc_init(); #endif diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index 8f27740c1aa..37dc0b741b2 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -50,14 +50,14 @@ #include "mpu.h" #include "stm32_pwr.h" -#ifdef CONFIG_STM32H7_BBSRAM +#ifdef CONFIG_STM32_BBSRAM /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_BKPSRAM) -#error Driver Requires CONFIG_STM32H7_BKPSRAM to be enabled +#if !defined(CONFIG_STM32_BKPSRAM) +#error Driver Requires CONFIG_STM32_BKPSRAM to be enabled #endif #define MAX_OPENCNT (255) /* Limit of uint8_t */ @@ -168,7 +168,7 @@ static const struct file_operations g_stm32_bbsram_fops = #endif }; -static struct stm32_bbsram_s g_bbsram[CONFIG_STM32H7_BBSRAM_FILES]; +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32_BBSRAM_FILES]; /**************************************************************************** * Private Functions @@ -690,7 +690,7 @@ static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) avail = STM32_BBSRAM_SIZE; - for (i = 0; (i < CONFIG_STM32H7_BBSRAM_FILES) && ent[i] && (avail > 0); + for (i = 0; (i < CONFIG_STM32_BBSRAM_FILES) && ent[i] && (avail > 0); i++) { /* Validate the actual allocations against what is in the BBSRAM */ @@ -855,7 +855,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { struct bbsramfh_s *bbf; @@ -873,7 +873,7 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) { once = true; - DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32H7_BBSRAM_FILES); + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32_BBSRAM_FILES); bbf = g_bbsram[fileno].bbf; diff --git a/arch/arm/src/stm32h7/stm32_bbsram.h b/arch/arm/src/stm32h7/stm32_bbsram.h index 08421e22571..cecff041fa7 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.h +++ b/arch/arm/src/stm32h7/stm32_bbsram.h @@ -48,8 +48,8 @@ #define STM32_BBSRAM_SIZE 4096 -#if !defined(CONFIG_STM32H7_BBSRAM_FILES) -# define CONFIG_STM32H7_BBSRAM_FILES 4 +#if !defined(CONFIG_STM32_BBSRAM_FILES) +# define CONFIG_STM32_BBSRAM_FILES 4 #endif /* REVISIT: What guarantees that STM32_BBSRAM_GETDESC_IOCTL has a unique @@ -107,8 +107,8 @@ extern "C" * the last entry should be 0 * A size of -1 will use all the remaining spaces * - * If the length of sizes is greater then CONFIG_STM32H7_BBSRAM_FILES - * CONFIG_STM32H7_BBSRAM_FILES will be returned. + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. * * Returned Value: * Number of files created on success; Negated errno on failure. @@ -137,7 +137,7 @@ int stm32_bbsraminitialize(char *devpath, int *sizes); * *****************************************************************************/ -#if defined(CONFIG_STM32H7_SAVE_CRASHDUMP) +#if defined(CONFIG_STM32_SAVE_CRASHDUMP) int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); #endif diff --git a/arch/arm/src/stm32h7/stm32_capture.c b/arch/arm/src/stm32h7/stm32_capture.c index ec1c3e0dfd7..32ef41e9d9c 100644 --- a/arch/arm/src/stm32h7/stm32_capture.c +++ b/arch/arm/src/stm32h7/stm32_capture.c @@ -49,7 +49,7 @@ /* Sanity checks ************************************************************/ -#if !defined(CONFIG_STM32H7_STM32H7X3XX) +#if !defined(CONFIG_STM32_STM32H7X3XX) # warning "This driver is for STM32H7X3XX devices" #endif @@ -59,7 +59,7 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIMX_CAP) +#if defined(CONFIG_STM32_TIMX_CAP) /* Check if any channel is enabled. * This is done to simplify the logic below. @@ -102,25 +102,25 @@ /* Check if we have any advanced timers */ -#if defined(CONFIG_STM32H7_TIM1_CAP) || defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM8_CAP) # define USE_ADVANCED_TIM 1 #endif /* Check if we have any general purpose timers */ -#if defined(CONFIG_STM32H7_TIM2_CAP) || defined(CONFIG_STM32H7_TIM3_CAP) || \ - defined(CONFIG_STM32H7_TIM4_CAP) || defined(CONFIG_STM32H7_TIM5_CAP) || \ - defined(CONFIG_STM32H7_TIM12_CAP) || defined(CONFIG_STM32H7_TIM13_CAP) || \ - defined(CONFIG_STM32H7_TIM14_CAP) || defined(CONFIG_STM32H7_TIM15_CAP) || \ - defined(CONFIG_STM32H7_TIM16_CAP) || defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || \ + defined(CONFIG_STM32_TIM14_CAP) || defined(CONFIG_STM32_TIM15_CAP) || \ + defined(CONFIG_STM32_TIM16_CAP) || defined(CONFIG_STM32_TIM17_CAP) # define USE_GENERAL_TIM 1 #endif /* Check if we have any low-power timers */ -#if defined(CONFIG_STM32H7_LPTIM1_CAP) || defined(CONFIG_STM32H7_LPTIM2_CAP) || \ - defined(CONFIG_STM32H7_LPTIM3_CAP) || defined(CONFIG_STM32H7_LPTIM4_CAP) || \ - defined(CONFIG_STM32H7_LPTIM5_CAP) +#if defined(CONFIG_STM32_LPTIM1_CAP) || defined(CONFIG_STM32_LPTIM2_CAP) || \ + defined(CONFIG_STM32_LPTIM3_CAP) || defined(CONFIG_STM32_LPTIM4_CAP) || \ + defined(CONFIG_STM32_LPTIM5_CAP) # define USE_LOWPOWER_TIM 1 #endif @@ -237,7 +237,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: switch (channel) { @@ -265,7 +265,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: switch (channel) { @@ -293,7 +293,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: switch (channel) { @@ -321,7 +321,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: switch (channel) { @@ -349,7 +349,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: switch (channel) { @@ -379,7 +379,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: switch (channel) { @@ -407,7 +407,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case STM32_TIM9_BASE: switch (channel) { @@ -435,7 +435,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case STM32_TIM10_BASE: switch (channel) { @@ -463,7 +463,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case STM32_TIM11_BASE: switch (channel) { @@ -491,7 +491,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: switch (channel) { @@ -519,7 +519,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: switch (channel) { @@ -547,7 +547,7 @@ uint32_t stm32_cap_gpio(const struct stm32_cap_priv_s *priv, break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: switch (channel) { @@ -589,31 +589,31 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, { /* APB2 Timers */ -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case STM32_TIM1_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM1EN; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case STM32_TIM8_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM8EN; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case STM32_TIM15_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM15EN; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case STM32_TIM16_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM16EN; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case STM32_TIM17_BASE: offset = STM32_RCC_APB2ENR; mask = RCC_APB2ENR_TIM17EN; @@ -622,50 +622,50 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB1L Timers */ -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case STM32_TIM2_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM2EN; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case STM32_TIM3_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM3EN; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case STM32_TIM4_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM4EN; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case STM32_TIM5_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM5EN; break; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case STM32_TIM12_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM12EN; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case STM32_TIM13_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM13EN; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case STM32_TIM14_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_TIM14EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM1_CAP +#ifdef CONFIG_STM32_LPTIM1_CAP case STM32_LPTIM1_BASE: offset = STM32_RCC_APB1LENR; mask = RCC_APB1LENR_LPTIM1EN; @@ -674,25 +674,25 @@ static inline int stm32_cap_set_rcc(const struct stm32_cap_priv_s *priv, /* APB4 Timers */ -#ifdef CONFIG_STM32H7_LPTIM2_CAP +#ifdef CONFIG_STM32_LPTIM2_CAP case STM32_LPTIM2_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM2EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3_CAP +#ifdef CONFIG_STM32_LPTIM3_CAP case STM32_LPTIM3_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM3EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4_CAP +#ifdef CONFIG_STM32_LPTIM4_CAP case STM32_LPTIM4_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM4EN; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5_CAP +#ifdef CONFIG_STM32_LPTIM5_CAP case STM32_LPTIM5_BASE: offset = STM32_RCC_APB4ENR; mask = RCC_APB4ENR_LPTIM5EN; @@ -744,62 +744,62 @@ static int stm32_cap_setclock(struct stm32_cap_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case STM32_TIM9_BASE: freqin = STM32_APB2_TIM9_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case STM32_TIM10_BASE: freqin = STM32_APB2_TIM10_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case STM32_TIM11_BASE: freqin = STM32_APB2_TIM11_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; @@ -1350,7 +1350,7 @@ struct stm32_cap_ops_s stm32_cap_ops = .getflags = &stm32_cap_getflags }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP const struct stm32_cap_priv_s stm32_tim1_priv = { .ops = &stm32_cap_ops, @@ -1362,7 +1362,7 @@ const struct stm32_cap_priv_s stm32_tim1_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP const struct stm32_cap_priv_s stm32_tim2_priv = { .ops = &stm32_cap_ops, @@ -1374,7 +1374,7 @@ const struct stm32_cap_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP const struct stm32_cap_priv_s stm32_tim3_priv = { .ops = &stm32_cap_ops, @@ -1386,7 +1386,7 @@ const struct stm32_cap_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP const struct stm32_cap_priv_s stm32_tim4_priv = { .ops = &stm32_cap_ops, @@ -1398,7 +1398,7 @@ const struct stm32_cap_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP const struct stm32_cap_priv_s stm32_tim5_priv = { .ops = &stm32_cap_ops, @@ -1412,7 +1412,7 @@ const struct stm32_cap_priv_s stm32_tim5_priv = /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP const struct stm32_cap_priv_s stm32_tim8_priv = { .ops = &stm32_cap_ops, @@ -1424,7 +1424,7 @@ const struct stm32_cap_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP const struct stm32_cap_priv_s stm32_tim9_priv = { .ops = &stm32_cap_ops, @@ -1436,7 +1436,7 @@ const struct stm32_cap_priv_s stm32_tim9_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP const struct stm32_cap_priv_s stm32_tim10_priv = { .ops = &stm32_cap_ops, @@ -1448,7 +1448,7 @@ const struct stm32_cap_priv_s stm32_tim10_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP const struct stm32_cap_priv_s stm32_tim11_priv = { .ops = &stm32_cap_ops, @@ -1460,7 +1460,7 @@ const struct stm32_cap_priv_s stm32_tim11_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP const struct stm32_cap_priv_s stm32_tim12_priv = { .ops = &stm32_cap_ops, @@ -1472,7 +1472,7 @@ const struct stm32_cap_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP const struct stm32_cap_priv_s stm32_tim13_priv = { .ops = &stm32_cap_ops, @@ -1484,7 +1484,7 @@ const struct stm32_cap_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP const struct stm32_cap_priv_s stm32_tim14_priv = { .ops = &stm32_cap_ops, @@ -1496,7 +1496,7 @@ const struct stm32_cap_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static const struct stm32_cap_priv_s stm32_tim15_priv = { .ops = &stm32_cap_ops, @@ -1508,7 +1508,7 @@ static const struct stm32_cap_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static const struct stm32_cap_priv_s stm32_tim16_priv = { .ops = &stm32_cap_ops, @@ -1520,7 +1520,7 @@ static const struct stm32_cap_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static const struct stm32_cap_priv_s stm32_tim17_priv = { .ops = &stm32_cap_ops, @@ -1536,54 +1536,54 @@ static inline const struct stm32_cap_priv_s * stm32_cap_get_priv(int timer) { switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: return &stm32_tim1_priv; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: return &stm32_tim2_priv; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: return &stm32_tim3_priv; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: return &stm32_tim4_priv; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: return &stm32_tim5_priv; #endif /* TIM6 and TIM7 cannot be used in capture */ -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: return &stm32_tim8_priv; #endif -#ifdef CONFIG_STM32H7_TIM9_CAP +#ifdef CONFIG_STM32_TIM9_CAP case 9: return &stm32_tim9_priv; #endif -#ifdef CONFIG_STM32H7_TIM10_CAP +#ifdef CONFIG_STM32_TIM10_CAP case 10: return &stm32_tim10_priv; #endif -#ifdef CONFIG_STM32H7_TIM11_CAP +#ifdef CONFIG_STM32_TIM11_CAP case 11: return &stm32_tim11_priv; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: return &stm32_tim12_priv; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: return &stm32_tim13_priv; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: return &stm32_tim14_priv; #endif @@ -1640,4 +1640,4 @@ int stm32_cap_deinit(struct stm32_cap_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM14) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM14) */ diff --git a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c index c1a1e71517d..79ee35e3022 100644 --- a/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_capture_lowerhalf.c @@ -125,123 +125,123 @@ static const struct cap_ops_s g_cap_ops = .getfreq = stm32_getfreq, }; -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP static struct stm32_lowerhalf_s g_cap1_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM1_RES, - .channel = CONFIG_STM32H7_TIM1_CHANNEL, - .clock = CONFIG_STM32H7_TIM1_CLOCK, + .channel = CONFIG_STM32_TIM1_CHANNEL, + .clock = CONFIG_STM32_TIM1_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP static struct stm32_lowerhalf_s g_cap2_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM2_RES, - .channel = CONFIG_STM32H7_TIM2_CHANNEL, - .clock = CONFIG_STM32H7_TIM2_CLOCK, + .channel = CONFIG_STM32_TIM2_CHANNEL, + .clock = CONFIG_STM32_TIM2_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP static struct stm32_lowerhalf_s g_cap3_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM3_RES, - .channel = CONFIG_STM32H7_TIM3_CHANNEL, - .clock = CONFIG_STM32H7_TIM3_CLOCK, + .channel = CONFIG_STM32_TIM3_CHANNEL, + .clock = CONFIG_STM32_TIM3_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP static struct stm32_lowerhalf_s g_cap4_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM4_RES, - .channel = CONFIG_STM32H7_TIM4_CHANNEL, - .clock = CONFIG_STM32H7_TIM4_CLOCK, + .channel = CONFIG_STM32_TIM4_CHANNEL, + .clock = CONFIG_STM32_TIM4_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP static struct stm32_lowerhalf_s g_cap5_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM5_RES, - .channel = CONFIG_STM32H7_TIM5_CHANNEL, - .clock = CONFIG_STM32H7_TIM5_CLOCK, + .channel = CONFIG_STM32_TIM5_CHANNEL, + .clock = CONFIG_STM32_TIM5_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP static struct stm32_lowerhalf_s g_cap8_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM8_RES, - .channel = CONFIG_STM32H7_TIM8_CHANNEL, - .clock = CONFIG_STM32H7_TIM8_CLOCK, + .channel = CONFIG_STM32_TIM8_CHANNEL, + .clock = CONFIG_STM32_TIM8_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP static struct stm32_lowerhalf_s g_cap12_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM12_RES, - .channel = CONFIG_STM32H7_TIM12_CHANNEL, - .clock = CONFIG_STM32H7_TIM12_CLOCK, + .channel = CONFIG_STM32_TIM12_CHANNEL, + .clock = CONFIG_STM32_TIM12_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP static struct stm32_lowerhalf_s g_cap13_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM13_RES, - .channel = CONFIG_STM32H7_TIM13_CHANNEL, - .clock = CONFIG_STM32H7_TIM13_CLOCK, + .channel = CONFIG_STM32_TIM13_CHANNEL, + .clock = CONFIG_STM32_TIM13_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP static struct stm32_lowerhalf_s g_cap14_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM14_RES, - .channel = CONFIG_STM32H7_TIM14_CHANNEL, - .clock = CONFIG_STM32H7_TIM14_CLOCK, + .channel = CONFIG_STM32_TIM14_CHANNEL, + .clock = CONFIG_STM32_TIM14_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP static struct stm32_lowerhalf_s g_cap15_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM15_RES, - .channel = CONFIG_STM32H7_TIM15_CHANNEL, - .clock = CONFIG_STM32H7_TIM15_CLOCK, + .channel = CONFIG_STM32_TIM15_CHANNEL, + .clock = CONFIG_STM32_TIM15_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP static struct stm32_lowerhalf_s g_cap16_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM16_RES, - .channel = CONFIG_STM32H7_TIM16_CHANNEL, - .clock = CONFIG_STM32H7_TIM16_CLOCK, + .channel = CONFIG_STM32_TIM16_CHANNEL, + .clock = CONFIG_STM32_TIM16_CLOCK, }; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP static struct stm32_lowerhalf_s g_cap17_lowerhalf = { .ops = &g_cap_ops, .resolution = STM32_TIM17_RES, - .channel = CONFIG_STM32H7_TIM17_CHANNEL, - .clock = CONFIG_STM32H7_TIM17_CLOCK, + .channel = CONFIG_STM32_TIM17_CHANNEL, + .clock = CONFIG_STM32_TIM17_CLOCK, }; #endif @@ -504,62 +504,62 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_CAP +#ifdef CONFIG_STM32_TIM1_CAP case 1: lower = &g_cap1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2_CAP +#ifdef CONFIG_STM32_TIM2_CAP case 2: lower = &g_cap2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3_CAP +#ifdef CONFIG_STM32_TIM3_CAP case 3: lower = &g_cap3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4_CAP +#ifdef CONFIG_STM32_TIM4_CAP case 4: lower = &g_cap4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5_CAP +#ifdef CONFIG_STM32_TIM5_CAP case 5: lower = &g_cap5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8_CAP +#ifdef CONFIG_STM32_TIM8_CAP case 8: lower = &g_cap8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12_CAP +#ifdef CONFIG_STM32_TIM12_CAP case 12: lower = &g_cap12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13_CAP +#ifdef CONFIG_STM32_TIM13_CAP case 13: lower = &g_cap13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14_CAP +#ifdef CONFIG_STM32_TIM14_CAP case 14: lower = &g_cap14_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM15_CAP +#ifdef CONFIG_STM32_TIM15_CAP case 15: lower = &g_cap15_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM16_CAP +#ifdef CONFIG_STM32_TIM16_CAP case 16: lower = &g_cap16_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM17_CAP +#ifdef CONFIG_STM32_TIM17_CAP case 17: lower = &g_cap17_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_dma.c b/arch/arm/src/stm32h7/stm32_dma.c index adbecb87cea..5ea0a3f87e7 100644 --- a/arch/arm/src/stm32h7/stm32_dma.c +++ b/arch/arm/src/stm32h7/stm32_dma.c @@ -51,22 +51,22 @@ #define DMAMUX_NUM 2 #define DMA_CONTROLLERS 4 -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA # define MDMA_NCHAN 16 #else # define MDMA_NCHAN 0 #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NSTREAMS 8 #else # define DMA1_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NSTREAMS 8 #else # define DMA2_NSTREAMS 0 #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA # define BDMA_NCHAN 8 #else # define BDMA_NCHAN 0 @@ -185,7 +185,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA static void stm32_mdma_disable(DMA_CHANNEL dmachan); static int stm32_mdma_interrupt(int irq, void *context, void *arg); static void stm32_mdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -193,7 +193,7 @@ static void stm32_mdma_free(DMA_HANDLE handle); static void stm32_mdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_mdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -201,7 +201,7 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_sdma_disable(DMA_CHANNEL dmachan); static int stm32_sdma_interrupt(int irq, void *context, void *arg); static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -209,7 +209,7 @@ static void stm32_sdma_free(DMA_HANDLE handle); static void stm32_sdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_sdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -217,7 +217,7 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg); #endif #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA static void stm32_bdma_disable(DMA_CHANNEL dmachan); static int stm32_bdma_interrupt(int irq, void *context, void *arg); static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg); @@ -225,7 +225,7 @@ static void stm32_bdma_free(DMA_HANDLE handle); static void stm32_bdma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool half); static size_t stm32_bdma_residual(DMA_HANDLE handle); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg); #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -265,7 +265,7 @@ static inline void dmachan_modifyreg32(DMA_CHANNEL dmachan, struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* 0 - MDMA */ { @@ -275,7 +275,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_mdma_free, .dma_start = stm32_mdma_start, .dma_residual = stm32_mdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_mdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -288,7 +288,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 1 - DMA1 */ { @@ -298,7 +298,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -311,7 +311,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 2 - DMA2 */ { @@ -321,7 +321,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_sdma_free, .dma_start = stm32_sdma_start, .dma_residual = stm32_sdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_sdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -334,7 +334,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* 3 - BDMA */ { @@ -344,7 +344,7 @@ struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = .dma_free = stm32_bdma_free, .dma_start = stm32_bdma_start, .dma_residual = stm32_bdma_residual, -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE .dma_capable = stm32_bdma_capable, #endif #ifdef CONFIG_DEBUG_DMA_INFO @@ -427,7 +427,7 @@ struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA */ { @@ -559,7 +559,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -627,7 +627,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -695,7 +695,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA */ { @@ -920,7 +920,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * Master DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /**************************************************************************** * Name: stm32_mdma_disable @@ -1028,7 +1028,7 @@ static size_t stm32_mdma_residual(DMA_HANDLE handle) * Name: stm32_mdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_mdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1084,13 +1084,13 @@ static void stm32_mdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ /**************************************************************************** * Standard DMA functions ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_sdma_disable @@ -1158,7 +1158,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) /* Get the stream and the controller that generated the interrupt */ -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S6) { stream = irq - STM32_IRQ_DMA1S0; @@ -1171,7 +1171,7 @@ static int stm32_sdma_interrupt(int irq, void *context, void *arg) } else #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S4) { stream = irq - STM32_IRQ_DMA2S0; @@ -1258,7 +1258,7 @@ static void stm32_sdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_sdma_capable(cfg)); #endif @@ -1530,7 +1530,7 @@ static size_t stm32_sdma_residual(DMA_HANDLE handle) * Name: stm32_sdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -1604,7 +1604,7 @@ static bool stm32_sdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -1766,13 +1766,13 @@ static void stm32_sdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_DMA1 || CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Basic DMA functions ****************************************************************************/ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /**************************************************************************** * Name: stm32_bdma_channel_disable @@ -1898,7 +1898,7 @@ static void stm32_bdma_setup(DMA_HANDLE handle, stm32_dmacfg_t *cfg) "scr: %08" PRIx32 "\n", cfg->paddr, cfg->maddr, cfg->ndata, cfg->cfg1); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(stm32_bdma_capable(cfg)); #endif @@ -2106,7 +2106,7 @@ static size_t stm32_bdma_residual(DMA_HANDLE handle) * Name: stm32_bdma_capable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) { uint32_t transfer_size; @@ -2177,7 +2177,7 @@ static bool stm32_bdma_capable(stm32_dmacfg_t *cfg) dmainfo("stm32_dmacapable: dcache unaligned " "maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n", cfg->maddr, mend); -#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED) +#if !defined(CONFIG_STM32_DMACAPABLE_ASSUME_CACHE_ALIGNED) return false; #endif } @@ -2253,7 +2253,7 @@ static void stm32_bdma_dump(DMA_HANDLE handle, const char *msg) } #endif -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ /**************************************************************************** * Name: stm32_dmamux_dump @@ -2341,30 +2341,30 @@ void weak_function arm_dma_initialize(void) #ifdef CONFIG_ARCH_IRQPRIO switch (controller) { -#if defined(CONFIG_STM32H7_DMA1) || defined(CONFIG_STM32H7_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) case DMA1: case DMA2: { up_prioritize_irq(dmachan->irq, CONFIG_DMA_PRI); break; } -#endif /* CONFIG_STM32H7_DMA1 && CONFIG_STM32H7_DMA2 */ +#endif /* CONFIG_STM32_DMA1 && CONFIG_STM32_DMA2 */ -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA case MDMA: { up_prioritize_irq(dmachan->irq, CONFIG_MDMA_PRI); break; } -#endif /* CONFIG_STM32H7_MDMA */ +#endif /* CONFIG_STM32_MDMA */ -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA case BDMA: { up_prioritize_irq(dmachan->irq, CONFIG_BDMA_PRI); break; } -#endif /* CONFIG_STM32H7_BDMA */ +#endif /* CONFIG_STM32_BDMA */ default: { @@ -2666,7 +2666,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg) { DMA_CHANNEL dmachan = (DMA_CHANNEL)handle; diff --git a/arch/arm/src/stm32h7/stm32_dma.h b/arch/arm/src/stm32h7/stm32_dma.h index d8cfdc3524e..39b440be58e 100644 --- a/arch/arm/src/stm32h7/stm32_dma.h +++ b/arch/arm/src/stm32h7/stm32_dma.h @@ -194,7 +194,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * Name: stm32_dmacapable ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(DMA_HANDLE handle, stm32_dmacfg_t *cfg); #else # define stm32_dmacapable(handle, cfg) (true) diff --git a/arch/arm/src/stm32h7/stm32_dtcm.h b/arch/arm/src/stm32h7/stm32_dtcm.h index aba82326484..c55ded32e57 100644 --- a/arch/arm/src/stm32h7/stm32_dtcm.h +++ b/arch/arm/src/stm32h7/stm32_dtcm.h @@ -50,7 +50,7 @@ * heap. */ -#ifndef CONFIG_STM32H7_DTCMEXCLUDE +#ifndef CONFIG_STM32_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32h7/stm32_dualcore.c b/arch/arm/src/stm32h7/stm32_dualcore.c index 85ab5e0ba3c..d0b3d84148f 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.c +++ b/arch/arm/src/stm32h7/stm32_dualcore.c @@ -52,7 +52,7 @@ ****************************************************************************/ #if (defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED)) || \ + defined(CONFIG_STM32_CORTEXM4_ENABLED)) || \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM4) /**************************************************************************** @@ -105,7 +105,7 @@ static void stm32_cpu2sem_wait(void) #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_cm7_take_sem @@ -134,7 +134,7 @@ static void stm32_cpu2sem_take(void) ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_start_cm4 @@ -162,7 +162,7 @@ void stm32_start_cm4(void) stm32_cpu2sem_take(); } -#ifdef CONFIG_STM32H7_CORTEXM7_BOOTM4 +#ifdef CONFIG_STM32_CORTEXM7_BOOTM4 else { /* CM4 not started at boot - force CM4 boot */ diff --git a/arch/arm/src/stm32h7/stm32_dualcore.h b/arch/arm/src/stm32h7/stm32_dualcore.h index 64f42ade6b3..9a8973b6ccb 100644 --- a/arch/arm/src/stm32h7/stm32_dualcore.h +++ b/arch/arm/src/stm32h7/stm32_dualcore.h @@ -51,7 +51,7 @@ extern "C" #endif #if defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /**************************************************************************** * Name: stm32_start_cm4 diff --git a/arch/arm/src/stm32h7/stm32_ethernet.c b/arch/arm/src/stm32h7/stm32_ethernet.c index 9cd6b485b88..abb490cf59f 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.c +++ b/arch/arm/src/stm32h7/stm32_ethernet.c @@ -69,11 +69,11 @@ #include /* STM32_NETHERNET determines the number of physical interfaces that can - * be supported by the hardware. CONFIG_STM32H7_ETHMAC will defined if + * be supported by the hardware. CONFIG_STM32_ETHMAC will defined if * any STM32H7 Ethernet support is enabled in the configuration. */ -#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H7_ETHMAC) +#if STM32_NETHERNET > 0 && defined(CONFIG_STM32_ETHMAC) /**************************************************************************** * Pre-processor Definitions @@ -162,79 +162,79 @@ # warning "No PHY specified!" #endif -#ifndef CONFIG_STM32H7_PHYADDR -# error "CONFIG_STM32H7_PHYADDR must be defined in the NuttX configuration" +#ifndef CONFIG_STM32_PHYADDR +# error "CONFIG_STM32_PHYADDR must be defined in the NuttX configuration" #endif -#if !defined(CONFIG_STM32H7_MII) && !defined(CONFIG_STM32H7_RMII) -# warning "Neither CONFIG_STM32H7_MII nor CONFIG_STM32H7_RMII defined" +#if !defined(CONFIG_STM32_MII) && !defined(CONFIG_STM32_RMII) +# warning "Neither CONFIG_STM32_MII nor CONFIG_STM32_RMII defined" #endif -#if defined(CONFIG_STM32H7_MII) && defined(CONFIG_STM32H7_RMII) -# error "Both CONFIG_STM32H7_MII and CONFIG_STM32H7_RMII defined" +#if defined(CONFIG_STM32_MII) && defined(CONFIG_STM32_RMII) +# error "Both CONFIG_STM32_MII and CONFIG_STM32_RMII defined" #endif -#ifdef CONFIG_STM32H7_MII -# if !defined(CONFIG_STM32H7_MII_MCO1) && !defined(CONFIG_STM32H7_MII_MCO2) && \ - !defined(CONFIG_STM32H7_MII_EXTCLK) -# warning "Neither CONFIG_STM32H7_MII_MCO1, CONFIG_STM32H7_MII_MCO2, nor CONFIG_STM32H7_MII_EXTCLK defined" +#ifdef CONFIG_STM32_MII +# if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && \ + !defined(CONFIG_STM32_MII_EXTCLK) +# warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_MII_MCO1) && defined(CONFIG_STM32H7_MII_MCO2) -# error "Both CONFIG_STM32H7_MII_MCO1 and CONFIG_STM32H7_MII_MCO2 defined" +# if defined(CONFIG_STM32_MII_MCO1) && defined(CONFIG_STM32_MII_MCO2) +# error "Both CONFIG_STM32_MII_MCO1 and CONFIG_STM32_MII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_RMII -# if !defined(CONFIG_STM32H7_RMII_MCO1) && !defined(CONFIG_STM32H7_RMII_MCO2) && \ - !defined(CONFIG_STM32H7_RMII_EXTCLK) -# warning "Neither CONFIG_STM32H7_RMII_MCO1, CONFIG_STM32H7_RMII_MCO2, nor CONFIG_STM32H7_RMII_EXTCLK defined" +#ifdef CONFIG_STM32_RMII +# if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && \ + !defined(CONFIG_STM32_RMII_EXTCLK) +# warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif -# if defined(CONFIG_STM32H7_RMII_MCO1) && defined(CONFIG_STM32H7_RMII_MCO2) -# error "Both CONFIG_STM32H7_RMII_MCO1 and CONFIG_STM32H7_RMII_MCO2 defined" +# if defined(CONFIG_STM32_RMII_MCO1) && defined(CONFIG_STM32_RMII_MCO2) +# error "Both CONFIG_STM32_RMII_MCO1 and CONFIG_STM32_RMII_MCO2 defined" # endif #endif -#ifdef CONFIG_STM32H7_AUTONEG -# ifndef CONFIG_STM32H7_PHYSR -# error "CONFIG_STM32H7_PHYSR must be defined in the NuttX configuration" +#ifdef CONFIG_STM32_AUTONEG +# ifndef CONFIG_STM32_PHYSR +# error "CONFIG_STM32_PHYSR must be defined in the NuttX configuration" # endif -# ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG -# ifndef CONFIG_STM32H7_PHYSR_ALTMODE -# error "CONFIG_STM32H7_PHYSR_ALTMODE must be defined in the NuttX configuration" +# ifdef CONFIG_STM32_PHYSR_ALTCONFIG +# ifndef CONFIG_STM32_PHYSR_ALTMODE +# error "CONFIG_STM32_PHYSR_ALTMODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10HD -# error "CONFIG_STM32H7_PHYSR_10HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10HD +# error "CONFIG_STM32_PHYSR_10HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100HD -# error "CONFIG_STM32H7_PHYSR_100HD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100HD +# error "CONFIG_STM32_PHYSR_100HD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_10FD -# error "CONFIG_STM32H7_PHYSR_10FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_10FD +# error "CONFIG_STM32_PHYSR_10FD must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100FD -# error "CONFIG_STM32H7_PHYSR_100FD must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100FD +# error "CONFIG_STM32_PHYSR_100FD must be defined in the NuttX configuration" # endif # else -# ifndef CONFIG_STM32H7_PHYSR_SPEED -# error "CONFIG_STM32H7_PHYSR_SPEED must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_SPEED +# error "CONFIG_STM32_PHYSR_SPEED must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_100MBPS -# error "CONFIG_STM32H7_PHYSR_100MBPS must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_100MBPS +# error "CONFIG_STM32_PHYSR_100MBPS must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_MODE -# error "CONFIG_STM32H7_PHYSR_MODE must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_MODE +# error "CONFIG_STM32_PHYSR_MODE must be defined in the NuttX configuration" # endif -# ifndef CONFIG_STM32H7_PHYSR_FULLDUPLEX -# error "CONFIG_STM32H7_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# ifndef CONFIG_STM32_PHYSR_FULLDUPLEX +# error "CONFIG_STM32_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" # endif # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP -# warning "CONFIG_STM32H7_ETH_PTP is not yet supported" +#ifdef CONFIG_STM32_ETH_PTP +# warning "CONFIG_STM32_ETH_PTP is not yet supported" #endif -#undef CONFIG_STM32H7_ETH_HWCHECKSUM +#undef CONFIG_STM32_ETH_HWCHECKSUM /* Add 4 to the configured buffer size to account for the 2 byte checksum * memory needed at the end of the maximum size packet. Buffer sizes must @@ -262,16 +262,16 @@ # warning "You are using an incomplete/untested configuration" #endif -#ifndef CONFIG_STM32H7_ETH_NRXDESC -# define CONFIG_STM32H7_ETH_NRXDESC 8 +#ifndef CONFIG_STM32_ETH_NRXDESC +# define CONFIG_STM32_ETH_NRXDESC 8 #endif -#ifndef CONFIG_STM32H7_ETH_NTXDESC -# define CONFIG_STM32H7_ETH_NTXDESC 4 +#ifndef CONFIG_STM32_ETH_NTXDESC +# define CONFIG_STM32_ETH_NTXDESC 4 #endif /* We need at least one more free buffer than transmit buffers */ -#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32H7_ETH_NTXDESC+1) +#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1) /* Buffers used for DMA access must begin on an address aligned with the * D-Cache line and must be an even multiple of the D-Cache line size. @@ -289,10 +289,10 @@ #define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE) #define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE) -#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NRXDESC) -#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H7_ETH_NTXDESC) +#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NRXDESC) +#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32_ETH_NTXDESC) -#define RXBUFFER_SIZE (CONFIG_STM32H7_ETH_NRXDESC * ALIGNED_BUFSIZE) +#define RXBUFFER_SIZE (CONFIG_STM32_ETH_NRXDESC * ALIGNED_BUFSIZE) #define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE) #define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE) @@ -303,7 +303,7 @@ */ #ifndef CONFIG_DEBUG_NET_INFO -# undef CONFIG_STM32H7_ETHMAC_REGDEBUG +# undef CONFIG_STM32_ETHMAC_REGDEBUG #endif /* Clocking *****************************************************************/ @@ -394,7 +394,7 @@ * ETH_MACCR_ACS Automatic pad/CRC stripping 0 (disabled) * ETH_MACCR_DR Retry disable 1 (disabled) * ETH_MACCR_IPC IPv4 checksum offload - * Depends on CONFIG_STM32H7_ETH_HWCHECKSUM + * Depends on CONFIG_STM32_ETH_HWCHECKSUM * ETH_MACCR_LM Loopback mode 0 (disabled) * ETH_MACCR_DO Receive own disable 0 (enabled) * ETH_MACCR_DCRS Carrier sense disable 0 (enabled) @@ -409,7 +409,7 @@ * ETH_MACCR_FES Fast Ethernet speed Depends on priv->mbps100 */ -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM # define MACCR_SET_BITS \ (ETH_MACCR_BL_10 | ETH_MACCR_DR | ETH_MACCR_IPC | ETH_MACCR_IPG(96)) #else @@ -558,10 +558,10 @@ #define MTLRXQOMR_SET_MASK \ ((0x7 << ETH_MTLRXQOMR_RQS_SHIFT) | ETH_MTLRXQOMR_RTC_64) -#ifdef CONFIG_STM32H7_ETH_HWCHECKSUM +#ifdef CONFIG_STM32_ETH_HWCHECKSUM /* TODO */ -# error CONFIG_STM32H7_ETH_HWCHECKSUM not supported +# error CONFIG_STM32_ETH_HWCHECKSUM not supported #endif /* Clear the DMAMR bits that will be setup during MAC initialization (or that @@ -731,7 +731,7 @@ static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET]; /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); @@ -803,7 +803,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, union stm32_desc_u *rxtable, uint8_t *rxbuffer); /* PHY Initialization */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int stm32_phyintenable(struct stm32_ethmac_s *priv); #endif @@ -812,17 +812,17 @@ static int stm32_phyintenable(struct stm32_ethmac_s *priv); static inline int stm32_dm9161(struct stm32_ethmac_s *priv); #endif static int stm32_phyinit(struct stm32_ethmac_s *priv); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv); #endif #endif /* MAC/DMA Initialization */ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void); #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void); #endif static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv); @@ -852,7 +852,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -924,7 +924,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -951,7 +951,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_checksetup(void) { } @@ -1093,10 +1093,10 @@ static struct eth_desc_s *stm32_get_next_txdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]; union stm32_desc_u *last = - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC + - CONFIG_STM32H7_ETH_NTXDESC - 1]; + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC + + CONFIG_STM32_ETH_NTXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1313,7 +1313,7 @@ static int stm32_transmit(struct stm32_ethmac_s *priv) * stoppable transmit events. */ - if (priv->inflight >= CONFIG_STM32H7_ETH_NTXDESC) + if (priv->inflight >= CONFIG_STM32_ETH_NTXDESC) { stm32_disableint(priv, ETH_DMACIER_RIE); } @@ -1379,7 +1379,7 @@ static int stm32_txpoll(struct net_driver_s *dev) * In a race condition, ETH_TDES3_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (tdes2) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) != 0 || @@ -1452,7 +1452,7 @@ static void stm32_dopoll(struct stm32_ethmac_s *priv) * In a race condition, ETH_TDES3_RD_OWN may be cleared BUT still * not available because stm32_freeframe() has not yet run. If * stm32_freeframe() has run, the buffer1 pointer (des0) will be - * nullified (and inflight should be < CONFIG_STM32H7_ETH_NTXDESC). + * nullified (and inflight should be < CONFIG_STM32_ETH_NTXDESC). */ if ((priv->txhead->des3 & ETH_TDES3_RD_OWN) == 0 && @@ -1578,10 +1578,10 @@ static struct eth_desc_s *stm32_get_next_rxdesc(struct stm32_ethmac_s *priv, struct eth_desc_s * curr) { union stm32_desc_u *first = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC]; union stm32_desc_u *last = - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC + - CONFIG_STM32H7_ETH_NRXDESC - 1]; + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC + + CONFIG_STM32_ETH_NRXDESC - 1]; union stm32_desc_u *next = ((union stm32_desc_u *)curr) + 1; if (next > last) @@ -1732,8 +1732,8 @@ static int stm32_recvframe(struct stm32_ethmac_s *priv) for (i = 0; (rxdesc->des3 & ETH_RDES3_WB_OWN) == 0 && - i < CONFIG_STM32H7_ETH_NRXDESC && - priv->inflight < CONFIG_STM32H7_ETH_NTXDESC; + i < CONFIG_STM32_ETH_NRXDESC && + priv->inflight < CONFIG_STM32_ETH_NTXDESC; i++) { /* Check if this is a normal descriptor */ @@ -2831,7 +2831,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, /* Initialize each TX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NTXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NTXDESC; i++) { txdesc = &txtable[i].desc; @@ -2867,7 +2867,7 @@ static void stm32_txdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCATXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); + stm32_putreg(CONFIG_STM32_ETH_NTXDESC - 1, STM32_ETH_DMACTXRLR); /* Set Transmit Descriptor List Address Register */ @@ -2920,7 +2920,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Initialize each RX descriptor */ - for (i = 0; i < CONFIG_STM32H7_ETH_NRXDESC; i++) + for (i = 0; i < CONFIG_STM32_ETH_NRXDESC; i++) { rxdesc = &rxtable[i].desc; @@ -2953,7 +2953,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, * properly but the DMACCARXDR advances to outside the descriptor ring */ - stm32_putreg(CONFIG_STM32H7_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); + stm32_putreg(CONFIG_STM32_ETH_NRXDESC - 1, STM32_ETH_DMACRXRLR); /* Set Receive Descriptor List Address Register */ @@ -2961,7 +2961,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, /* Set Receive Descriptor Tail pointer Address */ - stm32_putreg((uint32_t)&rxtable[CONFIG_STM32H7_ETH_NRXDESC - 1].desc, + stm32_putreg((uint32_t)&rxtable[CONFIG_STM32_ETH_NRXDESC - 1].desc, STM32_ETH_DMACRXDTPR); } @@ -2997,7 +2997,7 @@ static void stm32_rxdescinit(struct stm32_ethmac_s *priv, #ifdef CONFIG_NETDEV_PHY_IOCTL static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY #ifdef CONFIG_ARCH_PHY_INTERRUPT struct stm32_ethmac_s *priv = (struct stm32_ethmac_s *)dev->d_private; #endif @@ -3027,7 +3027,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) { struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); - req->phy_id = CONFIG_STM32H7_PHYADDR; + req->phy_id = CONFIG_STM32_PHYADDR; ret = OK; } break; @@ -3062,7 +3062,7 @@ static int stm32_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) } #endif /* CONFIG_NETDEV_PHY_IOCTL */ -#ifndef CONFIG_STM32H7_NO_PHY +#ifndef CONFIG_STM32_NO_PHY /**************************************************************************** * Function: stm32_phyintenable * @@ -3119,7 +3119,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY ID1: %d\n", ret); @@ -3142,7 +3142,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, 16, &phyval); + CONFIG_STM32_PHYADDR, 16, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY Register 0x10: %d\n", ret); @@ -3176,7 +3176,7 @@ static inline int stm32_dm9161(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static void stm32_phyregdump(struct stm32_ethmac_s *priv) { uint16_t phyval; @@ -3186,7 +3186,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) for (i = 0; i < 0x20; i++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, i, &phyval); + CONFIG_STM32_PHYADDR, i, &phyval); if (ret < 0) { nerr("ERROR: Failed to read reg: 0%2x\n", i); @@ -3217,7 +3217,7 @@ static void stm32_phyregdump(struct stm32_ethmac_s *priv) static int stm32_phyinit(struct stm32_ethmac_s *priv) { -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG volatile uint32_t timeout; #endif uint32_t regval; @@ -3240,7 +3240,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Put the PHY in reset mode */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_RESET); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_RESET); if (ret < 0) { nerr("ERROR: Failed to reset the PHY: %d\n", ret); @@ -3254,7 +3254,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) to -= 10; phyval = 0xffff; ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, &phyval); + CONFIG_STM32_PHYADDR, MII_MCR, &phyval); ninfo("MII_MCR: phyval: %u ret: %d\n", phyval, ret); } @@ -3271,7 +3271,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) } ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID1, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID1, &phyval); if (ret < 0) { @@ -3289,7 +3289,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("MII_PHYID1: phyval: %u ret: %d\n", phyval, ret); ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_PHYID2, &phyval); + CONFIG_STM32_PHYADDR, MII_PHYID2, &phyval); if (ret < 0) { @@ -3306,7 +3306,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) ninfo("MII_PHYID2: phyval: %u ret: %d\n", phyval, ret); -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG stm32_phyregdump(priv); #endif @@ -3322,13 +3322,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Perform auto-negotiation if so configured */ -#ifdef CONFIG_STM32H7_AUTONEG +#ifdef CONFIG_STM32_AUTONEG /* Wait for link status */ for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3352,7 +3352,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Enable auto-negotiation */ ret = mdio_write(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MCR, MII_MCR_ANENABLE); + CONFIG_STM32_PHYADDR, MII_MCR, MII_MCR_ANENABLE); if (ret < 0) { nerr("ERROR: Failed to enable auto-negotiation: %d\n", ret); @@ -3364,7 +3364,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) for (timeout = 0; timeout < PHY_RETRY_TIMEOUT; timeout++) { ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, MII_MSR, &phyval); + CONFIG_STM32_PHYADDR, MII_MSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read the PHY MSR: %d\n", ret); @@ -3387,7 +3387,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Read the result of the auto-negotiation from the PHY-specific register */ ret = mdio_read(priv->mdio, - CONFIG_STM32H7_PHYADDR, CONFIG_STM32H7_PHYSR, &phyval); + CONFIG_STM32_PHYADDR, CONFIG_STM32_PHYSR, &phyval); if (ret < 0) { nerr("ERROR: Failed to read PHY status register\n"); @@ -3396,38 +3396,38 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ - ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32H7_PHYSR, phyval); + ninfo("PHYSR[%d]: %04x\n", CONFIG_STM32_PHYSR, phyval); /* Different PHYs present speed and mode information in different ways. IF - * This CONFIG_STM32H7_PHYSR_ALTCONFIG is selected, this indicates that + * This CONFIG_STM32_PHYSR_ALTCONFIG is selected, this indicates that * the PHY represents speed and mode information are combined, for * example, with separate bits for 10HD, 100HD, 10FD and 100FD. */ -#ifdef CONFIG_STM32H7_PHYSR_ALTCONFIG - switch (phyval & CONFIG_STM32H7_PHYSR_ALTMODE) +#ifdef CONFIG_STM32_PHYSR_ALTCONFIG + switch (phyval & CONFIG_STM32_PHYSR_ALTMODE) { default: nerr("ERROR: Unrecognized PHY status setting\n"); /* Falls through */ - case CONFIG_STM32H7_PHYSR_10HD: + case CONFIG_STM32_PHYSR_10HD: priv->fduplex = 0; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100HD: + case CONFIG_STM32_PHYSR_100HD: priv->fduplex = 0; priv->mbps100 = 1; break; - case CONFIG_STM32H7_PHYSR_10FD: + case CONFIG_STM32_PHYSR_10FD: priv->fduplex = 1; priv->mbps100 = 0; break; - case CONFIG_STM32H7_PHYSR_100FD: + case CONFIG_STM32_PHYSR_100FD: priv->fduplex = 1; priv->mbps100 = 1; break; @@ -3440,13 +3440,13 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) */ #else - if ((phyval & CONFIG_STM32H7_PHYSR_MODE) == - CONFIG_STM32H7_PHYSR_FULLDUPLEX) + if ((phyval & CONFIG_STM32_PHYSR_MODE) == + CONFIG_STM32_PHYSR_FULLDUPLEX) { priv->fduplex = 1; } - if ((phyval & CONFIG_STM32H7_PHYSR_SPEED) == CONFIG_STM32H7_PHYSR_100MBPS) + if ((phyval & CONFIG_STM32_PHYSR_SPEED) == CONFIG_STM32_PHYSR_100MBPS) { priv->mbps100 = 1; } @@ -3455,14 +3455,14 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) #else /* Auto-negotiation not selected */ phyval = 0; -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD phyval |= MII_MCR_FULLDPLX; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS phyval |= MII_MCR_SPEED100; #endif - ret = stm32_phywrite(CONFIG_STM32H7_PHYADDR, MII_MCR, phyval, 0xffff); + ret = stm32_phywrite(CONFIG_STM32_PHYADDR, MII_MCR, phyval, 0xffff); if (ret < 0) { nerr("ERROR: Failed to write the PHY MCR: %d\n", ret); @@ -3473,10 +3473,10 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) /* Remember the selected speed and duplex modes */ -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #endif #endif @@ -3504,7 +3504,7 @@ static int stm32_phyinit(struct stm32_ethmac_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_MII +#ifdef CONFIG_STM32_MII static inline void stm32_selectmii(void) { uint32_t regval; @@ -3530,7 +3530,7 @@ static inline void stm32_selectmii(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII static inline void stm32_selectrmii(void) { uint32_t regval; @@ -3562,17 +3562,17 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) { /* Configure GPIO pins to support Ethernet */ -#if defined(CONFIG_STM32H7_MII) || defined(CONFIG_STM32H7_RMII) +#if defined(CONFIG_STM32_MII) || defined(CONFIG_STM32_RMII) /* MDC and MDIO are common to both modes */ -# ifndef CONFIG_STM32H7_NO_PHY +# ifndef CONFIG_STM32_NO_PHY stm32_configgpio(GPIO_ETH_MDC); stm32_configgpio(GPIO_ETH_MDIO); # endif /* Set up the MII interface */ -# if defined(CONFIG_STM32H7_MII) +# if defined(CONFIG_STM32_MII) /* Select the MII interface */ @@ -3587,7 +3587,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_MII_MCO1) +# if defined(CONFIG_STM32_MII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3595,7 +3595,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO2) +# elif defined(CONFIG_STM32_MII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3603,7 +3603,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_MII_MCO) +# elif defined(CONFIG_STM32_MII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3634,7 +3634,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) /* Set up the RMII interface. */ -# elif defined(CONFIG_STM32H7_RMII) +# elif defined(CONFIG_STM32_RMII) /* Select the RMII interface */ @@ -3649,7 +3649,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) * PLLI2S clock (through a configurable prescaler) on PC9 pin." */ -# if defined(CONFIG_STM32H7_RMII_MCO1) +# if defined(CONFIG_STM32_RMII_MCO1) /* Configure MC01 to drive the PHY. Board logic must provide MC01 clocking * info. */ @@ -3657,7 +3657,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO1); stm32_mco1config(BOARD_CFGR_MC01_SOURCE, BOARD_CFGR_MC01_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO2) +# elif defined(CONFIG_STM32_RMII_MCO2) /* Configure MC02 to drive the PHY. Board logic must provide MC02 clocking * info. */ @@ -3665,7 +3665,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) stm32_configgpio(GPIO_MCO2); stm32_mco2config(BOARD_CFGR_MC02_SOURCE, BOARD_CFGR_MC02_DIVIDER); -# elif defined(CONFIG_STM32H7_RMII_MCO) +# elif defined(CONFIG_STM32_RMII_MCO) /* Setup MCO pin for alternative usage */ stm32_configgpio(GPIO_MCO); @@ -3688,7 +3688,7 @@ static inline void stm32_ethgpioconfig(struct stm32_ethmac_s *priv) # endif #endif -#ifdef CONFIG_STM32H7_ETH_PTP +#ifdef CONFIG_STM32_ETH_PTP /* Enable pulse-per-second (PPS) output signal */ stm32_configgpio(GPIO_ETH_PPS_OUT); @@ -4027,7 +4027,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) * sequence in stm32_rcc.c. */ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4050,24 +4050,24 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv) /* Initialize TX Descriptors list */ stm32_txdescinit(priv, - &g_txtable[priv->intf * CONFIG_STM32H7_ETH_NTXDESC]); + &g_txtable[priv->intf * CONFIG_STM32_ETH_NTXDESC]); /* Initialize RX Descriptors list */ stm32_rxdescinit(priv, - &g_rxtable[priv->intf * CONFIG_STM32H7_ETH_NRXDESC], + &g_rxtable[priv->intf * CONFIG_STM32_ETH_NRXDESC], &g_rxbuffer[priv->intf * RXBUFFER_SIZE]); /* Initialize the PHY */ -#ifdef CONFIG_STM32H7_NO_PHY +#ifdef CONFIG_STM32_NO_PHY ninfo("MAC without PHY\n"); -#ifdef CONFIG_STM32H7_ETHFD +#ifdef CONFIG_STM32_ETHFD priv->fduplex = 1; #else priv->fduplex = 0; #endif -#ifdef CONFIG_STM32H7_ETH100MBPS +#ifdef CONFIG_STM32_ETH100MBPS priv->mbps100 = 1; #else priv->mbps100 = 0; @@ -4190,7 +4190,7 @@ static inline int stm32_ethinitialize(int intf) return -EAGAIN; } -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT /* Perform any necessary, board-specific PHY initialization */ ret = stm32_phy_boardinitialize(0); @@ -4238,4 +4238,4 @@ void arm_netinitialize(void) } #endif -#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H7_ETHMAC */ +#endif /* STM32_NETHERNET > 0 && CONFIG_STM32_ETHMAC */ diff --git a/arch/arm/src/stm32h7/stm32_ethernet.h b/arch/arm/src/stm32h7/stm32_ethernet.h index 8faf17694ca..347beebab66 100644 --- a/arch/arm/src/stm32h7/stm32_ethernet.h +++ b/arch/arm/src/stm32h7/stm32_ethernet.h @@ -77,7 +77,7 @@ int stm32_ethinitialize(int intf); * Description: * Some boards require specialized initialization of the PHY before it can * be used. This may include such things as configuring GPIOs, resetting - * the PHY, etc. If CONFIG_STM32H7_PHYINIT is defined in the configuration + * the PHY, etc. If CONFIG_STM32_PHYINIT is defined in the configuration * then the board specific logic must provide stm32_phyinitialize(); The * STM32 Ethernet driver will call this function one time before it first * uses the PHY. @@ -92,7 +92,7 @@ int stm32_ethinitialize(int intf); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_PHYINIT +#ifdef CONFIG_STM32_PHYINIT int stm32_phy_boardinitialize(int intf); #endif diff --git a/arch/arm/src/stm32h7/stm32_exti_gpio.c b/arch/arm/src/stm32h7/stm32_exti_gpio.c index 4b27006a665..74c8e812fc4 100644 --- a/arch/arm/src/stm32h7/stm32_exti_gpio.c +++ b/arch/arm/src/stm32h7/stm32_exti_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Types @@ -378,4 +378,4 @@ int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, return OK; } -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index 459f0204a8b..15eecf55a7e 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -90,9 +90,9 @@ * critical Rx/Tx transactions on the CAN bus. */ -# if defined(CONFIG_STM32H7_FDCAN_HPWORK) +# if defined(CONFIG_STM32_FDCAN_HPWORK) # define CANWORK HPWORK -# elif defined(CONFIG_STM32H7_FDCAN_LPWORK) +# elif defined(CONFIG_STM32_FDCAN_LPWORK) # define CANWORK LPWORK # else # define CANWORK LPWORK @@ -326,7 +326,7 @@ struct fdcan_message_ram /* FDCAN device structures **************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static const struct fdcan_config_s stm32_fdcan0_config = { .tx_pin = GPIO_CAN1_TX, @@ -339,7 +339,7 @@ static const struct fdcan_config_s stm32_fdcan0_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static const struct fdcan_config_s stm32_fdcan1_config = { .tx_pin = GPIO_CAN2_TX, @@ -352,7 +352,7 @@ static const struct fdcan_config_s stm32_fdcan1_config = }; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static const struct fdcan_config_s stm32_fdcan2_config = { .tx_pin = GPIO_CAN3_TX, @@ -411,15 +411,15 @@ struct fdcan_driver_s * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 static struct fdcan_driver_s g_fdcan0; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 static struct fdcan_driver_s g_fdcan1; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 static struct fdcan_driver_s g_fdcan2; #endif @@ -437,7 +437,7 @@ static int fdcan_txpoll(struct net_driver_s *dev); /* Helper functions */ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv); #endif @@ -511,7 +511,7 @@ static void fdcan_errint(struct fdcan_driver_s *priv, bool enable); * Dump common register values to the console for debugging purposes. ****************************************************************************/ -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG static void fdcan_dumpregs(struct fdcan_driver_s *priv) { printf("-------------- FDCAN Reg Dump ----------------\n"); @@ -685,7 +685,7 @@ int32_t fdcan_bittiming(struct fdcan_bitseg *timing) return 3; /* Solution not found */ } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] CLK_FREQ %lu, target_bitrate %lu, prescaler %lu, bs1 %d" ", bs2 %d\n", CLK_FREQ, target_bitrate, prescaler_bs, bs1 - 1, bs2 - 1); @@ -1803,7 +1803,7 @@ static int fdcan_ifup(struct net_driver_s *dev) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2092,7 +2092,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG const struct fdcan_bitseg *tim = &priv->arbi_timing; ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2116,7 +2116,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) return -EIO; } -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG tim = &priv->data_timing; ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); @@ -2136,14 +2136,14 @@ int fdcan_initialize(struct fdcan_driver_s *priv) /* Operation Configuration */ -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK +#ifdef CONFIG_STM32_FDCAN_LOOPBACK /* Enable External Loopback Mode (Rx pin disconnected) (RM0433 pg 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_TEST); modifyreg32(priv->base + STM32_FDCAN_TEST_OFFSET, 0, FDCAN_TEST_LBCK); #endif -#ifdef CONFIG_STM32H7_FDCAN_LOOPBACK_INTERNAL +#ifdef CONFIG_STM32_FDCAN_LOOPBACK_INTERNAL /* Enable Bus Monitoring / Restricted Op Mode (RM0433 pg 2492, 2494) */ modifyreg32(priv->base + STM32_FDCAN_CCCR_OFFSET, 0, FDCAN_CCCR_MON); @@ -2331,7 +2331,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) regval &= ~FDCAN_GFC_ANFE; /* Accept non-matching extid frames into FIFO0 */ putreg32(regval, priv->base + STM32_FDCAN_GFC_OFFSET); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2339,7 +2339,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) fdcan_setinit(priv->base, 0); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2395,7 +2395,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_RX_FIFO0; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB RX %i %p\r\n", i, &priv->rx[i]); #endif priv->rx[i].header.w1 = 0x0; @@ -2411,7 +2411,7 @@ static void fdcan_reset(struct fdcan_driver_s *priv) { for (uint32_t i = 0; i < NUM_TX_FIFO; i++) { - #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG + #ifdef CONFIG_STM32_FDCAN_REGDEBUG ninfo("[fdcan] MB TX %i %p\r\n", i, &priv->tx[i]); #endif priv->tx[i].header.w1 = 0x0; @@ -2458,7 +2458,7 @@ int stm32_fdcansockinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 case 0: priv = &g_fdcan0; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2477,7 +2477,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 case 1: priv = &g_fdcan1; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2496,7 +2496,7 @@ int stm32_fdcansockinitialize(int intf) break; #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 case 2: priv = &g_fdcan2; memset(priv, 0, sizeof(struct fdcan_driver_s)); @@ -2579,7 +2579,7 @@ int stm32_fdcansockinitialize(int intf) netdev_register(&priv->dev, NET_LL_CAN); -#ifdef CONFIG_STM32H7_FDCAN_REGDEBUG +#ifdef CONFIG_STM32_FDCAN_REGDEBUG fdcan_dumpregs(priv); #endif @@ -2600,15 +2600,15 @@ int stm32_fdcansockinitialize(int intf) #if !defined(CONFIG_NETDEV_LATEINIT) void arm_netinitialize(void) { -#ifdef CONFIG_STM32H7_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); #endif -#ifdef CONFIG_STM32H7_FDCAN2 +#ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); #endif -#ifdef CONFIG_STM32H7_FDCAN3 +#ifdef CONFIG_STM32_FDCAN3 stm32_fdcansockinitialize(2); #endif } diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.h b/arch/arm/src/stm32h7/stm32_fdcan_sock.h index 0c92ea109ae..f5f66c31090 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.h +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.h @@ -31,7 +31,7 @@ #include "hardware/stm32_fdcan.h" -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /**************************************************************************** * Pre-processor Definitions @@ -105,5 +105,5 @@ int stm32_fdcansockinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_FDCAN */ +#endif /* CONFIG_STM32_FDCAN */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_FDCAN_SOCK_H */ diff --git a/arch/arm/src/stm32h7/stm32_flash.c b/arch/arm/src/stm32h7/stm32_flash.c index 3a963bbc22b..c9afb10a362 100644 --- a/arch/arm/src/stm32h7/stm32_flash.c +++ b/arch/arm/src/stm32h7/stm32_flash.c @@ -26,15 +26,15 @@ #include -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7b3xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h743xx_flash.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h743xx_flash.c" #else # error "Unsupported STM32 H7 chip" diff --git a/arch/arm/src/stm32h7/stm32_fmc.c b/arch/arm/src/stm32h7/stm32_fmc.c index 841f2e64525..1b790354b18 100644 --- a/arch/arm/src/stm32h7/stm32_fmc.c +++ b/arch/arm/src/stm32h7/stm32_fmc.c @@ -26,7 +26,7 @@ #include -#if defined(CONFIG_STM32H7_FMC) +#if defined(CONFIG_STM32_FMC) #include "stm32.h" @@ -41,7 +41,7 @@ /**************************************************************************** * To use FMC, you must first enable it in configuration: * - * CONFIG_STM32H7_FMC=y + * CONFIG_STM32_FMC=y * * FMC is statically configured at startup. Its configuration is adjusted * using BOARD_XXX macros described below, which should be declared @@ -549,4 +549,4 @@ void stm32_fmc_sdram_command(uint32_t cmd) putreg32(cmd, STM32_FMC_SDCMR); } -#endif /* CONFIG_STM32H7_FMC */ +#endif /* CONFIG_STM32_FMC */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.c b/arch/arm/src/stm32h7/stm32_gpio.c index 8723b1d4b5f..77bcccbc4ea 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.c +++ b/arch/arm/src/stm32h7/stm32_gpio.c @@ -44,11 +44,11 @@ * families */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) || \ - defined(CONFIG_STM32H7_STM32H7X3XX) || \ - defined(CONFIG_STM32H7_STM32H7B3XX) || \ - defined(CONFIG_STM32H7_STM32H7X5XX) || \ - defined(CONFIG_STM32H7_STM32H7X7XX) +#if defined(CONFIG_STM32_STM32H7X0XX) || \ + defined(CONFIG_STM32_STM32H7X3XX) || \ + defined(CONFIG_STM32_STM32H7B3XX) || \ + defined(CONFIG_STM32_STM32H7X5XX) || \ + defined(CONFIG_STM32_STM32H7X7XX) /**************************************************************************** * Private Data @@ -80,14 +80,14 @@ const uint32_t g_gpiobase[STM32_NGPIO] = STM32_GPIOE_BASE, #endif #if STM32_NGPIO > 5 -# if defined(CONFIG_STM32H7_HAVE_GPIOF) +# if defined(CONFIG_STM32_HAVE_GPIOF) STM32_GPIOF_BASE, # else 0, # endif #endif #if STM32_NGPIO > 6 -# if defined(CONFIG_STM32H7_HAVE_GPIOG) +# if defined(CONFIG_STM32_HAVE_GPIOG) STM32_GPIOG_BASE, # else 0, @@ -526,7 +526,7 @@ bool stm32_gpioread(uint32_t pinset) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void) { /* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit @@ -543,4 +543,4 @@ void stm32_iocompensation(void) } #endif -#endif /* CONFIG_STM32H7_STM32H7X3XX || CONFIG_STM32H7_STM32H7X7XX || CONFIG_STM32H7_STM32H7B3XX */ +#endif /* CONFIG_STM32_STM32H7X3XX || CONFIG_STM32_STM32H7X7XX || CONFIG_STM32_STM32H7B3XX */ diff --git a/arch/arm/src/stm32h7/stm32_gpio.h b/arch/arm/src/stm32h7/stm32_gpio.h index ab46e15a402..18ce28cc321 100644 --- a/arch/arm/src/stm32h7/stm32_gpio.h +++ b/arch/arm/src/stm32h7/stm32_gpio.h @@ -199,10 +199,10 @@ #if STM32_NGPIO > 4 # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) # define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */ #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) # define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */ #endif #if STM32_NGPIO > 7 @@ -350,7 +350,7 @@ bool stm32_gpioread(uint32_t pinset); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION void stm32_iocompensation(void); #endif diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 9b7cdc9df2f..e01dd136a21 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -156,28 +156,28 @@ * * One of: * - * CONFIG_STM32H7_STM32H7X3XX + * CONFIG_STM32_STM32H7X3XX * * and one or more interfaces: * - * CONFIG_STM32H7_I2C1 - * CONFIG_STM32H7_I2C2 - * CONFIG_STM32H7_I2C3 - * CONFIG_STM32H7_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32H7_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32H7_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32H7_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32H7_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32H7_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in msec) * * Debugging output enabled with: @@ -225,8 +225,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) || defined(CONFIG_STM32H7_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -234,14 +234,14 @@ #undef INVALID_CLOCK_SOURCE -#if defined(CONFIG_STM32H7_I2C1) || defined(CONFIG_STM32H7_I2C2) || \ - defined(CONFIG_STM32H7_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) # if STM32_RCC_D2CCIP2R_I2C123SRC != RCC_D2CCIP2R_I2C123SEL_HSI # warning "Clock Source STM32_RCC_D2CCIP2R_I2C123SRC must be HSI" # define INVALID_CLOCK_SOURCE # endif #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 # if STM32_RCC_D3CCIPR_I2C4SRC != RCC_D3CCIPR_I2C4SEL_HSI # warning "Clock Source STM32_RCC_D3CCIPR_I2C4SRC must be HSI" # define INVALID_CLOCK_SOURCE @@ -258,25 +258,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32H7_I2CTIMEOSEC) && !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 -# define CONFIG_STM32H7_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32H7_I2CTIMEOSEC) -# define CONFIG_STM32H7_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32H7_I2CTIMEOMS) -# define CONFIG_STM32H7_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32H7_I2CTIMEOTICKS -# define CONFIG_STM32H7_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32H7_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32H7_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32H7_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -446,9 +446,9 @@ static inline void stm32_i2c_putreg32(struct stm32_i2c_priv_s *priv, static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32H7_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv); #ifdef CONFIG_I2C_TRACE @@ -488,7 +488,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -524,7 +524,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -560,7 +560,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -596,7 +596,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -726,7 +726,7 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -743,7 +743,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -799,12 +799,12 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32H7_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -842,10 +842,10 @@ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -983,10 +983,10 @@ static inline void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32H7_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32H7_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2715,22 +2715,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -2816,5 +2816,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32H7_I2C1 || CONFIG_STM32H7_I2C2 || \ - * CONFIG_STM32H7_I2C3 || CONFIG_STM32H7_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || \ + * CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32h7/stm32_i2c.h b/arch/arm/src/stm32h7/stm32_i2c.h index ae507efe603..78dc96b1ba5 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.h +++ b/arch/arm/src/stm32h7/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32H7_I2C_DYNTIMEO -# if CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32H7_I2C_DYNTIMEO because of CONFIG_STM32H7_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32H7_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32h7/stm32_iwdg.c b/arch/arm/src/stm32h7/stm32_iwdg.c index 13150c39431..39212b5a753 100644 --- a/arch/arm/src/stm32h7/stm32_iwdg.c +++ b/arch/arm/src/stm32h7/stm32_iwdg.c @@ -41,7 +41,7 @@ #include "stm32_rcc.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -681,9 +681,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB4_FZ1); cr |= DBGMCU_APB4_WDGLSD1; @@ -692,4 +692,4 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32h7/stm32_lptim.c b/arch/arm/src/stm32h7/stm32_lptim.c index daa7bc8029f..958243f7631 100644 --- a/arch/arm/src/stm32h7/stm32_lptim.c +++ b/arch/arm/src/stm32h7/stm32_lptim.c @@ -43,9 +43,9 @@ #include "stm32_gpio.h" #include "stm32_lptim.h" -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) || \ - defined(CONFIG_STM32H7_LPTIM3) || defined(CONFIG_STM32H7_LPTIM4) || \ - defined(CONFIG_STM32H7_LPTIM5) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) || \ + defined(CONFIG_STM32_LPTIM3) || defined(CONFIG_STM32_LPTIM4) || \ + defined(CONFIG_STM32_LPTIM5) /**************************************************************************** * Private Function prototypes @@ -103,35 +103,35 @@ static const struct stm32_lptim_ops_s stm32_lptim_ops = .ackint = &stm32_lptim_ackint }; -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 struct stm32_lptim_dev_s stm32_lptim1_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 struct stm32_lptim_dev_s stm32_lptim2_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM2_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 struct stm32_lptim_dev_s stm32_lptim3_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM3_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 struct stm32_lptim_dev_s stm32_lptim4_priv = { .ops = &stm32_lptim_ops, .base = STM32_LPTIM4_BASE, }; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 struct stm32_lptim_dev_s stm32_lptim5_priv = { .ops = &stm32_lptim_ops, @@ -205,7 +205,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, { switch (dev->base) { -#if defined(CONFIG_STM32H7_LPTIM1) || defined(CONFIG_STM32H7_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM1_BASE: case STM32_LPTIM2_BASE: if (input == 0) @@ -221,7 +221,7 @@ static int stm32_lptim_setinput(struct stm32_lptim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(dev->base + STM32_LPTIM_CFGR2_OFFSET, LPTIM_CFGR2_IN1SEL_MASK, mux); @@ -301,27 +301,27 @@ static int stm32_lptim_setisr(struct stm32_lptim_dev_s *dev, switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: vectorno = STM32_IRQ_LPTIM1; break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: vectorno = STM32_IRQ_LPTIM2; break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: vectorno = STM32_IRQ_LPTIM3; break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: vectorno = STM32_IRQ_LPTIM4; break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: vectorno = STM32_IRQ_LPTIM5; break; @@ -391,31 +391,31 @@ struct stm32_lptim_dev_s *stm32_lptim_init(int lptimer) switch (lptimer) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case 1: dev = &stm32_lptim1_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_LPTIM1EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case 2: dev = &stm32_lptim2_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM2EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case 3: dev = &stm32_lptim3_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM3EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case 4: dev = &stm32_lptim4_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM4EN); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case 5: dev = &stm32_lptim5_priv; modifyreg32(STM32_RCC_APB4ENR, 0, RCC_APB4ENR_LPTIM5EN); @@ -436,27 +436,27 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) switch (dev->base) { -#ifdef CONFIG_STM32H7_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1LLPENR, RCC_APB1LENR_LPTIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 case STM32_LPTIM3_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 case STM32_LPTIM4_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_LPTIM5 +#ifdef CONFIG_STM32_LPTIM5 case STM32_LPTIM5_BASE: modifyreg32(STM32_RCC_APB4LPENR, RCC_APB4ENR_LPTIM5EN, 0); break; @@ -468,4 +468,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_LPTIM1 || ... || CONFIG_STM32H7_LPTIM5) */ +#endif /* defined(CONFIG_STM32_LPTIM1 || ... || CONFIG_STM32_LPTIM5) */ diff --git a/arch/arm/src/stm32h7/stm32_lse.c b/arch/arm/src/stm32h7/stm32_lse.c index e55b9936798..0fdfaf611c7 100644 --- a/arch/arm/src/stm32h7/stm32_lse.c +++ b/arch/arm/src/stm32h7/stm32_lse.c @@ -42,16 +42,16 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -96,7 +96,7 @@ void stm32_rcc_enablelse(void) { uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif const uint32_t *drives = drives_rev_y; @@ -131,18 +131,18 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. With the * enable off */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -170,7 +170,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -179,13 +179,13 @@ void stm32_rcc_enablelse(void) while (drive < sizeof(drives_rev_y) / sizeof(drives_rev_y[0])); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= drives[CONFIG_STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; + regval |= drives[CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY]; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32h7/stm32_ltdc.c b/arch/arm/src/stm32h7/stm32_ltdc.c index 79f6ac0f0de..c946c889300 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.c +++ b/arch/arm/src/stm32h7/stm32_ltdc.c @@ -127,8 +127,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_LTDC_DEFBACKLIGHT -# define CONFIG_STM32H7_LTDC_DEFBACKLIGHT 0xf0 +#ifndef CONFIG_STM32_LTDC_DEFBACKLIGHT +# define CONFIG_STM32_LTDC_DEFBACKLIGHT 0xf0 #endif #define STM32_LTDC_BACKLIGHT_OFF 0x00 @@ -136,23 +136,23 @@ /* Layer 1 format */ -#if defined(CONFIG_STM32H7_LTDC_L1_L8) +#if defined(CONFIG_STM32_LTDC_L1_L8) # define STM32_LTDC_L1_BPP 8 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L1CMAP -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#elif defined(CONFIG_STM32_LTDC_L1_RGB565) # define STM32_LTDC_L1_BPP 16 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB565 -#elif defined(CONFIG_STM32H7_LTDC_L1_RGB888) +#elif defined(CONFIG_STM32_LTDC_L1_RGB888) # define STM32_LTDC_L1_BPP 24 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L1_DMA2D_PF DMA2D_PF_RGB888 -#elif defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) +#elif defined(CONFIG_STM32_LTDC_L1_ARGB8888) # define STM32_LTDC_L1_BPP 32 # define STM32_LTDC_L1_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L1PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -163,24 +163,24 @@ /* Layer 2 format */ -#ifdef CONFIG_STM32H7_LTDC_L2 -# if defined(CONFIG_STM32H7_LTDC_L2_L8) +#ifdef CONFIG_STM32_LTDC_L2 +# if defined(CONFIG_STM32_LTDC_L2_L8) # define STM32_LTDC_L2_BPP 8 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB8 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_L8) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_L8 # define STM32_LTDC_L2CMAP -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB565) +# elif defined(CONFIG_STM32_LTDC_L2_RGB565) # define STM32_LTDC_L2_BPP 16 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB16_565 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB565) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_LTDC_L2_RGB888) +# elif defined(CONFIG_STM32_LTDC_L2_RGB888) # define STM32_LTDC_L2_BPP 24 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB24 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_RGB888) # define STM32_LTDC_L2_DMA2D_PF DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) +# elif defined(CONFIG_STM32_LTDC_L2_ARGB8888) # define STM32_LTDC_L2_BPP 32 # define STM32_LTDC_L2_COLOR_FMT FB_FMT_RGB32 # define STM32_LTDC_L2PFCR_PF LTDC_LXPFCR_PF(LTDC_PF_ARGB8888) @@ -188,7 +188,7 @@ # else # error "LTDC pixel format not supported" # endif -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ /* Framebuffer sizes in bytes */ @@ -208,13 +208,13 @@ #define STM32_LTDC_LX_BYPP(n) ((n) / 8) -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT * 2) #else #define STM32_LTDC_L1_FBSIZE (STM32_LTDC_L1_STRIDE * STM32_LTDC_HEIGHT) #endif -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # ifndef CONFIG_STM32H7_LTDC_L2_WIDTH # define CONFIG_STM32H7_LTDC_L2_WIDTH STM32_LTDC_WIDTH # endif @@ -258,7 +258,7 @@ /* Debug option */ -#ifdef CONFIG_STM32H7_LTDC_REGDEBUG +#ifdef CONFIG_STM32_LTDC_REGDEBUG # define regerr lcderr # define reginfo lcdinfo #else @@ -273,10 +273,10 @@ * against wild framebuffer writes. */ -#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32H7_LTDC_FB_SIZE +#define STM32_LTDC_BUFFER_SIZE CONFIG_STM32_LTDC_FB_SIZE #define STM32_LTDC_BUFFER_FREE (STM32_LTDC_BUFFER_SIZE - \ STM32_LTDC_TOTAL_FBSIZE) -#define STM32_LTDC_BUFFER_START (CONFIG_STM32H7_LTDC_FB_BASE + \ +#define STM32_LTDC_BUFFER_START (CONFIG_STM32_LTDC_FB_BASE + \ STM32_LTDC_BUFFER_FREE/2) #if STM32_LTDC_BUFFER_FREE < 0 @@ -289,7 +289,7 @@ #define STM32_LTDC_ENDBUF_L1 (STM32_LTDC_BUFFER_L1 + \ STM32_LTDC_L1_FBSIZE) -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define STM32_LTDC_BUFFER_L2 STM32_LTDC_ENDBUF_L1 # define STM32_LTDC_ENDBUF_L2 (STM32_LTDC_BUFFER_L2 + \ STM32_LTDC_L2_FBSIZE) @@ -299,7 +299,7 @@ /* LTDC layer */ -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_NLAYERS 2 #else # define LTDC_NLAYERS 1 @@ -307,27 +307,27 @@ /* DMA2D layer */ -#ifdef CONFIG_STM32H7_DMA2D -# define DMA2D_NLAYERS CONFIG_STM32H7_DMA2D_NLAYERS +#ifdef CONFIG_STM32_DMA2D +# define DMA2D_NLAYERS CONFIG_STM32_DMA2D_NLAYERS # if DMA2D_NLAYERS < 1 # error "DMA2D must at least support 1 overlay" # endif -#define STM32_DMA2D_WIDTH CONFIG_STM32H7_DMA2D_LAYER_PPLINE +#define STM32_DMA2D_WIDTH CONFIG_STM32_DMA2D_LAYER_PPLINE -# if defined(CONFIG_STM32H7_DMA2D_L8) +# if defined(CONFIG_STM32_DMA2D_L8) # define STM32_DMA2D_STRIDE (STM32_DMA2D_WIDTH) # define STM32_DMA2D_BPP 8 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_L8 -# elif defined(CONFIG_STM32H7_DMA2D_RGB565) +# elif defined(CONFIG_STM32_DMA2D_RGB565) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 16 + 7) / 8) # define STM32_DMA2D_BPP 16 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB565 -# elif defined(CONFIG_STM32H7_DMA2D_RGB888) +# elif defined(CONFIG_STM32_DMA2D_RGB888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 24 + 7) / 8) # define STM32_DMA2D_BPP 24 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_RGB888 -# elif defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# elif defined(CONFIG_STM32_DMA2D_ARGB8888) # define STM32_DMA2D_STRIDE ((STM32_DMA2D_WIDTH * 32 + 7) / 8) # define STM32_DMA2D_BPP 32 # define STM32_DMA2D_COLOR_FMT DMA2D_PF_ARGB8888 @@ -335,63 +335,63 @@ # error "DMA2D pixel format not supported" # endif -# ifdef CONFIG_STM32H7_DMA2D_LAYER_SHARED -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE +# ifdef CONFIG_STM32_DMA2D_LAYER_SHARED +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE # define STM32_DMA2D_LAYER_SIZE 0 # else -# define STM32_DMA2D_FBSIZE CONFIG_STM32H7_DMA2D_FB_SIZE / DMA2D_NLAYERS +# define STM32_DMA2D_FBSIZE CONFIG_STM32_DMA2D_FB_SIZE / DMA2D_NLAYERS # define STM32_DMA2D_LAYER_SIZE STM32_DMA2D_FBSIZE -# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32H7_DMA2D_FB_SIZE +# if STM32_DMA2D_FBSIZE * DMA2D_NLAYERS > CONFIG_STM32_DMA2D_FB_SIZE # error "DMA2D framebuffer size to small for configured number of overlays" # endif -# endif /* CONFIG_STM32H7_DMA2D_LAYER_SHARED */ +# endif /* CONFIG_STM32_DMA2D_LAYER_SHARED */ # define STM32_DMA2D_HEIGHT STM32_DMA2D_FBSIZE / STM32_DMA2D_STRIDE -# define STM32_DMA2D_BUFFER_START CONFIG_STM32H7_DMA2D_FB_BASE +# define STM32_DMA2D_BUFFER_START CONFIG_STM32_DMA2D_FB_BASE #else # define DMA2D_NLAYERS 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_NOVERLAYS LTDC_NLAYERS + DMA2D_NLAYERS /* Dithering */ -#ifndef CONFIG_STM32H7_LTDC_DITHER_RED +#ifndef CONFIG_STM32_LTDC_DITHER_RED # define STM32_LTDC_DITHER_RED 0 #else -# define STM32_LTDC_DITHER_RED CONFIG_STM32H7_LTDC_DITHER_RED +# define STM32_LTDC_DITHER_RED CONFIG_STM32_LTDC_DITHER_RED #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_GREEN +#ifndef CONFIG_STM32_LTDC_DITHER_GREEN # define STM32_LTDC_DITHER_GREEN 0 #else -# define STM32_LTDC_DITHER_GREEN CONFIG_STM32H7_LTDC_DITHER_GREEN +# define STM32_LTDC_DITHER_GREEN CONFIG_STM32_LTDC_DITHER_GREEN #endif -#ifndef CONFIG_STM32H7_LTDC_DITHER_BLUE +#ifndef CONFIG_STM32_LTDC_DITHER_BLUE # define STM32_LTDC_DITHER_BLUE 0 #else -# define STM32_LTDC_DITHER_BLUE CONFIG_STM32H7_LTDC_DITHER_BLUE +# define STM32_LTDC_DITHER_BLUE CONFIG_STM32_LTDC_DITHER_BLUE #endif /* Background color */ -#ifndef CONFIG_STM32H7_LTDC_BACKCOLOR +#ifndef CONFIG_STM32_LTDC_BACKCOLOR # define STM32_LTDC_BACKCOLOR 0 #else -# define STM32_LTDC_BACKCOLOR CONFIG_STM32H7_LTDC_BACKCOLOR +# define STM32_LTDC_BACKCOLOR CONFIG_STM32_LTDC_BACKCOLOR #endif /* Layer default color */ -#ifdef CONFIG_STM32H7_LTDC_L1_COLOR -# define STM32_LTDC_L1_COLOR CONFIG_STM32H7_LTDC_L1_COLOR +#ifdef CONFIG_STM32_LTDC_L1_COLOR +# define STM32_LTDC_L1_COLOR CONFIG_STM32_LTDC_L1_COLOR #else # define STM32_LTDC_L1_COLOR 0x000000 #endif -#ifdef CONFIG_STM32H7_LTDC_L2 -# ifdef CONFIG_STM32H7_LTDC_L2_COLOR -# define STM32_LTDC_L2_COLOR CONFIG_STM32H7_LTDC_L2_COLOR +#ifdef CONFIG_STM32_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2_COLOR +# define STM32_LTDC_L2_COLOR CONFIG_STM32_LTDC_L2_COLOR # else # define STM32_LTDC_L2_COLOR 0x000000 # endif @@ -425,28 +425,28 @@ /* Check pixel format support by DMA2D driver */ -#ifdef CONFIG_STM32H7_DMA2D -# if defined(CONFIG_STM32H7_LTDC_L1_L8) || \ - defined(CONFIG_STM32H7_LTDC_L2_L8) -# if !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_DMA2D +# if defined(CONFIG_STM32_LTDC_L1_L8) || \ + defined(CONFIG_STM32_LTDC_L2_L8) +# if !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must support FB_FMT_RGB8 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB565) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB565) -# if !defined(CONFIG_STM32H7_DMA2D_RGB565) +# if defined(CONFIG_STM32_LTDC_L1_RGB565) || \ + defined(CONFIG_STM32_LTDC_L2_RGB565) +# if !defined(CONFIG_STM32_DMA2D_RGB565) # error "DMA2D must support FB_FMT_RGB16_565 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_RGB888) || \ - defined(CONFIG_STM32H7_LTDC_L2_RGB888) -# if !defined(CONFIG_STM32H7_DMA2D_RGB888) +# if defined(CONFIG_STM32_LTDC_L1_RGB888) || \ + defined(CONFIG_STM32_LTDC_L2_RGB888) +# if !defined(CONFIG_STM32_DMA2D_RGB888) # error "DMA2D must support FB_FMT_RGB24 pixel format" # endif # endif -# if defined(CONFIG_STM32H7_LTDC_L1_ARGB8888) || \ - defined(CONFIG_STM32H7_LTDC_L2_ARGB8888) -# if !defined(CONFIG_STM32H7_DMA2D_ARGB8888) +# if defined(CONFIG_STM32_LTDC_L1_ARGB8888) || \ + defined(CONFIG_STM32_LTDC_L2_ARGB8888) +# if !defined(CONFIG_STM32_DMA2D_ARGB8888) # error "DMA2D must support FB_FMT_RGB32 pixel format" # endif # endif @@ -454,12 +454,12 @@ /* Calculate the size of the layers clut table */ -#ifdef CONFIG_STM32H7_FB_CMAP -# if defined(CONFIG_STM32H7_DMA2D) && !defined(CONFIG_STM32H7_DMA2D_L8) +#ifdef CONFIG_STM32_FB_CMAP +# if defined(CONFIG_STM32_DMA2D) && !defined(CONFIG_STM32_DMA2D_L8) # error "DMA2D must also support L8 CLUT pixel format if supported by LTDC" # endif # ifdef STM32_LTDC_L1CMAP -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) @@ -467,7 +467,7 @@ # endif # ifdef STM32_LTDC_L2CMAP # undef STM32_LAYER_CLUT_SIZE -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * sizeof(uint32_t) * 2 # else # define STM32_LAYER_CLUT_SIZE STM32_LTDC_NCLUT * 3 * sizeof(uint8_t) * 2 @@ -475,7 +475,7 @@ # endif #endif -#ifndef CONFIG_STM32H7_FB_CMAP +#ifndef CONFIG_STM32_FB_CMAP # if defined(STM32_LTDC_L1CMAP) || defined(STM32_LTDC_L2CMAP) # undef STM32_LTDC_L1CMAP # undef STM32_LTDC_L2CMAP @@ -512,9 +512,9 @@ /* Acceleration support for LTDC overlays */ -#ifdef CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L1_CHROMAKEYEN # define STM32_LTDC_L1_CHROMAEN true -# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# define STM32_LTDC_L1_CHROMAKEY CONFIG_STM32_LTDC_L1_CHROMAKEY # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L1_CHROMAEN false @@ -522,9 +522,9 @@ # define LTDC_LTDC_ACCL_L1 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_LTDC_L2_CHROMAKEYEN +#ifdef CONFIG_STM32_LTDC_L2_CHROMAKEYEN # define STM32_LTDC_L2_CHROMAEN true -# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# define STM32_LTDC_L2_CHROMAKEY CONFIG_STM32_LTDC_L2_CHROMAKEY # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP | FB_ACCL_CHROMA #else # define STM32_LTDC_L2_CHROMAEN false @@ -532,34 +532,34 @@ # define LTDC_LTDC_ACCL_L2 FB_ACCL_TRANSP #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D # ifdef CONFIG_FB_OVERLAY_BLIT -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_BLIT_ACCL FB_ACCL_BLIT # else # define LTDC_BLIT_ACCL FB_ACCL_BLIT | FB_ACCL_BLEND -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ # else # define LTDC_BLIT_ACCL 0 # endif /* CONFIG_FB_OVERLAY_BLIT */ -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP # define LTDC_DMA2D_ACCL LTDC_BLIT_ACCL # else # define LTDC_DMA2D_ACCL FB_ACCL_COLOR | LTDC_BLIT_ACCL -# endif /* CONFIG_STM32H7_FB_CMAP */ +# endif /* CONFIG_STM32_FB_CMAP */ #else # define LTDC_DMA2D_ACCL 0 -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ #define LTDC_L1_ACCL LTDC_LTDC_ACCL_L1 | LTDC_DMA2D_ACCL -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 # define LTDC_L2_ACCL LTDC_LTDC_ACCL_L2 | LTDC_DMA2D_ACCL #endif /* Acceleration support for DMA2D overlays */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP # ifdef CONFIG_FB_OVERLAY_BLIT # define DMA2D_ACCL FB_ACCL_BLIT | FB_ACCL_AREA # else @@ -585,7 +585,7 @@ /* Color normalization */ -#if defined(CONFIG_STM32H7_LTDC_L1_RGB565) +#if defined(CONFIG_STM32_LTDC_L1_RGB565) # define RGB888_R(x) (((((x) >> 11) & 0x1f) * 527 + 23) >> 6) # define RGB888_G(x) (((((x) >> 5) & 0x3f) * 259 + 33) >> 6) # define RGB888_B(x) ((((x) & 0x1f) * 527 + 23) >> 6) @@ -618,7 +618,7 @@ struct stm32_ltdc_s struct fb_overlayinfo_s oinfo; /* Overlay info */ #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D struct stm32_dma2d_overlay_s dma2dinfo; /* Overlay info for DMA2D */ #endif @@ -643,7 +643,7 @@ struct stm32_ltdcdev_s /* Cmap information */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP struct fb_cmap_s cmap; #endif @@ -651,7 +651,7 @@ struct stm32_ltdcdev_s struct stm32_ltdc_s layer[LTDC_NOVERLAYS]; -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Interface to the dma2d controller */ struct dma2d_layer_s *dma2d; @@ -699,7 +699,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, bool enable); static void stm32_ltdc_linit(uint8_t lid); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void); # ifdef CONFIG_FB_OVERLAY_BLIT @@ -708,7 +708,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, # endif #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lputclut(struct stm32_ltdc_s *layer, const struct fb_cmap_s *cmap); static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, @@ -731,7 +731,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, * mapping */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap); static int stm32_putcmap(struct fb_vtable_s *vtable, @@ -746,7 +746,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, static int stm32_waitforvsync(struct fb_vtable_s *vtable); #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo); #endif @@ -806,16 +806,16 @@ static const uint32_t g_ltdcpins[] = #define STM32_LTDC_NPINCONFIGS (sizeof(g_ltdcpins) / sizeof(uint32_t)) -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* The layers clut table entries */ static uint8_t g_redclut[STM32_LTDC_NCLUT]; static uint8_t g_greenclut[STM32_LTDC_NCLUT]; static uint8_t g_blueclut[STM32_LTDC_NCLUT]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY static uint8_t g_transpclut[STM32_LTDC_NCLUT]; # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The LTDC semaphore that enforces mutually exclusive access */ @@ -847,12 +847,12 @@ static struct stm32_ltdcdev_s g_vtable = .waitforvsync = stm32_waitforvsync #endif -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) , .pandisplay = stm32_pandisplay #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP , .getcmap = stm32_getcmap, .putcmap = stm32_putcmap @@ -873,7 +873,7 @@ static struct stm32_ltdcdev_s g_vtable = # endif #endif /* CONFIG_FB_OVERLAY */ }, -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 .pinfo = { .fbmem = (uint8_t *)STM32_LTDC_BUFFER_L2, @@ -901,7 +901,7 @@ static struct stm32_ltdcdev_s g_vtable = .display = 0, .bpp = STM32_LTDC_L1_BPP, .xres_virtual = STM32_LTDC_WIDTH, -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) .yres_virtual = STM32_LTDC_HEIGHT * 2, #else .yres_virtual = STM32_LTDC_HEIGHT, @@ -919,9 +919,9 @@ static struct stm32_ltdcdev_s g_vtable = .noverlays = LTDC_NOVERLAYS # endif } -#endif /* CONFIG_STM32H7_LTDC_L2 */ +#endif /* CONFIG_STM32_LTDC_L2 */ , -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP .cmap = { .first = 0, @@ -929,7 +929,7 @@ static struct stm32_ltdcdev_s g_vtable = .red = g_redclut, .green = g_greenclut, .blue = g_blueclut, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY .transp = g_transpclut # endif } @@ -965,7 +965,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L1_DMA2D_PF, @@ -977,7 +977,7 @@ static struct stm32_ltdcdev_s g_vtable = #endif .lock = &g_lock } -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , .layer[LTDC_LAYER_L2] = { @@ -1009,7 +1009,7 @@ static struct stm32_ltdcdev_s g_vtable = }, #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D .dma2dinfo = { .fmt = STM32_LTDC_L2_DMA2D_PF, @@ -1031,7 +1031,7 @@ static struct stm32_ltdcdev_s g_vtable = static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = { STM32_LTDC_WIDTH -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_WIDTH #endif }; @@ -1041,7 +1041,7 @@ static const uint32_t stm32_width_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = { STM32_LTDC_HEIGHT -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_HEIGHT #endif }; @@ -1051,7 +1051,7 @@ static const uint32_t stm32_height_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_STRIDE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_STRIDE #endif }; @@ -1061,7 +1061,7 @@ static const uint32_t stm32_stride_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_BPP -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_BPP #endif }; @@ -1071,7 +1071,7 @@ static const uint32_t stm32_bpp_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_FBSIZE -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_FBSIZE #endif }; @@ -1081,7 +1081,7 @@ static const uint32_t stm32_fblen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = { STM32_LTDC_BUFFER_L1 -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_BUFFER_L2 #endif }; @@ -1091,7 +1091,7 @@ static const uint32_t stm32_fbmem_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_COLOR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_COLOR #endif }; @@ -1101,7 +1101,7 @@ static const uint32_t stm32_defaultcolor_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAKEY -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAKEY #endif }; @@ -1111,7 +1111,7 @@ static const uint32_t stm32_chromakey_layer_t[LTDC_NLAYERS] = static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1_CHROMAEN -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2_CHROMAEN #endif }; @@ -1121,7 +1121,7 @@ static const bool stm32_chromakeyen_layer_t[LTDC_NLAYERS] = static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR_PF -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR_PF #endif }; @@ -1133,7 +1133,7 @@ static const uint32_t stm32_fmt_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CR #endif }; @@ -1143,7 +1143,7 @@ static const uintptr_t stm32_cr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WHPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WHPCR #endif }; @@ -1153,7 +1153,7 @@ static const uintptr_t stm32_whpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1WVPCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2WVPCR #endif }; @@ -1163,7 +1163,7 @@ static const uintptr_t stm32_wvpcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1PFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2PFCR #endif }; @@ -1173,7 +1173,7 @@ static const uintptr_t stm32_pfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1DCCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2DCCR #endif }; @@ -1183,7 +1183,7 @@ static const uintptr_t stm32_dccr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CKCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CKCR #endif }; @@ -1193,7 +1193,7 @@ static const uintptr_t stm32_ckcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CACR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CACR #endif }; @@ -1203,7 +1203,7 @@ static const uintptr_t stm32_cacr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1BFCR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2BFCR #endif }; @@ -1213,7 +1213,7 @@ static const uintptr_t stm32_bfcr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBAR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBAR #endif }; @@ -1223,7 +1223,7 @@ static const uintptr_t stm32_cfbar_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLR #endif }; @@ -1233,22 +1233,22 @@ static const uintptr_t stm32_cfblr_layer_t[LTDC_NLAYERS] = static const uintptr_t stm32_cfblnr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CFBLNR -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CFBLNR #endif }; /* LTDC_LxCLUTWR */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static const uintptr_t stm32_clutwr_layer_t[LTDC_NLAYERS] = { STM32_LTDC_L1CLUTWR -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 , STM32_LTDC_L2CLUTWR # endif }; -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* The initialized state of the driver */ @@ -1501,7 +1501,7 @@ static int stm32_ltdcirq(int irq, void *context, void *arg) putreg32(LTDC_ICR_CRRIF, STM32_LTDC_ICR); priv->error = OK; -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) fb_remove_paninfo(&g_vtable.vtable, FB_NO_OVERLAY); #endif } @@ -1681,7 +1681,7 @@ static void stm32_ltdc_globalconfig(void) /* Configure dither */ stm32_ltdc_dither( -#ifdef CONFIG_STM32H7_LTDC_DITHER +#ifdef CONFIG_STM32_LTDC_DITHER true, #else false, @@ -1953,7 +1953,7 @@ static void stm32_ltdc_lchromakey(struct stm32_ltdc_s *layer, /* Set chromakey */ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP uint8_t r = g_vtable.cmap.red[chroma]; uint8_t g = g_vtable.cmap.green[chroma]; uint8_t b = g_vtable.cmap.blue[chroma]; @@ -2023,7 +2023,7 @@ static void stm32_ltdc_lchromakeyenable(struct stm32_ltdc_s *layer, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static void stm32_ltdc_lclutenable(struct stm32_ltdc_s *layer, bool enable) { uint32_t regval; @@ -2127,7 +2127,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, for (n = cmap->first; n < cmap->len && n < STM32_LTDC_NCLUT; n++) { -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n] = priv_cmap->transp[n]; # endif cmap->red[n] = priv_cmap->red[n]; @@ -2136,7 +2136,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, reginfo("color = %d, transp=%02x, red=%02x, green=%02x, blue=%02x\n", n, -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY cmap->transp[n], # endif cmap->red[n], @@ -2144,7 +2144,7 @@ static void stm32_ltdc_lgetclut(struct stm32_ltdc_s *layer, cmap->blue[n]); } } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ltdc_lclear @@ -2176,7 +2176,7 @@ static void stm32_ltdc_lclear(uint8_t overlayno) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) +#if defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, const struct fb_area_s *area) { @@ -2187,7 +2187,7 @@ static bool stm32_ltdc_lvalidate(const struct stm32_ltdc_s *layer, return (offset <= layer->oinfo.fblen && area->w > 0 && area->h > 0); } -#endif /* defined(CONFIG_STM32H7_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ +#endif /* defined(CONFIG_STM32_DMA2D) && defined(CONFIG_FB_OVERLAY_BLIT) */ /**************************************************************************** * Name: stm32_ltdc_linit @@ -2247,7 +2247,7 @@ static void stm32_ltdc_linit(uint8_t overlay) stm32_ltdc_lchromakeyenable(layer, stm32_chromakeyen_layer_t[overlay]); -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Disable clut by default */ if (dev->vinfo.fmt == FB_FMT_RGB8) @@ -2287,7 +2287,7 @@ static void stm32_ltdc_linit(uint8_t overlay) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D static void stm32_ltdc_dma2dlinit(void) { int n; @@ -2323,7 +2323,7 @@ static void stm32_ltdc_dma2dlinit(void) layer->dma2dinfo.oinfo = &layer->oinfo; } } -#endif /* CONFIG_STM32H7_DMA2D */ +#endif /* CONFIG_STM32_DMA2D */ /**************************************************************************** * Public Functions @@ -2410,7 +2410,7 @@ static int stm32_getplaneinfo(struct fb_vtable_s *vtable, int planeno, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP static int stm32_getcmap(struct fb_vtable_s *vtable, struct fb_cmap_s *cmap) { @@ -2440,7 +2440,7 @@ static int stm32_getcmap(struct fb_vtable_s *vtable, */ struct stm32_ltdc_s *layer; -# ifdef CONFIG_STM32H7_LTDC_L2 +# ifdef CONFIG_STM32_LTDC_L2 layer = &priv->layer[LTDC_LAYER_L2]; # else layer = &priv->layer[LTDC_LAYER_L1]; @@ -2510,7 +2510,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, priv_cmap->red[n] = cmap->red[n]; priv_cmap->green[n] = cmap->green[n]; priv_cmap->blue[n] = cmap->blue[n]; -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY /* Not supported by LTDC */ priv_cmap->transp[n] = cmap->transp[n]; @@ -2530,7 +2530,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, stm32_ltdc_lputclut(layer, priv_cmap); } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Update dma2d cmap */ priv->dma2d->setclut(cmap); @@ -2542,7 +2542,7 @@ static int stm32_putcmap(struct fb_vtable_s *vtable, return ret; } -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /**************************************************************************** * Name: stm32_ioctl_waitforvsync @@ -2570,7 +2570,7 @@ static int stm32_waitforvsync(struct fb_vtable_s *vtable) * Description: * Entrypoint ioctl FBIOPAN_DISPLAY ****************************************************************************/ -#if defined(CONFIG_STM32H7_LTDC_FB_DOUBLE_BUFFER) +#if defined(CONFIG_STM32_LTDC_FB_DOUBLE_BUFFER) static int stm32_pandisplay(struct fb_vtable_s *vtable, struct fb_planeinfo_s *pinfo) { @@ -2647,7 +2647,7 @@ static int stm32_settransp(struct fb_vtable_s *vtable, layer->oinfo.transp.transp = oinfo->transp.transp; layer->oinfo.transp.transp_mode = oinfo->transp.transp_mode; -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (layer->oinfo.transp.transp_mode == 0) { layer->dma2dinfo.transp_mode = STM32_DMA2D_PFCCR_AM_CONST; @@ -2694,14 +2694,14 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, int ret; struct stm32_ltdc_s *layer = &priv->layer[oinfo->overlay]; -# ifndef CONFIG_STM32H7_LTDC_L1_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L1_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L1) { return -ENOSYS; } # endif -# ifndef CONFIG_STM32H7_LTDC_L2_CHROMAKEY +# ifndef CONFIG_STM32_LTDC_L2_CHROMAKEY if (oinfo->overlay == LTDC_LAYER_L2) { return -ENOSYS; @@ -2709,7 +2709,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, # endif nxsem_wait(layer->lock); -# ifdef CONFIG_STM32H7_FB_CMAP +# ifdef CONFIG_STM32_FB_CMAP if (oinfo->chromakey >= g_vtable.cmap.len) { lcderr("ERROR: Clut index %d is out of range\n", oinfo->chromakey); @@ -2729,7 +2729,7 @@ static int stm32_setchromakey(struct fb_vtable_s *vtable, nxsem_post(layer->lock); return ret; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* Chromakey not supported by DMA2D */ @@ -2757,7 +2757,7 @@ static int stm32_setcolor(struct fb_vtable_s *vtable, if (oinfo->overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D /* Set color within the active overlay is not supported by LTDC. So use * DMA2D controller instead when configured. @@ -2817,7 +2817,7 @@ static int stm32_setblank(struct fb_vtable_s *vtable, return OK; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D else if (oinfo->overlay < LTDC_NOVERLAYS) { /* DMA2D overlays are non visible */ @@ -2851,7 +2851,7 @@ static int stm32_setarea(struct fb_vtable_s *vtable, return -ENOSYS; } -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D if (oinfo->overlay < LTDC_NOVERLAYS) { struct stm32_ltdcdev_s *priv = (struct stm32_ltdcdev_s *)vtable; @@ -2885,7 +2885,7 @@ static int stm32_blit(struct fb_vtable_s *vtable, if (blit->dest.overlay < LTDC_NOVERLAYS && blit->src.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s sarea; const struct fb_area_s *darea = &blit->dest.area; @@ -2944,7 +2944,7 @@ static int stm32_blend(struct fb_vtable_s *vtable, blend->foreground.overlay < LTDC_NOVERLAYS && blend->background.overlay < LTDC_NOVERLAYS) { -# ifdef CONFIG_STM32H7_DMA2D +# ifdef CONFIG_STM32_DMA2D int ret; struct fb_area_s barea; const struct fb_area_s *darea = &blend->dest.area; @@ -3055,7 +3055,7 @@ int stm32_ltdcinitialize(void) lcdinfo("Configure global register\n"); stm32_ltdc_globalconfig(); -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D /* Initialize the dma2d controller */ ret = stm32_dma2dinitialize(); @@ -3071,26 +3071,26 @@ int stm32_ltdcinitialize(void) DEBUGASSERT(g_vtable.dma2d != NULL); #endif -#ifdef CONFIG_STM32H7_FB_CMAP +#ifdef CONFIG_STM32_FB_CMAP /* Cleanup clut */ memset(&g_redclut, 0, STM32_LTDC_NCLUT); memset(&g_blueclut, 0, STM32_LTDC_NCLUT); memset(&g_greenclut, 0, STM32_LTDC_NCLUT); -# ifdef CONFIG_STM32H7_FB_TRANSPARENCY +# ifdef CONFIG_STM32_FB_TRANSPARENCY memset(&g_transpclut, 0, STM32_LTDC_NCLUT); # endif -#endif /* CONFIG_STM32H7_FB_CMAP */ +#endif /* CONFIG_STM32_FB_CMAP */ /* Initialize ltdc layer */ lcdinfo("Initialize ltdc layer\n"); stm32_ltdc_linit(LTDC_LAYER_L1); -#ifdef CONFIG_STM32H7_LTDC_L2 +#ifdef CONFIG_STM32_LTDC_L2 stm32_ltdc_linit(LTDC_LAYER_L2); #endif -#ifdef CONFIG_STM32H7_DMA2D +#ifdef CONFIG_STM32_DMA2D stm32_ltdc_dma2dlinit(); #endif /* Enable the backlight */ @@ -3184,7 +3184,7 @@ void stm32_ltdcuninitialize(void) #ifdef CONFIG_STM32H7_LCD_BACKLIGHT void stm32_backlight(bool blon) { - /* Set default backlight level CONFIG_STM32H7_LTDC_DEFBACKLIGHT */ + /* Set default backlight level CONFIG_STM32_LTDC_DEFBACKLIGHT */ lcderr("ERROR: Not supported\n"); } diff --git a/arch/arm/src/stm32h7/stm32_ltdc.h b/arch/arm/src/stm32h7/stm32_ltdc.h index 53a73da7d08..da7d21b7ed7 100644 --- a/arch/arm/src/stm32h7/stm32_ltdc.h +++ b/arch/arm/src/stm32h7/stm32_ltdc.h @@ -91,12 +91,12 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); * Name: stm32_lcd_backlight * * Description: - * If CONFIG_STM32F7_LCD_BACKLIGHT is defined, then the board-specific + * If CONFIG_STM32_LCD_BACKLIGHT is defined, then the board-specific * logic must provide this interface to turn the backlight on and off. * ****************************************************************************/ -#ifdef CONFIG_STM32F7_LCD_BACKLIGHT +#ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif #endif /* __ARCH_ARM_SRC_STM32F7_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32h7/stm32_mdio.c b/arch/arm/src/stm32h7/stm32_mdio.c index d524b27ce1f..412aedcb915 100644 --- a/arch/arm/src/stm32h7/stm32_mdio.c +++ b/arch/arm/src/stm32h7/stm32_mdio.c @@ -30,7 +30,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32H7_ETHMAC_REGDEBUG +#ifdef CONFIG_STM32_ETHMAC_REGDEBUG static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); static void stm32_checksetup(void); diff --git a/arch/arm/src/stm32h7/stm32_mpuinit.c b/arch/arm/src/stm32h7/stm32_mpuinit.c index 625e7eb2a5f..a141895b210 100644 --- a/arch/arm/src/stm32h7/stm32_mpuinit.c +++ b/arch/arm/src/stm32h7/stm32_mpuinit.c @@ -44,7 +44,7 @@ ****************************************************************************/ #ifdef CONFIG_RPTUN -# ifdef CONFIG_STM32H7_SHMEM_SRAM3 +# ifdef CONFIG_STM32_SHMEM_SRAM3 # define STM32_SHMEM_BASE STM32_SRAM3_BASE # define STM32_SHMEM_SIZE STM32_SRAM3_SIZE # else diff --git a/arch/arm/src/stm32h7/stm32_oneshot.c b/arch/arm/src/stm32h7/stm32_oneshot.c index 078d6efe502..e1fc56718ec 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.c +++ b/arch/arm/src/stm32h7/stm32_oneshot.c @@ -39,7 +39,7 @@ #include "stm32_oneshot.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32H7_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irg_num, void * context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32H7_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32H7_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -401,4 +401,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32h7/stm32_oneshot.h b/arch/arm/src/stm32h7/stm32_oneshot.h index 412f901e16b..f16523985ff 100644 --- a/arch/arm/src/stm32h7/stm32_oneshot.h +++ b/arch/arm/src/stm32h7/stm32_oneshot.h @@ -36,22 +36,22 @@ #include "stm32_tim.h" -#ifdef CONFIG_STM32H7_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32H7_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32H7_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32H7_ONESHOT_MAXTIMERS -# define CONFIG_STM32H7_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32H7_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -193,5 +193,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32H7_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32h7/stm32_otg.h b/arch/arm/src/stm32h7/stm32_otg.h index 43208d091f9..a847ccf74c0 100644 --- a/arch/arm/src/stm32h7/stm32_otg.h +++ b/arch/arm/src/stm32h7/stm32_otg.h @@ -37,21 +37,21 @@ #include "stm32_rcc.h" #include "hardware/stm32_otg.h" -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) #if (STM32_RCC_D2CCIP2R_USBSRC == RCC_D2CCIP2R_USBSEL_HSI48) && \ - !defined(CONFIG_STM32H7_HSI48) + !defined(CONFIG_STM32_HSI48) # error board.h selected HSI48 as USB clock source, but HSI48 is not \ enabled. Enable STM32_HSI48 #endif -#if defined(CONFIG_STM32H7_OTGHS) && !defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS) && !defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) # error OTG HS selected but no ULPI enabled #endif -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) && \ - !defined(CONFIG_STM32H7_SYSCFG_IOCOMPENSATION) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) && \ + !defined(CONFIG_STM32_SYSCFG_IOCOMPENSATION) # error External ULPI needs IOCOMPENSATION enabled #endif @@ -126,7 +126,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller); struct usbdev_s; void stm32_usbsuspend(struct usbdev_s *dev, bool resume); -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * @@ -145,5 +145,5 @@ void stm32_usbulpireset(struct usbdev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32h7/stm32_otgdev.c b/arch/arm/src/stm32h7/stm32_otgdev.c index 22e1774b527..ed564555d03 100644 --- a/arch/arm/src/stm32h7/stm32_otgdev.c +++ b/arch/arm/src/stm32h7/stm32_otgdev.c @@ -53,8 +53,8 @@ #include "stm32_otg.h" #include "arm_internal.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32H7_OTGFS) || \ - defined(CONFIG_STM32H7_OTGHS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS) || \ + defined(CONFIG_STM32_OTGHS)) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ /* OTG device selection *****************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -70,7 +70,7 @@ # define GPIO_OTG_ID GPIO_OTGFS_ID # define GPIO_OTG_SOF GPIO_OTGFS_SOF # define STM32_OTG_FIFO_SIZE 4096 -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) # define STM32_IRQ_OTG STM32_IRQ_OTGHS # define STM32_OTG_BASE STM32_OTGHS_BASE # define GPIO_OTG_DM GPIO_OTGHS_DM @@ -82,7 +82,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_USBDEV) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_USBDEV) && defined(CONFIG_STM32_OTGHS_USBDEV) # error Only one USBDEV role supported #endif @@ -552,7 +552,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -879,7 +879,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -942,7 +942,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -2138,8 +2138,8 @@ static void stm32_usbreset(struct stm32_usbdev_s *priv) stm32_setaddress(priv, 0); priv->devstate = DEVSTATE_DEFAULT; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; @@ -3447,7 +3447,7 @@ static inline void stm32_enuminterrupt(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GUSBCFG); regval &= ~OTG_GUSBCFG_TRDT_MASK; -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= OTG_GUSBCFG_TRDT(9); #else regval |= OTG_GUSBCFG_TRDT(6); @@ -5289,9 +5289,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Full speed serial transceiver select */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5299,9 +5299,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GUSBCFG); #endif -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* ULPI Full speed mode */ regval = stm32_getreg(STM32_OTG_GUSBCFG); @@ -5343,9 +5343,9 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_GCCFG); -#if (defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI)) || \ - defined(CONFIG_STM32H7_OTGFS_USBDEV) +#if (defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI)) || \ + defined(CONFIG_STM32_OTGFS_USBDEV) /* Enable USB FS transceiver */ regval |= OTG_GCCFG_PWRDWN; @@ -5360,8 +5360,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) stm32_putreg(regval, STM32_OTG_GCCFG); up_mdelay(20); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable delay to default timing, necessary for some ULPI PHYs such * as such as USB334x */ @@ -5404,10 +5404,10 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval = stm32_getreg(STM32_OTG_DCFG); regval &= ~OTG_DCFG_DSPD_MASK; -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_FS) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_FS) regval |= OTG_DCFG_DSPD_FSHS; -#elif defined(CONFIG_STM32H7_OTGHS_USBDEV) +#elif defined(CONFIG_STM32_OTGHS_USBDEV) regval |= OTG_DCFG_DSPD_HS; #else regval |= OTG_DCFG_DSPD_FS; @@ -5550,8 +5550,8 @@ static void stm32_hwinitialize(struct stm32_usbdev_s *priv) regval &= OTG_GINT_RESERVED; stm32_putreg(regval | OTG_GINT_RC_W1, STM32_OTG_GINTSTS); -#if defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_NO_ULPI) +#if defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_NO_ULPI) /* Disable the ULPI Clock enable in RCC AHB1 Register. This must * be done because if both the ULPI and the FS PHY clock enable bits * are set at the same time, the ARM never awakens from WFI due to @@ -5636,7 +5636,7 @@ void arm_usbinitialize(void) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5660,8 +5660,8 @@ void arm_usbinitialize(void) * current detection. */ -#if !(defined(CONFIG_STM32H7_OTGHS_USBDEV) && \ - defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI)) +#if !(defined(CONFIG_STM32_OTGHS_USBDEV) && \ + defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI)) /* Configure OTG alternate function pins */ stm32_configgpio(GPIO_OTG_DM); @@ -5674,7 +5674,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -# ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +# ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); # endif @@ -5866,7 +5866,7 @@ int usbdev_register(struct usbdevclass_driver_s *driver) stm32_pullup(&priv->usbdev, true); -#if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) priv->usbdev.speed = USB_SPEED_HIGH; #else priv->usbdev.speed = USB_SPEED_FULL; diff --git a/arch/arm/src/stm32h7/stm32_otghost.c b/arch/arm/src/stm32h7/stm32_otghost.c index 095f2204183..1e34a411832 100644 --- a/arch/arm/src/stm32h7/stm32_otghost.c +++ b/arch/arm/src/stm32h7/stm32_otghost.c @@ -60,7 +60,7 @@ #include "stm32_otg.h" #include "stm32_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32H7_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* OTG host selection *******************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) # define STM32_IRQ_OTG STM32_IRQ_OTGFS # define STM32_OTG_BASE STM32_OTGFS_BASE # define GPIO_OTG_DM GPIO_OTGFS_DM @@ -89,7 +89,7 @@ # error Not selected USBDEV peripheral #endif -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_HOST) # error Only one HOST role supported #endif @@ -100,8 +100,8 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -114,16 +114,16 @@ * CONFIG_STM32H7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. - * CONFIG_STM32H7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG_FEATURES. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32H7_SYSCFG -# error "CONFIG_STM32H7_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ @@ -153,8 +153,8 @@ /* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ #ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_STM32H7_USBHOST_REGDEBUG -# undef CONFIG_STM32H7_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -299,7 +299,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -312,7 +312,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32H7_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -523,7 +523,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { uinfo("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -538,7 +538,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -602,7 +602,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -624,7 +624,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -5414,7 +5414,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* Enable USB regulator if configured */ -#ifdef CONFIG_STM32H7_OTG_USBREGEN +#ifdef CONFIG_STM32_OTG_USBREGEN regval |= STM32_PWR_CR3_USBREGEN; #else regval &= ~STM32_PWR_CR3_USBREGEN; @@ -5458,7 +5458,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32H7_OTG_SOFOUTPUT +#ifdef CONFIG_STM32_OTG_SOFOUTPUT stm32_configgpio(GPIO_OTG_SOF); #endif @@ -5484,4 +5484,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32H7_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32h7/stm32_pulsecount.c b/arch/arm/src/stm32h7/stm32_pulsecount.c index f0a5189aba0..b963fbf02cd 100644 --- a/arch/arm/src/stm32h7/stm32_pulsecount.c +++ b/arch/arm/src/stm32h7/stm32_pulsecount.c @@ -83,7 +83,7 @@ /* Advanced timer support */ -# if defined(CONFIG_STM32H7_TIM1_PULSECOUNT) || defined(CONFIG_STM32H7_TIM8_PULSECOUNT) +# if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) # endif /* Synchronisation support */ @@ -191,10 +191,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -221,107 +221,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32H7_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32H7_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32H7_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32H7_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32H7_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -332,7 +332,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -340,7 +340,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1332,21 +1332,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32H7_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32H7_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1419,7 +1419,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCEN_TIM1; @@ -1428,7 +1428,7 @@ static int pulsecount_set_apb_clock(struct stm32_tim_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCEN_TIM8; @@ -1611,7 +1611,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = TIMRCCRST_TIM1; @@ -1620,7 +1620,7 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = TIMRCCRST_TIM8; @@ -1782,7 +1782,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1792,7 +1792,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index d2dc3b4f06e..103b8d72785 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -49,7 +49,7 @@ * 2. STM32 TIMER IP version 2 - F3 (no F37x), F7, H7, L4, L4+ */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /**************************************************************************** * Pre-processor Definitions @@ -171,7 +171,7 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32H7_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -243,7 +243,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -316,10 +316,10 @@ static int pwm_break_dt_configure(struct stm32_pwmtimer_s *priv); static int pwm_sync_configure(struct stm32_pwmtimer_s *priv, uint8_t trgo); #endif -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -356,7 +356,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -379,16 +379,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -403,114 +403,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1POL, - .idle = CONFIG_STM32H7_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH1NPOL, - .idle = CONFIG_STM32H7_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM1_CH2MODE, -#ifdef CONFIG_STM32H7_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2POL, - .idle = CONFIG_STM32H7_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH2NPOL, - .idle = CONFIG_STM32H7_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM1_CH3MODE, -#ifdef CONFIG_STM32H7_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3POL, - .idle = CONFIG_STM32H7_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH3NPOL, - .idle = CONFIG_STM32H7_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM1_CH4MODE, -#ifdef CONFIG_STM32H7_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH4POL, - .idle = CONFIG_STM32H7_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM1_CH5MODE, -#ifdef CONFIG_STM32H7_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH5POL, - .idle = CONFIG_STM32H7_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM1_CH6MODE, -#ifdef CONFIG_STM32H7_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM1_CH6POL, - .idle = CONFIG_STM32H7_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -521,18 +521,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32H7_TIM1_MODE, - .lock = CONFIG_STM32H7_TIM1_LOCK, - .t_dts = CONFIG_STM32H7_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -540,72 +540,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = TIMCLK_TIM1, }; -#endif /* CONFIG_STM32H7_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM2_CH1MODE, -#ifdef CONFIG_STM32H7_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH1POL, - .idle = CONFIG_STM32H7_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM2_CH2MODE, -#ifdef CONFIG_STM32H7_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH2POL, - .idle = CONFIG_STM32H7_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM2_CH3MODE, -#ifdef CONFIG_STM32H7_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH3POL, - .idle = CONFIG_STM32H7_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM2_CH4MODE, -#ifdef CONFIG_STM32H7_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM2_CH4POL, - .idle = CONFIG_STM32H7_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -617,14 +617,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32H7_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -636,72 +636,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .base = STM32_TIM2_BASE, .pclk = TIMCLK_TIM2, }; -#endif /* CONFIG_STM32H7_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM3_CH1MODE, -#ifdef CONFIG_STM32H7_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH1POL, - .idle = CONFIG_STM32H7_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM3_CH2MODE, -#ifdef CONFIG_STM32H7_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH2POL, - .idle = CONFIG_STM32H7_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM3_CH3MODE, -#ifdef CONFIG_STM32H7_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH3POL, - .idle = CONFIG_STM32H7_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM3_CH4MODE, -#ifdef CONFIG_STM32H7_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM3_CH4POL, - .idle = CONFIG_STM32H7_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -713,14 +713,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32H7_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -732,72 +732,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = TIMCLK_TIM3, }; -#endif /* CONFIG_STM32H7_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM4_CH1MODE, -#ifdef CONFIG_STM32H7_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH1POL, - .idle = CONFIG_STM32H7_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM4_CH2MODE, -#ifdef CONFIG_STM32H7_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH2POL, - .idle = CONFIG_STM32H7_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM4_CH3MODE, -#ifdef CONFIG_STM32H7_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH3POL, - .idle = CONFIG_STM32H7_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM4_CH4MODE, -#ifdef CONFIG_STM32H7_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM4_CH4POL, - .idle = CONFIG_STM32H7_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -809,14 +809,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32H7_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -828,71 +828,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = TIMCLK_TIM4, }; -#endif /* CONFIG_STM32H7_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM5_CH1MODE, -#ifdef CONFIG_STM32H7_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH1POL, - .idle = CONFIG_STM32H7_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM5_CH2MODE, -#ifdef CONFIG_STM32H7_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH2POL, - .idle = CONFIG_STM32H7_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM5_CH3MODE, -#ifdef CONFIG_STM32H7_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH3POL, - .idle = CONFIG_STM32H7_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM5_CH4MODE, -#ifdef CONFIG_STM32H7_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM5_CH4POL, - .idle = CONFIG_STM32H7_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -903,14 +903,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32H7_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -922,18 +922,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = TIMCLK_TIM5, }; -#endif /* CONFIG_STM32H7_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -948,114 +948,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1POL, - .idle = CONFIG_STM32H7_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH1NPOL, - .idle = CONFIG_STM32H7_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM8_CH2MODE, -#ifdef CONFIG_STM32H7_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2POL, - .idle = CONFIG_STM32H7_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH2NPOL, - .idle = CONFIG_STM32H7_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32H7_TIM8_CH3MODE, -#ifdef CONFIG_STM32H7_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3POL, - .idle = CONFIG_STM32H7_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH3NPOL, - .idle = CONFIG_STM32H7_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32H7_TIM8_CH4MODE, -#ifdef CONFIG_STM32H7_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH4POL, - .idle = CONFIG_STM32H7_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32H7_TIM8_CH5MODE, -#ifdef CONFIG_STM32H7_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH5POL, - .idle = CONFIG_STM32H7_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32H7_TIM8_CH6MODE, -#ifdef CONFIG_STM32H7_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM8_CH6POL, - .idle = CONFIG_STM32H7_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -1066,18 +1066,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32H7_TIM8_MODE, - .lock = CONFIG_STM32H7_TIM8_LOCK, - .t_dts = CONFIG_STM32H7_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1085,40 +1085,40 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = TIMCLK_TIM8, }; -#endif /* CONFIG_STM32H7_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM static struct stm32_pwmchan_s g_pwm12channels[] = { /* TIM12 has 2 channels */ -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM12_CH1MODE, -#ifdef CONFIG_STM32H7_TIM12_CH1OUT + .mode = CONFIG_STM32_TIM12_CH1MODE, +#ifdef CONFIG_STM32_TIM12_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH1POL, - .idle = CONFIG_STM32H7_TIM12_CH1IDLE, + .pol = CONFIG_STM32_TIM12_CH1POL, + .idle = CONFIG_STM32_TIM12_CH1IDLE, .pincfg = PWM_TIM12_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM12_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM12_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM12_CH2POL, - .idle = CONFIG_STM32H7_TIM12_CH2IDLE, + .pol = CONFIG_STM32_TIM12_CH2POL, + .idle = CONFIG_STM32_TIM12_CH2IDLE, .pincfg = PWM_TIM12_CH2CFG, } #endif @@ -1130,7 +1130,7 @@ static struct stm32_pwmchan_s g_pwm12channels[] = static struct stm32_pwmtimer_s g_pwm12dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 12, @@ -1149,24 +1149,24 @@ static struct stm32_pwmtimer_s g_pwm12dev = .base = STM32_TIM12_BASE, .pclk = TIMCLK_TIM12, }; -#endif /* CONFIG_STM32H7_TIM12_PWM */ +#endif /* CONFIG_STM32_TIM12_PWM */ -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM static struct stm32_pwmchan_s g_pwm13channels[] = { /* TIM13 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM13_CH1MODE, -#ifdef CONFIG_STM32H7_TIM13_CH1OUT + .mode = CONFIG_STM32_TIM13_CH1MODE, +#ifdef CONFIG_STM32_TIM13_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM13_CH1POL, - .idle = CONFIG_STM32H7_TIM13_CH1IDLE, + .pol = CONFIG_STM32_TIM13_CH1POL, + .idle = CONFIG_STM32_TIM13_CH1IDLE, .pincfg = PWM_TIM13_CH1CFG, } #endif @@ -1178,7 +1178,7 @@ static struct stm32_pwmchan_s g_pwm13channels[] = static struct stm32_pwmtimer_s g_pwm13dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 13, @@ -1197,24 +1197,24 @@ static struct stm32_pwmtimer_s g_pwm13dev = .base = STM32_TIM13_BASE, .pclk = TIMCLK_TIM13, }; -#endif /* CONFIG_STM32H7_TIM13_PWM */ +#endif /* CONFIG_STM32_TIM13_PWM */ -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM static struct stm32_pwmchan_s g_pwm14channels[] = { /* TIM14 has 1 channel */ -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM14_CH1MODE, -#ifdef CONFIG_STM32H7_TIM14_CH1OUT + .mode = CONFIG_STM32_TIM14_CH1MODE, +#ifdef CONFIG_STM32_TIM14_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM14_CH1POL, - .idle = CONFIG_STM32H7_TIM14_CH1IDLE, + .pol = CONFIG_STM32_TIM14_CH1POL, + .idle = CONFIG_STM32_TIM14_CH1IDLE, .pincfg = PWM_TIM14_CH1CFG, } #endif @@ -1226,7 +1226,7 @@ static struct stm32_pwmchan_s g_pwm14channels[] = static struct stm32_pwmtimer_s g_pwm14dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 14, @@ -1245,18 +1245,18 @@ static struct stm32_pwmtimer_s g_pwm14dev = .base = STM32_TIM14_BASE, .pclk = TIMCLK_TIM14, }; -#endif /* CONFIG_STM32H7_TIM14_PWM */ +#endif /* CONFIG_STM32_TIM14_PWM */ -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1267,36 +1267,36 @@ static struct stm32_pwmchan_s g_pwm15channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1POL, - .idle = CONFIG_STM32H7_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH1NPOL, - .idle = CONFIG_STM32H7_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32H7_TIM15_CH2MODE, -#ifdef CONFIG_STM32H7_TIM12_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM12_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM15_CH2POL, - .idle = CONFIG_STM32H7_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1308,7 +1308,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1316,10 +1316,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM15_LOCK, - .t_dts = CONFIG_STM32H7_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1327,18 +1327,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = TIMCLK_TIM15, }; -#endif /* CONFIG_STM32H7_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1349,16 +1349,16 @@ static struct stm32_pwmchan_s g_pwm16channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM16_CH1POL, - .idle = CONFIG_STM32H7_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, @@ -1374,7 +1374,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1382,10 +1382,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM16_LOCK, - .t_dts = CONFIG_STM32H7_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1393,18 +1393,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = TIMCLK_TIM16, }; -#endif /* CONFIG_STM32H7_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32H7_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1415,16 +1415,16 @@ static struct stm32_pwmchan_s g_pwm17channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32H7_TIM17_CH1POL, - .idle = CONFIG_STM32H7_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, @@ -1440,7 +1440,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1448,10 +1448,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32H7_TIM17_LOCK, - .t_dts = CONFIG_STM32H7_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32H7_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1459,7 +1459,7 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = TIMCLK_TIM17, }; -#endif /* CONFIG_STM32H7_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ /* TODO: support for TIM19,20,21,22 */ @@ -1796,7 +1796,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1853,7 +1853,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2581,7 +2581,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32H7_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3134,7 +3134,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCEN_TIM1; @@ -3143,7 +3143,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCEN_TIM2; @@ -3152,7 +3152,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCEN_TIM3; @@ -3161,7 +3161,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCEN_TIM4; @@ -3170,7 +3170,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCEN_TIM5; @@ -3179,7 +3179,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCEN_TIM8; @@ -3188,7 +3188,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCEN_TIM12; @@ -3197,7 +3197,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCEN_TIM13; @@ -3206,7 +3206,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCEN_TIM14; @@ -3215,7 +3215,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCEN_TIM15; @@ -3224,7 +3224,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCEN_TIM16; @@ -3233,7 +3233,7 @@ static int pwm_set_apb_clock(struct stm32_pwmtimer_s *priv, bool on) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCEN_TIM17; @@ -3531,7 +3531,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = TIMRCCRST_TIM1; @@ -3540,7 +3540,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = TIMRCCRST_TIM2; @@ -3549,7 +3549,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = TIMRCCRST_TIM3; @@ -3558,7 +3558,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = TIMRCCRST_TIM4; @@ -3567,7 +3567,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = TIMRCCRST_TIM5; @@ -3576,7 +3576,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = TIMRCCRST_TIM8; @@ -3585,7 +3585,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { regaddr = TIMRCCRST_TIM12; @@ -3594,7 +3594,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { regaddr = TIMRCCRST_TIM13; @@ -3603,7 +3603,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { regaddr = TIMRCCRST_TIM14; @@ -3612,7 +3612,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = TIMRCCRST_TIM15; @@ -3621,7 +3621,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = TIMRCCRST_TIM16; @@ -3630,7 +3630,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = TIMRCCRST_TIM17; @@ -3747,7 +3747,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { lower = &g_pwm1dev; @@ -3758,7 +3758,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { lower = &g_pwm2dev; @@ -3766,7 +3766,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { lower = &g_pwm3dev; @@ -3774,7 +3774,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { lower = &g_pwm4dev; @@ -3782,7 +3782,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { lower = &g_pwm5dev; @@ -3790,7 +3790,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { lower = &g_pwm8dev; @@ -3801,7 +3801,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM12_PWM +#ifdef CONFIG_STM32_TIM12_PWM case 12: { lower = &g_pwm12dev; @@ -3809,7 +3809,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM13_PWM +#ifdef CONFIG_STM32_TIM13_PWM case 13: { lower = &g_pwm13dev; @@ -3817,7 +3817,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM14_PWM +#ifdef CONFIG_STM32_TIM14_PWM case 14: { lower = &g_pwm14dev; @@ -3825,7 +3825,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { lower = &g_pwm15dev; @@ -3833,7 +3833,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { lower = &g_pwm16dev; @@ -3841,7 +3841,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) } #endif -#ifdef CONFIG_STM32H7_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { lower = &g_pwm17dev; @@ -3861,4 +3861,4 @@ errout: return (struct pwm_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ diff --git a/arch/arm/src/stm32h7/stm32_pwm.h b/arch/arm/src/stm32h7/stm32_pwm.h index bc6002af3bf..8cb724fca02 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.h +++ b/arch/arm/src/stm32h7/stm32_pwm.h @@ -39,7 +39,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM # include # include "hardware/stm32_tim.h" #endif @@ -57,41 +57,41 @@ * pulsed output signal generation. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32H7_TIM12 -# undef CONFIG_STM32H7_TIM12_PWM +#ifndef CONFIG_STM32_TIM12 +# undef CONFIG_STM32_TIM12_PWM #endif -#ifndef CONFIG_STM32H7_TIM13 -# undef CONFIG_STM32H7_TIM13_PWM +#ifndef CONFIG_STM32_TIM13 +# undef CONFIG_STM32_TIM13_PWM #endif -#ifndef CONFIG_STM32H7_TIM14 -# undef CONFIG_STM32H7_TIM14_PWM +#ifndef CONFIG_STM32_TIM14 +# undef CONFIG_STM32_TIM14_PWM #endif -#ifndef CONFIG_STM32H7_TIM15 -# undef CONFIG_STM32H7_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32H7_TIM16 -# undef CONFIG_STM32H7_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32H7_TIM17 -# undef CONFIG_STM32H7_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -103,38 +103,38 @@ /* Check if PWM support for any channel is enabled. */ -#ifdef CONFIG_STM32H7_PWM +#ifdef CONFIG_STM32_PWM /* PWM driver channels configuration */ -#ifdef CONFIG_STM32H7_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32H7_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 # define PWM_TIM1_CHANNEL1 1 #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 # define PWM_TIM1_CHANNEL2 1 #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 # define PWM_TIM1_CHANNEL3 1 #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 # define PWM_TIM1_CHANNEL4 1 #else # define PWM_TIM1_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 # define PWM_TIM1_CHANNEL5 1 #else # define PWM_TIM1_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 # define PWM_TIM1_CHANNEL6 1 #else # define PWM_TIM1_CHANNEL6 0 @@ -143,22 +143,22 @@ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4 + \ PWM_TIM1_CHANNEL5 + PWM_TIM1_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 # define PWM_TIM2_CHANNEL1 1 #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 # define PWM_TIM2_CHANNEL2 1 #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 # define PWM_TIM2_CHANNEL3 1 #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 # define PWM_TIM2_CHANNEL4 1 #else # define PWM_TIM2_CHANNEL4 0 @@ -166,22 +166,22 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 # define PWM_TIM3_CHANNEL1 1 #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 # define PWM_TIM3_CHANNEL2 1 #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 # define PWM_TIM3_CHANNEL3 1 #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 # define PWM_TIM3_CHANNEL4 1 #else # define PWM_TIM3_CHANNEL4 0 @@ -189,22 +189,22 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 # define PWM_TIM4_CHANNEL1 1 #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 # define PWM_TIM4_CHANNEL2 1 #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 # define PWM_TIM4_CHANNEL3 1 #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 # define PWM_TIM4_CHANNEL4 1 #else # define PWM_TIM4_CHANNEL4 0 @@ -212,22 +212,22 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 # define PWM_TIM5_CHANNEL1 1 #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 # define PWM_TIM5_CHANNEL2 1 #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 # define PWM_TIM5_CHANNEL3 1 #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 # define PWM_TIM5_CHANNEL4 1 #else # define PWM_TIM5_CHANNEL4 0 @@ -235,32 +235,32 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32H7_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 # define PWM_TIM8_CHANNEL1 1 #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 # define PWM_TIM8_CHANNEL2 1 #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 # define PWM_TIM8_CHANNEL3 1 #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 # define PWM_TIM8_CHANNEL4 1 #else # define PWM_TIM8_CHANNEL4 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 # define PWM_TIM8_CHANNEL5 1 #else # define PWM_TIM8_CHANNEL5 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 # define PWM_TIM8_CHANNEL6 1 #else # define PWM_TIM8_CHANNEL6 0 @@ -269,59 +269,59 @@ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4 + \ PWM_TIM8_CHANNEL5 + PWM_TIM8_CHANNEL6) -#ifdef CONFIG_STM32H7_TIM12_CHANNEL1 +#ifdef CONFIG_STM32_TIM12_CHANNEL1 # define PWM_TIM12_CHANNEL1 1 #else # define PWM_TIM12_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CHANNEL2 +#ifdef CONFIG_STM32_TIM12_CHANNEL2 # define PWM_TIM12_CHANNEL2 1 #else # define PWM_TIM12_CHANNEL2 0 #endif #define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM13_CHANNEL1 +#ifdef CONFIG_STM32_TIM13_CHANNEL1 # define PWM_TIM13_CHANNEL1 1 #else # define PWM_TIM13_CHANNEL1 0 #endif #define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM14_CHANNEL1 +#ifdef CONFIG_STM32_TIM14_CHANNEL1 # define PWM_TIM14_CHANNEL1 1 #else # define PWM_TIM14_CHANNEL1 0 #endif #define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1) -#ifdef CONFIG_STM32H7_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 # define PWM_TIM15_CHANNEL1 1 #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 # define PWM_TIM15_CHANNEL2 1 #else # define PWM_TIM15_CHANNEL2 0 #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32H7_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 # define PWM_TIM16_CHANNEL1 1 #else # define PWM_TIM16_CHANNEL1 0 #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32H7_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 # define PWM_TIM17_CHANNEL1 1 #else # define PWM_TIM17_CHANNEL1 0 #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#else /* !CONFIG_STM32H7_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: @@ -338,425 +338,425 @@ * is not supported by this driver: Only one output channel per timer. */ -#ifdef CONFIG_STM32H7_TIM1_PWM -# if !defined(CONFIG_STM32H7_TIM1_CHANNEL) -# error "CONFIG_STM32H7_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM1_CHANNEL == 1 -# define CONFIG_STM32H7_TIM1_CHANNEL1 1 -# define CONFIG_STM32H7_TIM1_CH1MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 2 -# define CONFIG_STM32H7_TIM1_CHANNEL2 1 -# define CONFIG_STM32H7_TIM1_CH2MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 3 -# define CONFIG_STM32H7_TIM1_CHANNEL3 1 -# define CONFIG_STM32H7_TIM1_CH3MODE CONFIG_STM32H7_TIM1_CHMODE -# elif CONFIG_STM32H7_TIM1_CHANNEL == 4 -# define CONFIG_STM32H7_TIM1_CHANNEL4 1 -# define CONFIG_STM32H7_TIM1_CH4MODE CONFIG_STM32H7_TIM1_CHMODE +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM2_PWM -# if !defined(CONFIG_STM32H7_TIM2_CHANNEL) -# error "CONFIG_STM32H7_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM2_CHANNEL == 1 -# define CONFIG_STM32H7_TIM2_CHANNEL1 1 -# define CONFIG_STM32H7_TIM2_CH1MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 2 -# define CONFIG_STM32H7_TIM2_CHANNEL2 1 -# define CONFIG_STM32H7_TIM2_CH2MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 3 -# define CONFIG_STM32H7_TIM2_CHANNEL3 1 -# define CONFIG_STM32H7_TIM2_CH3MODE CONFIG_STM32H7_TIM2_CHMODE -# elif CONFIG_STM32H7_TIM2_CHANNEL == 4 -# define CONFIG_STM32H7_TIM2_CHANNEL4 1 -# define CONFIG_STM32H7_TIM2_CH4MODE CONFIG_STM32H7_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM3_PWM -# if !defined(CONFIG_STM32H7_TIM3_CHANNEL) -# error "CONFIG_STM32H7_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM3_CHANNEL == 1 -# define CONFIG_STM32H7_TIM3_CHANNEL1 1 -# define CONFIG_STM32H7_TIM3_CH1MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 2 -# define CONFIG_STM32H7_TIM3_CHANNEL2 1 -# define CONFIG_STM32H7_TIM3_CH2MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 3 -# define CONFIG_STM32H7_TIM3_CHANNEL3 1 -# define CONFIG_STM32H7_TIM3_CH3MODE CONFIG_STM32H7_TIM3_CHMODE -# elif CONFIG_STM32H7_TIM3_CHANNEL == 4 -# define CONFIG_STM32H7_TIM3_CHANNEL4 1 -# define CONFIG_STM32H7_TIM3_CH4MODE CONFIG_STM32H7_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM4_PWM -# if !defined(CONFIG_STM32H7_TIM4_CHANNEL) -# error "CONFIG_STM32H7_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM4_CHANNEL == 1 -# define CONFIG_STM32H7_TIM4_CHANNEL1 1 -# define CONFIG_STM32H7_TIM4_CH1MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 2 -# define CONFIG_STM32H7_TIM4_CHANNEL2 1 -# define CONFIG_STM32H7_TIM4_CH2MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 3 -# define CONFIG_STM32H7_TIM4_CHANNEL3 1 -# define CONFIG_STM32H7_TIM4_CH3MODE CONFIG_STM32H7_TIM4_CHMODE -# elif CONFIG_STM32H7_TIM4_CHANNEL == 4 -# define CONFIG_STM32H7_TIM4_CHANNEL4 1 -# define CONFIG_STM32H7_TIM4_CH4MODE CONFIG_STM32H7_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM5_PWM -# if !defined(CONFIG_STM32H7_TIM5_CHANNEL) -# error "CONFIG_STM32H7_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM5_CHANNEL == 1 -# define CONFIG_STM32H7_TIM5_CHANNEL1 1 -# define CONFIG_STM32H7_TIM5_CH1MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 2 -# define CONFIG_STM32H7_TIM5_CHANNEL2 1 -# define CONFIG_STM32H7_TIM5_CH2MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 3 -# define CONFIG_STM32H7_TIM5_CHANNEL3 1 -# define CONFIG_STM32H7_TIM5_CH3MODE CONFIG_STM32H7_TIM5_CHMODE -# elif CONFIG_STM32H7_TIM5_CHANNEL == 4 -# define CONFIG_STM32H7_TIM5_CHANNEL4 1 -# define CONFIG_STM32H7_TIM5_CH4MODE CONFIG_STM32H7_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM8_PWM -# if !defined(CONFIG_STM32H7_TIM8_CHANNEL) -# error "CONFIG_STM32H7_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM8_CHANNEL == 1 -# define CONFIG_STM32H7_TIM8_CHANNEL1 1 -# define CONFIG_STM32H7_TIM8_CH1MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 2 -# define CONFIG_STM32H7_TIM8_CHANNEL2 1 -# define CONFIG_STM32H7_TIM8_CH2MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 3 -# define CONFIG_STM32H7_TIM8_CHANNEL3 1 -# define CONFIG_STM32H7_TIM8_CH3MODE CONFIG_STM32H7_TIM8_CHMODE -# elif CONFIG_STM32H7_TIM8_CHANNEL == 4 -# define CONFIG_STM32H7_TIM8_CHANNEL4 1 -# define CONFIG_STM32H7_TIM8_CH4MODE CONFIG_STM32H7_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM12_PWM -# if !defined(CONFIG_STM32H7_TIM12_CHANNEL) -# error "CONFIG_STM32H7_TIM12_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM12_CHANNEL == 1 -# define CONFIG_STM32H7_TIM12_CHANNEL1 1 -# define CONFIG_STM32H7_TIM12_CH1MODE CONFIG_STM32H7_TIM12_CHMODE -# elif CONFIG_STM32H7_TIM12_CHANNEL == 2 -# define CONFIG_STM32H7_TIM12_CHANNEL2 1 -# define CONFIG_STM32H7_TIM12_CH2MODE CONFIG_STM32H7_TIM12_CHMODE +#ifdef CONFIG_STM32_TIM12_PWM +# if !defined(CONFIG_STM32_TIM12_CHANNEL) +# error "CONFIG_STM32_TIM12_CHANNEL must be provided" +# elif CONFIG_STM32_TIM12_CHANNEL == 1 +# define CONFIG_STM32_TIM12_CHANNEL1 1 +# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE +# elif CONFIG_STM32_TIM12_CHANNEL == 2 +# define CONFIG_STM32_TIM12_CHANNEL2 1 +# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM12_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL" # endif # define PWM_TIM12_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM13_PWM -# if !defined(CONFIG_STM32H7_TIM13_CHANNEL) -# error "CONFIG_STM32H7_TIM13_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM13_CHANNEL == 1 -# define CONFIG_STM32H7_TIM13_CHANNEL1 1 -# define CONFIG_STM32H7_TIM13_CH1MODE CONFIG_STM32H7_TIM13_CHMODE +#ifdef CONFIG_STM32_TIM13_PWM +# if !defined(CONFIG_STM32_TIM13_CHANNEL) +# error "CONFIG_STM32_TIM13_CHANNEL must be provided" +# elif CONFIG_STM32_TIM13_CHANNEL == 1 +# define CONFIG_STM32_TIM13_CHANNEL1 1 +# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM13_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL" # endif # define PWM_TIM13_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM14_PWM -# if !defined(CONFIG_STM32H7_TIM14_CHANNEL) -# error "CONFIG_STM32H7_TIM14_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM14_CHANNEL == 1 -# define CONFIG_STM32H7_TIM14_CHANNEL1 1 -# define CONFIG_STM32H7_TIM14_CH1MODE CONFIG_STM32H7_TIM14_CHMODE +#ifdef CONFIG_STM32_TIM14_PWM +# if !defined(CONFIG_STM32_TIM14_CHANNEL) +# error "CONFIG_STM32_TIM14_CHANNEL must be provided" +# elif CONFIG_STM32_TIM14_CHANNEL == 1 +# define CONFIG_STM32_TIM14_CHANNEL1 1 +# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM14_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL" # endif # define PWM_TIM14_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM15_PWM -# if !defined(CONFIG_STM32H7_TIM15_CHANNEL) -# error "CONFIG_STM32H7_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM15_CHANNEL == 1 -# define CONFIG_STM32H7_TIM15_CHANNEL1 1 -# define CONFIG_STM32H7_TIM15_CH1MODE CONFIG_STM32H7_TIM15_CHMODE -# elif CONFIG_STM32H7_TIM15_CHANNEL == 2 -# define CONFIG_STM32H7_TIM15_CHANNEL2 1 -# define CONFIG_STM32H7_TIM15_CH2MODE CONFIG_STM32H7_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM16_PWM -# if !defined(CONFIG_STM32H7_TIM16_CHANNEL) -# error "CONFIG_STM32H7_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM16_CHANNEL == 1 -# define CONFIG_STM32H7_TIM16_CHANNEL1 1 -# define CONFIG_STM32H7_TIM16_CH1MODE CONFIG_STM32H7_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32H7_TIM17_PWM -# if !defined(CONFIG_STM32H7_TIM17_CHANNEL) -# error "CONFIG_STM32H7_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32H7_TIM17_CHANNEL == 1 -# define CONFIG_STM32H7_TIM17_CHANNEL1 1 -# define CONFIG_STM32H7_TIM17_CH1MODE CONFIG_STM32H7_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # else -# error "Unsupported value of CONFIG_STM32H7_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#endif /* CONFIG_STM32H7_PWM_MULTICHAN */ +#endif /* CONFIG_STM32_PWM_MULTICHAN */ -#ifdef CONFIG_STM32H7_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT #else # define PWM_TIM1_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT #else # define PWM_TIM1_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT #else # define PWM_TIM1_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT #else # define PWM_TIM1_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT #else # define PWM_TIM1_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT #else # define PWM_TIM1_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT #else # define PWM_TIM1_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT #else # define PWM_TIM2_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT #else # define PWM_TIM2_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT #else # define PWM_TIM2_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT #else # define PWM_TIM2_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT #else # define PWM_TIM3_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT #else # define PWM_TIM3_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT #else # define PWM_TIM3_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT #else # define PWM_TIM3_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT #else # define PWM_TIM4_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT #else # define PWM_TIM4_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT #else # define PWM_TIM4_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT #else # define PWM_TIM4_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT #else # define PWM_TIM5_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT #else # define PWM_TIM5_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT #else # define PWM_TIM5_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT #else # define PWM_TIM5_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT #else # define PWM_TIM8_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT #else # define PWM_TIM8_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT #else # define PWM_TIM8_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT #else # define PWM_TIM8_CH2NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT #else # define PWM_TIM8_CH3CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT #else # define PWM_TIM8_CH3NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT #else # define PWM_TIM8_CH4CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH1OUT +#ifdef CONFIG_STM32_TIM12_CH1OUT # define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT #else # define PWM_TIM12_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM12_CH2OUT +#ifdef CONFIG_STM32_TIM12_CH2OUT # define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT #else # define PWM_TIM12_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM13_CH1OUT +#ifdef CONFIG_STM32_TIM13_CH1OUT # define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT #else # define PWM_TIM13_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM14_CH1OUT +#ifdef CONFIG_STM32_TIM14_CH1OUT # define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT #else # define PWM_TIM14_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT #else # define PWM_TIM15_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT #else # define PWM_TIM15_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT #else # define PWM_TIM15_CH2CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT #else # define PWM_TIM16_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT #else # define PWM_TIM16_CH1NCFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT #else # define PWM_TIM17_CH1CFG 0 #endif -#ifdef CONFIG_STM32H7_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT #else # define PWM_TIM17_CH1NCFG 0 @@ -764,21 +764,21 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32H7_TIM1_CH1NOUT) || defined(CONFIG_STM32H7_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM8_CH1NOUT) || defined(CONFIG_STM32H7_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32H7_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32H7_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -789,7 +789,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: * low-level ops accept pwm_lowerhalf_s as first argument, but llops access @@ -925,7 +925,7 @@ enum stm32_pwm_output_e #endif }; -#ifdef CONFIG_STM32H7_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1011,7 +1011,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32H7_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1057,5 +1057,5 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_PWM */ +#endif /* CONFIG_STM32_PWM */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWM_H */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index c1d97009676..287ca4b42ea 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -37,7 +37,7 @@ #include "stm32_pwr.h" #include "stm32_gpio.h" -#if defined(CONFIG_STM32H7_PWR) +#if defined(CONFIG_STM32_PWR) #define BREG_WAIT_USTIMEOUT 1000 /* uS to wait for regulator to come ready */ diff --git a/arch/arm/src/stm32h7/stm32_qencoder.c b/arch/arm/src/stm32h7/stm32_qencoder.c index 406ec36796b..d3d29deb35c 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.c +++ b/arch/arm/src/stm32h7/stm32_qencoder.c @@ -60,14 +60,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32H7_TIM2_QE) || defined(CONFIG_STM32H7_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM3_QE) || \ - defined(CONFIG_STM32H7_TIM4_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -89,51 +89,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32H7_QENCODER_FILTER -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32H7_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -276,7 +276,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -287,7 +287,7 @@ static const struct stm32_qeconfig_s g_tim1config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM1EN, .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32H7_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -302,7 +302,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -313,7 +313,7 @@ static const struct stm32_qeconfig_s g_tim2config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM2EN, .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32H7_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -328,7 +328,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -339,7 +339,7 @@ static const struct stm32_qeconfig_s g_tim3config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM3EN, .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32H7_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -354,7 +354,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -365,7 +365,7 @@ static const struct stm32_qeconfig_s g_tim4config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM4EN, .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32H7_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -380,7 +380,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -391,7 +391,7 @@ static const struct stm32_qeconfig_s g_tim5config = .regaddr = STM32_RCC_APB1LENR, .enable = RCC_APB1LENR_TIM5EN, .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32H7_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -406,7 +406,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -417,7 +417,7 @@ static const struct stm32_qeconfig_s g_tim8config = .regaddr = STM32_RCC_APB2ENR, .enable = RCC_APB2ENR_TIM8EN, .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32H7_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -562,7 +562,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, stm32_getreg16(priv, STM32_GTIM_CCR2_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg16(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -593,27 +593,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -733,7 +733,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32H7_TIM1_QE) || defined(CONFIG_STM32H7_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -944,37 +944,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32H7_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM2RST; break; #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM3RST; break; #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM4RST; break; #endif -#ifdef CONFIG_STM32H7_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1LRSTR; resetbit = RCC_APB1LRSTR_TIM5RST; break; #endif -#ifdef CONFIG_STM32H7_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32h7/stm32_qencoder.h b/arch/arm/src/stm32h7/stm32_qencoder.h index a8b93505d59..0af33dc2c71 100644 --- a/arch/arm/src/stm32h7/stm32_qencoder.h +++ b/arch/arm/src/stm32h7/stm32_qencoder.h @@ -43,23 +43,23 @@ * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32H7_TIM1 -# undef CONFIG_STM32H7_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32H7_TIM2 -# undef CONFIG_STM32H7_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32H7_TIM3 -# undef CONFIG_STM32H7_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32H7_TIM4 -# undef CONFIG_STM32H7_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32H7_TIM5 -# undef CONFIG_STM32H7_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32H7_TIM8 -# undef CONFIG_STM32H7_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index c6f72058489..f09d07c0d57 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -57,7 +57,7 @@ #include "stm32_rcc.h" #include "hardware/stm32_qspi.h" -#ifdef CONFIG_STM32H7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -68,7 +68,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32H7_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -81,7 +81,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) && defined(CONFIG_STM32H7_QSPI_DMA) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -93,7 +93,7 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA # ifdef DMAMAP_QUADSPI @@ -105,26 +105,26 @@ # define DMACHAN_QUADSPI DMAMAP_QUADSPI # endif -# if defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_SCR_PRILO -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_SCR_PRIMED -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIHI -# elif defined(CONFIG_STM32H7_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_SCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_SCR_PRIMED # endif -#endif /* CONFIG_STM32H7_QSPI_DMA */ +#endif /* CONFIG_STM32_QSPI_DMA */ #ifndef STM32_SYSCLK_FREQUENCY # error your board.h needs to define the value of STM32_SYSCLK_FREQUENCY #endif -#if !defined(CONFIG_STM32H7_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32H7_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32H7_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -189,14 +189,14 @@ struct stm32h7_qspidev_s mutex_t lock; /* Assures mutually exclusive access to QSPI */ bool memmap; /* TRUE: Controller is in memory mapped mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* Interrupt number */ sem_t op_sem; /* Block until complete */ struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -206,11 +206,11 @@ struct stm32h7_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32h7_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -247,7 +247,7 @@ struct qspi_xctnspec_s uint8_t isddr; /* true if 'double data rate' */ uint8_t issioo; /* true if 'send instruction only once' mode */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS uint8_t function; /* functional mode; to distinguish a read or write */ int8_t disposition; /* how it all turned out */ uint32_t idxnow; /* index into databuffer of current byte in transfer */ @@ -260,7 +260,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -287,16 +287,16 @@ static void qspi_dumpgpioconfig(const char *msg); /* Interrupts */ -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS static int qspi0_interrupt(int irq, void *context, void *arg); #endif /* DMA support */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32H7_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32h7_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32h7_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); @@ -306,8 +306,8 @@ static void qspi_dma_sampledone(struct stm32h7_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32H7_QSPI_DMATHRESHOLD -# define CONFIG_STM32H7_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -361,13 +361,13 @@ static struct stm32h7_qspidev_s g_qspi0dev = }, .base = STM32_QUADSPI_BASE, .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS .handler = qspi0_interrupt, .irq = STM32_IRQ_QUADSPI, .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -393,7 +393,7 @@ static struct stm32h7_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32h7_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -445,7 +445,7 @@ static inline uint32_t qspi_getreg(struct stm32h7_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -468,7 +468,7 @@ static inline void qspi_putreg(struct stm32h7_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32H7_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -649,7 +649,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32H7_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -867,7 +867,7 @@ static int qspi_setupxctnfromcmd(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPICMD_ISWRITE(cmdinfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1010,7 +1010,7 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, xctn->isddr = 0; -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) xctn->function = QSPIMEM_ISWRITE(meminfo->flags) ? CCR_FMODE_INDWR : CCR_FMODE_INDRD; xctn->disposition = - EIO; @@ -1135,7 +1135,7 @@ static void qspi_ccrconfig(struct stm32h7_qspidev_s *priv, } } -#if defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi0_interrupt * @@ -1358,7 +1358,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -1631,7 +1631,7 @@ static int qspi_memory_dma(struct stm32h7_qspidev_s *priv, } #endif -#if !defined(CONFIG_STM32H7_QSPI_INTERRUPTS) +#if !defined(CONFIG_STM32_QSPI_INTERRUPTS) /**************************************************************************** * Name: qspi_receive_blocking * @@ -2065,7 +2065,7 @@ static int qspi_command(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2246,7 +2246,7 @@ static int qspi_memory(struct qspi_dev_s *dev, QSPI_FCR_CTEF | QSPI_FCR_CTCF | QSPI_FCR_CSMF | QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* interrupt mode will need access to the transaction context */ priv->xctn = &xctn; @@ -2307,11 +2307,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32H7_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32H7_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2473,18 +2473,18 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval &= ~(QSPI_CR_TEIE | QSPI_CR_TCIE | QSPI_CR_FTIE | QSPI_CR_SMIE | QSPI_CR_TOIE | QSPI_CR_FSEL | QSPI_CR_DFM); -#if defined(CONFIG_STM32H7_QSPI_MODE_BANK2) +#if defined(CONFIG_STM32_QSPI_MODE_BANK2) regval |= QSPI_CR_FSEL; #endif -#if defined(CONFIG_STM32H7_QSPI_MODE_DUAL) +#if defined(CONFIG_STM32_QSPI_MODE_DUAL) regval |= QSPI_CR_DFM; #endif /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32H7_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2505,10 +2505,10 @@ static int qspi_hw_initialize(struct stm32h7_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32H7_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32H7_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32H7_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while ((nsize & 0x80000000) == 0) @@ -2618,7 +2618,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization. */ -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2632,7 +2632,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) } #endif -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Attach the interrupt handler */ ret = irq_attach(priv->irq, priv->handler, NULL); @@ -2658,7 +2658,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) priv->initialized = true; priv->memmap = false; -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS up_enable_irq(priv->irq); #endif } @@ -2666,12 +2666,12 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) return &priv->qspi; errout_with_irq: -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS irq_detach(priv->irq); errout_with_dmach: #endif -#ifdef CONFIG_STM32H7_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2737,7 +2737,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_putreg(&g_qspi0dev, QSPI_FCR_CTOF, STM32_QUADSPI_FCR_OFFSET); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS /* Enable Timeout interrupt */ regval = qspi_getreg(priv, STM32_QUADSPI_CR_OFFSET); @@ -2756,7 +2756,7 @@ void stm32_qspi_enter_memorymapped(struct qspi_dev_s *dev, qspi_setupxctnfrommem(&xctn, meminfo); -#ifdef CONFIG_STM32H7_QSPI_INTERRUPTS +#ifdef CONFIG_STM32_QSPI_INTERRUPTS priv->xctn = NULL; #endif @@ -2802,4 +2802,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32h7/stm32_qspi.h b/arch/arm/src/stm32h7/stm32_qspi.h index dd2c257584c..096b3cdf257 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.h +++ b/arch/arm/src/stm32h7/stm32_qspi.h @@ -35,7 +35,7 @@ #include "chip.h" -#ifdef CONFIG_STM32H7_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -127,5 +127,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32H7_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_QSPI_H */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index 668be18c4dd..dcb7abdbe98 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -59,15 +59,15 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32H7_STM32H7X0XX) +#if defined(CONFIG_STM32_STM32H7X0XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X3XX) +#elif defined(CONFIG_STM32_STM32H7X3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7B3XX) +#elif defined(CONFIG_STM32_STM32H7B3XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X5XX) +#elif defined(CONFIG_STM32_STM32H7X5XX) # include "stm32h7x3xx_rcc.c" -#elif defined(CONFIG_STM32H7_STM32H7X7XX) +#elif defined(CONFIG_STM32_STM32H7X7XX) # include "stm32h7x7xx_rcc.c" #else # error "Unsupported STM32 H7 chip" @@ -86,9 +86,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -100,19 +100,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, void stm32_clockconfig(void) { -#ifndef CONFIG_STM32H7_BYPASS_CLOCKCONFIG +#ifndef CONFIG_STM32_BYPASS_CLOCKCONFIG /* Make sure that we are starting in the reset state */ rcc_reset(); -# if defined(CONFIG_STM32H7_PWR) +# if defined(CONFIG_STM32_PWR) /* Insure the bkp is initialized */ stm32_pwr_initbkp(false); # endif -# if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +# if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -127,13 +127,13 @@ void stm32_clockconfig(void) stm32_stdclockconfig(); # endif -#endif /* !CONFIG_STM32H7_BYPASS_CLOCKCONFIG */ +#endif /* !CONFIG_STM32_BYPASS_CLOCKCONFIG */ /* Enable peripheral clocking */ rcc_enableperipherals(); -#ifdef CONFIG_STM32H7_SYSCFG_IOCOMPENSATION +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION /* Enable I/O Compensation */ stm32_iocompensation(); @@ -153,9 +153,9 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -168,7 +168,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.h b/arch/arm/src/stm32h7/stm32_rcc.h index 786bb7064db..8dfaf0eb654 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.h +++ b/arch/arm/src/stm32h7/stm32_rcc.h @@ -124,9 +124,9 @@ static inline void stm32_mco2config(uint32_t source, uint32_t div) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None @@ -157,7 +157,7 @@ void stm32_stdclockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -174,9 +174,9 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_STM32H7_CUSTOM_CLOCKCONFIG is defined, then clocking will be - * enabled by an externally provided, board-specific function called - * stm32_board_clockconfig(). + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). * * Input Parameters: * None diff --git a/arch/arm/src/stm32h7/stm32_rng.c b/arch/arm/src/stm32h7/stm32_rng.c index 0e6e67df1c5..df53d7f7343 100644 --- a/arch/arm/src/stm32h7/stm32_rng.c +++ b/arch/arm/src/stm32h7/stm32_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32H7_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -311,4 +311,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32H7_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 648af00143d..c46354c4569 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -60,7 +60,7 @@ #define VRING_NR (8) /* Number of descriptors */ #define VRING_SIZE (512) /* Size of one descriptor */ -#ifdef CONFIG_STM32H7_SHMEM_SRAM3 +#ifdef CONFIG_STM32_SHMEM_SRAM3 /* Use 32kB of the SRAM3 as a shared memory */ # define VRING_SHMEM STM32_SRAM3_BASE diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index ed25043062d..4bfbe237a91 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -44,7 +44,7 @@ #include -#ifdef CONFIG_STM32H7_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -65,17 +65,17 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32H7_PWR -# error "CONFIG_STM32H7_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) # define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE #else # warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" @@ -491,7 +491,7 @@ static int rtc_setup(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* STMicro app note AN4759 suggests using 7999 and 124 to * get exactly 1MHz when using the RTC at 8MHz. */ @@ -940,17 +940,17 @@ int up_rtc_initialize(void) * external high rate clock */ -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Use the HSE clock as the input to the RTC block */ rtc_dumpregs("On reset HSE"); -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Use the LSI clock as the input to the RTC block */ rtc_dumpregs("On reset LSI"); -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) /* Use the LSE clock as the input to the RTC block */ rtc_dumpregs("On reset LSE"); @@ -1102,7 +1102,7 @@ int up_rtc_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) #else int up_rtc_getdatetime(struct tm *tp) @@ -1111,7 +1111,7 @@ int up_rtc_getdatetime(struct tm *tp) uint32_t dr; uint32_t tr; uint32_t tmp; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; uint32_t prediv_s; uint32_t usecs; @@ -1129,7 +1129,7 @@ int up_rtc_getdatetime(struct tm *tp) { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1186,7 +1186,7 @@ int up_rtc_getdatetime(struct tm *tp) clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); tp->tm_isdst = 0; -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS /* Return RTC sub-seconds if a non-NULL value * of nsec has been provided to receive the sub-second value. */ @@ -1207,7 +1207,7 @@ int up_rtc_getdatetime(struct tm *tp) } rtc_dumptime((const struct tm *)tp, &usecs, "Returning"); -#else /* CONFIG_STM32H7_HAVE_RTC_SUBSECONDS */ +#else /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ rtc_dumptime((const struct tm *)tp, NULL, "Returning"); #endif @@ -1237,7 +1237,7 @@ int up_rtc_getdatetime(struct tm *tp) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(struct tm *tp) { return stm32_rtc_getdatetime_with_subseconds(tp, NULL); @@ -1270,8 +1270,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32H7_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1775,11 +1775,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32H7_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32H7_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32H7_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1950,4 +1950,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32H7_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32h7/stm32_rtc.h b/arch/arm/src/stm32h7/stm32_rtc.h index e3b3f69096c..82290558797 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.h +++ b/arch/arm/src/stm32h7/stm32_rtc.h @@ -46,21 +46,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32H7_RTC_MAGIC) -# define CONFIG_STM32H7_RTC_MAGIC (0xfacefeed) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeed) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32H7_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32H7_RTC_MAGIC_REG) -# define CONFIG_STM32H7_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32H7_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32H7_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32H7_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -106,7 +106,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index cfddcb3be49..2aca3035cd2 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -56,7 +56,7 @@ #include "stm32_rcc.h" #include "stm32_sdmmc.h" -#if defined(CONFIG_STM32H7_SDMMC1) || defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -101,14 +101,14 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32H7_SDMMC_IDMA - Enable SDMMC IDMA. + * CONFIG_STM32_SDMMC_IDMA - Enable SDMMC IDMA. * DMA support for SDMMC. If disabled, the SDMMC will work in * interrupt mode and still use the IDMA to a local buffer for data * lengths less the 32 bytes due to the FIFO limitations. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_STM32H7_SDMMC_XFRDEBUG - Enables some very low-level debug + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level debug * output This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO * CONFIG_SDMMC1/2_SDIO_MODE * Build ins additional support needed only for SDIO cards (vs. SD memory @@ -125,15 +125,15 @@ * hence, if only SDMMC2 is defined it will be slot 0. */ -#if !defined(CONFIG_STM32H7_SDMMC1) +#if !defined(CONFIG_STM32_SDMMC1) # define SDMMC2_SLOT 0 #else # define SDMMC2_SLOT 1 #endif -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) # warning "Large Non-DMA transfer may result in RX overrun failures" -#elif defined(CONFIG_STM32H7_SDMMC1) +#elif defined(CONFIG_STM32_SDMMC1) # define SRAM123_START STM32_SRAM123_BASE # define SRAM123_END (SRAM123_START + STM32_SRAM123_SIZE) # define SRAM4_START STM32_SRAM4_BASE @@ -150,7 +150,7 @@ #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32H7_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif #ifdef CONFIG_SDMMC1_SDIO_PULLUP @@ -316,7 +316,7 @@ /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_AFTER_SETUP 1 # define SAMPLENDX_END_TRANSFER 2 @@ -381,7 +381,7 @@ struct stm32_dev_s uint32_t blocksize; /* Current block size */ uint32_t receivecnt; /* Real count to receive */ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) struct work_s cbfifo; /* Monitor for Lame FIFO */ #endif uint8_t rxfifo[FIFO_SIZE_IN_BYTES] /* To offload with IDMA and support un-alinged buffers */ @@ -389,7 +389,7 @@ struct stm32_dev_s bool unaligned_rx; /* read buffer is not cache-line or 32 bit aligned */ /* Input dma buffer for unaligned transfers */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) uint8_t sdmmc_rxbuffer[SDMMC_MAX_BLOCK_SIZE] aligned_data(ARMV7M_DCACHE_LINESIZE); #endif @@ -397,7 +397,7 @@ struct stm32_dev_s /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) struct stm32_sdioregs_s { uint8_t power; @@ -434,7 +434,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* Debug Helpers ************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -456,7 +456,7 @@ static uint8_t stm32_log2(uint16_t value); static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, uint32_t dlen, bool receive); static void stm32_datadisable(struct stm32_dev_s *priv); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv); #else @@ -499,7 +499,7 @@ static int stm32_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg); static void stm32_blocksetup(struct sdio_dev_s *dev, unsigned int blocksize, unsigned int nblocks); -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes); static int stm32_sendsetup(struct sdio_dev_s *dev, @@ -527,7 +527,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -546,7 +546,7 @@ static void stm32_default(struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -562,7 +562,7 @@ struct stm32_dev_s g_sdmmcdev1 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -582,7 +582,7 @@ struct stm32_dev_s g_sdmmcdev1 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -601,7 +601,7 @@ struct stm32_dev_s g_sdmmcdev1 = #endif }; #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -617,7 +617,7 @@ struct stm32_dev_s g_sdmmcdev2 = .attach = stm32_attach, .sendcmd = stm32_sendcmd, .blocksetup = stm32_blocksetup, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) .recvsetup = stm32_dmarecvsetup, .sendsetup = stm32_dmasendsetup, #else @@ -637,7 +637,7 @@ struct stm32_dev_s g_sdmmcdev2 = .eventwait = stm32_eventwait, .callbackenable = stm32_callbackenable, .registercallback = stm32_registercallback, -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) # if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) .dmapreflight = stm32_dmapreflight, # endif @@ -658,7 +658,7 @@ struct stm32_dev_s g_sdmmcdev2 = #endif /* Register logging support */ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -899,7 +899,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * @@ -915,7 +915,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -938,7 +938,7 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; @@ -954,7 +954,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -985,7 +985,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) @@ -1002,7 +1002,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_XFRDEBUG) +#if defined(CONFIG_STM32_SDMMC_XFRDEBUG) static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], @@ -1104,7 +1104,7 @@ static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, { DEBUGASSERT((dlen % priv->blocksize) == 0); -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) /* If this is an unaligned receive, then receive one block at a * time to the internal buffer */ @@ -1202,7 +1202,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sendfifo(struct stm32_dev_s *priv) { union @@ -1267,7 +1267,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_recvfifo(struct stm32_dev_s *priv) { union @@ -1328,7 +1328,7 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * ****************************************************************************/ -#if defined (CONFIG_STM32H7_SDMMC_IDMA) +#if defined (CONFIG_STM32_SDMMC_IDMA) static void stm32_recvdma(struct stm32_dev_s *priv) { uint32_t dctrl; @@ -1547,7 +1547,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SDMMC_IDMA) +#if !defined(CONFIG_STM32_SDMMC_IDMA) static void stm32_sdmmc_fifo_monitor(void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1643,7 +1643,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* Is the RX FIFO half full or more? Is so then we must be * processing a receive transaction. */ @@ -1689,7 +1689,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) * half-full interrupt will be received. */ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA /* If the transfer would not trigger fifo half full * we used IDMA to manage the lame fifo @@ -1909,7 +1909,7 @@ static void stm32_reset(struct sdio_dev_s *dev) flags = enter_critical_section(); -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { regaddress = STM32_RCC_AHB3RSTR; @@ -1917,7 +1917,7 @@ static void stm32_reset(struct sdio_dev_s *dev) } #endif -#if defined CONFIG_STM32H7_SDMMC2 +#if defined CONFIG_STM32_SDMMC2 if (priv->base == STM32_SDMMC2_BASE) { regaddress = STM32_RCC_AHB2RSTR; @@ -1998,7 +1998,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_DMABEFOREWRITE; -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2305,7 +2305,7 @@ static void stm32_blocksetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t nbytes) { @@ -2381,7 +2381,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, * ****************************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC_IDMA +#ifndef CONFIG_STM32_SDMMC_IDMA static int stm32_sendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t nbytes) { @@ -3065,7 +3065,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_IDMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3074,7 +3074,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, /* IDMA must be possible to the buffer */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (priv->base == STM32_SDMMC1_BASE) { /* For SDMMC1, IDMA cannot access SRAM123 or SRAM4. */ @@ -3134,7 +3134,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -3239,7 +3239,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#if defined(CONFIG_STM32H7_SDMMC_IDMA) +#if defined(CONFIG_STM32_SDMMC_IDMA) static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3423,7 +3423,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) if (slotno == 0) { /* Select SDMMC 1 */ @@ -3456,7 +3456,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#if defined(CONFIG_STM32H7_SDMMC2) +#if defined(CONFIG_STM32_SDMMC2) if (slotno == SDMMC2_SLOT) { /* Select SDMMC 2 */ @@ -3629,4 +3629,4 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, } #endif -#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index e7442fe452c..cf668117e80 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -81,11 +81,11 @@ # if !defined(DMAMAP_USART1_RX) # error "USART1 DMA map not defined (DMAMAP_USART1_RX)" # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -93,11 +93,11 @@ # if !defined(DMAMAP_USART2_RX) # error "USART2 DMA map not defined (DMAMAP_USART2_RX)" # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -105,11 +105,11 @@ # if !defined(DMAMAP_USART3_RX) # error "USART3 DMA map not defined (DMAMAP_USART3_RX)" # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -117,11 +117,11 @@ # if !defined(DMAMAP_UART4_RX) # error "UART4 DMA map not defined (DMAMAP_UART4_RX)" # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -129,11 +129,11 @@ # if !defined(DMAMAP_UART5_RX) # error "UART5 DMA map not defined (DMAMAP_UART5_RX)" # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -141,11 +141,11 @@ # if !defined(DMAMAP_USART6_RX) # error "USART6 DMA map not defined (DMAMAP_USART6_RX)" # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -153,11 +153,11 @@ # if !defined(DMAMAP_UART7_RX) # error "UART7 DMA map not defined (DMAMAP_UART7_RX)" # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -165,11 +165,11 @@ # if !defined(DMAMAP_UART8_RX) # error "UART8 DMA map not defined (DMAMAP_UART8_RX)" # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -205,14 +205,14 @@ # define ARMV7M_DCACHE_LINESIZE 32 # endif -# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \ - (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) -# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE -# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE) +# undef CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE # endif # define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* DMA priority */ @@ -247,11 +247,11 @@ # if !defined(DMAMAP_USART1_TX) # error "USART1 DMA map not defined (DMAMAP_USART1_TX)" # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -259,11 +259,11 @@ # if !defined(DMAMAP_USART2_TX) # error "USART2 DMA map not defined (DMAMAP_USART2_TX)" # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -271,11 +271,11 @@ # if !defined(DMAMAP_USART3_TX) # error "USART3 DMA map not defined (DMAMAP_USART3_TX)" # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -283,11 +283,11 @@ # if !defined(DMAMAP_UART4_TX) # error "UART4 DMA map not defined (DMAMAP_UART4_TX)" # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -295,11 +295,11 @@ # if !defined(DMAMAP_UART5_TX) # error "UART5 DMA map not defined (DMAMAP_UART5_TX)" # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -307,11 +307,11 @@ # if !defined(DMAMAP_USART6_TX) # error "USART6 DMA map not defined (DMAMAP_USART6_TX)" # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -319,11 +319,11 @@ # if !defined(DMAMAP_UART7_TX) # error "UART7 DMA map not defined (DMAMAP_UART7_TX)" # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -331,11 +331,11 @@ # if !defined(DMAMAP_UART8_TX) # error "UART8 DMA map not defined (DMAMAP_UART8_TX)" # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32_DMA1) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32_DMA1 # endif -# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2) -# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2 +# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32_DMA2) +# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32_DMA2 # endif # endif #endif @@ -371,7 +371,7 @@ #endif #define TXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1) -#define TXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \ +#define TXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE \ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) /* If built with CONFIG_ARMV7M_DCACHE Buffers need to be aligned and @@ -475,8 +475,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32H7_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32H7_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # warning stm32h7 serial power managemnt was taken from stm32f7 and is untested! @@ -501,7 +501,7 @@ * See up_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -511,13 +511,13 @@ /* Warnings for potentially unsafe configuration combinations. */ -#if defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) && \ +#if defined(CONFIG_STM32_FLOWCONTROL_BROKEN) && \ !defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) -# error "CONFIG_STM32H7_FLOWCONTROL_BROKEN requires \ +# error "CONFIG_STM32_FLOWCONTROL_BROKEN requires \ CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS to be enabled." #endif -#ifndef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifndef CONFIG_STM32_FLOWCONTROL_BROKEN /* Combination of RXDMA + IFLOWCONTROL does not work as one might expect. * Since RXDMA uses circular DMA-buffer, DMA will always keep reading new * data from USART peripheral even if DMA buffer underruns. Thus this @@ -560,7 +560,7 @@ # warning "RXDMA and IFLOWCONTROL both enabled for UART8. \ This combination can lead to data loss." # endif -#endif /* CONFIG_STM32H7_FLOWCONTROL_BROKEN */ +#endif /* CONFIG_STM32_FLOWCONTROL_BROKEN */ /**************************************************************************** * Private Types @@ -868,49 +868,49 @@ static char g_uart8rxfifo[RXDMA_BUFFER_SIZE] /* Receive/Transmit buffers */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[USART1_TXBUFSIZE_ADJUSTED] \ USART1_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[USART2_TXBUFSIZE_ADJUSTED] \ USART2_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[USART3_TXBUFSIZE_ADJUSTED] \ USART3_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[UART4_TXBUFSIZE_ADJUSTED] \ UART4_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[UART5_TXBUFSIZE_ADJUSTED] \ UART5_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static char g_usart6rxbuffer[CONFIG_USART6_RXBUFSIZE]; static char g_usart6txbuffer[USART6_TXBUFSIZE_ADJUSTED] \ USART6_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; static char g_uart7txbuffer[UART7_TXBUFSIZE_ADJUSTED] \ UART7_TXBUFSIZE_ALGN; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static char g_uart8rxbuffer[CONFIG_UART8_RXBUFSIZE]; static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ UART8_TXBUFSIZE_ALGN; @@ -918,7 +918,7 @@ static char g_uart8txbuffer[UART8_TXBUFSIZE_ADJUSTED] \ /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 static struct up_dev_s g_usart1priv = { .dev = @@ -988,7 +988,7 @@ static struct up_dev_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 static struct up_dev_s g_usart2priv = { .dev = @@ -1058,7 +1058,7 @@ static struct up_dev_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 static struct up_dev_s g_usart3priv = { .dev = @@ -1128,7 +1128,7 @@ static struct up_dev_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 static struct up_dev_s g_uart4priv = { .dev = @@ -1198,7 +1198,7 @@ static struct up_dev_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 static struct up_dev_s g_uart5priv = { .dev = @@ -1268,7 +1268,7 @@ static struct up_dev_s g_uart5priv = /* This describes the state of the STM32 USART6 port. */ -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 static struct up_dev_s g_usart6priv = { .dev = @@ -1338,7 +1338,7 @@ static struct up_dev_s g_usart6priv = /* This describes the state of the STM32 UART7 port. */ -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 static struct up_dev_s g_uart7priv = { .dev = @@ -1408,7 +1408,7 @@ static struct up_dev_s g_uart7priv = /* This describes the state of the STM32 UART8 port. */ -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 static struct up_dev_s g_uart8priv = { .dev = @@ -1480,28 +1480,28 @@ static struct up_dev_s g_uart8priv = static struct up_dev_s * const g_uart_devs[STM32_NSERIAL] = { -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 [0] = &g_usart1priv, #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 [1] = &g_usart2priv, #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 [2] = &g_usart3priv, #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 [3] = &g_uart4priv, #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 [4] = &g_uart5priv, #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 [5] = &g_usart6priv, #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 [6] = &g_uart7priv, #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 [7] = &g_uart8priv, #endif }; @@ -1797,7 +1797,7 @@ static void up_set_format(struct uart_dev_s *dev) regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); #if defined(CONFIG_SERIAL_IFLOWCONTROL) && \ - !defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1990,49 +1990,49 @@ static void up_set_apb_clock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_USART2 +#ifdef CONFIG_STM32_USART2 case STM32_USART2_BASE: rcc_en = RCC_APB1LENR_USART2EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART3 +#ifdef CONFIG_STM32_USART3 case STM32_USART3_BASE: rcc_en = RCC_APB1LENR_USART3EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART4 +#ifdef CONFIG_STM32_UART4 case STM32_UART4_BASE: rcc_en = RCC_APB1LENR_UART4EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART5 +#ifdef CONFIG_STM32_UART5 case STM32_UART5_BASE: rcc_en = RCC_APB1LENR_UART5EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 case STM32_USART6_BASE: rcc_en = RCC_APB2ENR_USART6EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32H7_UART7 +#ifdef CONFIG_STM32_UART7 case STM32_UART7_BASE: rcc_en = RCC_APB1LENR_UART7EN; regaddr = STM32_RCC_APB1LENR; break; #endif -#ifdef CONFIG_STM32H7_UART8 +#ifdef CONFIG_STM32_UART8 case STM32_UART8_BASE: rcc_en = RCC_APB1LENR_UART8EN; regaddr = STM32_RCC_APB1LENR; @@ -2104,7 +2104,7 @@ static int up_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32H7_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -2477,8 +2477,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32H7_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32H7_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Get the masked USART status word. */ @@ -2592,14 +2592,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif #if defined(CONFIG_SERIAL_TERMIOS) \ - || defined(CONFIG_STM32H7_USART_SINGLEWIRE) \ - || defined(CONFIG_STM32H7_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_USART_SINGLEWIRE) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; @@ -2622,7 +2622,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2689,7 +2689,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2740,7 +2740,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif -#ifdef CONFIG_STM32H7_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2877,8 +2877,8 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg) break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32H7_USART_BREAKS -# ifdef CONFIG_STM32H7_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -3088,7 +3088,7 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev, struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32H7_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -3911,7 +3911,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3940,7 +3940,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32H7_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32h7/stm32_spi.c b/arch/arm/src/stm32h7/stm32_spi.c index 329abb73f25..7ca1e810308 100644 --- a/arch/arm/src/stm32h7/stm32_spi.c +++ b/arch/arm/src/stm32h7/stm32_spi.c @@ -75,9 +75,9 @@ #include "stm32_spi.h" #include "stm32_dma.h" -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI5) || defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI5) || defined(CONFIG_STM32_SPI6) /**************************************************************************** * Pre-processor Definitions @@ -87,19 +87,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,39 +137,39 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI1_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI2_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI3_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI4_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI4_DMA_BUFFER > 0 -# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI4_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI4_DMA_BUFFER) && \ + CONFIG_STM32_SPI4_DMA_BUFFER > 0 +# define SPI4_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI4_DMA_BUFFER) # define SPI4_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32H7_SPI5_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI5_DMA_BUFFER > 0 -# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI5_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI5_DMA_BUFFER) && \ + CONFIG_STM32_SPI5_DMA_BUFFER > 0 +# define SPI5_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI5_DMA_BUFFER) # define SPI5_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -#if defined(CONFIG_STM32H7_SPI6_DMA_BUFFER) && \ - CONFIG_STM32H7_SPI6_DMA_BUFFER > 0 -# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32H7_SPI6_DMA_BUFFER) +#if defined(CONFIG_STM32_SPI6_DMA_BUFFER) && \ + CONFIG_STM32_SPI6_DMA_BUFFER > 0 +# define SPI6_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI6_DMA_BUFFER) # define SPI6_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -180,8 +180,8 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) # if STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL1 # define SPI123_KERNEL_CLOCK_FREQ STM32_PLL1Q_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI123SRC == RCC_D2CCIP1R_SPI123SEL_PLL2 @@ -194,7 +194,7 @@ # endif #endif /* SPI123 */ -#if defined(CONFIG_STM32H7_SPI4) || defined(CONFIG_STM32H7_SPI5) +#if defined(CONFIG_STM32_SPI4) || defined(CONFIG_STM32_SPI5) # if STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_APB # define SPI45_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY # elif STM32_RCC_D2CCIP1R_SPI45SRC == RCC_D2CCIP1R_SPI45SEL_PLL2 @@ -207,7 +207,7 @@ # endif #endif /* SPI45 */ -#if defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI6) # if STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PCLK4 # define SPI6_KERNEL_CLOCK_FREQ STM32_PCLK4_FREQUENCY # elif STM32_RCC_D3CCIPR_SPI6SRC == RCC_D3CCIPR_SPI6SEL_PLL2 @@ -238,7 +238,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -288,7 +288,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -354,7 +354,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -403,7 +403,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32H7_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -418,15 +418,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI1_COMMTYPE - .config = CONFIG_STM32H7_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -475,7 +475,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32H7_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -490,15 +490,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI2_COMMTYPE - .config = CONFIG_STM32H7_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -547,7 +547,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI123_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32H7_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -562,15 +562,15 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI3_COMMTYPE - .config = CONFIG_STM32H7_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 static const struct spi_ops_s g_sp4iops = { .lock = spi_lock, @@ -619,7 +619,7 @@ static struct stm32_spidev_s g_spi4dev = .spibase = STM32_SPI4_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI4, -#ifdef CONFIG_STM32H7_SPI4_DMA +#ifdef CONFIG_STM32_SPI4_DMA .rxch = DMAMAP_SPI4_RX, .txch = DMAMAP_SPI4_TX, # if defined(SPI4_DMABUFSIZE_ADJUSTED) @@ -634,15 +634,15 @@ static struct stm32_spidev_s g_spi4dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI4_COMMTYPE - .config = CONFIG_STM32H7_SPI4_COMMTYPE, +#ifdef CONFIG_STM32_SPI4_COMMTYPE + .config = CONFIG_STM32_SPI4_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 static const struct spi_ops_s g_sp5iops = { .lock = spi_lock, @@ -691,7 +691,7 @@ static struct stm32_spidev_s g_spi5dev = .spibase = STM32_SPI5_BASE, .spiclock = SPI45_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI5, -#ifdef CONFIG_STM32H7_SPI5_DMA +#ifdef CONFIG_STM32_SPI5_DMA .rxch = DMAMAP_SPI5_RX, .txch = DMAMAP_SPI5_TX, # if defined(SPI5_DMABUFSIZE_ADJUSTED) @@ -706,15 +706,15 @@ static struct stm32_spidev_s g_spi5dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI5_COMMTYPE - .config = CONFIG_STM32H7_SPI5_COMMTYPE, +#ifdef CONFIG_STM32_SPI5_COMMTYPE + .config = CONFIG_STM32_SPI5_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI5 */ +#endif /* CONFIG_STM32_SPI5 */ -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 static const struct spi_ops_s g_sp6iops = { .lock = spi_lock, @@ -764,7 +764,7 @@ static struct stm32_spidev_s g_spi6dev = .spibase = STM32_SPI6_BASE, .spiclock = SPI6_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI6, -#ifdef CONFIG_STM32H7_SPI6_DMA +#ifdef CONFIG_STM32_SPI6_DMA .rxch = DMAMAP_SPI6_RX, .txch = DMAMAP_SPI6_TX, # if defined(SPI6_DMABUFSIZE_ADJUSTED) @@ -779,13 +779,13 @@ static struct stm32_spidev_s g_spi6dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32H7_SPI6_COMMTYPE - .config = CONFIG_STM32H7_SPI6_COMMTYPE, +#ifdef CONFIG_STM32_SPI6_COMMTYPE + .config = CONFIG_STM32_SPI6_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32H7_SPI6 */ +#endif /* CONFIG_STM32_SPI6 */ /**************************************************************************** * Private Functions @@ -1107,7 +1107,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -1124,7 +1124,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -1164,7 +1164,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -1213,7 +1213,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -1228,7 +1228,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -1248,7 +1248,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1310,7 +1310,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1370,7 +1370,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1394,7 +1394,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1929,9 +1929,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32H7_SPI_DMA) || defined(CONFIG_STM32H7_DMACAPABLE) || \ - defined(CONFIG_STM32H7_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32H7_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -2020,8 +2020,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32H7_SPI_DMA || CONFIG_STM32H7_DMACAPABLE || - * CONFIG_STM32H7_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -2045,7 +2045,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -2063,12 +2063,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32H7_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32H7_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -2132,7 +2132,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32H7_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -2264,7 +2264,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32H7_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2285,7 +2285,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2519,7 +2519,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2601,7 +2601,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2626,7 +2626,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2651,7 +2651,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2676,7 +2676,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 if (bus == 4) { /* Select SPI4 */ @@ -2701,7 +2701,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 if (bus == 5) { /* Select SPI5 */ @@ -2726,7 +2726,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 if (bus == 6) { /* Select SPI6 */ @@ -2759,6 +2759,6 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1 || CONFIG_STM32H7_SPI2 || CONFIG_STM32H7_SPI3 || - * CONFIG_STM32H7_SPI4 || CONFIG_STM32H7_SPI5 || CONFIG_STM32H7_SPI6 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 || + * CONFIG_STM32_SPI4 || CONFIG_STM32_SPI5 || CONFIG_STM32_SPI6 */ diff --git a/arch/arm/src/stm32h7/stm32_spi.h b/arch/arm/src/stm32h7/stm32_spi.h index a9b0532e075..663a2eac486 100644 --- a/arch/arm/src/stm32h7/stm32_spi.h +++ b/arch/arm/src/stm32h7/stm32_spi.h @@ -114,42 +114,42 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid); @@ -177,32 +177,32 @@ int stm32_spi6cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32h7/stm32_spi_slave.c b/arch/arm/src/stm32h7/stm32_spi_slave.c index efa9fc56411..83499c4d8ef 100644 --- a/arch/arm/src/stm32h7/stm32_spi_slave.c +++ b/arch/arm/src/stm32h7/stm32_spi_slave.c @@ -67,19 +67,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32H7_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32H7_SPI_INTERRUPTS) && defined(CONFIG_STM32H7_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -187,7 +187,7 @@ struct stm32_spidev_s uint32_t spiclock; /* Clocking for the SPI module */ uint8_t irq; /* SPI IRQ number */ uint32_t nss_pin; /* Chip select pin configuration */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the TX DMA */ uint32_t rxch; /* The RX DMA channel number */ @@ -221,7 +221,7 @@ struct stm32_spidev_s /* Input queue */ uint16_t ihead; /* Location of next unread value */ -#ifndef CONFIG_STM32H7_SPI_DMA +#ifndef CONFIG_STM32_SPI_DMA uint16_t itail; /* Index of next free memory pointer */ #endif uint8_t *inq; @@ -250,7 +250,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg); static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, @@ -311,7 +311,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = #define SPI_SLAVE_OUTQ(x) spi##x##_outq #define SPI_SLAVE_INQ(x) spi##x##_inq -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #define SPI_SLAVE_INIT_DMA(x) \ .rxch = DMAMAP_SPI##x##_RX, \ .txch = DMAMAP_SPI##x##_TX, \ @@ -340,7 +340,7 @@ static const struct spi_slave_ctrlrops_s g_ctrlr_ops = .initialized = false, \ .lock = NXMUTEX_INITIALIZER, \ SPI_SLAVE_INIT_PM_PREPARE \ - .config = CONFIG_STM32H7_SPI##x##_COMMTYPE, \ + .config = CONFIG_STM32_SPI##x##_COMMTYPE, \ } #ifdef CONFIG_STM32H7_SPI1_SLAVE @@ -706,7 +706,7 @@ static inline bool spi_9to16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -726,7 +726,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -746,7 +746,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) { stm32_dmacfg_t dmacfg; @@ -795,7 +795,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) { /* TODO: set up dma to transfer out the new data from priv->outq, @@ -850,7 +850,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, size_t nwords) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -875,7 +875,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1223,7 +1223,7 @@ static int spi_nssinterrupt(int irq, void *context, void *arg) spi_enable(priv, false); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Setup DMAs */ @@ -1363,7 +1363,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return; @@ -1377,7 +1377,7 @@ static void spi_qflush(struct spi_slave_ctrlr_s *ctrlr) /* Flush the input buffers */ -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->ihead = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else @@ -1454,7 +1454,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) DEBUGASSERT(priv != NULL && priv->dev != NULL); DEBUGASSERT(priv->ihead < CONFIG_STM32H7_SPI_SLAVE_QSIZE); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (!priv->dmarunning) { return 0; @@ -1465,7 +1465,7 @@ static size_t spi_qpoll(struct spi_slave_ctrlr_s *ctrlr) spi_lock(ctrlr, true); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA itail = CONFIG_STM32H7_SPI_SLAVE_QSIZE - stm32_dmaresidual(priv->rxdma); #else #error Support only simplex mode rx with dma @@ -1657,7 +1657,7 @@ static void spi_slave_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32H7_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* DMA will be started in the interrupt handler, synchronized to the master * nss */ @@ -1796,4 +1796,4 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus) return (struct spi_slave_ctrlr_s *)priv; } -#endif /* CONFIG_STM32H7_SPI1..6_SLAVE */ +#endif /* CONFIG_STM32_SPI1..6_SLAVE */ diff --git a/arch/arm/src/stm32h7/stm32_start.c b/arch/arm/src/stm32h7/stm32_start.c index 70c7d4ade3f..fa55412dc06 100644 --- a/arch/arm/src/stm32h7/stm32_start.c +++ b/arch/arm/src/stm32h7/stm32_start.c @@ -305,7 +305,7 @@ void __start(void) #if defined(CONFIG_ARCH_STM32H7_DUALCORE) && \ defined(CONFIG_ARCH_CHIP_STM32H7_CORTEXM7) && \ - defined(CONFIG_STM32H7_CORTEXM4_ENABLED) + defined(CONFIG_STM32_CORTEXM4_ENABLED) /* Start CM4 core after clock configuration is done */ diff --git a/arch/arm/src/stm32h7/stm32_tickless.c b/arch/arm/src/stm32h7/stm32_tickless.c index 1de1d5abf73..7fb140248cb 100644 --- a/arch/arm/src/stm32h7/stm32_tickless.c +++ b/arch/arm/src/stm32h7/stm32_tickless.c @@ -89,23 +89,23 @@ #undef HAVE_32BIT_TICKLESS -#if (CONFIG_STM32H7_TICKLESS_TIMER == 2) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 5) +#if (CONFIG_STM32_TICKLESS_TIMER == 2) || \ + (CONFIG_STM32_TICKLESS_TIMER == 5) #define HAVE_32BIT_TICKLESS 1 #endif -#if (CONFIG_STM32H7_TICKLESS_TIMER == 6) || \ - (CONFIG_STM32H7_TICKLESS_TIMER == 7) +#if (CONFIG_STM32_TICKLESS_TIMER == 6) || \ + (CONFIG_STM32_TICKLESS_TIMER == 7) # error Basic timers not supported by the tickless driver #endif -#if CONFIG_STM32H7_TICKLESS_CHANNEL == 1 +#if CONFIG_STM32_TICKLESS_CHANNEL == 1 #define DIER_CAPT_IE GTIM_DIER_CC1IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 2 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 2 #define DIER_CAPT_IE GTIM_DIER_CC2IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 3 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 3 #define DIER_CAPT_IE GTIM_DIER_CC3IE -#elif CONFIG_STM32H7_TICKLESS_CHANNEL == 4 +#elif CONFIG_STM32_TICKLESS_CHANNEL == 4 #define DIER_CAPT_IE GTIM_DIER_CC4IE #endif @@ -413,50 +413,50 @@ static uint64_t stm32_get_counter(void) void up_timer_initialize(void) { - switch (CONFIG_STM32H7_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM1STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM2STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: g_tickless.base = STM32_TIM3_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM3STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: g_tickless.base = STM32_TIM4_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM4STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: g_tickless.base = STM32_TIM5_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM5STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: g_tickless.base = STM32_TIM8_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM8STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: g_tickless.base = STM32_TIM9_BASE; @@ -464,7 +464,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: g_tickless.base = STM32_TIM10_BASE; @@ -473,7 +473,7 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: g_tickless.base = STM32_TIM11_BASE; @@ -481,40 +481,40 @@ void up_timer_initialize(void) break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: g_tickless.base = STM32_TIM12_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM12STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: g_tickless.base = STM32_TIM13_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM13STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: g_tickless.base = STM32_TIM14_BASE; modifyreg32(STM32_DBGMCU_APB1LFZ1, 0, DBGMCU_APB1L_TIM14STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: g_tickless.base = STM32_TIM15_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM15STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM16STOP); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; modifyreg32(STM32_DBGMCU_APB2FZ1, 0, DBGMCU_APB2Z1_TIM17STOP); @@ -528,8 +528,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32H7_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32H7_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; @@ -1001,10 +1001,10 @@ int up_alarm_start(const struct timespec *ts) flags = enter_critical_section(); - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, tm); + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); stm32_tickless_ackint(g_tickless.channel); - stm32_tickless_enableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_enableint(CONFIG_STM32_TICKLESS_CHANNEL); g_tickless.pending = true; @@ -1021,7 +1021,7 @@ int up_alarm_start(const struct timespec *ts) while (tm <= stm32_get_counter()) { tm = stm32_get_counter() + offset++; - STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32H7_TICKLESS_CHANNEL, + STM32_TIM_SETCOMPARE(g_tickless.tch, CONFIG_STM32_TICKLESS_CHANNEL, tm); } @@ -1042,7 +1042,7 @@ int up_alarm_cancel(struct timespec *ts) ts->tv_sec = nsecs / NSEC_PER_SEC; ts->tv_nsec = nsecs - ts->tv_sec * NSEC_PER_SEC; - stm32_tickless_disableint(CONFIG_STM32H7_TICKLESS_CHANNEL); + stm32_tickless_disableint(CONFIG_STM32_TICKLESS_CHANNEL); return 0; } diff --git a/arch/arm/src/stm32h7/stm32_tim.c b/arch/arm/src/stm32h7/stm32_tim.c index 4b04b9a9f24..63f84f00a15 100644 --- a/arch/arm/src/stm32h7/stm32_tim.c +++ b/arch/arm/src/stm32h7/stm32_tim.c @@ -72,77 +72,77 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32H7_TIM1_PWM) || defined (CONFIG_STM32H7_TIM1_ADC) || \ - defined(CONFIG_STM32H7_TIM1_DAC) || defined(CONFIG_STM32H7_TIM1_QE) -# undef CONFIG_STM32H7_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32H7_TIM2_PWM) || defined (CONFIG_STM32H7_TIM2_ADC) || \ - defined(CONFIG_STM32H7_TIM2_DAC) || defined(CONFIG_STM32H7_TIM2_QE) -# undef CONFIG_STM32H7_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) || defined (CONFIG_STM32H7_TIM3_ADC) || \ - defined(CONFIG_STM32H7_TIM3_DAC) || defined(CONFIG_STM32H7_TIM3_QE) -# undef CONFIG_STM32H7_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32H7_TIM4_PWM) || defined (CONFIG_STM32H7_TIM4_ADC) || \ - defined(CONFIG_STM32H7_TIM4_DAC) || defined(CONFIG_STM32H7_TIM4_QE) -# undef CONFIG_STM32H7_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32H7_TIM5_PWM) || defined (CONFIG_STM32H7_TIM5_ADC) || \ - defined(CONFIG_STM32H7_TIM5_DAC) || defined(CONFIG_STM32H7_TIM5_QE) -# undef CONFIG_STM32H7_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32H7_TIM6_ADC) || \ - defined(CONFIG_STM32H7_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) -# undef CONFIG_STM32H7_TIM6 +#if defined(CONFIG_STM32H7_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32H7_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32H7_TIM7_PWM) || defined (CONFIG_STM32H7_TIM7_ADC) || \ - defined(CONFIG_STM32H7_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) -# undef CONFIG_STM32H7_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32H7_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32H7_TIM8_PWM) || defined (CONFIG_STM32H7_TIM8_ADC) || \ - defined(CONFIG_STM32H7_TIM8_DAC) || defined(CONFIG_STM32H7_TIM8_QE) -# undef CONFIG_STM32H7_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32H7_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ - defined(CONFIG_STM32H7_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) -# undef CONFIG_STM32H7_TIM12 +#if defined(CONFIG_STM32_TIM12_PWM) || defined (CONFIG_STM32H7_TIM12_ADC) || \ + defined(CONFIG_STM32_TIM12_DAC) || defined(CONFIG_STM32H7_TIM12_QE) +# undef CONFIG_STM32_TIM12 #endif -#if defined(CONFIG_STM32H7_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ - defined(CONFIG_STM32H7_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) -# undef CONFIG_STM32H7_TIM13 +#if defined(CONFIG_STM32_TIM13_PWM) || defined (CONFIG_STM32H7_TIM13_ADC) || \ + defined(CONFIG_STM32_TIM13_DAC) || defined(CONFIG_STM32H7_TIM13_QE) +# undef CONFIG_STM32_TIM13 #endif -#if defined(CONFIG_STM32H7_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ - defined(CONFIG_STM32H7_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) -# undef CONFIG_STM32H7_TIM14 +#if defined(CONFIG_STM32_TIM14_PWM) || defined (CONFIG_STM32H7_TIM14_ADC) || \ + defined(CONFIG_STM32_TIM14_DAC) || defined(CONFIG_STM32H7_TIM14_QE) +# undef CONFIG_STM32_TIM14 #endif -#if defined(CONFIG_STM32H7_TIM15_PWM) || defined (CONFIG_STM32H7_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32H7_TIM15_DAC) || defined(CONFIG_STM32H7_TIM15_QE) -# undef CONFIG_STM32H7_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32H7_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32H7_TIM16_ADC) || \ defined(CONFIG_STM32H7_TIM16_DAC) || defined(CONFIG_STM32H7_TIM16_QE) -# undef CONFIG_STM32H7_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32H7_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32H7_TIM17_ADC) || \ defined(CONFIG_STM32H7_TIM17_DAC) || defined(CONFIG_STM32H7_TIM17_QE) -# undef CONFIG_STM32H7_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32H7_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT)||\ defined(GPIO_TIM1_CH5OUT) ||defined(GPIO_TIM1_CH6OUT) @@ -150,35 +150,35 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT)||\ defined(GPIO_TIM8_CH5OUT) ||defined(GPIO_TIM8_CH6OUT) @@ -186,37 +186,37 @@ # endif #endif -#if defined(CONFIG_STM32H7_TIM12) +#if defined(CONFIG_STM32_TIM12) # if defined(GPIO_TIM12_CH1OUT) ||defined(GPIO_TIM12_CH2OUT) # define HAVE_TIM12_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM13) +#if defined(CONFIG_STM32_TIM13) # if defined(GPIO_TIM13_CH1OUT) # define HAVE_TIM13_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM14) +#if defined(CONFIG_STM32_TIM14) # if defined(GPIO_TIM14_CH1OUT) # define HAVE_TIM14_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT) # define HAVE_TIM15_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) # define HAVE_TIM16_GPIOCONFIG 1 # endif #endif -#if defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) # define HAVE_TIM17_GPIOCONFIG 1 # endif @@ -226,13 +226,13 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM12) || defined(CONFIG_STM32H7_TIM13) || \ - defined(CONFIG_STM32H7_TIM14) || defined(CONFIG_STM32H7_TIM15) || \ - defined(CONFIG_STM32H7_TIM16) || defined(CONFIG_STM32H7_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM12) || defined(CONFIG_STM32_TIM13) || \ + defined(CONFIG_STM32_TIM14) || defined(CONFIG_STM32_TIM15) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -312,7 +312,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = &stm32_tim_checkint, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -320,7 +320,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -329,7 +329,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -338,7 +338,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -347,7 +347,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -356,7 +356,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -365,7 +365,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -374,7 +374,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -383,7 +383,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 struct stm32_tim_priv_s stm32_tim12_priv = { .ops = &stm32_tim_ops, @@ -392,7 +392,7 @@ struct stm32_tim_priv_s stm32_tim12_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 struct stm32_tim_priv_s stm32_tim13_priv = { .ops = &stm32_tim_ops, @@ -401,7 +401,7 @@ struct stm32_tim_priv_s stm32_tim13_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 struct stm32_tim_priv_s stm32_tim14_priv = { .ops = &stm32_tim_ops, @@ -410,7 +410,7 @@ struct stm32_tim_priv_s stm32_tim14_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -419,7 +419,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -428,7 +428,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -519,12 +519,12 @@ static int stm32_tim_getwidth(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32H7_TIM2) +#if defined(CONFIG_STM32_TIM2) case STM32_TIM2_BASE: return 32; #endif -#if defined(CONFIG_STM32H7_TIM5) +#if defined(CONFIG_STM32_TIM5) case STM32_TIM5_BASE: return 32; #endif @@ -626,72 +626,72 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = STM32_APB2_TIM1_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = STM32_APB1_TIM2_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = STM32_APB1_TIM3_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = STM32_APB1_TIM4_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = STM32_APB1_TIM5_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = STM32_APB1_TIM6_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = STM32_APB1_TIM7_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = STM32_APB2_TIM8_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: freqin = STM32_APB1_TIM12_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: freqin = STM32_APB1_TIM13_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: freqin = STM32_APB1_TIM14_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = STM32_APB2_TIM15_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = STM32_APB2_TIM16_CLKIN; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = STM32_APB2_TIM17_CLKIN; break; @@ -745,72 +745,72 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: vectorno = STM32_IRQ_TIM12; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: vectorno = STM32_IRQ_TIM13; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: vectorno = STM32_IRQ_TIM14; break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1016,7 +1016,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1049,7 +1049,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1078,7 +1078,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1107,7 +1107,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1136,7 +1136,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1165,7 +1165,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1199,7 +1199,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: switch (channel) { @@ -1218,7 +1218,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: switch (channel) { @@ -1232,7 +1232,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: switch (channel) { @@ -1247,7 +1247,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1266,7 +1266,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1280,7 +1280,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1364,85 +1364,85 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM2EN); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM3EN); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM4EN); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM5EN); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM6EN); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM7EN); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: dev = (struct stm32_tim_dev_s *)&stm32_tim12_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM12EN); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: dev = (struct stm32_tim_dev_s *)&stm32_tim13_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM13EN); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: dev = (struct stm32_tim_dev_s *)&stm32_tim14_priv; modifyreg32(STM32_RCC_APB1LENR, 0, RCC_APB1LENR_TIM14EN); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1474,72 +1474,72 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case STM32_TIM12_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM12EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case STM32_TIM13_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM13EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case STM32_TIM14_BASE: modifyreg32(STM32_RCC_APB1LENR, RCC_APB1LENR_TIM14EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32H7_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1555,4 +1555,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s * dev) return OK; } -#endif /* defined(CONFIG_STM32H7_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c index 895e54e7a2f..cc5e18737e5 100644 --- a/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32h7/stm32_tim_lowerhalf.c @@ -58,13 +58,13 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32H7_TIM1) || defined(CONFIG_STM32H7_TIM2) || \ - defined(CONFIG_STM32H7_TIM3) || defined(CONFIG_STM32H7_TIM4) || \ - defined(CONFIG_STM32H7_TIM5) || defined(CONFIG_STM32H7_TIM6) || \ - defined(CONFIG_STM32H7_TIM7) || defined(CONFIG_STM32H7_TIM8) || \ - defined(CONFIG_STM32H7_TIM9) || defined(CONFIG_STM32H7_TIM10) || \ - defined(CONFIG_STM32H7_TIM11) || defined(CONFIG_STM32H7_TIM12) || \ - defined(CONFIG_STM32H7_TIM13) || defined(CONFIG_STM32H7_TIM14)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM9) || defined(CONFIG_STM32_TIM10) || \ + defined(CONFIG_STM32_TIM11) || defined(CONFIG_STM32_TIM12) || \ + defined(CONFIG_STM32_TIM13) || defined(CONFIG_STM32_TIM14)) /**************************************************************************** * Pre-processor Definitions @@ -135,7 +135,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -143,7 +143,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -151,7 +151,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -159,7 +159,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -167,7 +167,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -175,7 +175,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -183,7 +183,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -191,7 +191,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -199,7 +199,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 static struct stm32_lowerhalf_s g_tim9_lowerhalf = { .ops = &g_timer_ops, @@ -207,7 +207,7 @@ static struct stm32_lowerhalf_s g_tim9_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 static struct stm32_lowerhalf_s g_tim10_lowerhalf = { .ops = &g_timer_ops, @@ -215,7 +215,7 @@ static struct stm32_lowerhalf_s g_tim10_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 static struct stm32_lowerhalf_s g_tim11_lowerhalf = { .ops = &g_timer_ops, @@ -223,7 +223,7 @@ static struct stm32_lowerhalf_s g_tim11_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 static struct stm32_lowerhalf_s g_tim12_lowerhalf = { .ops = &g_timer_ops, @@ -231,7 +231,7 @@ static struct stm32_lowerhalf_s g_tim12_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 static struct stm32_lowerhalf_s g_tim13_lowerhalf = { .ops = &g_timer_ops, @@ -239,7 +239,7 @@ static struct stm32_lowerhalf_s g_tim13_lowerhalf = }; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 static struct stm32_lowerhalf_s g_tim14_lowerhalf = { .ops = &g_timer_ops, @@ -473,72 +473,72 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32H7_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM9 +#ifdef CONFIG_STM32_TIM9 case 9: lower = &g_tim9_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM10 +#ifdef CONFIG_STM32_TIM10 case 10: lower = &g_tim10_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM11 +#ifdef CONFIG_STM32_TIM11 case 11: lower = &g_tim11_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM12 +#ifdef CONFIG_STM32_TIM12 case 12: lower = &g_tim12_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM13 +#ifdef CONFIG_STM32_TIM13 case 13: lower = &g_tim13_lowerhalf; break; #endif -#ifdef CONFIG_STM32H7_TIM14 +#ifdef CONFIG_STM32_TIM14 case 14: lower = &g_tim14_lowerhalf; break; diff --git a/arch/arm/src/stm32h7/stm32_uart.h b/arch/arm/src/stm32h7/stm32_uart.h index ea171109805..8748d83c343 100644 --- a/arch/arm/src/stm32h7/stm32_uart.h +++ b/arch/arm/src/stm32h7/stm32_uart.h @@ -41,43 +41,43 @@ */ #if STM32_NUART < 4 -# undef CONFIG_STM32H7_UART8 +# undef CONFIG_STM32_UART8 #endif #if STM32_NUART < 3 -# undef CONFIG_STM32H7_UART7 +# undef CONFIG_STM32_UART7 #endif #if STM32_NUART < 2 -# undef CONFIG_STM32H7_UART5 +# undef CONFIG_STM32_UART5 #endif #if STM32_NUART < 1 -# undef CONFIG_STM32H7_UART4 +# undef CONFIG_STM32_UART4 #endif #if STM32_NUSART < 4 -# undef CONFIG_STM32H7_USART6 +# undef CONFIG_STM32_USART6 #endif #if STM32_NUSART < 3 -# undef CONFIG_STM32H7_USART3 +# undef CONFIG_STM32_USART3 #endif #if STM32_NUSART < 2 -# undef CONFIG_STM32H7_USART2 +# undef CONFIG_STM32_USART2 #endif #if STM32_NUSART < 1 -# undef CONFIG_STM32H7_USART1 +# undef CONFIG_STM32_USART1 #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32H7_USART1) || defined(CONFIG_STM32H7_USART2) || \ - defined(CONFIG_STM32H7_USART3) || defined(CONFIG_STM32H7_UART4) || \ - defined(CONFIG_STM32H7_UART5) || defined(CONFIG_STM32H7_USART6) || \ - defined(CONFIG_STM32H7_UART7) || defined(CONFIG_STM32H7_UART8) +#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \ + defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \ + defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6) || \ + defined(CONFIG_STM32_UART7) || defined(CONFIG_STM32_UART8) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART1) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1) # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -87,7 +87,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART2) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -97,7 +97,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART3) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -107,7 +107,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART4) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -117,7 +117,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART5) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_USART6) +#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -137,7 +137,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 6 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART7) +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART7) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -147,7 +147,7 @@ # undef CONFIG_UART8_SERIAL_CONSOLE # define CONSOLE_UART 7 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32H7_UART8) +#elif defined(CONFIG_UART8_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART8) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -296,42 +296,42 @@ /* Is RX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_RXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) # undef SERIAL_HAVE_ONLY_RXDMA #endif /* Is TX DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_TXDMA 1 -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_TXDMA) +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_TXDMA) +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_TXDMA) +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_TXDMA) +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_TXDMA) +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_TXDMA) +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_TXDMA) +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_TXDMA) +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_TXDMA) # undef SERIAL_HAVE_ONLY_TXDMA #endif @@ -343,28 +343,28 @@ /* No DMA ops */ #undef SERIAL_HAVE_NODMA_OPS -#if defined(CONFIG_STM32H7_USART1) && !defined(CONFIG_USART1_RXDMA) && \ +#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA) && \ !defined(CONFIG_USART1_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART2) && !defined(CONFIG_USART2_RXDMA) && \ +#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA) && \ !defined(CONFIG_USART2_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART3) && !defined(CONFIG_USART3_RXDMA) && \ +#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA) && \ !defined(CONFIG_USART3_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART4) && !defined(CONFIG_UART4_RXDMA) && \ +#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_UART4_RXDMA) && \ !defined(CONFIG_UART4_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART5) && !defined(CONFIG_UART5_RXDMA) && \ +#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_UART5_RXDMA) && \ !defined(CONFIG_UART5_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_USART6) && !defined(CONFIG_USART6_RXDMA) && \ +#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA) && \ !defined(CONFIG_USART6_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART7) && !defined(CONFIG_UART7_RXDMA) && \ +#elif defined(CONFIG_STM32_UART7) && !defined(CONFIG_UART7_RXDMA) && \ !defined(CONFIG_UART7_TXDMA) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_STM32H7_UART8) && !defined(CONFIG_UART8_RXDMA) && \ +#elif defined(CONFIG_STM32_UART8) && !defined(CONFIG_UART8_RXDMA) && \ !defined(CONFIG_UART8_TXDMA) # define SERIAL_HAVE_NODMA_OPS #endif diff --git a/arch/arm/src/stm32h7/stm32_usbhost.h b/arch/arm/src/stm32h7/stm32_usbhost.h index 031b66ad229..798b0aaf965 100644 --- a/arch/arm/src/stm32h7/stm32_usbhost.h +++ b/arch/arm/src/stm32h7/stm32_usbhost.h @@ -28,10 +28,10 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32H7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block * or - * CONFIG_STM32H7_OTGHS - Enable the STM32 USB OTG HS block - * CONFIG_STM32H7_SYSCFG - Needed + * CONFIG_STM32_OTGHS - Enable the STM32 USB OTG HS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * @@ -44,7 +44,7 @@ * CONFIG_STM32H7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32H7_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG_FEATURES. */ @@ -58,7 +58,7 @@ #include #include -#if (defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_OTGHS)) && \ +#if (defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS)) && \ defined(CONFIG_USBHOST) #ifdef HAVE_USBHOST_TRACE @@ -190,5 +190,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* (CONFIG_STM32H7_OTGFS || CONFIG_STM32H7_OTGHS) && CONFIG_USBHOST */ +#endif /* (CONFIG_STM32_OTGFS || CONFIG_STM32_OTGHS) && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32H7_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32h7/stm32_wdg.h b/arch/arm/src/stm32h7/stm32_wdg.h index f869669264a..f5f51837661 100644 --- a/arch/arm/src/stm32h7/stm32_wdg.h +++ b/arch/arm/src/stm32h7/stm32_wdg.h @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32h7/stm32_wwdg.c b/arch/arm/src/stm32h7/stm32_wwdg.c index 4e96d10a3d3..7a4c29aeb9a 100644 --- a/arch/arm/src/stm32h7/stm32_wwdg.c +++ b/arch/arm/src/stm32h7/stm32_wwdg.c @@ -39,7 +39,7 @@ #include "arm_internal.h" #include "stm32_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32H7_WWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) /**************************************************************************** * Pre-processor Definitions @@ -783,9 +783,9 @@ void stm32_wwdginitialize(const char *devpath) * on the WWDG1 STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32H7_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32H7_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr = getreg32(STM32_DBGMCU_APB3_FZ1); cr |= DBGMCU_APB3_WWDG1STOP; @@ -794,4 +794,4 @@ void stm32_wwdginitialize(const char *devpath) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32H7_WWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32h7/stm32h743xx_flash.c b/arch/arm/src/stm32h7/stm32h743xx_flash.c index ddf3c13a5b8..9e996ee83f3 100644 --- a/arch/arm/src/stm32h7/stm32h743xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h743xx_flash.c @@ -69,7 +69,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32H7_FLASH_OVERRIDE_x @@ -85,49 +85,49 @@ #define FLASH_SECTOR_SIZE _K(128) #define FLASH_PAGE_SIZE 32 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_B +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_B # warning "Flash size not defined defaulting to 128KiB (B)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_B) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_B) -# define CONFIG_STM32H7_FLASH_CONFIG_B +# define CONFIG_STM32_FLASH_CONFIG_B -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_B) +#if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NBLOCKS 1 # define STM32_FLASH_SIZE _K(1 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 8 # define STM32_FLASH_SIZE _K(8 * 128) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 16 # define STM32_FLASH_SIZE _K(16 * 128) @@ -135,10 +135,10 @@ #endif -#ifndef CONFIG_STM32H7_FLASH_CR_PSIZE +#ifndef CONFIG_STM32_FLASH_CR_PSIZE #define FLASH_CR_PSIZE FLASH_CR_PSIZE_X64 #else -#define FLASH_CR_PSIZE (CONFIG_STM32H7_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) +#define FLASH_CR_PSIZE (CONFIG_STM32_FLASH_CR_PSIZE << FLASH_CR_PSIZE_SHIFT) #endif #define FLASH_KEY1 0x45670123 diff --git a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c index 278d0d2171d..7e1f8eb7d64 100644 --- a/arch/arm/src/stm32h7/stm32h7b3xx_flash.c +++ b/arch/arm/src/stm32h7/stm32h7b3xx_flash.c @@ -69,7 +69,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32H7_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32H7_FLASH_OVERRIDE_x @@ -86,38 +86,38 @@ #define FLASH_PAGE_SIZE 16 -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32H7_FLASH_CONFIG_I) -# define CONFIG_STM32H7_FLASH_OVERRIDE_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_G # warning "Flash size not defined defaulting to 1024KiB (G)" #endif -#if !defined(CONFIG_STM32H7_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32H7_FLASH_CONFIG_B -# undef CONFIG_STM32H7_FLASH_CONFIG_G -# undef CONFIG_STM32H7_FLASH_CONFIG_I +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I -# if defined(CONFIG_STM32H7_FLASH_OVERRIDE_G) +# if defined(CONFIG_STM32_FLASH_OVERRIDE_G) -# define CONFIG_STM32H7_FLASH_CONFIG_G +# define CONFIG_STM32_FLASH_CONFIG_G -# elif defined(CONFIG_STM32H7_FLASH_OVERRIDE_I) +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) -# define CONFIG_STM32H7_FLASH_CONFIG_I +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif -#if defined(CONFIG_STM32H7_FLASH_CONFIG_G) +#if defined(CONFIG_STM32_FLASH_CONFIG_G) # define STM32_FLASH_NBLOCKS 128 # define STM32_FLASH_SIZE _K(128 * 8) -#elif defined(CONFIG_STM32H7_FLASH_CONFIG_I) +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) # define STM32_FLASH_NBLOCKS 256 # define STM32_FLASH_SIZE _K(256 * 8) diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 5fb2cae9f94..c65bc2feeda 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -146,23 +146,23 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ STM32_PWR_CR3_SMPSEXTHP | \ STM32_PWR_CR3_SMPSLEVEL_MASK) -# if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY) +# if defined(CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_SDEN -# elif defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# elif defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_BYPASS # else # define STM32_PWR_CR3_SELECTION STM32_PWR_CR3_LDOEN # endif #else # define STM32_PWR_CR3_MASK 0xffffffff -# if defined(CONFIG_STM32H7_PWR_EXTERNAL_SOURCE_SUPPLY) +# if defined(CONFIG_STM32_PWR_EXTERNAL_SOURCE_SUPPLY) # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_SCUEN) # else # define STM32_PWR_CR3_SELECTION (STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN) @@ -192,7 +192,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -250,32 +250,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS +# ifndef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /* Enable only clocking for USB OTG HS */ regval |= RCC_AHB1ENR_OTGHSEN; @@ -286,7 +286,7 @@ static inline void rcc_enableahb1(void) # endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -314,19 +314,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32H7_CRYP +#ifdef CONFIG_STM32_CRYP /* Cryptographic clock enable */ regval |= RCC_AHB2ENR_CRYPTEN; @@ -353,25 +353,25 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#if defined(CONFIG_STM32H7_LTDC) && defined(CONFIG_STM32H7_DMA2D) +#if defined(CONFIG_STM32_LTDC) && defined(CONFIG_STM32_DMA2D) /* Enable DMA2D */ regval |= RCC_AHB3ENR_DMA2DEN; @@ -400,7 +400,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -422,10 +422,10 @@ static inline void rcc_enableahb4(void) #if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32_NGPIO > 7 @@ -443,25 +443,25 @@ static inline void rcc_enableahb4(void) ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32H7_HSEM +#ifdef CONFIG_STM32_HSEM /* HSEM clock enable */ regval |= RCC_AHB4ENR_HSEMEN; @@ -488,31 +488,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -522,7 +522,7 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1HENR); -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN /* FDCAN clock enable */ regval |= RCC_APB1HENR_FDCANEN; @@ -549,31 +549,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -600,13 +600,13 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /* LTDC clock enable */ regval |= RCC_APB3ENR_LTDCEN; #endif -#ifdef CONFIG_STM32H7_WWDG +#ifdef CONFIG_STM32_WWDG /* RM0433 Rev 8 * Reference manual - STM32H742, STM32H743/753 and STM32H750 Value line @@ -651,19 +651,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -762,7 +762,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -776,7 +776,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -832,7 +832,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -963,7 +963,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1105,13 +1105,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c index 481183e8ea5..526dc538e4a 100644 --- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c @@ -139,7 +139,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * When the Soc does not supports SMPS we support only the LDO supply. */ -#ifdef CONFIG_STM32H7_HAVE_SMPS +#ifdef CONFIG_STM32_HAVE_SMPS # define STM32_PWR_CR3_MASK ~(STM32_PWR_CR3_BYPASS | \ STM32_PWR_CR3_LDOEN | \ STM32_PWR_CR3_SDEN | \ @@ -179,7 +179,7 @@ static inline void rcc_reset(void) regval |= RCC_CR_HSION; putreg32(regval, STM32_RCC_CR); -#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) +#if defined(CONFIG_STM32_AXI_SRAM_CORRUPTION_WAR) /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to * data read corruption. See ES0392 Rev 6. */ @@ -237,32 +237,32 @@ static inline void rcc_enableahb1(void) */ regval = getreg32(STM32_RCC_AHB1ENR); -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) /* ADC1 & 2 clock enable */ regval |= RCC_AHB1ENR_ADC12EN; #endif -#ifdef CONFIG_STM32H7_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32H7_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB1ENR_OTGFSEN; #endif -#ifdef CONFIG_STM32H7_OTGHS -# if defined(CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI) +#ifdef CONFIG_STM32_OTGHS +# if defined(CONFIG_STM32_OTGHS_EXTERNAL_ULPI) /* Enable clocking for USB OTG HS and external PHY */ regval |= (RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN); @@ -273,7 +273,7 @@ static inline void rcc_enableahb1(void) #endif #endif -#ifdef CONFIG_STM32H7_ETHMAC +#ifdef CONFIG_STM32_ETHMAC /* Enable ethernet clocks */ regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | @@ -301,13 +301,13 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR); -#ifdef CONFIG_STM32H7_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 /* SDMMC2 clock enable */ regval |= RCC_AHB2ENR_SDMMC2EN; #endif -#ifdef CONFIG_STM32H7_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -334,19 +334,19 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32H7_MDMA +#ifdef CONFIG_STM32_MDMA /* MDMA clock enable */ regval |= RCC_AHB3ENR_MDMAEN; #endif -#ifdef CONFIG_STM32H7_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 /* SDMMC clock enable */ regval |= RCC_AHB3ENR_SDMMC1EN; #endif -#ifdef CONFIG_STM32H7_FMC +#ifdef CONFIG_STM32_FMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FMCEN; @@ -375,7 +375,7 @@ static inline void rcc_enableahb4(void) regval = getreg32(STM32_RCC_AHB4ENR); -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* ADC3 clock enable */ regval |= RCC_AHB4ENR_ADC3EN; @@ -397,10 +397,10 @@ static inline void rcc_enableahb4(void) #if STM32_NGPIO > 4 | RCC_AHB4ENR_GPIOEEN #endif -#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) +#if (STM32_NGPIO > 5) && (defined(CONFIG_STM32_HAVE_GPIOF)) | RCC_AHB4ENR_GPIOFEN #endif -#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) +#if (STM32_NGPIO > 6) && (defined(CONFIG_STM32_HAVE_GPIOG)) | RCC_AHB4ENR_GPIOGEN #endif #if STM32_NGPIO > 7 @@ -418,19 +418,19 @@ static inline void rcc_enableahb4(void) ); #endif -#ifdef CONFIG_STM32H7_BDMA +#ifdef CONFIG_STM32_BDMA /* BDMA clock enable */ regval |= RCC_AHB4ENR_BDMAEN; #endif -#ifdef CONFIG_STM32H7_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB4ENR_CRCEN; #endif -#ifdef CONFIG_STM32H7_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM /* Backup SRAM clock enable */ regval |= RCC_AHB4ENR_BKPSRAMEN; @@ -457,31 +457,31 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1LENR); -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1LENR_SPI2EN; #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1LENR_SPI3EN; #endif -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1LENR_I2C1EN; #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1LENR_I2C2EN; #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1LENR_I2C3EN; @@ -516,31 +516,31 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 /* SPI4 clock enable */ regval |= RCC_APB2ENR_SPI4EN; #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 /* SPI5 clock enable */ regval |= RCC_APB2ENR_SPI5EN; #endif -#ifdef CONFIG_STM32H7_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32H7_USART6 +#ifdef CONFIG_STM32_USART6 /* USART6 clock enable */ regval |= RCC_APB2ENR_USART6EN; @@ -590,19 +590,19 @@ static inline void rcc_enableapb4(void) regval = getreg32(STM32_RCC_APB4ENR); -#ifdef CONFIG_STM32H7_SYSCFG +#ifdef CONFIG_STM32_SYSCFG /* System configuration controller clock enable */ regval |= RCC_APB4ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB4ENR_I2C4EN; #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 /* SPI6 clock enable */ regval |= RCC_APB4ENR_SPI6EN; @@ -696,7 +696,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_HSI48 +#ifdef CONFIG_STM32_HSI48 /* Enable HSI48 */ regval = getreg32(STM32_RCC_CR); @@ -710,7 +710,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32H7_CSI +#ifdef CONFIG_STM32_CSI /* Enable CSI */ regval = getreg32(STM32_RCC_CR); @@ -766,7 +766,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_D3CFGR_D3PPRE; putreg32(regval, STM32_RCC_D3CFGR); -#ifdef CONFIG_STM32H7_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -897,7 +897,7 @@ void stm32_stdclockconfig(void) { } -#ifndef CONFIG_STM32H7_PWR_IGNORE_ACTVOSRDY +#ifndef CONFIG_STM32_PWR_IGNORE_ACTVOSRDY /* See Reference manual Section 5.4.1, System supply startup */ while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) @@ -1038,13 +1038,13 @@ void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_D2CCIP1R); #endif -#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_STM32H7_RTC_LSECLOCK) +#if defined(CONFIG_STM32_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig index 81256b344b3..6c5b66cd269 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,13 +48,13 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig index 5ead89d6a20..007834df663 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig index 2f5b1ee1c58..dad31466087 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -50,9 +51,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig index d0502ff974d..ed872fc7b3b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -57,11 +58,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig index 0478f186776..676f5681af1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/lvgl/defconfig @@ -6,13 +6,14 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,14 +67,14 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xC0600000 -CONFIG_STM32H7_LTDC_FB_SIZE=2097152 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xC0600000 +CONFIG_STM32_LTDC_FB_SIZE=2097152 +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig index 5f25013c7d1..a1d0ec0844f 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/mfrc522/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,10 +49,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig index 6486a55fbbb..8f04d2c7ab6 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig @@ -20,6 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,11 +61,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig index 2579b2ca842..8498dcc669e 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_slave/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_UART4=y -CONFIG_STM32H7_USART1=y -CONFIG_STM32H7_USART6=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART1=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=38400 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig index 8d434e7ed5e..0f07506b59b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,18 +70,18 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_PHYSR=30 -CONFIG_STM32H7_PHYSR_100FD=0x6 -CONFIG_STM32H7_PHYSR_100HD=0x2 -CONFIG_STM32H7_PHYSR_10FD=0x5 -CONFIG_STM32H7_PHYSR_10HD=0x1 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x7 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RMII_MCO1=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_PHYSR=30 +CONFIG_STM32_PHYSR_100FD=0x6 +CONFIG_STM32_PHYSR_100HD=0x2 +CONFIG_STM32_PHYSR_10FD=0x5 +CONFIG_STM32_PHYSR_10HD=0x1 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x7 +CONFIG_STM32_PWR=y +CONFIG_STM32_RMII_MCO1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig index 293a768c652..4f5046b5bf4 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,9 +46,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig index 25020b5ef45..b15a5f909aa 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,11 +52,11 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_QSPI=y -CONFIG_STM32H7_QSPI_INTERRUPTS=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_QSPI_INTERRUPTS=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_NXFFS=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig index 790cb3c5968..483c66da524 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/qencoder/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,11 +49,11 @@ CONFIG_SENSORS_QENCODER=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM5=y -CONFIG_STM32H7_TIM5_QE=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM5=y +CONFIG_STM32_TIM5_QE=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig index c50bb277960..ccccc22e495 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -68,11 +69,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig index 3dbb6830e69..f341419ebfc 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,11 +59,11 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig index b7502e7c4a2..3578ec87beb 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_RAMTEST=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig index f79049ddbd2..7ef37a7cbf7 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -66,9 +67,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART1=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig index 7f6c62f7326..2dec3ec8389 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/tone/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,15 +56,15 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ONESHOT=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_TIM17=y -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CH2OUT=y -CONFIG_STM32H7_TIM4_CHANNEL=2 -CONFIG_STM32H7_TIM4_PWM=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_ONESHOT=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_TIM17=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CH2OUT=y +CONFIG_STM32_TIM4_CHANNEL=2 +CONFIG_STM32_TIM4_PWM=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig index 0c36755c1c7..3a56b8e9afa 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig @@ -8,11 +8,12 @@ # CONFIG_MMCSD_HAVE_WRITEPROTECT is not set # CONFIG_MMCSD_MMCSUPPORT is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_SDMMC_IDMA is not set +# CONFIG_STM32_SDMMC_IDMA is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -60,12 +61,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig index 77d040d77ad..3772f3440ed 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -49,11 +50,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig index 12364f56d13..e2faa065b1b 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="linum-stm32h753bi" CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753BI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,12 +66,12 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_ZMODEM=y CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 3072adbe60f..6cccfd1a0ba 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -488,7 +488,7 @@ * linum board routes only DQ[15:0] bits. */ -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 120000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" @@ -502,7 +502,7 @@ * this value will need to be doubled. */ -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC # define BOARD_SDRAM1_SIZE (6*1024*1024) #else # define BOARD_SDRAM1_SIZE (8*1024*1024) diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index d0d7904d73a..e4b1d4e9275 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -30,11 +30,11 @@ if(CONFIG_USERLED) list(APPEND SRCS stm32_userled.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() @@ -70,7 +70,7 @@ if(CONFIG_CL_MFRC522) list(APPEND SRCS stm32_mfrc522.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile index c2ae5df6f58..56336dc4c5a 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile @@ -32,11 +32,11 @@ else endif endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif @@ -68,7 +68,7 @@ ifeq ($(CONFIG_CL_MFRC522),y) CSRCS += stm32_mfrc522.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 8ce1c6eee65..64027b170b9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -86,7 +86,7 @@ * PD7 Enable power supply SD Card pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -162,7 +162,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -225,7 +225,7 @@ int stm32_pwm_setup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index bab56899d14..02f6a1cc0ae 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -47,7 +47,7 @@ # include "stm32_rtc.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -132,10 +132,10 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -166,7 +166,7 @@ int stm32_bringup(void) struct rtc_lowerhalf_s *lower; #endif -#ifdef CONFIG_STM32H7_RMII +#ifdef CONFIG_STM32_RMII /* Reset Ethernet PHY */ stm32_configgpio(GPIO_ETH_RESET); @@ -289,7 +289,7 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 /* Enable and configure CAN1 */ @@ -298,7 +298,7 @@ int stm32_bringup(void) stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 /* Enable and configure CAN2 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c index 15113bb0f06..bc5b9ffcacb 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c index de8539d1a6f..097d5fc17ae 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_mfrc522.c @@ -36,7 +36,7 @@ #include "linum-stm32h753bi.h" #include "stm32_spi.h" -#if defined(CONFIG_SPI) && defined(CONFIG_STM32H7_SPI4) && defined(CONFIG_CL_MFRC522) +#if defined(CONFIG_SPI) && defined(CONFIG_STM32_SPI4) && defined(CONFIG_CL_MFRC522) /**************************************************************************** * Pre-processor Definitions @@ -83,4 +83,4 @@ int stm32_mfrc522initialize(const char *devpath) return ret; } -#endif /* CONFIG_SPI && CONFIG_STM32H7_SPI4 && CONFIG_MFRC522 */ +#endif /* CONFIG_SPI && CONFIG_STM32_SPI4 && CONFIG_MFRC522 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c index b64a561aa2a..18b39f615b1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4 +#ifndef CONFIG_STM32_TIM4 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM4_PWM +#ifndef CONFIG_STM32_TIM4_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c index cf5467941e0..77db8bb8c3f 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "linum-stm32h753bi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -89,7 +89,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -132,7 +132,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -140,4 +140,4 @@ int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI4 */ +#endif /* CONFIG_STM32_SPI4 */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c index 0ffbbc6e81a..76ff702a627 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_touchscreen.c @@ -48,8 +48,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C3 -# error "FT5x06 support requires CONFIG_STM32H7_I2C3" +#ifndef CONFIG_STM32_I2C3 +# error "FT5x06 support requires CONFIG_STM32_I2C3" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c index 88b139eb458..884e370b0c9 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "linum-stm32h753bi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig index 9008dcbeb95..e73fc9f8fa8 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,19 +68,19 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig index bd2ea04db96..11f85e483ed 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,10 +46,10 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig index 314c36575b7..715f1f0df18 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig +++ b/boards/arm/stm32h7/nucleo-h723zg/configs/oa_tc6/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h723zg" CONFIG_ARCH_BOARD_NUCLEO_H723ZG=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H723ZG=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,11 +74,11 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DTCMEXCLUDE=y -CONFIG_STM32H7_FLASH_OVERRIDE_G=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_SRAM4EXCLUDE=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DTCMEXCLUDE=y +CONFIG_STM32_FLASH_OVERRIDE_G=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM4EXCLUDE=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING6=y diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt index f27901f9491..45813c92cc5 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h723zg/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile index dedc375fb9c..f57fd57f306 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h723zg/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h index b9036604f88..4302c7eec2e 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h +++ b/boards/arm/stm32h7/nucleo-h723zg/src/nucleo-h723zg.h @@ -46,7 +46,7 @@ /* Can't support USB host or device features if USB OTG HS is not enabled */ -#ifndef CONFIG_STM32H7_OTGHS +#ifndef CONFIG_STM32_OTGHS # undef HAVE_USBDEV #endif @@ -74,7 +74,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -213,7 +213,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -250,7 +250,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS void weak_function stm32_usbinitialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c index 60de3707aae..1a4bc8d2eaf 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c index 4b07cc70335..8caa51be221 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c index 445db3e6757..43d7a676c91 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_bringup.c @@ -97,16 +97,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c index 8df03e00109..f8b200de768 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c index 23d61b098aa..0570f528631 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h723zg.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_NET_OA_TC6 @@ -101,7 +101,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -115,7 +115,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -129,7 +129,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -159,7 +159,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -173,7 +173,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -187,7 +187,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -225,42 +225,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -268,4 +268,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c index 2216484a508..953b452e86f 100644 --- a/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h723zg/src/stm32_usb.c @@ -78,7 +78,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_VBUS); stm32_configgpio(GPIO_OTGHS_PWRON); stm32_configgpio(GPIO_OTGHS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig index 35961190575..2ffafc58713 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/capture/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,9 +44,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_TIM4=y -CONFIG_STM32H7_TIM4_CAP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_TIM4=y +CONFIG_STM32_TIM4_CAP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig index 81c3cdcdab6..b36d0f21e25 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/composite/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,10 +76,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SPI3=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_USBMSC=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig index 2fa4212858e..27247352da0 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/elf/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_DTCMEXCLUDE is not set +# CONFIG_STM32_DTCMEXCLUDE is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,9 +55,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y CONFIG_STM32_ROMFS=y CONFIG_STM32_ROMFS_IMAGEFILE="../../apps/examples/elf/main/elf_romfs.img" +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TLS_NELEM=4 diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig index 6966a2baf20..9be0478f7ea 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -73,18 +74,18 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FLASH_OVERRIDE_I=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig index 73d680b2e78..ac1dce20115 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/mcuboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,10 +56,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_MCUBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig index 67f590adaf0..ec57eb558ba 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig index 7fe65a420a1..788de2f32ef 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig index 7afab9a8915..8d9cdb06d9a 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-app/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -54,10 +55,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig index 108860120e5..ceb8ba55d35 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxboot-loader/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,10 +57,10 @@ CONFIG_SPI=y CONFIG_START_DAY=28 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 -CONFIG_STM32H7_FLASH_OVERRIDE_I=y -CONFIG_STM32H7_USART3=y CONFIG_STM32_APP_FORMAT_NXBOOT=y +CONFIG_STM32_FLASH_OVERRIDE_I=y CONFIG_STM32_PROGMEM_OTA_PARTITION=y +CONFIG_STM32_USART3=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig index 8f193c58d45..86c0aa28e5d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/nxlines_oled/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,8 +60,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig index 25861432828..5977b0463ba 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/otg_fs_host/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig index 36c6b375d46..e43edd2ca1d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/pwm/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -45,21 +46,21 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_CH1NOUT=y -CONFIG_STM32H7_TIM1_CH1OUT=y -CONFIG_STM32H7_TIM1_CH2NOUT=y -CONFIG_STM32H7_TIM1_CH2OUT=y -CONFIG_STM32H7_TIM1_CH3NOUT=y -CONFIG_STM32H7_TIM1_CH3OUT=y -CONFIG_STM32H7_TIM1_CH4OUT=y -CONFIG_STM32H7_TIM1_CHANNEL1=y -CONFIG_STM32H7_TIM1_CHANNEL2=y -CONFIG_STM32H7_TIM1_CHANNEL3=y -CONFIG_STM32H7_TIM1_CHANNEL4=y -CONFIG_STM32H7_TIM1_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_CH2NOUT=y +CONFIG_STM32_TIM1_CH2OUT=y +CONFIG_STM32_TIM1_CH3NOUT=y +CONFIG_STM32_TIM1_CH3OUT=y +CONFIG_STM32_TIM1_CH4OUT=y +CONFIG_STM32_TIM1_CHANNEL1=y +CONFIG_STM32_TIM1_CHANNEL2=y +CONFIG_STM32_TIM1_CHANNEL3=y +CONFIG_STM32_TIM1_CHANNEL4=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig index 9060c7e249b..914de95443f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi/configs/rndis/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi" CONFIG_ARCH_BOARD_NUCLEO_H743ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -69,9 +70,9 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt index d4e92b8f5ed..4967d7e733d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi/src/CMakeLists.txt @@ -40,11 +40,11 @@ if(CONFIG_STM32_ROMFS) list(APPEND SRCS stm32_romfs_initialize.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -72,7 +72,7 @@ if(CONFIG_LCD_SSD1306) list(APPEND SRCS stm32_ssd1306.c) endif() -if(CONFIG_STM32H7_PROGMEM) +if(CONFIG_STM32_PROGMEM) list(APPEND SRCS stm32_progmem.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile index 985900a61a9..bf54e0db6ef 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi/src/Makefile @@ -42,11 +42,11 @@ ifeq ($(CONFIG_STM32_ROMFS),y) CSRCS += stm32_romfs_initialize.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -74,7 +74,7 @@ ifeq ($(CONFIG_LCD_SSD1306),y) CSRCS += stm32_ssd1306.c endif -ifeq ($(CONFIG_STM32H7_PROGMEM),y) +ifeq ($(CONFIG_STM32_PROGMEM),y) CSRCS += stm32_progmem.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h index 4bcfe00d50b..2523adbe4a9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h +++ b/boards/arm/stm32h7/nucleo-h743zi/src/nucleo-h743zi.h @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -251,7 +251,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif @@ -288,7 +288,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -302,7 +302,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c index a4ac81103a6..1b0a972921a 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_adc.c @@ -48,8 +48,8 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -61,7 +61,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 15, 18, 19, 7, 12}; @@ -83,12 +83,12 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC123_INP12 }; -#endif /* CONFIG_STM32H7_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ /**************************************************************************** * ADC2 ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_adc2_chanlist[ADC2_NCHANNELS] = { @@ -103,9 +103,9 @@ static const uint32_t g_adc2_pinlist[ADC2_NCHANNELS] = GPIO_ADC12_INP4, GPIO_ADC12_INP8 }; -#endif /* CONFIG_STM32H7_ADC2 */ +#endif /* CONFIG_STM32_ADC2 */ -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -146,7 +146,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -158,7 +158,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -190,7 +190,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#ifdef CONFIG_STM32H7_ADC2 +#ifdef CONFIG_STM32_ADC2 /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC2_NCHANNELS; i++) @@ -222,7 +222,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -252,8 +252,8 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -265,5 +265,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c index 17cfeed669d..70d9ebd007e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c index a8999a87a40..ac08dece22d 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -62,7 +62,7 @@ # include "stm32_capture.h" #endif -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG # include "stm32_wdg.h" #endif @@ -96,40 +96,40 @@ static int stm32_capture_setup(void) int ret; struct cap_lowerhalf_s *lower[] = { -#if defined(CONFIG_STM32H7_TIM1_CAP) +#if defined(CONFIG_STM32_TIM1_CAP) stm32_cap_initialize(1), #endif -#if defined(CONFIG_STM32H7_TIM2_CAP) +#if defined(CONFIG_STM32_TIM2_CAP) stm32_cap_initialize(2), #endif -#if defined(CONFIG_STM32H7_TIM3_CAP) +#if defined(CONFIG_STM32_TIM3_CAP) stm32_cap_initialize(3), #endif -#if defined(CONFIG_STM32H7_TIM4_CAP) +#if defined(CONFIG_STM32_TIM4_CAP) stm32_cap_initialize(4), #endif -#if defined(CONFIG_STM32H7_TIM5_CAP) +#if defined(CONFIG_STM32_TIM5_CAP) stm32_cap_initialize(5), #endif -#if defined(CONFIG_STM32H7_TIM8_CAP) +#if defined(CONFIG_STM32_TIM8_CAP) stm32_cap_initialize(8), #endif -#if defined(CONFIG_STM32H7_TIM12_CAP) +#if defined(CONFIG_STM32_TIM12_CAP) stm32_cap_initialize(12), #endif -#if defined(CONFIG_STM32H7_TIM13_CAP) +#if defined(CONFIG_STM32_TIM13_CAP) stm32_cap_initialize(13), #endif -#if defined(CONFIG_STM32H7_TIM14_CAP) +#if defined(CONFIG_STM32_TIM14_CAP) stm32_cap_initialize(14), #endif -#if defined(CONFIG_STM32H7_TIM15_CAP) +#if defined(CONFIG_STM32_TIM15_CAP) stm32_cap_initialize(15), #endif -#if defined(CONFIG_STM32H7_TIM16_CAP) +#if defined(CONFIG_STM32_TIM16_CAP) stm32_cap_initialize(16), #endif -#if defined(CONFIG_STM32H7_TIM17_CAP) +#if defined(CONFIG_STM32_TIM17_CAP) stm32_cap_initialize(17), #endif /* TODO: LPTIMy_CAP */ @@ -216,16 +216,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } @@ -487,7 +487,7 @@ int stm32_bringup(void) #endif /* HAVE_PROGMEM_CHARDEV */ #endif /* CONFIG_MTD */ -#ifdef CONFIG_STM32H7_IWDG +#ifdef CONFIG_STM32_IWDG /* Initialize the watchdog timer */ stm32_iwdginitialize("/dev/watchdog0", STM32_LSI_FREQUENCY); diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c index 6412aca6a93..6017b9b69ad 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -62,7 +62,7 @@ int stm32_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c index a7037b3c4cc..0d1e8807238 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -66,7 +66,7 @@ int stm32_lsm6dsl_initialize(char *devpath) stm32_configgpio(GPIO_LPS22HB_INT1); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c index 6f5276f12d6..bb50400bd61 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_lsm9ds1.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32H7_I2C1 -# error "LSM9DS1 driver requires CONFIG_STM32H7_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM9DS1 driver requires CONFIG_STM32_I2C1 to be enabled" #endif #define LSM9DS1MAG_DEVPATH "/dev/lsm9ds1mag0" @@ -66,7 +66,7 @@ int stm32_lsm9ds1_initialize(void) sninfo("Initializing LMS9DS1!\n"); -#if defined(CONFIG_STM32H7_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(LMS9DS1_I2CBUS); if (i2c == NULL) { diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c index 40dbe2fcbf4..7979ef412b8 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_mmcsd.c @@ -44,7 +44,7 @@ # error "SD driver requires CONFIG_DISABLE_MOUNTPOINT to be disabled" #endif -#ifndef CONFIG_STM32H7_SPI3 +#ifndef CONFIG_STM32_SPI3 # error "MMC/SD requires SPI3 enabled" #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c index 0631fcba688..fba60268a2f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_pwm.c @@ -49,11 +49,11 @@ # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef HAVE_PWM #endif -#ifndef CONFIG_STM32H7_TIM1_PWM +#ifndef CONFIG_STM32_TIM1_PWM # undef HAVE_PWM #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c index 04b75b9f41d..42f9a514fe6 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-h743zi.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -63,7 +63,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 spiinfo("Configure GPIO for SPI3/CS\n"); # ifdef CONFIG_WL_NRF24L01 @@ -108,7 +108,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -122,7 +122,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -136,7 +136,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -192,7 +192,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -206,7 +206,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,7 +220,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -258,42 +258,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -301,4 +301,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c index 3efae55c0f7..ed51bc58578 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig index 23c77196423..436b8c8c378 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -104,19 +105,19 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_TIM8=y -CONFIG_STM32H7_TIM8_PULSECOUNT=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_TIM8=y +CONFIG_STM32_TIM8_PULSECOUNT=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig index 42df2d25cf2..c5bbd8b5b27 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig index 238e410712d..66ec35fe74b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index 1148378b855..2f4276ac9c9 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig index 5eb5fce08d0..68c89eacc79 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h743zi2" CONFIG_ARCH_BOARD_NUCLEO_H743ZI2=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt index ce26e66e8cc..1d7544f8cdb 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile index 9991b451550..f05dd5b891c 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h index ad98bd39fd3..6d63033cbb3 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/nucleo-h743zi2.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH743ZI2_PWMTIMER 1 #else # define NUCLEOH743ZI2_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c index c11ea35b3f3..3d2ddaf2c32 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c index be6710f36d0..36ad112abab 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c index f0d0a7df159..f526cd6876b 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_bringup.c @@ -35,11 +35,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -242,18 +242,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -264,7 +264,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -275,7 +275,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c index 51afc1e4447..943a4c4a884 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c index 547fda201e6..3b7a541084e 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h743zi2.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h745zi/Kconfig b/boards/arm/stm32h7/nucleo-h745zi/Kconfig index bff59a18183..bdc477c0e39 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/Kconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/Kconfig @@ -11,7 +11,7 @@ choice config NUCLEOH745ZI_SMPS bool "Internal SMPS only (default)" - select STM32H7_PWR_DIRECT_SMPS_SUPPLY + select STM32_PWR_DIRECT_SMPS_SUPPLY config NUCLEOH745ZI_LDO bool "Internal LDO only" diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig index 4d056b4494f..66d8897395c 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,6 +39,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig index f404c9aca7c..f339a51f052 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig index a4a5abb06fc..5aed1797432 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig index 32deeca5826..b64fcb0e0aa 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,7 +49,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig index 5876e49c1e4..2d7fa0de5d0 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h745zi" CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld index c4bf2bd60d6..56c5da03c47 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash.ld @@ -22,7 +22,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -40,7 +40,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld index b24bcef0596..7c33bec3bd8 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/nucleo-h745zi/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile index df3be92d509..37c9b6b815d 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile @@ -34,7 +34,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h index b3b16bee6f6..fa2747b2f48 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h +++ b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h @@ -47,7 +47,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -82,7 +82,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -226,7 +226,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) #define NUCLEOH745ZI_PWMTIMER 1 #else #define NUCLEOH745ZI_PWMTIMER 3 @@ -249,7 +249,7 @@ int stm32_bringup(void); -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -287,7 +287,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c index 7ab6b8a0331..cba9c51771b 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -49,9 +49,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -64,7 +64,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -92,7 +92,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -133,7 +133,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(int adcno) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -147,7 +147,7 @@ int stm32_adc_setup(int adcno) snprintf(devname, sizeof(devname), "/dev/adc%d", adcno); #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -178,7 +178,7 @@ int stm32_adc_setup(int adcno) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -208,7 +208,7 @@ int stm32_adc_setup(int adcno) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -220,5 +220,5 @@ int stm32_adc_setup(int adcno) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c index dfbbfecba2b..4e56b563eee 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a8e26a5b591..aa9ab6abbc6 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -144,11 +144,11 @@ int stm32_bringup(void) int adcno = 0; -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 adcno = 0; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 adcno = 2; #endif @@ -172,18 +172,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -194,7 +194,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -205,7 +205,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c index 1e34ac8a093..adeaaf3673c 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c index 77b5638be1f..c06f89ef35a 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h745zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig index e36ef998844..9f75e257f09 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/crypto/defconfig @@ -16,6 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,8 +48,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_CRYP=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_CRYP=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_CRYPTO=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig index 4482d9ba53b..64f82396477 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/jumbo/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -103,17 +104,17 @@ CONFIG_STACK_COLORATION=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSLOG_INTBUFFER=y CONFIG_SYSLOG_PRIORITY=y CONFIG_SYSLOG_PROCESS_NAME=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig index 6d3d69392c9..690987ab92f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/netnsh/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,17 +66,17 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig index 4e017f8e0db..d4005fc697a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -39,7 +40,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig index 6851a571ec6..d6e87352352 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/pysim/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -88,32 +89,32 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ADC1=y -CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 -CONFIG_STM32H7_ADC1_TIMTRIG=1 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWM_MULTICHAN=y -CONFIG_STM32H7_TIM1=y -CONFIG_STM32H7_TIM1_QE=y -CONFIG_STM32H7_TIM2=y -CONFIG_STM32H7_TIM2_ADC=y -CONFIG_STM32H7_TIM3=y -CONFIG_STM32H7_TIM3_CH1OUT=y -CONFIG_STM32H7_TIM3_CH2OUT=y -CONFIG_STM32H7_TIM3_CHANNEL1=y -CONFIG_STM32H7_TIM3_CHANNEL2=y -CONFIG_STM32H7_TIM3_PWM=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32_ADC1_TIMTRIG=1 +CONFIG_STM32_DMA1=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWM_MULTICHAN=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_QE=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_ADC=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_CH2OUT=y +CONFIG_STM32_TIM3_CHANNEL1=y +CONFIG_STM32_TIM3_CHANNEL2=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig index 602d566130d..f9643ef1a1a 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig +++ b/boards/arm/stm32h7/nucleo-h753zi/configs/socketcan/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-h753zi" CONFIG_ARCH_BOARD_NUCLEO_H753ZI=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H753ZI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -62,9 +63,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FDCAN1=y -CONFIG_STM32H7_FDCAN2=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FDCAN1=y +CONFIG_STM32_FDCAN2=y +CONFIG_STM32_USART3=y CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt index 73ac7a500a7..8e61aeb5382 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/nucleo-h753zi/src/CMakeLists.txt @@ -32,7 +32,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile index 0f164c5b1a4..e310e6c8a8e 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h753zi/src/Makefile @@ -38,7 +38,7 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h index 8549c8b633a..ff4a7a9380b 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h +++ b/boards/arm/stm32h7/nucleo-h753zi/src/nucleo-h753zi.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -143,7 +143,7 @@ /* PWM */ -#if defined(CONFIG_STM32H7_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) # define NUCLEOH753ZI_PWMTIMER 1 #else # define NUCLEOH753ZI_PWMTIMER 3 @@ -175,7 +175,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -213,7 +213,7 @@ int stm32_gpio_initialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c index 8bc9ba8841a..fca934607ef 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -91,7 +91,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -132,7 +132,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -144,7 +144,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -175,7 +175,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -217,5 +217,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c index 027cde005d7..d24de71d2ea 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_boot.c @@ -58,7 +58,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c index be030dcb4d2..805c1c46368 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_bringup.c @@ -36,11 +36,11 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif -#ifdef CONFIG_STM32H7_FDCAN +#ifdef CONFIG_STM32_FDCAN #include "stm32_fdcan_sock.h" #endif @@ -218,18 +218,18 @@ int stm32_bringup(void) #ifdef CONFIG_NETDEV_LATEINIT -# ifdef CONFIG_STM32H7_FDCAN1 +# ifdef CONFIG_STM32_FDCAN1 stm32_fdcansockinitialize(0); # endif -# ifdef CONFIG_STM32H7_FDCAN2 +# ifdef CONFIG_STM32_FDCAN2 stm32_fdcansockinitialize(1); # endif #endif #ifdef CONFIG_SENSORS_QENCODER -#ifdef CONFIG_STM32H7_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE ret = stm32_qencoder_initialize("/dev/qe0", 1); if (ret < 0) { @@ -240,7 +240,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE ret = stm32_qencoder_initialize("/dev/qe2", 3); if (ret < 0) { @@ -251,7 +251,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32H7_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE ret = stm32_qencoder_initialize("/dev/qe3", 4); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c index 24eae1bc1cf..8898b9655fa 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_pwm.c @@ -84,7 +84,7 @@ int stm32_pwm_setup(void) /* Register the PWM driver at "/dev/pwm0" */ - #if defined(CONFIG_STM32H7_TIM1_PWM) + #if defined(CONFIG_STM32_TIM1_PWM) ret = pwm_register("/dev/pwm0", pwm); if (ret < 0) { @@ -93,7 +93,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32H7_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) ret = pwm_register("/dev/pwm2", pwm); if (ret < 0) { diff --git a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c index 668f6ac2e23..73ddf89178f 100644 --- a/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c +++ b/boards/arm/stm32h7/nucleo-h753zi/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "nucleo-h753zi.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig index ad92a680c99..8bca8857583 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -75,9 +76,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SDMMC1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig index 42eadf579ad..5cf6dd2376c 100644 --- a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -72,11 +73,11 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_COMPOSITE=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig index 51e03a5d33f..e3de0edfcde 100644 --- a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig index 5122941e7e5..6c37d27f4ad 100644 --- a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig +++ b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="openh743i" CONFIG_ARCH_BOARD_OPENH743I=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743II=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,12 +56,12 @@ CONFIG_STACK_USAGE=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_OTGFS_HOST=y -CONFIG_STM32H7_OTGHS=y -CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y -CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_OTGFS_HOST=y +CONFIG_STM32_OTGHS=y +CONFIG_STM32_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32_SYSCFG_IOCOMPENSATION=y CONFIG_SYSTEM_CDCACM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=32 diff --git a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt index d6e3a6040cb..7e8e6aa2334 100644 --- a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt +++ b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c) -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Makefile index eda04e7c3af..c9f0115dbab 100644 --- a/boards/arm/stm32h7/openh743i/src/Makefile +++ b/boards/arm/stm32h7/openh743i/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h index 1645ce01182..ffab25f074b 100644 --- a/boards/arm/stm32h7/openh743i/src/openh743i.h +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -105,7 +105,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SDMMC +#ifdef CONFIG_STM32_SDMMC int stm32_sdio_initialize(void); #endif @@ -118,7 +118,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_boot.c b/boards/arm/stm32h7/openh743i/src/stm32_boot.c index df105a23b30..77c613755ab 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_boot.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_boot.c @@ -52,7 +52,7 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) +#if defined(CONFIG_STM32_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c index 1bf485416d9..a9dbd9ae9e7 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c @@ -38,7 +38,7 @@ # include #endif -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS # include "stm32_usbhost.h" #endif @@ -91,7 +91,7 @@ int stm32_bringup(void) usbdev_rndis_initialize(mac); #endif -#if defined(CONFIG_STM32H7_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) +#if defined(CONFIG_STM32_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) /* Initialize the SDIO block driver */ ret = stm32_sdio_initialize(); diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c index 600ace9250a..eb8a354de6a 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -45,13 +45,13 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32H7_SDMMC1 +#ifndef CONFIG_STM32_SDMMC1 # error SDMMC1 supported only #endif /* If IDMA is enabled, internal SRAM must be excluded from heap */ -#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) +#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32_SDMMC_IDMA) # error SDMMC1 with IDMA does not work CONFIG_MM_REGIONS > 1 #endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c index 5e53687605c..59dbdf27b08 100644 --- a/boards/arm/stm32h7/openh743i/src/stm32_usb.c +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -44,7 +44,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +#if defined(CONFIG_STM32_OTGFS_HOST) && defined(CONFIG_STM32_OTGHS_USBDEV) # ifndef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON # error PWRON must be disabled for this configuration # endif @@ -121,7 +121,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -307,7 +307,7 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) uinfo("resume: %d\n", resume); } -#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +#ifdef CONFIG_STM32_OTGHS_EXTERNAL_ULPI /**************************************************************************** * Name: stm32_usbulpireset * diff --git a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig index c8778936d3e..f324baba7d7 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/jumbo_cm7/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,9 +57,9 @@ CONFIG_SIGNAL_FD=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_I2C1=y -CONFIG_STM32H7_I2C3=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_I2CTOOL=y diff --git a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig index e3c035673f4..8b65fcd4526 100644 --- a/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/portenta-h7/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="portenta-h7" CONFIG_ARCH_BOARD_PORTENTA_H7=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,6 +43,6 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld index ad17d4464f0..b6cbb61a0c1 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash.ld @@ -28,7 +28,7 @@ # define FLASH_START 0x08000000 #endif -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -46,7 +46,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = FLASH_START, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K diff --git a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld index c8122812f94..8627f095004 100644 --- a/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/portenta-h7/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c index a61fab1bb64..cfbcb8fec4c 100644 --- a/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c +++ b/boards/arm/stm32h7/portenta-h7/src/stm32_bringup.c @@ -85,16 +85,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig index 5690c750d37..e1284a69ff0 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig @@ -6,15 +6,16 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -65,15 +66,15 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0x24020000 -CONFIG_STM32H7_LTDC_FB_SIZE=261120 -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0x24020000 +CONFIG_STM32_LTDC_FB_SIZE=261120 +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig index a8fe4e516ef..ea4a80f74f3 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/netnsh/defconfig @@ -6,11 +6,12 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -63,19 +64,19 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_ETHMAC=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_MII=y -CONFIG_STM32H7_PHYADDR=1 -CONFIG_STM32H7_PHYSR=31 -CONFIG_STM32H7_PHYSR_100FD=0x0018 -CONFIG_STM32H7_PHYSR_100HD=0x0008 -CONFIG_STM32H7_PHYSR_10FD=0x0014 -CONFIG_STM32H7_PHYSR_10HD=0x0004 -CONFIG_STM32H7_PHYSR_ALTCONFIG=y -CONFIG_STM32H7_PHYSR_ALTMODE=0x001c -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_ETHMAC=y +CONFIG_STM32_FMC=y +CONFIG_STM32_MII=y +CONFIG_STM32_PHYADDR=1 +CONFIG_STM32_PHYSR=31 +CONFIG_STM32_PHYSR_100FD=0x0018 +CONFIG_STM32_PHYSR_100HD=0x0008 +CONFIG_STM32_PHYSR_10FD=0x0014 +CONFIG_STM32_PHYSR_10HD=0x0004 +CONFIG_STM32_PHYSR_ALTCONFIG=y +CONFIG_STM32_PHYSR_ALTMODE=0x001c +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig index c138b61ca01..28dcea36030 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -41,9 +42,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig index b1c3acf72f0..d4f0bbb49a9 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -38,9 +39,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_UART7=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_UART7=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART7_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig index d3dd2789880..35697fcdf37 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm4_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM4=y @@ -43,7 +44,7 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig index e02a55c70a6..dcee32242f0 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,9 +43,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig index 52f90e5c3f8..9ee4b9596d6 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/nsh_cm7_rptun/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_CUTERM=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig index d187e442ce2..665a08ff3b2 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/touchtest/defconfig @@ -6,12 +6,13 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h745i-disco" CONFIG_ARCH_BOARD_STM32H745I_DISCO=y CONFIG_ARCH_BOARD_STM32H745I_DISCO_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H745XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -51,10 +52,10 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY=y -CONFIG_STM32H7_USART3=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_PWR_DIRECT_SMPS_SUPPLY=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h745i-disco/include/board.h b/boards/arm/stm32h7/stm32h745i-disco/include/board.h index 1593c65b032..4a60a547713 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/include/board.h +++ b/boards/arm/stm32h7/stm32h745i-disco/include/board.h @@ -343,7 +343,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld index e0f982d7c64..3ed5b169c6c 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash.ld @@ -97,7 +97,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -115,7 +115,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -192,7 +192,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld index 74787002507..98296d3ffd1 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h745i-disco/scripts/flash_m4.ld @@ -22,9 +22,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -34,7 +34,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt index 424170bc1a1..bb605d54ac7 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h745i-disco/src/CMakeLists.txt @@ -28,7 +28,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -44,7 +44,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile index 59db9b7cd6a..13359572cb5 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h745i-disco/src/Makefile @@ -30,7 +30,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -46,7 +46,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c index 24b15202874..24c252bc0cc 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c index 5af6ac7f31f..def80baa810 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_bringup.c @@ -35,7 +35,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c index df62ee84f7d..639db95d733 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_ft5x06.c @@ -49,8 +49,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c index 7a5b17ad617..eb02f937d6e 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_lcd.c @@ -39,7 +39,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c index d08defcdbc5..07f43943a3e 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32h745i_disco.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h index 57ef2b05e63..5a2ec9fad06 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h +++ b/boards/arm/stm32h7/stm32h745i-disco/src/stm32h745i_disco.h @@ -44,7 +44,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -184,7 +184,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -198,7 +198,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig index 43a7a87143c..3ddf480334a 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32h7/stm32h747i-disco/configs/nsh/defconfig @@ -8,11 +8,12 @@ # CONFIG_NSH_DISABLE_IFCONFIG is not set # CONFIG_NSH_DISABLE_PS is not set # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_CORTEXM4_ENABLED is not set +# CONFIG_STM32_CORTEXM4_ENABLED is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h747i-disco" CONFIG_ARCH_BOARD_STM32H747I_DISCO=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H747XI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -44,7 +45,7 @@ CONFIG_SPI=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt index 2aff1364c44..4583b43c5e7 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h747i-disco/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_OTGHS) +if(CONFIG_STM32_OTGHS) list(APPEND SRCS stm32_usb.c) endif() @@ -48,7 +48,7 @@ if(CONFIG_BOARDCTL_UNIQUEID) list(APPEND SRCS stm32_uid.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile index 788e0f0d91f..2f0eaeee20f 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/Makefile +++ b/boards/arm/stm32h7/stm32h747i-disco/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -ifeq ($(CONFIG_STM32H7_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32H7_OTGHS),y) +ifeq ($(CONFIG_STM32_OTGHS),y) CSRCS += stm32_usb.c endif @@ -50,7 +50,7 @@ ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) CSRCS += stm32_uid.c endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c index 89c9a723d69..de53c2b8742 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_adc.c @@ -48,9 +48,9 @@ /* Up to 3 ADC interfaces are supported */ -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ - defined(CONFIG_STM32H7_ADC3) -#ifndef CONFIG_STM32H7_ADC1 +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 # warning "Channel information only available for ADC1" #endif @@ -63,7 +63,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32H7_ADC1 +#ifdef CONFIG_STM32_ADC1 /* Identifying number of each ADC channel: Variable Resistor. * * ADC1: {5, 10, 12, 13, 15}; @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32H7_ADC3 +#ifdef CONFIG_STM32_ADC3 /* Identifying number of each ADC channel: Variable Resistor. * * ADC3: {6,}; @@ -124,7 +124,7 @@ static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = int stm32_adc_setup(void) { -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) static bool initialized = false; struct adc_dev_s *adc; int ret; @@ -136,7 +136,7 @@ int stm32_adc_setup(void) if (!initialized) { #endif -#if defined(CONFIG_STM32H7_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC1_NCHANNELS; i++) @@ -167,7 +167,7 @@ int stm32_adc_setup(void) devname[8]++; #endif -#if defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC3) /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < ADC3_NCHANNELS; i++) @@ -197,7 +197,7 @@ int stm32_adc_setup(void) } #endif -#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC3) /* Now we are initialized */ initialized = true; @@ -209,5 +209,5 @@ int stm32_adc_setup(void) #endif } -#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c index 595a6acb393..b994aaeeab1 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_boot.c @@ -58,13 +58,13 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGHS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGHS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); #endif -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /* Configure SPI chip selects */ stm32_spidev_initialize(); diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c index 84e93d0e997..12a8a37d4fd 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_bringup.c @@ -90,16 +90,16 @@ static void stm32_i2c_register(int bus) #if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) static void stm32_i2ctool(void) { -#ifdef CONFIG_STM32H7_I2C1 +#ifdef CONFIG_STM32_I2C1 stm32_i2c_register(1); #endif -#ifdef CONFIG_STM32H7_I2C2 +#ifdef CONFIG_STM32_I2C2 stm32_i2c_register(2); #endif -#ifdef CONFIG_STM32H7_I2C3 +#ifdef CONFIG_STM32_I2C3 stm32_i2c_register(3); #endif -#ifdef CONFIG_STM32H7_I2C4 +#ifdef CONFIG_STM32_I2C4 stm32_i2c_register(4); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c index a5885be43e0..b038469e60b 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "stm32h747i-disco.h" #include -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -91,7 +91,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -105,7 +105,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -119,7 +119,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -143,7 +143,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -157,7 +157,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 void stm32_spi5select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -171,7 +171,7 @@ uint8_t stm32_spi5status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 void stm32_spi6select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -209,42 +209,42 @@ uint8_t stm32_spi6status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI5 +#ifdef CONFIG_STM32_SPI5 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32H7_SPI6 +#ifdef CONFIG_STM32_SPI6 int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; @@ -252,4 +252,4 @@ int stm32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32H7_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c index 7295b74cebe..84c95e9204b 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "stm32h747i-disco.h" -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS /**************************************************************************** * Pre-processor Definitions @@ -54,7 +54,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32H7_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGHS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -132,7 +132,7 @@ void stm32_usbinitialize(void) { /* Configure the Overcurrent GPIO */ -#ifdef CONFIG_STM32H7_OTGHS +#ifdef CONFIG_STM32_OTGHS stm32_configgpio(GPIO_OTGHS_OVER); #endif } diff --git a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h index c53bb6f8a76..e1e5d28eedf 100644 --- a/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h +++ b/boards/arm/stm32h7/stm32h747i-disco/src/stm32h747i-disco.h @@ -95,7 +95,7 @@ /* SD/TF Card'detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif @@ -129,7 +129,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI +#ifdef CONFIG_STM32_SPI void stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig index f4913aa50bb..66fe8ef9f05 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h750b-dk/configs/lvgl/defconfig @@ -6,14 +6,15 @@ # modifications. # # CONFIG_STANDARD_SERIAL is not set -# CONFIG_STM32H7_FB_CMAP is not set -# CONFIG_STM32H7_LTDC_L1_CHROMAKEYEN is not set -# CONFIG_STM32H7_LTDC_L2 is not set +# CONFIG_STM32_FB_CMAP is not set +# CONFIG_STM32_LTDC_L1_CHROMAKEYEN is not set +# CONFIG_STM32_LTDC_L2 is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32h750b-dk" CONFIG_ARCH_BOARD_STM32H750B_DK=y CONFIG_ARCH_BOARD_STM32H750B_DK_TOUCHSCREEN_SWAPXY=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750XB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -67,14 +68,14 @@ CONFIG_SIG_DEFAULT=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32H7_DMA1=y -CONFIG_STM32H7_DMA2=y -CONFIG_STM32H7_FMC=y -CONFIG_STM32H7_I2C4=y -CONFIG_STM32H7_LTDC=y -CONFIG_STM32H7_LTDC_FB_BASE=0xd0000000 -CONFIG_STM32H7_LTDC_FB_SIZE=522240 -CONFIG_STM32H7_USART3=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FMC=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LTDC=y +CONFIG_STM32_LTDC_FB_BASE=0xd0000000 +CONFIG_STM32_LTDC_FB_SIZE=522240 +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TTY_SIGINT=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/stm32h750b-dk/include/board.h b/boards/arm/stm32h7/stm32h750b-dk/include/board.h index c63ca3b3fdc..62830d321eb 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/include/board.h +++ b/boards/arm/stm32h7/stm32h750b-dk/include/board.h @@ -340,7 +340,7 @@ #define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK -#if CONFIG_STM32H7_FMC +#if CONFIG_STM32_FMC # define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) # if FMC_SDCLK_FREQUENCY > 100000000 # error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld index eae68e2f5a1..d08b0b9d475 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash.ld @@ -95,7 +95,7 @@ #include -#ifndef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifndef CONFIG_STM32_CORTEXM4_ENABLED MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K @@ -114,7 +114,7 @@ MEMORY MEMORY { itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K - flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32H7_CORTEXM7_FLASH_SIZE + flash (rx) : ORIGIN = 0x08000000, LENGTH = CONFIG_STM32_CORTEXM7_FLASH_SIZE dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K @@ -191,7 +191,7 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram -#ifdef CONFIG_STM32H7_CORTEXM4_ENABLED +#ifdef CONFIG_STM32_CORTEXM4_ENABLED .shmem (NOLOAD): { . = ALIGN(4); diff --git a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld index ed39a30ec56..d6f3372fd37 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld +++ b/boards/arm/stm32h7/stm32h750b-dk/scripts/flash_m4.ld @@ -20,9 +20,9 @@ #include -#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) +#define STM32M4_FLASH_START (0x08000000 + CONFIG_STM32_CORTEXM7_FLASH_SIZE) -#if CONFIG_STM32H7_CORTEXM7_FLASH_SIZE != 1048576 +#if CONFIG_STM32_CORTEXM7_FLASH_SIZE != 1048576 # error TODO: not supported yet - BCM4_ADD0 must be configured #endif @@ -32,7 +32,7 @@ MEMORY { flash (rx) : ORIGIN = STM32M4_FLASH_START, - LENGTH = (2048K - CONFIG_STM32H7_CORTEXM7_FLASH_SIZE) + LENGTH = (2048K - CONFIG_STM32_CORTEXM7_FLASH_SIZE) /* SRAM1 and SRAM2 */ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt index d89067b817f..4424e927661 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt +++ b/boards/arm/stm32h7/stm32h750b-dk/src/CMakeLists.txt @@ -26,7 +26,7 @@ else() list(APPEND SRCS stm32_userleds.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() @@ -42,7 +42,7 @@ if(CONFIG_INPUT_FT5X06) list(APPEND SRCS stm32_ft5x06.c) endif() -if(CONFIG_STM32H7_LTDC) +if(CONFIG_STM32_LTDC) list(APPEND SRCS stm32_lcd.c) endif() diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile index 7dec83d2100..942bfb9fd3e 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/Makefile +++ b/boards/arm/stm32h7/stm32h750b-dk/src/Makefile @@ -28,7 +28,7 @@ else CSRCS += stm32_userleds.c endif -ifeq ($(CONFIG_STM32H7_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif @@ -44,7 +44,7 @@ ifeq ($(CONFIG_INPUT_FT5X06),y) CSRCS += stm32_ft5x06.c endif -ifeq ($(CONFIG_STM32H7_LTDC),y) +ifeq ($(CONFIG_STM32_LTDC),y) CSRCS += stm32_lcd.c endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c index 0095a26c9b8..414344c964a 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_boot.c @@ -54,7 +54,7 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32H7_OTGFS) || defined(CONFIG_STM32H7_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32H7_HOST) /* Initialize USB */ stm32_usbinitialize(); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c index a7200dffe19..8282101411b 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_bringup.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS #include "stm32_usbhost.h" #endif diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c index e719e3ac6fd..72e3d357b34 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_ft5x06.c @@ -47,8 +47,8 @@ # error "FT5x06 support requires CONFIG_INPUT" #endif -#ifndef CONFIG_STM32H7_I2C4 -# error "FT5x06 support requires CONFIG_STM32H7_I2C4" +#ifndef CONFIG_STM32_I2C4 +# error "FT5x06 support requires CONFIG_STM32_I2C4" #endif #ifndef CONFIG_FT5X06_I2CDEV diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c index de3e72c627f..9ffca9632b1 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_lcd.c @@ -37,7 +37,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_LTDC +#ifdef CONFIG_STM32_LTDC /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c index 882307c6985..50d12205e65 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32_usb.c @@ -43,7 +43,7 @@ #include "stm32h750b-dk.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -136,7 +136,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h index 5e0e6b7f2de..ff114ac8193 100644 --- a/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h +++ b/boards/arm/stm32h7/stm32h750b-dk/src/stm32h750b-dk.h @@ -42,7 +42,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -182,7 +182,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif @@ -196,7 +196,7 @@ void weak_function stm32_usbinitialize(void); * ****************************************************************************/ -#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) int stm32_usbhost_initialize(void); #endif diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig index 3a3b4caf7f8..3ed170d4cce 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -43,7 +44,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig index bb9f06926d9..52d6fd71d4d 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -58,10 +59,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig index 5aedb0aecee..fc9b8d1a017 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -55,8 +56,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig index 53715932255..e2a79412f1c 100644 --- a/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h743/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h743" CONFIG_ARCH_BOARD_WEACT_STM32H743=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H743VI=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -47,9 +48,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt index af3c82ac515..6f41b679d00 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt @@ -34,7 +34,7 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Makefile index 3d686ef415e..0bbd3d18694 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h743/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c index 4c09ec8ce10..6173d41518e 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c index a11654bc8fa..91513bcf091 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c index eb46659de26..4aff43a107a 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h743.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h index 34f91044d7e..c97eb79129b 100644 --- a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h +++ b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig index 70ab99d673a..edb8697b24e 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -42,7 +43,7 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig index d1fa7662bd6..ffe5056a984 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/sdcard/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -59,10 +60,10 @@ CONFIG_SDMMC1_SDIO_MODE=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_PWR=y -CONFIG_STM32H7_RTC=y -CONFIG_STM32H7_SDMMC1=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SDMMC1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig index 5098495e7f2..df870df8aef 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/st7735/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -56,8 +57,8 @@ CONFIG_SPI_CMDDATA=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_SPI4=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_SPI4=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig index f8e8e730321..bb2110e2862 100644 --- a/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig +++ b/boards/arm/stm32h7/weact-stm32h750/configs/usbnsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="weact-stm32h750" CONFIG_ARCH_BOARD_WEACT_STM32H750=y CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32H750VB=y CONFIG_ARCH_CHIP_STM32H7=y CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y @@ -48,9 +49,9 @@ CONFIG_SPI=y CONFIG_START_DAY=11 CONFIG_START_MONTH=5 CONFIG_START_YEAR=2024 -CONFIG_STM32H7_HSI48=y -CONFIG_STM32H7_OTGFS=y -CONFIG_STM32H7_USART1=y +CONFIG_STM32_HSI48=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt index 6c5220cccc2..2d990344622 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt +++ b/boards/arm/stm32h7/weact-stm32h750/src/CMakeLists.txt @@ -34,15 +34,15 @@ if(CONFIG_VIDEO_FB) endif() endif() -if(CONFIG_STM32H7_SPI) +if(CONFIG_STM32_SPI) list(APPEND SRCS stm32_spi.c) endif() -if(CONFIG_STM32H7_SDMMC) +if(CONFIG_STM32_SDMMC) list(APPEND SRCS stm32_sdmmc.c) endif() -if(CONFIG_STM32H7_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32h7/weact-stm32h750/src/Makefile b/boards/arm/stm32h7/weact-stm32h750/src/Makefile index 80033455ab3..083f46024de 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/Makefile +++ b/boards/arm/stm32h7/weact-stm32h750/src/Makefile @@ -36,7 +36,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif endif -ifeq ($(CONFIG_STM32H7_SDMMC),y) +ifeq ($(CONFIG_STM32_SDMMC),y) CSRCS += stm32_sdmmc.c endif diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c index 34102ce9f2d..4c9423b7a3b 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_boot.c @@ -52,9 +52,9 @@ void stm32_boardinitialize(void) { -#if defined(CONFIG_STM32H7_SPI1) || defined(CONFIG_STM32H7_SPI2) || \ - defined(CONFIG_STM32H7_SPI3) || defined(CONFIG_STM32H7_SPI4) || \ - defined(CONFIG_STM32H7_SPI6) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) || defined(CONFIG_STM32_SPI4) || \ + defined(CONFIG_STM32_SPI6) /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak * function stm32_spidev_initialize() has been brought into the link. */ diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c index 226882d0e6c..46b87280b62 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_spi.c @@ -87,7 +87,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 void stm32_spi4select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -130,7 +130,7 @@ uint8_t stm32_spi4status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32H7_SPI4 +#ifdef CONFIG_STM32_SPI4 int stm32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_ST7735 diff --git a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c index ca8e4cbab7b..506bb238ed0 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c +++ b/boards/arm/stm32h7/weact-stm32h750/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32_otg.h" #include "weact-stm32h750.h" -#ifdef CONFIG_STM32H7_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h index ecf03db7907..26c286a16b3 100644 --- a/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h +++ b/boards/arm/stm32h7/weact-stm32h750/src/weact-stm32h750.h @@ -53,7 +53,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32H7_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -88,7 +88,7 @@ # undef HAVE_USBMONITOR #endif -#if !defined(CONFIG_STM32H7_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) +#if !defined(CONFIG_STM32_PROGMEM) || !defined(CONFIG_MTD_PROGMEM) # undef HAVE_PROGMEM_CHARDEV #endif @@ -131,7 +131,7 @@ * PD4 Card detected pin */ -#if defined(CONFIG_STM32H7_SDMMC1) +#if defined(CONFIG_STM32_SDMMC1) # define HAVE_SDIO #endif From 0d4a9cf1c83c0340a704e0ea1db0ffc51457eeb7 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:39 +0200 Subject: [PATCH 089/268] !arch/stm32l4: use common STM32 Kconfig symbols BREAKING CHANGE: STM32L4 Kconfig symbols were renamed from CONFIG_STM32L4_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32l4/boards/nucleo-l496zg/index.rst | 2 +- .../boards/stm32l476vg-disco/index.rst | 2 +- .../boards/stm32l4r9ai-disco/index.rst | 8 +- Documentation/platforms/arm/stm32l4/index.rst | 6 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32l4/chip.h | 58 +- arch/arm/include/stm32l4/irq.h | 8 +- arch/arm/include/stm32l4/stm32l4x3xx_irq.h | 2 +- arch/arm/include/stm32l4/stm32l4x6xx_irq.h | 4 +- arch/arm/src/stm32l4/CMakeLists.txt | 46 +- arch/arm/src/stm32l4/Kconfig | 6324 ++--------------- arch/arm/src/stm32l4/Make.defs | 48 +- arch/arm/src/stm32l4/hardware/stm32l4_adc.h | 18 +- arch/arm/src/stm32l4/hardware/stm32l4_comp.h | 6 +- arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h | 24 +- arch/arm/src/stm32l4/hardware/stm32l4_flash.h | 118 +- .../src/stm32l4/hardware/stm32l4_memorymap.h | 8 +- .../arm/src/stm32l4/hardware/stm32l4_pinmap.h | 8 +- arch/arm/src/stm32l4/hardware/stm32l4_pwr.h | 16 +- .../arm/src/stm32l4/hardware/stm32l4_syscfg.h | 8 +- .../arm/src/stm32l4/hardware/stm32l4_usbdev.h | 4 +- .../src/stm32l4/hardware/stm32l4x3xx_rcc.h | 4 +- .../src/stm32l4/hardware/stm32l4x3xx_syscfg.h | 4 +- .../src/stm32l4/hardware/stm32l4x5xx_rcc.h | 4 +- .../src/stm32l4/hardware/stm32l4x5xx_syscfg.h | 4 +- .../src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h | 4 +- .../stm32l4/hardware/stm32l4x6xx_firewall.h | 4 +- .../src/stm32l4/hardware/stm32l4x6xx_rcc.h | 6 +- .../src/stm32l4/hardware/stm32l4x6xx_syscfg.h | 4 +- .../src/stm32l4/hardware/stm32l4xrxx_rcc.h | 4 +- .../src/stm32l4/hardware/stm32l4xrxx_syscfg.h | 4 +- arch/arm/src/stm32l4/stm32l4_1wire.c | 30 +- arch/arm/src/stm32l4/stm32l4_adc.c | 172 +- arch/arm/src/stm32l4/stm32l4_adc.h | 290 +- arch/arm/src/stm32l4/stm32l4_allocateheap.c | 16 +- arch/arm/src/stm32l4/stm32l4_can.c | 36 +- arch/arm/src/stm32l4/stm32l4_can.h | 30 +- arch/arm/src/stm32l4/stm32l4_comp.c | 16 +- arch/arm/src/stm32l4/stm32l4_comp.h | 2 +- arch/arm/src/stm32l4/stm32l4_dac.c | 230 +- arch/arm/src/stm32l4/stm32l4_dac.h | 46 +- arch/arm/src/stm32l4/stm32l4_dbgmcu.h | 8 +- arch/arm/src/stm32l4/stm32l4_dfsdm.c | 52 +- arch/arm/src/stm32l4/stm32l4_dfsdm.h | 26 +- arch/arm/src/stm32l4/stm32l4_dfumode.c | 4 +- arch/arm/src/stm32l4/stm32l4_dfumode.h | 2 +- arch/arm/src/stm32l4/stm32l4_dma.c | 6 +- arch/arm/src/stm32l4/stm32l4_dma.h | 18 +- arch/arm/src/stm32l4/stm32l4_exti.h | 2 +- arch/arm/src/stm32l4/stm32l4_exti_comp.c | 4 +- arch/arm/src/stm32l4/stm32l4_firewall.h | 8 +- arch/arm/src/stm32l4/stm32l4_flash.c | 22 +- arch/arm/src/stm32l4/stm32l4_freerun.c | 4 +- arch/arm/src/stm32l4/stm32l4_freerun.h | 4 +- arch/arm/src/stm32l4/stm32l4_gpio.c | 8 +- arch/arm/src/stm32l4/stm32l4_gpio.h | 4 +- arch/arm/src/stm32l4/stm32l4_hsi48.h | 4 +- arch/arm/src/stm32l4/stm32l4_i2c.c | 96 +- arch/arm/src/stm32l4/stm32l4_i2c.h | 8 +- arch/arm/src/stm32l4/stm32l4_idle.c | 2 +- arch/arm/src/stm32l4/stm32l4_iwdg.c | 18 +- arch/arm/src/stm32l4/stm32l4_lptim.c | 52 +- arch/arm/src/stm32l4/stm32l4_lse.c | 26 +- arch/arm/src/stm32l4/stm32l4_oneshot.c | 12 +- arch/arm/src/stm32l4/stm32l4_oneshot.h | 20 +- arch/arm/src/stm32l4/stm32l4_otgfs.h | 8 +- arch/arm/src/stm32l4/stm32l4_otgfsdev.c | 14 +- arch/arm/src/stm32l4/stm32l4_otgfshost.c | 82 +- arch/arm/src/stm32l4/stm32l4_pmstop.c | 2 +- arch/arm/src/stm32l4/stm32l4_pulsecount.c | 96 +- arch/arm/src/stm32l4/stm32l4_pwm.c | 618 +- arch/arm/src/stm32l4/stm32l4_pwm.h | 512 +- arch/arm/src/stm32l4/stm32l4_pwr.c | 2 +- arch/arm/src/stm32l4/stm32l4_pwr.h | 6 +- arch/arm/src/stm32l4/stm32l4_qencoder.c | 106 +- arch/arm/src/stm32l4/stm32l4_qencoder.h | 24 +- arch/arm/src/stm32l4/stm32l4_qspi.c | 70 +- arch/arm/src/stm32l4/stm32l4_qspi.h | 4 +- arch/arm/src/stm32l4/stm32l4_rcc.c | 18 +- arch/arm/src/stm32l4/stm32l4_rcc.h | 14 +- arch/arm/src/stm32l4/stm32l4_rng.c | 4 +- arch/arm/src/stm32l4/stm32l4_rtc.c | 36 +- arch/arm/src/stm32l4/stm32l4_rtc.h | 20 +- arch/arm/src/stm32l4/stm32l4_sai.c | 66 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 146 +- arch/arm/src/stm32l4/stm32l4_serial.c | 100 +- arch/arm/src/stm32l4/stm32l4_spi.c | 78 +- arch/arm/src/stm32l4/stm32l4_spi.h | 12 +- arch/arm/src/stm32l4/stm32l4_start.c | 2 +- arch/arm/src/stm32l4/stm32l4_tickless.c | 20 +- arch/arm/src/stm32l4/stm32l4_tim.c | 268 +- arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c | 56 +- arch/arm/src/stm32l4/stm32l4_uart.h | 106 +- arch/arm/src/stm32l4/stm32l4_usbdev.c | 16 +- arch/arm/src/stm32l4/stm32l4_usbhost.h | 22 +- arch/arm/src/stm32l4/stm32l4_wdg.h | 4 +- arch/arm/src/stm32l4/stm32l4x3xx_rcc.c | 104 +- arch/arm/src/stm32l4/stm32l4x5xx_rcc.c | 108 +- arch/arm/src/stm32l4/stm32l4x6xx_dma.c | 2 +- arch/arm/src/stm32l4/stm32l4x6xx_rcc.c | 126 +- arch/arm/src/stm32l4/stm32l4xrxx_dma.c | 34 +- arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 120 +- boards/arm/stm32l4/b-l475e-iot01a/Kconfig | 4 +- .../b-l475e-iot01a/configs/nsh/defconfig | 5 +- .../configs/spirit-6lowpan/defconfig | 5 +- .../configs/spirit-starhub/defconfig | 5 +- .../configs/spirit-starpoint/defconfig | 5 +- .../include/b-l475e-iot01a_clock.h | 4 +- .../b-l475e-iot01a/src/b-l475e-iot01a.h | 10 +- .../stm32l4/b-l475e-iot01a/src/stm32_boot.c | 2 +- .../stm32l4/b-l475e-iot01a/src/stm32_spi.c | 34 +- .../stm32l4/b-l475e-iot01a/src/stm32_timer.c | 22 +- boards/arm/stm32l4/nucleo-l432kc/Kconfig | 22 +- .../nucleo-l432kc/configs/nsh/defconfig | 19 +- .../nucleo-l432kc/configs/spwm/defconfig | 25 +- .../nucleo-l432kc/configs/wgen/defconfig | 35 +- .../arm/stm32l4/nucleo-l432kc/include/board.h | 2 +- .../nucleo-l432kc/include/nucleo-l432kc.h | 10 +- .../stm32l4/nucleo-l432kc/src/CMakeLists.txt | 4 +- boards/arm/stm32l4/nucleo-l432kc/src/Makefile | 4 +- .../stm32l4/nucleo-l432kc/src/nucleo-l432kc.h | 6 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_adc.c | 10 +- .../stm32l4/nucleo-l432kc/src/stm32_at45db.c | 2 +- .../stm32l4/nucleo-l432kc/src/stm32_boot.c | 6 +- .../stm32l4/nucleo-l432kc/src/stm32_bringup.c | 26 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_dac.c | 4 +- .../stm32l4/nucleo-l432kc/src/stm32_dac7571.c | 2 +- .../nucleo-l432kc/src/stm32_dac_wgen.c | 14 +- .../stm32l4/nucleo-l432kc/src/stm32_ina219.c | 2 +- .../stm32l4/nucleo-l432kc/src/stm32_ina226.c | 2 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c | 12 +- .../arm/stm32l4/nucleo-l432kc/src/stm32_spi.c | 24 +- .../stm32l4/nucleo-l432kc/src/stm32_spwm.c | 10 +- .../nucleo-l452re/configs/nsh/defconfig | 29 +- .../nucleo-l452re/include/nucleo-l452re.h | 10 +- .../stm32l4/nucleo-l452re/src/nucleo-l452re.h | 14 +- .../arm/stm32l4/nucleo-l452re/src/stm32_adc.c | 4 +- .../stm32l4/nucleo-l452re/src/stm32_bringup.c | 2 +- .../arm/stm32l4/nucleo-l452re/src/stm32_dac.c | 2 +- .../arm/stm32l4/nucleo-l452re/src/stm32_spi.c | 24 +- .../nucleo-l476rg/configs/nsh/defconfig | 19 +- .../nucleo-l476rg/configs/nxdemo/defconfig | 21 +- .../nucleo-l476rg/include/nucleo-l476rg.h | 4 +- .../stm32l4/nucleo-l476rg/src/nucleo-l476rg.h | 8 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_adc.c | 4 +- .../nucleo-l476rg/src/stm32_ajoystick.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_boot.c | 4 +- .../stm32l4/nucleo-l476rg/src/stm32_bringup.c | 12 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_can.c | 6 +- .../nucleo-l476rg/src/stm32_lsm303agr.c | 6 +- .../stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c | 6 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c | 22 +- .../arm/stm32l4/nucleo-l476rg/src/stm32_spi.c | 26 +- .../nucleo-l476rg/src/stm32_spimmcsd.c | 2 +- .../nucleo-l496zg/configs/nsh/defconfig | 59 +- .../arm/stm32l4/nucleo-l496zg/include/board.h | 6 +- .../stm32l4/nucleo-l496zg/src/CMakeLists.txt | 4 +- boards/arm/stm32l4/nucleo-l496zg/src/Makefile | 4 +- .../stm32l4/nucleo-l496zg/src/nucleo-144.h | 8 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_adc.c | 28 +- .../stm32l4/nucleo-l496zg/src/stm32_boot.c | 2 +- .../stm32l4/nucleo-l496zg/src/stm32_bringup.c | 26 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_dac.c | 8 +- .../stm32l4/nucleo-l496zg/src/stm32_dfsdm.c | 20 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_spi.c | 30 +- .../arm/stm32l4/nucleo-l496zg/src/stm32_usb.c | 4 +- .../steval-stlcs01v1/configs/lwl/defconfig | 3 +- .../steval-stlcs01v1/configs/usbnsh/defconfig | 7 +- .../stm32l4/steval-stlcs01v1/include/board.h | 4 +- .../steval-stlcs01v1/src/CMakeLists.txt | 2 +- .../arm/stm32l4/steval-stlcs01v1/src/Makefile | 2 +- .../steval-stlcs01v1/src/steval-stlcs01v1.h | 2 +- .../stm32l4/steval-stlcs01v1/src/stm32_boot.c | 2 +- .../stm32l4/steval-stlcs01v1/src/stm32_usb.c | 6 +- .../stm32l476-mdk/configs/nsh/defconfig | 17 +- .../stm32l4/stm32l476-mdk/src/CMakeLists.txt | 2 +- boards/arm/stm32l4/stm32l476-mdk/src/Makefile | 2 +- .../stm32l476-mdk/src/stm32_clockconfig.c | 6 +- .../stm32l476vg-disco/configs/knsh/defconfig | 19 +- .../stm32l476vg-disco/configs/nsh/defconfig | 19 +- .../stm32l4/stm32l476vg-disco/src/Makefile | 4 +- .../stm32l476vg-disco/src/stm32_boot.c | 2 +- .../stm32l476vg-disco/src/stm32_clockconfig.c | 6 +- .../stm32l4/stm32l476vg-disco/src/stm32_usb.c | 8 +- .../stm32l476vg-disco/src/stm32l476vg-disco.h | 4 +- .../stm32l4r9ai-disco/configs/knsh/defconfig | 23 +- .../stm32l4r9ai-disco/configs/nsh/defconfig | 25 +- .../include/stm32l4r9ai-disco-clocking.h | 6 +- .../stm32l4/stm32l4r9ai-disco/src/Makefile | 10 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_adc.c | 4 +- .../stm32l4r9ai-disco/src/stm32_boot.c | 4 +- .../stm32l4r9ai-disco/src/stm32_bringup.c | 10 +- .../stm32l4r9ai-disco/src/stm32_clockconfig.c | 6 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_dac.c | 2 +- .../stm32l4r9ai-disco/src/stm32_dfsdm.c | 20 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_spi.c | 28 +- .../stm32l4/stm32l4r9ai-disco/src/stm32_usb.c | 8 +- .../stm32l4r9ai-disco/src/stm32l4r9ai-disco.h | 8 +- 198 files changed, 3314 insertions(+), 8787 deletions(-) diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst index 0080c9db8d2..89df8dc28f4 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l496zg/index.rst @@ -153,7 +153,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL:: Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L4_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst index f3eb6fc33a3..c1d763f67d7 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l476vg-disco/index.rst @@ -468,7 +468,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings:: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst index ddec498f57d..b87198bfdd5 100644 --- a/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/stm32l4r9ai-disco/index.rst @@ -130,7 +130,7 @@ Pins and Connectors:: To configure USART1 as the console:: - CONFIG_STM32L4_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -172,7 +172,7 @@ Pins and Connectors:: To configure USART2 as the console:: - CONFIG_STM32L4_USART2=y + CONFIG_STM32_USART2=y CONFIG_USART2_SERIALDRIVER=y CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USART2_RXBUFSIZE=256 @@ -192,7 +192,7 @@ Pins and Connectors:: To configure USART4 as the console:: - CONFIG_STM32L4_UART4=y + CONFIG_STM32_UART4=y CONFIG_USART4_SERIALDRIVER=y CONFIG_USART4_SERIAL_CONSOLE=y CONFIG_USART4_RXBUFSIZE=512 @@ -357,7 +357,7 @@ NOTES: not enabled in the default configuration but can be enabled with the following settings: (TODO: need to test!):: - CONFIG_STM32L4_OTGFS=y + CONFIG_STM32_OTGFS=y CONFIG_USBDEV=y CONFIG_USBDEV_SELFPOWERED=y diff --git a/Documentation/platforms/arm/stm32l4/index.rst b/Documentation/platforms/arm/stm32l4/index.rst index 6be0b2f932c..2e8e1080c39 100644 --- a/Documentation/platforms/arm/stm32l4/index.rst +++ b/Documentation/platforms/arm/stm32l4/index.rst @@ -28,9 +28,9 @@ STM32L4X6 Yes RM0351 STM32L4XR Yes RM0432 (STM32L4+) ============ ======= ====== ================================ -[1]: Please avoid depending on CONFIG_STM32L4_STM32L4X1 and -CONFIG_STM32L4_STM32L4X2 as the MCUs are of the same subfamily -as CONFIG_STM32L4_STM32L4X3. +[1]: Please avoid depending on CONFIG_STM32_STM32L4X1 and +CONFIG_STM32_STM32L4X2 as the MCUs are of the same subfamily +as CONFIG_STM32_STM32L4X3. Peripheral Support ================== diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index b4c6ffbadf3..9f092d029e4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -655,6 +655,7 @@ config ARCH_CHIP_STM32H7 config ARCH_CHIP_STM32L4 bool "STMicro STM32 L4" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 79b07b9e1c9..f8d06093bad 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -61,36 +61,36 @@ * Parts STM32L4x6xE have 512Kb of FLASH * Parts STM32L4x6xG have 1024Kb of FLASH * - * The correct FLASH size must be set with a CONFIG_STM32L4_FLASH_CONFIG_* + * The correct FLASH size must be set with a CONFIG_STM32_FLASH_CONFIG_* * selection. */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ # define STM32_SRAM3_SIZE (384*1024) /* 384Kb SRAM3 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L496XX) +#elif defined(CONFIG_STM32_STM32L496XX) # define STM32_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L475XX) || defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) +#elif defined(CONFIG_STM32_STM32L475XX) || defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) # define STM32_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) +#elif defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) # define STM32_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L432XX) || defined(CONFIG_STM32L4_STM32L433XX) +#elif defined(CONFIG_STM32_STM32L432XX) || defined(CONFIG_STM32_STM32L433XX) # define STM32_SRAM1_SIZE (48*1024) /* 48Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */ -#elif defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) +#elif defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) # define STM32_SRAM1_SIZE (32*1024) /* 32Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (8*1024) /* 8Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L4 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -119,9 +119,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -149,9 +149,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -165,7 +165,7 @@ # define STM32_NLPUART 1 /* LPUART 1 */ # define STM32_QSPI 1 /* QuadSPI1 */ # define STM32_NSPI 3 /* SPI1-3 */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define STM32_NI2C 4 /* I2C1-4 */ #else # define STM32_NI2C 3 /* I2C1-3 */ @@ -173,7 +173,7 @@ # define STM32_NSWPMI 1 /* SWPMI1 */ # define STM32_NUSBOTGFS 1 /* USB OTG FS */ # define STM32_NUSBFS 0 /* No USB FS */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define STM32_NCAN 2 /* CAN1-2 */ #else # define STM32_NCAN 1 /* CAN1 */ @@ -181,7 +181,7 @@ # define STM32_NSAI 2 /* SAI1-2 */ # define STM32_NSDMMC 1 /* SDMMC interface */ # define STM32_NDMA 2 /* DMA1-2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define STM32_NPORTS 9 /* 9 GPIO ports, GPIOA-I */ #else # define STM32_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ @@ -191,10 +191,10 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ -#if defined(CONFIG_STM32L4_STM32L451XX) || defined(CONFIG_STM32L4_STM32L452XX) || \ - defined(CONFIG_STM32L4_STM32L462XX) +#if defined(CONFIG_STM32_STM32L451XX) || defined(CONFIG_STM32_STM32L452XX) || \ + defined(CONFIG_STM32_STM32L462XX) # define STM32_NFSMC 0 /* No FSMC memory controller */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ @@ -211,14 +211,14 @@ # define STM32_NI2C 4 /* I2C1-4 */ # define STM32_NSWPMI 1 /* SWPMI1 */ # define STM32_NUSBOTGFS 0 /* No USB OTG FS */ -#if defined(CONFIG_STM32L4_STM32L451XX) +#if defined(CONFIG_STM32_STM32L451XX) # define STM32_NUSBFS 0 /* No USB FS */ #else # define STM32_NUSBFS 1 /* USB FS */ #endif # define STM32_NCAN 1 /* CAN1 */ # define STM32_NSAI 1 /* SAI1 */ -#if defined(CONFIG_STM32L4_HAVE_SDMMC1) +#if defined(CONFIG_STM32_HAVE_SDMMC1) # define STM32_NSDMMC 1 /* SDMMC interface */ #else # define STM32_NSDMMC 0 /* No SDMMC interface */ @@ -230,9 +230,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L451XX */ +#endif /* CONFIG_STM32_STM32L451XX */ -#if defined(CONFIG_STM32L4_STM32L432XX) +#if defined(CONFIG_STM32_STM32L432XX) # define STM32_NFSMC 0 /* No FSMC memory controller */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ @@ -260,9 +260,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L432XX */ +#endif /* CONFIG_STM32_STM32L432XX */ -#if defined(CONFIG_STM32L4_STM32L433XX) +#if defined(CONFIG_STM32_STM32L433XX) # define STM32_NFSMC 0 /* No FSMC memory controller */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ @@ -290,9 +290,9 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L433XX */ +#endif /* CONFIG_STM32_STM32L433XX */ -#if defined(CONFIG_STM32L4_STM32L412XX) || defined(CONFIG_STM32L4_STM32L422XX) +#if defined(CONFIG_STM32_STM32L412XX) || defined(CONFIG_STM32_STM32L422XX) # define STM32_NFSMC 0 /* No FSMC memory controller */ # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ @@ -320,7 +320,7 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 1 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L4_STM32L412XX || CONFIG_STM32L4_STM32L422XX */ +#endif /* CONFIG_STM32_STM32L412XX || CONFIG_STM32_STM32L422XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index 528204f8969..11c1a9a9d1f 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -69,13 +69,13 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include #else # error "Unsupported STM32 L4 chip" diff --git a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h index 2d6e4d570f2..e0d1c6bf7d1 100644 --- a/arch/arm/include/stm32l4/stm32l4x3xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x3xx_irq.h @@ -136,7 +136,7 @@ #define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */ #define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define STM32_IRQ_NEXTINTS 85 #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h index 7e937ff34c7..7b3eca2a848 100644 --- a/arch/arm/include/stm32l4/stm32l4x6xx_irq.h +++ b/arch/arm/include/stm32l4/stm32l4x6xx_irq.h @@ -148,9 +148,9 @@ #define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */ #define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32_STM32L476XX) || defined(CONFIG_STM32_STM32L486XX) # define STM32_IRQ_NEXTINTS 82 -#elif defined(CONFIG_STM32L4_STM32L496XX) +#elif defined(CONFIG_STM32_STM32L496XX) # define STM32_IRQ_NEXTINTS 91 #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/CMakeLists.txt b/arch/arm/src/stm32l4/CMakeLists.txt index 040c98142bc..f27e4933b24 100644 --- a/arch/arm/src/stm32l4/CMakeLists.txt +++ b/arch/arm/src/stm32l4/CMakeLists.txt @@ -58,11 +58,11 @@ else() list(APPEND SRCS stm32l4_tickless.c) endif() -if(CONFIG_STM32L4_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32L4_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32l4_freerun.c) endif() @@ -70,37 +70,37 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32l4_userspace.c stm32l4_mpuinit.c) endif() -if(CONFIG_STM32L4_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32l4_hsi48.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32l4_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32l4_dac.c) endif() -if(CONFIG_STM32L4_DFSDM) +if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32l4_dfsdm.c) endif() -if(CONFIG_STM32L4_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32l4_dma.c) endif() if(CONFIG_USBDEV) - if(CONFIG_STM32L4_USBFS) + if(CONFIG_STM32_USBFS) list(APPEND SRCS stm32l4_usbdev.c) endif() - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfsdev.c) endif() endif() if(CONFIG_USBHOST) - if(CONFIG_STM32L4_OTGFS) + if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32l4_otgfshost.c) endif() endif() @@ -124,11 +124,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32L4_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32l4_exti_pwr.c) endif() -if(CONFIG_STM32L4_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32l4_exti_alarm.c) endif() @@ -144,23 +144,23 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32l4_dumpgpio.c) endif() -if(CONFIG_STM32L4_COMP) +if(CONFIG_STM32_COMP) list(APPEND SRCS stm32l4_comp.c stm32l4_exti_comp.c) endif() -if(CONFIG_STM32L4_RNG) +if(CONFIG_STM32_RNG) list(APPEND SRCS stm32l4_rng.c) endif() -if(CONFIG_STM32L4_SAI) +if(CONFIG_STM32_SAI) list(APPEND SRCS stm32l4_sai.c) endif() -if(CONFIG_STM32L4_LPTIM) +if(CONFIG_STM32_LPTIM) list(APPEND SRCS stm32l4_lptim.c) endif() -if(CONFIG_STM32L4_PWM) +if(CONFIG_STM32_PWM) list(APPEND SRCS stm32l4_pwm.c) endif() @@ -172,27 +172,27 @@ if(CONFIG_SENSORS_QENCODER) list(APPEND SRCS stm32l4_qencoder.c) endif() -if(CONFIG_STM32L4_QSPI) +if(CONFIG_STM32_QSPI) list(APPEND SRCS stm32l4_qspi.c) endif() -if(CONFIG_STM32L4_CAN) +if(CONFIG_STM32_CAN) list(APPEND SRCS stm32l4_can.c) endif() -if(CONFIG_STM32L4_FIREWALL) +if(CONFIG_STM32_FIREWALL) list(APPEND SRCS stm32l4_firewall.c) endif() -if(CONFIG_STM32L4_IWDG) +if(CONFIG_STM32_IWDG) list(APPEND SRCS stm32l4_iwdg.c) endif() -if(CONFIG_STM32L4_SDMMC1) +if(CONFIG_STM32_SDMMC1) list(APPEND SRCS stm32l4_sdmmc.c) endif() -if(CONFIG_STM32L4_1WIREDRIVER) +if(CONFIG_STM32_1WIREDRIVER) list(APPEND SRCS stm32l4_1wire.c) endif() diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index b6d2bb1fb80..05f0c301135 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -7,6 +7,36 @@ if ARCH_CHIP_STM32L4 comment "STM32L4 Configuration Options" +config STM32_L4_PERIPHERALS + bool + default ARCH_CHIP_STM32L4 + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_RNG + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_SWPMI + select STM32_HAVE_FIREWALL + select STM32_HAVE_LPTIM_CHANNEL + select STM32_HAVE_TIM_ADC_CHANNEL + select STM32_HAVE_ADC_L4 + select STM32_HAVE_DAC_LL_OPS + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 L4 Chip Selection" default ARCH_CHIP_STM32L476RG @@ -14,544 +44,544 @@ choice config ARCH_CHIP_STM32L412KB bool "STM32L412KB" - select STM32L4_STM32L412XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L412XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 40 Kb SRAM config ARCH_CHIP_STM32L432KB bool "STM32L432KB" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L432KC bool "STM32L432KC" - select STM32L4_STM32L432XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L432XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CB bool "STM32L433CB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433CC bool "STM32L433CC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RB bool "STM32L433RB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_B select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433RC bool "STM32L433RC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L433VC bool "STM32L433VC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L433XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L442KC bool "STM32L442KC" - select STM32L4_STM32L442XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L442XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_K ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443CC bool "STM32L443CC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443RC bool "STM32L443RC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L443VC bool "STM32L443VC" - select STM32L4_STM32L443XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L443XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM config ARCH_CHIP_STM32L451CC bool "STM32L451CC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451CE bool "STM32L451CE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RC bool "STM32L451RC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451RE bool "STM32L451RE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VC bool "STM32L451VC" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L451VE bool "STM32L451VE" - select STM32L4_STM32L451XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L451XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CC bool "STM32L452CC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452CE bool "STM32L452CE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RC bool "STM32L452RC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452RE bool "STM32L452RE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VC bool "STM32L452VC" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_C + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_C select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L452VE bool "STM32L452VE" - select STM32L4_STM32L452XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L452XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462CE bool "STM32L462CE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_C ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462RE bool "STM32L462RE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L462VE bool "STM32L462VE" - select STM32L4_STM32L462XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L462XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, USB FS, AES, 512 Kb FLASH, 128+32 Kb SRAM config ARCH_CHIP_STM32L475RG bool "STM32L475RG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RE bool "STM32L475RE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475RC bool "STM32L475RC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP100 config ARCH_CHIP_STM32L475VG bool "STM32L475VG" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VE bool "STM32L475VE" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L475VC bool "STM32L475VC" - select STM32L4_STM32L475XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L475XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 256Kb FLASH, 96+32 Kb SRAM, LQFP64 config ARCH_CHIP_STM32L476JG bool "STM32L476JG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476JE bool "STM32L476JE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RG bool "STM32L476RG" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L476RE bool "STM32L476RE" - select STM32L4_STM32L476XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L476XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486RG bool "STM32L486RG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486JG bool "STM32L486JG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_J ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486VG bool "STM32L486VG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486QG bool "STM32L486QG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486ZG bool "STM32L486ZG" - select STM32L4_STM32L486XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L486XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L496RE bool "STM32L496RE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496RG bool "STM32L496RG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VE bool "STM32L496VE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496VG bool "STM32L496VG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZE bool "STM32L496ZE" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_E + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_E select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496ZG bool "STM32L496ZG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L496AG bool "STM32L496AG" - select STM32L4_STM32L496XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L496XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6RG bool "STM32L4A6RG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6VG bool "STM32L4A6VG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6QG bool "STM32L4A6QG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6ZG bool "STM32L4A6ZG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4A6AG bool "STM32L4A6AG" - select STM32L4_STM32L4A6XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4A6XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM config ARCH_CHIP_STM32L4R5VG bool "STM32L4R5VG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QG bool "STM32L4R5QG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZG bool "STM32L4R5ZG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AG bool "STM32L4R5AG" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5VI bool "STM32L4R5VI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5QI bool "STM32L4R5QI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Q ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5ZI bool "STM32L4R5ZI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R5AI bool "STM32L4R5AI" - select STM32L4_STM32L4R5XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R5XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VG bool "STM32L4R9VG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZG bool "STM32L4R9ZG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AG bool "STM32L4R9AG" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_G + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_G select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 1024Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9VI bool "STM32L4R9VI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_V ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9ZI bool "STM32L4R9ZI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_Z ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM config ARCH_CHIP_STM32L4R9AI bool "STM32L4R9AI" - select STM32L4_STM32L4R9XX - select STM32L4_FLASH_CONFIG_I + select STM32_STM32L4R9XX + select STM32_FLASH_CONFIG_I select STM32L4_IO_CONFIG_A ---help--- STM32 L4+ Cortex M4, 2048Kb FLASH, 640 Kb SRAM @@ -560,5924 +590,402 @@ endchoice # STM32 L4 Chip Selection # Chip product lines -config STM32L4_STM32L4X1 +config STM32_STM32L4X1 # STM32L4x1 Access Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). # # Note: This is _not_ for STM32L471xx (documented in RM0392). bool default n - select STM32L4_STM32L4X3 + select STM32_STM32L4X3 -config STM32L4_STM32L4X2 +config STM32_STM32L4X2 # STM32L4x2 USB Device Lines # # Avoid using this config as it is basically same subfamily - # as STM32L4_STM32L4X3 (documented in RM0394). + # as STM32_STM32L4X3 (documented in RM0394). bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_USBFS + select STM32_STM32L4X3 + select STM32_HAVE_USBFS -config STM32L4_STM32L4X3 +config STM32_STM32L4X3 # STM32L4 devices documented in RM0394, regardless of what ST's # marketing calls them. bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 if !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2) - select STM32L4_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 if !(STM32_STM32L432XX || STM32_STM32L442XX) + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_LCD if !(STM32_STM32L4X1 || STM32_STM32L4X2) + select STM32_HAVE_HSI48 -config STM32L4_STM32L4X5 +config STM32_STM32L4X5 # STM32L4 USB OTG Lines (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_QSPI + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_DFSDM1 + select STM32_HAVE_QSPI -config STM32L4_STM32L4X6 +config STM32_STM32L4X6 # STM32L4x6 (documented in RM0351) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_ADC3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_LCD - select STM32L4_HAVE_QSPI + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_LCD + select STM32_HAVE_QSPI -config STM32L4_STM32L4XR +config STM32_STM32L4XR # STM32L4+ (documented in RM0432) bool default n select ARCH_HAVE_FPU - select STM32L4_HAVE_LPUART1 - select STM32L4_HAVE_USART1 - select STM32L4_HAVE_USART2 - select STM32L4_HAVE_USART3 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_UART5 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_FSMC - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_TIM4 - select STM32L4_HAVE_TIM5 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_TIM8 - select STM32L4_HAVE_TIM17 - select STM32L4_HAVE_LPTIM1 - select STM32L4_HAVE_LPTIM2 - select STM32L4_HAVE_COMP - select STM32L4_HAVE_SAI1 - select STM32L4_HAVE_SAI2 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_OTGFS - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 - select STM32L4_HAVE_DMAMUX + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_DAC2 + select STM32_HAVE_FSMC + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM17 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM2 + select STM32_HAVE_COMP + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2C4 + select STM32_HAVE_DCMI + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMAMUX # Chip subfamilies: -config STM32L4_STM32L412XX +config STM32_STM32L412XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 -config STM32L4_STM32L422XX +config STM32_STM32L422XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_ADC2 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_ADC2 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L431XX +config STM32_STM32L431XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) + select STM32_STM32L4X1 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 if (STM32L4_IO_CONFIG_V || STM32L4_IO_CONFIG_R) -config STM32L4_STM32L432XX +config STM32_STM32L432XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L433XX +config STM32_STM32L433XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 -config STM32L4_STM32L442XX +config STM32_STM32L442XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L443XX +config STM32_STM32L443XX bool default n - select STM32L4_STM32L4X3 - select STM32L4_HAVE_DAC2 - select STM32L4_HAVE_TIM7 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_AES + select STM32_STM32L4X3 + select STM32_HAVE_DAC2 + select STM32_HAVE_TIM7 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L451XX +config STM32_STM32L451XX bool default n - select STM32L4_STM32L4X1 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X1 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 if !STM32L4_IO_CONFIG_C + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L452XX +config STM32_STM32L452XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 -config STM32L4_STM32L462XX +config STM32_STM32L462XX bool default n - select STM32L4_STM32L4X2 - select STM32L4_HAVE_UART4 - select STM32L4_HAVE_TIM3 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_SDMMC1 - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_AES + select STM32_STM32L4X2 + select STM32_HAVE_UART4 + select STM32_HAVE_TIM3 + select STM32_HAVE_I2C4 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L471XX +config STM32_STM32L471XX bool default n + select STM32_HAVE_CAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 # TODO -config STM32L4_STM32L475XX +config STM32_STM32L475XX bool default n - select STM32L4_STM32L4X5 + select STM32_STM32L4X5 -config STM32L4_STM32L476XX +config STM32_STM32L476XX bool default n - select STM32L4_STM32L4X6 + select STM32_STM32L4X6 -config STM32L4_STM32L486XX +config STM32_STM32L486XX bool default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_AES + select STM32_STM32L4X6 + select STM32_HAVE_AES + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L496XX +config STM32_STM32L496XX bool default n - select STM32L4_STM32L4X6 - select STM32L4_HAVE_I2C4 - select STM32L4_HAVE_CAN2 - select STM32L4_HAVE_DCMI - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_DFSDM1 - select STM32L4_HAVE_HSI48 + select STM32_STM32L4X6 + select STM32_ADC2_HAVE_OUTPUT_DFSDM + select STM32_ADC3_HAVE_OUTPUT_DFSDM + select STM32_HAVE_I2C4 + select STM32_HAVE_CAN2 + select STM32_HAVE_DCMI + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_DFSDM1 + select STM32_HAVE_HSI48 -config STM32L4_STM32L4A6XX +config STM32_STM32L4A6XX bool default n - select STM32L4_STM32L496XX - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L496XX + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R5XX +config STM32_STM32L4R5XX bool default n - select STM32L4_STM32L4XR + select STM32_STM32L4XR -config STM32L4_STM32L4S5XX +config STM32_STM32L4S5XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4XR + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R7XX +config STM32_STM32L4R7XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 -config STM32L4_STM32L4S7XX +config STM32_STM32L4S7XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 -config STM32L4_STM32L4R9XX +config STM32_STM32L4R9XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC -config STM32L4_STM32L4S9XX +config STM32_STM32L4S9XX bool default n - select STM32L4_STM32L4XR - select STM32L4_HAVE_DMA2D - select STM32L4_HAVE_LTDC - select STM32L4_HAVE_AES - select STM32L4_HAVE_HASH - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L4 - default STM32L4_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L4 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L476VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L4xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L4_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L4_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L4_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L4_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L4_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32L4_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L4_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L4_FLASH_CONFIG_8 - bool - default n - depends on STM32L4_STM32L412XX - -config STM32L4_FLASH_CONFIG_B - bool - default n - depends on STM32L4_STM32L4X1 || STM32L4_STM32L4X3 - -config STM32L4_FLASH_CONFIG_C - bool - default n - depends on !STM32L4_STM32L496XX - -config STM32L4_FLASH_CONFIG_E - bool - default n - -config STM32L4_FLASH_CONFIG_G - bool - default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 - -config STM32L4_FLASH_CONFIG_I - bool - default n - depends on STM32L4_STM32L4XR + select STM32_STM32L4XR + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_LTDC + select STM32_HAVE_AES + select STM32_HAVE_HASH + select STM32_HAVE_IP_AES_M3M4_V1 # Pin/package configurations config STM32L4_IO_CONFIG_K + # Package designator K bool default n config STM32L4_IO_CONFIG_T + # Package designator T bool default n config STM32L4_IO_CONFIG_C + # Package designator C bool default n config STM32L4_IO_CONFIG_R + # Package designator R bool default n config STM32L4_IO_CONFIG_J + # Package designator J bool default n config STM32L4_IO_CONFIG_M + # Package designator M bool default n config STM32L4_IO_CONFIG_V + # Package designator V bool default n config STM32L4_IO_CONFIG_Q + # Package designator Q bool default n config STM32L4_IO_CONFIG_Z + # Package designator Z bool default n config STM32L4_IO_CONFIG_A + # Package designator A bool default n comment "STM32L4 SRAM2 and SRAM3 Options" -config STM32L4_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L4_SRAM2_INIT - ---help--- - The STM32L4 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L4_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L4 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32L4_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32L4_STM32L4XR - default y - ---help--- - Add the STM32L4 SRAM3 to the heap for use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -comment "STM32L4 Peripherals" - -menu "STM32L4 Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32L4_HAVE_ADC2 - bool - default n - -config STM32L4_HAVE_ADC3 - bool - default n - -config STM32L4_HAVE_AES - bool - default n - -config STM32L4_HAVE_CAN2 - bool - default n - -config STM32L4_HAVE_COMP - bool - default n - -config STM32L4_HAVE_DAC2 - bool - default n - -config STM32L4_HAVE_DCMI - bool - default n - -config STM32L4_HAVE_DFSDM1 - bool - default n - -config STM32L4_HAVE_DMA2D - bool - default n - -config STM32L4_HAVE_DMAMUX - bool - default n - -config STM32L4_HAVE_FSMC - bool - default n - -config STM32L4_HAVE_HASH - bool - default n - -config STM32L4_HAVE_HSI48 - bool - default n - -config STM32L4_HAVE_I2C4 - bool - default n - -config STM32L4_HAVE_LCD - bool - default n - -config STM32L4_HAVE_LTDC - bool - default n - -config STM32L4_HAVE_LPTIM1 - bool - default n - -config STM32L4_HAVE_LPTIM2 - bool - default n - -config STM32L4_HAVE_OTGFS - bool - default n - -config STM32L4_HAVE_USBFS - bool - default n - -config STM32L4_HAVE_SAI1 - bool - default n - -config STM32L4_HAVE_SAI2 - bool - default n - -config STM32L4_RTC - bool "RTC" - default n - select RTC - -config STM32L4_HAVE_SDMMC1 - bool - default n - -config STM32L4_HAVE_TIM3 - bool - default n - -config STM32L4_HAVE_TIM4 - bool - default n - -config STM32L4_HAVE_TIM5 - bool - default n - -config STM32L4_HAVE_TIM7 - bool - default n - -config STM32L4_HAVE_TIM8 - bool - default n - -config STM32L4_HAVE_TIM17 - bool - default n - -config STM32L4_HAVE_LPUART1 - bool - default n - -config STM32L4_HAVE_USART1 - bool - default n - -config STM32L4_HAVE_USART2 - bool - default n - -config STM32L4_HAVE_USART3 - bool - default n - -config STM32L4_HAVE_UART4 - bool - default n - -config STM32L4_HAVE_UART5 - bool - default n - -config STM32L4_HAVE_QSPI - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L4_ADC - bool - default n - -config STM32L4_CAN - bool - default n - -config STM32L4_DAC - bool - default n - -config STM32L4_DFSDM - bool - default n - -config STM32L4_DMAMUX - bool - default n - depends on STM32L4_HAVE_DMAMUX - -config STM32L4_DMA - bool - default n - select STM32L4_DMAMUX if STM32L4_HAVE_DMAMUX - -config STM32L4_I2C - bool - default n - -config STM32L4_SAI - bool - default n - -config STM32L4_SPI - bool - default n - -config STM32L4_PWM - bool - default n - -config STM32L4_USART - bool - default n - -config STM32L4_LPTIM - bool - default n - -config STM32L4_SDMMC - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32L4_DMAMUX1 - bool "DMAMUX1" - default n - depends on STM32L4_HAVE_DMAMUX - select STM32L4_DMAMUX - -config STM32L4_DMA1 - bool "DMA1" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_DMA2 - bool "DMA2" - default n - select STM32L4_DMA - select ARCH_DMA - select STM32L4_DMAMUX1 if STM32L4_HAVE_DMAMUX - -config STM32L4_CRC - bool "CRC" - default n - -config STM32L4_TSC - bool "TSC" - default n - -comment "AHB2 Peripherals" - -config STM32L4_OTGFS - bool "OTG FS" - default n - select USBHOST_HAVE_ASYNCH if USBHOST - depends on STM32L4_HAVE_OTGFS - -config STM32L4_ADC1 - bool "ADC1" - default n - select STM32L4_ADC - -config STM32L4_ADC2 - bool "ADC2" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC2 - -config STM32L4_ADC3 - bool "ADC3" - default n - select STM32L4_ADC - depends on STM32L4_HAVE_ADC3 - -config STM32L4_AES - bool "AES" - default n - depends on STM32L4_HAVE_AES - -config STM32L4_DCMI - bool "DCMI" - default n - depends on STM32L4_HAVE_DCMI - -config STM32L4_DMA2D - bool "DMA2D" - default n - depends on STM32L4_HAVE_DMA2D - -config STM32L4_HASH - bool "HASH" - default n - depends on STM32L4_HAVE_HASH - -config STM32L4_RNG - bool "RNG" - default n - select ARCH_HAVE_RNG - -comment "AHB3 Peripherals" - -config STM32L4_FSMC - bool "FSMC" - default n - depends on STM32L4_HAVE_FSMC - -config STM32L4_QSPI - bool "QuadSPI" - default n - depends on STM32L4_HAVE_QSPI - ---help--- - The STM32L4 QSPI block is intended to support one serial NOR flash device - -if STM32L4_QSPI - -config STM32L4_QSPI_FLASH_SIZE - int "Size of attached serial flash, bytes" - default 16777216 - range 1 2147483647 - ---help--- - The STM32L4 QSPI peripheral requires the size of the Flash be specified - -config STM32L4_QSPI_FIFO_THESHOLD - int "Number of bytes before asserting FIFO threshold flag" - default 4 - range 1 16 - ---help--- - The STM32L4 QSPI peripheral requires that the FIFO threshold be specified - I would leave it at the default value of 4 unless you know what you are doing. - -config STM32L4_QSPI_CSHT - int "Number of cycles Chip Select must be inactive between transactions" - default 1 - range 1 8 - ---help--- - The STM32L4 QSPI peripheral requires that it be specified the minimum number - of AHB cycles that Chip Select be held inactive between transactions. - -choice - prompt "Transfer technique" - default STM32L4_QSPI_DMA - ---help--- - You can choose between using polling, interrupts, or DMA to transfer data - over the QSPI interface. - -config STM32L4_QSPI_POLLING - bool "Polling" - ---help--- - Use conventional register I/O with status polling to transfer data. - -config STM32L4_QSPI_INTERRUPTS - bool "Interrupts" - ---help--- - User interrupt driven I/O transfers. - -config STM32L4_QSPI_DMA - bool "DMA" - depends on STM32L4_DMA - ---help--- - Use DMA to improve QSPI transfer performance. - -endchoice - -choice - prompt "DMA Channel" - default STM32L4_QSPI_DMA_CHAN_1_5 - depends on STM32L4_DMA - ---help--- - You can choose between two DMA channels for use with QSPI: - either DMA1 channel 5, or DMA2 channel 7. - If you only see one choice here, it is probably because - you have not also enabled the associated DMA controller. - -config STM32L4_QSPI_DMA_CHAN_1_5 - bool "DMA1 Channel 5" - depends on STM32L4_DMA1 && !STM32L4_DMAMUX - ---help--- - Use DMA1 channel 5 for QSPI. - -config STM32L4_QSPI_DMA_CHAN_2_7 - bool "DMA2 Channel 7" - depends on STM32L4_DMA2 && !STM32L4_DMAMUX - ---help--- - Use DMA2 channel 7 for QSPI. - -endchoice - -choice - prompt "DMA Priority" - default STM32L4_QSPI_DMAPRIORITY_MEDIUM - depends on STM32L4_DMA - ---help--- - The DMA controller supports priority levels. You are probably fine - with the default of 'medium' except for special cases. In the event - of contention between to channels at the same priority, the lower - numbered channel has hardware priority over the higher numbered one. - -config STM32L4_QSPI_DMAPRIORITY_VERYHIGH - bool "Very High priority" - depends on STM32L4_DMA - ---help--- - 'Highest' priority. - -config STM32L4_QSPI_DMAPRIORITY_HIGH - bool "High priority" - depends on STM32L4_DMA - ---help--- - 'High' priority. - -config STM32L4_QSPI_DMAPRIORITY_MEDIUM - bool "Medium priority" - depends on STM32L4_DMA - ---help--- - 'Medium' priority. - -config STM32L4_QSPI_DMAPRIORITY_LOW - bool "Low priority" - depends on STM32L4_DMA - ---help--- - 'Low' priority. - -endchoice - -config STM32L4_QSPI_DMATHRESHOLD - int "QSPI DMA threshold" - default 4 - depends on STM32L4_QSPI_DMA - ---help--- - When QSPI DMA is enabled, small DMA transfers will still be performed - by polling logic. This value is the threshold below which transfers - will still be performed by conventional register status polling. - -config STM32L4_QSPI_DMADEBUG - bool "QSPI DMA transfer debug" - depends on STM32L4_QSPI_DMA && DEBUG_SPI && DEBUG_DMA - default n - ---help--- - Enable special debug instrumentation to analyze QSPI DMA data transfers. - This logic is as non-invasive as possible: It samples DMA - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. - -config STM32L4_QSPI_REGDEBUG - bool "QSPI Register level debug" - depends on DEBUG_SPI_INFO - default n - ---help--- - Output detailed register-level QSPI device debug information. - Requires also CONFIG_DEBUG_SPI_INFO. - -endif - -comment "APB1 Peripherals" - -config STM32L4_PWR - bool "PWR" - default n - -config STM32L4_TIM2 - bool "TIM2" - default n - -config STM32L4_TIM3 - bool "TIM3" - default n - depends on STM32L4_HAVE_TIM3 - -config STM32L4_TIM4 - bool "TIM4" - default n - depends on STM32L4_HAVE_TIM4 - -config STM32L4_TIM5 - bool "TIM5" - default n - depends on STM32L4_HAVE_TIM5 - -config STM32L4_TIM6 - bool "TIM6" - default n - -config STM32L4_TIM7 - bool "TIM7" - default n - depends on STM32L4_HAVE_TIM7 - -config STM32L4_LCD - bool "LCD" - default n - depends on STM32L4_HAVE_LCD - -config STM32L4_SPI2 - bool "SPI2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select SPI - select STM32L4_SPI - -config STM32L4_SPI3 - bool "SPI3" - default n - select SPI - select STM32L4_SPI - -config STM32L4_LPUART1 - bool "LPUART1" - default n - depends on STM32L4_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART2 - bool "USART2" - default n - depends on STM32L4_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_USART3 - bool "USART3" - default n - depends on STM32L4_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART4 - bool "UART4" - default n - depends on STM32L4_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_UART5 - bool "UART5" - default n - depends on STM32L4_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_I2C1 - bool "I2C1" - default n - select STM32L4_I2C - -config STM32L4_I2C2 - bool "I2C2" - default n - depends on !(STM32L4_STM32L432XX || STM32L4_STM32L442XX) - select STM32L4_I2C - -config STM32L4_I2C3 - bool "I2C3" - default n - select STM32L4_I2C - -config STM32L4_I2C4 - bool "I2C4" - default n - select STM32L4_I2C - depends on STM32L4_HAVE_I2C4 - -config STM32L4_CAN1 - bool "CAN1" - default n - select CAN - select STM32L4_CAN - -config STM32L4_CAN2 - bool "CAN2" - default n - select CAN - select STM32L4_CAN - depends on STM32L4_HAVE_CAN2 - -config STM32L4_DAC1 - bool "DAC1" - default n - select STM32L4_DAC - -config STM32L4_DAC2 - bool "DAC2" - default n - select STM32L4_DAC - depends on STM32L4_HAVE_DAC2 - -config STM32L4_OPAMP - bool "OPAMP" - default n - -config STM32L4_LPTIM1 - bool "LPTIM1" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM1 - -config STM32L4_LPUART1 - bool "LPUART1" - default n - select LPUART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - -config STM32L4_SWPMI - bool "SWPMI" - default n - -config STM32L4_LPTIM2 - bool "LPTIM2" - default n - select STM32L4_LPTIM - depends on STM32L4_HAVE_LPTIM2 - -config STM32L4_USBFS - bool "USB FS" - default n - depends on STM32L4_HAVE_USBFS - select USBDEV - -comment "APB2 Peripherals" - -config STM32L4_SYSCFG - bool "SYSCFG" - default y - -config STM32L4_FIREWALL - bool "FIREWALL" - default y - depends on STM32L4_SYSCFG - -config STM32L4_SDMMC1 - bool "SDMMC1" - default n - select ARCH_HAVE_SDIO - select SCHED_HPWORK - select STM32L4_SAI1PLL - select STM32L4_SDMMC - select ARCH_HAVE_SDIOWAIT_WRCOMPLETE - select ARCH_HAVE_SDIO_PREFLIGHT - depends on STM32L4_HAVE_SDMMC1 - -config STM32L4_TIM1 - bool "TIM1" - default n - -config STM32L4_SPI1 - bool "SPI1" - default n - select SPI - select STM32L4_SPI - -config STM32L4_TIM8 - bool "TIM8" - default n - depends on STM32L4_HAVE_TIM8 - -config STM32L4_USART1 - bool "USART1" - default n - depends on STM32L4_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L4_USART - -config STM32L4_TIM15 - bool "TIM15" - default n - -config STM32L4_TIM16 - bool "TIM16" - default n - -config STM32L4_TIM17 - bool "TIM17" - default n - depends on STM32L4_HAVE_TIM17 - -config STM32L4_COMP - bool "COMP" - default n - select COMP - depends on STM32L4_HAVE_COMP - -config STM32L4_SAI1 - bool "SAI1" - default n - depends on STM32L4_HAVE_SAI1 - -config STM32L4_SAI1_A - bool "SAI1 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI1_B - bool "SAI1 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI1 - -config STM32L4_SAI2 - bool "SAI2" - default n - depends on STM32L4_HAVE_SAI2 - -config STM32L4_SAI2_A - bool "SAI2 Block A" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_SAI2_B - bool "SAI2 Block B" - default n - select AUDIO - select I2S - select SCHED_HPWORK - select STM32L4_SAI - depends on STM32L4_SAI2 - -config STM32L4_DFSDM1 - bool "DFSDM1" - default n - depends on STM32L4_HAVE_DFSDM1 - -comment "Other Peripherals" - -config STM32L4_BKPSRAM - bool "Enable BKP RAM Domain" - default n - -config STM32L4_IWDG - bool "IWDG" - default n - select WATCHDOG - -config STM32L4_WWDG - bool "WWDG" - default n - select WATCHDOG - -endmenu - -config STM32L4_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L4 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L4_HAVE_SAI2 - ---help--- - The STM32L4 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L4_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW - bool "Workaround for FLASH data cache corruption" - default n - depends on STM32L4_STM32L4X5 || STM32L4_STM32L4X6 || STM32L4_STM32L4XR - ---help--- - Enable the workaround to fix flash data cache corruption when reading - from one flash bank while writing on other flash bank. See your STM32 - errata to check if your STM32 is affected by this problem. - -choice - prompt "JTAG Configuration" - default STM32L4_JTAG_DISABLE - ---help--- - JTAG Enable settings (by default JTAG-DP and SW-DP are disabled) - -config STM32L4_JTAG_DISABLE - bool "Disable all JTAG clocking" - -config STM32L4_JTAG_FULL_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP)" - -config STM32L4_JTAG_NOJNTRST_ENABLE - bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST" - -config STM32L4_JTAG_SW_ENABLE - bool "Set JTAG-DP disabled and SW-DP enabled" - -endchoice - -config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L4_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L4_RTC - -config STM32L4_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L4_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L4_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L4_RTC_LSECLOCK - depends on STM32L4_RTC - -config STM32L4_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L4_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L4_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L4_RTC_LSECLOCK - -config STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32L4_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L4_ONESHOT - bool - default y - -config STM32L4_FREERUN - bool - default y - -config STM32L4_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L4_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L4_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L4_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L4_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L4_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L4_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L4_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L4_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L4_LPTIM1_CLK_APB1 - -config STM32L4_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L4_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L4_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L4_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L4_LPTIM1_PWM - -config STM32L4_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L4_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L4_LPTIM2_CLK_APB1 - -config STM32L4_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L4_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L4_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L4_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_LL_OPS - bool "PWM low-level operations" - default n - ---help--- - Enable low-level PWM ops. - -config STM32L4_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L4_TIM1 - select STM32L4_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM1_PWM - -config STM32L4_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM1_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 1 lock level configuration - -config STM32L4_TIM1_TDTS - int "TIM1 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 1 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM1_DEADTIME - int "TIM1 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 1 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM1_CHANNEL1 - -config STM32L4_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L4_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM1_CHANNEL2 - -config STM32L4_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM1_CHANNEL3 - -config STM32L4_TIM1_CHANNEL4 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM1_CHANNEL4 - -config STM32L4_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM1_CHANNEL = 1 - -config STM32L4_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 1 - -if STM32L4_TIM1_CHANNEL = 2 - -config STM32L4_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 2 - -if STM32L4_TIM1_CHANNEL = 3 - -config STM32L4_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM1_CHANNEL = 3 - -if STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM1_CHANNEL = 4 - -config STM32L4_TIM1_CHMODE - int "TIM1 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM1_PWM - -config STM32L4_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L4_TIM2 - select STM32L4_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM2_PWM - -config STM32L4_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL1 - -config STM32L4_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL2 - -config STM32L4_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL3 - -config STM32L4_TIM2_CHANNEL4 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM2_CHANNEL4 - -config STM32L4_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM2_CHANNEL = 1 - -config STM32L4_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM2_CHANNEL = 1 - -if STM32L4_TIM2_CHANNEL = 2 - -config STM32L4_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM2_CHANNEL = 2 - -if STM32L4_TIM2_CHANNEL = 3 - -config STM32L4_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM2_CHANNEL = 3 - -if STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM2_CHANNEL = 4 - -config STM32L4_TIM2_CHMODE - int "TIM2 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM2_PWM - -config STM32L4_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L4_TIM3 - select STM32L4_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM3_PWM - -config STM32L4_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL1 - -config STM32L4_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL2 - -config STM32L4_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL3 - -config STM32L4_TIM3_CHANNEL4 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM3_CHANNEL4 - -config STM32L4_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM3_CHANNEL = 1 - -config STM32L4_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM3_CHANNEL = 1 - -if STM32L4_TIM3_CHANNEL = 2 - -config STM32L4_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM3_CHANNEL = 2 - -if STM32L4_TIM3_CHANNEL = 3 - -config STM32L4_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM3_CHANNEL = 3 - -if STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM3_CHANNEL = 4 - -config STM32L4_TIM3_CHMODE - int "TIM3 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM3_PWM - -config STM32L4_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L4_TIM4 - select STM32L4_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM4_PWM - -config STM32L4_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL1 - -config STM32L4_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL2 - -config STM32L4_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL3 - -config STM32L4_TIM4_CHANNEL4 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM4_CHANNEL4 - -config STM32L4_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM4_CHANNEL = 1 - -config STM32L4_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM4_CHANNEL = 1 - -if STM32L4_TIM4_CHANNEL = 2 - -config STM32L4_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM4_CHANNEL = 2 - -if STM32L4_TIM4_CHANNEL = 3 - -config STM32L4_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM4_CHANNEL = 3 - -if STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM4_CHANNEL = 4 - -config STM32L4_TIM4_CHMODE - int "TIM4 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM4_PWM - -config STM32L4_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L4_TIM5 - select STM32L4_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM5_PWM - -config STM32L4_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL1 - -config STM32L4_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL2 - -config STM32L4_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL3 - -config STM32L4_TIM5_CHANNEL4 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM5_CHANNEL4 - -config STM32L4_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM5_CHANNEL = 1 - -config STM32L4_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM5_CHANNEL = 1 - -if STM32L4_TIM5_CHANNEL = 2 - -config STM32L4_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM5_CHANNEL = 2 - -if STM32L4_TIM5_CHANNEL = 3 - -config STM32L4_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L4_TIM5_CHANNEL = 3 - -if STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM5_CHANNEL = 4 - -config STM32L4_TIM5_CHMODE - int "TIM5 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM5_PWM - -config STM32L4_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L4_TIM8 - select STM32L4_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM8_PWM - -config STM32L4_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -config STM32L4_TIM8_LOCK - int "TIM1 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 8 lock level configuration - -config STM32L4_TIM8_TDTS - int "TIM8 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 8 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM8_DEADTIME - int "TIM8 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 8 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM8_CHANNEL1 - -config STM32L4_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L4_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L4_TIM8_CHANNEL2 - -config STM32L4_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L4_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L4_TIM8_CHANNEL3 - -config STM32L4_TIM8_CHANNEL4 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L4_TIM8_CHANNEL4 - -config STM32L4_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL4 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -if STM32L4_TIM8_CHANNEL = 1 - -config STM32L4_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 1 - -if STM32L4_TIM8_CHANNEL = 2 - -config STM32L4_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 2 - -if STM32L4_TIM8_CHANNEL = 3 - -config STM32L4_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L4_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - ---help--- - Enables channel 3 Complementary Output. - -endif # STM32L4_TIM8_CHANNEL = 3 - -if STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L4_TIM8_CHANNEL = 4 - -config STM32L4_TIM8_CHMODE - int "TIM8 Channel Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM8_PWM - -config STM32L4_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L4_TIM15 - select STM32L4_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM15_PWM - -config STM32L4_TIM15_LOCK - int "TIM15 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 15 lock level configuration - -config STM32L4_TIM15_TDTS - int "TIM15 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 15 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM15_DEADTIME - int "TIM15 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 15 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM15_CHANNEL1 - -config STM32L4_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L4_TIM15_CHANNEL2 - -config STM32L4_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 6 - range 0 11 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L4_TIM15_CHANNEL2 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -if STM32L4_TIM15_CHANNEL = 1 - -config STM32L4_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 1 - -if STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L4_TIM15_CH2NOUT - bool "TIM15 Channel 2 Complementary Output" - default n - ---help--- - Enables channel 2 Complementary Output. - -endif # STM32L4_TIM15_CHANNEL = 2 - -config STM32L4_TIM15_CHMODE - int "TIM15 Channel Mode" - default 6 - range 0 9 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM15_PWM - -config STM32L4_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L4_TIM16 - select STM32L4_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM16_PWM - -config STM32L4_TIM16_LOCK - int "TIM16 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 16 lock level configuration - -config STM32L4_TIM16_TDTS - int "TIM16 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 16 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM16_DEADTIME - int "TIM16 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 16 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM16_CHANNEL1 - -config STM32L4_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM16_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM16_CHANNEL = 1 - -config STM32L4_TIM16_CHMODE - int "TIM16 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM16_PWM - -config STM32L4_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L4_TIM17 - select STM32L4_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L4_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L4_TIM17_PWM - -config STM32L4_TIM17_LOCK - int "TIM17 Lock Level Configuration" - default 0 - range 0 3 - ---help--- - Timer 17 lock level configuration - -config STM32L4_TIM17_TDTS - int "TIM17 t_DTS Division" - default 0 - range 0 2 - ---help--- - Timer 17 dead-time and sampling clock (t_DTS) division - -config STM32L4_TIM17_DEADTIME - int "TIM17 Initial Dead-time" - default 0 - range 0 255 - ---help--- - Timer 17 initial dead-time - -if STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_TIM17_CHANNEL1 - -config STM32L4_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L4_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_TIM17_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L4_TIM17_CHANNEL = 1 - -config STM32L4_TIM17_CHMODE - int "TIM17 Channel Mode" - default 6 - range 0 7 - ---help--- - Specifies the channel mode. See enum stm32l4_pwm_chanmode_e in stm32l4_pwm.h. - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_TIM17_PWM - -if STM32L4_LPTIM1_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL1 - bool "LPTIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM1_CHANNEL1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM1_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM1_CHANNEL - int "LPTIM1 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM1_CHANNEL = 1 - -config STM32L4_LPTIM1_CH1OUT - bool "LPTIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM1_CH1NOUT - bool "LPTIM1 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM1_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM1_PWM - -if STM32L4_LPTIM2_PWM - -if STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL1 - bool "LPTIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L4_LPTIM2_CHANNEL1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - depends on STM32L4_LPTIM2_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L4_LPTIM2_CHANNEL1 - -endif # STM32L4_PWM_MULTICHAN - -if !STM32L4_PWM_MULTICHAN - -config STM32L4_LPTIM2_CHANNEL - int "LPTIM2 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If LPTIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -if STM32L4_LPTIM2_CHANNEL = 1 - -config STM32L4_LPTIM2_CH1OUT - bool "LPTIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L4_LPTIM2_CH1NOUT - bool "LPTIM2 Channel 1 Complementary Output" - default n - ---help--- - Enables channel 1 Complementary Output. - -endif # STM32L4_LPTIM2_CHANNEL = 1 - -endif # !STM32L4_PWM_MULTICHAN - -endif # STM32L4_LPTIM2_PWM - -config STM32L4_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L4_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L4_PULSECOUNT - bool - default n - select ARCH_HAVE_PULSECOUNT - select PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT - bool "TIM1 pulse count" - default n - depends on STM32L4_TIM1 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 1 for pulse count output. - -if STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM1_PULSECOUNT_TDTS - int "TIM1 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM1_PULSECOUNT_CHANNEL - int "TIM1 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM1_PULSECOUNT_POL - int "TIM1 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM1_PULSECOUNT_IDLE - int "TIM1 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM1_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT - bool "TIM8 pulse count" - default n - depends on STM32L4_TIM8 - select STM32L4_PULSECOUNT - ---help--- - Reserve timer 8 for pulse count output. - -if STM32L4_TIM8_PULSECOUNT - -config STM32L4_TIM8_PULSECOUNT_TDTS - int "TIM8 pulse count clock division" - default 0 - range 0 2 - -config STM32L4_TIM8_PULSECOUNT_CHANNEL - int "TIM8 pulse count channel" - default 1 - range 1 4 - ---help--- - Specifies the timer channel {1,..,4}. - -config STM32L4_TIM8_PULSECOUNT_POL - int "TIM8 pulse count output polarity" - default 0 - range 0 1 - -config STM32L4_TIM8_PULSECOUNT_IDLE - int "TIM8 pulse count idle state" - default 0 - range 0 1 - -endif # STM32L4_TIM8_PULSECOUNT -config STM32L4_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L4_TIM1 && STM32L4_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM1_ADC1 - depends on STM32L4_TIM1_ADC - -config STM32L4_TIM1_ADC1 - bool "TIM1 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L4_TIM1_ADC2 - bool "TIM1 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L4_TIM1_ADC3 - bool "TIM1 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L4_TIM1_ADC_CHAN - int "TIM1 channel" - default 1 - range 1 4 - depends on STM32L4_TIM1_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L4_TIM2 && STM32L4_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM2_ADC1 - depends on STM32L4_TIM2_ADC - -config STM32L4_TIM2_ADC1 - bool "TIM2 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L4_TIM2_ADC2 - bool "TIM2 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L4_TIM2_ADC3 - bool "TIM2 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L4_TIM2_ADC_CHAN - int "TIM2 channel" - default 1 - range 1 4 - depends on STM32L4_TIM2_ADC - ---help--- - Values 1:CC1 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L4_TIM3 && STM32L4_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM3_ADC1 - depends on STM32L4_TIM3_ADC - -config STM32L4_TIM3_ADC1 - bool "TIM3 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L4_TIM3_ADC2 - bool "TIM3 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L4_TIM3_ADC3 - bool "TIM3 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L4_TIM3_ADC_CHAN - int "TIM3 channel" - default 1 - range 1 4 - depends on STM32L4_TIM3_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L4_TIM4 && STM32L4_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM4_ADC1 - depends on STM32L4_TIM4_ADC - -config STM32L4_TIM4_ADC1 - bool "TIM4 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L4_TIM4_ADC2 - bool "TIM4 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L4_TIM4_ADC3 - bool "TIM4 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L4_TIM4_ADC_CHAN - int "TIM4 channel" - default 1 - range 1 4 - depends on STM32L4_TIM4_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L4_TIM6 && STM32L4_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM6_ADC1 - depends on STM32L4_TIM6_ADC - -config STM32L4_TIM6_ADC1 - bool "TIM6 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L4_TIM6_ADC2 - bool "TIM6 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L4_TIM6_ADC3 - bool "TIM6 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L4_TIM6_ADC_CHAN - int "TIM6 channel" - default 1 - range 1 4 - depends on STM32L4_TIM6_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L4_TIM8 && STM32L4_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM8_ADC1 - depends on STM32L4_TIM8_ADC - -config STM32L4_TIM8_ADC1 - bool "TIM8 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L4_TIM8_ADC2 - bool "TIM8 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L4_TIM8_ADC3 - bool "TIM8 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L4_TIM8_ADC_CHAN - int "TIM8 channel" - default 1 - range 1 4 - depends on STM32L4_TIM8_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L4_TIM15 && STM32L4_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L4_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select ADC to trigger" - default STM32L4_TIM15_ADC1 - depends on STM32L4_TIM15_ADC - -config STM32L4_TIM15_ADC1 - bool "TIM15 trigger ADC1" - depends on STM32L4_ADC1 - select STM32L4_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L4_TIM15_ADC2 - bool "TIM15 trigger ADC2" - depends on STM32L4_ADC2 - select STM32L4_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L4_TIM15_ADC3 - bool "TIM15 trigger ADC3" - depends on STM32L4_ADC3 - select STM32L4_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L4_TIM15_ADC_CHAN - int "TIM15 channel" - default 1 - range 1 4 - depends on STM32L4_TIM15_ADC - ---help--- - Values 1:CC2 2:CC2 3:CC3 4:CC4 - -config STM32L4_HAVE_ADC1_TIMER - bool - -config STM32L4_HAVE_ADC2_TIMER - bool - -config STM32L4_HAVE_ADC3_TIMER - bool - -config STM32L4_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L4_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L4_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L4_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L4_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L4_TIM1 && STM32L4_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L4_TIM1_DAC1 - depends on STM32L4_TIM1_DAC - -config STM32L4_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L4_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L4_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L4_TIM2 && STM32L4_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L4_TIM2_DAC1 - depends on STM32L4_TIM2_DAC - -config STM32L4_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L4_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L4_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L4_TIM3 && STM32L4_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L4_TIM3_DAC1 - depends on STM32L4_TIM3_DAC - -config STM32L4_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L4_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L4_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L4_TIM4 && STM32L4_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L4_TIM4_DAC1 - depends on STM32L4_TIM4_DAC - -config STM32L4_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L4_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L4_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L4_TIM5 && STM32L4_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L4_TIM5_DAC1 - depends on STM32L4_TIM5_DAC - -config STM32L4_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L4_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L4_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L4_TIM6 && STM32L4_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L4_TIM6_DAC1 - depends on STM32L4_TIM6_DAC - -config STM32L4_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L4_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L4_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L4_TIM7 && STM32L4_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L4_TIM7_DAC1 - depends on STM32L4_TIM7_DAC - -config STM32L4_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L4_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L4_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L4_TIM8 && STM32L4_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L4_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L4_TIM8_DAC1 - depends on STM32L4_TIM8_DAC - -config STM32L4_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L4_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L4_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L4_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L4_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L4_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L4_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L4_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L4_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L4_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -menu "STM32L4 TIMx Outputs Configuration" - -config STM32L4_TIM1_CH1POL - int "TIM1 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output polarity - -config STM32L4_TIM1_CH1IDLE - int "TIM1 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1OUT - ---help--- - TIM1 Channel 1 output IDLE - -config STM32L4_TIM1_CH1NPOL - int "TIM1 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output polarity - -config STM32L4_TIM1_CH1NIDLE - int "TIM1 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH1NOUT - ---help--- - TIM1 Channel 1 Complementary Output IDLE - -config STM32L4_TIM1_CH2POL - int "TIM1 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output polarity - -config STM32L4_TIM1_CH2IDLE - int "TIM1 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2OUT - ---help--- - TIM1 Channel 2 output IDLE - -config STM32L4_TIM1_CH2NPOL - int "TIM1 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output polarity - -config STM32L4_TIM1_CH2NIDLE - int "TIM1 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH2NOUT - ---help--- - TIM1 Channel 2 Complementary Output IDLE - -config STM32L4_TIM1_CH3POL - int "TIM1 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output polarity - -config STM32L4_TIM1_CH3IDLE - int "TIM1 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3OUT - ---help--- - TIM1 Channel 3 output IDLE - -config STM32L4_TIM1_CH3NPOL - int "TIM1 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output polarity - -config STM32L4_TIM1_CH3NIDLE - int "TIM1 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH3NOUT - ---help--- - TIM1 Channel 3 Complementary Output IDLE - -config STM32L4_TIM1_CH4POL - int "TIM1 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output polarity - -config STM32L4_TIM1_CH4IDLE - int "TIM1 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH4OUT - ---help--- - TIM1 Channel 4 output IDLE - -config STM32L4_TIM1_CH5POL - int "TIM1 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output polarity - -config STM32L4_TIM1_CH5IDLE - int "TIM1 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH5OUT - ---help--- - TIM1 Channel 5 output IDLE - -config STM32L4_TIM1_CH6POL - int "TIM1 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output polarity - -config STM32L4_TIM1_CH6IDLE - int "TIM1 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM1_CH6OUT - ---help--- - TIM1 Channel 6 output IDLE - -config STM32L4_TIM2_CH1POL - int "TIM2 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output polarity - -config STM32L4_TIM2_CH1IDLE - int "TIM2 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH1OUT - ---help--- - TIM2 Channel 1 output IDLE - -config STM32L4_TIM2_CH2POL - int "TIM2 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output polarity - -config STM32L4_TIM2_CH2IDLE - int "TIM2 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH2OUT - ---help--- - TIM2 Channel 2 output IDLE - -config STM32L4_TIM2_CH3POL - int "TIM2 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output polarity - -config STM32L4_TIM2_CH3IDLE - int "TIM2 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH3OUT - ---help--- - TIM2 Channel 3 output IDLE - -config STM32L4_TIM2_CH4POL - int "TIM2 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output polarity - -config STM32L4_TIM2_CH4IDLE - int "TIM2 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM2_CH4OUT - ---help--- - TIM2 Channel 4 output IDLE - -config STM32L4_TIM3_CH1POL - int "TIM3 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output polarity - -config STM32L4_TIM3_CH1IDLE - int "TIM3 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH1OUT - ---help--- - TIM3 Channel 1 output IDLE - -config STM32L4_TIM3_CH2POL - int "TIM3 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output polarity - -config STM32L4_TIM3_CH2IDLE - int "TIM3 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH2OUT - ---help--- - TIM3 Channel 2 output IDLE - -config STM32L4_TIM3_CH3POL - int "TIM3 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output polarity - -config STM32L4_TIM3_CH3IDLE - int "TIM3 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH3OUT - ---help--- - TIM3 Channel 3 output IDLE - -config STM32L4_TIM3_CH4POL - int "TIM3 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output polarity - -config STM32L4_TIM3_CH4IDLE - int "TIM3 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM3_CH4OUT - ---help--- - TIM3 Channel 4 output IDLE - -config STM32L4_TIM4_CH1POL - int "TIM4 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output polarity - -config STM32L4_TIM4_CH1IDLE - int "TIM4 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH1OUT - ---help--- - TIM4 Channel 1 output IDLE - -config STM32L4_TIM4_CH2POL - int "TIM4 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output polarity - -config STM32L4_TIM4_CH2IDLE - int "TIM4 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH2OUT - ---help--- - TIM4 Channel 2 output IDLE - -config STM32L4_TIM4_CH3POL - int "TIM4 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output polarity - -config STM32L4_TIM4_CH3IDLE - int "TIM4 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH3OUT - ---help--- - TIM4 Channel 3 output IDLE - -config STM32L4_TIM4_CH4POL - int "TIM4 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output polarity - -config STM32L4_TIM4_CH4IDLE - int "TIM4 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM4_CH4OUT - ---help--- - TIM4 Channel 4 output IDLE - -config STM32L4_TIM5_CH1POL - int "TIM5 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output polarity - -config STM32L4_TIM5_CH1IDLE - int "TIM5 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH1OUT - ---help--- - TIM5 Channel 1 output IDLE - -config STM32L4_TIM5_CH2POL - int "TIM5 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output polarity - -config STM32L4_TIM5_CH2IDLE - int "TIM5 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH2OUT - ---help--- - TIM5 Channel 2 output IDLE - -config STM32L4_TIM5_CH3POL - int "TIM5 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output polarity - -config STM32L4_TIM5_CH3IDLE - int "TIM5 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH3OUT - ---help--- - TIM5 Channel 3 output IDLE - -config STM32L4_TIM5_CH4POL - int "TIM5 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output polarity - -config STM32L4_TIM5_CH4IDLE - int "TIM5 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM5_CH4OUT - ---help--- - TIM5 Channel 4 output IDLE - -config STM32L4_TIM8_CH1POL - int "TIM8 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output polarity - -config STM32L4_TIM8_CH1IDLE - int "TIM8 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1OUT - ---help--- - TIM8 Channel 1 output IDLE - -config STM32L4_TIM8_CH1NPOL - int "TIM8 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output polarity - -config STM32L4_TIM8_CH1NIDLE - int "TIM8 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH1NOUT - ---help--- - TIM8 Channel 1 Complementary Output IDLE - -config STM32L4_TIM8_CH2POL - int "TIM8 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output polarity - -config STM32L4_TIM8_CH2IDLE - int "TIM8 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2OUT - ---help--- - TIM8 Channel 2 output IDLE - -config STM32L4_TIM8_CH2NPOL - int "TIM8 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output polarity - -config STM32L4_TIM8_CH2NIDLE - int "TIM8 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH2NOUT - ---help--- - TIM8 Channel 2 Complementary Output IDLE - -config STM32L4_TIM8_CH3POL - int "TIM8 Channel 3 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output polarity - -config STM32L4_TIM8_CH3IDLE - int "TIM8 Channel 3 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3OUT - ---help--- - TIM8 Channel 3 output IDLE - -config STM32L4_TIM8_CH3NPOL - int "TIM8 Channel 3 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output polarity - -config STM32L4_TIM8_CH3NIDLE - int "TIM8 Channel 3 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH3NOUT - ---help--- - TIM8 Channel 3 Complementary Output IDLE - -config STM32L4_TIM8_CH4POL - int "TIM8 Channel 4 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output polarity - -config STM32L4_TIM8_CH4IDLE - int "TIM8 Channel 4 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH4OUT - ---help--- - TIM8 Channel 4 output IDLE - -config STM32L4_TIM8_CH5POL - int "TIM8 Channel 5 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output polarity - -config STM32L4_TIM8_CH5IDLE - int "TIM8 Channel 5 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH5OUT - ---help--- - TIM8 Channel 5 output IDLE - -config STM32L4_TIM8_CH6POL - int "TIM8 Channel 6 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output polarity - -config STM32L4_TIM8_CH6IDLE - int "TIM8 Channel 6 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM8_CH6OUT - ---help--- - TIM8 Channel 6 output IDLE - -config STM32L4_TIM9_CH1POL - int "TIM9 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output polarity - -config STM32L4_TIM9_CH1IDLE - int "TIM9 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH1OUT - ---help--- - TIM9 Channel 1 output IDLE - -config STM32L4_TIM9_CH2POL - int "TIM9 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output polarity - -config STM32L4_TIM9_CH2IDLE - int "TIM9 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM9_CH2OUT - ---help--- - TIM9 Channel 2 output IDLE - -config STM32L4_TIM10_CH1POL - int "TIM10 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output polarity - -config STM32L4_TIM10_CH1IDLE - int "TIM10 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM10_CH1OUT - ---help--- - TIM10 Channel 1 output IDLE - -config STM32L4_TIM11_CH1POL - int "TIM11 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output polarity - -config STM32L4_TIM11_CH1IDLE - int "TIM11 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM11_CH1OUT - ---help--- - TIM11 Channel 1 output IDLE - -config STM32L4_TIM12_CH1POL - int "TIM12 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output polarity - -config STM32L4_TIM12_CH1IDLE - int "TIM12 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH1OUT - ---help--- - TIM12 Channel 1 output IDLE - -config STM32L4_TIM12_CH2POL - int "TIM12 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output polarity - -config STM32L4_TIM12_CH2IDLE - int "TIM12 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM12_CH2OUT - ---help--- - TIM12 Channel 2 output IDLE - -config STM32L4_TIM13_CH1POL - int "TIM13 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output polarity - -config STM32L4_TIM13_CH1IDLE - int "TIM13 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM13_CH1OUT - ---help--- - TIM13 Channel 1 output IDLE - -config STM32L4_TIM14_CH1POL - int "TIM14 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output polarity - -config STM32L4_TIM14_CH1IDLE - int "TIM14 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM14_CH1OUT - ---help--- - TIM14 Channel 1 output IDLE - -config STM32L4_TIM15_CH1POL - int "TIM15 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output polarity - -config STM32L4_TIM15_CH1IDLE - int "TIM15 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1OUT - ---help--- - TIM15 Channel 1 output IDLE - -config STM32L4_TIM15_CH1NPOL - int "TIM15 Channel 1 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output polarity - -config STM32L4_TIM15_CH1NIDLE - int "TIM15 Channel 1 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH1NOUT - ---help--- - TIM15 Channel 1 Complementary Output IDLE - -config STM32L4_TIM15_CH2POL - int "TIM15 Channel 2 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output polarity - -config STM32L4_TIM15_CH2IDLE - int "TIM15 Channel 2 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2OUT - ---help--- - TIM15 Channel 2 output IDLE - -config STM32L4_TIM15_CH2NPOL - int "TIM15 Channel 2 Complementary Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output polarity - -config STM32L4_TIM15_CH2NIDLE - int "TIM15 Channel 2 Complementary Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM15_CH2NOUT - ---help--- - TIM15 Channel 2 Complementary Output IDLE - -config STM32L4_TIM16_CH1POL - int "TIM16 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output polarity - -config STM32L4_TIM16_CH1IDLE - int "TIM16 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM16_CH1OUT - ---help--- - TIM16 Channel 1 output IDLE - -config STM32L4_TIM17_CH1POL - int "TIM17 Channel 1 Output polarity" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output polarity - -config STM32L4_TIM17_CH1IDLE - int "TIM17 Channel 1 Output IDLE" - default 0 - range 0 1 - depends on STM32L4_TIM17_CH1OUT - ---help--- - TIM17 Channel 1 output IDLE - -endmenu #STM32L4 TIMx Outputs Configuration - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L4_ADC - -config STM32L4_ADC_MAX_SAMPLES - int "The maximum number of channels that can be sampled" - default 16 - ---help--- - The maximum number of samples which can be handled without - overrun depends on various factors. This is the user's - responsibility to correctly select this value. - Since the interface to update the sampling time is available - for all supported devices, the user can change the default - values in the board initialization logic and avoid ADC overrun. - -config STM32L4_ADC_NO_STARTUP_CONV - bool "Do not start conversion when opening ADC device" - default n - ---help--- - Do not start conversion when opening ADC device. - -config STM32L4_ADC_NOIRQ - bool "Do not use default ADC interrupts" - default n - ---help--- - Do not use default ADC interrupts handlers. - -config STM32L4_ADC_SMPR - int "ADC sample time" - default 0 - range 0 7 - ---help--- - ADC sample time - 0 - 2.5 ADC clock cycles - 1 - 6.5 ADC clock cycles - 2 - 12.5 ADC clock cycles - 3 - 24.5 ADC clock cycles - 4 - 47.5 ADC clock cycles - 5 - 92.5 ADC clock cycles - 6 - 247.5 ADC clock cycles - 7 - 640.5 ADC clock cycles - -config STM32L4_ADC_LL_OPS - bool "ADC low-level operations" - default n - ---help--- - Enable low-level ADC ops. - -config STM32L4_ADC1_RESOLUTION - int "ADC1 resolution" - depends on STM32L4_ADC1 - default 0 - range 0 3 - ---help--- - ADC1 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC2_RESOLUTION - int "ADC2 resolution" - depends on STM32L4_ADC2 - default 0 - range 0 3 - ---help--- - ADC2 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC3_RESOLUTION - int "ADC3 resolution" - depends on STM32L4_ADC3 - default 0 - range 0 3 - ---help--- - ADC3 resolution. 0 - 12 bit, 1 - 10 bit, 2 - 8 bit, 3 - 6 bit - -config STM32L4_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L4_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC1_DMA_CFG - int "ADC1 DMA configuration" - depends on STM32L4_ADC1_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC1 DMA in One Shot Mode, 1 - ADC1 DMA in Circular Mode - -config STM32L4_ADC1_DMA_BATCH - int "ADC1 DMA number of conversions" - depends on STM32L4_ADC1 && STM32L4_ADC1_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L4_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC2_DMA_CFG - int "ADC2 DMA configuration" - depends on STM32L4_ADC2_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC2 DMA in One Shot Mode, 1 - ADC2 DMA in Circular Mode - -config STM32L4_ADC2_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC2 && STM32L4_ADC2_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L4_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L4_ADC3_DMA_CFG - int "ADC3 DMA configuration" - depends on STM32L4_ADC3_DMA - range 0 1 - default 1 - ---help--- - 0 - ADC3 DMA in One Shot Mode, 1 - ADC3 DMA in Circular Mode - -config STM32L4_ADC3_DMA_BATCH - int "ADC2 DMA number of conversions" - depends on STM32L4_ADC3 && STM32L4_ADC3_DMA - default 1 - ---help--- - This option allows you to select the number of regular group conversions - that will trigger a DMA callback transerring data to the upper-half driver. - By default, this value is 1, which means that data is transferred after - each group conversion. - -config STM32L4_ADC1_INJ_CHAN - int "ADC1 configured injected channels" - depends on STM32L4_ADC1 - range 0 4 - default 0 - ---help--- - Number of configured ADC1 injected channels. - -config STM32L4_ADC2_INJ_CHAN - int "ADC2 configured injected channels" - depends on STM32L4_ADC2 - range 0 4 - default 0 - ---help--- - Number of configured ADC2 injected channels. - -config STM32L4_ADC3_INJ_CHAN - int "ADC3 configured injected channels" - depends on STM32L4_ADC3 - range 0 4 - default 0 - ---help--- - Number of configured ADC3 injected channels. - -config STM32L4_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L4_ADC1 && STM32L4_DFSDM1 && (STM32L4_STM32L496XX || STM32L4_STM32L4XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L4_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L4_ADC2 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L4_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L4_ADC3 && STM32L4_DFSDM1 && STM32L4_STM32L496XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -menu "STM32L4 ADCx triggering Configuration" - -config STM32L4_ADC1_EXTTRIG - int "ADC1 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_EXTTRIG > 0 - -config STM32L4_ADC1_EXTSEL - int "ADC1 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC2_EXTTRIG - int "ADC2 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_EXTTRIG > 0 - -config STM32L4_ADC2_EXTSEL - int "ADC2 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -config STM32L4_ADC3_EXTTRIG - int "ADC3 External trigger configuration for regular channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware trigger detection disabled - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_EXTTRIG > 0 - -config STM32L4_ADC3_EXTSEL - int "ADC3 External trigger selection for regular group" - default 0 - range 0 15 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of - a regular group. See Reference Manual for more information. - -endif - -if STM32L4_ADC1_INJ_CHAN > 0 - -config STM32L4_ADC1_JEXTTRIG - int "ADC1 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC1 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC1_JEXTTRIG > 0 - -config STM32L4_ADC1_JEXTSEL - int "ADC1 External Trigger Selection for injected group" - default 0 - range 0 15 - depends on STM32L4_ADC1 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC2_INJ_CHAN > 0 - -config STM32L4_ADC2_JEXTTRIG - int "ADC2 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC2 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC2_JEXTTRIG > 0 - -config STM32L4_ADC2_JEXTSEL - int "ADC2 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC2 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -if STM32L4_ADC3_INJ_CHAN > 0 - -config STM32L4_ADC3_JEXTTRIG - int "ADC3 External Trigger Enable and Polarity Selection for injected channels" - default 0 - range 0 4 - depends on STM32L4_ADC3 - ---help--- - Values 0: Hardware and software trigger detection disabled, JQDIS=0 - (queue enabled) - 0: Hardware trigger detection disabled, JQDIS=1 (queue disabled) - 1: Hardware trigger detection on the rising edge - 2: Hardware trigger detection on the falling edge - 3: Hardware trigger detection on the rising and falling edges - -if STM32L4_ADC3_JEXTTRIG > 0 - -config STM32L4_ADC3_JEXTSEL - int "ADC3 External Trigger Selection for injected group" - default 0 - range 0 5 - depends on STM32L4_ADC3 - ---help--- - Select the external event used to trigger the start of conversion of an - injected group - -endif - -endif - -endmenu #STM32L4 ADCx triggering Configuration - -endmenu - -menu "DAC Configuration" - depends on STM32L4_DAC - -config STM32L4_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L4_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC1_DMA - -config STM32L4_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L4_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L4_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L4_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L4_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L4_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L4_DAC2_DMA - -config STM32L4_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L4_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L4_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L4_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L4_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -config STM32L4_DAC_LL_OPS - bool "DAC low-level operations" - default n - ---help--- - Enable low-level DAC ops. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L4_DFSDM1 - -config STM32L4_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L4_STM32L4X3 - select STM32L4_DFSDM - -config STM32L4_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L4_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L4_SERIALDRIVER - bool - -config STM32L4_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L4_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L4_LPUART1_SERIALDRIVER - depends on STM32L4_LPUART1 - -config STM32L4_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L4_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L4_LPUART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L4_USART1_SERIALDRIVER - depends on STM32L4_USART1 - -config STM32L4_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L4_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L4_USART1 && (STM32L4_DMA1 || STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L4_USART2_SERIALDRIVER - depends on STM32L4_USART2 - -config STM32L4_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L4_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L4_USART2 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L4_USART3_SERIALDRIVER - depends on STM32L4_USART3 - -config STM32L4_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L4_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L4_USART3 && (STM32L4_DMA1 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L4_UART4_SERIALDRIVER - depends on STM32L4_UART4 - -config STM32L4_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L4_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L4_UART4 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L4_UART5_SERIALDRIVER - depends on STM32L4_UART5 - -config STM32L4_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L4_SERIALDRIVER - -config STM32L4_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L4_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L4_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L4_UART5 && (STM32L4_DMA2 || STM32L4_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L4_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L4_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L4_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_USART3 || STM32L4_UART4 || STM32L4_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L4_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L4_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L4_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L4_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L4_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L4_USART && STM32L4_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L4 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L4_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L4_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L4 serial driver. - -config STM32L4_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L4_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L4 serial driver. - -config STM32L4_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L4_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L4 serial driver. - -if PM - -config STM32L4_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L4_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L4_SPI - -config STM32L4_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L4_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L4_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L4_I2C - -config STM32L4_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L4_I2C - -config STM32L4_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -config STM32L4_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L4_I2C && !STM32L4_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L4_SDMMC - -config STM32L4_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L4_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L4_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L4_SDMMC1 - -config STM32L4_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L4_CAN1 || STM32L4_CAN2 - -config STM32L4_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L4_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L4_CAN1 is defined. - -config STM32L4_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L4_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L4_CAN2 is defined. - -config STM32L4_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L4_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L4_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L4_TIM1 || STM32L4_TIM2 || STM32L4_TIM3 || STM32L4_TIM4 || STM32L4_TIM5 || STM32L4_TIM8 - -config STM32L4_TIM1_QE - bool "TIM1" - default n - depends on STM32L4_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L4_TIM1_QE - -config STM32L4_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM2_QE - bool "TIM2" - default n - depends on STM32L4_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L4_TIM2_QE - -config STM32L4_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM3_QE - bool "TIM3" - default n - depends on STM32L4_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L4_TIM3_QE - -config STM32L4_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM4_QE - bool "TIM4" - default n - depends on STM32L4_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L4_TIM4_QE - -config STM32L4_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM5_QE - bool "TIM5" - default n - depends on STM32L4_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L4_TIM5_QE - -config STM32L4_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_TIM8_QE - bool "TIM8" - default n - depends on STM32L4_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L4_TIM8_QE - -config STM32L4_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L4_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L4_QENCODER_SAMPLE_FDTS_4 - -config STM32L4_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L4_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L4_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L4_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L4_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L4_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L4_QENCODER_FILTER - prompt "Input channel event count" - default STM32L4_QENCODER_SAMPLE_EVENT_6 - -config STM32L4_QENCODER_SAMPLE_EVENT_1 - depends on STM32L4_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L4_QENCODER_SAMPLE_EVENT_2 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L4_QENCODER_SAMPLE_EVENT_4 - depends on STM32L4_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L4_QENCODER_SAMPLE_EVENT_5 - depends on STM32L4_QENCODER_SAMPLE_FDTS_16 || STM32L4_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L4_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L4_QENCODER_SAMPLE_FDTS && !STM32L4_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L4_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L4_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L4_SAI - -choice - prompt "Operation mode" - default STM32L4_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L4_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L4_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L4_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L4_SAI1_BOTH_ASYNC - depends on STM32L4_SAI1_A && STM32L4_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L4_SAI2_BOTH_ASYNC - depends on STM32L4_SAI2_A && STM32L4_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L4_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L4_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L4_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L4 diff --git a/arch/arm/src/stm32l4/Make.defs b/arch/arm/src/stm32l4/Make.defs index 3d981681ff0..d7609705c50 100644 --- a/arch/arm/src/stm32l4/Make.defs +++ b/arch/arm/src/stm32l4/Make.defs @@ -50,11 +50,11 @@ else CHIP_CSRCS += stm32l4_tickless.c endif -ifeq ($(CONFIG_STM32L4_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32l4_oneshot.c stm32l4_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32L4_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32l4_freerun.c endif @@ -62,37 +62,37 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c endif -ifeq ($(CONFIG_STM32L4_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32l4_hsi48.c endif -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CHIP_CSRCS += stm32l4_adc.c endif -ifeq ($(CONFIG_STM32L4_DAC),y) +ifeq ($(CONFIG_STM32_DAC),y) CHIP_CSRCS += stm32l4_dac.c endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) +ifeq ($(CONFIG_STM32_DFSDM),y) CHIP_CSRCS += stm32l4_dfsdm.c endif -ifeq ($(CONFIG_STM32L4_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32l4_dma.c endif ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32L4_USBFS),y) +ifeq ($(CONFIG_STM32_USBFS),y) CHIP_CSRCS += stm32l4_usbdev.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfsdev.c endif endif ifeq ($(CONFIG_USBHOST),y) -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CHIP_CSRCS += stm32l4_otgfshost.c endif endif @@ -116,11 +116,11 @@ CHIP_CSRCS += stm32l4_pminitialize.c endif endif -ifeq ($(CONFIG_STM32L4_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32l4_exti_pwr.c endif -ifeq ($(CONFIG_STM32L4_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32l4_exti_alarm.c endif @@ -137,27 +137,27 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32l4_dumpgpio.c endif -ifeq ($(CONFIG_STM32L4_COMP),y) +ifeq ($(CONFIG_STM32_COMP),y) CHIP_CSRCS += stm32l4_comp.c stm32l4_exti_comp.c endif -ifeq ($(CONFIG_STM32L4_RNG),y) +ifeq ($(CONFIG_STM32_RNG),y) CHIP_CSRCS += stm32l4_rng.c endif -ifeq ($(CONFIG_STM32L4_SAI),y) +ifeq ($(CONFIG_STM32_SAI),y) CHIP_CSRCS += stm32l4_sai.c endif -ifeq ($(CONFIG_STM32L4_LPTIM),y) +ifeq ($(CONFIG_STM32_LPTIM),y) CHIP_CSRCS += stm32l4_lptim.c endif -ifeq ($(CONFIG_STM32L4_PWM),y) +ifeq ($(CONFIG_STM32_PWM),y) CHIP_CSRCS += stm32l4_pwm.c endif -ifeq ($(CONFIG_STM32L4_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_PULSECOUNT),y) CHIP_CSRCS += stm32l4_pulsecount.c endif @@ -165,26 +165,26 @@ ifeq ($(CONFIG_SENSORS_QENCODER),y) CHIP_CSRCS += stm32l4_qencoder.c endif -ifeq ($(CONFIG_STM32L4_QSPI),y) +ifeq ($(CONFIG_STM32_QSPI),y) CHIP_CSRCS += stm32l4_qspi.c endif -ifeq ($(CONFIG_STM32L4_CAN),y) +ifeq ($(CONFIG_STM32_CAN),y) CHIP_CSRCS += stm32l4_can.c endif -ifeq ($(CONFIG_STM32L4_FIREWALL),y) +ifeq ($(CONFIG_STM32_FIREWALL),y) CHIP_CSRCS += stm32l4_firewall.c endif -ifeq ($(CONFIG_STM32L4_IWDG),y) +ifeq ($(CONFIG_STM32_IWDG),y) CHIP_CSRCS += stm32l4_iwdg.c endif -ifeq ($(CONFIG_STM32L4_SDMMC1),y) +ifeq ($(CONFIG_STM32_SDMMC1),y) CHIP_CSRCS += stm32l4_sdmmc.c endif -ifeq ($(CONFIG_STM32L4_1WIREDRIVER),y) +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) CHIP_CSRCS += stm32l4_1wire.c endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h index f030bc56d98..edd726b2626 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_adc.h @@ -74,7 +74,7 @@ #define STM32_ADC_CSR_OFFSET 0x0000 /* Common status register */ #define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */ #endif @@ -169,7 +169,7 @@ #define STM32_ADC_CSR (STM32_ADCCMN_BASE+STM32_ADC_CSR_OFFSET) #define STM32_ADC_CCR (STM32_ADCCMN_BASE+STM32_ADC_CCR_OFFSET) -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_ADC_CDR (STM32_ADCCMN_BASE+STM32_ADC_CDR_OFFSET) #endif @@ -226,23 +226,23 @@ # define ADC_CFGR_EXTSEL_T1CC3 (0x02 << ADC_CFGR_EXTSEL_SHIFT) /* 0010: Timer 1 CC3 event */ # define ADC_CFGR_EXTSEL_T2CC4 (0x03 << ADC_CFGR_EXTSEL_SHIFT) /* 0011: Timer 2 CC4 event */ # define ADC_CFGR_EXTSEL_T3TRGO (0x04 << ADC_CFGR_EXTSEL_SHIFT) /* 0100: Timer 3 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4CC4 (0x05 << ADC_CFGR_EXTSEL_SHIFT) /* 0101: Timer 4 CC4 event */ # endif # define ADC_CFGR_EXTSEL_EXTI11 (0x06 << ADC_CFGR_EXTSEL_SHIFT) /* 0110: EXTI line 11 */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T8TRGO (0x07 << ADC_CFGR_EXTSEL_SHIFT) /* 0111: Timer 8 TRGO event */ # define ADC_CFGR_EXTSEL_T8TRGO2 (0x08 << ADC_CFGR_EXTSEL_SHIFT) /* 1000: Timer 8 TRGO2 event */ # endif # define ADC_CFGR_EXTSEL_T1TRGO (0x09 << ADC_CFGR_EXTSEL_SHIFT) /* 1001: Timer 1 TRGO event */ # define ADC_CFGR_EXTSEL_T1TRGO2 (0x0a << ADC_CFGR_EXTSEL_SHIFT) /* 1010: Timer 1 TRGO2 event */ # define ADC_CFGR_EXTSEL_T2TRGO (0x0b << ADC_CFGR_EXTSEL_SHIFT) /* 1011: Timer 2 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T4TRGO (0x0c << ADC_CFGR_EXTSEL_SHIFT) /* 1100: Timer 4 TRGO event */ # endif # define ADC_CFGR_EXTSEL_T6TRGO (0x0d << ADC_CFGR_EXTSEL_SHIFT) /* 1101: Timer 6 TRGO event */ # define ADC_CFGR_EXTSEL_T15TRGO (0x0e << ADC_CFGR_EXTSEL_SHIFT) /* 1110: Timer 15 TRGO event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define ADC_CFGR_EXTSEL_T3CC4 (0x0f << ADC_CFGR_EXTSEL_SHIFT) /* 1111: Timer 3 CC4 event */ # endif #define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */ @@ -541,7 +541,7 @@ #define ADC_CSR_AWD3_MST (1 << 9) /* Bit 9: Analog watchdog 3 flag (master ADC) */ #define ADC_CSR_JQOVF_MST (1 << 10) /* Bit 10: Injected Context Queue Overflow flag (master ADC) */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CSR_ADRDY_SLV (1 << 16) /* Bit 16: Slave ADC ready */ # define ADC_CSR_EOSMP_SLV (1 << 17) /* Bit 17: End of Sampling phase flag (slave ADC) */ # define ADC_CSR_EOC_SLV (1 << 18) /* Bit 18: End of regular conversion (slave ADC) */ @@ -557,7 +557,7 @@ /* Common control register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CCR_DUAL_SHIFT (0) /* Bits 0-4: Dual ADC mode selection */ # define ADC_CCR_DUAL_MASK (31 << ADC_CCR_DUAL_SHIFT) # define ADC_CCR_DUAL_IND (0 << ADC_CCR_DUAL_SHIFT) /* Independent mode */ @@ -605,7 +605,7 @@ /* Common regular data register for dual mode */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define ADC_CDR_RDATA_MST_SHIFT (0) /* Bits 0-15: Regular data of the master ADC */ # define ADC_CDR_RDATA_MST_MASK (0xffff << ADC_CDR_RDATA_MST_SHIFT) # define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h index 350f0ab77f7..6752cb25ed0 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_comp.h @@ -58,7 +58,7 @@ # define COMP_CSR_INMSEL_DAC1 (4 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel1 */ # define COMP_CSR_INMSEL_DAC2 (5 << COMP_CSR_INMSEL_SHIFT) /* DAC Channel2 */ # define COMP_CSR_INMSEL_PIN1 (6 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 1: COMP1=PB1; COMP2=PB3 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMSEL_INMESEL (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: Selected by INMESEL */ #else # define COMP_CSR_INMSEL_PIN2 (7 << COMP_CSR_INMSEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ @@ -68,7 +68,7 @@ #define COMP_CSR_INPSEL_MASK (3 << COMP_CSR_INPSEL_SHIFT) # define COMP_CSR_INPSEL_PIN1 (0 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 1: COMP1=PC5; COMP2=PB4 */ # define COMP_CSR_INPSEL_PIN2 (1 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 2: COMP1=PB2; COMP2=PB6 */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INPSEL_PIN3 (2 << COMP_CSR_INPSEL_SHIFT) /* Input plus pin 3: COMP1=PA1; COMP2=PA3 */ #endif @@ -101,7 +101,7 @@ #define COMP_CSR_BRGEN (1 << 22) /* Bit 22: Scaler bridge enable */ #define COMP_CSR_SCALEN (1 << 23) /* Bit 23: Voltage scaler enable bit */ /* Bit 24: Reserved */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define COMP_CSR_INMESEL_SHIFT (25) /* Bits 25-26: Input minus extended selection bits */ # define COMP_CSR_INMESEL_MASK (3 << COMP_CSR_INMESEL_SHIFT) # define COMP_CSR_INMESEL_PIN2 (0 << COMP_CSR_INMESEL_SHIFT) /* Input minus pin 2: COMP1=PC4; COMP2=PB7 */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h index eaa9eae9024..e64073321a2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_dfsdm.h @@ -47,7 +47,7 @@ #define STM32_DFSDM_CH1CFGR1_OFFSET 0x0020 /* DFSDM channel configuration 1 register */ #define STM32_DFSDM_CH2CFGR1_OFFSET 0x0040 /* DFSDM channel configuration 2 register */ #define STM32_DFSDM_CH3CFGR1_OFFSET 0x0060 /* DFSDM channel configuration 3 register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_DFSDM_CH4CFGR1_OFFSET 0x0080 /* DFSDM channel configuration 4 register */ # define STM32_DFSDM_CH5CFGR1_OFFSET 0x00a0 /* DFSDM channel configuration 5 register */ # define STM32_DFSDM_CH6CFGR1_OFFSET 0x00c0 /* DFSDM channel configuration 6 register */ @@ -60,7 +60,7 @@ #define STM32_DFSDM_CH1CFGR2_OFFSET 0x0024 /* DFSDM channel configuration 1 register 2 */ #define STM32_DFSDM_CH2CFGR2_OFFSET 0x0044 /* DFSDM channel configuration 2 register 2 */ #define STM32_DFSDM_CH3CFGR2_OFFSET 0x0064 /* DFSDM channel configuration 3 register 2 */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_DFSDM_CH4CFGR2_OFFSET 0x0084 /* DFSDM channel configuration 4 register 2 */ # define STM32_DFSDM_CH5CFGR2_OFFSET 0x00a4 /* DFSDM channel configuration 5 register 2 */ # define STM32_DFSDM_CH6CFGR2_OFFSET 0x00c4 /* DFSDM channel configuration 6 register 2 */ @@ -73,7 +73,7 @@ #define STM32_DFSDM_CH1AWSCDR_OFFSET 0x0028 /* DFSDM channel 1 analog watchdog and short-circuit detector register */ #define STM32_DFSDM_CH2AWSCDR_OFFSET 0x0048 /* DFSDM channel 2 analog watchdog and short-circuit detector register */ #define STM32_DFSDM_CH3AWSCDR_OFFSET 0x0068 /* DFSDM channel 3 analog watchdog and short-circuit detector register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_DFSDM_CH4AWSCDR_OFFSET 0x0088 /* DFSDM channel 4 analog watchdog and short-circuit detector register */ # define STM32_DFSDM_CH5AWSCDR_OFFSET 0x00a8 /* DFSDM channel 5 analog watchdog and short-circuit detector register */ # define STM32_DFSDM_CH6AWSCDR_OFFSET 0x00c8 /* DFSDM channel 6 analog watchdog and short-circuit detector register */ @@ -86,7 +86,7 @@ #define STM32_DFSDM_CH1WDATR_OFFSET 0x002c /* DFSDM channel 1 watchdog filter data register */ #define STM32_DFSDM_CH2WDATR_OFFSET 0x004c /* DFSDM channel 2 watchdog filter data register */ #define STM32_DFSDM_CH3WDATR_OFFSET 0x006c /* DFSDM channel 3 watchdog filter data register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_DFSDM_CH4WDATR_OFFSET 0x008c /* DFSDM channel 4 watchdog filter data register */ # define STM32_DFSDM_CH5WDATR_OFFSET 0x00ac /* DFSDM channel 5 watchdog filter data register */ # define STM32_DFSDM_CH6WDATR_OFFSET 0x00cc /* DFSDM channel 6 watchdog filter data register */ @@ -99,14 +99,14 @@ #define STM32_DFSDM_CH1DATINR_OFFSET 0x0030 /* DFSDM channel 1 data input register */ #define STM32_DFSDM_CH2DATINR_OFFSET 0x0050 /* DFSDM channel 2 data input register */ #define STM32_DFSDM_CH3DATINR_OFFSET 0x0070 /* DFSDM channel 3 data input register */ -#ifndef CONFIG_STM32L4_STM32L4X3 +#ifndef CONFIG_STM32_STM32L4X3 # define STM32_DFSDM_CH4DATINR_OFFSET 0x0090 /* DFSDM channel 4 data input register */ # define STM32_DFSDM_CH5DATINR_OFFSET 0x00b0 /* DFSDM channel 5 data input register */ # define STM32_DFSDM_CH6DATINR_OFFSET 0x00d0 /* DFSDM channel 6 data input register */ # define STM32_DFSDM_CH7DATINR_OFFSET 0x00f0 /* DFSDM channel 7 data input register */ #endif -#ifdef CONFIG_STM32L4_STM32L4XR +#ifdef CONFIG_STM32_STM32L4XR # define STM32_DFSDM_CHDLYR_OFFSET(ch) (0x14 + 0x20 * (ch)) /* DFSDM channel delay register */ # define STM32_DFSDM_CH0DLYR_OFFSET 0x0014 /* DFSDM channel 0 delay register */ @@ -148,7 +148,7 @@ #define STM32_DFSDM_CHAWSCDR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHAWSCDR_OFFSET(y)) #define STM32_DFSDM_CHWDATR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHWDATR_OFFSET(y) #define STM32_DFSDM_CHDATINR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDATINR_OFFSET(y)) -#ifdef CONFIG_STM32L4_STM32L4XR +#ifdef CONFIG_STM32_STM32L4XR # define STM32_DFSDM_CHDLYR(y) (STM32_DFSDM_BASE + STM32_DFSDM_CHDLYR_OFFSET(y)) #endif @@ -289,17 +289,17 @@ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO (0x00 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0000: Timer 1 TRGO event */ # define DFSDM_FLTCR1_JEXTSEL_T1TRGO2 (0x01 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0001: Timer 1 TRGO2 event */ -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 8 TRGO event */ # else # define DFSDM_FLTCR1_JEXTSEL_T3TRGO (0x02 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0010: Timer 3 TRGO event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T8TRGO2 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 8 TRGO2 event */ # else # define DFSDM_FLTCR1_JEXTSEL_T16CC1 (0x03 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0011: Timer 16 CC1 (or OC1) event */ # endif -# if !defined(CONFIG_STM32L4_STM32L4X3) +# if !defined(CONFIG_STM32_STM32L4X3) # define DFSDM_FLTCR1_JEXTSEL_T4TRGO (0x04 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0100: Timer 4 TRGO event */ # endif # define DFSDM_FLTCR1_JEXTSEL_T6TRGO (0x05 << DFSDM_FLTCR1_JEXTSEL_SHIFT) /* 0101: Timer 6 TRGO event */ @@ -413,8 +413,8 @@ /* DFSDM data register for the regular channel (DFSDM_FLTxRDATAR) */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define DFSDM_FLTRDATAR_RDATACH_SHIFT (0) /* Bits 0-3: channel most recently converted */ # define DFSDM_FLTRDATAR_RDATACH_MASK (7 << DFSDM_FLTRDATAR_RDATACH_SHIFT) #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h index 738544c954e..7261aeb2596 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_flash.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with * CONFIG_STM32L4_FLASH_OVERRIDE_x. For example: @@ -47,10 +47,10 @@ * The STM32L4x5/STM32L4x6 devices have two banks, but on 512 and 256 Kb * devices an option byte is available to map all pages to the first bank. * - * The STM32L43x/44x/45x/46x chips (CONFIG_STM32L4_STM32L4X3) have a + * The STM32L43x/44x/45x/46x chips (CONFIG_STM32_STM32L4X3) have a * single bank only. * - * STM32L4+ devices (CONFIG_STM32L4_STM32L4XR) have single and dual bank + * STM32L4+ devices (CONFIG_STM32_STM32L4XR) have single and dual bank * operating modes. * * The STM32L4R/Sxx devices have 1 Mb or 2 Mb of flash @@ -69,65 +69,65 @@ #define _K(x) ((x)*1024) -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_G) && \ - !defined(CONFIG_STM32L4_FLASH_CONFIG_I) -# define CONFIG_STM32L4_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_I) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_I) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L4_FLASH_CONFIG_8 -# undef CONFIG_STM32L4_FLASH_CONFIG_B -# undef CONFIG_STM32L4_FLASH_CONFIG_C -# undef CONFIG_STM32L4_FLASH_CONFIG_E -# undef CONFIG_STM32L4_FLASH_CONFIG_G -# undef CONFIG_STM32L4_FLASH_CONFIG_I -# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_8) -# define CONFIG_STM32L4_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) -# define CONFIG_STM32L4_FLASH_CONFIG_B -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) -# define CONFIG_STM32L4_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) -# define CONFIG_STM32L4_FLASH_CONFIG_E -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) -# define CONFIG_STM32L4_FLASH_CONFIG_G -# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_I) -# define CONFIG_STM32L4_FLASH_CONFIG_I +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# undef CONFIG_STM32_FLASH_CONFIG_I +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_I) +# define CONFIG_STM32_FLASH_CONFIG_I # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L4_FLASH_CONFIG_8) /* 64 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ # define STM32_FLASH_NPAGES 32 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ # define STM32_FLASH_NPAGES 64 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32L4_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2 MB, STM32L4+ only */ # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 4096 #else @@ -152,14 +152,14 @@ #define STM32_FLASH_PCROP1ER_OFFSET 0x0028 #define STM32_FLASH_WRP1AR_OFFSET 0x002c #define STM32_FLASH_WRP1BR_OFFSET 0x0030 -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define STM32_FLASH_PCROP2SR_OFFSET 0x0044 # define STM32_FLASH_PCROP2ER_OFFSET 0x0048 # define STM32_FLASH_WRP2AR_OFFSET 0x004c # define STM32_FLASH_WRP2BR_OFFSET 0x0050 #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_FLASH_CFGR_OFFSET 0x0130 #endif @@ -177,14 +177,14 @@ #define STM32_FLASH_PCROP1ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP1ER_OFFSET) #define STM32_FLASH_WRP1AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1AR_OFFSET) #define STM32_FLASH_WRP1BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP1BR_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define STM32_FLASH_PCROP2SR (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2SR_OFFSET) # define STM32_FLASH_PCROP2ER (STM32_FLASHIF_BASE+STM32_FLASH_PCROP2ER_OFFSET) # define STM32_FLASH_WRP2AR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2AR_OFFSET) # define STM32_FLASH_WRP2BR (STM32_FLASHIF_BASE+STM32_FLASH_WRP2BR_OFFSET) #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_FLASH_CFGR (STM32_FLASHIF_BASE+STM32_FLASH_CFGR_OFFSET) #endif @@ -224,7 +224,7 @@ #define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */ #define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */ #define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) # define FLASH_SR_PEMPTY (1 << 17) /* Bit 17: Program empty */ #endif @@ -238,8 +238,8 @@ #define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT) #define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */ # define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */ #endif @@ -257,8 +257,8 @@ #define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 0-18: ECC fail address */ #define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT) -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */ #endif #define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */ @@ -275,19 +275,19 @@ #define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */ #define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/ #define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */ -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */ # define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */ #endif -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_DBANK (1 << 22) /* Bit 22: Dual bank mode for 2MB devices */ #endif #define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */ #define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */ #define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L496XX) || \ + defined(CONFIG_STM32_STM32L4XR) # define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */ # define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */ #endif @@ -307,7 +307,7 @@ /* Flash Configuration Register (CFGR) */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define FLASH_CFGR_LVEN (1 << 0) /* Bit 0: Low voltage enable */ #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h index c677abec168..7adfe4082c2 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_memorymap.h @@ -62,7 +62,7 @@ #define STM32_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff6fff: System memory */ #define STM32_OTP_BASE 0x1fff7000 /* 0x1fff7000-0x1fff73ff: OTP memory */ /* 0x1fff7400-0x1fff77ff: Reserved */ -#ifdef CONFIG_STM32L4_STM32L4XR +#ifdef CONFIG_STM32_STM32L4XR # define STM32_OPTION_BASE 0x1ff00000 /* 0x1ff00000-0x1ff0000f: Option bytes */ /* 0x1ff00010-0x1ff00fff: Reserved */ # define STM32_OPTION2_BASE 0x1ff01000 /* 0x1ff01000-0x1ff0100f: Option bytes 2 */ @@ -134,7 +134,7 @@ #define STM32_OPAMP_BASE 0x40007800 #define STM32_DAC_BASE 0x40007400 #define STM32_PWR_BASE 0x40007000 -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define STM32_USB_SRAM_BASE 0x40006c00 # define STM32_USB_FS_BASE 0x40006800 #else @@ -176,7 +176,7 @@ #define STM32_TIM8_BASE 0x40013400 #define STM32_SPI1_BASE 0x40013000 #define STM32_TIM1_BASE 0x40012c00 -#ifndef CONFIG_STM32L4_STM32L4XR +#ifndef CONFIG_STM32_STM32L4XR # define STM32_SDMMC1_BASE 0x40012800 #endif #define STM32_FIREWALL_BASE 0x40011c00 @@ -199,7 +199,7 @@ /* AHB2 Base Addresses ******************************************************/ -#ifdef CONFIG_STM32L4_STM32L4XR +#ifdef CONFIG_STM32_STM32L4XR # define STM32_SDMMC1_BASE 0x50062400 #endif #define STM32_OCTOSPIIOM_BASE 0x50061c00 diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h index c8e33f62f18..ed73d23b642 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pinmap.h @@ -30,13 +30,13 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_pinmap.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_pinmap.h" #else # error "Unsupported STM32 L4 pin map" diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index a6aaf5eba1e..09be34e1e02 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -61,7 +61,7 @@ #define STM32_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ #define STM32_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ #define STM32_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ #endif @@ -92,7 +92,7 @@ #define STM32_PWR_PDCRH (STM32_PWR_BASE+STM32_PWR_PDCRH_OFFSET) #define STM32_PWR_PUCRI (STM32_PWR_BASE+STM32_PWR_PUCRI_OFFSET) #define STM32_PWR_PDCRI (STM32_PWR_BASE+STM32_PWR_PDCRI_OFFSET) -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define STM32_PWR_CR5 (STM32_PWR_BASE+STM32_PWR_CR5_OFFSET) #endif @@ -107,7 +107,7 @@ # define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */ # define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */ # define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR1_RRSTP (1 << 4) /* Bit 4: SRAM3 retention in Stop 2 mode */ #endif #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */ @@ -133,12 +133,12 @@ # define PWR_CR2_PLS_EXT (7 << PWR_CR2_PLS_SHIFT) /* 111: External input analog voltage PVD_IN */ #define PWR_CR2_PVME1 (1 << 4) /* Bit 4: Peripheral voltage monitoring 1 enable (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_PVME2 (1 << 5) /* Bit 5: Peripheral voltage monitoring 2 enable (VDDIO2 vs 0.9V) */ #endif #define PWR_CR2_PVME3 (1 << 6) /* Bit 6: Peripheral voltage monitoring 3 enable (VDDA vs 1.62V) */ #define PWR_CR2_PVME4 (1 << 7) /* Bit 7: Peripheral voltage monitoring 4 enable (VDDA vs 2.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_CR2_IOSV (1 << 9) /* Bit 9: VDDIO2 Independent I/Os supply valid */ #endif #define PWR_CR2_USV (1 << 10) /* Bit 10: VDDUSB USB supply valid */ @@ -152,7 +152,7 @@ #define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */ #define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */ #define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR3_DSIPDEN (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */ #endif #define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */ @@ -187,7 +187,7 @@ #define PWR_SR2_VOSF (1 << 10) /* Bit 10: Voltage scaling flag */ #define PWR_SR2_PVDO (1 << 11) /* Bit 11: Power voltage detector output */ #define PWR_SR2_PVMO1 (1 << 12) /* Bit 12: Peripheral voltage monitoring output 1 (VDDUSB vs 1.2V) */ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) # define PWR_SR2_PVMO2 (1 << 13) /* Bit 13: Peripheral voltage monitoring output 2 (VDDIO2 vs 0.9V) */ #endif #define PWR_SR2_PVMO3 (1 << 14) /* Bit 14: Peripheral voltage monitoring output 3 (VDDA vs 1.62V) */ @@ -208,7 +208,7 @@ /* Power control register 5 */ -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) # define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */ #endif diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h index a038906b332..3671571d944 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_syscfg.h @@ -30,13 +30,13 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_syscfg.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_syscfg.h" #else # error "Unsupported STM32 L4 chip" diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h index 1fdac887f95..e3adb9b3109 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_usbdev.h @@ -30,7 +30,7 @@ #include #include -#if defined(CONFIG_STM32L4_STM32L4X2) +#if defined(CONFIG_STM32_STM32L4X2) /**************************************************************************** * Pre-processor Definitions @@ -251,5 +251,5 @@ #define USB_BCDR_PS2DET (1 << 7) /* Bit 7: DM pull-up detection status */ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ -#endif /* CONFIG_STM32L4_STM32L4X2 */ +#endif /* CONFIG_STM32_STM32L4X2 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_USBDEV_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h index f7951f4ed79..38db3afd938 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -791,5 +791,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h index 94a366dbf51..17502c2562f 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x3xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /**************************************************************************** * Pre-processor Definitions @@ -169,5 +169,5 @@ #define SYSCFG_SKR_SHIFT 0 #define SYSCFG_SKR_MASK (0xFF << SYSCFG_SKR_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X3 */ +#endif /* CONFIG_STM32_STM32L4X3 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X3XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h index c3c76f22cb6..5d81e280f12 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -721,5 +721,5 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: Window watchdog reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-Power reset flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h index 20d9addcad0..40983ec4297 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x5xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) /**************************************************************************** * Pre-processor Definitions @@ -163,5 +163,5 @@ #define SYSCFG_CFGR2_ECCL (1 << 3) /* Bit 3: ECC lock enable (same) */ #define SYSCFG_CFGR2_SPF (1 << 8) /* Bit 8: SRAM2 parity error flag */ -#endif /* CONFIG_STM32L4_STM32L4X5 */ +#endif /* CONFIG_STM32_STM32L4X5 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X5XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h index 34509ed7668..f8dc5a36325 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_dbgmcu.h @@ -81,14 +81,14 @@ #define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ #define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ #endif #define DBGMCU_APB1_LPTIM1STOP (1 << 31) /* Bit 31: LPTIM1 stopper when core is halted */ /* Debug MCU APB1 freeze register 2 */ -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define DBGMCU_APB1_FZ2_I2C4STOP (1 << 1) /* Bit 1: I2C4 SMBUS timeout mode stopped when Core is halted */ #endif #define DBGMCU_APB1_FZ2_LPTIM2STOP (1 << 5) /* Bit 5: LPTIM2 stopper when core is halted */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h index 19df3fe795c..6428f606e4b 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_firewall.h @@ -81,7 +81,7 @@ /* Volatile Data Segment Start Address */ #define FIREWALL_VDSADD_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSADD_MASK (0x0fff << FIREWALL_VDSADD_SHIFT) #else # define FIREWALL_VDSADD_MASK (0x07ff << FIREWALL_VDSADD_SHIFT) @@ -90,7 +90,7 @@ /* Volatile Data Segment Length */ #define FIREWALL_VDSLENG_SHIFT 6 -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define FIREWALL_VDSLENG_MASK (0x0fff << FIREWALL_VDSLENG_SHIFT) #else # define FIREWALL_VDSLENG_MASK (0x07ff << FIREWALL_VDSLENG_SHIFT) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h index 73d2f0b9785..29a19f63a14 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -712,7 +712,7 @@ #define RCC_CCIPR_CLK48SEL_SHIFT (26) #define RCC_CCIPR_CLK48SEL_MASK (3 << RCC_CCIPR_CLK48SEL_SHIFT) -#if defined(CONFIG_STM32L4_STM32L496XX) +#if defined(CONFIG_STM32_STM32L496XX) # define RCC_CCIPR_CLK48SEL_HSI48 (0 << RCC_CCIPR_CLK48SEL_SHIFT) #else # define RCC_CCIPR_CLK48SEL_NONE (0 << RCC_CCIPR_CLK48SEL_SHIFT) @@ -807,5 +807,5 @@ # define RCC_CCIPR2_I2C4SEL_SYSCLK (1 << RCC_CCIPR2_I2C4SEL_SHIFT) # define RCC_CCIPR2_I2C4SEL_HSI (2 << RCC_CCIPR2_I2C4SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h index 9819f2a7eb1..bc0ff376cfb 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4x6xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Pre-processor Definitions @@ -179,5 +179,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4X6 */ +#endif /* CONFIG_STM32_STM32L4X6 */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4X6XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h index ecc515f1141..467ee101d5a 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -860,5 +860,5 @@ # define RCC_CCIPR2_SAI2SEL_SAI2_EXT (3 << RCC_CCIPR2_SAI2SEL_SHIFT) # define RCC_CCIPR2_SAI2SEL_HSI (4 << RCC_CCIPR2_SAI2SEL_SHIFT) -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_RCC_H */ diff --git a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h index 4d3b2cad341..b24b23bc0fc 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4xrxx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Pre-processor Definitions @@ -181,5 +181,5 @@ /* There is one bit per SRAM2 page (32 to 63) */ -#endif /* CONFIG_STM32L4_STM32L4XR */ +#endif /* CONFIG_STM32_STM32L4XR */ #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4XRXX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_1wire.c b/arch/arm/src/stm32l4/stm32l4_1wire.c index c316fb57fb4..d22c0e8d5a9 100644 --- a/arch/arm/src/stm32l4/stm32l4_1wire.c +++ b/arch/arm/src/stm32l4/stm32l4_1wire.c @@ -172,7 +172,7 @@ static int stm32_1wire_pm_prepare(struct pm_callback_s *cb, int domain, /* 1-Wire device structures */ -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire1_config = { @@ -196,7 +196,7 @@ static struct stm32_1wire_priv_s stm32_1wire1_priv = #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire2_config = { @@ -220,7 +220,7 @@ static struct stm32_1wire_priv_s stm32_1wire2_priv = #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire3_config = { @@ -244,7 +244,7 @@ static struct stm32_1wire_priv_s stm32_1wire3_priv = #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire4_config = { @@ -268,7 +268,7 @@ static struct stm32_1wire_priv_s stm32_1wire4_priv = #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER static const struct stm32_1wire_config_s stm32_1wire5_config = { @@ -463,35 +463,35 @@ static void stm32_1wire_set_apb_clock(struct stm32_1wire_priv_s *priv, default: return; -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1150,31 +1150,31 @@ struct onewire_dev_s *stm32_1wireinitialize(int port) switch (port) { -#ifdef CONFIG_STM32L4_USART1_1WIREDRIVER +#ifdef CONFIG_STM32_USART1_1WIREDRIVER case 1: priv = &stm32_1wire1_priv; break; #endif -#ifdef CONFIG_STM32L4_USART2_1WIREDRIVER +#ifdef CONFIG_STM32_USART2_1WIREDRIVER case 2: priv = &stm32_1wire2_priv; break; #endif -#ifdef CONFIG_STM32L4_USART3_1WIREDRIVER +#ifdef CONFIG_STM32_USART3_1WIREDRIVER case 3: priv = &stm32_1wire3_priv; break; #endif -#ifdef CONFIG_STM32L4_UART4_1WIREDRIVER +#ifdef CONFIG_STM32_UART4_1WIREDRIVER case 4: priv = &stm32_1wire4_priv; break; #endif -#ifdef CONFIG_STM32L4_UART5_1WIREDRIVER +#ifdef CONFIG_STM32_UART5_1WIREDRIVER case 5: priv = &stm32_1wire5_priv; break; diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index 347b5837903..c1e4c5730a2 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -56,16 +56,16 @@ /* Some ADC peripheral must be enabled */ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) -# if defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) +# if defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) # error "Using non-existent ADC" # endif #endif @@ -88,16 +88,16 @@ /* ADC interrupts ***********************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4XR) # define STM32_IRQ_ADC12 STM32_IRQ_ADC1 #endif /* ADC Channels/DMA *********************************************************/ #ifdef ADC_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMA2) +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMA2) # /* REVISIT: check accordingly to which one is configured in board.h */ -# error "STM32L4 ADC DMA support requires CONFIG_STM32L4_DMA1 or CONFIG_STM32L4_DMA2" +# error "STM32L4 ADC DMA support requires CONFIG_STM32_DMA1 or CONFIG_STM32_DMA2" # endif #endif @@ -110,10 +110,10 @@ /* Sample time default configuration */ -#ifndef CONFIG_STM32L4_ADC_SMPR +#ifndef CONFIG_STM32_ADC_SMPR # define ADC_SMPR_DEFAULT ADC_SMPR_640p5 #else -# define ADC_SMPR_DEFAULT CONFIG_STM32L4_ADC_SMPR +# define ADC_SMPR_DEFAULT CONFIG_STM32_ADC_SMPR #endif #define ADC_SMPR1_DEFAULT ((ADC_SMPR_DEFAULT << ADC_SMPR1_SMP0_SHIFT) | \ @@ -161,10 +161,10 @@ struct stm32_dev_s { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS const struct stm32_adc_ops_s *llops; /* Low-level ADC ops */ #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ const struct adc_callback_s *cb; uint8_t irq; /* Interrupt generated by this ADC block */ #endif @@ -219,7 +219,7 @@ struct stm32_dev_s /* List of selected ADC channels to sample */ - uint8_t r_chanlist[CONFIG_STM32L4_ADC_MAX_SAMPLES]; + uint8_t r_chanlist[CONFIG_STM32_ADC_MAX_SAMPLES]; #ifdef ADC_HAVE_INJECTED /* List of selected ADC injected channels to sample */ @@ -280,12 +280,12 @@ static int adc_timinit(struct stm32_dev_s *priv); #ifdef ADC_HAVE_DMA static void adc_dma_cfg(struct stm32_dev_s *priv); static void adc_dma_start(struct adc_dev_s *dev); -# ifndef CONFIG_STM32L4_ADC_NOIRQ +# ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg); # endif #endif -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset); #endif @@ -303,7 +303,7 @@ static int adc_pm_prepare(struct pm_callback_s *cb, int domain, enum pm_state_e state); #endif -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static void adc_llops_intack(struct stm32_adc_dev_s *dev, uint32_t source); static void adc_llops_inten(struct stm32_adc_dev_s *dev, @@ -339,19 +339,19 @@ static uint32_t adc_llops_injget(struct stm32_adc_dev_s *dev, static void adc_llops_inj_startconv(struct stm32_adc_dev_s *dev, bool enable); # endif -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC Interrupt Handler */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(struct adc_dev_s *dev, uint32_t regval); -# if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +# if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg); # endif -# if defined(CONFIG_STM32L4_ADC3) +# if defined(CONFIG_STM32_ADC3) static int adc3_interrupt(int irq, void *context, void *arg); # endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ /* ADC Driver Methods */ @@ -381,7 +381,7 @@ static const struct adc_ops_s g_adcops = /* Publicly visible ADC lower-half operations */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS static const struct stm32_adc_ops_s g_adc_llops = { .int_ack = adc_llops_intack, @@ -408,29 +408,29 @@ static const struct stm32_adc_ops_s g_adc_llops = # endif .dump_regs = adc_llops_dumpregs }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /* ADC1 state */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 #ifdef ADC1_HAVE_DMA -static uint16_t g_adc1_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC1_DMA_BATCH]; +static uint16_t g_adc1_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC1_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 1, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC1_RESOLUTION, + .resolution = CONFIG_STM32_ADC1_RESOLUTION, #endif .base = STM32_ADC1_BASE, #if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_EXTCFG) @@ -443,14 +443,14 @@ static struct stm32_dev_s g_adcpriv1 = .channel = ADC1_TIMER_CHANNEL, .tbase = ADC1_TIMER_BASE, .pclck = ADC1_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC1_SAMPLE_FREQUENCY, #endif #ifdef ADC1_HAVE_DMA .dmachan = ADC1_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC1_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC1_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc1_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC1_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC1_DMA_BATCH #endif #ifdef ADC1_HAVE_DFSDM .hasdfsdm = true, @@ -472,25 +472,25 @@ static struct adc_dev_s g_adcdev1 = /* ADC2 state */ -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 #ifdef ADC2_HAVE_DMA -static uint16_t g_adc2_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC2_DMA_BATCH]; +static uint16_t g_adc2_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC2_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 2, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC2_RESOLUTION, + .resolution = CONFIG_STM32_ADC2_RESOLUTION, #endif .base = STM32_ADC2_BASE, #if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_EXTCFG) @@ -503,14 +503,14 @@ static struct stm32_dev_s g_adcpriv2 = .channel = ADC2_TIMER_CHANNEL, .tbase = ADC2_TIMER_BASE, .pclck = ADC2_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC2_SAMPLE_FREQUENCY, #endif #ifdef ADC2_HAVE_DMA .dmachan = ADC2_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC2_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC2_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc2_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC2_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC2_DMA_BATCH #endif #ifdef ADC2_HAVE_DFSDM .hasdfsdm = true, @@ -532,25 +532,25 @@ static struct adc_dev_s g_adcdev2 = /* ADC3 state */ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 #ifdef ADC3_HAVE_DMA -static uint16_t g_adc3_dmabuffer[CONFIG_STM32L4_ADC_MAX_SAMPLES * - CONFIG_STM32L4_ADC3_DMA_BATCH]; +static uint16_t g_adc3_dmabuffer[CONFIG_STM32_ADC_MAX_SAMPLES * + CONFIG_STM32_ADC3_DMA_BATCH]; #endif static struct stm32_dev_s g_adcpriv3 = { -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS .llops = &g_adc_llops, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC3, .isr = adc3_interrupt, -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ .intf = 3, #ifdef HAVE_ADC_RESOLUTION - .resolution = CONFIG_STM32L4_ADC3_RESOLUTION, + .resolution = CONFIG_STM32_ADC3_RESOLUTION, #endif .base = STM32_ADC3_BASE, #if defined(ADC3_HAVE_TIMER) || defined(ADC3_HAVE_EXTCFG) @@ -563,14 +563,14 @@ static struct stm32_dev_s g_adcpriv3 = .channel = ADC3_TIMER_CHANNEL, .tbase = ADC3_TIMER_BASE, .pclck = ADC3_TIMER_PCLK_FREQUENCY, - .freq = CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY, + .freq = CONFIG_STM32_ADC3_SAMPLE_FREQUENCY, #endif #ifdef ADC3_HAVE_DMA .dmachan = ADC3_DMA_CHAN, - .dmacfg = CONFIG_STM32L4_ADC3_DMA_CFG, + .dmacfg = CONFIG_STM32_ADC3_DMA_CFG, .hasdma = true, .r_dmabuffer = g_adc3_dmabuffer, - .dmabatch = CONFIG_STM32L4_ADC3_DMA_BATCH + .dmabatch = CONFIG_STM32_ADC3_DMA_BATCH #endif #ifdef ADC3_HAVE_DFSDM .hasdfsdm = true, @@ -1298,7 +1298,7 @@ static void adc_enable(struct stm32_dev_s *priv) static int adc_bind(struct adc_dev_s *dev, const struct adc_callback_s *callback) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; DEBUGASSERT(priv != NULL); @@ -1353,8 +1353,8 @@ static void adc_reset(struct adc_dev_s *dev) static int adc_setup(struct adc_dev_s *dev) { -#if !defined(CONFIG_STM32L4_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ - !defined(CONFIG_STM32L4_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) +#if !defined(CONFIG_STM32_ADC_NOIRQ) || defined(ADC_HAVE_TIMER) || \ + !defined(CONFIG_STM32_ADC_NO_STARTUP_CONV) || defined(HAVE_ADC_RESOLUTION) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; #endif int ret = OK; @@ -1364,7 +1364,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Attach the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1479,7 +1479,7 @@ static int adc_setup(struct adc_dev_s *dev) * or later with ANIOC_TRIGGER ioctl call. */ -#ifndef CONFIG_STM32L4_ADC_NO_STARTUP_CONV +#ifndef CONFIG_STM32_ADC_NO_STARTUP_CONV /* Start regular conversion */ if (priv->cchannels > 0) @@ -1496,7 +1496,7 @@ static int adc_setup(struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1536,7 +1536,7 @@ static int adc_setup(struct adc_dev_s *dev) static void adc_shutdown(struct adc_dev_s *dev) { -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Disable ADC interrupts and detach the ADC interrupt handler */ struct stm32_dev_s *priv = (struct stm32_dev_s *)dev->ad_priv; @@ -1801,12 +1801,12 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) break; case 17: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC1_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC1_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_TSEN; #endif break; case 18: -#if !(defined(CONFIG_STM32L4_STM32L4X3) && defined(CONFIG_STM32L4_DAC2_OUTPUT_ADC)) +#if !(defined(CONFIG_STM32_STM32L4X3) && defined(CONFIG_STM32_DAC2_OUTPUT_ADC)) *adc_ccr |= ADC_CCR_VBATEN; #endif break; @@ -1824,7 +1824,7 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) * Name: adc_offset_set ****************************************************************************/ -#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32L4_ADC_LL_OPS) +#if defined(ADC_HAVE_DFSDM) || defined(CONFIG_STM32_ADC_LL_OPS) static int adc_offset_set(struct stm32_dev_s *priv, uint8_t ch, uint8_t i, uint16_t offset) @@ -1893,7 +1893,7 @@ static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch) priv->rnchannels = 1; } - DEBUGASSERT(priv->rnchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); + DEBUGASSERT(priv->rnchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); bits = adc_sqrbits(priv, ADC_SQR4_FIRST, ADC_SQR4_LAST, ADC_SQR4_SQ_OFFSET); @@ -2107,7 +2107,7 @@ static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) return ret; } -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /**************************************************************************** * Name: adc_interrupt @@ -2225,13 +2225,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) static int adc12_interrupt(int irq, void *context, void *arg) { uint32_t regval; uint32_t pending; -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 regval = getreg32(STM32_ADC1_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2244,7 +2244,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 regval = getreg32(STM32_ADC2_ISR); pending = regval & ADC_INT_MASK; if (pending != 0) @@ -2273,7 +2273,7 @@ static int adc12_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static int adc3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -2293,7 +2293,7 @@ static int adc3_interrupt(int irq, void *context, void *arg) return OK; } #endif -#endif /* CONFIG_STM32L4_ADC_NOIRQ */ +#endif /* CONFIG_STM32_ADC_NOIRQ */ #ifdef ADC_HAVE_DMA /**************************************************************************** @@ -2360,7 +2360,7 @@ static void adc_dma_start(struct adc_dev_s *dev) priv->dma = stm32_dmachannel(priv->dmachan); -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ stm32_dmasetup(priv->dma, priv->base + STM32_ADC_DR_OFFSET, (uint32_t)priv->r_dmabuffer, @@ -2388,7 +2388,7 @@ static void adc_dma_start(struct adc_dev_s *dev) * ****************************************************************************/ -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static void adc_dmaconvcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { @@ -2424,7 +2424,7 @@ static void adc_dmaconvcallback(DMA_HANDLE handle, #endif #endif /* ADC_HAVE_DMA */ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /**************************************************************************** * Name: adc_llops_intack @@ -2671,7 +2671,7 @@ static void adc_llops_dumpregs(struct stm32_adc_dev_s *dev) adc_dumpregs(priv); } -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Functions @@ -2738,11 +2738,11 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, switch (intf) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 case 1: { ainfo("ADC1 selected\n"); - cjchannels = CONFIG_STM32L4_ADC1_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC1_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2757,11 +2757,11 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, break; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 case 2: { ainfo("ADC2 selected\n"); - cjchannels = CONFIG_STM32L4_ADC2_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC2_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2776,11 +2776,11 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, break; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 case 3: { ainfo("ADC3 selected\n"); - cjchannels = CONFIG_STM32L4_ADC3_INJ_CHAN; + cjchannels = CONFIG_STM32_ADC3_INJ_CHAN; crchannels = cchannels - cjchannels; ainfo(" Reg. chan: %d Inj chan: %d\n", crchannels, cjchannels); # ifdef ADC_HAVE_INJECTED @@ -2804,10 +2804,10 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, priv = (struct stm32_dev_s *)dev->ad_priv; - DEBUGASSERT(crchannels <= CONFIG_STM32L4_ADC_MAX_SAMPLES); - if (crchannels > CONFIG_STM32L4_ADC_MAX_SAMPLES) + DEBUGASSERT(crchannels <= CONFIG_STM32_ADC_MAX_SAMPLES); + if (crchannels > CONFIG_STM32_ADC_MAX_SAMPLES) { - crchannels = CONFIG_STM32L4_ADC_MAX_SAMPLES; + crchannels = CONFIG_STM32_ADC_MAX_SAMPLES; } priv->cchannels = crchannels; @@ -2823,7 +2823,7 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, #endif -#ifndef CONFIG_STM32L4_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ priv->cb = NULL; #endif @@ -2838,5 +2838,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_adc.h b/arch/arm/src/stm32l4/stm32l4_adc.h index ee261533e98..d2e335bb3e7 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.h +++ b/arch/arm/src/stm32l4/stm32l4_adc.h @@ -46,94 +46,94 @@ * STM32L4X3, while STM32L4X6 adds support for timers 4 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_ADC -# undef CONFIG_STM32L4_TIM1_ADC1 -# undef CONFIG_STM32L4_TIM1_ADC2 -# undef CONFIG_STM32L4_TIM1_ADC3 +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_ADC +# undef CONFIG_STM32_TIM1_ADC1 +# undef CONFIG_STM32_TIM1_ADC2 +# undef CONFIG_STM32_TIM1_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_ADC -# undef CONFIG_STM32L4_TIM2_ADC1 -# undef CONFIG_STM32L4_TIM2_ADC2 -# undef CONFIG_STM32L4_TIM2_ADC3 +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_ADC +# undef CONFIG_STM32_TIM2_ADC1 +# undef CONFIG_STM32_TIM2_ADC2 +# undef CONFIG_STM32_TIM2_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_ADC -# undef CONFIG_STM32L4_TIM3_ADC1 -# undef CONFIG_STM32L4_TIM3_ADC2 -# undef CONFIG_STM32L4_TIM3_ADC3 +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_ADC +# undef CONFIG_STM32_TIM3_ADC1 +# undef CONFIG_STM32_TIM3_ADC2 +# undef CONFIG_STM32_TIM3_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_ADC -# undef CONFIG_STM32L4_TIM4_ADC1 -# undef CONFIG_STM32L4_TIM4_ADC2 -# undef CONFIG_STM32L4_TIM4_ADC3 +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_ADC +# undef CONFIG_STM32_TIM4_ADC1 +# undef CONFIG_STM32_TIM4_ADC2 +# undef CONFIG_STM32_TIM4_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_ADC -# undef CONFIG_STM32L4_TIM6_ADC1 -# undef CONFIG_STM32L4_TIM6_ADC2 -# undef CONFIG_STM32L4_TIM6_ADC3 +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_ADC +# undef CONFIG_STM32_TIM6_ADC1 +# undef CONFIG_STM32_TIM6_ADC2 +# undef CONFIG_STM32_TIM6_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_ADC -# undef CONFIG_STM32L4_TIM8_ADC1 -# undef CONFIG_STM32L4_TIM8_ADC2 -# undef CONFIG_STM32L4_TIM8_ADC3 +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_ADC +# undef CONFIG_STM32_TIM8_ADC1 +# undef CONFIG_STM32_TIM8_ADC2 +# undef CONFIG_STM32_TIM8_ADC3 #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_ADC -# undef CONFIG_STM32L4_TIM15_ADC1 -# undef CONFIG_STM32L4_TIM15_ADC2 -# undef CONFIG_STM32L4_TIM15_ADC3 +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_ADC +# undef CONFIG_STM32_TIM15_ADC1 +# undef CONFIG_STM32_TIM15_ADC2 +# undef CONFIG_STM32_TIM15_ADC3 #endif /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || \ - defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || \ + defined(CONFIG_STM32_ADC3) /* ADC output to DFSDM support. Note that DFSDM and DMA are * mutually exclusive. */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) # define ADC1_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC1_DMA +# undef CONFIG_STM32_ADC1_DMA #else # undef ADC1_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) # define ADC2_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC2_DMA +# undef CONFIG_STM32_ADC2_DMA #else # undef ADC2_HAVE_DFSDM #endif -#if defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC3_HAVE_DFSDM 1 -# undef CONFIG_STM32L4_ADC3_DMA +# undef CONFIG_STM32_ADC3_DMA #else # undef ADC3_HAVE_DFSDM #endif @@ -141,24 +141,24 @@ /* DMA support */ #undef ADC_HAVE_DMA -#if defined(CONFIG_STM32L4_ADC1_DMA) || defined(CONFIG_STM32L4_ADC2_DMA) || \ - defined(CONFIG_STM32L4_ADC3_DMA) +#if defined(CONFIG_STM32_ADC1_DMA) || defined(CONFIG_STM32_ADC2_DMA) || \ + defined(CONFIG_STM32_ADC3_DMA) # define ADC_HAVE_DMA 1 #endif -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_HAVE_DMA 1 #else # undef ADC1_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC2_DMA +#ifdef CONFIG_STM32_ADC2_DMA # define ADC2_HAVE_DMA 1 #else # undef ADC2_HAVE_DMA #endif -#ifdef CONFIG_STM32L4_ADC3_DMA +#ifdef CONFIG_STM32_ADC3_DMA # define ADC3_HAVE_DMA 1 #else # undef ADC3_HAVE_DMA @@ -166,9 +166,9 @@ /* Injected channels support */ -#if (defined(CONFIG_STM32L4_ADC1) && (CONFIG_STM32L4_ADC1_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC2) && (CONFIG_STM32L4_ADC2_INJ_CHAN > 0)) || \ - (defined(CONFIG_STM32L4_ADC3) && (CONFIG_STM32L4_ADC3_INJ_CHAN > 0)) +#if (defined(CONFIG_STM32_ADC1) && (CONFIG_STM32_ADC1_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC2) && (CONFIG_STM32_ADC2_INJ_CHAN > 0)) || \ + (defined(CONFIG_STM32_ADC3) && (CONFIG_STM32_ADC3_INJ_CHAN > 0)) # define ADC_HAVE_INJECTED #endif @@ -176,149 +176,149 @@ * information about the timer. */ -#if defined(CONFIG_STM32L4_TIM1_ADC1) +#if defined(CONFIG_STM32_TIM1_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM1_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM2_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM3_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM4_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM6_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM8_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC1) +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC1) # define ADC1_HAVE_TIMER 1 # define ADC1_TIMER_BASE STM32_TIM15_BASE # define ADC1_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -# define ADC1_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC1_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC1_HAVE_TIMER #endif #ifdef ADC1_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC1_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC1_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC1_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC1_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC1_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC1_JEXTTRIG == 0)) # error "ADC1 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC2) +#if defined(CONFIG_STM32_TIM1_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM1_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM2_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM2_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM2_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM3_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM4_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM6_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM8_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC2) +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC2) # define ADC2_HAVE_TIMER 1 # define ADC2_TIMER_BASE STM32_TIM15_BASE # define ADC2_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -# define ADC2_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC2_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC2_HAVE_TIMER #endif #ifdef ADC2_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC2_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC2_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC2_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC2_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC2_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC2_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC2_JEXTTRIG == 0)) # error "ADC2 External trigger must be enabled" # endif #endif -#if defined(CONFIG_STM32L4_TIM1_ADC3) +#if defined(CONFIG_STM32_TIM1_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM1_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM1_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM2_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM2_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM2_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM2_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM1_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM3_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM1_ADC_CHAN +#elif defined(CONFIG_STM32_TIM3_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM3_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM3_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM3_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM4_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM3_ADC_CHAN +#elif defined(CONFIG_STM32_TIM4_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM4_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM4_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM4_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM6_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM4_ADC_CHAN +#elif defined(CONFIG_STM32_TIM6_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM6_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB1_TIM6_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM6_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM8_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM6_ADC_CHAN +#elif defined(CONFIG_STM32_TIM8_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM8_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM8_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM8_ADC_CHAN -#elif defined(CONFIG_STM32L4_TIM15_ADC3) +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM8_ADC_CHAN +#elif defined(CONFIG_STM32_TIM15_ADC3) # define ADC3_HAVE_TIMER 1 # define ADC3_TIMER_BASE STM32_TIM15_BASE # define ADC3_TIMER_PCLK_FREQUENCY STM32_APB2_TIM15_CLKIN -# define ADC3_TIMER_CHANNEL CONFIG_STM32L4_TIM15_ADC_CHAN +# define ADC3_TIMER_CHANNEL CONFIG_STM32_TIM15_ADC_CHAN #else # undef ADC3_HAVE_TIMER #endif #ifdef ADC3_HAVE_TIMER -# ifndef CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY -# error "CONFIG_STM32L4_ADC3_SAMPLE_FREQUENCY not defined" +# ifndef CONFIG_STM32_ADC3_SAMPLE_FREQUENCY +# error "CONFIG_STM32_ADC3_SAMPLE_FREQUENCY not defined" # endif -# if ((CONFIG_STM32L4_ADC3_EXTTRIG == 0) && \ - (CONFIG_STM32L4_ADC3_JEXTTRIG == 0)) +# if ((CONFIG_STM32_ADC3_EXTTRIG == 0) && \ + (CONFIG_STM32_ADC3_JEXTTRIG == 0)) # error "ADC3 External trigger must be enabled" # endif #endif @@ -332,18 +332,18 @@ /* EXTSEL configuration *****************************************************/ -/* If external trigger is enabled, (CONFIG_STM32L4_ADC1_EXTTRIG > 0), +/* If external trigger is enabled, (CONFIG_STM32_ADC1_EXTTRIG > 0), * ADCx_EXTSEL_VALUE is set based on trigger polarity and event number. No * effort is made to check if the configuration is valid. */ -#ifdef CONFIG_STM32L4_ADC1_EXTTRIG -# if CONFIG_STM32L4_ADC1_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_EXTTRIG +# if CONFIG_STM32_ADC1_EXTTRIG > 0 # define ADC1_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC1_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC1_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC1_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC1_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_EXTTRIG */ +#endif /* CONFIG_STM32_ADC1_EXTTRIG */ #ifdef ADC1_EXTCFG_VALUE # define ADC1_HAVE_EXTCFG 1 @@ -351,13 +351,13 @@ # undef ADC1_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC2_EXTTRIG -# if CONFIG_STM32L4_ADC2_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_EXTTRIG +# if CONFIG_STM32_ADC2_EXTTRIG > 0 # define ADC2_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC2_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC2_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC2_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC2_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_EXTTRIG */ +#endif /* CONFIG_STM32_ADC2_EXTTRIG */ #ifdef ADC2_EXTCFG_VALUE # define ADC2_HAVE_EXTCFG 1 @@ -365,13 +365,13 @@ # undef ADC2_HAVE_EXTCFG #endif -#ifdef CONFIG_STM32L4_ADC3_EXTTRIG -# if CONFIG_STM32L4_ADC3_EXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_EXTTRIG +# if CONFIG_STM32_ADC3_EXTTRIG > 0 # define ADC3_EXTCFG_VALUE \ - ADC_CFGR_EXTEN(CONFIG_STM32L4_ADC3_EXTTRIG) | \ - ADC_CFGR_EXTSEL(CONFIG_STM32L4_ADC3_EXTSEL) + ADC_CFGR_EXTEN(CONFIG_STM32_ADC3_EXTTRIG) | \ + ADC_CFGR_EXTSEL(CONFIG_STM32_ADC_L4_ADC3_EXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_EXTTRIG */ +#endif /* CONFIG_STM32_ADC3_EXTTRIG */ #ifdef ADC3_EXTCFG_VALUE # define ADC3_HAVE_EXTCFG 1 @@ -386,37 +386,37 @@ /* JEXTSEL configuration ****************************************************/ -#ifdef CONFIG_STM32L4_ADC1_JEXTTRIG -# if CONFIG_STM32L4_ADC1_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC1_JEXTTRIG +# if CONFIG_STM32_ADC1_JEXTTRIG > 0 # define ADC1_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC1_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC1_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC1_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC1_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC1_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC1_JEXTTRIG */ #ifdef ADC1_JEXTCFG_VALUE # define ADC1_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC2_JEXTTRIG -# if CONFIG_STM32L4_ADC2_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC2_JEXTTRIG +# if CONFIG_STM32_ADC2_JEXTTRIG > 0 # define ADC2_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC2_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC2_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC2_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC2_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC2_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC2_JEXTTRIG */ #ifdef ADC2_JEXTCFG_VALUE # define ADC2_HAVE_JEXTCFG 1 #endif -#ifdef CONFIG_STM32L4_ADC3_JEXTTRIG -# if CONFIG_STM32L4_ADC3_JEXTTRIG > 0 +#ifdef CONFIG_STM32_ADC3_JEXTTRIG +# if CONFIG_STM32_ADC3_JEXTTRIG > 0 # define ADC3_JEXTCFG_VALUE \ - ADC_JSQR_JEXTEN(CONFIG_STM32L4_ADC3_JEXTTRIG) | \ - ADC_JSQR_JEXTSEL(CONFIG_STM32L4_ADC3_JEXTSEL) + ADC_JSQR_JEXTEN(CONFIG_STM32_ADC3_JEXTTRIG) | \ + ADC_JSQR_JEXTSEL(CONFIG_STM32_ADC_L4_ADC3_JEXTSEL) # endif -#endif /* CONFIG_STM32L4_ADC3_JEXTTRIG */ +#endif /* CONFIG_STM32_ADC3_JEXTTRIG */ #ifdef ADC3_JEXTCFG_VALUE # define ADC3_HAVE_JEXTCFG 1 @@ -495,7 +495,7 @@ * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_ADC_LL_OPS +#ifdef CONFIG_STM32_ADC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" ADC driver structure. @@ -584,7 +584,7 @@ struct stm32_adc_ops_s void (*dump_regs)(struct stm32_adc_dev_s *dev); }; -#endif /* CONFIG_STM32L4_ADC_LL_OPS */ +#endif /* CONFIG_STM32_ADC_LL_OPS */ /**************************************************************************** * Public Function Prototypes @@ -624,5 +624,5 @@ struct adc_dev_s *stm32_adc_initialize(int intf, const uint8_t *chanlist, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ADC_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index 8dce482c8ec..2a459135259 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -60,7 +60,7 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L4_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC=y : Enables the FSMC * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC @@ -71,7 +71,7 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L4_FSMC +#ifndef CONFIG_STM32_FSMC # undef CONFIG_STM32L4_FSMC_SRAM #endif @@ -116,14 +116,14 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L4_SRAM2_HEAP) + \ - defined(CONFIG_STM32L4_SRAM3_HEAP) + \ +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -313,7 +313,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L4_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -332,7 +332,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L4_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 1dd36db8d07..9d6231f4f1f 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -44,7 +44,7 @@ #include "stm32.h" #include "stm32l4_can.h" -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /**************************************************************************** * Pre-processor Definitions @@ -62,10 +62,10 @@ /* Bit timing ***************************************************************/ -#define CAN_BIT_QUANTA (CONFIG_STM32L4_CAN_TSEG1 + CONFIG_STM32L4_CAN_TSEG2 + 1) +#define CAN_BIT_QUANTA (CONFIG_STM32_CAN_TSEG1 + CONFIG_STM32_CAN_TSEG2 + 1) #ifndef CONFIG_DEBUG_CAN_INFO -# undef CONFIG_STM32L4_CAN_REGDEBUG +# undef CONFIG_STM32_CAN_REGDEBUG #endif /**************************************************************************** @@ -97,7 +97,7 @@ static void stm32l4can_putreg(struct stm32_can_s *priv, int offset, uint32_t value); static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, uint32_t value); -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg); static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, @@ -175,7 +175,7 @@ static const struct can_ops_s g_canops = .co_txempty = stm32l4can_txempty, }; -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 static struct stm32_can_s g_can1priv = { .port = 1, @@ -188,7 +188,7 @@ static struct stm32_can_s g_can1priv = .filter = 0, .base = STM32_CAN1_BASE, .fbase = STM32_CAN1_BASE, - .baud = CONFIG_STM32L4_CAN1_BAUD, + .baud = CONFIG_STM32_CAN1_BAUD, }; static struct can_dev_s g_can1dev = @@ -217,7 +217,7 @@ static struct can_dev_s g_can1dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static uint32_t stm32l4can_vgetreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -313,7 +313,7 @@ static uint32_t stm32l4can_getfreg(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_vputreg(uint32_t addr, uint32_t value) { /* Show the register value being written */ @@ -365,7 +365,7 @@ static void stm32l4can_putfreg(struct stm32_can_s *priv, int offset, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, const char *msg) { @@ -410,7 +410,7 @@ static void stm32l4can_dumpctrlregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, const char *msg) { @@ -476,7 +476,7 @@ static void stm32l4can_dumpmbregs(struct stm32_can_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_CAN_REGDEBUG +#ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32l4can_dumpfiltregs(struct stm32_can_s *priv, const char *msg) { @@ -535,7 +535,7 @@ static void stm32l4can_reset(struct can_dev_s *dev) /* Get the bits in the AHB1RSTR1 register needed to reset this CAN device */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (priv->port == 1) { regbit = RCC_APB1RSTR1_CAN1RST; @@ -1729,15 +1729,15 @@ static int stm32l4can_bittiming(struct stm32_can_s *priv) } } - /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32L4_CAN_TSEG1, - * ts2 is CONFIG_STM32L4_CAN_TSEG2 and we calculate brp to achieve + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_STM32_CAN_TSEG1, + * ts2 is CONFIG_STM32_CAN_TSEG2 and we calculate brp to achieve * CAN_BIT_QUANTA quanta in the bit time */ else { - ts1 = CONFIG_STM32L4_CAN_TSEG1; - ts2 = CONFIG_STM32L4_CAN_TSEG2; + ts1 = CONFIG_STM32_CAN_TSEG1; + ts2 = CONFIG_STM32_CAN_TSEG2; brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } @@ -2148,7 +2148,7 @@ struct can_dev_s *stm32_caninitialize(int port) * by stm32_clockconfig() early in the reset sequence. */ -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 if (port == 1) { /* Select the CAN1 device structure */ @@ -2172,4 +2172,4 @@ struct can_dev_s *stm32_caninitialize(int port) return dev; } -#endif /* CONFIG_CAN && (CONFIG_STM32L4_CAN1 || CONFIG_STM32L4_CAN2) */ +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 11174fd1a24..1a4d5e97315 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -43,38 +43,38 @@ /* Up to 1 CAN interfaces are supported */ #if STM32_NCAN < 1 -# undef CONFIG_STM32L4_CAN1 +# undef CONFIG_STM32_CAN1 #endif -#if defined(CONFIG_CAN) && defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_CAN) && defined(CONFIG_STM32_CAN1) /* CAN BAUD */ -#if defined(CONFIG_STM32L4_CAN1) && !defined(CONFIG_STM32L4_CAN1_BAUD) -# error "CONFIG_STM32L4_CAN1_BAUD is not defined" +#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" #endif /* User-defined TSEG1 and TSEG2 settings may be used. * - * CONFIG_STM32L4_CAN_TSEG1 = the number of CAN time quanta in segment 1 - * CONFIG_STM32L4_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CONFIG_STM32_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_STM32_CAN_TSEG2 = the number of CAN time quanta in segment 2 * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32L4_CAN_TSEG1 -# define CONFIG_STM32L4_CAN_TSEG1 6 +#ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 #endif -#if CONFIG_STM32L4_CAN_TSEG1 < 1 || CONFIG_STM32L4_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32L4_CAN_TSEG1 is out of range" +#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" #endif -#ifndef CONFIG_STM32L4_CAN_TSEG2 -# define CONFIG_STM32L4_CAN_TSEG2 7 +#ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 #endif -#if CONFIG_STM32L4_CAN_TSEG2 < 1 || CONFIG_STM32L4_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32L4_CAN_TSEG2 is out of range" +#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" #endif /**************************************************************************** @@ -123,5 +123,5 @@ struct can_dev_s *stm32_caninitialize(int port); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_CAN && CONFIG_STM32L4_CAN1 */ +#endif /* CONFIG_CAN && CONFIG_STM32_CAN1 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_CAN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.c b/arch/arm/src/stm32l4/stm32l4_comp.c index 6271db60ac6..4b57a5f900a 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_comp.c @@ -53,12 +53,12 @@ #include -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#ifdef CONFIG_STM32L4_COMP +#ifdef CONFIG_STM32_COMP /**************************************************************************** * Private Function Prototypes @@ -373,7 +373,7 @@ static int stm32_compconfig(const struct comp_dev_s *dev) regval |= COMP_CSR_INPSEL_PIN2; break; -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) case STM32_COMP_INP_PIN_3: stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INP_3 : GPIO_COMP2_INP_3); @@ -431,8 +431,8 @@ static int stm32_compconfig(const struct comp_dev_s *dev) case STM32_COMP_INM_PIN_2: stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_2 : GPIO_COMP2_INM_2); -#if defined(CONFIG_STM32L4_STM32L4X5) || defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) regval |= COMP_CSR_INMSEL_PIN2; #else regval |= COMP_CSR_INMSEL_INMESEL; @@ -441,7 +441,7 @@ static int stm32_compconfig(const struct comp_dev_s *dev) #endif break; -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) case STM32_COMP_INM_PIN_3: stm32_configgpio(cmp == STM32_COMP1 ? GPIO_COMP1_INM_3 : GPIO_COMP2_INM_3); @@ -606,4 +606,4 @@ stm32_compinitialize(int intf, const struct stm32_comp_config_s *cfg) return dev; } -#endif /* CONFIG_STM32L4_COMP */ +#endif /* CONFIG_STM32_COMP */ diff --git a/arch/arm/src/stm32l4/stm32l4_comp.h b/arch/arm/src/stm32l4/stm32l4_comp.h index 02f92d4c9c8..7d5eaa2d1f2 100644 --- a/arch/arm/src/stm32l4/stm32l4_comp.h +++ b/arch/arm/src/stm32l4/stm32l4_comp.h @@ -50,7 +50,7 @@ * Public Types ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) /* Comparators */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.c b/arch/arm/src/stm32l4/stm32l4_dac.c index 7b1bd5b0e0a..721fe597fa2 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.c +++ b/arch/arm/src/stm32l4/stm32l4_dac.c @@ -60,20 +60,20 @@ #endif #if STM32_NDAC < 2 -# undef CONFIG_STM32L4_DAC2 -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY +# undef CONFIG_STM32_DAC2 +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY #endif #if STM32_NDAC < 1 -# undef CONFIG_STM32L4_DAC1 -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY +# undef CONFIG_STM32_DAC1 +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY #endif -#if defined(CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DMA configuration. */ @@ -83,63 +83,63 @@ * supported by the driver. */ -#ifdef CONFIG_STM32L4_DAC1_DMA -# if !defined(CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC1_DMA +# if !defined(CONFIG_STM32_DAC1_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC1_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC1_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC1_TIMER" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC1_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC1_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC1_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC1_DMA -# undef CONFIG_STM32L4_DAC1_TIMER +# if !defined(CONFIG_STM32_DAC1_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC1_TIMER" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC1_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC1_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC1_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC1_DMA +# undef CONFIG_STM32_DAC1_TIMER # endif #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if !defined(CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE < 1 -# define CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE 1 +#ifdef CONFIG_STM32_DAC2_DMA +# if !defined(CONFIG_STM32_DAC2_DMA_BUFFER_SIZE) || CONFIG_STM32_DAC2_DMA_BUFFER_SIZE < 1 +# define CONFIG_STM32_DAC2_DMA_BUFFER_SIZE 1 # endif -# if !defined(CONFIG_STM32L4_DAC2_TIMER) -# warning "A timer number must be specified in CONFIG_STM32L4_DAC2_TIMER" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER_FREQUENCY -# elif !defined(CONFIG_STM32L4_DAC2_TIMER_FREQUENCY) || \ - (CONFIG_STM32L4_DAC2_TIMER_FREQUENCY < 1) -# warning "A timer frequency (>0) must be specified in CONFIG_STM32L4_DAC2_TIMER_FREQUENCY" -# undef CONFIG_STM32L4_DAC2_DMA -# undef CONFIG_STM32L4_DAC2_TIMER +# if !defined(CONFIG_STM32_DAC2_TIMER) +# warning "A timer number must be specified in CONFIG_STM32_DAC2_TIMER" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER_FREQUENCY +# elif !defined(CONFIG_STM32_DAC2_TIMER_FREQUENCY) || \ + (CONFIG_STM32_DAC2_TIMER_FREQUENCY < 1) +# warning "A timer frequency (>0) must be specified in CONFIG_STM32_DAC2_TIMER_FREQUENCY" +# undef CONFIG_STM32_DAC2_DMA +# undef CONFIG_STM32_DAC2_TIMER # endif #endif /* Select DMA channels, favor DMA1 if configured. */ #undef HAVE_DMA -#ifdef CONFIG_STM32L4_DAC1_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC1_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMAMAP_DAC1_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMAMAP_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC1_DMA_CHAN DMACHAN_DAC1_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC1_DMA_CHAN DMACHAN_DAC1_2 # else # error "No DMA channel for DAC1" # endif # define HAVE_DMA #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA1) +#ifdef CONFIG_STM32_DAC2_DMA +# if defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMAMAP_DAC2_0 -# elif defined(CONFIG_STM32L4_DMAMUX1) && defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMAMUX1) && defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMAMAP_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA1) +# elif defined(CONFIG_STM32_DMA1) # define DAC2_DMA_CHAN DMACHAN_DAC2_1 -# elif defined(CONFIG_STM32L4_DMA2) +# elif defined(CONFIG_STM32_DMA2) # define DAC2_DMA_CHAN DMACHAN_DAC2_2 # else # error "No DMA channel for DAC2" @@ -171,106 +171,106 @@ #undef NEED_TIM2 #undef NEED_TIM4 -#ifdef CONFIG_STM32L4_DAC1_DMA -# if CONFIG_STM32L4_DAC1_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC1" +#ifdef CONFIG_STM32_DAC1_DMA +# if CONFIG_STM32_DAC1_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC1" # endif # define NEED_TIM6 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6 # define DAC1_TIMER_BASE STM32_TIM6_BASE # define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC1" +# elif CONFIG_STM32_DAC1_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC1" # endif # define NEED_TIM8 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8 # define DAC1_TIMER_BASE STM32_TIM8_BASE # define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC1" +# elif CONFIG_STM32_DAC1_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC1" # endif # define NEED_TIM7 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7 # define DAC1_TIMER_BASE STM32_TIM7_BASE -# elif CONFIG_STM32L4_DAC1_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC1" +# elif CONFIG_STM32_DAC1_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC1" # endif # define NEED_TIM5 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5 # define DAC1_TIMER_BASE STM32_TIM5_BASE # define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC1" +# elif CONFIG_STM32_DAC1_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC1" # endif # define NEED_TIM2 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2 # define DAC1_TIMER_BASE STM32_TIM2_BASE # define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC1_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC1" +# elif CONFIG_STM32_DAC1_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC1" # endif # define NEED_TIM4 # define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4 # define DAC1_TIMER_BASE STM32_TIM4_BASE # define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC1_TIMER" +# error "Unsupported CONFIG_STM32_DAC1_TIMER" # endif #else # define DAC1_TSEL_VALUE DAC_CR_TSEL_SW #endif -#ifdef CONFIG_STM32L4_DAC2_DMA -# if CONFIG_STM32L4_DAC2_TIMER == 6 -# ifndef CONFIG_STM32L4_TIM6_DAC -# error "CONFIG_STM32L4_TIM6_DAC required for DAC2" +#ifdef CONFIG_STM32_DAC2_DMA +# if CONFIG_STM32_DAC2_TIMER == 6 +# ifndef CONFIG_STM32_TIM6_DAC +# error "CONFIG_STM32_TIM6_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6 # define DAC2_TIMER_BASE STM32_TIM6_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 8 -# ifndef CONFIG_STM32L4_TIM8_DAC -# error "CONFIG_STM32L4_TIM8_DAC required for DAC2" +# elif CONFIG_STM32_DAC2_TIMER == 8 +# ifndef CONFIG_STM32_TIM8_DAC +# error "CONFIG_STM32_TIM8_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8 # define DAC2_TIMER_BASE STM32_TIM8_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 7 -# ifndef CONFIG_STM32L4_TIM7_DAC -# error "CONFIG_STM32L4_TIM7_DAC required for DAC2" +# elif CONFIG_STM32_DAC2_TIMER == 7 +# ifndef CONFIG_STM32_TIM7_DAC +# error "CONFIG_STM32_TIM7_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7 # define DAC2_TIMER_BASE STM32_TIM7_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 5 -# ifndef CONFIG_STM32L4_TIM5_DAC -# error "CONFIG_STM32L4_TIM5_DAC required for DAC2" +# elif CONFIG_STM32_DAC2_TIMER == 5 +# ifndef CONFIG_STM32_TIM5_DAC +# error "CONFIG_STM32_TIM5_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5 # define DAC2_TIMER_BASE STM32_TIM5_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 2 -# ifndef CONFIG_STM32L4_TIM2_DAC -# error "CONFIG_STM32L4_TIM2_DAC required for DAC2" +# elif CONFIG_STM32_DAC2_TIMER == 2 +# ifndef CONFIG_STM32_TIM2_DAC +# error "CONFIG_STM32_TIM2_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2 # define DAC2_TIMER_BASE STM32_TIM2_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY -# elif CONFIG_STM32L4_DAC2_TIMER == 4 -# ifndef CONFIG_STM32L4_TIM4_DAC -# error "CONFIG_STM32L4_TIM4_DAC required for DAC2" +# elif CONFIG_STM32_DAC2_TIMER == 4 +# ifndef CONFIG_STM32_TIM4_DAC +# error "CONFIG_STM32_TIM4_DAC required for DAC2" # endif # define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4 # define DAC2_TIMER_BASE STM32_TIM4_BASE # define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY # else -# error "Unsupported CONFIG_STM32L4_DAC2_TIMER" +# error "Unsupported CONFIG_STM32_DAC2_TIMER" # endif #else # define DAC2_TSEL_VALUE DAC_CR_TSEL_SW @@ -307,7 +307,7 @@ struct stm32_dac_s struct stm32_chan_s { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS const struct stm32_dac_ops_s *llops; /* Low-level DAC ops */ #endif uint8_t inuse : 1; /* True, the driver is in use and not available */ @@ -365,7 +365,7 @@ static int dac_timinit(struct stm32_chan_s *chan); static int dac_chaninit(struct stm32_chan_s *chan); static void dac_blockinit(void); -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static void dac_llops_enable(struct stm32_dac_dev_s *dev, bool enabled); static void dac_llops_writedro(struct stm32_dac_dev_s *dev, uint16_t data); #ifdef HAVE_DMA @@ -373,7 +373,7 @@ static void dac_llops_startdma(struct stm32_dac_dev_s *dev); static void dac_llops_stopdma(struct stm32_dac_dev_s *dev); #endif static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev); -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Private Data @@ -391,7 +391,7 @@ static const struct dac_ops_s g_dacops = /* Publicly visible DAC lower-half operations */ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS static const struct stm32_dac_ops_s g_dac_llops = { .enable = dac_llops_enable, @@ -402,37 +402,37 @@ static const struct stm32_dac_ops_s g_dac_llops = #endif .dump_regs = dac_llops_dumpregs }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 /* Channel 1 */ -#ifdef CONFIG_STM32L4_DAC1_DMA -uint16_t stm32_dac1_dmabuffer[CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC1_DMA +uint16_t stm32_dac1_dmabuffer[CONFIG_STM32_DAC1_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac1priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 0, -#ifdef CONFIG_STM32L4_DAC1_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC1_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC1_OUT, #endif .dro = STM32_DAC_DHR12R1, .cr = STM32_DAC_CR, -#ifdef CONFIG_STM32L4_DAC1_DMA +#ifdef CONFIG_STM32_DAC1_DMA .hasdma = 1, .dmachan = DAC1_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE, + .buffer_len = CONFIG_STM32_DAC1_DMA_BUFFER_SIZE, .dmabuffer = stm32_dac1_dmabuffer, - .timer = CONFIG_STM32L4_DAC1_TIMER, + .timer = CONFIG_STM32_DAC1_TIMER, .tsel = DAC1_TSEL_VALUE, .tbase = DAC1_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC1_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC1_TIMER_FREQUENCY, #endif }; @@ -442,37 +442,37 @@ static struct dac_dev_s g_dac1dev = .ad_priv = &g_dac1priv, }; -#endif /* CONFIG_STM32L4_DAC1 */ +#endif /* CONFIG_STM32_DAC1 */ -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 /* Channel 2 */ -#ifdef CONFIG_STM32L4_DAC2_DMA -uint16_t stm32_dac2_dmabuffer[CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE]; +#ifdef CONFIG_STM32_DAC2_DMA +uint16_t stm32_dac2_dmabuffer[CONFIG_STM32_DAC2_DMA_BUFFER_SIZE]; #endif static struct stm32_chan_s g_dac2priv = { -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS .llops = &g_dac_llops, #endif .intf = 1, -#ifdef CONFIG_STM32L4_DAC2_OUTPUT_ADC +#ifdef CONFIG_STM32_DAC2_OUTPUT_ADC .pin = 0xffffffffu, #else .pin = GPIO_DAC2_OUT, #endif .dro = STM32_DAC_DHR12R2, .cr = STM32_DAC_CR, -#ifdef CONFIG_STM32L4_DAC2_DMA +#ifdef CONFIG_STM32_DAC2_DMA .hasdma = 1, .dmachan = DAC2_DMA_CHAN, - .buffer_len = CONFIG_STM32L4_DAC2_DMA_BUFFER_SIZE, + .buffer_len = CONFIG_STM32_DAC2_DMA_BUFFER_SIZE, .dmabuffer = stm32_dac2_dmabuffer, - .timer = CONFIG_STM32L4_DAC2_TIMER, + .timer = CONFIG_STM32_DAC2_TIMER, .tsel = DAC2_TSEL_VALUE, .tbase = DAC2_TIMER_BASE, - .tfrequency = CONFIG_STM32L4_DAC2_TIMER_FREQUENCY, + .tfrequency = CONFIG_STM32_DAC2_TIMER_FREQUENCY, #endif }; @@ -482,7 +482,7 @@ static struct dac_dev_s g_dac2dev = .ad_priv = &g_dac2priv, }; -#endif /* CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC2 */ static struct stm32_dac_s g_dacblock; @@ -755,12 +755,12 @@ static void dac_dmatxcallback(DMA_HANDLE handle, uint8_t isr, switch (chan->intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: dev = &g_dac2dev; break; @@ -1215,7 +1215,7 @@ static void dac_blockinit(void) g_dacblock.init = 1; } -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /**************************************************************************** * Name: dac_llops_enable @@ -1319,7 +1319,7 @@ static void dac_llops_dumpregs(struct stm32_dac_dev_s *dev) dac_dumpregs(priv); } -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Functions @@ -1351,13 +1351,13 @@ struct dac_dev_s *stm32_dacinitialize(int intf) switch (intf) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 case 0: ainfo("DAC1-1 Selected\n"); dev = &g_dac1dev; break; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 case 1: ainfo("DAC1-2 Selected\n"); dev = &g_dac2dev; @@ -1385,5 +1385,5 @@ struct dac_dev_s *stm32_dacinitialize(int intf) return dev; } -#endif /* CONFIG_STM32L4_DAC1 || CONFIG_STM32L4_DAC2 */ +#endif /* CONFIG_STM32_DAC1 || CONFIG_STM32_DAC2 */ #endif /* CONFIG_DAC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dac.h b/arch/arm/src/stm32l4/stm32l4_dac.h index 144edea439a..d6b9b1e704b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dac.h +++ b/arch/arm/src/stm32l4/stm32l4_dac.h @@ -46,37 +46,37 @@ * is intended to be used for that purpose. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_DAC +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_DAC #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_DAC +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_DAC #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_DAC +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_DAC #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_DAC +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_DAC #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_DAC +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_DAC #endif -#ifndef CONFIG_STM32L4_TIM6 -# undef CONFIG_STM32L4_TIM6_DAC +#ifndef CONFIG_STM32_TIM6 +# undef CONFIG_STM32_TIM6_DAC #endif -#ifndef CONFIG_STM32L4_TIM7 -# undef CONFIG_STM32L4_TIM7_DAC +#ifndef CONFIG_STM32_TIM7 +# undef CONFIG_STM32_TIM7_DAC #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_DAC +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_DAC #endif -#ifndef CONFIG_STM32L4_TIM15 +#ifndef CONFIG_STM32_TIM15 # undef CONFIG_STM32L4_TIM15_DAC #endif -#ifndef CONFIG_STM32L4_TIM16 +#ifndef CONFIG_STM32_TIM16 # undef CONFIG_STM32L4_TIM16_DAC #endif -#ifndef CONFIG_STM32L4_TIM17 +#ifndef CONFIG_STM32_TIM17 # undef CONFIG_STM32L4_TIM17_DAC #endif @@ -97,7 +97,7 @@ * Public Types ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC_LL_OPS +#ifdef CONFIG_STM32_DAC_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" DAC driver structure. @@ -137,16 +137,16 @@ struct stm32_dac_ops_s void (*dump_regs)(struct stm32_dac_dev_s *dev); }; -#endif /* CONFIG_STM32L4_DAC_LL_OPS */ +#endif /* CONFIG_STM32_DAC_LL_OPS */ /**************************************************************************** * Public Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1_DMA +#ifdef CONFIG_STM32_DAC1_DMA extern uint16_t stm32_dac1_dmabuffer[]; #endif -#ifdef CONFIG_STM32L4_DAC2_DMA +#ifdef CONFIG_STM32_DAC2_DMA extern uint16_t stm32_dac2_dmabuffer[]; #endif diff --git a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h index 5e460f90603..fac299d947d 100644 --- a/arch/arm/src/stm32l4/stm32l4_dbgmcu.h +++ b/arch/arm/src/stm32l4/stm32l4_dbgmcu.h @@ -31,13 +31,13 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dbgmcu.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dbgmcu.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.c b/arch/arm/src/stm32l4/stm32l4_dfsdm.c index ef79acc58da..82472993748 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.c +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.c @@ -53,7 +53,7 @@ /* The peripheral must be enabled */ -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /**************************************************************************** * Pre-processor Definitions @@ -61,14 +61,14 @@ /* Sanity checking **********************************************************/ -#if !defined(CONFIG_STM32L4_DFSDM1_FLT0) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT1) && \ - !defined(CONFIG_STM32L4_DFSDM1_FLT2) && !defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if !defined(CONFIG_STM32_DFSDM1_FLT0) && \ + !defined(CONFIG_STM32_DFSDM1_FLT1) && \ + !defined(CONFIG_STM32_DFSDM1_FLT2) && !defined(CONFIG_STM32_DFSDM1_FLT3) # error "At least one DFSDM filter must be defined" #endif -#if defined(CONFIG_STM32L4_STM32L4X3) -# if defined(CONFIG_STM32L4_DFSDM1_FLT2) || defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_STM32L4X3) +# if defined(CONFIG_STM32_DFSDM1_FLT2) || defined(CONFIG_STM32_DFSDM1_FLT3) # error "Non-existent DFSDM filter defined" # endif #endif @@ -122,7 +122,7 @@ * without, although there is a risk of overrun. */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # define DFSDM_MAX_CHANNELS 4 # define DFSDM_MAX_FILTERS 2 #else @@ -131,8 +131,8 @@ #endif #ifdef DFSDM_HAVE_DMA -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error "STM32L4 DFSDM DMA support requires CONFIG_STM32L4_DMA1" +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error "STM32L4 DFSDM DMA support requires CONFIG_STM32_DMA1" # endif #endif @@ -232,16 +232,16 @@ static void dfsdm_startconv(struct stm32_dev_s *priv, bool enable); /* Interrupt Handler */ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t regval); -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg); #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg); #endif @@ -274,7 +274,7 @@ static const struct adc_ops_s g_adcops = /* DFSDM FLT0 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static struct stm32_dev_s g_dfsdmpriv0 = { .irq = STM32_IRQ_DFSDM0, @@ -303,7 +303,7 @@ static struct adc_dev_s g_dfsdmdev0 = /* DFSDM FLT1 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static struct stm32_dev_s g_dfsdmpriv1 = { .irq = STM32_IRQ_DFSDM1, @@ -332,7 +332,7 @@ static struct adc_dev_s g_dfsdmdev1 = /* DFSDM FLT2 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static struct stm32_dev_s g_dfsdmpriv2 = { .irq = STM32_IRQ_DFSDM2, @@ -361,7 +361,7 @@ static struct adc_dev_s g_dfsdmdev2 = /* DFSDM FLT3 */ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static struct stm32_dev_s g_dfsdmpriv3 = { .irq = STM32_IRQ_DFSDM3, @@ -1582,7 +1582,7 @@ static int dfsdm_interrupt(struct adc_dev_s *dev, uint32_t isr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -1607,7 +1607,7 @@ static int dfsdm_flt0_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -1632,7 +1632,7 @@ static int dfsdm_flt1_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -1657,7 +1657,7 @@ static int dfsdm_flt2_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) static int dfsdm_flt3_interrupt(int irq, void *context, void *arg) { uint32_t regval; @@ -1760,25 +1760,25 @@ struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, switch (intf) { -#if defined(CONFIG_STM32L4_DFSDM1_FLT0) +#if defined(CONFIG_STM32_DFSDM1_FLT0) case 0: ainfo("DFSDM FLT0 selected\n"); dev = &g_dfsdmdev0; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT1) +#if defined(CONFIG_STM32_DFSDM1_FLT1) case 1: ainfo("DFSDM FLT1 selected\n"); dev = &g_dfsdmdev1; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT2) +#if defined(CONFIG_STM32_DFSDM1_FLT2) case 2: ainfo("DFSDM FLT2 selected\n"); dev = &g_dfsdmdev2; break; #endif -#if defined(CONFIG_STM32L4_DFSDM1_FLT3) +#if defined(CONFIG_STM32_DFSDM1_FLT3) case 3: ainfo("DFSDM FLT3 selected\n"); dev = &g_dfsdmdev3; @@ -1817,5 +1817,5 @@ struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, return dev; } -#endif /* CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_STM32_DFSDM */ #endif /* CONFIG_ADC */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfsdm.h b/arch/arm/src/stm32l4/stm32l4_dfsdm.h index 82395d4c767..f7fbe48b98b 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfsdm.h +++ b/arch/arm/src/stm32l4/stm32l4_dfsdm.h @@ -45,43 +45,43 @@ * on STM32L4X3, while STM32L4X6 adds support for timers 4,7 and 8 as well. */ -#ifndef CONFIG_STM32L4_TIM1 +#ifndef CONFIG_STM32_TIM1 # undef CONFIG_STM32L4_TIM1_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM3 +#ifndef CONFIG_STM32_TIM3 # undef CONFIG_STM32L4_TIM3_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM4 +#ifndef CONFIG_STM32_TIM4 # undef CONFIG_STM32L4_TIM4_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM6 +#ifndef CONFIG_STM32_TIM6 # undef CONFIG_STM32L4_TIM6_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM7 +#ifndef CONFIG_STM32_TIM7 # undef CONFIG_STM32L4_TIM7_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM8 +#ifndef CONFIG_STM32_TIM8 # undef CONFIG_STM32L4_TIM8_DFSDM #endif -#ifndef CONFIG_STM32L4_TIM16 +#ifndef CONFIG_STM32_TIM16 # undef CONFIG_STM32L4_TIM16_DFSDM #endif -#if defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_STM32_DFSDM) /* DMA support */ #undef DFSDM_HAVE_DMA -#if defined(CONFIG_STM32L4_DFSDM1_DMA) +#if defined(CONFIG_STM32_DFSDM1_DMA) # define DFSDM_HAVE_DMA 1 #endif /* ADC output to DFSDM support */ #undef ADC_HAVE_DFSDM -#if defined(CONFIG_STM32L4_ADC1_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC2_OUTPUT_DFSDM) || \ - defined(CONFIG_STM32L4_ADC3_OUTPUT_DFSDM) +#if defined(CONFIG_STM32_ADC1_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC2_OUTPUT_DFSDM) || \ + defined(CONFIG_STM32_ADC3_OUTPUT_DFSDM) # define ADC_HAVE_DFSDM #endif @@ -330,5 +330,5 @@ struct adc_dev_s *stm32_dfsdm_initialize(int intf, const uint8_t *chanlist, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_STM32_DFSDM */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_DFSDM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.c b/arch/arm/src/stm32l4/stm32l4_dfumode.c index 8f2db0fba1b..a4c76d51dfd 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.c +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.c @@ -44,7 +44,7 @@ typedef void (*boot_call_t)(void); * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) static inline void rcc_reset(void) { uint32_t regval; @@ -127,7 +127,7 @@ static inline void apb_reset(void) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) void stm32_dfumode(void) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_dfumode.h b/arch/arm/src/stm32l4/stm32l4_dfumode.h index c27e1887717..f5871ad29ff 100644 --- a/arch/arm/src/stm32l4/stm32l4_dfumode.h +++ b/arch/arm/src/stm32l4/stm32l4_dfumode.h @@ -41,7 +41,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) void stm32_dfumode(void) noreturn_function; #endif diff --git a/arch/arm/src/stm32l4/stm32l4_dma.c b/arch/arm/src/stm32l4/stm32l4_dma.c index 5c2b8826acb..c0e9bf79add 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.c +++ b/arch/arm/src/stm32l4/stm32l4_dma.c @@ -35,10 +35,10 @@ * family. */ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) #include "stm32l4x6xx_dma.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) #include "stm32l4xrxx_dma.c" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index 2d7a3aa548c..2bc4efc3fbb 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -34,13 +34,13 @@ /* Include the correct DMA register definitions for this STM32 family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_dma.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_dma.h" # include "hardware/stm32l4xrxx_dmamux.h" #else @@ -90,7 +90,7 @@ struct stm32_dmaregs_s uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32L4_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -126,8 +126,8 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) /**************************************************************************** * Name: stm32_dmachannel @@ -168,7 +168,7 @@ extern "C" DMA_HANDLE stm32_dmachannel(unsigned int chan); -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) /**************************************************************************** * Name: stm32_dmachannel @@ -291,7 +291,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32l4/stm32l4_exti.h b/arch/arm/src/stm32l4/stm32l4_exti.h index 3b660bafe10..a30e5321fa1 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti.h +++ b/arch/arm/src/stm32l4/stm32l4_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_exti_comp.c b/arch/arm/src/stm32l4/stm32l4_exti_comp.c index f7508e387fd..8579f144a09 100644 --- a/arch/arm/src/stm32l4/stm32l4_exti_comp.c +++ b/arch/arm/src/stm32l4/stm32l4_exti_comp.c @@ -70,8 +70,8 @@ static struct comp_callback_s g_comp_handlers[STM32_COMP_NUM]; static const uint32_t g_comp_lines[STM32_COMP_NUM] = { -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) EXTI1_COMP1, EXTI1_COMP2 #else diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 48eb504d41b..06fe9d2c1d9 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -36,13 +36,13 @@ * family */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_firewall.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_firewall.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_flash.c b/arch/arm/src/stm32l4/stm32l4_flash.c index 46736f121a7..6905cd47afe 100644 --- a/arch/arm/src/stm32l4/stm32l4_flash.c +++ b/arch/arm/src/stm32l4/stm32l4_flash.c @@ -50,12 +50,12 @@ #include "stm32l4_flash.h" #include "arm_internal.h" -#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR)) +#if !(defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR)) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif @@ -153,9 +153,9 @@ static inline void flash_erase(size_t page) modifyreg32(STM32_FLASH_CR, FLASH_CR_PNB_MASK, FLASH_CR_PNB(page & 0xff)); -#if defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || \ - defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || \ + defined(CONFIG_STM32_STM32L4XR) if (page <= 0xff) { /* Select bank 1 */ @@ -180,7 +180,7 @@ static inline void flash_erase(size_t page) modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0); } -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) static void data_cache_disable(void) { modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0); @@ -196,7 +196,7 @@ static void data_cache_enable(void) modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN); } -#endif /* defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ +#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */ /**************************************************************************** * Public Functions @@ -494,7 +494,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) /* Write the page. Must be with double-words. */ -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_disable(); #endif @@ -530,7 +530,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t buflen) modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); set_pg_bit = false; -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif @@ -548,7 +548,7 @@ out: if (set_pg_bit) { modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0); -#if defined(CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) +#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) data_cache_enable(); #endif } diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.c b/arch/arm/src/stm32l4/stm32l4_freerun.c index 29aedb4864c..c768b6237e3 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.c +++ b/arch/arm/src/stm32l4/stm32l4_freerun.c @@ -37,7 +37,7 @@ #include "stm32l4_freerun.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions @@ -272,4 +272,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32L4_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32l4/stm32l4_freerun.h b/arch/arm/src/stm32l4/stm32l4_freerun.h index 4f99980e27d..c1aeacf7afd 100644 --- a/arch/arm/src/stm32l4/stm32l4_freerun.h +++ b/arch/arm/src/stm32l4/stm32l4_freerun.h @@ -35,7 +35,7 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types @@ -140,5 +140,5 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); } #endif -#endif /* CONFIG_STM32L4_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_FREERUN_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index cfe12286031..1a1e18a76f8 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -344,10 +344,10 @@ int stm32_configgpio(uint32_t cfgset) * (RM0351 Rev 7, p521) */ -#if defined(CONFIG_STM32L4_STM32L471XX) || \ - defined(CONFIG_STM32L4_STM32L475XX) || \ - defined(CONFIG_STM32L4_STM32L476XX) || \ - defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32_STM32L471XX) || \ + defined(CONFIG_STM32_STM32L475XX) || \ + defined(CONFIG_STM32_STM32L476XX) || \ + defined(CONFIG_STM32_STM32L486XX) if (pinmode == GPIO_MODER_ANALOG) { diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 13e321fc0d4..fd79b6b232e 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -39,8 +39,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_gpio.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_hsi48.h b/arch/arm/src/stm32l4/stm32l4_hsi48.h index f9636dce34d..de78d9f6be9 100644 --- a/arch/arm/src/stm32l4/stm32l4_hsi48.h +++ b/arch/arm/src/stm32l4/stm32l4_hsi48.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_STM32L4_HAVE_HSI48 +#ifdef CONFIG_STM32_HAVE_HSI48 /**************************************************************************** * Public Types @@ -92,5 +92,5 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); -#endif /* CONFIG_STM32L4_HAVE_HSI48 */ +#endif /* CONFIG_STM32_HAVE_HSI48 */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_HSI48_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.c b/arch/arm/src/stm32l4/stm32l4_i2c.c index 91a1ca0bc41..a7ad24d6416 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.c +++ b/arch/arm/src/stm32l4/stm32l4_i2c.c @@ -171,28 +171,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32L4_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32L4_I2C1 - * CONFIG_STM32L4_I2C2 - * CONFIG_STM32L4_I2C3 - * CONFIG_STM32L4_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32L4_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32L4_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32L4_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32L4_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32L4_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -272,8 +272,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C2) || \ - defined(CONFIG_STM32L4_I2C3) || defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -285,25 +285,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32L4_I2CTIMEOSEC) && !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 -# define CONFIG_STM32L4_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32L4_I2CTIMEOSEC) -# define CONFIG_STM32L4_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32L4_I2CTIMEOMS) -# define CONFIG_STM32L4_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32L4_I2CTIMEOTICKS -# define CONFIG_STM32L4_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32L4_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32L4_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32L4_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -471,9 +471,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32L4_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -517,7 +517,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -553,7 +553,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -589,7 +589,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -625,7 +625,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -758,7 +758,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -775,7 +775,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -833,12 +833,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32L4_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -877,10 +877,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32L4_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32L4_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2319,7 +2319,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); @@ -2404,7 +2404,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); @@ -2909,22 +2909,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3010,4 +3010,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32L4_I2C1 || CONFIG_STM32L4_I2C2 || CONFIG_STM32L4_I2C3 || CONFIG_STM32L4_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32l4/stm32l4_i2c.h b/arch/arm/src/stm32l4/stm32l4_i2c.h index 5cf6b3b0dbc..04302121439 100644 --- a/arch/arm/src/stm32l4/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/stm32l4_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32L4_I2C_DYNTIMEO -# if CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32L4_I2C_DYNTIMEO because of CONFIG_STM32L4_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32L4_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32l4/stm32l4_idle.c b/arch/arm/src/stm32l4/stm32l4_idle.c index 0a156b2512e..985d307308b 100644 --- a/arch/arm/src/stm32l4/stm32l4_idle.c +++ b/arch/arm/src/stm32l4/stm32l4_idle.c @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l4/stm32l4_iwdg.c b/arch/arm/src/stm32l4/stm32l4_iwdg.c index fcc02723cc1..833283f7810 100644 --- a/arch/arm/src/stm32l4/stm32l4_iwdg.c +++ b/arch/arm/src/stm32l4/stm32l4_iwdg.c @@ -42,7 +42,7 @@ #include "stm32l4_dbgmcu.h" #include "stm32l4_wdg.h" -#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32L4_IWDG) +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) /**************************************************************************** * Pre-processor Definitions @@ -104,7 +104,7 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); #else @@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -221,7 +221,7 @@ static uint16_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG_REGDEBUG +#ifdef CONFIG_STM32_IWDG_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -637,7 +637,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_settimeout((struct watchdog_lowerhalf_s *)priv, - CONFIG_STM32L4_IWDG_DEFTIMOUT); + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -648,9 +648,9 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) * on DBG_IWDG_STOP configuration bit in DBG module. */ -#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \ - defined(CONFIG_STM32L4_JTAG_SW_ENABLE) +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { uint32_t cr; @@ -661,4 +661,4 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) #endif } -#endif /* CONFIG_WATCHDOG && CONFIG_STM32L4_IWDG */ +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32l4/stm32l4_lptim.c b/arch/arm/src/stm32l4/stm32l4_lptim.c index 2b1c4845aa5..9ce24f201a3 100644 --- a/arch/arm/src/stm32l4/stm32l4_lptim.c +++ b/arch/arm/src/stm32l4/stm32l4_lptim.c @@ -84,7 +84,7 @@ #include "stm32l4_lptim.h" #include "stm32l4_rcc.h" -#if defined(CONFIG_STM32L4_LPTIM1) || defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM1) || defined(CONFIG_STM32_LPTIM2) /**************************************************************************** * Private Types @@ -150,7 +150,7 @@ static const struct stm32_lptim_ops_s stm32_lptim_ops = .getperiod = &stm32_lptim_getperiod }; -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) static struct stm32_lptim_priv_s stm32_lptim1_priv = { .ops = &stm32_lptim_ops, @@ -160,7 +160,7 @@ static struct stm32_lptim_priv_s stm32_lptim1_priv = }; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) static struct stm32_lptim_priv_s stm32_lptim2_priv = { .ops = &stm32_lptim_ops, @@ -182,11 +182,11 @@ static struct stm32_lptim_dev_s *stm32_lptim_getstruct(int timer) { switch (timer) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case 1: return (struct stm32_lptim_dev_s *)&stm32_lptim1_priv; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case 2: return (struct stm32_lptim_dev_s *)&stm32_lptim2_priv; #endif @@ -217,12 +217,12 @@ static int stm32_lptim_enable(struct stm32_lptim_dev_s *dev) switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_LPTIM1EN); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB1ENR2, 0, RCC_APB1ENR2_LPTIM2EN); break; @@ -245,12 +245,12 @@ static int stm32_lptim_disable(struct stm32_lptim_dev_s *dev) switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_LPTIM1EN, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB1ENR2, RCC_APB1ENR2_LPTIM2EN, 0); break; @@ -273,13 +273,13 @@ static int stm32_lptim_reset(struct stm32_lptim_dev_s *dev) switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: modifyreg32(STM32_RCC_APB1RSTR1, 0, RCC_APB1RSTR1_LPTIM1RST); modifyreg32(STM32_RCC_APB1RSTR1, RCC_APB1RSTR1_LPTIM1RST, 0); break; #endif -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM2_BASE: modifyreg32(STM32_RCC_APB1RSTR2, 0, RCC_APB1RSTR2_LPTIM2RST); modifyreg32(STM32_RCC_APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST, 0); @@ -304,7 +304,7 @@ static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, switch (((struct stm32_lptim_priv_s *)dev)->base) { -#if defined(CONFIG_STM32L4_LPTIM1) +#if defined(CONFIG_STM32_LPTIM1) case STM32_LPTIM1_BASE: switch (channel) { @@ -327,9 +327,9 @@ static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM1 */ +#endif /* CONFIG_STM32_LPTIM1 */ -#if defined(CONFIG_STM32L4_LPTIM2) +#if defined(CONFIG_STM32_LPTIM2) case STM32_LPTIM2_BASE: switch (channel) { @@ -352,7 +352,7 @@ static int stm32_lptim_get_gpioconfig(struct stm32_lptim_dev_s *dev, return ERROR; } break; -#endif /* CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM2 */ default: return ERROR; @@ -531,12 +531,12 @@ static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: ccr_mask = RCC_CCIPR_LPTIM1SEL_MASK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: ccr_mask = RCC_CCIPR_LPTIM2SEL_MASK; break; @@ -550,12 +550,12 @@ static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, case STM32_LPTIM_CLK_PCLK: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_PCLK; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_PCLK; break; @@ -565,12 +565,12 @@ static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, case STM32_LPTIM_CLK_HSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_HSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_HSI; break; @@ -580,12 +580,12 @@ static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, case STM32_LPTIM_CLK_LSI: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSI; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSI; break; @@ -595,12 +595,12 @@ static int stm32_lptim_setclocksource(struct stm32_lptim_dev_s *dev, case STM32_LPTIM_CLK_LSE: switch (priv->base) { -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 case STM32_LPTIM1_BASE: ccr_bits = RCC_CCIPR_LPTIM1SEL_LSE; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 case STM32_LPTIM2_BASE: ccr_bits = RCC_CCIPR_LPTIM2SEL_LSE; break; @@ -796,4 +796,4 @@ int stm32_lptim_deinit(struct stm32_lptim_dev_s * dev) return OK; } -#endif /* CONFIG_STM32L4_LPTIM1 || CONFIG_STM32L4_LPTIM2 */ +#endif /* CONFIG_STM32_LPTIM1 || CONFIG_STM32_LPTIM2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_lse.c b/arch/arm/src/stm32l4/stm32l4_lse.c index 0a36765f326..c273c49d3e8 100644 --- a/arch/arm/src/stm32l4/stm32l4_lse.c +++ b/arch/arm/src/stm32l4/stm32l4_lse.c @@ -35,16 +35,16 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -86,11 +86,11 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif @@ -103,18 +103,18 @@ void stm32_rcc_enablelse(void) stm32_waste(); } -#if defined(CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32L4_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32L4 only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32L4_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.c b/arch/arm/src/stm32l4/stm32l4_oneshot.c index dbcdb372253..ebacd10a609 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.c +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.c @@ -39,7 +39,7 @@ #include "stm32l4_oneshot.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32L4_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32L4_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32L4_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -457,4 +457,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32L4_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32l4/stm32l4_oneshot.h b/arch/arm/src/stm32l4/stm32l4_oneshot.h index d8dc54996ed..d8e77479d20 100644 --- a/arch/arm/src/stm32l4/stm32l4_oneshot.h +++ b/arch/arm/src/stm32l4/stm32l4_oneshot.h @@ -36,22 +36,22 @@ #include "stm32l4_tim.h" -#ifdef CONFIG_STM32L4_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32L4_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32L4_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32L4_ONESHOT_MAXTIMERS -# define CONFIG_STM32L4_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32L4_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -194,5 +194,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32L4_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_ONESHOT_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfs.h b/arch/arm/src/stm32l4/stm32l4_otgfs.h index 9b6991c9904..9a930afa962 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfs.h +++ b/arch/arm/src/stm32l4/stm32l4_otgfs.h @@ -33,11 +33,11 @@ #include "stm32.h" -#if defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_STM32_OTGFS) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -116,5 +116,5 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_OTGFS_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c index a7c8ef95eef..bf1cbe30796 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfsdev.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfsdev.c @@ -50,7 +50,7 @@ #include "stm32l4_otgfs.h" #include "stm32l4_pwr.h" -#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32L4_OTGFS)) +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32_OTGFS)) /**************************************************************************** * Pre-processor Definitions @@ -58,8 +58,8 @@ /* Configuration ************************************************************/ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif #ifndef CONFIG_USBDEV_EP0_MAXSIZE @@ -548,7 +548,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint32_t val, uint32_t addr); #else @@ -893,7 +893,7 @@ const struct trace_msg_t g_usb_trace_strings_intdecode[] = * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static uint32_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -956,7 +956,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#if defined(CONFIG_STM32L4_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +#if defined(CONFIG_STM32_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) static void stm32_putreg(uint32_t val, uint32_t addr) { /* Show the register value being written */ @@ -5687,7 +5687,7 @@ void arm_usbinitialize(void) /* SOF output pin configuration is configurable. */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT stm32_configgpio(GPIO_OTGFS_SOF); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_otgfshost.c b/arch/arm/src/stm32l4/stm32l4_otgfshost.c index 41d83c9592f..0d28603efda 100644 --- a/arch/arm/src/stm32l4/stm32l4_otgfshost.c +++ b/arch/arm/src/stm32l4/stm32l4_otgfshost.c @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32l4_usbhost.h" -#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32L4_OTGFS) +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32_OTGFS) /**************************************************************************** * Pre-processor Definitions @@ -69,62 +69,62 @@ * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: + * CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: * 128 - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. - * CONFIG_STM32L4_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB * packets. Depends on CONFIG_DEBUG. */ /* Pre-requisites (partial) */ -#ifndef CONFIG_STM32L4_SYSCFG -# error "CONFIG_STM32L4_SYSCFG is required" +#ifndef CONFIG_STM32_SYSCFG +# error "CONFIG_STM32_SYSCFG is required" #endif /* Default RxFIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_RXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_RXFIFO_SIZE 128 +#ifndef CONFIG_STM32_OTGFS_RXFIFO_SIZE +# define CONFIG_STM32_OTGFS_RXFIFO_SIZE 128 #endif /* Default host non-periodic Tx FIFO size */ -#ifndef CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_NPTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_NPTXFIFO_SIZE 96 #endif /* Default host periodic Tx fifo size register */ -#ifndef CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE -# define CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE 96 +#ifndef CONFIG_STM32_OTGFS_PTXFIFO_SIZE +# define CONFIG_STM32_OTGFS_PTXFIFO_SIZE 96 #endif /* Maximum size of a descriptor */ -#ifndef CONFIG_STM32L4_OTGFS_DESCSIZE -# define CONFIG_STM32L4_OTGFS_DESCSIZE 128 +#ifndef CONFIG_STM32_OTGFS_DESCSIZE +# define CONFIG_STM32_OTGFS_DESCSIZE 128 #endif /* Register/packet debug depends on CONFIG_DEBUG */ #ifndef CONFIG_DEBUG -# undef CONFIG_STM32L4_USBHOST_REGDEBUG -# undef CONFIG_STM32L4_USBHOST_PKTDUMP +# undef CONFIG_STM32_USBHOST_REGDEBUG +# undef CONFIG_STM32_USBHOST_PKTDUMP #endif /* HCD Setup ****************************************************************/ @@ -269,7 +269,7 @@ struct stm32_usbhost_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); static uint32_t stm32_getreg(uint32_t addr); @@ -282,7 +282,7 @@ static void stm32_putreg(uint32_t addr, uint32_t value); static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, uint32_t setbits); -#ifdef CONFIG_STM32L4_USBHOST_PKTDUMP +#ifdef CONFIG_STM32_USBHOST_PKTDUMP # define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) #else # define stm32_pktdump(m,b,n) @@ -380,7 +380,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv); /* Second level interrupt handlers */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv); #endif static inline void @@ -504,7 +504,7 @@ static struct usbhost_connection_s g_usbconn = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) { lldbg("%08" PRIx32 "%s%08" PRIx32 "\n", addr, iswrite ? "<-" : "->", val); @@ -519,7 +519,7 @@ static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) { static uint32_t prevaddr = 0; @@ -583,7 +583,7 @@ static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static uint32_t stm32_getreg(uint32_t addr) { /* Read the value from the register */ @@ -605,7 +605,7 @@ static uint32_t stm32_getreg(uint32_t addr) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBHOST_REGDEBUG +#ifdef CONFIG_STM32_USBHOST_REGDEBUG static void stm32_putreg(uint32_t addr, uint32_t val) { /* Check if we need to print this value */ @@ -3009,7 +3009,7 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR static inline void stm32_gint_sofisr(struct stm32_usbhost_s *priv) { /* Handle SOF interrupt */ @@ -3580,7 +3580,7 @@ static int stm32_gint_isr(int irq, void *context, void *arg) /* Handle the start of frame interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR if ((pending & OTGFS_GINT_SOF) != 0) { usbhost_vtrace1(OTGFS_VTRACE1_GINT_SOF, 0); @@ -3746,7 +3746,7 @@ static inline void stm32_hostinit_enable(void) * OTGFS_GINT_DISC : Disconnect detected interrupt */ -#ifdef CONFIG_STM32L4_OTGFS_SOFINTR +#ifdef CONFIG_STM32_OTGFS_SOFINTR regval |= (OTGFS_GINT_SOF | OTGFS_GINT_RXFLVL | OTGFS_GINT_IISOOXFR | OTGFS_GINT_HPRT | OTGFS_GINT_HC | OTGFS_GINT_DISC); #else @@ -4277,7 +4277,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* There is no special memory requirement for the STM32. */ - alloc = kmm_malloc(CONFIG_STM32L4_OTGFS_DESCSIZE); + alloc = kmm_malloc(CONFIG_STM32_OTGFS_DESCSIZE); if (!alloc) { return -ENOMEM; @@ -4286,7 +4286,7 @@ static int stm32_alloc(struct usbhost_driver_s *drvr, /* Return the allocated address and size of the descriptor buffer */ *buffer = alloc; - *maxlen = CONFIG_STM32L4_OTGFS_DESCSIZE; + *maxlen = CONFIG_STM32_OTGFS_DESCSIZE; return OK; } @@ -5163,21 +5163,21 @@ static void stm32_host_initialize(struct stm32_usbhost_s *priv) /* Configure Rx FIFO size (GRXFSIZ) */ - stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32L4_OTGFS_RXFIFO_SIZE); - offset = CONFIG_STM32L4_OTGFS_RXFIFO_SIZE; + stm32_putreg(STM32_OTGFS_GRXFSIZ, CONFIG_STM32_OTGFS_RXFIFO_SIZE); + offset = CONFIG_STM32_OTGFS_RXFIFO_SIZE; /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_NPTXFIFO_SIZE << OTGFS_HNPTXFSIZ_NPTXFD_SHIFT)); stm32_putreg(STM32_OTGFS_HNPTXFSIZ, regval); - offset += CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE; + offset += CONFIG_STM32_OTGFS_NPTXFIFO_SIZE; /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ regval = (offset | - (CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE << + (CONFIG_STM32_OTGFS_PTXFIFO_SIZE << OTGFS_HPTXFSIZ_PTXFD_SHIFT)); stm32_putreg(STM32_OTGFS_HPTXFSIZ, regval); @@ -5457,7 +5457,7 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) /* SOF output pin configuration is configurable */ -#ifdef CONFIG_STM32L4_OTGFS_SOFOUTPUT +#ifdef CONFIG_STM32_OTGFS_SOFOUTPUT stm32_configgpio(GPIO_OTGFS_SOF); #endif @@ -5483,4 +5483,4 @@ struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) return &g_usbconn; } -#endif /* CONFIG_USBHOST && CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_USBHOST && CONFIG_STM32_OTGFS */ diff --git a/arch/arm/src/stm32l4/stm32l4_pmstop.c b/arch/arm/src/stm32l4/stm32l4_pmstop.c index 3b07546af4b..cd57bbd4aa8 100644 --- a/arch/arm/src/stm32l4/stm32l4_pmstop.c +++ b/arch/arm/src/stm32l4/stm32l4_pmstop.c @@ -150,7 +150,7 @@ int stm32_pmstop2(void) uint32_t regval; regval = getreg32(STM32_PWR_CR1); -#ifdef CONFIG_STM32L4_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP /* SRAM3 is used as heap, so it must not be powered off in Stop 2 mode. */ regval |= PWR_CR1_RRSTP; diff --git a/arch/arm/src/stm32l4/stm32l4_pulsecount.c b/arch/arm/src/stm32l4/stm32l4_pulsecount.c index 54bfd8d5dd1..14704082eb7 100644 --- a/arch/arm/src/stm32l4/stm32l4_pulsecount.c +++ b/arch/arm/src/stm32l4/stm32l4_pulsecount.c @@ -46,7 +46,7 @@ * intended for use with the pulsecount upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PULSECOUNT) || defined(CONFIG_STM32L4_TIM8_PULSECOUNT) +#if defined(CONFIG_STM32_TIM1_PULSECOUNT) || defined(CONFIG_STM32_TIM8_PULSECOUNT) /**************************************************************************** * Pre-processor Definitions @@ -159,10 +159,10 @@ static int pulsecount_configure(struct pulsecount_lowerhalf_s *dev); static int pulsecount_timer(struct pulsecount_lowerhalf_s *dev, const struct pulsecount_info_s *info); static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev); -# ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +# ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg); # endif -# ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +# ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg); # endif static uint8_t pulsecount_count(uint32_t count); @@ -189,107 +189,107 @@ static int pulsecount_ioctl(struct pulsecount_lowerhalf_s *dev, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_tim_s g_pulsecount1dev = { .channel = { - .channel = CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH1OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH2OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH3OUT, }, -#elif CONFIG_STM32L4_TIM1_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM1_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM1_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM1_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM1_PULSECOUNT_IDLE, .pincfg = GPIO_TIM1_CH4OUT, }, #endif }, .timid = 1, .timtype = TIMTYPE_TIM1, - .t_dts = CONFIG_STM32L4_TIM1_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM1_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM1UP, .base = STM32_TIM1_BASE, .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_tim_s g_pulsecount8dev = { .channel = { - .channel = CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL, -#if CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 1 + .channel = CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL, +#if CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 1 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH1OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 2 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 2 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH2OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 3 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 3 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH3OUT, }, -#elif CONFIG_STM32L4_TIM8_PULSECOUNT_CHANNEL == 4 +#elif CONFIG_STM32_TIM8_PULSECOUNT_CHANNEL == 4 .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_PULSECOUNT_POL, - .idle = CONFIG_STM32L4_TIM8_PULSECOUNT_IDLE, + .pol = CONFIG_STM32_TIM8_PULSECOUNT_POL, + .idle = CONFIG_STM32_TIM8_PULSECOUNT_IDLE, .pincfg = GPIO_TIM8_CH4OUT, }, #endif }, .timid = 8, .timtype = TIMTYPE_TIM8, - .t_dts = CONFIG_STM32L4_TIM8_PULSECOUNT_TDTS, + .t_dts = CONFIG_STM32_TIM8_PULSECOUNT_TDTS, .irq = STM32_IRQ_TIM8UP, .base = STM32_TIM8_BASE, .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ static const struct pulsecount_ops_s g_pulsecountops = { @@ -300,7 +300,7 @@ static const struct pulsecount_ops_s g_pulsecountops = .ioctl = pulsecount_ioctl, }; -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount1lower = { .ops = &g_pulsecountops, @@ -308,7 +308,7 @@ static struct stm32_pulsecount_s g_pulsecount1lower = }; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static struct stm32_pulsecount_s g_pulsecount8lower = { .ops = &g_pulsecountops, @@ -1224,21 +1224,21 @@ static int pulsecount_interrupt(struct pulsecount_lowerhalf_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT static int pulsecount_tim1interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount1dev); } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT */ -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT static int pulsecount_tim8interrupt(int irq, void *context, void *arg) { return pulsecount_interrupt((struct pulsecount_lowerhalf_s *) &g_pulsecount8dev); } -#endif /* CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM8_PULSECOUNT */ /**************************************************************************** * Name: pulsecount_count @@ -1308,7 +1308,7 @@ static int pulsecount_setapbclock(struct stm32_tim_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { regaddr = STM32_RCC_APB2ENR; @@ -1317,7 +1317,7 @@ static int pulsecount_setapbclock(struct stm32_tim_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { regaddr = STM32_RCC_APB2ENR; @@ -1482,13 +1482,13 @@ static int pulsecount_ll_stop(struct pulsecount_lowerhalf_s *dev) switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; @@ -1624,7 +1624,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PULSECOUNT +#ifdef CONFIG_STM32_TIM1_PULSECOUNT case 1: { lower = &g_pulsecount1lower; @@ -1634,7 +1634,7 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) } #endif -#ifdef CONFIG_STM32L4_TIM8_PULSECOUNT +#ifdef CONFIG_STM32_TIM8_PULSECOUNT case 8: { lower = &g_pulsecount8lower; @@ -1654,4 +1654,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer) return (struct pulsecount_lowerhalf_s *)lower; } -#endif /* CONFIG_STM32L4_TIM1_PULSECOUNT || CONFIG_STM32L4_TIM8_PULSECOUNT */ +#endif /* CONFIG_STM32_TIM1_PULSECOUNT || CONFIG_STM32_TIM8_PULSECOUNT */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.c b/arch/arm/src/stm32l4/stm32l4_pwm.c index 679112ed21a..68b03c67ace 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.c +++ b/arch/arm/src/stm32l4/stm32l4_pwm.c @@ -46,12 +46,12 @@ * intended for use with the PWM upper half driver. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /**************************************************************************** * Pre-processor Definitions @@ -91,9 +91,9 @@ * supported capture/compare. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) # define HAVE_ADVTIM #else # undef HAVE_ADVTIM @@ -101,7 +101,7 @@ /* Low power Timer support */ -#if defined(CONFIG_STM32L4_LPTIM1_PWM) || defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) || defined(CONFIG_STM32_LPTIM2_PWM) # define HAVE_LPTIM #else # undef HAVE_LPTIM @@ -109,7 +109,7 @@ /* Synchronisation support */ -#ifdef CONFIG_STM32L4_PWM_TRGO +#ifdef CONFIG_STM32_PWM_TRGO # define HAVE_TRGO #endif @@ -165,7 +165,7 @@ struct stm32_pwmchan_s struct stm32_pwmtimer_s { const struct pwm_ops_s *ops; /* PWM operations */ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS const struct stm32_pwm_ops_s *llops; /* Low-level PWM ops */ #endif struct stm32_pwmchan_s *channels; /* Channels configuration */ @@ -226,7 +226,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, uint32_t ccr); static int pwm_mode_configure(struct pwm_lowerhalf_s *dev, uint8_t channel, uint32_t mode); -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif static int pwm_arr_update(struct pwm_lowerhalf_s *dev, uint32_t arr); @@ -237,10 +237,10 @@ static int pwm_soft_update(struct pwm_lowerhalf_s *dev); static int pwm_frequency_update(struct pwm_lowerhalf_s *dev, uint32_t frequency); static int pwm_timer_enable(struct pwm_lowerhalf_s *dev, bool state); -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) static int pwm_deadtime_update(struct pwm_lowerhalf_s *dev, uint8_t dt); #endif -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index); #endif @@ -273,7 +273,7 @@ static const struct pwm_ops_s g_pwmops = .ioctl = pwm_ioctl, }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static const struct stm32_pwm_ops_s g_llpwmops = { .configure = pwm_configure, @@ -296,16 +296,16 @@ static const struct stm32_pwm_ops_s g_llpwmops = }; #endif -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM static struct stm32_pwmchan_s g_pwm1channels[] = { /* TIM1 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 +#ifdef CONFIG_STM32_TIM1_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM1_CH1MODE, + .mode = CONFIG_STM32_TIM1_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -320,114 +320,114 @@ static struct stm32_pwmchan_s g_pwm1channels[] = #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1POL, - .idle = CONFIG_STM32L4_TIM1_CH1IDLE, + .pol = CONFIG_STM32_TIM1_CH1POL, + .idle = CONFIG_STM32_TIM1_CH1IDLE, .pincfg = PWM_TIM1_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH1NOUT +#ifdef CONFIG_STM32_TIM1_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH1NPOL, - .idle = CONFIG_STM32L4_TIM1_CH1NIDLE, + .pol = CONFIG_STM32_TIM1_CH1NPOL, + .idle = CONFIG_STM32_TIM1_CH1NIDLE, .pincfg = PWM_TIM1_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 +#ifdef CONFIG_STM32_TIM1_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM1_CH2MODE, -#ifdef CONFIG_STM32L4_TIM1_CH2OUT + .mode = CONFIG_STM32_TIM1_CH2MODE, +#ifdef CONFIG_STM32_TIM1_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2POL, - .idle = CONFIG_STM32L4_TIM1_CH2IDLE, + .pol = CONFIG_STM32_TIM1_CH2POL, + .idle = CONFIG_STM32_TIM1_CH2IDLE, .pincfg = PWM_TIM1_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH2NOUT +#ifdef CONFIG_STM32_TIM1_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH2NPOL, - .idle = CONFIG_STM32L4_TIM1_CH2NIDLE, + .pol = CONFIG_STM32_TIM1_CH2NPOL, + .idle = CONFIG_STM32_TIM1_CH2NIDLE, .pincfg = PWM_TIM1_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 +#ifdef CONFIG_STM32_TIM1_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM1_CH3MODE, -#ifdef CONFIG_STM32L4_TIM1_CH3OUT + .mode = CONFIG_STM32_TIM1_CH3MODE, +#ifdef CONFIG_STM32_TIM1_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3POL, - .idle = CONFIG_STM32L4_TIM1_CH3IDLE, + .pol = CONFIG_STM32_TIM1_CH3POL, + .idle = CONFIG_STM32_TIM1_CH3IDLE, .pincfg = PWM_TIM1_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM1_CH3NOUT +#ifdef CONFIG_STM32_TIM1_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH3NPOL, - .idle = CONFIG_STM32L4_TIM1_CH3NIDLE, + .pol = CONFIG_STM32_TIM1_CH3NPOL, + .idle = CONFIG_STM32_TIM1_CH3NIDLE, .pincfg = PWM_TIM1_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 +#ifdef CONFIG_STM32_TIM1_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM1_CH4MODE, -#ifdef CONFIG_STM32L4_TIM1_CH4OUT + .mode = CONFIG_STM32_TIM1_CH4MODE, +#ifdef CONFIG_STM32_TIM1_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH4POL, - .idle = CONFIG_STM32L4_TIM1_CH4IDLE, + .pol = CONFIG_STM32_TIM1_CH4POL, + .idle = CONFIG_STM32_TIM1_CH4IDLE, .pincfg = PWM_TIM1_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL5 +#ifdef CONFIG_STM32_TIM1_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM1_CH5MODE, -#ifdef CONFIG_STM32L4_TIM1_CH5OUT + .mode = CONFIG_STM32_TIM1_CH5MODE, +#ifdef CONFIG_STM32_TIM1_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH5POL, - .idle = CONFIG_STM32L4_TIM1_CH5IDLE, + .pol = CONFIG_STM32_TIM1_CH5POL, + .idle = CONFIG_STM32_TIM1_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL6 +#ifdef CONFIG_STM32_TIM1_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM1_CH6MODE, -#ifdef CONFIG_STM32L4_TIM1_CH6OUT + .mode = CONFIG_STM32_TIM1_CH6MODE, +#ifdef CONFIG_STM32_TIM1_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM1_CH6POL, - .idle = CONFIG_STM32L4_TIM1_CH6IDLE, + .pol = CONFIG_STM32_TIM1_CH6POL, + .idle = CONFIG_STM32_TIM1_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -438,18 +438,18 @@ static struct stm32_pwmchan_s g_pwm1channels[] = static struct stm32_pwmtimer_s g_pwm1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, .chan_num = PWM_TIM1_NCHANNELS, .channels = g_pwm1channels, .timtype = TIMTYPE_TIM1, - .mode = CONFIG_STM32L4_TIM1_MODE, - .lock = CONFIG_STM32L4_TIM1_LOCK, - .t_dts = CONFIG_STM32L4_TIM1_TDTS, + .mode = CONFIG_STM32_TIM1_MODE, + .lock = CONFIG_STM32_TIM1_LOCK, + .t_dts = CONFIG_STM32_TIM1_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM1_DEADTIME, + .deadtime = CONFIG_STM32_TIM1_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM1_TRGO) .trgo = STM32_TIM1_TRGO, @@ -457,72 +457,72 @@ static struct stm32_pwmtimer_s g_pwm1dev = .base = STM32_TIM1_BASE, .pclk = STM32_APB2_TIM1_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM1_PWM */ +#endif /* CONFIG_STM32_TIM1_PWM */ -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM static struct stm32_pwmchan_s g_pwm2channels[] = { /* TIM2 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 +#ifdef CONFIG_STM32_TIM2_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM2_CH1MODE, -#ifdef CONFIG_STM32L4_TIM2_CH1OUT + .mode = CONFIG_STM32_TIM2_CH1MODE, +#ifdef CONFIG_STM32_TIM2_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH1POL, - .idle = CONFIG_STM32L4_TIM2_CH1IDLE, + .pol = CONFIG_STM32_TIM2_CH1POL, + .idle = CONFIG_STM32_TIM2_CH1IDLE, .pincfg = PWM_TIM2_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 +#ifdef CONFIG_STM32_TIM2_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM2_CH2MODE, -#ifdef CONFIG_STM32L4_TIM2_CH2OUT + .mode = CONFIG_STM32_TIM2_CH2MODE, +#ifdef CONFIG_STM32_TIM2_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH2POL, - .idle = CONFIG_STM32L4_TIM2_CH2IDLE, + .pol = CONFIG_STM32_TIM2_CH2POL, + .idle = CONFIG_STM32_TIM2_CH2IDLE, .pincfg = PWM_TIM2_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 +#ifdef CONFIG_STM32_TIM2_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM2_CH3MODE, -#ifdef CONFIG_STM32L4_TIM2_CH3OUT + .mode = CONFIG_STM32_TIM2_CH3MODE, +#ifdef CONFIG_STM32_TIM2_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH3POL, - .idle = CONFIG_STM32L4_TIM2_CH3IDLE, + .pol = CONFIG_STM32_TIM2_CH3POL, + .idle = CONFIG_STM32_TIM2_CH3IDLE, .pincfg = PWM_TIM2_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 +#ifdef CONFIG_STM32_TIM2_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM2_CH4MODE, -#ifdef CONFIG_STM32L4_TIM2_CH4OUT + .mode = CONFIG_STM32_TIM2_CH4MODE, +#ifdef CONFIG_STM32_TIM2_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM2_CH4POL, - .idle = CONFIG_STM32L4_TIM2_CH4IDLE, + .pol = CONFIG_STM32_TIM2_CH4POL, + .idle = CONFIG_STM32_TIM2_CH4IDLE, .pincfg = PWM_TIM2_CH4CFG, } #endif @@ -534,14 +534,14 @@ static struct stm32_pwmchan_s g_pwm2channels[] = static struct stm32_pwmtimer_s g_pwm2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, .chan_num = PWM_TIM2_NCHANNELS, .channels = g_pwm2channels, .timtype = TIMTYPE_TIM2, - .mode = CONFIG_STM32L4_TIM2_MODE, + .mode = CONFIG_STM32_TIM2_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -554,72 +554,72 @@ static struct stm32_pwmtimer_s g_pwm2dev = .pclk = STM32_APB1_TIM2_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM2_PWM */ +#endif /* CONFIG_STM32_TIM2_PWM */ -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM static struct stm32_pwmchan_s g_pwm3channels[] = { /* TIM3 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 +#ifdef CONFIG_STM32_TIM3_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM3_CH1MODE, -#ifdef CONFIG_STM32L4_TIM3_CH1OUT + .mode = CONFIG_STM32_TIM3_CH1MODE, +#ifdef CONFIG_STM32_TIM3_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH1POL, - .idle = CONFIG_STM32L4_TIM3_CH1IDLE, + .pol = CONFIG_STM32_TIM3_CH1POL, + .idle = CONFIG_STM32_TIM3_CH1IDLE, .pincfg = PWM_TIM3_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 +#ifdef CONFIG_STM32_TIM3_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM3_CH2MODE, -#ifdef CONFIG_STM32L4_TIM3_CH2OUT + .mode = CONFIG_STM32_TIM3_CH2MODE, +#ifdef CONFIG_STM32_TIM3_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH2POL, - .idle = CONFIG_STM32L4_TIM3_CH2IDLE, + .pol = CONFIG_STM32_TIM3_CH2POL, + .idle = CONFIG_STM32_TIM3_CH2IDLE, .pincfg = PWM_TIM3_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 +#ifdef CONFIG_STM32_TIM3_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM3_CH3MODE, -#ifdef CONFIG_STM32L4_TIM3_CH3OUT + .mode = CONFIG_STM32_TIM3_CH3MODE, +#ifdef CONFIG_STM32_TIM3_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH3POL, - .idle = CONFIG_STM32L4_TIM3_CH3IDLE, + .pol = CONFIG_STM32_TIM3_CH3POL, + .idle = CONFIG_STM32_TIM3_CH3IDLE, .pincfg = PWM_TIM3_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 +#ifdef CONFIG_STM32_TIM3_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM3_CH4MODE, -#ifdef CONFIG_STM32L4_TIM3_CH4OUT + .mode = CONFIG_STM32_TIM3_CH4MODE, +#ifdef CONFIG_STM32_TIM3_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM3_CH4POL, - .idle = CONFIG_STM32L4_TIM3_CH4IDLE, + .pol = CONFIG_STM32_TIM3_CH4POL, + .idle = CONFIG_STM32_TIM3_CH4IDLE, .pincfg = PWM_TIM3_CH4CFG, } #endif @@ -631,14 +631,14 @@ static struct stm32_pwmchan_s g_pwm3channels[] = static struct stm32_pwmtimer_s g_pwm3dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 3, .chan_num = PWM_TIM3_NCHANNELS, .channels = g_pwm3channels, .timtype = TIMTYPE_TIM3, - .mode = CONFIG_STM32L4_TIM3_MODE, + .mode = CONFIG_STM32_TIM3_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -650,72 +650,72 @@ static struct stm32_pwmtimer_s g_pwm3dev = .base = STM32_TIM3_BASE, .pclk = STM32_APB1_TIM3_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM3_PWM */ +#endif /* CONFIG_STM32_TIM3_PWM */ -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM static struct stm32_pwmchan_s g_pwm4channels[] = { /* TIM4 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 +#ifdef CONFIG_STM32_TIM4_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM4_CH1MODE, -#ifdef CONFIG_STM32L4_TIM4_CH1OUT + .mode = CONFIG_STM32_TIM4_CH1MODE, +#ifdef CONFIG_STM32_TIM4_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH1POL, - .idle = CONFIG_STM32L4_TIM4_CH1IDLE, + .pol = CONFIG_STM32_TIM4_CH1POL, + .idle = CONFIG_STM32_TIM4_CH1IDLE, .pincfg = PWM_TIM4_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 +#ifdef CONFIG_STM32_TIM4_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM4_CH2MODE, -#ifdef CONFIG_STM32L4_TIM4_CH2OUT + .mode = CONFIG_STM32_TIM4_CH2MODE, +#ifdef CONFIG_STM32_TIM4_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH2POL, - .idle = CONFIG_STM32L4_TIM4_CH2IDLE, + .pol = CONFIG_STM32_TIM4_CH2POL, + .idle = CONFIG_STM32_TIM4_CH2IDLE, .pincfg = PWM_TIM4_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 +#ifdef CONFIG_STM32_TIM4_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM4_CH3MODE, -#ifdef CONFIG_STM32L4_TIM4_CH3OUT + .mode = CONFIG_STM32_TIM4_CH3MODE, +#ifdef CONFIG_STM32_TIM4_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH3POL, - .idle = CONFIG_STM32L4_TIM4_CH3IDLE, + .pol = CONFIG_STM32_TIM4_CH3POL, + .idle = CONFIG_STM32_TIM4_CH3IDLE, .pincfg = PWM_TIM4_CH3CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 +#ifdef CONFIG_STM32_TIM4_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM4_CH4MODE, -#ifdef CONFIG_STM32L4_TIM4_CH4OUT + .mode = CONFIG_STM32_TIM4_CH4MODE, +#ifdef CONFIG_STM32_TIM4_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM4_CH4POL, - .idle = CONFIG_STM32L4_TIM4_CH4IDLE, + .pol = CONFIG_STM32_TIM4_CH4POL, + .idle = CONFIG_STM32_TIM4_CH4IDLE, .pincfg = PWM_TIM4_CH4CFG, } #endif @@ -727,14 +727,14 @@ static struct stm32_pwmchan_s g_pwm4channels[] = static struct stm32_pwmtimer_s g_pwm4dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 4, .chan_num = PWM_TIM4_NCHANNELS, .channels = g_pwm4channels, .timtype = TIMTYPE_TIM4, - .mode = CONFIG_STM32L4_TIM4_MODE, + .mode = CONFIG_STM32_TIM4_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -746,71 +746,71 @@ static struct stm32_pwmtimer_s g_pwm4dev = .base = STM32_TIM4_BASE, .pclk = STM32_APB1_TIM4_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM4_PWM */ +#endif /* CONFIG_STM32_TIM4_PWM */ -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM static struct stm32_pwmchan_s g_pwm5channels[] = { /* TIM5 has 4 channels */ -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 +#ifdef CONFIG_STM32_TIM5_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM5_CH1MODE, -#ifdef CONFIG_STM32L4_TIM5_CH1OUT + .mode = CONFIG_STM32_TIM5_CH1MODE, +#ifdef CONFIG_STM32_TIM5_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH1POL, - .idle = CONFIG_STM32L4_TIM5_CH1IDLE, + .pol = CONFIG_STM32_TIM5_CH1POL, + .idle = CONFIG_STM32_TIM5_CH1IDLE, .pincfg = PWM_TIM5_CH1CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 +#ifdef CONFIG_STM32_TIM5_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM5_CH2MODE, -#ifdef CONFIG_STM32L4_TIM5_CH2OUT + .mode = CONFIG_STM32_TIM5_CH2MODE, +#ifdef CONFIG_STM32_TIM5_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH2POL, - .idle = CONFIG_STM32L4_TIM5_CH2IDLE, + .pol = CONFIG_STM32_TIM5_CH2POL, + .idle = CONFIG_STM32_TIM5_CH2IDLE, .pincfg = PWM_TIM5_CH2CFG, } #endif /* No complementary outputs */ }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 +#ifdef CONFIG_STM32_TIM5_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM5_CH3MODE, -#ifdef CONFIG_STM32L4_TIM5_CH3OUT + .mode = CONFIG_STM32_TIM5_CH3MODE, +#ifdef CONFIG_STM32_TIM5_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH3POL, - .idle = CONFIG_STM32L4_TIM5_CH3IDLE, + .pol = CONFIG_STM32_TIM5_CH3POL, + .idle = CONFIG_STM32_TIM5_CH3IDLE, .pincfg = PWM_TIM5_CH3CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 +#ifdef CONFIG_STM32_TIM5_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM5_CH4MODE, -#ifdef CONFIG_STM32L4_TIM5_CH4OUT + .mode = CONFIG_STM32_TIM5_CH4MODE, +#ifdef CONFIG_STM32_TIM5_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM5_CH4POL, - .idle = CONFIG_STM32L4_TIM5_CH4IDLE, + .pol = CONFIG_STM32_TIM5_CH4POL, + .idle = CONFIG_STM32_TIM5_CH4IDLE, .pincfg = PWM_TIM5_CH4CFG, } #endif @@ -821,14 +821,14 @@ static struct stm32_pwmchan_s g_pwm5channels[] = static struct stm32_pwmtimer_s g_pwm5dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 5, .chan_num = PWM_TIM5_NCHANNELS, .channels = g_pwm5channels, .timtype = TIMTYPE_TIM5, - .mode = CONFIG_STM32L4_TIM5_MODE, + .mode = CONFIG_STM32_TIM5_MODE, .lock = 0, /* No lock */ .t_dts = 0, /* No t_dts */ #ifdef HAVE_PWM_COMPLEMENTARY @@ -840,18 +840,18 @@ static struct stm32_pwmtimer_s g_pwm5dev = .base = STM32_TIM5_BASE, .pclk = STM32_APB1_TIM5_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM5_PWM */ +#endif /* CONFIG_STM32_TIM5_PWM */ -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM static struct stm32_pwmchan_s g_pwm8channels[] = { /* TIM8 has 4 channels, 4 complementary */ -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 +#ifdef CONFIG_STM32_TIM8_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM8_CH1MODE, + .mode = CONFIG_STM32_TIM8_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -866,114 +866,114 @@ static struct stm32_pwmchan_s g_pwm8channels[] = #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1POL, - .idle = CONFIG_STM32L4_TIM8_CH1IDLE, + .pol = CONFIG_STM32_TIM8_CH1POL, + .idle = CONFIG_STM32_TIM8_CH1IDLE, .pincfg = PWM_TIM8_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH1NOUT +#ifdef CONFIG_STM32_TIM8_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH1NPOL, - .idle = CONFIG_STM32L4_TIM8_CH1NIDLE, + .pol = CONFIG_STM32_TIM8_CH1NPOL, + .idle = CONFIG_STM32_TIM8_CH1NIDLE, .pincfg = PWM_TIM8_CH1NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 +#ifdef CONFIG_STM32_TIM8_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM8_CH2MODE, -#ifdef CONFIG_STM32L4_TIM8_CH2OUT + .mode = CONFIG_STM32_TIM8_CH2MODE, +#ifdef CONFIG_STM32_TIM8_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2POL, - .idle = CONFIG_STM32L4_TIM8_CH2IDLE, + .pol = CONFIG_STM32_TIM8_CH2POL, + .idle = CONFIG_STM32_TIM8_CH2IDLE, .pincfg = PWM_TIM8_CH2CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH2NOUT +#ifdef CONFIG_STM32_TIM8_CH2NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH2NPOL, - .idle = CONFIG_STM32L4_TIM8_CH2NIDLE, + .pol = CONFIG_STM32_TIM8_CH2NPOL, + .idle = CONFIG_STM32_TIM8_CH2NIDLE, .pincfg = PWM_TIM8_CH2NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 +#ifdef CONFIG_STM32_TIM8_CHANNEL3 { .channel = 3, - .mode = CONFIG_STM32L4_TIM8_CH3MODE, -#ifdef CONFIG_STM32L4_TIM8_CH3OUT + .mode = CONFIG_STM32_TIM8_CH3MODE, +#ifdef CONFIG_STM32_TIM8_CH3OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3POL, - .idle = CONFIG_STM32L4_TIM8_CH3IDLE, + .pol = CONFIG_STM32_TIM8_CH3POL, + .idle = CONFIG_STM32_TIM8_CH3IDLE, .pincfg = PWM_TIM8_CH3CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM8_CH3NOUT +#ifdef CONFIG_STM32_TIM8_CH3NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH3NPOL, - .idle = CONFIG_STM32L4_TIM8_CH3NIDLE, + .pol = CONFIG_STM32_TIM8_CH3NPOL, + .idle = CONFIG_STM32_TIM8_CH3NIDLE, .pincfg = PWM_TIM8_CH3NCFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 +#ifdef CONFIG_STM32_TIM8_CHANNEL4 { .channel = 4, - .mode = CONFIG_STM32L4_TIM8_CH4MODE, -#ifdef CONFIG_STM32L4_TIM8_CH4OUT + .mode = CONFIG_STM32_TIM8_CH4MODE, +#ifdef CONFIG_STM32_TIM8_CH4OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH4POL, - .idle = CONFIG_STM32L4_TIM8_CH4IDLE, + .pol = CONFIG_STM32_TIM8_CH4POL, + .idle = CONFIG_STM32_TIM8_CH4IDLE, .pincfg = PWM_TIM8_CH4CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL5 +#ifdef CONFIG_STM32_TIM8_CHANNEL5 { .channel = 5, - .mode = CONFIG_STM32L4_TIM8_CH5MODE, -#ifdef CONFIG_STM32L4_TIM8_CH5OUT + .mode = CONFIG_STM32_TIM8_CH5MODE, +#ifdef CONFIG_STM32_TIM8_CH5OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH5POL, - .idle = CONFIG_STM32L4_TIM8_CH5IDLE, + .pol = CONFIG_STM32_TIM8_CH5POL, + .idle = CONFIG_STM32_TIM8_CH5IDLE, .pincfg = 0, /* Not available externally */ } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL6 +#ifdef CONFIG_STM32_TIM8_CHANNEL6 { .channel = 6, - .mode = CONFIG_STM32L4_TIM8_CH6MODE, -#ifdef CONFIG_STM32L4_TIM8_CH6OUT + .mode = CONFIG_STM32_TIM8_CH6MODE, +#ifdef CONFIG_STM32_TIM8_CH6OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM8_CH6POL, - .idle = CONFIG_STM32L4_TIM8_CH6IDLE, + .pol = CONFIG_STM32_TIM8_CH6POL, + .idle = CONFIG_STM32_TIM8_CH6IDLE, .pincfg = 0, /* Not available externally */ } #endif @@ -984,18 +984,18 @@ static struct stm32_pwmchan_s g_pwm8channels[] = static struct stm32_pwmtimer_s g_pwm8dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 8, .chan_num = PWM_TIM8_NCHANNELS, .channels = g_pwm8channels, .timtype = TIMTYPE_TIM8, - .mode = CONFIG_STM32L4_TIM8_MODE, - .lock = CONFIG_STM32L4_TIM8_LOCK, - .t_dts = CONFIG_STM32L4_TIM8_TDTS, + .mode = CONFIG_STM32_TIM8_MODE, + .lock = CONFIG_STM32_TIM8_LOCK, + .t_dts = CONFIG_STM32_TIM8_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM8_DEADTIME, + .deadtime = CONFIG_STM32_TIM8_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM8_TRGO) .trgo = STM32_TIM8_TRGO, @@ -1003,18 +1003,18 @@ static struct stm32_pwmtimer_s g_pwm8dev = .base = STM32_TIM8_BASE, .pclk = STM32_APB2_TIM8_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM8_PWM */ +#endif /* CONFIG_STM32_TIM8_PWM */ -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM static struct stm32_pwmchan_s g_pwm15channels[] = { /* TIM15 has 2 channels, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 +#ifdef CONFIG_STM32_TIM15_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM15_CH1MODE, + .mode = CONFIG_STM32_TIM15_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1025,36 +1025,36 @@ static struct stm32_pwmchan_s g_pwm15channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1POL, - .idle = CONFIG_STM32L4_TIM15_CH1IDLE, + .pol = CONFIG_STM32_TIM15_CH1POL, + .idle = CONFIG_STM32_TIM15_CH1IDLE, .pincfg = PWM_TIM15_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM15_CH1NOUT +#ifdef CONFIG_STM32_TIM15_CH1NOUT .out2 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH1NPOL, - .idle = CONFIG_STM32L4_TIM15_CH1NIDLE, + .pol = CONFIG_STM32_TIM15_CH1NPOL, + .idle = CONFIG_STM32_TIM15_CH1NIDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif }, #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 +#ifdef CONFIG_STM32_TIM15_CHANNEL2 { .channel = 2, - .mode = CONFIG_STM32L4_TIM15_CH2MODE, -#ifdef CONFIG_STM32L4_TIM15_CH2OUT + .mode = CONFIG_STM32_TIM15_CH2MODE, +#ifdef CONFIG_STM32_TIM15_CH2OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM15_CH2POL, - .idle = CONFIG_STM32L4_TIM15_CH2IDLE, + .pol = CONFIG_STM32_TIM15_CH2POL, + .idle = CONFIG_STM32_TIM15_CH2IDLE, .pincfg = PWM_TIM15_CH2CFG, } #endif @@ -1066,7 +1066,7 @@ static struct stm32_pwmchan_s g_pwm15channels[] = static struct stm32_pwmtimer_s g_pwm15dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 15, @@ -1074,10 +1074,10 @@ static struct stm32_pwmtimer_s g_pwm15dev = .channels = g_pwm15channels, .timtype = TIMTYPE_TIM15, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM15_LOCK, - .t_dts = CONFIG_STM32L4_TIM15_TDTS, + .lock = CONFIG_STM32_TIM15_LOCK, + .t_dts = CONFIG_STM32_TIM15_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM15_DEADTIME, + .deadtime = CONFIG_STM32_TIM15_DEADTIME, #endif #if defined(HAVE_TRGO) && defined(STM32_TIM15_TRGO) .trgo = STM32_TIM15_TRGO, @@ -1085,18 +1085,18 @@ static struct stm32_pwmtimer_s g_pwm15dev = .base = STM32_TIM15_BASE, .pclk = STM32_APB2_TIM15_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM15_PWM */ +#endif /* CONFIG_STM32_TIM15_PWM */ -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM static struct stm32_pwmchan_s g_pwm16channels[] = { /* TIM16 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 +#ifdef CONFIG_STM32_TIM16_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM16_CH1MODE, + .mode = CONFIG_STM32_TIM16_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1107,16 +1107,16 @@ static struct stm32_pwmchan_s g_pwm16channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM16_CH1POL, - .idle = CONFIG_STM32L4_TIM16_CH1IDLE, + .pol = CONFIG_STM32_TIM16_CH1POL, + .idle = CONFIG_STM32_TIM16_CH1IDLE, .pincfg = PWM_TIM16_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM16_CH1NOUT +#ifdef CONFIG_STM32_TIM16_CH1NOUT .out2 = { .in_use = 1, @@ -1132,7 +1132,7 @@ static struct stm32_pwmchan_s g_pwm16channels[] = static struct stm32_pwmtimer_s g_pwm16dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 16, @@ -1140,10 +1140,10 @@ static struct stm32_pwmtimer_s g_pwm16dev = .channels = g_pwm16channels, .timtype = TIMTYPE_TIM16, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM16_LOCK, - .t_dts = CONFIG_STM32L4_TIM16_TDTS, + .lock = CONFIG_STM32_TIM16_LOCK, + .t_dts = CONFIG_STM32_TIM16_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM16_DEADTIME, + .deadtime = CONFIG_STM32_TIM16_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM16 */ @@ -1151,18 +1151,18 @@ static struct stm32_pwmtimer_s g_pwm16dev = .base = STM32_TIM16_BASE, .pclk = STM32_APB2_TIM16_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM16_PWM */ +#endif /* CONFIG_STM32_TIM16_PWM */ -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM static struct stm32_pwmchan_s g_pwm17channels[] = { /* TIM17 has 1 channel, 1 complementary */ -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 +#ifdef CONFIG_STM32_TIM17_CHANNEL1 { .channel = 1, - .mode = CONFIG_STM32L4_TIM17_CH1MODE, + .mode = CONFIG_STM32_TIM17_CH1MODE, #ifdef HAVE_BREAK .brk = { @@ -1173,16 +1173,16 @@ static struct stm32_pwmchan_s g_pwm17channels[] = /* No BREAK2 */ }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CH1OUT .out1 = { .in_use = 1, - .pol = CONFIG_STM32L4_TIM17_CH1POL, - .idle = CONFIG_STM32L4_TIM17_CH1IDLE, + .pol = CONFIG_STM32_TIM17_CH1POL, + .idle = CONFIG_STM32_TIM17_CH1IDLE, .pincfg = PWM_TIM17_CH1CFG, }, #endif -#ifdef CONFIG_STM32L4_TIM17_CH1NOUT +#ifdef CONFIG_STM32_TIM17_CH1NOUT .out2 = { .in_use = 1, @@ -1198,7 +1198,7 @@ static struct stm32_pwmchan_s g_pwm17channels[] = static struct stm32_pwmtimer_s g_pwm17dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 17, @@ -1206,10 +1206,10 @@ static struct stm32_pwmtimer_s g_pwm17dev = .channels = g_pwm17channels, .timtype = TIMTYPE_TIM17, .mode = STM32_TIMMODE_COUNTUP, - .lock = CONFIG_STM32L4_TIM17_LOCK, - .t_dts = CONFIG_STM32L4_TIM17_TDTS, + .lock = CONFIG_STM32_TIM17_LOCK, + .t_dts = CONFIG_STM32_TIM17_TDTS, #ifdef HAVE_PWM_COMPLEMENTARY - .deadtime = CONFIG_STM32L4_TIM17_DEADTIME, + .deadtime = CONFIG_STM32_TIM17_DEADTIME, #endif #if defined(HAVE_TRGO) .trgo = 0, /* TRGO not supported for TIM17 */ @@ -1217,19 +1217,19 @@ static struct stm32_pwmtimer_s g_pwm17dev = .base = STM32_TIM17_BASE, .pclk = STM32_APB2_TIM17_CLKIN, }; -#endif /* CONFIG_STM32L4_TIM17_PWM */ +#endif /* CONFIG_STM32_TIM17_PWM */ -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM static struct stm32_pwmchan_s g_pwmlp1channels[] = { /* LPTIM1 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CH1OUT .out1 = { .in_use = 1, @@ -1246,7 +1246,7 @@ static struct stm32_pwmchan_s g_pwmlp1channels[] = static struct stm32_pwmtimer_s g_pwmlp1dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 1, @@ -1263,29 +1263,29 @@ static struct stm32_pwmtimer_s g_pwmlp1dev = .trgo = 0, /* TRGO not supported for LPTIM1 */ #endif .base = STM32_LPTIM1_BASE, -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) .pclk = STM32_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) .pclk = STM32_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) .pclk = STM32_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM1_PWM */ +#endif /* CONFIG_STM32_LPTIM1_PWM */ -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM static struct stm32_pwmchan_s g_pwmlp2channels[] = { /* LPTIM2 has 1 channel */ -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 { .channel = 1, .mode = 0, -#ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CH1OUT .out1 = { .in_use = 1, @@ -1302,7 +1302,7 @@ static struct stm32_pwmchan_s g_pwmlp2channels[] = static struct stm32_pwmtimer_s g_pwmlp2dev = { .ops = &g_pwmops, -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS .llops = &g_llpwmops, #endif .timid = 2, @@ -1319,17 +1319,17 @@ static struct stm32_pwmtimer_s g_pwmlp2dev = .trgo = 0, /* TRGO not supported for LPTIM2 */ #endif .base = STM32_LPTIM2_BASE, -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) .pclk = STM32_PCLK1_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) .pclk = STM32_LSE_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) .pclk = STM32_LSI_FREQUENCY, -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) .pclk = STM32_HSI_FREQUENCY, #endif }; -#endif /* CONFIG_STM32L4_LPTIM2_PWM */ +#endif /* CONFIG_STM32_LPTIM2_PWM */ /**************************************************************************** * Private Functions @@ -1493,7 +1493,7 @@ static void pwm_dumpregs(struct pwm_lowerhalf_s *dev, pwm_getreg(priv, STM32_GTIM_CCR2_OFFSET), pwm_getreg(priv, STM32_GTIM_CCR3_OFFSET), pwm_getreg(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM8_PWM) if (priv->timtype == TIMTYPE_ADVANCED) { pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -1601,7 +1601,7 @@ static int pwm_ccr_update(struct pwm_lowerhalf_s *dev, uint8_t index, * Name: pwm_ccr_get ****************************************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) { struct stm32_pwmtimer_s *priv = (struct stm32_pwmtimer_s *)dev; @@ -1656,7 +1656,7 @@ static uint32_t pwm_ccr_get(struct pwm_lowerhalf_s *dev, uint8_t index) return pwm_getreg(priv, offset); } -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Name: pwm_arr_update @@ -2486,7 +2486,7 @@ static int pwm_outputs_enable(struct pwm_lowerhalf_s *dev, return OK; } -#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32L4_PWM_LL_OPS) +#if defined(HAVE_PWM_COMPLEMENTARY) && defined(CONFIG_STM32_PWM_LL_OPS) /**************************************************************************** * Name: pwm_deadtime_update @@ -3083,7 +3083,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: { regaddr = STM32_RCC_APB2ENR; @@ -3092,7 +3092,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: { regaddr = STM32_RCC_APB1ENR1; @@ -3101,7 +3101,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: { regaddr = STM32_RCC_APB1ENR1; @@ -3110,7 +3110,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: { regaddr = STM32_RCC_APB1ENR1; @@ -3119,7 +3119,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: { regaddr = STM32_RCC_APB1ENR1; @@ -3128,7 +3128,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: { regaddr = STM32_RCC_APB2ENR; @@ -3137,7 +3137,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: { regaddr = STM32_RCC_APB2ENR; @@ -3146,7 +3146,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: { regaddr = STM32_RCC_APB2ENR; @@ -3155,7 +3155,7 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: { regaddr = STM32_RCC_APB2ENR; @@ -3190,10 +3190,10 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: { -#if defined(CONFIG_STM32L4_LPTIM1_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM1_CLK_APB1) /* Enable APB clock for LPTIM1 */ if (on) @@ -3208,11 +3208,11 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } clock_bits = RCC_CCIPR_LPTIM1SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM1SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM1_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM1SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM1_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM1_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM1SEL_HSI; #endif /* Choose which clock will be used for LPTIM1 */ @@ -3223,10 +3223,10 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: { -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) /* Enable APB clock for LPTIM2 */ if (on) @@ -3241,11 +3241,11 @@ static int pwm_setapbclock(struct stm32_pwmtimer_s *priv, } clock_bits = RCC_CCIPR_LPTIM2SEL_PCLK; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSI) clock_bits = RCC_CCIPR_LPTIM2SEL_LSI; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_LSE) +#elif defined(CONFIG_STM32_LPTIM2_CLK_LSE) clock_bits = RCC_CCIPR_LPTIM2SEL_LSE; -#elif defined(CONFIG_STM32L4_LPTIM2_CLK_HSI) +#elif defined(CONFIG_STM32_LPTIM2_CLK_HSI) clock_bits = RCC_CCIPR_LPTIM2SEL_HSI; #endif /* Choose which clock will be used for LPTIM2 */ @@ -3541,49 +3541,49 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM16RST; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM17RST; @@ -3597,13 +3597,13 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) { switch (priv->timid) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_LPTIM1RST; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: regaddr = STM32_RCC_APB1RSTR2; resetbit = RCC_APB1RSTR2_LPTIM2RST; @@ -3705,7 +3705,7 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1_PWM +#ifdef CONFIG_STM32_TIM1_PWM case 1: lower = &g_pwm1dev; @@ -3714,31 +3714,31 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM2_PWM +#ifdef CONFIG_STM32_TIM2_PWM case 2: lower = &g_pwm2dev; break; #endif -#ifdef CONFIG_STM32L4_TIM3_PWM +#ifdef CONFIG_STM32_TIM3_PWM case 3: lower = &g_pwm3dev; break; #endif -#ifdef CONFIG_STM32L4_TIM4_PWM +#ifdef CONFIG_STM32_TIM4_PWM case 4: lower = &g_pwm4dev; break; #endif -#ifdef CONFIG_STM32L4_TIM5_PWM +#ifdef CONFIG_STM32_TIM5_PWM case 5: lower = &g_pwm5dev; break; #endif -#ifdef CONFIG_STM32L4_TIM8_PWM +#ifdef CONFIG_STM32_TIM8_PWM case 8: lower = &g_pwm8dev; @@ -3747,19 +3747,19 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer) break; #endif -#ifdef CONFIG_STM32L4_TIM15_PWM +#ifdef CONFIG_STM32_TIM15_PWM case 15: lower = &g_pwm15dev; break; #endif -#ifdef CONFIG_STM32L4_TIM16_PWM +#ifdef CONFIG_STM32_TIM16_PWM case 16: lower = &g_pwm16dev; break; #endif -#ifdef CONFIG_STM32L4_TIM17_PWM +#ifdef CONFIG_STM32_TIM17_PWM case 17: lower = &g_pwm17dev; break; @@ -3799,13 +3799,13 @@ struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_LPTIM1_PWM +#ifdef CONFIG_STM32_LPTIM1_PWM case 1: lower = &g_pwmlp1dev; break; #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM +#ifdef CONFIG_STM32_LPTIM2_PWM case 2: lower = &g_pwmlp2dev; break; diff --git a/arch/arm/src/stm32l4/stm32l4_pwm.h b/arch/arm/src/stm32l4/stm32l4_pwm.h index 66d75febf09..26e52e0dc61 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwm.h +++ b/arch/arm/src/stm32l4/stm32l4_pwm.h @@ -50,43 +50,43 @@ /* Timer devices may be used for different purposes. One special purpose is * to generate modulated outputs for such things as motor control. If - * CONFIG_STM32L4_TIMn is defined then the CONFIG_STM32L4_TIMn_PWM must also + * CONFIG_STM32_TIMn is defined then the CONFIG_STM32_TIMn_PWM must also * be defined to indicate that timer "n" is intended to be used for pulsed * output signal generation. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_PWM +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_PWM #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_PWM +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_PWM #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_PWM +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_PWM #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_PWM +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_PWM #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_PWM +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_PWM #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_PWM +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_PWM #endif -#ifndef CONFIG_STM32L4_TIM15 -# undef CONFIG_STM32L4_TIM15_PWM +#ifndef CONFIG_STM32_TIM15 +# undef CONFIG_STM32_TIM15_PWM #endif -#ifndef CONFIG_STM32L4_TIM16 -# undef CONFIG_STM32L4_TIM16_PWM +#ifndef CONFIG_STM32_TIM16 +# undef CONFIG_STM32_TIM16_PWM #endif -#ifndef CONFIG_STM32L4_TIM17 -# undef CONFIG_STM32L4_TIM17_PWM +#ifndef CONFIG_STM32_TIM17 +# undef CONFIG_STM32_TIM17_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM1 -# undef CONFIG_STM32L4_LPTIM1_PWM +#ifndef CONFIG_STM32_LPTIM1 +# undef CONFIG_STM32_LPTIM1_PWM #endif -#ifndef CONFIG_STM32L4_LPTIM2 -# undef CONFIG_STM32L4_LPTIM2_PWM +#ifndef CONFIG_STM32_LPTIM2 +# undef CONFIG_STM32_LPTIM2_PWM #endif /* The basic timers (timer 6 and 7) are not capable of generating output @@ -98,24 +98,24 @@ /* Check if PWM support for any channel is enabled. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined(CONFIG_STM32L4_TIM2_PWM) || \ - defined(CONFIG_STM32L4_TIM3_PWM) || defined(CONFIG_STM32L4_TIM4_PWM) || \ - defined(CONFIG_STM32L4_TIM5_PWM) || defined(CONFIG_STM32L4_TIM8_PWM) || \ - defined(CONFIG_STM32L4_TIM15_PWM) || defined(CONFIG_STM32L4_TIM16_PWM) || \ - defined(CONFIG_STM32L4_TIM17_PWM) || defined(CONFIG_STM32L4_LPTIM1_PWM) || \ - defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \ + defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \ + defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \ + defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \ + defined(CONFIG_STM32_TIM17_PWM) || defined(CONFIG_STM32_LPTIM1_PWM) || \ + defined(CONFIG_STM32_LPTIM2_PWM) /* PWM driver channels configuration */ -#ifdef CONFIG_STM32L4_PWM_MULTICHAN +#ifdef CONFIG_STM32_PWM_MULTICHAN -#ifdef CONFIG_STM32L4_TIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # else # define PWM_TIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 @@ -124,13 +124,13 @@ #else # define PWM_TIM1_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # else # define PWM_TIM1_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 @@ -139,13 +139,13 @@ #else # define PWM_TIM1_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # else # define PWM_TIM1_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 @@ -154,8 +154,8 @@ #else # define PWM_TIM1_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM1_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # else # define PWM_TIM1_CH4CFG 0 @@ -167,8 +167,8 @@ #define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \ PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM2_CH1OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT # else # define PWM_TIM2_CH1CFG 0 @@ -177,8 +177,8 @@ #else # define PWM_TIM2_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM2_CH2OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT # else # define PWM_TIM2_CH2CFG 0 @@ -187,8 +187,8 @@ #else # define PWM_TIM2_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM2_CH3OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT # else # define PWM_TIM2_CH3CFG 0 @@ -197,8 +197,8 @@ #else # define PWM_TIM2_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM2_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM2_CH4OUT +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else # define PWM_TIM2_CH4CFG 0 @@ -210,8 +210,8 @@ #define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \ PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM3_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM3_CH1OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT # else # define PWM_TIM3_CH1CFG 0 @@ -220,8 +220,8 @@ #else # define PWM_TIM3_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM3_CH2OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT # else # define PWM_TIM3_CH2CFG 0 @@ -230,8 +230,8 @@ #else # define PWM_TIM3_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM3_CH3OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT # else # define PWM_TIM3_CH3CFG 0 @@ -240,8 +240,8 @@ #else # define PWM_TIM3_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM3_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM3_CH4OUT +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else # define PWM_TIM3_CH4CFG 0 @@ -253,8 +253,8 @@ #define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \ PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM4_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM4_CH1OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT # else # define PWM_TIM4_CH1CFG 0 @@ -263,8 +263,8 @@ #else # define PWM_TIM4_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM4_CH2OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT # else # define PWM_TIM4_CH2CFG 0 @@ -273,8 +273,8 @@ #else # define PWM_TIM4_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM4_CH3OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT # else # define PWM_TIM4_CH3CFG 0 @@ -283,8 +283,8 @@ #else # define PWM_TIM4_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM4_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM4_CH4OUT +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else # define PWM_TIM4_CH4CFG 0 @@ -296,8 +296,8 @@ #define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \ PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM5_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM5_CH1OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT # else # define PWM_TIM5_CH1CFG 0 @@ -306,8 +306,8 @@ #else # define PWM_TIM5_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM5_CH2OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT # else # define PWM_TIM5_CH2CFG 0 @@ -316,8 +316,8 @@ #else # define PWM_TIM5_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM5_CH3OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT # else # define PWM_TIM5_CH3CFG 0 @@ -326,8 +326,8 @@ #else # define PWM_TIM5_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM5_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM5_CH4OUT +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else # define PWM_TIM5_CH4CFG 0 @@ -339,13 +339,13 @@ #define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \ PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM8_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # else # define PWM_TIM8_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH1OUT +# ifdef CONFIG_STM32_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG GPIO_TIM8_CH1NOUT # else # define PWM_TIM8_CH1NCFG 0 @@ -354,13 +354,13 @@ #else # define PWM_TIM8_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM8_CH2OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # else # define PWM_TIM8_CH2CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH2NOUT +# ifdef CONFIG_STM32_TIM8_CH2NOUT # define PWM_TIM8_CH2NCFG GPIO_TIM8_CH2NOUT # else # define PWM_TIM8_CH2NCFG 0 @@ -369,13 +369,13 @@ #else # define PWM_TIM8_CHANNEL2 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL3 -# ifdef CONFIG_STM32L4_TIM8_CH3OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # else # define PWM_TIM8_CH3CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM8_CH3NOUT +# ifdef CONFIG_STM32_TIM8_CH3NOUT # define PWM_TIM8_CH3NCFG GPIO_TIM8_CH3NOUT # else # define PWM_TIM8_CH3NCFG 0 @@ -384,8 +384,8 @@ #else # define PWM_TIM8_CHANNEL3 0 #endif -#ifdef CONFIG_STM32L4_TIM8_CHANNEL4 -# ifdef CONFIG_STM32L4_TIM8_CH4OUT +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else # define PWM_TIM8_CH4CFG 0 @@ -397,13 +397,13 @@ #define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \ PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4) -#ifdef CONFIG_STM32L4_TIM15_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM15_CH1OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # else # define PWM_TIM15_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM15_CH1NOUT +# ifdef CONFIG_STM32_TIM15_CH1NOUT # define PWM_TIM15_CH1NCFG GPIO_TIM15_CH1NOUT # else # define PWM_TIM15_CH1NCFG 0 @@ -412,8 +412,8 @@ #else # define PWM_TIM15_CHANNEL1 0 #endif -#ifdef CONFIG_STM32L4_TIM15_CHANNEL2 -# ifdef CONFIG_STM32L4_TIM15_CH2OUT +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else # define PWM_TIM15_CH2CFG 0 @@ -424,13 +424,13 @@ #endif #define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2) -#ifdef CONFIG_STM32L4_TIM16_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM16_CH1OUT +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # else # define PWM_TIM16_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM16_CH1NOUT +# ifdef CONFIG_STM32_TIM16_CH1NOUT # define PWM_TIM16_CH1NCFG GPIO_TIM16_CH1NOUT # else # define PWM_TIM16_CH1NCFG 0 @@ -441,13 +441,13 @@ #endif #define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1 -#ifdef CONFIG_STM32L4_TIM17_CHANNEL1 -# ifdef CONFIG_STM32L4_TIM17_CH1OUT +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # else # define PWM_TIM17_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_TIM17_CH1NOUT +# ifdef CONFIG_STM32_TIM17_CH1NOUT # define PWM_TIM17_CH1NCFG GPIO_TIM17_CH1NOUT # else # define PWM_TIM17_CH1NCFG 0 @@ -458,13 +458,13 @@ #endif #define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM1_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM1_CH1OUT +#ifdef CONFIG_STM32_LPTIM1_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # else # define PWM_LPTIM1_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM1_CH1NOUT +# ifdef CONFIG_STM32_LPTIM1_CH1NOUT # define PWM_LPTIM1_CH1NCFG GPIO_LPTIM1_CH1NOUT # else # define PWM_LPTIM1_CH1NCFG 0 @@ -475,13 +475,13 @@ #endif #define PWM_LPTIM1_NCHANNELS PWM_LPTIM1_CHANNEL1 -#ifdef CONFIG_STM32L4_LPTIM2_CHANNEL1 -# ifdef CONFIG_STM32L4_LPTIM2_CH1OUT +#ifdef CONFIG_STM32_LPTIM2_CHANNEL1 +# ifdef CONFIG_STM32_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # else # define PWM_LPTIM2_CH1CFG 0 # endif -# ifdef CONFIG_STM32L4_LPTIM2_CH1NOUT +# ifdef CONFIG_STM32_LPTIM2_CH1NOUT # define PWM_LPTIM2_CH1NCFG GPIO_LPTIM2_CH1NOUT # else # define PWM_LPTIM2_CH1NCFG 0 @@ -492,12 +492,12 @@ #endif #define PWM_LPTIM2_NCHANNELS PWM_LPTIM2_CHANNEL1 -#else /* !CONFIG_STM32L4_PWM_MULTICHAN */ +#else /* !CONFIG_STM32_PWM_MULTICHAN */ /* For each timer that is enabled for PWM usage, we need the following * additional configuration settings: * - * CONFIG_STM32L4_TIMx_CHANNEL - Specifies the timer output channel + * CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel * {1,..,4} * PWM_TIMx_CHn - One of the values defined in chip/stm32*_pinmap.h. * In the case where there are multiple pin selections, the correct @@ -510,250 +510,250 @@ * Only one output channel per timer. */ -#ifdef CONFIG_STM32L4_TIM1_PWM -# if !defined(CONFIG_STM32L4_TIM1_CHANNEL) -# error "CONFIG_STM32L4_TIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM1_CHANNEL == 1 -# define CONFIG_STM32L4_TIM1_CHANNEL1 1 -# define CONFIG_STM32L4_TIM1_CH1MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH1OUT +#ifdef CONFIG_STM32_TIM1_PWM +# if !defined(CONFIG_STM32_TIM1_CHANNEL) +# error "CONFIG_STM32_TIM1_CHANNEL must be provided" +# elif CONFIG_STM32_TIM1_CHANNEL == 1 +# define CONFIG_STM32_TIM1_CHANNEL1 1 +# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH1OUT # define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH1NOUT +# ifdef CONFIG_STM32_TIM1_CH1NOUT # define PWM_TIM1_CH1NCFG GPIO_TIM1_CH1NOUT # else # define PWM_TIM1_CH1NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 2 -# define CONFIG_STM32L4_TIM1_CHANNEL2 1 -# define CONFIG_STM32L4_TIM1_CH2MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH2OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 2 +# define CONFIG_STM32_TIM1_CHANNEL2 1 +# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH2OUT # define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH2NOUT +# ifdef CONFIG_STM32_TIM1_CH2NOUT # define PWM_TIM1_CH2NCFG GPIO_TIM1_CH2NOUT # else # define PWM_TIM1_CH2NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 3 -# define CONFIG_STM32L4_TIM1_CHANNEL3 1 -# define CONFIG_STM32L4_TIM1_CH3MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH3OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 3 +# define CONFIG_STM32_TIM1_CHANNEL3 1 +# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH3OUT # define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT # endif -# ifdef CONFIG_STM32L4_TIM1_CH3NOUT +# ifdef CONFIG_STM32_TIM1_CH3NOUT # define PWM_TIM1_CH3NCFG GPIO_TIM1_CH3NOUT # else # define PWM_TIM1_CH3NCFG 0 # endif -# elif CONFIG_STM32L4_TIM1_CHANNEL == 4 -# define CONFIG_STM32L4_TIM1_CHANNEL4 1 -# define CONFIG_STM32L4_TIM1_CH4MODE CONFIG_STM32L4_TIM1_CHMODE -# ifdef CONFIG_STM32L4_TIM1_CH4OUT +# elif CONFIG_STM32_TIM1_CHANNEL == 4 +# define CONFIG_STM32_TIM1_CHANNEL4 1 +# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE +# ifdef CONFIG_STM32_TIM1_CH4OUT # define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT # endif # else -# error "Unsupported value of CONFIG_STM32L4_TIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL" # endif # define PWM_TIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM2_PWM -# if !defined(CONFIG_STM32L4_TIM2_CHANNEL) -# error "CONFIG_STM32L4_TIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM2_CHANNEL == 1 -# define CONFIG_STM32L4_TIM2_CHANNEL1 1 -# define CONFIG_STM32L4_TIM2_CH1MODE CONFIG_STM32L4_TIM2_CHMODE +#ifdef CONFIG_STM32_TIM2_PWM +# if !defined(CONFIG_STM32_TIM2_CHANNEL) +# error "CONFIG_STM32_TIM2_CHANNEL must be provided" +# elif CONFIG_STM32_TIM2_CHANNEL == 1 +# define CONFIG_STM32_TIM2_CHANNEL1 1 +# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 2 -# define CONFIG_STM32L4_TIM2_CHANNEL2 1 -# define CONFIG_STM32L4_TIM2_CH2MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 2 +# define CONFIG_STM32_TIM2_CHANNEL2 1 +# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 3 -# define CONFIG_STM32L4_TIM2_CHANNEL3 1 -# define CONFIG_STM32L4_TIM2_CH3MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 3 +# define CONFIG_STM32_TIM2_CHANNEL3 1 +# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT -# elif CONFIG_STM32L4_TIM2_CHANNEL == 4 -# define CONFIG_STM32L4_TIM2_CHANNEL4 1 -# define CONFIG_STM32L4_TIM2_CH4MODE CONFIG_STM32L4_TIM2_CHMODE +# elif CONFIG_STM32_TIM2_CHANNEL == 4 +# define CONFIG_STM32_TIM2_CHANNEL4 1 +# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE # define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL" # endif # define PWM_TIM2_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM3_PWM -# if !defined(CONFIG_STM32L4_TIM3_CHANNEL) -# error "CONFIG_STM32L4_TIM3_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM3_CHANNEL == 1 -# define CONFIG_STM32L4_TIM3_CHANNEL1 1 -# define CONFIG_STM32L4_TIM3_CH1MODE CONFIG_STM32L4_TIM3_CHMODE +#ifdef CONFIG_STM32_TIM3_PWM +# if !defined(CONFIG_STM32_TIM3_CHANNEL) +# error "CONFIG_STM32_TIM3_CHANNEL must be provided" +# elif CONFIG_STM32_TIM3_CHANNEL == 1 +# define CONFIG_STM32_TIM3_CHANNEL1 1 +# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 2 -# define CONFIG_STM32L4_TIM3_CHANNEL2 1 -# define CONFIG_STM32L4_TIM3_CH2MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 2 +# define CONFIG_STM32_TIM3_CHANNEL2 1 +# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 3 -# define CONFIG_STM32L4_TIM3_CHANNEL3 1 -# define CONFIG_STM32L4_TIM3_CH3MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 3 +# define CONFIG_STM32_TIM3_CHANNEL3 1 +# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT -# elif CONFIG_STM32L4_TIM3_CHANNEL == 4 -# define CONFIG_STM32L4_TIM3_CHANNEL4 1 -# define CONFIG_STM32L4_TIM3_CH4MODE CONFIG_STM32L4_TIM3_CHMODE +# elif CONFIG_STM32_TIM3_CHANNEL == 4 +# define CONFIG_STM32_TIM3_CHANNEL4 1 +# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE # define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM3_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL" # endif # define PWM_TIM3_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM4_PWM -# if !defined(CONFIG_STM32L4_TIM4_CHANNEL) -# error "CONFIG_STM32L4_TIM4_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM4_CHANNEL == 1 -# define CONFIG_STM32L4_TIM4_CHANNEL1 1 -# define CONFIG_STM32L4_TIM4_CH1MODE CONFIG_STM32L4_TIM4_CHMODE +#ifdef CONFIG_STM32_TIM4_PWM +# if !defined(CONFIG_STM32_TIM4_CHANNEL) +# error "CONFIG_STM32_TIM4_CHANNEL must be provided" +# elif CONFIG_STM32_TIM4_CHANNEL == 1 +# define CONFIG_STM32_TIM4_CHANNEL1 1 +# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 2 -# define CONFIG_STM32L4_TIM4_CHANNEL2 1 -# define CONFIG_STM32L4_TIM4_CH2MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 2 +# define CONFIG_STM32_TIM4_CHANNEL2 1 +# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 3 -# define CONFIG_STM32L4_TIM4_CHANNEL3 1 -# define CONFIG_STM32L4_TIM4_CH3MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 3 +# define CONFIG_STM32_TIM4_CHANNEL3 1 +# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT -# elif CONFIG_STM32L4_TIM4_CHANNEL == 4 -# define CONFIG_STM32L4_TIM4_CHANNEL4 1 -# define CONFIG_STM32L4_TIM4_CH4MODE CONFIG_STM32L4_TIM4_CHMODE +# elif CONFIG_STM32_TIM4_CHANNEL == 4 +# define CONFIG_STM32_TIM4_CHANNEL4 1 +# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE # define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM4_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL" # endif # define PWM_TIM4_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM5_PWM -# if !defined(CONFIG_STM32L4_TIM5_CHANNEL) -# error "CONFIG_STM32L4_TIM5_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM5_CHANNEL == 1 -# define CONFIG_STM32L4_TIM5_CHANNEL1 1 -# define CONFIG_STM32L4_TIM5_CH1MODE CONFIG_STM32L4_TIM5_CHMODE +#ifdef CONFIG_STM32_TIM5_PWM +# if !defined(CONFIG_STM32_TIM5_CHANNEL) +# error "CONFIG_STM32_TIM5_CHANNEL must be provided" +# elif CONFIG_STM32_TIM5_CHANNEL == 1 +# define CONFIG_STM32_TIM5_CHANNEL1 1 +# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 2 -# define CONFIG_STM32L4_TIM5_CHANNEL2 1 -# define CONFIG_STM32L4_TIM5_CH2MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 2 +# define CONFIG_STM32_TIM5_CHANNEL2 1 +# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 3 -# define CONFIG_STM32L4_TIM5_CHANNEL3 1 -# define CONFIG_STM32L4_TIM5_CH3MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 3 +# define CONFIG_STM32_TIM5_CHANNEL3 1 +# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT -# elif CONFIG_STM32L4_TIM5_CHANNEL == 4 -# define CONFIG_STM32L4_TIM5_CHANNEL4 1 -# define CONFIG_STM32L4_TIM5_CH4MODE CONFIG_STM32L4_TIM5_CHMODE +# elif CONFIG_STM32_TIM5_CHANNEL == 4 +# define CONFIG_STM32_TIM5_CHANNEL4 1 +# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE # define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM5_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL" # endif # define PWM_TIM5_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM8_PWM -# if !defined(CONFIG_STM32L4_TIM8_CHANNEL) -# error "CONFIG_STM32L4_TIM8_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM8_CHANNEL == 1 -# define CONFIG_STM32L4_TIM8_CHANNEL1 1 -# define CONFIG_STM32L4_TIM8_CH1MODE CONFIG_STM32L4_TIM8_CHMODE +#ifdef CONFIG_STM32_TIM8_PWM +# if !defined(CONFIG_STM32_TIM8_CHANNEL) +# error "CONFIG_STM32_TIM8_CHANNEL must be provided" +# elif CONFIG_STM32_TIM8_CHANNEL == 1 +# define CONFIG_STM32_TIM8_CHANNEL1 1 +# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT # define PWM_TIM8_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 2 -# define CONFIG_STM32L4_TIM8_CHANNEL2 1 -# define CONFIG_STM32L4_TIM8_CH2MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 2 +# define CONFIG_STM32_TIM8_CHANNEL2 1 +# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT # define PWM_TIM8_CH2NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 3 -# define CONFIG_STM32L4_TIM8_CHANNEL3 1 -# define CONFIG_STM32L4_TIM8_CH3MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 3 +# define CONFIG_STM32_TIM8_CHANNEL3 1 +# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT # define PWM_TIM8_CH3NCFG 0 -# elif CONFIG_STM32L4_TIM8_CHANNEL == 4 -# define CONFIG_STM32L4_TIM8_CHANNEL4 1 -# define CONFIG_STM32L4_TIM8_CH4MODE CONFIG_STM32L4_TIM8_CHMODE +# elif CONFIG_STM32_TIM8_CHANNEL == 4 +# define CONFIG_STM32_TIM8_CHANNEL4 1 +# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE # define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM8_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL" # endif # define PWM_TIM8_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM15_PWM -# if !defined(CONFIG_STM32L4_TIM15_CHANNEL) -# error "CONFIG_STM32L4_TIM15_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM15_CHANNEL == 1 -# define CONFIG_STM32L4_TIM15_CHANNEL1 1 -# define CONFIG_STM32L4_TIM15_CH1MODE CONFIG_STM32L4_TIM15_CHMODE +#ifdef CONFIG_STM32_TIM15_PWM +# if !defined(CONFIG_STM32_TIM15_CHANNEL) +# error "CONFIG_STM32_TIM15_CHANNEL must be provided" +# elif CONFIG_STM32_TIM15_CHANNEL == 1 +# define CONFIG_STM32_TIM15_CHANNEL1 1 +# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT # define PWM_TIM15_CH1NCFG 0 -# elif CONFIG_STM32L4_TIM15_CHANNEL == 2 -# define CONFIG_STM32L4_TIM15_CHANNEL2 1 -# define CONFIG_STM32L4_TIM15_CH2MODE CONFIG_STM32L4_TIM15_CHMODE +# elif CONFIG_STM32_TIM15_CHANNEL == 2 +# define CONFIG_STM32_TIM15_CHANNEL2 1 +# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE # define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT # else -# error "Unsupported value of CONFIG_STM32L4_TIM15_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL" # endif # define PWM_TIM15_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM16_PWM -# if !defined(CONFIG_STM32L4_TIM16_CHANNEL) -# error "CONFIG_STM32L4_TIM16_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM16_CHANNEL == 1 -# define CONFIG_STM32L4_TIM16_CHANNEL1 1 -# define CONFIG_STM32L4_TIM16_CH1MODE CONFIG_STM32L4_TIM16_CHMODE +#ifdef CONFIG_STM32_TIM16_PWM +# if !defined(CONFIG_STM32_TIM16_CHANNEL) +# error "CONFIG_STM32_TIM16_CHANNEL must be provided" +# elif CONFIG_STM32_TIM16_CHANNEL == 1 +# define CONFIG_STM32_TIM16_CHANNEL1 1 +# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE # define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT # define PWM_TIM16_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM16_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL" # endif # define PWM_TIM16_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_TIM17_PWM -# if !defined(CONFIG_STM32L4_TIM17_CHANNEL) -# error "CONFIG_STM32L4_TIM17_CHANNEL must be provided" -# elif CONFIG_STM32L4_TIM17_CHANNEL == 1 -# define CONFIG_STM32L4_TIM17_CHANNEL1 1 -# define CONFIG_STM32L4_TIM17_CH1MODE CONFIG_STM32L4_TIM17_CHMODE +#ifdef CONFIG_STM32_TIM17_PWM +# if !defined(CONFIG_STM32_TIM17_CHANNEL) +# error "CONFIG_STM32_TIM17_CHANNEL must be provided" +# elif CONFIG_STM32_TIM17_CHANNEL == 1 +# define CONFIG_STM32_TIM17_CHANNEL1 1 +# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE # define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT # define PWM_TIM17_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_TIM17_CHANNEL" +# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL" # endif # define PWM_TIM17_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM1_PWM -# if !defined(CONFIG_STM32L4_LPTIM1_CHANNEL) -# error "CONFIG_STM32L4_LPTIM1_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM1_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM1_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM1_PWM +# if !defined(CONFIG_STM32_LPTIM1_CHANNEL) +# error "CONFIG_STM32_LPTIM1_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM1_CHANNEL == 1 +# define CONFIG_STM32_LPTIM1_CHANNEL1 1 # define PWM_LPTIM1_CH1CFG GPIO_LPTIM1_CH1OUT # define PWM_LPTIM1_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM1_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM1_CHANNEL" # endif # define PWM_LPTIM1_NCHANNELS 1 #endif -#ifdef CONFIG_STM32L4_LPTIM2_PWM -# if !defined(CONFIG_STM32L4_LPTIM2_CHANNEL) -# error "CONFIG_STM32L4_LPTIM2_CHANNEL must be provided" -# elif CONFIG_STM32L4_LPTIM2_CHANNEL == 1 -# define CONFIG_STM32L4_LPTIM2_CHANNEL1 1 +#ifdef CONFIG_STM32_LPTIM2_PWM +# if !defined(CONFIG_STM32_LPTIM2_CHANNEL) +# error "CONFIG_STM32_LPTIM2_CHANNEL must be provided" +# elif CONFIG_STM32_LPTIM2_CHANNEL == 1 +# define CONFIG_STM32_LPTIM2_CHANNEL1 1 # define PWM_LPTIM2_CH1CFG GPIO_LPTIM2_CH1OUT # define PWM_LPTIM2_CH1NCFG 0 # else -# error "Unsupported value of CONFIG_STM32L4_LPTIM2_CHANNEL" +# error "Unsupported value of CONFIG_STM32_LPTIM2_CHANNEL" # endif # define PWM_LPTIM2_NCHANNELS 1 #endif @@ -762,27 +762,27 @@ /* Complementary outputs support */ -#if defined(CONFIG_STM32L4_TIM1_CH1NOUT) || defined(CONFIG_STM32L4_TIM1_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM1_CH3NOUT) +#if defined(CONFIG_STM32_TIM1_CH1NOUT) || defined(CONFIG_STM32_TIM1_CH2NOUT) || \ + defined(CONFIG_STM32_TIM1_CH3NOUT) # define HAVE_TIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM8_CH1NOUT) || defined(CONFIG_STM32L4_TIM8_CH2NOUT) || \ - defined(CONFIG_STM32L4_TIM8_CH3NOUT) +#if defined(CONFIG_STM32_TIM8_CH1NOUT) || defined(CONFIG_STM32_TIM8_CH2NOUT) || \ + defined(CONFIG_STM32_TIM8_CH3NOUT) # define HAVE_TIM8_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM15_CH1NOUT) +#if defined(CONFIG_STM32_TIM15_CH1NOUT) # define HAVE_TIM15_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM16_CH1NOUT) +#if defined(CONFIG_STM32_TIM16_CH1NOUT) # define HAVE_TIM16_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_TIM17_CH1NOUT) +#if defined(CONFIG_STM32_TIM17_CH1NOUT) # define HAVE_TIM17_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM1_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM1_CH1NOUT) # define HAVE_LPTIM1_COMPLEMENTARY #endif -#if defined(CONFIG_STM32L4_LPTIM2_CH1NOUT) +#if defined(CONFIG_STM32_LPTIM2_CH1NOUT) # define HAVE_LPTIM2_COMPLEMENTARY #endif #if defined(HAVE_TIM1_COMPLEMENTARY) || defined(HAVE_TIM8_COMPLEMENTARY) || \ @@ -794,7 +794,7 @@ /* Low-level ops helpers ****************************************************/ -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* NOTE: low-level ops accept pwm_lowerhalf_s as first argument, but llops * access can be found in stm32_pwm_dev_s @@ -826,7 +826,7 @@ (dev)->llops->freq_update((struct pwm_lowerhalf_s *)dev, freq) #define PWM_TIM_ENABLE(dev, state) \ (dev)->llops->tim_enable((struct pwm_lowerhalf_s *)dev, state) -#ifdef CONFIG_DEBUG_STM32L4_PWM_INFO +#ifdef CONFIG_DEBUG_STM32_PWM_INFO # define PWM_DUMP_REGS(dev, msg) \ (dev)->llops->dump_regs((struct pwm_lowerhalf_s *)dev, msg) #else @@ -922,7 +922,7 @@ enum stm32_pwm_output_e /* 1 << 11 reserved - no complementary output for CH6 */ }; -#ifdef CONFIG_STM32L4_PWM_LL_OPS +#ifdef CONFIG_STM32_PWM_LL_OPS /* This structure provides the publicly visible representation of the * "lower-half" PWM driver structure. @@ -1008,7 +1008,7 @@ struct stm32_pwm_ops_s #endif }; -#endif /* CONFIG_STM32L4_PWM_LL_OPS */ +#endif /* CONFIG_STM32_PWM_LL_OPS */ /**************************************************************************** * Public Data @@ -1073,5 +1073,5 @@ struct pwm_lowerhalf_s *stm32_lp_pwminitialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_TIMx_PWM */ +#endif /* CONFIG_STM32_TIMx_PWM */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_PWM_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.c b/arch/arm/src/stm32l4/stm32l4_pwr.c index 088c66dfe4f..5bd1d6db51e 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.c +++ b/arch/arm/src/stm32l4/stm32l4_pwr.c @@ -221,7 +221,7 @@ bool stm32_pwr_enableusv(bool set) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32_pwr_enable_pvme2(bool set) { uint32_t regval; diff --git a/arch/arm/src/stm32l4/stm32l4_pwr.h b/arch/arm/src/stm32l4/stm32l4_pwr.h index 2de90b4f585..d214f11fe49 100644 --- a/arch/arm/src/stm32l4/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/stm32l4_pwr.h @@ -121,7 +121,7 @@ bool stm32_pwr_enableusv(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32_pwr_enable_pvme2(bool set); #endif @@ -137,7 +137,7 @@ bool stm32_pwr_enable_pvme2(bool set); * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32_pwr_get_pvmo2(void); #endif @@ -156,7 +156,7 @@ bool stm32_pwr_get_pvmo2(void); * True: The bit was previously set. ****************************************************************************/ -#if !defined(CONFIG_STM32L4_STM32L4X3) +#if !defined(CONFIG_STM32_STM32L4X3) bool stm32_pwr_vddio2_valid(bool set); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index b7ce3145b32..18ca8468adf 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -62,14 +62,14 @@ /* If TIM2 or TIM5 are enabled, then we have 32-bit timers */ -#if defined(CONFIG_STM32L4_TIM2_QE) || defined(CONFIG_STM32L4_TIM5_QE) +#if defined(CONFIG_STM32_TIM2_QE) || defined(CONFIG_STM32_TIM5_QE) # define HAVE_32BIT_TIMERS 1 #endif /* If TIM1,3,4, or 8 are enabled, then we have 16-bit timers */ -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM3_QE) || \ - defined(CONFIG_STM32L4_TIM4_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM3_QE) || \ + defined(CONFIG_STM32_TIM4_QE) || defined(CONFIG_STM32_TIM8_QE) # define HAVE_16BIT_TIMERS 1 #endif @@ -91,51 +91,51 @@ /* Input filter *************************************************************/ -#ifdef CONFIG_STM32L4_QENCODER_FILTER -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_1) +#ifdef CONFIG_STM32_QENCODER_FILTER +# if defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_1) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_NOFILT # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_CKINT) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_2) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_CKINT) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_2) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT2 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_4) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_4) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT4 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FCKINT8 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_2) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_2) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd26 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd28 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_4) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_4) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd46 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd48 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_8) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_8) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd86 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd88 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_16) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_16) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd165 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd166 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd168 # endif -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_FDTS_32) -# if defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_5) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_FDTS_32) +# if defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_5) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd325 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_6) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_6) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd326 -# elif defined(CONFIG_STM32L4_QENCODER_SAMPLE_EVENT_8) +# elif defined(CONFIG_STM32_QENCODER_SAMPLE_EVENT_8) # define STM32_QENCODER_ICF GTIM_CCMR_ICF_FDTSd328 # endif # endif @@ -271,7 +271,7 @@ static const struct qe_ops_s g_qecallbacks = /* Per-timer state structures */ -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE static const struct stm32_qeconfig_s g_tim1config = { .timid = 1, @@ -280,7 +280,7 @@ static const struct stm32_qeconfig_s g_tim1config = .width = TIM1_BITWIDTH, #endif .base = STM32_TIM1_BASE, - .psc = CONFIG_STM32L4_TIM1_QEPSC, + .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, }; @@ -295,7 +295,7 @@ static struct stm32_lowerhalf_s g_tim1lower = #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE static const struct stm32_qeconfig_s g_tim2config = { .timid = 2, @@ -304,7 +304,7 @@ static const struct stm32_qeconfig_s g_tim2config = .width = TIM2_BITWIDTH, #endif .base = STM32_TIM2_BASE, - .psc = CONFIG_STM32L4_TIM2_QEPSC, + .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, }; @@ -319,7 +319,7 @@ static struct stm32_lowerhalf_s g_tim2lower = #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE static const struct stm32_qeconfig_s g_tim3config = { .timid = 3, @@ -328,7 +328,7 @@ static const struct stm32_qeconfig_s g_tim3config = .width = TIM3_BITWIDTH, #endif .base = STM32_TIM3_BASE, - .psc = CONFIG_STM32L4_TIM3_QEPSC, + .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, }; @@ -343,7 +343,7 @@ static struct stm32_lowerhalf_s g_tim3lower = #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE static const struct stm32_qeconfig_s g_tim4config = { .timid = 4, @@ -352,7 +352,7 @@ static const struct stm32_qeconfig_s g_tim4config = .width = TIM4_BITWIDTH, #endif .base = STM32_TIM4_BASE, - .psc = CONFIG_STM32L4_TIM4_QEPSC, + .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, }; @@ -367,7 +367,7 @@ static struct stm32_lowerhalf_s g_tim4lower = #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE static const struct stm32_qeconfig_s g_tim5config = { .timid = 5, @@ -376,7 +376,7 @@ static const struct stm32_qeconfig_s g_tim5config = .width = TIM5_BITWIDTH, #endif .base = STM32_TIM5_BASE, - .psc = CONFIG_STM32L4_TIM5_QEPSC, + .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, }; @@ -391,7 +391,7 @@ static struct stm32_lowerhalf_s g_tim5lower = #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE static const struct stm32_qeconfig_s g_tim8config = { .timid = 8, @@ -400,7 +400,7 @@ static const struct stm32_qeconfig_s g_tim8config = .width = TIM8_BITWIDTH, #endif .base = STM32_TIM8_BASE, - .psc = CONFIG_STM32L4_TIM8_QEPSC, + .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, }; @@ -553,7 +553,7 @@ static void stm32_dumpregs(struct stm32_lowerhalf_s *priv, sninfo(" CCR3: %08" PRIx32 " CCR4: %08" PRIx32 "\n", stm32_getreg32(priv, STM32_GTIM_CCR3_OFFSET), stm32_getreg32(priv, STM32_GTIM_CCR4_OFFSET)); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { sninfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n", @@ -584,27 +584,27 @@ static struct stm32_lowerhalf_s *stm32_tim2lower(int tim) { switch (tim) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: return &g_tim1lower; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: return &g_tim2lower; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: return &g_tim3lower; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: return &g_tim4lower; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: return &g_tim5lower; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: return &g_tim8lower; #endif @@ -739,7 +739,7 @@ static int stm32_setup(struct qe_lowerhalf_s *lower) stm32_putreg16(priv, STM32_GTIM_PSC_OFFSET, (uint16_t)priv->config->psc); -#if defined(CONFIG_STM32L4_TIM1_QE) || defined(CONFIG_STM32L4_TIM8_QE) +#if defined(CONFIG_STM32_TIM1_QE) || defined(CONFIG_STM32_TIM8_QE) if (priv->config->timid == 1 || priv->config->timid == 8) { /* Clear the Repetition Counter value */ @@ -950,37 +950,37 @@ static int stm32_shutdown(struct qe_lowerhalf_s *lower) switch (priv->config->timid) { -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE case 1: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM1RST; break; #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE case 2: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM2RST; break; #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE case 3: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM3RST; break; #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE case 4: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM4RST; break; #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE case 5: regaddr = STM32_RCC_APB1RSTR1; resetbit = RCC_APB1RSTR1_TIM5RST; break; #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE case 8: regaddr = STM32_RCC_APB2RSTR; resetbit = RCC_APB2RSTR_TIM8RST; diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.h b/arch/arm/src/stm32l4/stm32l4_qencoder.h index fefe8c0d9e9..4b07b1fd42a 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.h +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.h @@ -43,23 +43,23 @@ * timer "n" is intended to be used for as a quadrature encoder. */ -#ifndef CONFIG_STM32L4_TIM1 -# undef CONFIG_STM32L4_TIM1_QE +#ifndef CONFIG_STM32_TIM1 +# undef CONFIG_STM32_TIM1_QE #endif -#ifndef CONFIG_STM32L4_TIM2 -# undef CONFIG_STM32L4_TIM2_QE +#ifndef CONFIG_STM32_TIM2 +# undef CONFIG_STM32_TIM2_QE #endif -#ifndef CONFIG_STM32L4_TIM3 -# undef CONFIG_STM32L4_TIM3_QE +#ifndef CONFIG_STM32_TIM3 +# undef CONFIG_STM32_TIM3_QE #endif -#ifndef CONFIG_STM32L4_TIM4 -# undef CONFIG_STM32L4_TIM4_QE +#ifndef CONFIG_STM32_TIM4 +# undef CONFIG_STM32_TIM4_QE #endif -#ifndef CONFIG_STM32L4_TIM5 -# undef CONFIG_STM32L4_TIM5_QE +#ifndef CONFIG_STM32_TIM5 +# undef CONFIG_STM32_TIM5_QE #endif -#ifndef CONFIG_STM32L4_TIM8 -# undef CONFIG_STM32L4_TIM8_QE +#ifndef CONFIG_STM32_TIM8 +# undef CONFIG_STM32_TIM8_QE #endif /* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.c b/arch/arm/src/stm32l4/stm32l4_qspi.c index 85c80431636..5c5f29eeb08 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.c +++ b/arch/arm/src/stm32l4/stm32l4_qspi.c @@ -56,7 +56,7 @@ #include "hardware/stm32l4_qspi.h" #include "hardware/stm32l4_pinmap.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -67,7 +67,7 @@ /* Check if QSPI debug is enabled */ #ifndef CONFIG_DEBUG_DMA -# undef CONFIG_STM32L4_QSPI_DMADEBUG +# undef CONFIG_STM32_QSPI_DMADEBUG #endif #define DMA_INITIAL 0 @@ -80,7 +80,7 @@ /* Can't have both interrupt-driven QSPI and DMA QSPI */ -#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32L4_QSPI_DMA) +#if defined(STM32_QSPI_INTERRUPTS) && defined(CONFIG_STM32_QSPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for QSPI" #endif @@ -92,23 +92,23 @@ GPIO_QSPI_IO1 GPIO_QSPI_IO2 GPIO_QSPI_IO3 GPIO_QSPI_SCK in your board.h #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# if defined(CONFIG_STM32L4_QSPI_DMA_CHAN_1_5) +# if defined(CONFIG_STM32_QSPI_DMA_CHAN_1_5) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_1 -# elif defined(CONFIG_STM32L4_QSPI_DMA_CHAN_2_7) +# elif defined(CONFIG_STM32_QSPI_DMA_CHAN_2_7) # define DMACHAN_QUADSPI DMACHAN_QUADSPI_2 # else # error QSPI DMA channel must be specified via DMACHAN_QUADSPI in your board.h # endif -# if defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_LOW) +# if defined(CONFIG_STM32_QSPI_DMAPRIORITY_LOW) # define QSPI_DMA_PRIO DMA_CCR_PRILO -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_MEDIUM) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_MEDIUM) # define QSPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_HIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_HIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIHI -# elif defined(CONFIG_STM32L4_QSPI_DMAPRIORITY_VERYHIGH) +# elif defined(CONFIG_STM32_QSPI_DMAPRIORITY_VERYHIGH) # define QSPI_DMA_PRIO DMA_CCR_PRIVERYHI # else # define QSPI_DMA_PRIO DMA_CCR_PRIMED @@ -120,8 +120,8 @@ # error your board.h needs to define the value of BOARD_AHB_FREQUENCY #endif -#if !defined(CONFIG_STM32L4_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32L4_QSPI_FLASH_SIZE -# error you must specify a positive flash size via CONFIG_STM32L4_QSPI_FLASH_SIZE +#if !defined(CONFIG_STM32_QSPI_FLASH_SIZE) || 0 == CONFIG_STM32_QSPI_FLASH_SIZE +# error you must specify a positive flash size via CONFIG_STM32_QSPI_FLASH_SIZE #endif /* DMA timeout. The value is not critical; we just don't want the system to @@ -169,7 +169,7 @@ struct stm32_qspidev_s struct qspi_xctnspec_s *xctn; /* context of transaction in progress */ #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA bool candma; /* DMA is supported */ sem_t dmawait; /* Used to wait for DMA completion */ int result; /* DMA result */ @@ -179,11 +179,11 @@ struct stm32_qspidev_s /* Debug stuff */ -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; #endif -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG bool wrlast; /* Last was a write */ uint32_t addresslast; /* Last address */ uint32_t valuelast; /* Last value */ @@ -233,7 +233,7 @@ struct qspi_xctnspec_s /* Helpers */ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address); #else @@ -267,9 +267,9 @@ static int qspi0_interrupt(int irq, void *context, void *arg); /* DMA support */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA -# ifdef CONFIG_STM32L4_QSPI_DMADEBUG +# ifdef CONFIG_STM32_QSPI_DMADEBUG # define qspi_dma_sample(s,i) stm32_dmasample((s)->dmach, &(s)->dmaregs[i]) static void qspi_dma_sampleinit(struct stm32_qspidev_s *priv); static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); @@ -279,8 +279,8 @@ static void qspi_dma_sampledone(struct stm32_qspidev_s *priv); # define qspi_dma_sampledone(s) # endif -# ifndef CONFIG_STM32L4_QSPI_DMATHRESHOLD -# define CONFIG_STM32L4_QSPI_DMATHRESHOLD 4 +# ifndef CONFIG_STM32_QSPI_DMATHRESHOLD +# define CONFIG_STM32_QSPI_DMATHRESHOLD 4 # endif #endif @@ -340,7 +340,7 @@ static struct stm32_qspidev_s g_qspi0dev = .op_sem = SEM_INITIALIZER(0), #endif .intf = 0, -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA .candma = true, .dmawait = SEM_INITIALIZER(0), #endif @@ -366,7 +366,7 @@ static struct stm32_qspidev_s g_qspi0dev = * ****************************************************************************/ -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG static bool qspi_checkreg(struct stm32_qspidev_s *priv, bool wr, uint32_t value, uint32_t address) { @@ -418,7 +418,7 @@ static inline uint32_t qspi_getreg(struct stm32_qspidev_s *priv, uint32_t address = priv->base + offset; uint32_t value = getreg32(address); -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, false, value, address)) { spiinfo("%08" PRIx32 "->%08" PRIx32 "\n", address, value); @@ -441,7 +441,7 @@ static inline void qspi_putreg(struct stm32_qspidev_s *priv, { uint32_t address = priv->base + offset; -#ifdef CONFIG_STM32L4_QSPI_REGDEBUG +#ifdef CONFIG_STM32_QSPI_REGDEBUG if (qspi_checkreg(priv, true, value, address)) { spiinfo("%08" PRIx32 "<-%08" PRIx32 "\n", address, value); @@ -581,7 +581,7 @@ static void qspi_dumpgpioconfig(const char *msg) } #endif -#ifdef CONFIG_STM32L4_QSPI_DMADEBUG +#ifdef CONFIG_STM32_QSPI_DMADEBUG /**************************************************************************** * Name: qspi_dma_sampleinit * @@ -1269,7 +1269,7 @@ static int qspi0_interrupt(int irq, void *context, void *arg) return OK; } -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /**************************************************************************** * Name: qspi_dma_timeout * @@ -2202,11 +2202,11 @@ static int qspi_memory(struct qspi_dev_s *dev, ret = xctn.disposition; -#elif defined(CONFIG_STM32L4_QSPI_DMA) +#elif defined(CONFIG_STM32_QSPI_DMA) /* Can we perform DMA? Should we perform DMA? */ if (priv->candma && - meminfo->buflen > CONFIG_STM32L4_QSPI_DMATHRESHOLD && + meminfo->buflen > CONFIG_STM32_QSPI_DMATHRESHOLD && IS_ALIGNED((uintptr_t)meminfo->buffer, 4) && IS_ALIGNED(meminfo->buflen, 4)) { @@ -2371,7 +2371,7 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) /* Configure QSPI FIFO Threshold */ regval &= ~(QSPI_CR_FTHRES_MASK); - regval |= ((CONFIG_STM32L4_QSPI_FIFO_THESHOLD - 1) << + regval |= ((CONFIG_STM32_QSPI_FIFO_THESHOLD - 1) << QSPI_CR_FTHRES_SHIFT); qspi_putreg(priv, regval, STM32_QUADSPI_CR_OFFSET); @@ -2392,10 +2392,10 @@ static int qspi_hw_initialize(struct stm32_qspidev_s *priv) regval = qspi_getreg(priv, STM32_QUADSPI_DCR_OFFSET); regval &= ~(QSPI_DCR_CKMODE | QSPI_DCR_CSHT_MASK | QSPI_DCR_FSIZE_MASK); regval |= (0x00); - regval |= ((CONFIG_STM32L4_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); - if (0 != CONFIG_STM32L4_QSPI_FLASH_SIZE) + regval |= ((CONFIG_STM32_QSPI_CSHT - 1) << QSPI_DCR_CSHT_SHIFT); + if (0 != CONFIG_STM32_QSPI_FLASH_SIZE) { - unsigned int nsize = CONFIG_STM32L4_QSPI_FLASH_SIZE; + unsigned int nsize = CONFIG_STM32_QSPI_FLASH_SIZE; int nlog2size = 31; while (!(nsize & 0x80000000)) { @@ -2501,7 +2501,7 @@ struct qspi_dev_s *stm32_qspi_initialize(int intf) { /* Now perform one time initialization */ -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA /* Pre-allocate DMA channels. */ if (priv->candma) @@ -2554,7 +2554,7 @@ errout_with_irq: errout_with_dmach: #endif -#ifdef CONFIG_STM32L4_QSPI_DMA +#ifdef CONFIG_STM32_QSPI_DMA if (priv->dmach) { stm32_dmafree(priv->dmach); @@ -2685,4 +2685,4 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev) qspi_lock(dev, false); } -#endif /* CONFIG_STM32L4_QSPI */ +#endif /* CONFIG_STM32_QSPI */ diff --git a/arch/arm/src/stm32l4/stm32l4_qspi.h b/arch/arm/src/stm32l4/stm32l4_qspi.h index e4f9c9cec22..3e6f0590936 100644 --- a/arch/arm/src/stm32l4/stm32l4_qspi.h +++ b/arch/arm/src/stm32l4/stm32l4_qspi.h @@ -34,7 +34,7 @@ #include "chip.h" -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /**************************************************************************** * Pre-processor Definitions @@ -126,5 +126,5 @@ void stm32_qspi_exit_memorymapped(struct qspi_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_QSPI */ +#endif /* CONFIG_STM32_QSPI */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_QSPI_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index a397f68af72..26830f433d5 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -43,13 +43,13 @@ /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "stm32l4x3xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "stm32l4x5xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "stm32l4x6xx_rcc.c" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "stm32l4xrxx_rcc.c" #else # error "Unsupported STM32L4 chip" @@ -98,7 +98,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L4_PWR) && defined(CONFIG_STM32L4_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -163,7 +163,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -185,7 +185,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -220,7 +220,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -235,7 +235,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index a4287889351..b316142dab8 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -32,13 +32,13 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) +#if defined(CONFIG_STM32_STM32L4X3) # include "hardware/stm32l4x3xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X5) +#elif defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_rcc.h" -#elif defined(CONFIG_STM32L4_STM32L4XR) +#elif defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4xrxx_rcc.h" #else # error "Unsupported STM32L4 chip" @@ -107,7 +107,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -130,7 +130,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -147,7 +147,7 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32l4/stm32l4_rng.c b/arch/arm/src/stm32l4/stm32l4_rng.c index 4447ffcf6eb..9c3e70831ae 100644 --- a/arch/arm/src/stm32l4/stm32l4_rng.c +++ b/arch/arm/src/stm32l4/stm32l4_rng.c @@ -41,7 +41,7 @@ #include "hardware/stm32l4_rng.h" #include "arm_internal.h" -#if defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) /**************************************************************************** @@ -315,4 +315,4 @@ void devurandom_register(void) #endif #endif /* CONFIG_DEV_RANDOM || CONFIG_DEV_URANDOM_ARCH */ -#endif /* CONFIG_STM32L4_RNG */ +#endif /* CONFIG_STM32_RNG */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.c b/arch/arm/src/stm32l4/stm32l4_rtc.c index 7292d5eb79a..afd88e708aa 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.c +++ b/arch/arm/src/stm32l4/stm32l4_rtc.c @@ -46,7 +46,7 @@ #include "stm32l4_exti.h" #include "stm32l4_rtc.h" -#ifdef CONFIG_STM32L4_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -67,8 +67,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32L4_PWR -# error "CONFIG_STM32L4_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -869,13 +869,13 @@ int up_rtc_initialize(void) stm32_pwr_enablebkp(true); -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else @@ -918,7 +918,7 @@ int up_rtc_initialize(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32L4_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -931,7 +931,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ @@ -939,7 +939,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#else /* defined(CONFIG_STM32L4_RTC_LSECLOCK) */ +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | @@ -1021,7 +1021,7 @@ int up_rtc_initialize(void) int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1040,7 +1040,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1102,7 +1102,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; @@ -1182,8 +1182,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32L4_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1669,11 +1669,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32L4_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32L4_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32L4_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1844,4 +1844,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32L4_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32l4/stm32l4_rtc.h b/arch/arm/src/stm32l4/stm32l4_rtc.h index ebb8d093f81..af354a7bd7d 100644 --- a/arch/arm/src/stm32l4/stm32l4_rtc.h +++ b/arch/arm/src/stm32l4/stm32l4_rtc.h @@ -41,21 +41,21 @@ #define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ -#if !defined(CONFIG_STM32L4_RTC_MAGIC) -# define CONFIG_STM32L4_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32L4_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32L4_RTC_MAGIC_REG) -# define CONFIG_STM32L4_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32L4_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32L4_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32L4_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -156,7 +156,7 @@ bool stm32_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32l4/stm32l4_sai.c b/arch/arm/src/stm32l4/stm32l4_sai.c index 550b5a5b00e..4b2ab152851 100644 --- a/arch/arm/src/stm32l4/stm32l4_sai.c +++ b/arch/arm/src/stm32l4/stm32l4_sai.c @@ -63,7 +63,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sai.h" -#ifdef CONFIG_STM32L4_SAI +#ifdef CONFIG_STM32_SAI /**************************************************************************** * Pre-processor Definitions @@ -81,11 +81,11 @@ # error CONFIG_I2S required by this driver #endif -#ifdef CONFIG_STM32L4_SAI_POLLING +#ifdef CONFIG_STM32_SAI_POLLING # error "Polling SAI not yet supported" #endif -#ifdef CONFIG_STM32L4_SAI_INTERRUPTS +#ifdef CONFIG_STM32_SAI_INTERRUPTS # error "Interrupt driven SAI not yet supported" #endif @@ -101,7 +101,7 @@ # define CONFIG_STM32L4_SAI_MAXINFLIGHT (16) #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* SAI DMA priority */ # if defined(CONFIG_STM32L4_SAI_DMAPRIO) @@ -149,7 +149,7 @@ struct stm32_sai_s mutex_t lock; /* Assures mutually exclusive access to SAI */ uint32_t frequency; /* SAI clock frequency */ uint32_t syncen; /* Synchronization setting */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA uint16_t dma_ch; /* DMA channel number */ DMA_HANDLE dma; /* DMA channel handle */ uint32_t dma_ccr; /* DMA control register */ @@ -191,7 +191,7 @@ static void sai_buf_initialize(struct stm32_sai_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_schedule(struct stm32_sai_s *priv, int result); static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg); #endif @@ -229,19 +229,19 @@ static const struct i2s_ops_s g_i2sops = /* SAI1 state */ -#ifdef CONFIG_STM32L4_SAI1_A +#ifdef CONFIG_STM32_SAI1_A static struct stm32_sai_s g_sai1a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI1_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_A, #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, @@ -250,19 +250,19 @@ static struct stm32_sai_s g_sai1a_priv = }; #endif -#ifdef CONFIG_STM32L4_SAI1_B +#ifdef CONFIG_STM32_SAI1_B static struct stm32_sai_s g_sai1b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI1_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI1_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI1_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI1_B, #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, @@ -273,19 +273,19 @@ static struct stm32_sai_s g_sai1b_priv = /* SAI2 state */ -#ifdef CONFIG_STM32L4_SAI2_A +#ifdef CONFIG_STM32_SAI2_A static struct stm32_sai_s g_sai2a_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_A_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B +#ifdef CONFIG_STM32_SAI2_A_SYNC_WITH_B .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_A, #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, @@ -294,19 +294,19 @@ static struct stm32_sai_s g_sai2a_priv = }; #endif -#ifdef CONFIG_STM32L4_SAI2_B +#ifdef CONFIG_STM32_SAI2_B static struct stm32_sai_s g_sai2b_priv = { .dev.ops = &g_i2sops, .base = STM32_SAI2_B_BASE, .lock = NXMUTEX_INITIALIZER, .frequency = STM32_SAI2_FREQUENCY, -#ifdef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A +#ifdef CONFIG_STM32_SAI2_B_SYNC_WITH_A .syncen = SAI_CR1_SYNCEN_SYNC_INT, #else .syncen = SAI_CR1_SYNCEN_ASYNC, #endif -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA .dma_ch = DMACHAN_SAI2_B, #endif .datalen = CONFIG_STM32L4_SAI_DEFAULT_DATALEN, @@ -500,7 +500,7 @@ static void sai_timeout(wdparm_t arg) struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; DEBUGASSERT(priv != NULL); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Cancel the DMA */ stm32_dmastop(priv->dma); @@ -530,7 +530,7 @@ static void sai_timeout(wdparm_t arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static int sai_dma_setup(struct stm32_sai_s *priv) { struct sai_buffer_s *bfcontainer; @@ -702,7 +702,7 @@ static void sai_worker(void *arg) */ flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA sai_dma_setup(priv); #endif leave_critical_section(flags); @@ -814,7 +814,7 @@ static void sai_schedule(struct stm32_sai_s *priv, int result) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA static void sai_dma_callback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_sai_s *priv = (struct stm32_sai_s *)arg; @@ -1005,7 +1005,7 @@ static int sai_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1110,7 +1110,7 @@ static int sai_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, * progress, then this will do nothing. */ -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA ret = sai_dma_setup(priv); #endif DEBUGASSERT(ret == OK); @@ -1269,7 +1269,7 @@ static void sai_portinitialize(struct stm32_sai_s *priv) sai_datawidth((struct i2s_dev_s *)priv, CONFIG_STM32L4_SAI_DEFAULT_DATALEN); -#ifdef CONFIG_STM32L4_SAI_DMA +#ifdef CONFIG_STM32_SAI_DMA /* Get DMA channel */ priv->dma = stm32_dmachannel(priv->dma_ch); @@ -1324,14 +1324,14 @@ struct i2s_dev_s *stm32_sai_initialize(int intf) switch (intf) { -#ifdef CONFIG_STM32L4_SAI1_A +#ifdef CONFIG_STM32_SAI1_A case SAI1_BLOCK_A: { i2sinfo("SAI1 Block A Selected\n"); priv = &g_sai1a_priv; stm32_configgpio(GPIO_SAI1_SD_A); -# ifndef CONFIG_STM32L4_SAI1_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI1_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI1_FS_A); stm32_configgpio(GPIO_SAI1_SCK_A); stm32_configgpio(GPIO_SAI1_MCLK_A); @@ -1340,14 +1340,14 @@ struct i2s_dev_s *stm32_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI1_B +#ifdef CONFIG_STM32_SAI1_B case SAI1_BLOCK_B: { i2sinfo("SAI1 Block B Selected\n"); priv = &g_sai1b_priv; stm32_configgpio(GPIO_SAI1_SD_B); -# ifndef CONFIG_STM32L4_SAI1_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI1_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI1_FS_B); stm32_configgpio(GPIO_SAI1_SCK_B); stm32_configgpio(GPIO_SAI1_MCLK_B); @@ -1356,14 +1356,14 @@ struct i2s_dev_s *stm32_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI2_A +#ifdef CONFIG_STM32_SAI2_A case SAI2_BLOCK_A: { i2sinfo("SAI2 Block A Selected\n"); priv = &g_sai2a_priv; stm32_configgpio(GPIO_SAI2_SD_A); -# ifndef CONFIG_STM32L4_SAI2_A_SYNC_WITH_B +# ifndef CONFIG_STM32_SAI2_A_SYNC_WITH_B stm32_configgpio(GPIO_SAI2_FS_A); stm32_configgpio(GPIO_SAI2_SCK_A); stm32_configgpio(GPIO_SAI2_MCLK_A); @@ -1372,14 +1372,14 @@ struct i2s_dev_s *stm32_sai_initialize(int intf) } #endif -#ifdef CONFIG_STM32L4_SAI2_B +#ifdef CONFIG_STM32_SAI2_B case SAI2_BLOCK_B: { i2sinfo("SAI2 Block B Selected\n"); priv = &g_sai2b_priv; stm32_configgpio(GPIO_SAI2_SD_B); -# ifndef CONFIG_STM32L4_SAI2_B_SYNC_WITH_A +# ifndef CONFIG_STM32_SAI2_B_SYNC_WITH_A stm32_configgpio(GPIO_SAI2_FS_B); stm32_configgpio(GPIO_SAI2_SCK_B); stm32_configgpio(GPIO_SAI2_MCLK_B); diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index f33087ecc8d..bea2a35c088 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -50,7 +50,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_sdmmc.h" -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -62,7 +62,7 @@ * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. - * CONFIG_STM32L4_DMA2 - Enable STM32 DMA2 support. Required if + * CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * @@ -71,27 +71,27 @@ * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_STM32L4_SDMMC_DMA - Enable SDMMC. This is a marginally + * CONFIG_STM32_SDMMC_DMA - Enable SDMMC. This is a marginally * optional. For most usages, SDMMC will cause data overruns if used * without DMA. NOTE the above system DMA configuration options. * CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). * CONFIG_SDMMC_DMAPRIO - SDMMC DMA priority. This can be selected if - * CONFIG_STM32L4_SDMMC_DMA is enabled. - * CONFIG_STM32L4_SDMMC_XFRDEBUG - Enables some very low-level + * CONFIG_STM32_SDMMC_DMA is enabled. + * CONFIG_STM32_SDMMC_XFRDEBUG - Enables some very low-level * debug output. This also requires CONFIG_DEBUG_FS and * CONFIG_DEBUG_INFO */ -#ifndef CONFIG_STM32L4_SDMMC_DMA +#ifndef CONFIG_STM32_SDMMC_DMA # warning "Large Non-DMA transfer may result in RX overrun failures" #else -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error "CONFIG_STM32L4_SDMMC_DMA support requires CONFIG_STM32L4_DMA2" +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error "CONFIG_STM32_SDMMC_DMA support requires CONFIG_STM32_DMA2" # endif # ifndef CONFIG_SDIO_DMA -# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32L4_SDMMC_DMA +# error CONFIG_SDIO_DMA must be defined with CONFIG_STM32_SDMMC_DMA # endif #endif @@ -99,34 +99,34 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" #endif -#ifdef CONFIG_STM32L4_SDMMC1 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC1_DMAPRIO -# define CONFIG_STM32L4_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC1 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC1_DMAPRIO +# define CONFIG_STM32_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC1_DMAPRIO" +# if (CONFIG_STM32_SDMMC1_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC1_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC1_DMAPRIO +# undef CONFIG_STM32_SDMMC1_DMAPRIO # endif #endif -#ifdef CONFIG_STM32L4_SDMMC2 -# ifdef CONFIG_STM32L4_SDMMC_DMA -# ifndef CONFIG_STM32L4_SDMMC2_DMAPRIO -# define CONFIG_STM32L4_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32_SDMMC2 +# ifdef CONFIG_STM32_SDMMC_DMA +# ifndef CONFIG_STM32_SDMMC2_DMAPRIO +# define CONFIG_STM32_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI # endif -# if (CONFIG_STM32L4_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_STM32L4_SDMMC2_DMAPRIO" +# if (CONFIG_STM32_SDMMC2_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_STM32_SDMMC2_DMAPRIO" # endif # else -# undef CONFIG_STM32L4_SDMMC2_DMAPRIO +# undef CONFIG_STM32_SDMMC2_DMAPRIO # endif #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_STM32L4_SDMMC_XFRDEBUG +# undef CONFIG_STM32_SDMMC_XFRDEBUG #endif /* Friendly CLKCR bit re-definitions ****************************************/ @@ -288,8 +288,8 @@ /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG -# ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG +# ifdef CONFIG_STM32_SDMMC_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 # define SAMPLENDX_AFTER_SETUP 2 @@ -321,7 +321,7 @@ struct stm32_dev_s #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE uint32_t d0_gpio; #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA uint32_t dmapri; #endif @@ -351,7 +351,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ bool onebit; /* true: Only 1-bit transfers are supported */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ @@ -360,7 +360,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -377,7 +377,7 @@ struct stm32_sdioregs_s struct stm32_sampleregs_s { struct stm32_sdioregs_s sdio; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) struct stm32_dmaregs_s dma; #endif }; @@ -400,7 +400,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void); static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs); @@ -415,7 +415,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv); # define stm32_dumpsamples(priv) #endif -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); #endif @@ -490,7 +490,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, /* DMA */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen); @@ -510,7 +510,7 @@ static void stm32_default(struct stm32_dev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 struct stm32_dev_s g_sdmmcdev1 = { .dev = @@ -546,7 +546,7 @@ struct stm32_dev_s g_sdmmcdev1 = .registercallback = stm32_registercallback, #endif #ifdef CONFIG_SDIO_DMA -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA #ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT .dmapreflight = stm32_dmapreflight, #endif @@ -566,13 +566,13 @@ struct stm32_dev_s g_sdmmcdev1 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC1_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC1_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC1_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC1_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC1_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 struct stm32_dev_s g_sdmmcdev2 = { .dev = @@ -620,8 +620,8 @@ struct stm32_dev_s g_sdmmcdev2 = #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE .d0_gpio = GPIO_SDMMC2_D0, #endif -#ifdef CONFIG_STM32L4_SDMMC2_DMAPRIO - .dmapri = CONFIG_STM32L4_SDMMC2_DMAPRIO, +#ifdef CONFIG_STM32_SDMMC2_DMAPRIO + .dmapri = CONFIG_STM32_SDMMC2_DMAPRIO, #endif .waitsem = SEM_INITIALIZER(0), }; @@ -629,7 +629,7 @@ struct stm32_dev_s g_sdmmcdev2 = /* Register logging support */ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -779,7 +779,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, priv->waitevents = waitevents; priv->wkupevent = wkupevent; priv->waitmask = waitmask; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, @@ -847,7 +847,7 @@ static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, @@ -863,7 +863,7 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiosample(struct stm32_dev_s *priv, struct stm32_sdioregs_s *regs) { @@ -887,12 +887,12 @@ static void stm32_sdiosample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmasample(priv->dma, ®s->dma); @@ -911,7 +911,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { mcinfo("SDIO Registers: %s\n", msg); @@ -941,12 +941,12 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dmadump(priv->dma, ®s->dma, msg); @@ -965,13 +965,13 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_XFRDEBUG +#ifdef CONFIG_STM32_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], @@ -984,7 +984,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer"); -#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32L4_SDMMC_DMA) +#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32_SDMMC_DMA) if (priv->dmamode) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], @@ -1002,7 +1002,7 @@ static void stm32_dumpsamples(struct stm32_dev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) { struct stm32_dev_s *priv = (struct stm32_dev_s *)arg; @@ -1361,7 +1361,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* DMA debug instrumentation */ @@ -1453,7 +1453,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) pending = enabled & priv->xfrmask; if (pending != 0) { -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (!priv->dmamode) #endif { @@ -1492,7 +1492,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg) /* Was this transfer performed in DMA mode? */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Yes.. Terminate the transfers only if the DMA has also @@ -1684,7 +1684,7 @@ static void stm32_reset(struct sdio_dev_s *dev) priv->waitevents = 0; /* Set of events to be waited for */ priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; /* Used to synchronize SDIO and DMA * completion events */ #endif @@ -1700,7 +1700,7 @@ static void stm32_reset(struct sdio_dev_s *dev) /* DMA data transfer support */ priv->widebus = false; /* Required for DMA support */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; /* true: DMA mode transfer */ #endif @@ -1739,7 +1739,7 @@ static sdio_capset_t stm32_capabilities(struct sdio_dev_s *dev) caps |= SDIO_CAPS_1BIT_ONLY; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA caps |= SDIO_CAPS_DMASUPPORTED; #endif @@ -2010,7 +2010,7 @@ static int stm32_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2065,7 +2065,7 @@ static int stm32_sendsetup(struct sdio_dev_s *dev, const priv->buffer = (uint32_t *)buffer; priv->remaining = nbytes; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->dmamode = false; #endif @@ -2119,7 +2119,7 @@ static int stm32_cancel(struct sdio_dev_s *dev) /* If this was a DMA transfer, make sure that DMA is stopped */ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA if (priv->dmamode) { /* Make sure that the DMA is stopped (it will be stopped automatically @@ -2644,7 +2644,7 @@ static sdio_eventset_t stm32_eventwait(struct sdio_dev_s *dev) errout_with_waitints: stm32_configwaitints(priv, 0, 0, 0); -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA priv->xfrflags = 0; #endif @@ -2741,7 +2741,7 @@ static int stm32_registercallback(struct sdio_dev_s *dev, * OK on success; a negated errno on failure ****************************************************************************/ -#if defined(CONFIG_STM32L4_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +#if defined(CONFIG_STM32_SDMMC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) static int stm32_dmapreflight(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -2777,7 +2777,7 @@ static int stm32_dmapreflight(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen) { @@ -2848,7 +2848,7 @@ static int stm32_dmarecvsetup(struct sdio_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA static int stm32_dmasendsetup(struct sdio_dev_s *dev, const uint8_t *buffer, size_t buflen) { @@ -3028,18 +3028,18 @@ static void stm32_default(struct stm32_dev_s *priv) struct sdio_dev_s *sdio_initialize(int slotno) { struct stm32_dev_s *priv = NULL; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA unsigned int dmachan; #endif -#ifdef CONFIG_STM32L4_SDMMC1 +#ifdef CONFIG_STM32_SDMMC1 if (slotno == 0) { /* Select SDMMC 1 */ priv = &g_sdmmcdev1; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC1_DMACHAN; #endif @@ -3068,14 +3068,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) } else #endif -#ifdef CONFIG_STM32L4_SDMMC2 +#ifdef CONFIG_STM32_SDMMC2 if (slotno == 1) { /* Select SDMMC 2 */ priv = &g_sdmmcdev2; -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA dmachan = SDMMC2_DMACHAN; #endif @@ -3110,7 +3110,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) return NULL; } -#ifdef CONFIG_STM32L4_SDMMC_DMA +#ifdef CONFIG_STM32_SDMMC_DMA /* Allocate a DMA channel */ priv->dma = stm32_dmachannel(dmachan); @@ -3211,4 +3211,4 @@ void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32L4_SDMMC1 || CONFIG_STM32L4_SDMMC2 */ +#endif /* CONFIG_STM32_SDMMC1 || CONFIG_STM32_SDMMC2 */ diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index f286b0cdf67..1e3180a641b 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -79,14 +79,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L4_DMA1) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32L4_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L4_DMA2) && !defined(CONFIG_STM32L4_DMAMUX) -# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32L4_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L4 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -113,7 +113,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L4_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -146,11 +146,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L4_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -182,8 +182,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L4_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L4_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -197,7 +197,7 @@ * See stm32l4serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -391,7 +391,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -399,7 +399,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -407,7 +407,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -415,7 +415,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -423,7 +423,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -431,7 +431,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -441,7 +441,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 LPUART1 port. */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -503,7 +503,7 @@ static struct stm32_serial_s g_lpuart1priv = /* This describes the state of the STM32 USART1 port. */ -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -565,7 +565,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -627,7 +627,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -689,7 +689,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -751,7 +751,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -816,22 +816,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1076,7 +1076,7 @@ static void stm32l4serial_setbaud_usart(struct stm32_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static void stm32l4serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -1121,7 +1121,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { stm32l4serial_setbaud_lpuart(priv); @@ -1191,7 +1191,7 @@ static void stm32l4serial_setformat(struct uart_dev_s *dev) regval = stm32l4serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1395,37 +1395,37 @@ static void stm32l4serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1494,7 +1494,7 @@ static int stm32l4serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L4_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1844,8 +1844,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L4_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L4_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1991,7 +1991,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L4_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2060,7 +2060,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L4_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2111,7 +2111,7 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L4_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2248,8 +2248,8 @@ static int stm32l4serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L4_USART_BREAKS -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2480,7 +2480,7 @@ static bool stm32l4serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L4_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2836,7 +2836,7 @@ static void stm32l4serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L4_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3177,7 +3177,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3206,7 +3206,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L4_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32l4/stm32l4_spi.c b/arch/arm/src/stm32l4/stm32l4_spi.c index b69995cb042..8eb04f9ef9e 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.c +++ b/arch/arm/src/stm32l4/stm32l4_spi.c @@ -80,8 +80,8 @@ #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -91,19 +91,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L4_SPI_INTERRUPTS) && defined(CONFIG_STM32L4_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -137,10 +137,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -185,7 +185,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -247,7 +247,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -287,10 +287,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,7 +305,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -345,10 +345,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,7 +361,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -401,10 +401,10 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L4_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -635,7 +635,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -668,7 +668,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -701,7 +701,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -716,7 +716,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -731,7 +731,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -751,7 +751,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -771,7 +771,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -822,7 +822,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, @@ -874,7 +874,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -890,7 +890,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1354,8 +1354,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L4_SPI_DMA) || defined(CONFIG_STM32L4_DMACAPABLE) -#if !defined(CONFIG_STM32L4_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1438,7 +1438,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L4_SPI_DMA || CONFIG_STM32L4_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1461,14 +1461,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1530,7 +1530,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L4_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1551,7 +1551,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1756,7 +1756,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L4_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If @@ -1810,7 +1810,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1835,7 +1835,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1860,7 +1860,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1893,4 +1893,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l4/stm32l4_spi.h b/arch/arm/src/stm32l4/stm32l4_spi.h index e71e9c67e46..12c8d4fe1be 100644 --- a/arch/arm/src/stm32l4/stm32l4_spi.h +++ b/arch/arm/src/stm32l4/stm32l4_spi.h @@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,19 +146,19 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 561447051ad..411490c5bbc 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -129,7 +129,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L4_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32l4/stm32l4_tickless.c b/arch/arm/src/stm32l4/stm32l4_tickless.c index 164b1b62f41..541399ba038 100644 --- a/arch/arm/src/stm32l4/stm32l4_tickless.c +++ b/arch/arm/src/stm32l4/stm32l4_tickless.c @@ -87,20 +87,20 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_ONESHOT -# error CONFIG_STM32L4_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_ONESHOT +# error CONFIG_STM32_ONESHOT must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_FREERUN -# error CONFIG_STM32L4_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_FREERUN +# error CONFIG_STM32_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_FREERUN -# error CONFIG_STM32L4_TICKLESS_FREERUN must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_FREERUN +# error CONFIG_STM32_TICKLESS_FREERUN must be selected for the Tickless OS option #endif -#ifndef CONFIG_STM32L4_TICKLESS_ONESHOT -# error CONFIG_STM32L4_TICKLESS_ONESHOT must be selected for the Tickless OS option +#ifndef CONFIG_STM32_TICKLESS_ONESHOT +# error CONFIG_STM32_TICKLESS_ONESHOT must be selected for the Tickless OS option #endif /**************************************************************************** @@ -186,7 +186,7 @@ void up_timer_initialize(void) /* Initialize the one-shot timer */ ret = stm32_oneshot_initialize(&g_tickless.oneshot, - CONFIG_STM32L4_TICKLESS_ONESHOT, + CONFIG_STM32_TICKLESS_ONESHOT, CONFIG_USEC_PER_TICK); if (ret < 0) { @@ -220,7 +220,7 @@ void up_timer_initialize(void) /* Initialize the free-running timer */ ret = stm32_freerun_initialize(&g_tickless.freerun, - CONFIG_STM32L4_TICKLESS_FREERUN, + CONFIG_STM32_TICKLESS_FREERUN, CONFIG_USEC_PER_TICK); if (ret < 0) { diff --git a/arch/arm/src/stm32l4/stm32l4_tim.c b/arch/arm/src/stm32l4/stm32l4_tim.c index d6b08e28659..86f354b0445 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim.c +++ b/arch/arm/src/stm32l4/stm32l4_tim.c @@ -72,118 +72,118 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) || defined (CONFIG_STM32L4_TIM1_ADC) || \ - defined(CONFIG_STM32L4_TIM1_DAC) || defined(CONFIG_STM32L4_TIM1_QE) -# undef CONFIG_STM32L4_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) || defined (CONFIG_STM32L4_TIM2_ADC) || \ - defined(CONFIG_STM32L4_TIM2_DAC) || defined(CONFIG_STM32L4_TIM2_QE) -# undef CONFIG_STM32L4_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) || defined (CONFIG_STM32L4_TIM3_ADC) || \ - defined(CONFIG_STM32L4_TIM3_DAC) || defined(CONFIG_STM32L4_TIM3_QE) -# undef CONFIG_STM32L4_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) || defined (CONFIG_STM32L4_TIM4_ADC) || \ - defined(CONFIG_STM32L4_TIM4_DAC) || defined(CONFIG_STM32L4_TIM4_QE) -# undef CONFIG_STM32L4_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) || defined (CONFIG_STM32L4_TIM5_ADC) || \ - defined(CONFIG_STM32L4_TIM5_DAC) || defined(CONFIG_STM32L4_TIM5_QE) -# undef CONFIG_STM32L4_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32L4_TIM6_ADC) || \ - defined(CONFIG_STM32L4_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE) -# undef CONFIG_STM32L4_TIM6 +#if defined(CONFIG_STM32L4_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L4_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32L4_TIM7_PWM) || defined (CONFIG_STM32L4_TIM7_ADC) || \ - defined(CONFIG_STM32L4_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE) -# undef CONFIG_STM32L4_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L4_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) || defined (CONFIG_STM32L4_TIM8_ADC) || \ - defined(CONFIG_STM32L4_TIM8_DAC) || defined(CONFIG_STM32L4_TIM8_QE) -# undef CONFIG_STM32L4_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) || defined (CONFIG_STM32L4_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32L4_TIM15_DAC) || defined(CONFIG_STM32L4_TIM15_QE) -# undef CONFIG_STM32L4_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L4_TIM16_ADC) || \ defined(CONFIG_STM32L4_TIM16_DAC) || defined(CONFIG_STM32L4_TIM16_QE) -# undef CONFIG_STM32L4_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L4_TIM17_ADC) || \ defined(CONFIG_STM32L4_TIM17_DAC) || defined(CONFIG_STM32L4_TIM17_QE) -# undef CONFIG_STM32L4_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L4_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -194,12 +194,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -305,7 +305,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .dump_regs = stm32_tim_dumpregs, }; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -313,7 +313,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -322,7 +322,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -331,7 +331,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -340,7 +340,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -349,7 +349,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -358,7 +358,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -367,7 +367,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -376,7 +376,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -385,7 +385,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -394,7 +394,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -713,66 +713,66 @@ static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -872,66 +872,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -986,64 +986,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -1092,13 +1092,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L4_TIM2) || defined(CONFIG_STM32L4_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: #endif return counter; @@ -1204,7 +1204,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1237,7 +1237,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1270,7 +1270,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1303,7 +1303,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1335,7 +1335,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1368,7 +1368,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1401,7 +1401,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1434,7 +1434,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1467,7 +1467,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1583,65 +1583,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1726,76 +1726,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1833,66 +1833,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1909,4 +1909,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32L4_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c index c01128d68c3..1c60f9abcf5 100644 --- a/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c +++ b/arch/arm/src/stm32l4/stm32l4_tim_lowerhalf.c @@ -60,12 +60,12 @@ #include "stm32l4_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L4_TIM1) || defined(CONFIG_STM32L4_TIM2) || \ - defined(CONFIG_STM32L4_TIM3) || defined(CONFIG_STM32L4_TIM4) || \ - defined(CONFIG_STM32L4_TIM5) || defined(CONFIG_STM32L4_TIM6) || \ - defined(CONFIG_STM32L4_TIM7) || defined(CONFIG_STM32L4_TIM8) || \ - defined(CONFIG_STM32L4_TIM15) || defined(CONFIG_STM32L4_TIM16) || \ - defined(CONFIG_STM32L4_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -137,7 +137,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -145,7 +145,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -153,7 +153,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -161,7 +161,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -169,7 +169,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -177,7 +177,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -185,7 +185,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -193,7 +193,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -201,7 +201,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -209,7 +209,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -217,7 +217,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -522,66 +522,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index 8af667ad4a0..83b4e34a84e 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -32,8 +32,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X5) || \ - defined(CONFIG_STM32L4_STM32L4X6) || defined(CONFIG_STM32L4_STM32L4XR) +#if defined(CONFIG_STM32_STM32L4X3) || defined(CONFIG_STM32_STM32L4X5) || \ + defined(CONFIG_STM32_STM32L4X6) || defined(CONFIG_STM32_STM32L4XR) # include "hardware/stm32l4_uart.h" #else # error "Unsupported STM32L4 chip" @@ -47,63 +47,63 @@ * the device. */ -#if !defined(CONFIG_STM32L4_HAVE_UART5) -# undef CONFIG_STM32L4_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L4_HAVE_UART4) -# undef CONFIG_STM32L4_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART3) -# undef CONFIG_STM32L4_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART2) -# undef CONFIG_STM32L4_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L4_HAVE_USART1) -# undef CONFIG_STM32L4_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L4_HAVE_LPUART1) -# undef CONFIG_STM32L4_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L4_LPUART1) -# undef CONFIG_STM32L4_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L4_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART1) -# undef CONFIG_STM32L4_USART1_SERIALDRIVER -# undef CONFIG_STM32L4_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART2) -# undef CONFIG_STM32L4_USART2_SERIALDRIVER -# undef CONFIG_STM32L4_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_USART3) -# undef CONFIG_STM32L4_USART3_SERIALDRIVER -# undef CONFIG_STM32L4_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART4) -# undef CONFIG_STM32L4_UART4_SERIALDRIVER -# undef CONFIG_STM32L4_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L4_UART5) -# undef CONFIG_STM32L4_UART5_SERIALDRIVER -# undef CONFIG_STM32L4_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L4_LPUART1) || defined(CONFIG_STM32L4_USART1) || \ - defined(CONFIG_STM32L4_USART2) || defined(CONFIG_STM32L4_USART3) || \ - defined(CONFIG_STM32L4_UART4) || defined(CONFIG_STM32L4_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -111,7 +111,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -119,7 +119,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -127,7 +127,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -135,7 +135,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -143,7 +143,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L4_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE @@ -177,27 +177,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L4_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L4_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L4_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L4_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L4_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -230,17 +230,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L4_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L4_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32l4/stm32l4_usbdev.c b/arch/arm/src/stm32l4/stm32l4_usbdev.c index 017b8f18a20..5bbac6ed9b7 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbdev.c +++ b/arch/arm/src/stm32l4/stm32l4_usbdev.c @@ -49,7 +49,7 @@ #include "stm32l4_gpio.h" #include "stm32l4_usbdev.h" -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USBFS) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USBFS) /**************************************************************************** * Pre-processor Definitions @@ -70,7 +70,7 @@ */ #ifndef CONFIG_DEBUG_USB_INFO -# undef CONFIG_STM32L4_USBDEV_REGDEBUG +# undef CONFIG_STM32_USBDEV_REGDEBUG #endif /* Initial interrupt mask: Reset + Suspend + Correct Transfer */ @@ -351,7 +351,7 @@ struct stm32_usbdev_s /* Register operations ******************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr); static void stm32_putreg(uint16_t val, uint32_t addr); static void stm32_checksetup(void); @@ -618,7 +618,7 @@ const struct trace_msg_t g_usb_trace_strings_deverror[] = * Name: stm32_getreg ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static uint16_t stm32_getreg(uint32_t addr) { static uint32_t prevaddr = 0; @@ -677,7 +677,7 @@ static uint16_t stm32_getreg(uint32_t addr) * Name: stm32_putreg ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ @@ -694,7 +694,7 @@ static void stm32_putreg(uint16_t val, uint32_t addr) * Name: stm32_dumpep ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_dumpep(int epno) { uint32_t addr; @@ -737,7 +737,7 @@ static void stm32_dumpep(int epno) * Name: stm32_checksetup ****************************************************************************/ -#ifdef CONFIG_STM32L4_USBDEV_REGDEBUG +#ifdef CONFIG_STM32_USBDEV_REGDEBUG static void stm32_checksetup(void) { uint32_t cfgr = getreg32(STM32_RCC_CFGR); @@ -3939,4 +3939,4 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver) return OK; } -#endif /* CONFIG_USBDEV && CONFIG_STM32L4_USB */ +#endif /* CONFIG_USBDEV && CONFIG_STM32_USB */ diff --git a/arch/arm/src/stm32l4/stm32l4_usbhost.h b/arch/arm/src/stm32l4/stm32l4_usbhost.h index 92fe5d17a78..d38e24247ce 100644 --- a/arch/arm/src/stm32l4/stm32l4_usbhost.h +++ b/arch/arm/src/stm32l4/stm32l4_usbhost.h @@ -34,11 +34,11 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_OTGFS) && defined(CONFIG_USBHOST) +#if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) -#if defined(CONFIG_STM32L4_STM32L4X5) +#if defined(CONFIG_STM32_STM32L4X5) # include "hardware/stm32l4x5xx_otgfs.h" -#elif defined(CONFIG_STM32L4_STM32L4X6) +#elif defined(CONFIG_STM32_STM32L4X6) # include "hardware/stm32l4x6xx_otgfs.h" #else # error "Unsupported STM32L4 chip" @@ -134,21 +134,21 @@ enum usbhost_trace1codes_e * Pre-requisites * * CONFIG_USBHOST - Enable general USB host support - * CONFIG_STM32L4_OTGFS - Enable the STM32 USB OTG FS block - * CONFIG_STM32L4_SYSCFG - Needed + * CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32_SYSCFG - Needed * * Options: * - * CONFIG_STM32L4_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. * Default 128 (512 bytes) - * CONFIG_STM32L4_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO * in 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in + * CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in * 32-bit words. Default 96 (384 bytes) - * CONFIG_STM32L4_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever + * CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever * want to do that? * - * CONFIG_STM32L4_USBHOST_REGDEBUG - Enable very low-level register access + * CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access * debug. Depends on CONFIG_DEBUG. */ @@ -204,5 +204,5 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32L4_OTGFS && CONFIG_USBHOST */ +#endif /* CONFIG_STM32_OTGFS && CONFIG_USBHOST */ #endif /* __ARCH_ARM_SRC_STM32L4_STM32L4_USBHOST_H */ diff --git a/arch/arm/src/stm32l4/stm32l4_wdg.h b/arch/arm/src/stm32l4/stm32l4_wdg.h index 7d7bbfb8d37..aced6a146c9 100644 --- a/arch/arm/src/stm32l4/stm32l4_wdg.h +++ b/arch/arm/src/stm32l4/stm32l4_wdg.h @@ -71,7 +71,7 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_STM32L4_IWDG +#ifdef CONFIG_STM32_IWDG void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); #endif @@ -92,7 +92,7 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_WWDG +#ifdef CONFIG_STM32_WWDG void stm32_wwdginitialize(const char *devpath); #endif diff --git a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c index a558bbaa59f..5c46cc182bc 100644 --- a/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x3xx_rcc.c @@ -55,7 +55,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -130,25 +130,25 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; @@ -198,19 +198,19 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -237,7 +237,7 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -264,91 +264,91 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR1_USBFSEN; @@ -369,19 +369,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -393,25 +393,25 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -438,7 +438,7 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -446,55 +446,55 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; @@ -523,19 +523,19 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -553,14 +553,14 @@ static inline void rcc_enableccip(void) regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -577,7 +577,7 @@ static inline void rcc_enableccip(void) /* I2C4 alone has their clock selection in CCIPR2 register. */ #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ @@ -600,7 +600,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -790,7 +790,7 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -825,7 +825,7 @@ static void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ regval = getreg32(STM32_RCC_PLLSAI2CFG); @@ -861,7 +861,7 @@ static void stm32_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -883,7 +883,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c index 5dadb8cb232..254efbeb45b 100644 --- a/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x5xx_rcc.c @@ -121,25 +121,25 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; @@ -194,19 +194,19 @@ static inline void rcc_enableahb2(void) ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -233,13 +233,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -266,97 +266,97 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; @@ -368,19 +368,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -392,19 +392,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -431,7 +431,7 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -439,73 +439,73 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; @@ -534,19 +534,19 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -564,14 +564,14 @@ static inline void rcc_enableccip(void) regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; @@ -590,7 +590,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -780,7 +780,7 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -815,7 +815,7 @@ static void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ regval = getreg32(STM32_RCC_PLLSAI2CFG); @@ -851,7 +851,7 @@ static void stm32_stdclockconfig(void) * and 4 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -873,7 +873,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c index bf916f033a9..3d9f0a7f91a 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_dma.c @@ -621,7 +621,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { uint32_t transfer_size; diff --git a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c index 5e14421ea49..7e2aedd4736 100644 --- a/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4x6xx_rcc.c @@ -55,7 +55,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -130,31 +130,31 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; @@ -212,37 +212,37 @@ static inline void rcc_enableahb2(void) ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -269,13 +269,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; #endif -#ifdef CONFIG_STM32L4_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; @@ -302,109 +302,109 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; #endif -#ifdef CONFIG_STM32L4_CAN2 +#ifdef CONFIG_STM32_CAN2 /* CAN 2 clock enable */ regval |= RCC_APB1ENR1_CAN2EN; @@ -425,19 +425,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -449,25 +449,25 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_SWPMI +#ifdef CONFIG_STM32_SWPMI /* Single-wire protocol master clock enable */ regval |= RCC_APB1ENR2_SWPMI1EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -494,7 +494,7 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -502,73 +502,73 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_APB2ENR_SDMMCEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; @@ -597,19 +597,19 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -627,14 +627,14 @@ static inline void rcc_enableccip(void) regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ regval |= RCC_CCIPR_DFSDMSEL_SYSCLK; @@ -645,7 +645,7 @@ static inline void rcc_enableccip(void) /* I2C4 alone has their clock selection in CCIPR2 register. */ #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ @@ -668,7 +668,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -683,7 +683,7 @@ static void stm32_stdclockconfig(void) * and freq */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -901,7 +901,7 @@ static void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -936,7 +936,7 @@ static void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ regval = getreg32(STM32_RCC_PLLSAI2CFG); @@ -999,7 +999,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c index 735ce580c69..0c7891e3187 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_dma.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_dma.c @@ -45,23 +45,23 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_DMAMUX -# error "Configuration error, CONFIG_STM32L4_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif -#ifndef CONFIG_STM32L4_DMAMUX1 -# error "Configuration error, CONFIG_STM32L4_DMAMUX1 not defined!" +#ifndef CONFIG_STM32_DMAMUX1 +# error "Configuration error, CONFIG_STM32_DMAMUX1 not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -166,7 +166,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_dma12_disable(DMA_CHANNEL dmachan); static int stm32_dma12_interrupt(int irq, void *context, void *arg); static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -212,7 +212,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -232,7 +232,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -293,7 +293,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -353,7 +353,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -571,7 +571,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32L4_DMA1) || defined(CONFIG_STM32L4_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_dma12_disable @@ -623,14 +623,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { channel = irq - STM32_IRQ_DMA2CH1; @@ -696,7 +696,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -885,7 +885,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32L4_DMA1 || CONFIG_STM32L4_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32_dmamux_sample @@ -1277,7 +1277,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index c6a08bed6d2..e3a42befec0 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -55,7 +55,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L4_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -130,37 +130,37 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L4_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32L4_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L4_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L4_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L4_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32L4_DMA2D +#ifdef CONFIG_STM32_DMA2D /* DMA2D clock enable */ regval |= RCC_AHB1ENR_DMA2DEN; @@ -218,43 +218,43 @@ static inline void rcc_enableahb2(void) ); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* USB OTG FS clock enable */ regval |= RCC_AHB2ENR_OTGFSEN; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L4_DCMI +#ifdef CONFIG_STM32_DCMI /* Digital Camera interfaces clock enable */ regval |= RCC_AHB2ENR_DCMIEN; #endif -#ifdef CONFIG_STM32L4_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L4_HASH +#ifdef CONFIG_STM32_HASH /* HASH module clock enable */ regval |= RCC_AHB2ENR_HASHEN; #endif -#ifdef CONFIG_STM32L4_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; #endif -#ifdef CONFIG_STM32L4_SDMMC +#ifdef CONFIG_STM32_SDMMC /* SDMMC clock enable */ regval |= RCC_AHB2ENR_SDMMC1EN; @@ -281,7 +281,7 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L4_FSMC +#ifdef CONFIG_STM32_FSMC /* Flexible static memory controller module clock enable */ regval |= RCC_AHB3ENR_FSMCEN; @@ -308,97 +308,97 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L4_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L4_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L4_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L4_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 /* CAN 1 clock enable */ regval |= RCC_APB1ENR1_CAN1EN; @@ -419,19 +419,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L4_DAC1) || defined(CONFIG_STM32L4_DAC2) +#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L4_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L4_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -443,19 +443,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L4_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L4_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -482,7 +482,7 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L4_SYSCFG) || defined(CONFIG_STM32L4_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -490,67 +490,67 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L4_FIREWALL +#ifdef CONFIG_STM32_FIREWALL /* Firewall clock enable */ regval |= RCC_APB2ENR_FWEN; #endif -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L4_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L4_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L4_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; @@ -579,19 +579,19 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval &= ~RCC_CCIPR_I2C2SEL_MASK; regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -609,7 +609,7 @@ static inline void rcc_enableccip(void) regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32L4_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; @@ -623,7 +623,7 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR2); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32L4_I2C4 +#ifdef CONFIG_STM32_I2C4 /* Select HSI16 as I2C4 clock source. */ regval &= ~RCC_CCIPR2_I2C4SEL_MASK; @@ -631,7 +631,7 @@ static inline void rcc_enableccip(void) #endif #endif -#ifdef CONFIG_STM32L4_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SAI1 as DFSDM audio clock source. */ regval &= ~RCC_CCIPR2_ADFSDMSEL_MASK; @@ -655,7 +655,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -850,7 +850,7 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32L4_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -885,7 +885,7 @@ static void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L4_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ regval = getreg32(STM32_RCC_PLLSAI2CFG); @@ -927,7 +927,7 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval |= (FLASH_ACR_ICEN | FLASH_ACR_DCEN); @@ -948,7 +948,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig index bc12730b681..43733a0c041 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/Kconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/Kconfig @@ -8,8 +8,8 @@ if ARCH_BOARD_B_L475E_IOT01A config B_L475E_IOT01A_MTD_FLASH bool "MTD driver for external 64Mbits flash memory" default n - select STM32L4_DMA1 - select STM32L4_QSPI + select STM32_DMA1 + select STM32_QSPI select MTD select MTD_MX25RXX select MTD_SMART diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig index 7fbc7b18e1f..39a2d9d018f 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -40,8 +41,8 @@ CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 -CONFIG_STM32L4_QSPI_FLASH_SIZE=8388608 -CONFIG_STM32L4_USART1=y +CONFIG_STM32_QSPI_FLASH_SIZE=8388608 +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_WATCHDOG=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig index 180321aac4b..3ad6b86f7b6 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-6lowpan/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -85,8 +86,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig index 63f9c072fd5..fe4ac62a657 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starhub/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -76,8 +77,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig index fd31a0624c1..de16e10426d 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig +++ b/boards/arm/stm32l4/b-l475e-iot01a/configs/spirit-starpoint/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l475e-iot01a" CONFIG_ARCH_BOARD_B_L475E_IOT01A=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L475VG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_STACKDUMP=y @@ -87,8 +88,8 @@ CONFIG_SPIRIT_NETDEV=y CONFIG_SPIRIT_PKTLEN=94 CONFIG_START_DAY=2 CONFIG_START_MONTH=8 -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_USART1=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_TELNET_CLIENT=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h index 47a7f317e0d..d1cc8a29580 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/b-l475e-iot01a_clock.h @@ -149,7 +149,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -175,7 +175,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h index 9d7cd5733aa..7a92708cf83 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/b-l475e-iot01a.h @@ -46,7 +46,7 @@ /* SPSGRF support depends on: * - * CONFIG_STM32L4_SPI3 - SPI3 support + * CONFIG_STM32_SPI3 - SPI3 support * CONFIG_WL_SPIRIT - Spirit wireless library * CONFIG_SPIRIT_NETDEV - Spirit network driver * CONFIG_SCHED_HPWORK - HP work queue support @@ -57,7 +57,7 @@ * And probably a few other things. */ -#if !defined(CONFIG_STM32L4_SPI3) +#if !defined(CONFIG_STM32_SPI3) # undef HAVE_SPSGRF #endif @@ -73,7 +73,7 @@ # undef HAVE_SPSGRF #endif -#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32L4_QSPI) +#if !defined(CONFIG_MTD_MX25RXX) || !defined(CONFIG_STM32_QSPI) # undef HAVE_MX25R6435F #endif @@ -154,8 +154,8 @@ int stm32_bringup(void); * ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) void weak_function stm32_spidev_initialize(void); #endif diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index c49b58bebb5..550eb357b23 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -50,7 +50,7 @@ void stm32_board_initialize(void) { -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /* Configure SPI chip selects if * 1) SPI is not disabled, and 2) the weak function * stm32_spidev_initialize() has been brought into the link. diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c index 789daee3080..dac9cc457ea 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_spi.c @@ -45,16 +45,16 @@ /* Currently no devices are defined on SPI1 or SPI2 */ -#undef CONFIG_STM32L4_SPI1 -#undef CONFIG_STM32L4_SPI2 +#undef CONFIG_STM32_SPI1 +#undef CONFIG_STM32_SPI2 /* Only the SPSGRF is currently supported on SPI3 */ #ifndef HAVE_SPSGRF -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI3 #endif -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -62,15 +62,15 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -89,7 +89,7 @@ struct spi_dev_s *g_spi3; void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -101,7 +101,7 @@ void weak_function stm32_spidev_initialize(void) /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -109,7 +109,7 @@ void weak_function stm32_spidev_initialize(void) /* Configure chip select GPIOs */ #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices */ g_spi3 = stm32_spibus_initialize(3); @@ -148,7 +148,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,7 +162,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -176,7 +176,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -221,21 +221,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -243,4 +243,4 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c index 119d3f6c57f..ecfabfc0424 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_timer.c @@ -56,7 +56,7 @@ int stm32_timer_driver_setup(void) { int ret = OK; -#ifdef CONFIG_STM32L4_TIM1 +#ifdef CONFIG_STM32_TIM1 ret = stm32_timer_initialize("/dev/timer0", 1); if (ret < 0) { @@ -65,7 +65,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2 +#ifdef CONFIG_STM32_TIM2 ret = stm32_timer_initialize("/dev/timer1", 2); if (ret < 0) { @@ -74,7 +74,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3 +#ifdef CONFIG_STM32_TIM3 ret = stm32_timer_initialize("/dev/timer2", 3); if (ret < 0) { @@ -83,7 +83,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4 +#ifdef CONFIG_STM32_TIM4 ret = stm32_timer_initialize("/dev/timer3", 4); if (ret < 0) { @@ -92,7 +92,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5 +#ifdef CONFIG_STM32_TIM5 ret = stm32_timer_initialize("/dev/timer4", 5); if (ret < 0) { @@ -101,7 +101,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM6 +#ifdef CONFIG_STM32_TIM6 ret = stm32_timer_initialize("/dev/timer5", 6); if (ret < 0) { @@ -110,7 +110,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM7 +#ifdef CONFIG_STM32_TIM7 ret = stm32_timer_initialize("/dev/timer6", 7); if (ret < 0) { @@ -119,7 +119,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8 +#ifdef CONFIG_STM32_TIM8 ret = stm32_timer_initialize("/dev/timer7", 8); if (ret < 0) { @@ -128,7 +128,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM15 +#ifdef CONFIG_STM32_TIM15 ret = stm32_timer_initialize("/dev/timer8", 15); if (ret < 0) { @@ -137,7 +137,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM16 +#ifdef CONFIG_STM32_TIM16 ret = stm32_timer_initialize("/dev/timer9", 16); if (ret < 0) { @@ -146,7 +146,7 @@ int stm32_timer_driver_setup(void) } #endif -#ifdef CONFIG_STM32L4_TIM17 +#ifdef CONFIG_STM32_TIM17 ret = stm32_timer_initialize("/dev/timer10", 17); if (ret < 0) { diff --git a/boards/arm/stm32l4/nucleo-l432kc/Kconfig b/boards/arm/stm32l4/nucleo-l432kc/Kconfig index 7ed758a07d7..ba154e7dd94 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/Kconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/Kconfig @@ -6,13 +6,13 @@ if ARCH_BOARD_NUCLEO_L432KC menu "U[S]ART Pin Layouts" - depends on STM32L4_USART1 || STM32L4_USART2 || STM32L4_LPUART1 + depends on STM32_USART1 || STM32_USART2 || STM32_LPUART1 comment "USART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART1 + depends on !STM32_USART1 choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 RX pin" default ARCH_BOARD_USART1_RX_PA10 ---help--- @@ -29,7 +29,7 @@ config ARCH_BOARD_USART1_RX_PB7 endchoice choice - depends on STM32L4_USART1 + depends on STM32_USART1 prompt "USART1 TX pin" default ARCH_BOARD_USART1_TX_PA9 ---help--- @@ -46,10 +46,10 @@ config ARCH_BOARD_USART1_TX_PB6 endchoice comment "USART2 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_USART2 + depends on !STM32_USART2 choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 RX pin" default ARCH_BOARD_USART2_RX_PA15 ---help--- @@ -66,7 +66,7 @@ config ARCH_BOARD_USART2_RX_PA15 endchoice choice - depends on STM32L4_USART2 + depends on STM32_USART2 prompt "USART2 TX pin" default ARCH_BOARD_USART2_TX_PA2 ---help--- @@ -79,10 +79,10 @@ config ARCH_BOARD_USART2_TX_PA2 endchoice comment "LPUART1 is disabled. (Enable it under: System Type -> STM32L4 Peripheral Support)" - depends on !STM32L4_LPUART1 + depends on !STM32_LPUART1 choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 RX pin" default ARCH_BOARD_LPUART1_RX_PA3 ---help--- @@ -94,7 +94,7 @@ config ARCH_BOARD_LPUART1_RX_PA3 endchoice choice - depends on STM32L4_LPUART1 + depends on STM32_LPUART1 prompt "LPUART1 TX pin" default ARCH_BOARD_LPUART1_TX_PA2 ---help--- @@ -142,7 +142,7 @@ config NUCLEOL432KC_SPWM_PHASE_NUM endif menuconfig NUCLEOL432KC_DAC_WGEN - depends on (STM32L4_DAC_LL_OPS) && (STM32L4_DAC1_DMA) && (STM32L4_TIM2_DAC) + depends on (STM32_DAC_LL_OPS) && (STM32_DAC1_DMA) && (STM32_TIM2_DAC) bool "Sinusoidal DAC wave generator example" default n diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig index a897ae2145b..dbc3a0ea493 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig index 91ef99032a1..19d272a0fd5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/spwm/defconfig @@ -5,11 +5,12 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # -# CONFIG_STM32L4_SYSCFG is not set +# CONFIG_STM32_SYSCFG is not set CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_HIPRI_INTERRUPT=y @@ -36,17 +37,17 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWM_LL_OPS=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_CH1NOUT=y -CONFIG_STM32L4_TIM1_CH1OUT=y -CONFIG_STM32L4_TIM1_PWM=y -CONFIG_STM32L4_TIM6=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWM_LL_OPS=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_CH1NOUT=y +CONFIG_STM32_TIM1_CH1OUT=y +CONFIG_STM32_TIM1_PWM=y +CONFIG_STM32_TIM6=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_READLINE=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig index 433b98f9aab..49803835477 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig +++ b/boards/arm/stm32l4/nucleo-l432kc/configs/wgen/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l432kc" CONFIG_ARCH_BOARD_NUCLEO_L432KC=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L432KC=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,23 +48,23 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DAC1_DMA=y -CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE=40 -CONFIG_STM32L4_DAC1_TIMER=2 -CONFIG_STM32L4_DAC1_TIMER_FREQUENCY=2000 -CONFIG_STM32L4_DAC_LL_OPS=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM2=y -CONFIG_STM32L4_TIM2_DAC=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DAC1_DMA=y +CONFIG_STM32_DAC1_DMA_BUFFER_SIZE=40 +CONFIG_STM32_DAC1_TIMER=2 +CONFIG_STM32_DAC1_TIMER_FREQUENCY=2000 +CONFIG_STM32_DAC_LL_OPS=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM2=y +CONFIG_STM32_TIM2_DAC=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index a639e4fc63b..f073103529b 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -264,7 +264,7 @@ * CH1 | 1(A4) 2(A8) */ -#if defined(CONFIG_STM32L4_LPTIM2_CLK_APB1) +#if defined(CONFIG_STM32_LPTIM2_CLK_APB1) # define STM32_LPTIM2_FREQUENCY STM32_APB1_LPTIM2_CLKIN #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h index cacbf3ea929..7e86c5e1849 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/nucleo-l432kc.h @@ -146,7 +146,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -266,7 +266,7 @@ /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -363,7 +363,7 @@ /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -457,7 +457,7 @@ /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt index 4a419a02045..374e99abc25 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l432kc/src/CMakeLists.txt @@ -36,11 +36,11 @@ if(CONFIG_DEV_GPIO) list(APPEND SRCS stm32_gpio.c) endif() -if(CONFIG_STM32L4_ADC) +if(CONFIG_STM32_ADC) list(APPEND SRCS stm32_adc.c) endif() -if(CONFIG_STM32L4_DAC) +if(CONFIG_STM32_DAC) list(APPEND SRCS stm32_dac.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile b/boards/arm/stm32l4/nucleo-l432kc/src/Makefile index 10e16a6729f..6f1745c753a 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l432kc/src/Makefile @@ -38,11 +38,11 @@ ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += stm32_gpio.c endif -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32L4_DAC),y) +ifeq ($(CONFIG_STM32_DAC),y) CSRCS += stm32_dac.c endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h index 03bc8bc6c09..11dfbed2ee9 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h +++ b/boards/arm/stm32l4/nucleo-l432kc/src/nucleo-l432kc.h @@ -61,7 +61,7 @@ /* Check if we can support AT45DB FLASH file system */ -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MTD_AT45DB) +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MTD_AT45DB) # undef HAVE_AT45DB #endif @@ -108,10 +108,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c index e3cb1ffeec3..d1dfcba1bf4 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l432kc.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -46,7 +46,7 @@ /* The number of ADC channels in the conversion list */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA # define ADC1_NCHANNELS 2 #else # define ADC1_NCHANNELS 1 @@ -58,7 +58,7 @@ /* Identifying number of each ADC channel. */ -#ifdef CONFIG_STM32L4_ADC1_DMA +#ifdef CONFIG_STM32_ADC1_DMA static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = { @@ -87,7 +87,7 @@ static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = GPIO_ADC1_IN11_0 }; -#endif /* CONFIG_STM32L4_ADC1_DMA */ +#endif /* CONFIG_STM32_ADC1_DMA */ /**************************************************************************** * Private Functions @@ -139,4 +139,4 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c index 60218b2de0c..6c3c1d65e23 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_at45db.c @@ -42,7 +42,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "AT45DB driver requires CONFIG_STM32_SPI1 to be enabled" #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c index d8416cda87b..a370c0e67b1 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_boot.c @@ -72,8 +72,8 @@ void stm32_board_initialize(void) * function stm32_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) stm32_spiinitialize(); #endif @@ -82,7 +82,7 @@ void stm32_board_initialize(void) * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c index a5c437d9652..48ac6fff613 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_bringup.c @@ -58,7 +58,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if (defined(CONFIG_STM32L4_I2C1) || defined(CONFIG_STM32L4_I2C3)) && defined(CONFIG_I2C_DRIVER) +#if (defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3)) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif @@ -82,10 +82,10 @@ int stm32_bringup(void) #ifdef HAVE_RTC_DRIVER struct rtc_lowerhalf_s *rtclower; #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 struct i2c_master_s *i2c1; #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 struct i2c_master_s *i2c3; #endif #ifdef CONFIG_SENSORS_QENCODER @@ -151,7 +151,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Get the I2C lower half instance */ i2c1 = stm32_i2cbus_initialize(1); @@ -171,7 +171,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Get the I2C lower half instance */ i2c3 = stm32_i2cbus_initialize(3); @@ -220,7 +220,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_ADC +#ifdef CONFIG_STM32_ADC /* Initialize ADC and register the ADC driver. */ ret = stm32_adc_setup(); @@ -230,7 +230,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_DAC +#ifdef CONFIG_STM32_DAC /* Initialize DAC and register the DAC driver. */ ret = stm32_dac_setup(); @@ -298,7 +298,7 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 1); if (ret != OK) @@ -309,7 +309,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 2); if (ret != OK) @@ -320,7 +320,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 3); if (ret != OK) @@ -331,7 +331,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 4); if (ret != OK) @@ -342,7 +342,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 5); if (ret != OK) @@ -353,7 +353,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 8); if (ret != OK) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c index 21d0208c7cd..fd48f855ab3 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac.c @@ -41,7 +41,7 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac; #endif @@ -59,7 +59,7 @@ int stm32_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32_dacinitialize(0); diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c index 8b241b1398e..48cabb1d468 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac7571.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_DAC7571) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c index a98c0f1e492..140d8488f45 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_dac_wgen.c @@ -66,19 +66,19 @@ # error "CONFIG_DAC is required" #endif -#ifndef CONFIG_STM32L4_DAC1 -# error "CONFIG_STM32L4_DAC1 is required" +#ifndef CONFIG_STM32_DAC1 +# error "CONFIG_STM32_DAC1 is required" #endif -#ifndef CONFIG_STM32L4_DAC_LL_OPS -# error "CONFIG_STM32L4_DAC_LL_OPS is required" +#ifndef CONFIG_STM32_DAC_LL_OPS +# error "CONFIG_STM32_DAC_LL_OPS is required" #endif -#ifndef CONFIG_STM32L4_DAC1_DMA -# error "CONFIG_STM32L4_DAC1_DMA is required" +#ifndef CONFIG_STM32_DAC1_DMA +# error "CONFIG_STM32_DAC1_DMA is required" #endif -#if (CONFIG_STM32L4_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) +#if (CONFIG_STM32_DAC1_DMA_BUFFER_SIZE < CONFIG_NUCLEOL432KC_DAC_WGEN_SAMPLES) # error "DMA buffer size should be equal or greater than the number of samples." #endif diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c index bb07eb99530..89946981ece 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina219.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA219) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c index cd4a2e747da..49be6a531d5 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_ina226.c @@ -38,7 +38,7 @@ #include "chip.h" #include -#if defined(CONFIG_I2C) && defined(CONFIG_STM32L4_I2C1) && \ +#if defined(CONFIG_I2C) && defined(CONFIG_STM32_I2C1) && \ defined(CONFIG_SENSORS_INA226) /**************************************************************************** diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c index 95dc42e521a..6997424c275 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_pwm.c @@ -87,7 +87,7 @@ int stm32_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -105,7 +105,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -123,7 +123,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32_pwminitialize(15); if (!pwm) { @@ -141,7 +141,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32_pwminitialize(16); if (!pwm) { @@ -159,7 +159,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) pwm = stm32_lp_pwminitialize(1); if (!pwm) { @@ -177,7 +177,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM2_PWM) pwm = stm32_lp_pwminitialize(2); if (!pwm) { diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c index 06b202c9581..f52a6b7bbbf 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "nucleo-l432kc.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void stm32_spiregister(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int ret = spi_register(g_spi1, 1); if (ret < 0) { @@ -78,7 +78,7 @@ void stm32_spiregister(void) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int ret = spi_register(g_spi2, 2); if (ret < 0) { @@ -98,7 +98,7 @@ void stm32_spiregister(void) void stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI1-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -118,7 +118,7 @@ void stm32_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI2-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -161,7 +161,7 @@ void stm32_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -182,7 +182,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -220,14 +220,14 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -235,4 +235,4 @@ int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c index 48ce28fe0b6..c1842f4e555 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c +++ b/boards/arm/stm32l4/nucleo-l432kc/src/stm32_spwm.c @@ -81,10 +81,10 @@ /* Phase 1 is TIM1 CH1 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 0 -# ifndef CONFIG_STM32L4_TIM1_CH1OUT +# ifndef CONFIG_STM32_TIM1_CH1OUT # error # endif -# ifndef CONFIG_STM32L4_TIM6 +# ifndef CONFIG_STM32_TIM6 # error # endif # endif @@ -92,7 +92,7 @@ /* Phase 2 is TIM1 CH2 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 1 -# ifndef CONFIG_STM32L4_TIM1_CH2OUT +# ifndef CONFIG_STM32_TIM1_CH2OUT # error # endif # endif @@ -100,7 +100,7 @@ /* Phase 3 is TIM1 CH3 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 2 -# ifndef CONFIG_STM32L4_TIM1_CH3OUT +# ifndef CONFIG_STM32_TIM1_CH3OUT # error # endif # endif @@ -108,7 +108,7 @@ /* Phase 4 is TIM1 CH4 */ # if CONFIG_NUCLEOL432KC_SPWM_PHASE_NUM > 3 -# ifndef CONFIG_STM32L4_TIM1_CH4OUT +# ifndef CONFIG_STM32_TIM1_CH4OUT # error # endif # endif diff --git a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig index 98f401ba27a..096df367817 100644 --- a/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l452re/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l452re" CONFIG_ARCH_BOARD_NUCLEO_L452RE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L452RE=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,20 +57,20 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_DAC1=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_DAC1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h index 55c553e4927..067c82da3eb 100644 --- a/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/include/nucleo-l452re.h @@ -144,7 +144,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -170,7 +170,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, @@ -262,7 +262,7 @@ /* CLK48 will come from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -360,7 +360,7 @@ /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -443,7 +443,7 @@ /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L4_USBFS) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h index c740f7bd1f7..50a629b7677 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h +++ b/boards/arm/stm32l4/nucleo-l452re/src/nucleo-l452re.h @@ -58,7 +58,7 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD #endif @@ -66,14 +66,14 @@ /* How many SPI modules does this chip support? */ #if STM32_NSPI < 1 -# undef CONFIG_STM32L4_SPI1 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI1 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 2 -# undef CONFIG_STM32L4_SPI2 -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI2 +# undef CONFIG_STM32_SPI3 #elif STM32_NSPI < 3 -# undef CONFIG_STM32L4_SPI3 +# undef CONFIG_STM32_SPI3 #endif /* Nucleo-L452RE GPIOs ******************************************************/ diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c index 943ed50997a..cfbe5dedc47 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_adc.c @@ -114,7 +114,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -286,7 +286,7 @@ int stm32_adc_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c index cfb99ae3d6d..0dcd2af9191 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_bringup.c @@ -45,7 +45,7 @@ ****************************************************************************/ #undef HAVE_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) && defined(CONFIG_I2C_DRIVER) +#if defined(CONFIG_STM32_I2C1) && defined(CONFIG_I2C_DRIVER) # define HAVE_I2C_DRIVER 1 #endif diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c index 204594da235..91caf4947c3 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_dac.c @@ -57,7 +57,7 @@ int stm32_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32_dacinitialize(0); diff --git a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c index ef717f106eb..ab1e9fac9a6 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l452re/src/stm32_spi.c @@ -40,7 +40,7 @@ #include -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -69,7 +69,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -83,7 +83,7 @@ void weak_function stm32_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -120,7 +120,7 @@ void weak_function stm32_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -141,7 +141,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -155,7 +155,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -193,21 +193,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -215,4 +215,4 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig index 4850d969065..09c040793ff 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,15 +45,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig index 648c01ff163..f71159d49eb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig +++ b/boards/arm/stm32l4/nucleo-l476rg/configs/nxdemo/defconfig @@ -15,6 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l476rg" CONFIG_ARCH_BOARD_NUCLEO_L476RG=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -53,16 +54,16 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_CMDDATA=y CONFIG_START_YEAR=2017 -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h index 48a4b158b7d..6e68c25c9d9 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/nucleo-l476rg.h @@ -143,7 +143,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -169,7 +169,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h index afd37181c06..664d7c2da77 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h +++ b/boards/arm/stm32l4/nucleo-l476rg/src/nucleo-l476rg.h @@ -61,12 +61,12 @@ # undef HAVE_RTC_DRIVER #endif -#if !defined(CONFIG_STM32L4_SPI1) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SPI1) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SPI) # undef HAVE_MMCSD_SPI #endif -#if !defined(CONFIG_STM32L4_SDIO) || !defined(CONFIG_MMCSD) || \ +#if !defined(CONFIG_STM32_SDIO) || !defined(CONFIG_MMCSD) || \ !defined(CONFIG_MMCSD_SDIO) # undef HAVE_MMCSD_SDIO #endif @@ -265,10 +265,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif #ifdef HAVE_MMCSD_SDIO diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c index 33a7c5f05f8..d3e99dada1c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_adc.c @@ -38,7 +38,7 @@ #include "stm32l4_adc.h" #include "nucleo-l476rg.h" -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 /**************************************************************************** * Pre-processor Definitions @@ -144,4 +144,4 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 */ +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c index e83a6e23d77..96fc9df7c48 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c @@ -51,8 +51,8 @@ # if !defined(CONFIG_ADC) # error CONFIG_ADC is required for the Itead joystick # undef CONFIG_INPUT_AJOYSTICK -# elif !defined(CONFIG_STM32L4_ADC1) -# error CONFIG_STM32L4_ADC1 is required for Itead joystick +# elif !defined(CONFIG_STM32_ADC1) +# error CONFIG_STM32_ADC1 is required for Itead joystick # undef CONFIG_INPUT_AJOYSTICK # endif #endif /* CONFIG_INPUT_AJOYSTICK */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index 1ec0b006d17..93bede4772f 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -64,7 +64,7 @@ void stm32_board_initialize(void) * function stm32_spiinitialize() has been brought into the link. */ -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) stm32_spiinitialize(); #endif @@ -73,7 +73,7 @@ void stm32_board_initialize(void) * brought into the build. */ -#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) stm32_usbinitialize(); #endif } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c index 4b632d44f55..4b229423773 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bringup.c @@ -327,7 +327,7 @@ int stm32_bringup(void) index = 0; -#ifdef CONFIG_STM32L4_TIM1_QE +#ifdef CONFIG_STM32_TIM1_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 1); if (ret < 0) @@ -338,7 +338,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM2_QE +#ifdef CONFIG_STM32_TIM2_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 2); if (ret < 0) @@ -349,7 +349,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM3_QE +#ifdef CONFIG_STM32_TIM3_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 3); if (ret < 0) @@ -360,7 +360,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM4_QE +#ifdef CONFIG_STM32_TIM4_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 4); if (ret < 0) @@ -371,7 +371,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM5_QE +#ifdef CONFIG_STM32_TIM5_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 5); if (ret < 0) @@ -382,7 +382,7 @@ int stm32_bringup(void) } #endif -#ifdef CONFIG_STM32L4_TIM8_QE +#ifdef CONFIG_STM32_TIM8_QE snprintf(buf, sizeof(buf), "/dev/qe%d", index++); ret = stm32_qencoder_initialize(buf, 8); if (ret < 0) diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c index 30bfae87ba1..117aa61f8f7 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_can.c @@ -43,11 +43,11 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32L4_CAN1) +#if defined(CONFIG_STM32_CAN1) # warning "Both CAN1 and CAN2 are enabled. Only CAN1 is connected." #endif -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 # define CAN_PORT 1 #endif @@ -65,7 +65,7 @@ int stm32_can_setup(void) { -#ifdef CONFIG_STM32L4_CAN1 +#ifdef CONFIG_STM32_CAN1 struct can_dev_s *can; int ret; diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c index ef81043b182..10b19e93004 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm303agr.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM303AGR driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM303AGR driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -61,7 +61,7 @@ int stm32_lsm303agr_initialize(char *devpath) sninfo("INFO: Initializing LMS303AGR sensor over I2C\n"); -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c index 99de5344b06..bda0f7bf9dc 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_lsm6dsl.c @@ -39,8 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_I2C1 -# error "LSM6DSL driver requires CONFIG_STM32L4_I2C1 to be enabled" +#ifndef CONFIG_STM32_I2C1 +# error "LSM6DSL driver requires CONFIG_STM32_I2C1 to be enabled" #endif /**************************************************************************** @@ -65,7 +65,7 @@ int stm32_lsm6dsl_initialize(char *devpath) stm32_configgpio(GPIO_HTS221_INT); /* IS THE SAME AS HTS221 FOR IKS01_A2 SHIELD */ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c = stm32_i2cbus_initialize(1); if (i2c == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c index b1ad17da3b2..8cb546fc69d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_pwm.c @@ -88,7 +88,7 @@ int stm32_pwm_setup(void) * (see board.h). Let's figure out which the user has configured. */ -#if defined(CONFIG_STM32L4_TIM1_PWM) +#if defined(CONFIG_STM32_TIM1_PWM) pwm = stm32_pwminitialize(1); if (!pwm) { @@ -106,7 +106,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM2_PWM) +#if defined(CONFIG_STM32_TIM2_PWM) pwm = stm32_pwminitialize(2); if (!pwm) { @@ -124,7 +124,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM3_PWM) +#if defined(CONFIG_STM32_TIM3_PWM) pwm = stm32_pwminitialize(3); if (!pwm) { @@ -142,7 +142,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM4_PWM) +#if defined(CONFIG_STM32_TIM4_PWM) pwm = stm32_pwminitialize(4); if (!pwm) { @@ -160,7 +160,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM5_PWM) +#if defined(CONFIG_STM32_TIM5_PWM) pwm = stm32_pwminitialize(5); if (!pwm) { @@ -178,7 +178,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM8_PWM) +#if defined(CONFIG_STM32_TIM8_PWM) pwm = stm32_pwminitialize(8); if (!pwm) { @@ -196,7 +196,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM15_PWM) +#if defined(CONFIG_STM32_TIM15_PWM) pwm = stm32_pwminitialize(15); if (!pwm) { @@ -214,7 +214,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM16_PWM) +#if defined(CONFIG_STM32_TIM16_PWM) pwm = stm32_pwminitialize(16); if (!pwm) { @@ -232,7 +232,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_TIM17_PWM) +#if defined(CONFIG_STM32_TIM17_PWM) pwm = stm32_pwminitialize(17); if (!pwm) { @@ -250,7 +250,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM1_PWM) +#if defined(CONFIG_STM32_LPTIM1_PWM) pwm = stm32_lp_pwminitialize(1); if (!pwm) { @@ -268,7 +268,7 @@ int stm32_pwm_setup(void) } #endif -#if defined(CONFIG_STM32L4_LPTIM2_PWM) +#if defined(CONFIG_STM32_LPTIM2_PWM) pwm = stm32_lp_pwminitialize(2); if (!pwm) { diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c index 39bbd5a6d59..5903f519b5c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spi.c @@ -39,8 +39,8 @@ #include "nucleo-l476rg.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || \ - defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -88,7 +88,7 @@ void weak_function stm32_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -131,7 +131,7 @@ void weak_function stm32_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -168,7 +168,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -189,7 +189,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -227,7 +227,7 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { #ifdef CONFIG_LCD_PCD8544 @@ -247,14 +247,14 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -262,4 +262,4 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c index a02484fbf5d..fe006549d81 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_spimmcsd.c @@ -40,7 +40,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32L4_SPI1 +#ifndef CONFIG_STM32_SPI1 # error "SD driver requires CONFIG_STM32_SPI1 to be enabled" #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig index 9a6ea2b69d5..71cee2c8a19 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig +++ b/boards/arm/stm32l4/nucleo-l496zg/configs/nsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="nucleo-l496zg" CONFIG_ARCH_BOARD_NUCLEO_L496ZG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L496ZG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -57,35 +58,35 @@ CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SERIAL_TERMIOS=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L4_ADC1=y -CONFIG_STM32L4_ADC1_DMA=y -CONFIG_STM32L4_ADC1_EXTTRIG=1 -CONFIG_STM32L4_ADC1_SAMPLE_FREQUENCY=1000 -CONFIG_STM32L4_ADC2=y -CONFIG_STM32L4_ADC2_DMA=y -CONFIG_STM32L4_ADC3=y -CONFIG_STM32L4_ADC3_DMA=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_FSMC=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C2=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_I2C4=y -CONFIG_STM32L4_LPUART1=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI1=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SPI3=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_TIM1=y -CONFIG_STM32L4_TIM1_ADC=y -CONFIG_STM32L4_USART2=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_ADC1=y +CONFIG_STM32_ADC1_DMA=y +CONFIG_STM32_ADC1_EXTTRIG=1 +CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=1000 +CONFIG_STM32_ADC2=y +CONFIG_STM32_ADC2_DMA=y +CONFIG_STM32_ADC3=y +CONFIG_STM32_ADC3_DMA=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_FSMC=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C2=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_I2C4=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SPI3=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_TIM1_ADC=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_I2CTOOL=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 84cda5cbb59..a630e93daf9 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -119,7 +119,7 @@ /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -229,7 +229,7 @@ /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -340,7 +340,7 @@ /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt index 3e922a252e9..fb76edca235 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt +++ b/boards/arm/stm32l4/nucleo-l496zg/src/CMakeLists.txt @@ -42,7 +42,7 @@ endif() if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) - if(CONFIG_STM32L4_DFSDM) + if(CONFIG_STM32_DFSDM) list(APPEND SRCS stm32_dfsdm.c) endif() endif() @@ -55,7 +55,7 @@ if(CONFIG_MMCSD) list(APPEND SRCS stm32_sdio.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile b/boards/arm/stm32l4/nucleo-l496zg/src/Makefile index 5170327a061..4516af4433c 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l496zg/src/Makefile @@ -44,7 +44,7 @@ endif ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c - ifeq ($(CONFIG_STM32L4_DFSDM),y) + ifeq ($(CONFIG_STM32_DFSDM),y) CSRCS += stm32_dfsdm.c endif endif @@ -57,7 +57,7 @@ ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h index e4e2a78aa0e..f13694a49e5 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h +++ b/boards/arm/stm32l4/nucleo-l496zg/src/nucleo-144.h @@ -103,7 +103,7 @@ #define GPIO_SPI3_CS2 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN6) #define GPIO_SPI3_CS3 (GPIO_SPI_CS | GPIO_PORTG | GPIO_PIN7) -#if defined(CONFIG_STM32L4_SDMMC1) || defined(CONFIG_STM32L4_SDMMC2) +#if defined(CONFIG_STM32_SDMMC1) || defined(CONFIG_STM32_SDMMC2) # define HAVE_SDIO #endif @@ -114,7 +114,7 @@ #define SDIO_SLOTNO 0 /* Only one slot */ #ifdef HAVE_SDIO -# if defined(CONFIG_STM32L4_SDMMC1) +# if defined(CONFIG_STM32_SDMMC1) # define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) # endif @@ -240,7 +240,7 @@ int stm32_sdio_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS void stm32_usbinitialize(void); #endif @@ -276,7 +276,7 @@ int stm32_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c index 549d4d1e873..e0ba48ff0a7 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_adc.c @@ -49,18 +49,18 @@ /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 -# undef CONFIG_STM32L4_ADC3 +# undef CONFIG_STM32_ADC3 #endif #if STM32_NADC < 2 -# undef CONFIG_STM32L4_ADC2 +# undef CONFIG_STM32_ADC2 #endif #if STM32_NADC < 1 -# undef CONFIG_STM32L4_ADC1 +# undef CONFIG_STM32_ADC1 #endif -#if defined(CONFIG_STM32L4_ADC1) || defined(CONFIG_STM32L4_ADC2) || defined(CONFIG_STM32L4_ADC3) +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) /* The number of ADC channels in the conversion list */ @@ -77,7 +77,7 @@ * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 static const uint8_t g_chanlist_adc1[ADC1_NCHANNELS] = { 3 @@ -98,7 +98,7 @@ static const uint32_t g_pinlist_adc1[ADC1_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 static const uint8_t g_chanlist_adc2[ADC2_NCHANNELS] = { 4, @@ -111,7 +111,7 @@ static const uint32_t g_pinlist_adc2[ADC2_NCHANNELS] = }; #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 static const uint8_t g_chanlist_adc3[ADC3_NCHANNELS] = { 17, @@ -153,7 +153,7 @@ int stm32_adc_setup(void) { /* Configure the pins as analog inputs for the selected channels */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 for (i = 0; i < ADC1_NCHANNELS; i++) { if (g_pinlist_adc1[i] != 0) @@ -163,7 +163,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 for (i = 0; i < ADC2_NCHANNELS; i++) { if (g_pinlist_adc2[i] != 0) @@ -173,7 +173,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 for (i = 0; i < ADC3_NCHANNELS; i++) { if (g_pinlist_adc3[i] != 0) @@ -187,7 +187,7 @@ int stm32_adc_setup(void) * interface */ -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 adc = stm32_adc_initialize(1, g_chanlist_adc1, ADC1_NCHANNELS); if (adc == NULL) { @@ -205,7 +205,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC2 +#ifdef CONFIG_STM32_ADC2 adc = stm32_adc_initialize(2, g_chanlist_adc2, ADC2_NCHANNELS); if (adc == NULL) { @@ -223,7 +223,7 @@ int stm32_adc_setup(void) } #endif -#ifdef CONFIG_STM32L4_ADC3 +#ifdef CONFIG_STM32_ADC3 adc = stm32_adc_initialize(3, g_chanlist_adc3, ADC3_NCHANNELS); if (adc == NULL) { @@ -249,5 +249,5 @@ int stm32_adc_setup(void) return OK; } -#endif /* CONFIG_STM32L4_ADC1 || CONFIG_STM32L4_ADC2 || CONFIG_STM32L4_ADC3 */ +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ #endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c index 9a0caa0d36f..3d4eb5a06ff 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_boot.c @@ -64,7 +64,7 @@ void stm32_board_initialize(void) board_autoled_initialize(); #endif -#if defined(CONFIG_STM32L4_OTGFS) || defined(CONFIG_STM32L4_HOST) +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32L4_HOST) stm32_usbinitialize(); #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c index e3022335e3e..b9133caa56d 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_bringup.c @@ -40,16 +40,16 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) struct i2c_master_s *i2c1; #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) struct i2c_master_s *i2c2; #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) struct i2c_master_s *i2c3; #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) struct i2c_master_s *i2c4; #endif @@ -102,7 +102,7 @@ int stm32_bringup(void) syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); } -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); @@ -161,29 +161,29 @@ int stm32_bringup(void) /* REVISIT: this is ugly! */ -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c1 = stm32_i2cbus_initialize(1); #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) i2c2 = stm32_i2cbus_initialize(2); #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) i2c3 = stm32_i2cbus_initialize(3); #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) i2c4 = stm32_i2cbus_initialize(4); #endif #ifdef CONFIG_I2C_DRIVER -#if defined(CONFIG_STM32L4_I2C1) +#if defined(CONFIG_STM32_I2C1) i2c_register(i2c1, 1); #endif -#if defined(CONFIG_STM32L4_I2C2) +#if defined(CONFIG_STM32_I2C2) i2c_register(i2c2, 2); #endif -#if defined(CONFIG_STM32L4_I2C3) +#if defined(CONFIG_STM32_I2C3) i2c_register(i2c3, 3); #endif -#if defined(CONFIG_STM32L4_I2C4) +#if defined(CONFIG_STM32_I2C4) i2c_register(i2c4, 4); #endif #endif diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c index 42ff6951b54..573f956fc50 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dac.c @@ -41,11 +41,11 @@ * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 static struct dac_dev_s *g_dac1; #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 static struct dac_dev_s *g_dac2; #endif @@ -65,7 +65,7 @@ int stm32_dac_setup(void) { int ret; -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 g_dac1 = stm32_dacinitialize(0); if (g_dac1 == NULL) { @@ -81,7 +81,7 @@ int stm32_dac_setup(void) } #endif -#ifdef CONFIG_STM32L4_DAC2 +#ifdef CONFIG_STM32_DAC2 g_dac2 = stm32_dacinitialize(1); if (g_dac2 == NULL) { diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c index 9d0a6261495..ab8ee9c8430 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dfsdm.c @@ -35,7 +35,7 @@ #include "stm32l4_dfsdm.h" #include "nucleo-144.h" -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -53,28 +53,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -88,7 +88,7 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { @@ -104,7 +104,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { @@ -120,7 +120,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { @@ -136,7 +136,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { @@ -157,4 +157,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c index 2e0d5f1fc03..f39ee47e689 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_spi.c @@ -95,7 +95,7 @@ * Private Data ****************************************************************************/ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) static const uint32_t g_spi1gpio[] = { # if defined(GPIO_SPI1_CS0) @@ -121,7 +121,7 @@ static const uint32_t g_spi1gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) static const uint32_t g_spi2gpio[] = { # if defined(GPIO_SPI2_CS0) @@ -147,7 +147,7 @@ static const uint32_t g_spi2gpio[] = }; #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) static const uint32_t g_spi3gpio[] = { # if defined(GPIO_SPI3_CS0) @@ -174,13 +174,13 @@ static const uint32_t g_spi3gpio[] = #endif #if defined(CONFIG_NUCLEO_SPI_TEST) -# if defined(CONFIG_STM32L4_SPI1) +# if defined(CONFIG_STM32_SPI1) struct spi_dev_s *spi1; # endif -# if defined(CONFIG_STM32L4_SPI2) +# if defined(CONFIG_STM32_SPI2) struct spi_dev_s *spi2; # endif -# if defined(CONFIG_STM32L4_SPI3) +# if defined(CONFIG_STM32_SPI3) struct spi_dev_s *spi3; # endif #endif @@ -201,7 +201,7 @@ void weak_function stm32_spidev_initialize(void) { /* Configure SPI CS GPIO for output */ -#if defined(CONFIG_STM32L4_SPI1) +#if defined(CONFIG_STM32_SPI1) for (int i = 0; i < nitems(g_spi1gpio); i++) { if (g_spi1gpio[i] != 0) @@ -211,7 +211,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32L4_SPI2) +#if defined(CONFIG_STM32_SPI2) for (int i = 0; i < nitems(g_spi2gpio); i++) { if (g_spi2gpio[i] != 0) @@ -221,7 +221,7 @@ void weak_function stm32_spidev_initialize(void) } #endif -#if defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI3) for (int i = 0; i < nitems(g_spi3gpio); i++) { if (g_spi3gpio[i] != 0) @@ -258,7 +258,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -279,7 +279,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -300,7 +300,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -345,21 +345,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c index 0344866c619..a499ca891ce 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_usb.c @@ -45,7 +45,7 @@ #include "stm32l4_otgfs.h" #include "nucleo-144.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -138,7 +138,7 @@ void stm32_usbinitialize(void) * Power On, and Overcurrent GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig index 135cc3d5070..fb9fe5e3914 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/lwl/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -37,7 +38,7 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig index 8a7ad6bdecd..a5db2db0518 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig +++ b/boards/arm/stm32l4/steval-stlcs01v1/configs/usbnsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="steval-stlcs01v1" CONFIG_ARCH_BOARD_STEVAL_STLCS01V1=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476JG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -40,9 +41,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_OTGFS=y -CONFIG_STM32L4_SAI1PLL=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_SAI1PLL=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USBDEV=y diff --git a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h index 4ecb2c970fb..fb86e68651c 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/include/board.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/include/board.h @@ -125,7 +125,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI1 is configured only if CONFIG_STM32L4_SAI1PLL is defined + * The PLLSAI1 is configured only if CONFIG_STM32_SAI1PLL is defined * * SAI1VCO input frequency = PLL input clock frequency * SAI1VCO output frequency = SAI1VCO input frequency × PLLSAI1N, @@ -147,7 +147,7 @@ * * The clock input and M divider are identical to the main PLL. * However the multiplier and postscalers are independent. - * The PLLSAI2 is configured only if CONFIG_STM32L4_SAI2PLL is defined + * The PLLSAI2 is configured only if CONFIG_STM32_SAI2PLL is defined * * SAI2VCO input frequency = PLL input clock frequency * SAI2VCO output frequency = SAI2VCO input frequency × PLLSAI2N, diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt index 88aa47097ce..2a3de594681 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_ARCH_LEDS) list(APPEND SRCS stm32_autoleds.c) endif() -if(CONFIG_STM32L4_OTGFS) +if(CONFIG_STM32_OTGFS) list(APPEND SRCS stm32_usb.c) endif() diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile b/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile index e46d406cb3e..80a41f0fa38 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile @@ -28,7 +28,7 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h index bcf021af660..d22ac346478 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/steval-stlcs01v1.h @@ -93,7 +93,7 @@ int stm32_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS void weak_function stm32_usbinitialize(void); #endif diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c index 1d8f7a02cb6..5908bb4deac 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_boot.c @@ -60,7 +60,7 @@ void stm32_board_initialize(void) * selected. */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Enable Vddusb - mandatory to use the USB OTG FS peripheral */ stm32_pwr_enableusv(true); diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c index cc7945e71a6..87f30cd3ee7 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/stm32_usb.c @@ -39,7 +39,7 @@ #include "stm32l4_otgfs.h" #include "steval-stlcs01v1.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -48,7 +48,7 @@ #if defined(CONFIG_USBDEV) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but not CONFIG_USBDEV" +# warning "CONFIG_STM32_OTGFS is enabled but not CONFIG_USBDEV" # undef HAVE_USB #endif @@ -99,4 +99,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig index 875e7b30a17..a3ccc532ef2 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476-mdk/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476-mdk" CONFIG_ARCH_BOARD_STM32L476_MDK=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -48,14 +49,14 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART3=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART3=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt index f47dc052ac4..5390a86c121 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt +++ b/boards/arm/stm32l4/stm32l476-mdk/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_spi.c stm32_userleds.c) -if(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile b/boards/arm/stm32l4/stm32l476-mdk/src/Makefile index 0aba6ed8c09..66a39c74229 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile +++ b/boards/arm/stm32l4/stm32l476-mdk/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_spi.c stm32_userleds.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 38b64581120..e8ee098c111 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -52,7 +52,7 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { uint32_t regval; @@ -175,7 +175,7 @@ void stm32_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -197,7 +197,7 @@ void stm32_board_clockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig index 9ee1fcccd70..8e0327c7228 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/knsh/defconfig @@ -14,6 +14,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -52,15 +53,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig index 9bab580b6f0..8f07bd33dcf 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l476vg-disco" CONFIG_ARCH_BOARD_STM32L476VG_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L476RG=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,15 +56,15 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_DMA2=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_QSPI=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_DMA2=y +CONFIG_STM32_PWR=y +CONFIG_STM32_QSPI=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_USART2_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile index a2438eee63b..aa94c8d033c 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile @@ -24,11 +24,11 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index be69ca1b000..34834af60d0 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -68,7 +68,7 @@ void stm32_board_initialize(void) stm32_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index ad5a8de00b9..202b4e0dbcc 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -52,7 +52,7 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { uint32_t regval; @@ -175,7 +175,7 @@ void stm32_board_clockconfig(void) * and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -197,7 +197,7 @@ void stm32_board_clockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c index 700c408c3e1..40155f6c84a 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32l4_otgfs.h" #include "stm32l476vg-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -325,4 +325,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h index 79b85d1a564..4f741df1ddc 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32l476vg-disco.h @@ -74,7 +74,7 @@ # undef HAVE_N25QXXX_CHARDEV #endif -#ifndef CONFIG_STM32L4_QSPI +#ifndef CONFIG_STM32_QSPI # undef HAVE_N25QXXX # undef HAVE_N25QXXX_NXFFS # undef HAVE_N25QXXX_SMARTFS @@ -116,7 +116,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig index 020cf49a740..9c6cfd36dfa 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/knsh/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -55,17 +56,17 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig index b2e29c4a535..ca695bde26d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="stm32l4r9ai-disco" CONFIG_ARCH_BOARD_STM32L4R9AI_DISCO=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l4" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L4=y CONFIG_ARCH_CHIP_STM32L4R9AI=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -56,18 +57,18 @@ CONFIG_RTC_IOCTL=y CONFIG_RTC_NALARMS=2 CONFIG_SCHED_WAITPID=y CONFIG_SPI_DRIVER=y -CONFIG_STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32L4_DMA1=y -CONFIG_STM32L4_I2C1=y -CONFIG_STM32L4_I2C3=y -CONFIG_STM32L4_PWR=y -CONFIG_STM32L4_RNG=y -CONFIG_STM32L4_RTC=y -CONFIG_STM32L4_SAI1PLL=y -CONFIG_STM32L4_SPI2=y -CONFIG_STM32L4_SRAM2_HEAP=y -CONFIG_STM32L4_UART4=y -CONFIG_STM32L4_USART2=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_I2C1=y +CONFIG_STM32_I2C3=y +CONFIG_STM32_PWR=y +CONFIG_STM32_RNG=y +CONFIG_STM32_RTC=y +CONFIG_STM32_SAI1PLL=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_UART4=y +CONFIG_STM32_USART2=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_UART4_BAUD=2000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index bb33ba52a60..e27666361ce 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -134,7 +134,7 @@ /* CLK48 will come from PLLSAI1 (implicitly Q) */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -244,7 +244,7 @@ /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE @@ -341,7 +341,7 @@ /* Enable CLK48; get it from PLLSAI1 */ -#if defined(CONFIG_STM32L4_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32L4_RNG) +#if defined(CONFIG_STM32_OTGFS) || defined(STM32_SDMMC) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile index 47936292ad5..377448e664a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile @@ -24,7 +24,7 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c -ifeq ($(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif @@ -39,10 +39,10 @@ CSRCS += stm32_buttons.c endif ifeq ($(CONFIG_ADC),y) -ifeq ($(CONFIG_STM32L4_ADC),y) +ifeq ($(CONFIG_STM32_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(CONFIG_STM32L4_DFSDM),y) +ifeq ($(CONFIG_STM32_DFSDM),y) CSRCS += stm32_dfsdm.c endif endif @@ -51,11 +51,11 @@ ifeq ($(CONFIG_DAC),y) CSRCS += stm32_dac.c endif -ifeq ($(CONFIG_STM32L4_SPI),y) +ifeq ($(CONFIG_STM32_SPI),y) CSRCS += stm32_spi.c endif -ifeq ($(CONFIG_STM32L4_OTGFS),y) +ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c index c756acc8a31..f0ed838edef 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_adc.c @@ -111,7 +111,7 @@ #define ADC1_NCHANNELS 4 -#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32L4_ADC1_DMA) +#if ADC1_NCHANNELS > 1 && !defined(CONFIG_STM32_ADC1_DMA) # warning "Reading multiple channels without DMA might cause overruns!" #endif @@ -274,7 +274,7 @@ int stm32_adc_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_ADC1 +#ifdef CONFIG_STM32_ADC1 int ret; int i; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index 32a642f5190..98c867d816a 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -64,11 +64,11 @@ void stm32_board_initialize(void) * function stm32_spiinitialize() has been brought into the link. */ -#ifdef CONFIG_STM32L4_SPI +#ifdef CONFIG_STM32_SPI stm32_spiinitialize(); #endif -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /* Initialize USB if the * 1) OTG FS controller is in the configuration and * 2) disabled, and diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c index 9bd8d1ff612..ecbd830badd 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_bringup.c @@ -65,10 +65,10 @@ ****************************************************************************/ #ifdef CONFIG_I2C -# ifdef CONFIG_STM32L4_I2C1 +# ifdef CONFIG_STM32_I2C1 static struct i2c_master_s *g_i2c1; # endif -# ifdef CONFIG_STM32L4_I2C3 +# ifdef CONFIG_STM32_I2C3 static struct i2c_master_s *g_i2c3; # endif #endif @@ -135,14 +135,14 @@ int stm32_bringup(void) #ifdef CONFIG_I2C i2cinfo("Initializing I2C buses\n"); -#ifdef CONFIG_STM32L4_I2C1 +#ifdef CONFIG_STM32_I2C1 g_i2c1 = stm32_i2cbus_initialize(1); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c1, 1); #endif #endif -#ifdef CONFIG_STM32L4_I2C3 +#ifdef CONFIG_STM32_I2C3 g_i2c3 = stm32_i2cbus_initialize(3); #ifdef CONFIG_I2C_DRIVER i2c_register(g_i2c3, 3); @@ -178,7 +178,7 @@ int stm32_bringup(void) ainfo("Initializing ADC\n"); stm32_adc_setup(); -#ifdef CONFIG_STM32L4_DFSDM +#ifdef CONFIG_STM32_DFSDM /* Initialize DFSDM and register its filters as additional ADC devices. */ ret = stm32_dfsdm_setup(); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c index 5119c7b5f56..0aec1065295 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_clockconfig.c @@ -52,7 +52,7 @@ * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { uint32_t regval; @@ -175,7 +175,7 @@ void stm32_board_clockconfig(void) * data cache, and 5 wait states */ -#ifdef CONFIG_STM32L4_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else @@ -197,7 +197,7 @@ void stm32_board_clockconfig(void) { } -#if defined(CONFIG_STM32L4_IWDG) || defined(CONFIG_STM32L4_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c index fd2d8f541d4..63124aab207 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dac.c @@ -57,7 +57,7 @@ int stm32_dac_setup(void) if (!initialized) { -#ifdef CONFIG_STM32L4_DAC1 +#ifdef CONFIG_STM32_DAC1 int ret; g_dac = stm32_dacinitialize(0); diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c index fd1716501c6..641f9dc1115 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_dfsdm.c @@ -38,7 +38,7 @@ #include -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) /**************************************************************************** * Public Functions @@ -56,28 +56,28 @@ int stm32_dfsdm_setup(void) { int ret; struct adc_dev_s *adc; -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 const uint8_t chanlist0[1] = { 0 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 const uint8_t chanlist1[2] = { 0, 1 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 const uint8_t chanlist2[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 const uint8_t chanlist3[4] = { 6, 5, 4, 3 @@ -91,7 +91,7 @@ int stm32_dfsdm_setup(void) * parallel inputs (CPU/DMA/ADC). */ -#ifdef CONFIG_STM32L4_DFSDM1_FLT0 +#ifdef CONFIG_STM32_DFSDM1_FLT0 adc = stm32_dfsdm_initialize(0, chanlist0, 1); if (adc == NULL) { @@ -107,7 +107,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT1 +#ifdef CONFIG_STM32_DFSDM1_FLT1 adc = stm32_dfsdm_initialize(1, chanlist1, 2); if (adc == NULL) { @@ -123,7 +123,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT2 +#ifdef CONFIG_STM32_DFSDM1_FLT2 adc = stm32_dfsdm_initialize(2, chanlist2, 8); if (adc == NULL) { @@ -139,7 +139,7 @@ int stm32_dfsdm_setup(void) } #endif -#ifdef CONFIG_STM32L4_DFSDM1_FLT3 +#ifdef CONFIG_STM32_DFSDM1_FLT3 adc = stm32_dfsdm_initialize(3, chanlist3, 4); if (adc == NULL) { @@ -160,4 +160,4 @@ int stm32_dfsdm_setup(void) return OK; } -#endif /* CONFIG_ADC && CONFIG_STM32L4_DFSDM */ +#endif /* CONFIG_ADC && CONFIG_STM32_DFSDM */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c index cc871792ae4..6d9e8e2bf6d 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "stm32l4r9ai-disco.h" -#if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) /**************************************************************************** * Public Data @@ -48,13 +48,13 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 struct spi_dev_s *g_spi2; #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 struct spi_dev_s *g_spi3; #endif @@ -72,7 +72,7 @@ struct spi_dev_s *g_spi3; void weak_function stm32_spiinitialize(void) { -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices on SPI1 */ g_spi1 = stm32_spibus_initialize(1); @@ -90,7 +90,7 @@ void weak_function stm32_spiinitialize(void) #endif #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 /* Configure SPI-based devices on SPI2 */ g_spi2 = stm32_spibus_initialize(2); @@ -106,7 +106,7 @@ void weak_function stm32_spiinitialize(void) #warning No devices specified on SPI2 #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 /* Configure SPI-based devices on SPI3 */ g_spi3 = stm32_spibus_initialize(3); @@ -149,7 +149,7 @@ void weak_function stm32_spiinitialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -170,7 +170,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -184,7 +184,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -222,21 +222,21 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; } #endif -#ifdef CONFIG_STM32L4_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return OK; @@ -244,4 +244,4 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32L4_SPI1 || CONFIG_STM32L4_SPI2 || CONFIG_STM32L4_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c index 52eacbacede..314bef362e1 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_usb.c @@ -44,7 +44,7 @@ #include "stm32l4_otgfs.h" #include "stm32l4r9ai-disco.h" -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS /**************************************************************************** * Pre-processor Definitions @@ -53,7 +53,7 @@ #if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) # define HAVE_USB 1 #else -# warning "CONFIG_STM32L4_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" # undef HAVE_USB #endif @@ -137,7 +137,7 @@ void stm32_usbinitialize(void) * Power On, and Over current GPIOs */ -#ifdef CONFIG_STM32L4_OTGFS +#ifdef CONFIG_STM32_OTGFS stm32_configgpio(GPIO_OTGFS_VBUS); stm32_configgpio(GPIO_OTGFS_PWRON); stm32_configgpio(GPIO_OTGFS_OVER); @@ -326,4 +326,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume) } #endif -#endif /* CONFIG_STM32L4_OTGFS */ +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h index b113923cce0..44df2b03d73 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32l4r9ai-disco.h @@ -67,7 +67,7 @@ /* Can't support USB host or device features if USB OTG FS is not enabled */ -#ifndef CONFIG_STM32L4_OTGFS +#ifndef CONFIG_STM32_OTGFS # undef HAVE_USBDEV # undef HAVE_USBHOST #endif @@ -188,10 +188,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32L4_SPI1 +#ifdef CONFIG_STM32_SPI1 extern struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32L4_SPI2 +#ifdef CONFIG_STM32_SPI2 extern struct spi_dev_s *g_spi2; #endif @@ -252,7 +252,7 @@ int stm32_dac_setup(void); * ****************************************************************************/ -#if defined(CONFIG_ADC) && defined(CONFIG_STM32L4_DFSDM) +#if defined(CONFIG_ADC) && defined(CONFIG_STM32_DFSDM) int stm32_dfsdm_setup(void); #endif From 4033c547425ea9beb262591c4dfba8722723f6d9 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:41 +0200 Subject: [PATCH 090/268] !arch/stm32l5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32L5 Kconfig symbols were renamed from CONFIG_STM32L5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32l5/boards/nucleo-l552ze/index.rst | 4 +- .../stm32l5/boards/stm32l562e-dk/index.rst | 8 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32l5/chip.h | 6 +- arch/arm/include/stm32l5/irq.h | 2 +- arch/arm/include/stm32l5/stm32l562xx_irq.h | 2 +- arch/arm/src/stm32l5/CMakeLists.txt | 2 +- arch/arm/src/stm32l5/Kconfig | 3231 +---------------- arch/arm/src/stm32l5/Make.defs | 2 +- .../src/stm32l5/hardware/stm32l562xx_rcc.h | 4 +- .../src/stm32l5/hardware/stm32l562xx_syscfg.h | 4 +- arch/arm/src/stm32l5/hardware/stm32l5_flash.h | 32 +- .../arm/src/stm32l5/hardware/stm32l5_pinmap.h | 2 +- arch/arm/src/stm32l5/hardware/stm32l5_spi.h | 2 +- .../arm/src/stm32l5/hardware/stm32l5_syscfg.h | 2 +- arch/arm/src/stm32l5/stm32l562xx_rcc.c | 108 +- arch/arm/src/stm32l5/stm32l5_allocateheap.c | 16 +- arch/arm/src/stm32l5/stm32l5_dbgmcu.h | 2 +- arch/arm/src/stm32l5/stm32l5_exti.h | 2 +- arch/arm/src/stm32l5/stm32l5_flash.c | 4 +- arch/arm/src/stm32l5/stm32l5_gpio.h | 2 +- arch/arm/src/stm32l5/stm32l5_idle.c | 2 +- arch/arm/src/stm32l5/stm32l5_lse.c | 20 +- arch/arm/src/stm32l5/stm32l5_rcc.c | 10 +- arch/arm/src/stm32l5/stm32l5_rcc.h | 10 +- arch/arm/src/stm32l5/stm32l5_serial.c | 98 +- arch/arm/src/stm32l5/stm32l5_spi.c | 80 +- arch/arm/src/stm32l5/stm32l5_spi.h | 12 +- arch/arm/src/stm32l5/stm32l5_start.c | 2 +- arch/arm/src/stm32l5/stm32l5_tim.c | 246 +- arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c | 56 +- arch/arm/src/stm32l5/stm32l5_uart.h | 104 +- .../nucleo-l552ze/configs/nsh/defconfig | 7 +- .../arm/stm32l5/nucleo-l552ze/include/board.h | 2 +- .../stm32l5/nucleo-l552ze/src/stm32_boot.c | 2 +- .../stm32l562e-dk/configs/nsh/defconfig | 5 +- .../stm32l562e-dk/src/stm32_clockconfig.c | 4 +- 37 files changed, 469 insertions(+), 3629 deletions(-) diff --git a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst index fcc67d7977d..66386780317 100644 --- a/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/nucleo-l552ze/index.rst @@ -104,7 +104,7 @@ You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL Use make menuconfig to configure USART3 as the console:: - CONFIG_STM32L5_USART3=y + CONFIG_STM32_USART3=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y CONFIG_USART3_RXBUFSIZE=256 @@ -126,7 +126,7 @@ Solder Bridges (active by default on Nucleo-L552ZE-Q):: Use make menuconfig to configure LPUART1 as the console:: - CONFIG_STM32L5_LPUART1=y + CONFIG_STM32_LPUART1=y CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_LPUART1_RXBUFSIZE=256 CONFIG_LPUART1_TXBUFSIZE=256 diff --git a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst index 6769e7af228..ddba39b1801 100644 --- a/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst +++ b/Documentation/platforms/arm/stm32l5/boards/stm32l562e-dk/index.rst @@ -84,7 +84,7 @@ the STLINK Virtual COM Port. Use make menuconfig to configure USART1 as the console:: - CONFIG_STM32L5_USART1=y + CONFIG_STM32_USART1=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USART1_RXBUFSIZE=256 @@ -220,9 +220,9 @@ NOTES: output on USART1, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART1=y - CONFIG_STM32L5_USART1_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART1=y + CONFIG_STM32_USART1_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART1_SERIALDRIVER=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9f092d029e4..78fb0616167 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -700,6 +700,7 @@ config ARCH_CHIP_STM32N6 config ARCH_CHIP_STM32L5 bool "STMicro STM32 L5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP diff --git a/arch/arm/include/stm32l5/chip.h b/arch/arm/include/stm32l5/chip.h index e6948539e5f..0986ac7a150 100644 --- a/arch/arm/include/stm32l5/chip.h +++ b/arch/arm/include/stm32l5/chip.h @@ -33,14 +33,14 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # define STM32_SRAM1_SIZE (192*1024) /* 192Kb SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -69,7 +69,7 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32l5/irq.h b/arch/arm/include/stm32l5/irq.h index 9a35b3bdaf3..94126296152 100644 --- a/arch/arm/include/stm32l5/irq.h +++ b/arch/arm/include/stm32l5/irq.h @@ -33,7 +33,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/include/stm32l5/stm32l562xx_irq.h b/arch/arm/include/stm32l5/stm32l562xx_irq.h index 731567e7ffa..35e326d15b0 100644 --- a/arch/arm/include/stm32l5/stm32l562xx_irq.h +++ b/arch/arm/include/stm32l5/stm32l562xx_irq.h @@ -160,7 +160,7 @@ #define STM32_IRQ_ICACHE (STM32_IRQ_FIRST + 107) /* 107: Instruction cache global interrupt */ #define STM32_IRQ_OTFDEC1 (STM32_IRQ_FIRST + 108) /* 108: OTFDEC1 global interrupt */ -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # define STM32_IRQ_NEXTINTS 109 #else # error "Unsupported STM32L5 chip" diff --git a/arch/arm/src/stm32l5/CMakeLists.txt b/arch/arm/src/stm32l5/CMakeLists.txt index 18f0fdaf03c..4f10e5e8aa1 100644 --- a/arch/arm/src/stm32l5/CMakeLists.txt +++ b/arch/arm/src/stm32l5/CMakeLists.txt @@ -61,7 +61,7 @@ endif() # Required chip type specific files -if(CONFIG_STM32L5_STM32L562XX) +if(CONFIG_STM32_STM32L562XX) list(APPEND SRCS stm32l562xx_rcc.c) endif() diff --git a/arch/arm/src/stm32l5/Kconfig b/arch/arm/src/stm32l5/Kconfig index 4a7589a116a..a41fb1c522d 100644 --- a/arch/arm/src/stm32l5/Kconfig +++ b/arch/arm/src/stm32l5/Kconfig @@ -7,6 +7,18 @@ if ARCH_CHIP_STM32L5 comment "STM32L5 Configuration Options" +config STM32_L5_PERIPHERALS + bool + default y + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_PWR + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + choice prompt "STM32 L5 Chip Selection" default ARCH_CHIP_STM32L552ZE @@ -14,16 +26,16 @@ choice config ARCH_CHIP_STM32L552ZE bool "STM32L552ZE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Z ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM config ARCH_CHIP_STM32L562QE bool "STM32L562QE" - select STM32L5_STM32L562XX - select STM32L5_FLASH_CONFIG_E + select STM32_STM32L562XX + select STM32_FLASH_CONFIG_E select STM32L5_IO_CONFIG_Q ---help--- STM32 L5 Cortex M33, 512 Kb FLASH, 256 Kb SRAM @@ -32,3243 +44,68 @@ endchoice # STM32 L5 Chip Selection # Chip families: -config STM32L5_STM32L562XX - # STM32L552 and STM32L562 devices documented in RM0439 +# STM32L552 and STM32L562 devices documented in RM0439 +config STM32_STM32L562XX bool default n select ARCH_HAVE_FPU - select STM32L5_HAVE_LPUART1 - select STM32L5_HAVE_USART1 - select STM32L5_HAVE_USART2 - select STM32L5_HAVE_USART3 - select STM32L5_HAVE_UART4 - select STM32L5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32L5 - default STM32L5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32L5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32L576VE is chosen, the Flash configuration would be 'E', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32L5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32L5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32L5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32L5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32L5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32L5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32L5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32L5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32L5_FLASH_CONFIG_8 - bool - default n - depends on STM32L5_STM32L512XX - -config STM32L5_FLASH_CONFIG_B - bool - default n - depends on STM32L5_STM32L5X1 || STM32L5_STM32L5X3 - -config STM32L5_FLASH_CONFIG_C - bool - default n - depends on !STM32L5_STM32L596XX - -config STM32L5_FLASH_CONFIG_E - bool - default n - -config STM32L5_FLASH_CONFIG_G - bool - default n - depends on STM32L5_STM32L5X5 || STM32L5_STM32L5X6 - -config STM32L5_FLASH_CONFIG_I - bool - default n - depends on STM32L5_STM32L5XR + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 # Pin/package configurations config STM32L5_IO_CONFIG_K + # Package designator K bool default n config STM32L5_IO_CONFIG_T + # Package designator T bool default n config STM32L5_IO_CONFIG_C + # Package designator C bool default n config STM32L5_IO_CONFIG_R + # Package designator R bool default n config STM32L5_IO_CONFIG_J + # Package designator J bool default n config STM32L5_IO_CONFIG_M + # Package designator M bool default n config STM32L5_IO_CONFIG_V + # Package designator V bool default n config STM32L5_IO_CONFIG_Q + # Package designator Q bool default n config STM32L5_IO_CONFIG_Z + # Package designator Z bool default n config STM32L5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32L5 SRAM2 Options" - -config STM32L5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - select STM32L5_SRAM2_INIT - ---help--- - The STM32L5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32L5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - ---help--- - The STM32L5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -comment "STM32L5 Peripherals" - -menu "STM32L5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32L5_HAVE_LPUART1 - bool - default n - -config STM32L5_HAVE_USART1 - bool - default n - -config STM32L5_HAVE_USART2 - bool - default n - -config STM32L5_HAVE_USART3 - bool - default n - -config STM32L5_HAVE_UART4 - bool - default n - -config STM32L5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32L5_SPI - bool - default n - -config STM32L5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -comment "AHB2 Peripherals" - -comment "AHB3 Peripherals" - -comment "APB1 Peripherals" - -config STM32L5_PWR - bool "PWR" - default n - -config STM32L5_RTC - bool "RTC" - default n - -config STM32L5_SPI2 - bool "SPI2" - default n - select SPI - select STM32L5_SPI - -config STM32L5_SPI3 - bool "SPI3" - default n - select SPI - select STM32L5_SPI - -config STM32L5_LPUART1 - bool "LPUART1" - default n - depends on STM32L5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART2 - bool "USART2" - default n - depends on STM32L5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_USART3 - bool "USART3" - default n - depends on STM32L5_HAVE_USART3 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART4 - bool "UART4" - default n - depends on STM32L5_HAVE_UART4 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -config STM32L5_UART5 - bool "UART5" - default n - depends on STM32L5_HAVE_UART5 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -comment "APB2 Peripherals" - -config STM32L5_SYSCFG - bool "SYSCFG" - default y - -config STM32L5_SPI1 - bool "SPI1" - default n - select SPI - select STM32L5_SPI - -config STM32L5_USART1 - bool "USART1" - default n - depends on STM32L5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32L5_USART - -endmenu - -config STM32L5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32L5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32L5_HAVE_SAI2 - ---help--- - The STM32L5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32L5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -config STM32L5_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32L5_RTC - -config STM32L5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32L5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32L5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32L5_RTC_LSECLOCK - depends on STM32L5_RTC - -config STM32L5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32L5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32L5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32L5_RTC_LSECLOCK - -config STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32L5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32L5_ONESHOT - bool - default y - -config STM32L5_FREERUN - bool - default y - -config STM32L5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32L5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32L5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32L5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32L5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32L5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32L5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32L5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32L5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32L5_LPTIM1_CLK_APB1 - -config STM32L5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32L5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32L5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32L5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32L5_LPTIM1_PWM - -config STM32L5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32L5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32L5_LPTIM2_CLK_APB1 - -config STM32L5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32L5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32L5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32L5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32L5_LPTIM2_PWM - -config STM32L5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32L5_TIM1 - select PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM1_PWM - -config STM32L5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM1_CHANNEL1 - -config STM32L5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32L5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM1_CHANNEL2 - -config STM32L5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM1_CHANNEL3 - -config STM32L5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM1_CHANNEL5 - -config STM32L5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM1_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM1_PWM - -config STM32L5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32L5_TIM2 - select PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM2_PWM - -config STM32L5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM2_CHANNEL1 - -config STM32L5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM2_CHANNEL2 - -config STM32L5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM2_CHANNEL3 - -config STM32L5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM2_CHANNEL5 - -config STM32L5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM2_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM2_PWM - -config STM32L5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32L5_TIM3 - select PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM3_PWM - -config STM32L5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM3_CHANNEL1 - -config STM32L5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM3_CHANNEL2 - -config STM32L5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM3_CHANNEL3 - -config STM32L5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM3_CHANNEL5 - -config STM32L5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM3_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM3_PWM - -config STM32L5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32L5_TIM4 - select PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM4_PWM - -config STM32L5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM4_CHANNEL1 - -config STM32L5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM4_CHANNEL2 - -config STM32L5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM4_CHANNEL3 - -config STM32L5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM4_CHANNEL5 - -config STM32L5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM4_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM4_PWM - -config STM32L5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32L5_TIM5 - select PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM5_PWM - -config STM32L5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32L5_TIM5_CHANNEL1 - -config STM32L5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM5_CHANNEL2 - -config STM32L5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32L5_TIM5_CHANNEL3 - -config STM32L5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM5_CHANNEL5 - -config STM32L5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM5_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM5_PWM - -config STM32L5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32L5_TIM8 - select PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM8_PWM - -config STM32L5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM8_CHANNEL1 - -config STM32L5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32L5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32L5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32L5_TIM8_CHANNEL2 - -config STM32L5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32L5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32L5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32L5_TIM8_CHANNEL3 - -config STM32L5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32L5_TIM8_CHANNEL5 - -config STM32L5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32L5_TIM8_CHANNEL5 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32L5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM8_PWM - -config STM32L5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32L5_TIM15 - select PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM15_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM15_CHANNEL1 - -config STM32L5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32L5_TIM15_CHANNEL2 - -config STM32L5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32L5_TIM15_CHANNEL2 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32L5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM15_PWM - -config STM32L5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32L5_TIM16 - select PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM16_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM16_CHANNEL1 - -config STM32L5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM16_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM16_PWM - -config STM32L5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32L5_TIM17 - select PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32L5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32L5_TIM17_PWM - -if STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32L5_TIM17_CHANNEL1 - -config STM32L5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32L5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32L5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32L5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32L5_TIM17_CHANNEL1 - -endif # STM32L5_PWM_MULTICHAN - -if !STM32L5_PWM_MULTICHAN - -config STM32L5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32L5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32L5_PWM_MULTICHAN - -endif # STM32L5_TIM17_PWM - -config STM32L5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32L5_TIM1_PWM || STM32L5_TIM2_PWM || STM32L5_TIM3_PWM || STM32L5_TIM4_PWM || STM32L5_TIM5_PWM || STM32L5_TIM8_PWM || STM32L5_TIM15_PWM || STM32L5_TIM16_PWM || STM32L5_TIM17_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32L5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32L5_TIM1 && STM32L5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32L5_TIM1_ADC1 - depends on STM32L5_TIM1_ADC - -config STM32L5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32L5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32L5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32L5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32L5_TIM2 && STM32L5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32L5_TIM2_ADC1 - depends on STM32L5_TIM2_ADC - -config STM32L5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32L5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32L5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32L5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32L5_TIM3 && STM32L5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32L5_TIM3_ADC1 - depends on STM32L5_TIM3_ADC - -config STM32L5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32L5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32L5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32L5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32L5_TIM4 && STM32L5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32L5_TIM4_ADC1 - depends on STM32L5_TIM4_ADC - -config STM32L5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32L5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32L5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32L5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32L5_TIM6 && STM32L5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32L5_TIM6_ADC1 - depends on STM32L5_TIM6_ADC - -config STM32L5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32L5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32L5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32L5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32L5_TIM8 && STM32L5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32L5_TIM8_ADC1 - depends on STM32L5_TIM8_ADC - -config STM32L5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32L5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32L5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32L5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32L5_TIM15 && STM32L5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32L5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32L5_TIM15_ADC1 - depends on STM32L5_TIM15_ADC - -config STM32L5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32L5_ADC1 - select STM32L5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32L5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32L5_ADC2 - select STM32L5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32L5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32L5_ADC3 - select STM32L5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32L5_HAVE_ADC1_TIMER - bool - -config STM32L5_HAVE_ADC2_TIMER - bool - -config STM32L5_HAVE_ADC3_TIMER - bool - -config STM32L5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32L5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32L5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32L5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32L5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32L5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32L5_TIM1 && STM32L5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32L5_TIM1_DAC1 - depends on STM32L5_TIM1_DAC - -config STM32L5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32L5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32L5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32L5_TIM2 && STM32L5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32L5_TIM2_DAC1 - depends on STM32L5_TIM2_DAC - -config STM32L5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32L5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32L5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32L5_TIM3 && STM32L5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32L5_TIM3_DAC1 - depends on STM32L5_TIM3_DAC - -config STM32L5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32L5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32L5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32L5_TIM4 && STM32L5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32L5_TIM4_DAC1 - depends on STM32L5_TIM4_DAC - -config STM32L5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32L5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32L5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32L5_TIM5 && STM32L5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32L5_TIM5_DAC1 - depends on STM32L5_TIM5_DAC - -config STM32L5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32L5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32L5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32L5_TIM6 && STM32L5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32L5_TIM6_DAC1 - depends on STM32L5_TIM6_DAC - -config STM32L5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32L5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32L5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32L5_TIM7 && STM32L5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32L5_TIM7_DAC1 - depends on STM32L5_TIM7_DAC - -config STM32L5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32L5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32L5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32L5_TIM8 && STM32L5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32L5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32L5_TIM8_DAC1 - depends on STM32L5_TIM8_DAC - -config STM32L5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32L5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32L5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32L5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32L5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32L5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32L5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32L5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32L5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32L5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32L5_ADC - -config STM32L5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32L5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32L5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32L5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32L5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32L5_ADC1 && STM32L5_DFSDM1 && (STM32L5_STM32L596XX || STM32L5_STM32L5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32L5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32L5_ADC2 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32L5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32L5_ADC3 && STM32L5_DFSDM1 && STM32L5_STM32L596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32L5_DAC - -config STM32L5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32L5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC1_DMA - -config STM32L5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32L5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32L5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32L5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32L5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32L5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32L5_DAC2_DMA - -config STM32L5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32L5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32L5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32L5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32L5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32L5_DFSDM1 - -config STM32L5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32L5_STM32L5X3 - select STM32L5_DFSDM - -config STM32L5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32L5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32L5_SERIALDRIVER - bool - -config STM32L5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32L5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32L5_LPUART1_SERIALDRIVER - depends on STM32L5_LPUART1 - -config STM32L5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32L5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32L5_LPUART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32L5_USART1_SERIALDRIVER - depends on STM32L5_USART1 - -config STM32L5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32L5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32L5_USART1 && (STM32L5_DMA1 || STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32L5_USART2_SERIALDRIVER - depends on STM32L5_USART2 - -config STM32L5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32L5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32L5_USART2 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32L5_USART3_SERIALDRIVER - depends on STM32L5_USART3 - -config STM32L5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32L5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32L5_USART3 && (STM32L5_DMA1 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32L5_UART4_SERIALDRIVER - depends on STM32L5_UART4 - -config STM32L5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32L5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32L5_UART4 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32L5_UART5_SERIALDRIVER - depends on STM32L5_UART5 - -config STM32L5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32L5_SERIALDRIVER - -config STM32L5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32L5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32L5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32L5_UART5 && (STM32L5_DMA2 || STM32L5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32L5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32L5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32L5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32L5_USART1 || STM32L5_USART2 || STM32L5_USART3 || STM32L5_UART4 || STM32L5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32L5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32L5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32L5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32L5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32L5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32L5_USART && STM32L5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32L5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32L5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32L5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32L5 serial driver. - -config STM32L5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32L5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32L5 serial driver. - -config STM32L5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32L5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32L5 serial driver. - -if PM - -config STM32L5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32L5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32L5_SPI - -config STM32L5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32L5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32L5_SPI_INTERRUPT. - -endmenu - -menu "I2C Configuration" - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32L5_I2C - -config STM32L5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32L5_I2C - -config STM32L5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -config STM32L5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32L5_I2C && !STM32L5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32L5_SDMMC - -config STM32L5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32L5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32L5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32L5_SDMMC1 - -config STM32L5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32L5_CAN1 || STM32L5_CAN2 - -config STM32L5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32L5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32L5_CAN1 is defined. - -config STM32L5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32L5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32L5_CAN2 is defined. - -config STM32L5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32L5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32L5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32L5_TIM1 || STM32L5_TIM2 || STM32L5_TIM3 || STM32L5_TIM4 || STM32L5_TIM5 || STM32L5_TIM8 - -config STM32L5_TIM1_QE - bool "TIM1" - default n - depends on STM32L5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32L5_TIM1_QE - -config STM32L5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM2_QE - bool "TIM2" - default n - depends on STM32L5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32L5_TIM2_QE - -config STM32L5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM3_QE - bool "TIM3" - default n - depends on STM32L5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32L5_TIM3_QE - -config STM32L5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM4_QE - bool "TIM4" - default n - depends on STM32L5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32L5_TIM4_QE - -config STM32L5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM5_QE - bool "TIM5" - default n - depends on STM32L5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32L5_TIM5_QE - -config STM32L5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_TIM8_QE - bool "TIM8" - default n - depends on STM32L5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32L5_TIM8_QE - -config STM32L5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32L5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32L5_QENCODER_SAMPLE_FDTS_4 - -config STM32L5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32L5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32L5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32L5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32L5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32L5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32L5_QENCODER_FILTER - prompt "Input channel event count" - default STM32L5_QENCODER_SAMPLE_EVENT_6 - -config STM32L5_QENCODER_SAMPLE_EVENT_1 - depends on STM32L5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32L5_QENCODER_SAMPLE_EVENT_2 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32L5_QENCODER_SAMPLE_EVENT_4 - depends on STM32L5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32L5_QENCODER_SAMPLE_EVENT_5 - depends on STM32L5_QENCODER_SAMPLE_FDTS_16 || STM32L5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32L5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32L5_QENCODER_SAMPLE_FDTS && !STM32L5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32L5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32L5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32L5_SAI - -choice - prompt "Operation mode" - default STM32L5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32L5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32L5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32L5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32L5_SAI1_BOTH_ASYNC - depends on STM32L5_SAI1_A && STM32L5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32L5_SAI2_BOTH_ASYNC - depends on STM32L5_SAI2_A && STM32L5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32L5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32L5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32L5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32L5 diff --git a/arch/arm/src/stm32l5/Make.defs b/arch/arm/src/stm32l5/Make.defs index e9f17420e4c..4c69a8265bc 100644 --- a/arch/arm/src/stm32l5/Make.defs +++ b/arch/arm/src/stm32l5/Make.defs @@ -56,6 +56,6 @@ endif # Required chip type specific files -ifeq ($(CONFIG_STM32L5_STM32L562XX),y) +ifeq ($(CONFIG_STM32_STM32L562XX),y) CHIP_CSRCS += stm32l562xx_rcc.c endif diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h index 3e2b1449eb8..64d4f7215e2 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_rcc.h @@ -29,7 +29,7 @@ #include -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -865,5 +865,5 @@ # define RCC_CCIPR2_OSPISEL_MSI (1 << RCC_CCIPR2_OSPISEL_SHIFT) # define RCC_CCIPR2_OSPISEL_PLL48M1CLK (2 << RCC_CCIPR2_OSPISEL_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_RCC_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h index fd82d211a58..9d900a32adf 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l562xx_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) /**************************************************************************** * Pre-processor Definitions @@ -133,5 +133,5 @@ #define SYSCFG_RSSCMDR_SHIFT 0 #define SYSCFG_RSSCMDR_MASK (0xFFFF << SYSCFG_RSSCMDR_SHIFT) -#endif /* CONFIG_STM32L5_STM32L562XX */ +#endif /* CONFIG_STM32_STM32L562XX */ #endif /* __ARCH_ARM_SRC_STM32L5_HARDWARE_STM32L562XX_SYSCFG_H */ diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h index 4020e680781..aa2363786a1 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_flash.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32L5_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32L5_FLASH_OVERRIDE_x @@ -46,33 +46,33 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32L5_FLASH_CONFIG_E) -# define CONFIG_STM32L5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32L5_FLASH_CONFIG_C -# undef CONFIG_STM32L5_FLASH_CONFIG_E -# if defined(CONFIG_STM32L5_FLASH_OVERRIDE_C) -# define CONFIG_STM32L5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32L5_FLASH_OVERRIDE_E) -# define CONFIG_STM32L5_FLASH_CONFIG_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32L5_FLASH_CONFIG_C) /* 256 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 64 # define STM32_FLASH_PAGESIZE 4096 -#elif defined(CONFIG_STM32L5_FLASH_CONFIG_E) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 4096 #else diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h index ee73d999963..9329d6bf0e0 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_pinmap.h" #else # error "Unsupported STM32 L5 pin map" diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h index e449f201f10..1e8eba96ff9 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_spi.h @@ -36,7 +36,7 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # define STM32_SPI_CLK_MAX 55000000UL #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h index c7ad3250550..3462b10413a 100644 --- a/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h +++ b/arch/arm/src/stm32l5/hardware/stm32l5_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_syscfg.h" #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/src/stm32l5/stm32l562xx_rcc.c b/arch/arm/src/stm32l5/stm32l562xx_rcc.c index 50591f093a3..aaac7fb7bff 100644 --- a/arch/arm/src/stm32l5/stm32l562xx_rcc.c +++ b/arch/arm/src/stm32l5/stm32l562xx_rcc.c @@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32L5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -92,19 +92,19 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32L5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32L5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32L5_DMAMUX1 +#ifdef CONFIG_STM32_DMAMUX1 /* DMAMUX1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; @@ -116,13 +116,13 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32L5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32L5_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; @@ -183,25 +183,25 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32L5_ADC) +#if defined(CONFIG_STM32_ADC) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; #endif -#ifdef CONFIG_STM32L5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32L5_HASH +#ifdef CONFIG_STM32_HASH /* Hash module enable */ regval |= RCC_AHB2ENR_HASHEN #endif -#ifdef CONFIG_STM32L5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -246,13 +246,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32L5_FMC +#ifdef CONFIG_STM32_FMC /* Flexible memory controller clock enable */ regval |= RCC_AHB3ENR_FMCEN; #endif -#ifdef CONFIG_STM32L5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 /* OCTOSPI1 module clock enable */ regval |= RCC_AHB3ENR_OSPI1EN; @@ -279,43 +279,43 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 /* TIM3 clock enable */ regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 /* TIM4 clock enable */ regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 /* TIM5 clock enable */ regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 /* TIM6 clock enable */ regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 /* TIM7 clock enable */ regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32L5_RTC +#ifdef CONFIG_STM32_RTC /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; @@ -327,55 +327,55 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 /* SPI3 clock enable */ regval |= RCC_APB1ENR1_SPI3EN; #endif -#ifdef CONFIG_STM32L5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32L5_USART3 +#ifdef CONFIG_STM32_USART3 /* USART3 clock enable */ regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32L5_UART4 +#ifdef CONFIG_STM32_UART4 /* UART4 clock enable */ regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32L5_UART5 +#ifdef CONFIG_STM32_UART5 /* UART5 clock enable */ regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32L5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32L5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32L5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; @@ -396,19 +396,19 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR1_PWREN; -#if defined (CONFIG_STM32L5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC1 interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32L5_OPAMP +#ifdef CONFIG_STM32_OPAMP /* OPAMP clock enable */ regval |= RCC_APB1ENR1_OPAMPEN; #endif -#ifdef CONFIG_STM32L5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -420,43 +420,43 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32L5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32L5_I2C4 +#ifdef CONFIG_STM32_I2C4 /* I2C4 clock enable */ regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32L5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32L5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; #endif -#ifdef CONFIG_STM32L5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 /* FDCAN1 clock enable */ regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32L5_USBFS +#ifdef CONFIG_STM32_USBFS /* USB FS clock enable */ regval |= RCC_APB1ENR2_USBFSEN; #endif -#ifdef CONFIG_STM32L5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 /* UCPD1 clock enable */ regval |= RCC_APB1ENR2_UCPD1EN; @@ -483,7 +483,7 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32L5_SYSCFG) || defined(CONFIG_STM32L5_COMP) +#if defined(CONFIG_STM32_SYSCFG) || defined(CONFIG_STM32_COMP) /* System configuration controller, comparators, and voltage reference * buffer clock enable */ @@ -491,61 +491,61 @@ static inline void rcc_enableapb2(void) regval |= RCC_APB2ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 /* TIM8 clock enable */ regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32L5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 /* TIM15 clock enable */ regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32L5_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32L5_SAI2 +#ifdef CONFIG_STM32_SAI2 /* SAI2 clock enable */ regval |= RCC_APB2ENR_SAI2EN; #endif -#ifdef CONFIG_STM32L5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* DFSDM clock enable */ regval |= RCC_APB2ENR_DFSDMEN; @@ -598,7 +598,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -753,7 +753,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32L5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -812,7 +812,7 @@ void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32L5_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -847,7 +847,7 @@ void stm32_stdclockconfig(void) } #endif -#ifdef CONFIG_STM32L5_SAI2PLL +#ifdef CONFIG_STM32_SAI2PLL /* Configure SAI2 PLL */ regval = getreg32(STM32_RCC_PLLSAI2CFG); @@ -898,7 +898,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32L5_IWDG) || defined(CONFIG_STM32L5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32l5/stm32l5_allocateheap.c b/arch/arm/src/stm32l5/stm32l5_allocateheap.c index d2c56c99527..c71cae5c6c1 100644 --- a/arch/arm/src/stm32l5/stm32l5_allocateheap.c +++ b/arch/arm/src/stm32l5/stm32l5_allocateheap.c @@ -60,7 +60,7 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32L5_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC=y : Enables the FSMC * CONFIG_STM32L5_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC @@ -71,7 +71,7 @@ * include the additional regions. */ -#ifndef CONFIG_STM32L5_FSMC +#ifndef CONFIG_STM32_FSMC # undef CONFIG_STM32L5_FSMC_SRAM #endif @@ -116,14 +116,14 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32L5_SRAM2_HEAP) + \ - defined(CONFIG_STM32L5_SRAM3_HEAP) + \ +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ defined(CONFIG_STM32L5_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -312,7 +312,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32L5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -332,7 +332,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32L5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h index a6b73b00ad5..9b3550752a4 100644 --- a/arch/arm/src/stm32l5/stm32l5_dbgmcu.h +++ b/arch/arm/src/stm32l5/stm32l5_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_dbgmcu.h" #else # error "Unsupported STM32L5 chip" diff --git a/arch/arm/src/stm32l5/stm32l5_exti.h b/arch/arm/src/stm32l5/stm32l5_exti.h index b64a8055015..6ea54c3b1de 100644 --- a/arch/arm/src/stm32l5/stm32l5_exti.h +++ b/arch/arm/src/stm32l5/stm32l5_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32l5/stm32l5_flash.c b/arch/arm/src/stm32l5/stm32l5_flash.c index 8f9625bb34c..f4182f8239a 100644 --- a/arch/arm/src/stm32l5/stm32l5_flash.c +++ b/arch/arm/src/stm32l5/stm32l5_flash.c @@ -50,11 +50,11 @@ #include "stm32l5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32L5_STM32L562XX) +#if !defined(CONFIG_STM32_STM32L562XX) # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32L5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32l5/stm32l5_gpio.h b/arch/arm/src/stm32l5/stm32l5_gpio.h index 16caeb1a50e..b258f8feef1 100644 --- a/arch/arm/src/stm32l5/stm32l5_gpio.h +++ b/arch/arm/src/stm32l5/stm32l5_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_gpio.h" #else # error "Unsupported STM32L5 chip" diff --git a/arch/arm/src/stm32l5/stm32l5_idle.c b/arch/arm/src/stm32l5/stm32l5_idle.c index 99d9448c1a0..2c259c32df5 100644 --- a/arch/arm/src/stm32l5/stm32l5_idle.c +++ b/arch/arm/src/stm32l5/stm32l5_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32L5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32l5/stm32l5_lse.c b/arch/arm/src/stm32l5/stm32l5_lse.c index e89c3a1887b..0a18e77e627 100644 --- a/arch/arm/src/stm32l5/stm32l5_lse.c +++ b/arch/arm/src/stm32l5/stm32l5_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32L5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32L5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.c b/arch/arm/src/stm32l5/stm32l5_rcc.c index d0a29a8c2c6..b624e1aed3d 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.c +++ b/arch/arm/src/stm32l5/stm32l5_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32L5_PWR) && defined(CONFIG_STM32L5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32l5/stm32l5_rcc.h b/arch/arm/src/stm32l5/stm32l5_rcc.h index 0b3f4a7740a..bfb2c42d2ae 100644 --- a/arch/arm/src/stm32l5/stm32l5_rcc.h +++ b/arch/arm/src/stm32l5/stm32l5_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l562xx_rcc.h" #else # error "Unsupported STM32L5 chip" @@ -100,7 +100,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -123,7 +123,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -138,7 +138,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -155,7 +155,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index ea07188a10c..9e994dfb0c3 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32L5_DMA1) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32L5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32L5_DMA2) && !defined(CONFIG_STM32L5_DMAMUX) -# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32L5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32L5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32L5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32L5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32L5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32L5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32l5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1021,7 +1021,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) uint32_t cr1; uint32_t brr; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { /* LPUART BRR = 256 * fCK / baud */ @@ -1111,7 +1111,7 @@ static void stm32l5serial_setformat(struct uart_dev_s *dev) regval = stm32l5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1315,37 +1315,37 @@ static void stm32l5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1414,7 +1414,7 @@ static int stm32l5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32L5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1765,8 +1765,8 @@ static int stm32l5serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32L5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32L5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1909,7 +1909,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1987,7 +1987,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2038,7 +2038,7 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32L5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2175,8 +2175,8 @@ static int stm32l5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32L5_USART_BREAKS -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2404,7 +2404,7 @@ static bool stm32l5serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32L5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2756,7 +2756,7 @@ static void stm32l5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32L5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3097,7 +3097,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3126,7 +3126,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32L5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32l5/stm32l5_spi.c b/arch/arm/src/stm32l5/stm32l5_spi.c index c1a374c8b91..87c822ee87a 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.c +++ b/arch/arm/src/stm32l5/stm32l5_spi.c @@ -76,15 +76,15 @@ #include "chip.h" #include "stm32.h" #include "stm32l5_gpio.h" -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # include "stm32l5_dma.h" #endif #include "stm32l5_spi.h" #include -#if defined(CONFIG_STM32L5_SPI1) || defined(CONFIG_STM32L5_SPI2) || \ - defined(CONFIG_STM32L5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -94,19 +94,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32L5_SPI_INTERRUPTS) && defined(CONFIG_STM32L5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -140,10 +140,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -187,7 +187,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxwait(struct stm32_spidev_s *priv); static void spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -247,7 +247,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -287,10 +287,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMACHAN_SPI1_RX, @@ -305,7 +305,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -345,10 +345,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -361,7 +361,7 @@ static struct stm32_spidev_s g_spi2dev = }; #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_spi3ops = { .lock = spi_lock, @@ -401,10 +401,10 @@ static struct stm32_spidev_s g_spi3dev = }, .spibase = STM32_SPI3_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32L5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI3, #endif -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI3_RX, .txch = DMACHAN_SPI3_TX, .rxsem = SEM_INITIALIZER(0), @@ -635,7 +635,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -666,7 +666,7 @@ static void spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -697,7 +697,7 @@ static void spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -712,7 +712,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -727,7 +727,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -747,7 +747,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -767,7 +767,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -818,7 +818,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -869,7 +869,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -885,7 +885,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1353,8 +1353,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32L5_SPI_DMA) || defined(CONFIG_STM32L5_DMACAPABLE) -#if !defined(CONFIG_STM32L5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1437,7 +1437,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32L5_SPI_DMA || CONFIG_STM32L5_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1460,13 +1460,13 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; -#ifdef CONFIG_STM32L5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer && @@ -1524,7 +1524,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32L5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1545,7 +1545,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1748,7 +1748,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32L5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. * NOTE: stm32_dmachannel() will always assign the DMA channel. * If the channel is not available, then stm32_dmachannel() will @@ -1804,7 +1804,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1829,7 +1829,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1854,7 +1854,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -1887,4 +1887,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32L5_SPI1 || CONFIG_STM32L5_SPI2 || CONFIG_STM32L5_SPI3 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32l5/stm32l5_spi.h b/arch/arm/src/stm32l5/stm32l5_spi.h index 005843df694..022c3479ddc 100644 --- a/arch/arm/src/stm32l5/stm32l5_spi.h +++ b/arch/arm/src/stm32l5/stm32l5_spi.h @@ -104,21 +104,21 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -146,19 +146,19 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32L5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32L5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); diff --git a/arch/arm/src/stm32l5/stm32l5_start.c b/arch/arm/src/stm32l5/stm32l5_start.c index 919e9edafea..45d63d4f1b6 100644 --- a/arch/arm/src/stm32l5/stm32l5_start.c +++ b/arch/arm/src/stm32l5/stm32l5_start.c @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32L5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32l5/stm32l5_tim.c b/arch/arm/src/stm32l5/stm32l5_tim.c index 509c9f3e9bb..7ed539190e4 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim.c +++ b/arch/arm/src/stm32l5/stm32l5_tim.c @@ -73,118 +73,118 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32L5_TIM1_PWM) || defined (CONFIG_STM32L5_TIM1_ADC) || \ - defined(CONFIG_STM32L5_TIM1_DAC) || defined(CONFIG_STM32L5_TIM1_QE) -# undef CONFIG_STM32L5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32L5_TIM2_PWM) || defined (CONFIG_STM32L5_TIM2_ADC) || \ - defined(CONFIG_STM32L5_TIM2_DAC) || defined(CONFIG_STM32L5_TIM2_QE) -# undef CONFIG_STM32L5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32L5_TIM3_PWM) || defined (CONFIG_STM32L5_TIM3_ADC) || \ - defined(CONFIG_STM32L5_TIM3_DAC) || defined(CONFIG_STM32L5_TIM3_QE) -# undef CONFIG_STM32L5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32L5_TIM4_PWM) || defined (CONFIG_STM32L5_TIM4_ADC) || \ - defined(CONFIG_STM32L5_TIM4_DAC) || defined(CONFIG_STM32L5_TIM4_QE) -# undef CONFIG_STM32L5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32L5_TIM5_PWM) || defined (CONFIG_STM32L5_TIM5_ADC) || \ - defined(CONFIG_STM32L5_TIM5_DAC) || defined(CONFIG_STM32L5_TIM5_QE) -# undef CONFIG_STM32L5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32L5_TIM6_ADC) || \ - defined(CONFIG_STM32L5_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) -# undef CONFIG_STM32L5_TIM6 +#if defined(CONFIG_STM32L5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32L5_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32L5_TIM7_PWM) || defined (CONFIG_STM32L5_TIM7_ADC) || \ - defined(CONFIG_STM32L5_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) -# undef CONFIG_STM32L5_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32L5_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32L5_TIM8_PWM) || defined (CONFIG_STM32L5_TIM8_ADC) || \ - defined(CONFIG_STM32L5_TIM8_DAC) || defined(CONFIG_STM32L5_TIM8_QE) -# undef CONFIG_STM32L5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32L5_TIM15_PWM) || defined (CONFIG_STM32L5_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32L5_TIM15_DAC) || defined(CONFIG_STM32L5_TIM15_QE) -# undef CONFIG_STM32L5_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32L5_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32L5_TIM16_ADC) || \ defined(CONFIG_STM32L5_TIM16_DAC) || defined(CONFIG_STM32L5_TIM16_QE) -# undef CONFIG_STM32L5_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32L5_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32L5_TIM17_ADC) || \ defined(CONFIG_STM32L5_TIM17_DAC) || defined(CONFIG_STM32L5_TIM17_QE) -# undef CONFIG_STM32L5_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32L5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,7 +301,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -309,7 +309,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -318,7 +318,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -327,7 +327,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -336,7 +336,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -345,7 +345,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -354,7 +354,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -363,7 +363,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -372,7 +372,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -381,7 +381,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -390,7 +390,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -654,66 +654,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -769,64 +769,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -875,13 +875,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32L5_TIM2) || defined(CONFIG_STM32L5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: #endif return counter; @@ -987,7 +987,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1020,7 +1020,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1053,7 +1053,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1086,7 +1086,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1118,7 +1118,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1151,7 +1151,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1184,7 +1184,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1217,7 +1217,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1250,7 +1250,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1366,65 +1366,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1509,76 +1509,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1616,66 +1616,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1692,4 +1692,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32L5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c index bc5367fa376..789b50c7bdc 100644 --- a/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c +++ b/arch/arm/src/stm32l5/stm32l5_tim_lowerhalf.c @@ -41,12 +41,12 @@ #include "stm32l5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32L5_TIM1) || defined(CONFIG_STM32L5_TIM2) || \ - defined(CONFIG_STM32L5_TIM3) || defined(CONFIG_STM32L5_TIM4) || \ - defined(CONFIG_STM32L5_TIM5) || defined(CONFIG_STM32L5_TIM6) || \ - defined(CONFIG_STM32L5_TIM7) || defined(CONFIG_STM32L5_TIM8) || \ - defined(CONFIG_STM32L5_TIM15) || defined(CONFIG_STM32L5_TIM16) || \ - defined(CONFIG_STM32L5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32L5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32L5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32l5/stm32l5_uart.h b/arch/arm/src/stm32l5/stm32l5_uart.h index 30bbad7b7bc..3afcb99c656 100644 --- a/arch/arm/src/stm32l5/stm32l5_uart.h +++ b/arch/arm/src/stm32l5/stm32l5_uart.h @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32L5_STM32L562XX) +#if defined(CONFIG_STM32_STM32L562XX) # include "hardware/stm32l5_uart.h" #else # error "Unsupported STM32L5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32L5_HAVE_UART5) -# undef CONFIG_STM32L5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32L5_HAVE_UART4) -# undef CONFIG_STM32L5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART3) -# undef CONFIG_STM32L5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART2) -# undef CONFIG_STM32L5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32L5_HAVE_USART1) -# undef CONFIG_STM32L5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32L5_HAVE_LPUART1) -# undef CONFIG_STM32L5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32L5_LPUART1) -# undef CONFIG_STM32L5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32L5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART1) -# undef CONFIG_STM32L5_USART1_SERIALDRIVER -# undef CONFIG_STM32L5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART2) -# undef CONFIG_STM32L5_USART2_SERIALDRIVER -# undef CONFIG_STM32L5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_USART3) -# undef CONFIG_STM32L5_USART3_SERIALDRIVER -# undef CONFIG_STM32L5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART4) -# undef CONFIG_STM32L5_UART4_SERIALDRIVER -# undef CONFIG_STM32L5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32L5_UART5) -# undef CONFIG_STM32L5_UART5_SERIALDRIVER -# undef CONFIG_STM32L5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32L5_LPUART1) || defined(CONFIG_STM32L5_USART1) || \ - defined(CONFIG_STM32L5_USART2) || defined(CONFIG_STM32L5_USART3) || \ - defined(CONFIG_STM32L5_UART4) || defined(CONFIG_STM32L5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32L5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32L5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32L5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32L5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32L5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32L5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32L5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32L5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig index 14235ae1136..f92e3c47ba9 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig +++ b/boards/arm/stm32l5/nucleo-l552ze/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD="nucleo-l552ze" CONFIG_ARCH_BOARD_NUCLEO_L552ZE=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L552ZE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -49,9 +50,9 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_LPUART1=y -CONFIG_STM32L5_RTC=y -CONFIG_STM32L5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_RTC=y +CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32l5/nucleo-l552ze/include/board.h b/boards/arm/stm32l5/nucleo-l552ze/include/board.h index 26c4c29257a..954e20c733b 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/include/board.h +++ b/boards/arm/stm32l5/nucleo-l552ze/include/board.h @@ -108,7 +108,7 @@ /* Enable CLK48; get it from HSI48 */ -#if defined(CONFIG_STM32L5_USBFS) || defined(CONFIG_STM32L5_RNG) +#if defined(CONFIG_STM32_USBFS) || defined(CONFIG_STM32_RNG) # define STM32_USE_CLK48 1 # define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48 # define STM32_HSI48_SYNCSRC SYNCSRC_NONE diff --git a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c index 218995b6634..7ba2e3c8fab 100644 --- a/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c +++ b/boards/arm/stm32l5/nucleo-l552ze/src/stm32_boot.c @@ -56,7 +56,7 @@ void stm32_board_initialize(void) { stm32_pwr_vddio2_valid(true); -#if defined(CONFIG_STM32L5_LPUART1) +#if defined(CONFIG_STM32_LPUART1) /* LPUART1 uses PG7/PG8 which are powered by VDDIO2. The GPIO config in * stm32_lowsetup() runs before VDDIO2 is enabled, so GPIOG writes * silently fail. Reconfigure here after VDDIO2 is valid. diff --git a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig index 2edfa787c5e..6f19b7f9874 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig +++ b/boards/arm/stm32l5/stm32l562e-dk/configs/nsh/defconfig @@ -10,9 +10,10 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l562e-dk" CONFIG_ARCH_BOARD_STM32L562E_DK=y -CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG=y +CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32l5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L562QE=y CONFIG_ARCH_CHIP_STM32L5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -44,7 +45,7 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32L5_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_STACKMONITOR=y CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c index 4dd66b53512..79ba04835ac 100644 --- a/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l5/stm32l562e-dk/src/stm32_clockconfig.c @@ -37,13 +37,13 @@ * Currently the STM32L562E-DK board support is restricted to running NuttX * in the Non-Secure domain together with TrustedFirmware-M (TFM). In this * setup the clock configuration is done by TFM, not by NuttX. Thus, the - * board's configuration sets CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG + * board's configuration sets CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG * to avoid the standard clock config logic to run and instead do just * nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } From a517f9f20e11ceec8fe62cf35243c79495aa70ba Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 18 May 2026 18:02:30 +0200 Subject: [PATCH 091/268] !arch/stm32u5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32U5 Kconfig symbols were renamed from CONFIG_STM32U5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- .../stm32u5/boards/b-u585i-iot02a/index.rst | 6 +- arch/arm/Kconfig | 1 + arch/arm/include/stm32u5/chip.h | 8 +- arch/arm/include/stm32u5/irq.h | 4 +- arch/arm/include/stm32u5/stm32u5xx_irq.h | 8 +- arch/arm/src/stm32u5/Kconfig | 3637 +---------------- arch/arm/src/stm32u5/hardware/stm32_flash.h | 32 +- .../src/stm32u5/hardware/stm32_memorymap.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_pinmap.h | 2 +- arch/arm/src/stm32u5/hardware/stm32_spi.h | 4 +- arch/arm/src/stm32u5/hardware/stm32_syscfg.h | 2 +- arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h | 4 +- arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h | 4 +- .../src/stm32u5/hardware/stm32u5xx_syscfg.h | 4 +- arch/arm/src/stm32u5/stm32_allocateheap.c | 22 +- arch/arm/src/stm32u5/stm32_dbgmcu.h | 2 +- arch/arm/src/stm32u5/stm32_exti.h | 2 +- arch/arm/src/stm32u5/stm32_flash.c | 6 +- arch/arm/src/stm32u5/stm32_gpio.h | 2 +- arch/arm/src/stm32u5/stm32_i2c.c | 96 +- arch/arm/src/stm32u5/stm32_i2c.h | 8 +- arch/arm/src/stm32u5/stm32_idle.c | 2 +- arch/arm/src/stm32u5/stm32_lse.c | 20 +- arch/arm/src/stm32u5/stm32_rcc.c | 10 +- arch/arm/src/stm32u5/stm32_rcc.h | 10 +- arch/arm/src/stm32u5/stm32_serial.c | 96 +- arch/arm/src/stm32u5/stm32_spi.c | 118 +- arch/arm/src/stm32u5/stm32_spi.h | 12 +- arch/arm/src/stm32u5/stm32_start.c | 2 +- arch/arm/src/stm32u5/stm32_tim.c | 246 +- arch/arm/src/stm32u5/stm32_tim_lowerhalf.c | 56 +- arch/arm/src/stm32u5/stm32_uart.h | 104 +- arch/arm/src/stm32u5/stm32u5xx_rcc.c | 160 +- .../b-u585i-iot02a/configs/nsh/defconfig | 9 +- .../stm32u5/b-u585i-iot02a/src/CMakeLists.txt | 2 +- .../arm/stm32u5/b-u585i-iot02a/src/Makefile | 2 +- .../b-u585i-iot02a/src/stm32_clockconfig.c | 4 +- .../stm32u5/b-u585i-iot02a/src/stm32_spi.c | 18 +- .../nucleo-u5a5zj-q/configs/nsh/defconfig | 17 +- .../nucleo-u5a5zj-q/src/CMakeLists.txt | 2 +- .../arm/stm32u5/nucleo-u5a5zj-q/src/Makefile | 2 +- .../nucleo-u5a5zj-q/src/stm32_clockconfig.c | 4 +- .../stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c | 18 +- 43 files changed, 702 insertions(+), 4070 deletions(-) diff --git a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst index 38846fffccc..60af81e77fa 100644 --- a/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst +++ b/Documentation/platforms/arm/stm32u5/boards/b-u585i-iot02a/index.rst @@ -102,9 +102,9 @@ NOTES: output on USART3, as described above under "Serial Console". The elevant configuration settings are listed below:: - CONFIG_STM32L5_USART3=y - CONFIG_STM32L5_USART3_SERIALDRIVER=y - CONFIG_STM32L5_USART=y + CONFIG_STM32_USART3=y + CONFIG_STM32_USART3_SERIALDRIVER=y + CONFIG_STM32_USART=y CONFIG_USART3_SERIALDRIVER=y CONFIG_USART3_SERIAL_CONSOLE=y diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 78fb0616167..febe16549dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -716,6 +716,7 @@ config ARCH_CHIP_STM32L5 config ARCH_CHIP_STM32U5 bool "STMicro STM32 U5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM33 select ARCH_HAVE_MPU select ARM_HAVE_DSP diff --git a/arch/arm/include/stm32u5/chip.h b/arch/arm/include/stm32u5/chip.h index 887ca72d38a..e0590348d6f 100644 --- a/arch/arm/include/stm32u5/chip.h +++ b/arch/arm/include/stm32u5/chip.h @@ -36,11 +36,11 @@ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_SRAM1_SIZE (0x00030000) /* 192Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x00080000) /* 512kB SRAM3 */ -#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) +#elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_SRAM1_SIZE (0x000C0000) /* 768Kb SRAM1 */ # define STM32_SRAM2_SIZE (0x00010000) /* 64kB SRAM2 */ # define STM32_SRAM3_SIZE (0x000d0000) /* 832kB SRAM3 */ @@ -49,7 +49,7 @@ # error "Unsupported STM32U5 chip" #endif -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # define STM32_NFSMC 1 /* Have FSMC memory controller */ # define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ # define STM32_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */ @@ -78,7 +78,7 @@ # define STM32_NCRC 1 /* CRC */ # define STM32_NCOMP 2 /* Comparators */ # define STM32_NOPAMP 2 /* Operational Amplifiers */ -#endif /* CONFIG_STM32U5_STM32U585XX */ +#endif /* CONFIG_STM32_STM32U585XX */ #if defined(CONFIG_STM32U5_STM32U5A5ZJT) # define STM32_NUSBOTGHS 1 /* USB OTG HS */ diff --git a/arch/arm/include/stm32u5/irq.h b/arch/arm/include/stm32u5/irq.h index 77c5c600bde..9810b119e02 100644 --- a/arch/arm/include/stm32u5/irq.h +++ b/arch/arm/include/stm32u5/irq.h @@ -34,9 +34,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # include #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/include/stm32u5/stm32u5xx_irq.h b/arch/arm/include/stm32u5/stm32u5xx_irq.h index f1042c3d4a9..e29a074fde6 100644 --- a/arch/arm/include/stm32u5/stm32u5xx_irq.h +++ b/arch/arm/include/stm32u5/stm32u5xx_irq.h @@ -131,10 +131,10 @@ #define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 71) /* 71: TIM17 global interrupt */ #define STM32_IRQ_COMP (STM32_IRQ_FIRST + 72) /* 72: COMP1/COMP2 interrupts */ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_IRQ_OTG_FS (STM32_IRQ_FIRST + 73) /* 73: USB OTG FS global interrupt */ #elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_IRQ_OTG_HS (STM32_IRQ_FIRST + 73) /* 73: USB OTG HS global interrupt */ #else # error "Unsupported STM32U5 chip" @@ -192,9 +192,9 @@ #define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 124) /* 124: FMAC interrupt */ #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_IRQ_NEXTINTS 125 #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/Kconfig b/arch/arm/src/stm32u5/Kconfig index 0a6b6cff64f..95e927f8b46 100644 --- a/arch/arm/src/stm32u5/Kconfig +++ b/arch/arm/src/stm32u5/Kconfig @@ -7,6 +7,71 @@ if ARCH_CHIP_STM32U5 comment "STM32U5 Configuration Options" +config STM32_U5_PERIPHERALS + bool + default y + select STM32_HAVE_COMP + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DMA2D + select STM32_HAVE_FMAC + select STM32_HAVE_FSMC + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPTIM3 + select STM32_HAVE_LPTIM4 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OTGFS if STM32_STM32U535XX || CONFIG_STM32_STM32U545XX || STM32_STM32U575XX || STM32_STM32U585XX + select STM32_HAVE_RNG + select STM32_HAVE_SAI1 + select STM32_HAVE_SAI2 + select STM32_HAVE_SDMMC1 + select STM32_HAVE_SDMMC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TSC + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_GPADMA1 + select STM32_HAVE_MDF1 + select STM32_HAVE_FLASH + select STM32_HAVE_RAMCFG + select STM32_HAVE_GTZC1 + select STM32_HAVE_GTZC2 + select STM32_HAVE_DCACHE1 + select STM32_HAVE_SRAM1 + select STM32_HAVE_SRAM2 + select STM32_HAVE_SRAM3 + select STM32_HAVE_SRAM5 + select STM32_HAVE_DCMI_PSSI + select STM32_HAVE_PKA + select STM32_HAVE_SAES + select STM32_HAVE_OCTOSPIM + select STM32_HAVE_OTFDEC1 + select STM32_HAVE_OTFDEC2 + select STM32_HAVE_OCTOSPI1 + select STM32_HAVE_OCTOSPI2 + select STM32_HAVE_LPGPIO1 + select STM32_HAVE_LPDMA1 + select STM32_HAVE_ADF1 + select STM32_HAVE_UCPD1 + select STM32_HAVE_VREF + select STM32_HAVE_RTCAPB + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_WDG_M3M4_V1 + choice prompt "STM32 U5 Chip Selection" default ARCH_CHIP_STM32U585AI @@ -14,15 +79,15 @@ choice config ARCH_CHIP_STM32U585AI bool "STM32U585AI" - select STM32U5_STM32U585XX - select STM32U5_FLASH_CONFIG_I + select STM32_STM32U585XX + select STM32_FLASH_CONFIG_I select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 2048 Kb FLASH, 768 Kb SRAM config ARCH_CHIP_STM32U5A5ZJT bool "STM32U5A5ZJT" - select STM32U5_STM32U5A5XX + select STM32_STM32U5A5XX select STM32U5_IO_CONFIG_A ---help--- STM32 U5 Cortex M33, 4096 Kb FLASH, 2500 Kb SRAM, tqfp144 @@ -31,3551 +96,115 @@ endchoice # STM32 U5 Chip Selection # Chip families: -config STM32U5_STM32U5A5XX - # STM32U575 and STM32U585 devices documented in RM0456 +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U5A5XX + bool + default n + select STM32_HAVE_OTGHS + select ARCH_HAVE_FPU + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C5 + select STM32_HAVE_I2C6 + +# STM32U575 and STM32U585 devices documented in RM0456 +config STM32_STM32U585XX bool default n select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -config STM32U5_STM32U585XX - # STM32U575 and STM32U585 devices documented in RM0456 - bool - default n - select ARCH_HAVE_FPU - select STM32U5_HAVE_LPUART1 - select STM32U5_HAVE_USART1 - select STM32U5_HAVE_USART2 - select STM32U5_HAVE_USART3 - select STM32U5_HAVE_UART4 - select STM32U5_HAVE_UART5 - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32U5 - default STM32U5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32U5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32U585AI is chosen, the Flash configuration would be 'I', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32U5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32U5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32U5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32U5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32U5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32U5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32U5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -config STM32U5_FLASH_OVERRIDE_I - bool "I 2048 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32U5_FLASH_CONFIG_8 - bool - default n - -config STM32U5_FLASH_CONFIG_B - bool - default n - -config STM32U5_FLASH_CONFIG_C - bool - default n - -config STM32U5_FLASH_CONFIG_E - bool - default n - -config STM32U5_FLASH_CONFIG_G - bool - default n - -config STM32U5_FLASH_CONFIG_I - bool - default n + select STM32_HAVE_AES + select STM32_HAVE_CORDIC + select STM32_HAVE_IP_AES_M3M4_V1 + select STM32_HAVE_IP_CORDIC_M3M4_V1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 # Pin/package configurations config STM32U5_IO_CONFIG_K + # Package designator K bool default n config STM32U5_IO_CONFIG_T + # Package designator T bool default n config STM32U5_IO_CONFIG_C + # Package designator C bool default n config STM32U5_IO_CONFIG_R + # Package designator R bool default n config STM32U5_IO_CONFIG_J + # Package designator J bool default n config STM32U5_IO_CONFIG_M + # Package designator M bool default n config STM32U5_IO_CONFIG_V + # Package designator V bool default n config STM32U5_IO_CONFIG_Q + # Package designator Q bool default n config STM32U5_IO_CONFIG_Z + # Package designator Z bool default n config STM32U5_IO_CONFIG_A + # Package designator A bool default n -comment "STM32U5 Peripherals" - -menu "STM32U5 Peripheral Support" - -# These "hidden" settings determine is a peripheral option is available for the -# selection MCU - -config STM32U5_HAVE_LPUART1 - bool - default n - -config STM32U5_HAVE_USART1 - bool - default n - -config STM32U5_HAVE_USART2 - bool - default n - -config STM32U5_HAVE_USART3 - bool - default n - -config STM32U5_HAVE_UART4 - bool - default n - -config STM32U5_HAVE_UART5 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32U5_SPI - bool - default n - -config STM32U5_PWM - bool - default n - -config STM32U5_USART - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32U5_GPADMA1 - bool "GPADMA1" - default n - -config STM32U5_CORDIC - bool "CORDIC" - default n - -config STM32U5_FMAC - bool "FMAC" - default n - -config STM32U5_MDF1 - bool "MDF1" - default n - -config STM32U5_FLASH - bool "FLASH" - default n - -config STM32U5_CRC - bool "CRC" - default n - -config STM32U5_TSC - bool "TSC" - default n - -config STM32U5_RAMCFG - bool "RAMCFG" - default n - -config STM32U5_DMA2D - bool "DMA2D" - default n - -config STM32U5_GTZC1 - bool "GTZC1" - default n - -config STM32U5_BKPSRAM - bool "BKPSRAM" - default n - -config STM32U5_DCACHE1 - bool "DCACHE1" - default n - -config STM32U5_SRAM1 - bool "SRAM1" - default y - -config STM32U5_SRAM2 - bool "SRAM2" - default n - -config STM32U5_SRAM3 - bool "SRAM3" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -config STM32U5_SRAM5 - bool "SRAM5" - default n - depends on STM32U5_STM32U575XX || STM32U5_STM32U585XX || STM32U5_STM32U59XX || STM32U5_STM32U59AXX || \ - STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - -comment "SRAM Options" - -config STM32U5_SRAM2_HEAP - bool "SRAM2 is used for heap" - default n - depends on STM32U5_SRAM2 - select STM32U5_SRAM2_INIT - ---help--- - The STM32U5 SRAM2 region has special properties (power, protection, parity) - which may be used by the application for special purposes. But if these - special properties are not needed, it may be instead added to the heap for - use by malloc(). - NOTE: you must also select an appropriate number of memory regions in the - 'Memory Management' section. - -config STM32U5_SRAM2_INIT - bool "SRAM2 is initialized to zero" - default n - depends on STM32U5_SRAM2 - ---help--- - The STM32U5 SRAM2 region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2 is being used for it's battery-backed capability, - this may be undesirable (because it will destroy the contents). In that - case, the board should handle the initialization itself at the appropriate - time. - -config STM32U5_SRAM3_HEAP - bool "SRAM3 is used for heap" - depends on STM32U5_SRAM3 - default n - -config STM32U5_SRAM5_HEAP - bool "SRAM5 is used for heap" - depends on STM32U5_SRAM5 - default n - -comment "AHB2 Peripherals" - -config STM32U5_ADC1 - bool "ADC1" - default n - -config STM32U5_DCMI_PSSI - bool "DCMI_PSSI" - default n - -config STM32U5_OTGFS - bool "OTG FS" - depends on STM32U5_STM32U535XX || CONFIG_STM32U5_STM32U545XX || STM32U5_STM32U575XX || STM32U5_STM32U585XX - default n - -config STM32U5_OTGHS - bool "OTG HS" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - -config STM32U5_AES - bool "AES" - default n - -config STM32U5_HASH - bool "HASH" - default n - -config STM32U5_RNG - bool "RNG" - default n - -config STM32U5_PKA - bool "PKA" - default n - -config STM32U5_SAES - bool "SAES" - default n - -config STM32U5_OCTOSPIM - bool "OCTOSPIM" - default n - -config STM32U5_OTFDEC1 - bool "OTFDEC1" - default n - -config STM32U5_OTFDEC2 - bool "OTFDEC2" - default n - -config STM32U5_SDMMC1 - bool "SDMMC1" - default n - -config STM32U5_SDMMC2 - bool "SDMMC2" - default n - -config STM32U5_FSMC - bool "FSMC" - default n - -config STM32U5_OCTOSPI1 - bool "OCTOSPI1" - default n - -config STM32U5_OCTOSPI2 - bool "OCTOSPI2" - default n - -comment "AHB3 Peripherals" - -config STM32U5_LPGPIO1 - bool "LPGPIO1" - default n - -config STM32U5_PWR - bool "PWR" - default n - -config STM32U5_ADC4 - bool "ADC4" - default n - -config STM32U5_DAC1 - bool "DAC1" - default n - -config STM32U5_LPDMA1 - bool "LPDMA1" - default n - -config STM32U5_ADF1 - bool "ADF1" - default n - -config STM32U5_GTZC2 - bool "GTZC2" - default n - -comment "APB1 Peripherals" - -config STM32U5_TIM2 - bool "TIM2" - default n - -config STM32U5_TIM3 - bool "TIM3" - default n - -config STM32U5_TIM4 - bool "TIM4" - default n - -config STM32U5_TIM5 - bool "TIM5" - default n - -config STM32U5_TIM6 - bool "TIM6" - default n - -config STM32U5_TIM7 - bool "TIM7" - default n - -config STM32U5_WWDG - bool "WWDG" - default n - -config STM32U5_SPI2 - bool "SPI2" - default n - select SPI - select STM32U5_SPI - -config STM32U5_USART2 - bool "USART2" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_USART3 - bool "USART3" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART4 - bool "UART4" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_UART5 - bool "UART5" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_I2C1 - bool "I2C1" - default n - select STM32U5_I2C - -config STM32U5_I2C2 - bool "I2C2" - default n - select STM32U5_I2C - -config STM32U5_I2C3 - bool "I2C3" - default n - select STM32U5_I2C - -config STM32U5_I2C4 - bool "I2C4" - default n - select STM32U5_I2C - -config STM32U5_I2C5 - bool "I2C5" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_I2C6 - bool "I2C6" - depends on STM32U5_STM32U59XX || STM32U5_STM32U59AXX || STM32U5_STM32U5A5XX || STM32U5_STM32U5A9XX - default n - select STM32U5_I2C - -config STM32U5_CRS - bool "CRS" - default n - -config STM32U5_LPTIM2 - bool "LPTIM2" - default n - -config STM32U5_FDCAN1 - bool "FDCAN1" - default n - -config STM32U5_UCPD1 - bool "UCPD1" - default n - -comment "APB2 Peripherals" - -config STM32U5_TIM1 - bool "TIM1" - default n - -config STM32U5_SPI1 - bool "SPI1" - default n - select SPI - select STM32U5_SPI - -config STM32U5_TIM8 - bool "TIM8" - default n - -config STM32U5_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_TIM15 - bool "TIM15" - default n - -config STM32U5_TIM16 - bool "TIM16" - default n - -config STM32U5_TIM17 - bool "TIM17" - default n - -config STM32U5_SAI1 - bool "SAI1" - default n - -config STM32U5_SAI2 - bool "SAI2" - default n - -comment "APB3 Peripherals" - -config STM32U5_SYSCFG - bool "SYSCFG" - default y - -config STM32U5_SPI3 - bool "SPI3" - default n - select SPI - select STM32U5_SPI - -config STM32U5_LPUART1 - bool "LPUART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32U5_USART - -config STM32U5_LPTIM1 - bool "LPTIM1" - default n - -config STM32U5_LPTIM3 - bool "LPTIM3" - default n - -config STM32U5_LPTIM4 - bool "LPTIM4" - default n - -config STM32U5_OPAMP - bool "OPAMP" - default n - -config STM32U5_COMP - bool "COMP" - default n - -config STM32U5_VREF - bool "VREF" - default n - -config STM32U5_RTCAPB - bool "RTCAPB" - default n - -endmenu - -config STM32U5_SAI1PLL - bool "SAI1PLL" - default n - ---help--- - The STM32U5 has a separate PLL for the SAI1 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_SAI2PLL - bool "SAI2PLL" - default n - depends on STM32U5_HAVE_SAI2 - ---help--- - The STM32U5 has a separate PLL for the SAI2 block. - Set this true and provide configuration parameters in - board.h to use this PLL. - -config STM32U5_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32 clock configuration. - -menu "RTC Configuration" - depends on STM32U5_RTC - -config STM32U5_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32U5_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32U5_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32U5_RTC_LSECLOCK - depends on STM32U5_RTC - -config STM32U5_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32U5_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32U5_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32U5_RTC_LSECLOCK - -config STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - bool "Automatically boost the LSE oscillator drive capability level until it starts-up" - default n - ---help--- - This will cycle through the values from low to high. To avoid - damaging the crystal. We want to use the lowest setting that gets - the OSC running. See app note AN2867 - - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY - bool "Decrease LSE oscillator drive capability after LSE start-up" - default n - depends on !STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY - ---help--- - The LSE oscillator drive capability can remain at the level used - during LSE start-up at run-time, or it can be reduced to the - 'Low drive capability' once the LSE started up successfully. - -endif # STM32U5_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32U5_ONESHOT - bool - default y - -config STM32U5_FREERUN - bool - default y - -config STM32U5_TICKLESS_ONESHOT - int "Tickless one-shot timer channel" - default 2 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the one-shot timer needed by the OS. - -config STM32U5_TICKLESS_FREERUN - int "Tickless free-running timer channel" - default 5 - range 1 8 - depends on STM32U5_FREERUN - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provide the free-running timer needed by the OS. - -endif # SCHED_TICKLESS - -if !SCHED_TICKLESS - -config STM32U5_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32U5_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endif # !SCHED_TICKLESS - -config STM32U5_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32U5_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -config STM32U5_LPTIM1_PWM - bool "LPTIM1 PWM" - default n - depends on STM32U5_LPTIM1 - select PWM - ---help--- - Reserve low-power timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM1_PWM - -choice - prompt "LPTIM1 clock source" - default STM32U5_LPTIM1_CLK_APB1 - -config STM32U5_LPTIM1_CLK_APB1 - bool "Clock LPTIM1 from APB1" - -config STM32U5_LPTIM1_CLK_LSE - bool "Clock LPTIM1 from LSE" - -config STM32U5_LPTIM1_CLK_LSI - bool "Clock LPTIM1 from LSI" - -config STM32U5_LPTIM1_CLK_HSI - bool "Clock LPTIM1 from HSI" -endchoice - -endif # STM32U5_LPTIM1_PWM - -config STM32U5_LPTIM2_PWM - bool "LPTIM2 PWM" - default n - depends on STM32U5_LPTIM2 - select PWM - ---help--- - Reserve low-power timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_LPTIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_LPTIM2_PWM - -choice - prompt "LPTIM2 clock source" - default STM32U5_LPTIM2_CLK_APB1 - -config STM32U5_LPTIM2_CLK_APB1 - bool "Clock LPTIM2 from APB1" - -config STM32U5_LPTIM2_CLK_LSE - bool "Clock LPTIM2 from LSE" - -config STM32U5_LPTIM2_CLK_LSI - bool "Clock LPTIM2 from LSI" - -config STM32U5_LPTIM2_CLK_HSI - bool "Clock LPTIM2 from HSI" -endchoice - -endif # STM32U5_LPTIM2_PWM - -config STM32U5_TIM1_PWM - bool "TIM1 PWM" - default n - depends on STM32U5_TIM1 - select STM32U5_PWM - ---help--- - Reserve timer 1 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM1 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM1_PWM - -config STM32U5_TIM1_MODE - int "TIM1 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL1 - bool "TIM1 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CH1MODE - int "TIM1 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH1OUT - bool "TIM1 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM1_CH1NOUT - bool "TIM1 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM1_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM1_CHANNEL1 - -config STM32U5_TIM1_CHANNEL2 - bool "TIM1 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CH2MODE - int "TIM1 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH2OUT - bool "TIM1 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM1_CH2NOUT - bool "TIM1 Channel 2 Complemenrary Output" - default n - depends on STM32U5_TIM1_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM1_CHANNEL2 - -config STM32U5_TIM1_CHANNEL3 - bool "TIM1 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CH3MODE - int "TIM1 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH3OUT - bool "TIM1 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM1_CH3NOUT - bool "TIM1 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM1_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM1_CHANNEL3 - -config STM32U5_TIM1_CHANNEL5 - bool "TIM1 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM1_CHANNEL5 - -config STM32U5_TIM1_CH4MODE - int "TIM1 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM1_CH4OUT - bool "TIM1 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM1_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM1_CHANNEL - int "TIM1 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM1 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM1_CHMODE - int "TIM1 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM1_PWM - -config STM32U5_TIM2_PWM - bool "TIM2 PWM" - default n - depends on STM32U5_TIM2 - select STM32U5_PWM - ---help--- - Reserve timer 2 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM2 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM2_PWM - -config STM32U5_TIM2_MODE - int "TIM2 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL1 - bool "TIM2 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CH1MODE - int "TIM2 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH1OUT - bool "TIM2 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM2_CHANNEL1 - -config STM32U5_TIM2_CHANNEL2 - bool "TIM2 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CH2MODE - int "TIM2 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH2OUT - bool "TIM2 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM2_CHANNEL2 - -config STM32U5_TIM2_CHANNEL3 - bool "TIM2 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CH3MODE - int "TIM2 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH3OUT - bool "TIM2 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM2_CHANNEL3 - -config STM32U5_TIM2_CHANNEL5 - bool "TIM2 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM2_CHANNEL5 - -config STM32U5_TIM2_CH4MODE - int "TIM2 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM2_CH4OUT - bool "TIM2 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM2_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM2_CHANNEL - int "TIM2 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM2 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM2_CHMODE - int "TIM2 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM2_PWM - -config STM32U5_TIM3_PWM - bool "TIM3 PWM" - default n - depends on STM32U5_TIM3 - select STM32U5_PWM - ---help--- - Reserve timer 3 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM3 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM3_PWM - -config STM32U5_TIM3_MODE - int "TIM3 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL1 - bool "TIM3 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CH1MODE - int "TIM3 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH1OUT - bool "TIM3 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM3_CHANNEL1 - -config STM32U5_TIM3_CHANNEL2 - bool "TIM3 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CH2MODE - int "TIM3 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH2OUT - bool "TIM3 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM3_CHANNEL2 - -config STM32U5_TIM3_CHANNEL3 - bool "TIM3 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CH3MODE - int "TIM3 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH3OUT - bool "TIM3 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM3_CHANNEL3 - -config STM32U5_TIM3_CHANNEL5 - bool "TIM3 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM3_CHANNEL5 - -config STM32U5_TIM3_CH4MODE - int "TIM3 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM3_CH4OUT - bool "TIM3 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM3_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM3_CHANNEL - int "TIM3 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM3 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM3_CHMODE - int "TIM3 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM3_PWM - -config STM32U5_TIM4_PWM - bool "TIM4 PWM" - default n - depends on STM32U5_TIM4 - select STM32U5_PWM - ---help--- - Reserve timer 4 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM4 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM4_PWM - -config STM32U5_TIM4_MODE - int "TIM4 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL1 - bool "TIM4 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CH1MODE - int "TIM4 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH1OUT - bool "TIM4 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM4_CHANNEL1 - -config STM32U5_TIM4_CHANNEL2 - bool "TIM4 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CH2MODE - int "TIM4 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH2OUT - bool "TIM4 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM4_CHANNEL2 - -config STM32U5_TIM4_CHANNEL3 - bool "TIM4 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CH3MODE - int "TIM4 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH3OUT - bool "TIM4 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM4_CHANNEL3 - -config STM32U5_TIM4_CHANNEL5 - bool "TIM4 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM4_CHANNEL5 - -config STM32U5_TIM4_CH4MODE - int "TIM4 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM4_CH4OUT - bool "TIM4 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM4_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM4_CHANNEL - int "TIM4 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM4 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM4_CHMODE - int "TIM4 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM4_PWM - -config STM32U5_TIM5_PWM - bool "TIM5 PWM" - default n - depends on STM32U5_TIM5 - select STM32U5_PWM - ---help--- - Reserve timer 5 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM5 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM5_PWM - -config STM32U5_TIM5_MODE - int "TIM5 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL1 - bool "TIM5 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CH1MODE - int "TIM5 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH1OUT - bool "TIM5 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32U5_TIM5_CHANNEL1 - -config STM32U5_TIM5_CHANNEL2 - bool "TIM5 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CH2MODE - int "TIM5 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH2OUT - bool "TIM5 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM5_CHANNEL2 - -config STM32U5_TIM5_CHANNEL3 - bool "TIM5 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CH3MODE - int "TIM5 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH3OUT - bool "TIM5 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -endif # STM32U5_TIM5_CHANNEL3 - -config STM32U5_TIM5_CHANNEL5 - bool "TIM5 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM5_CHANNEL5 - -config STM32U5_TIM5_CH4MODE - int "TIM5 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM5_CH4OUT - bool "TIM5 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM5_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM5_CHANNEL - int "TIM5 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM5 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM5_CHMODE - int "TIM5 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM5_PWM - -config STM32U5_TIM8_PWM - bool "TIM8 PWM" - default n - depends on STM32U5_TIM8 - select STM32U5_PWM - ---help--- - Reserve timer 8 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM8 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM8_PWM - -config STM32U5_TIM8_MODE - int "TIM8 Mode" - default 0 - range 0 4 - ---help--- - Specifies the timer mode. - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL1 - bool "TIM8 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CH1MODE - int "TIM8 Channel 1 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH1OUT - bool "TIM8 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM8_CH1NOUT - bool "TIM8 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM8_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM8_CHANNEL1 - -config STM32U5_TIM8_CHANNEL2 - bool "TIM8 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CH2MODE - int "TIM8 Channel 2 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH2OUT - bool "TIM8 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -config STM32U5_TIM8_CH2NOUT - bool "TIM8 Channel 2 Complementary Output" - default n - depends on STM32U5_TIM8_CH2OUT - ---help--- - Enables channel 2 complementary output. - -endif # STM32U5_TIM8_CHANNEL2 - -config STM32U5_TIM8_CHANNEL3 - bool "TIM8 Channel 3" - default n - ---help--- - Enables channel 3. - -if STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CH3MODE - int "TIM8 Channel 3 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH3OUT - bool "TIM8 Channel 3 Output" - default n - ---help--- - Enables channel 3 output. - -config STM32U5_TIM8_CH3NOUT - bool "TIM8 Channel 3 Complementary Output" - default n - depends on STM32U5_TIM8_CH3OUT - ---help--- - Enables channel 3 complementary output. - -endif # STM32U5_TIM8_CHANNEL3 - -config STM32U5_TIM8_CHANNEL5 - bool "TIM8 Channel 4" - default n - ---help--- - Enables channel 4. - -if STM32U5_TIM8_CHANNEL5 - -config STM32U5_TIM8_CH4MODE - int "TIM8 Channel 4 Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM8_CH4OUT - bool "TIM8 Channel 4 Output" - default n - ---help--- - Enables channel 4 output. - -endif # STM32U5_TIM8_CHANNEL5 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM8_CHANNEL - int "TIM8 PWM Output Channel" - default 1 - range 1 4 - ---help--- - If TIM8 is enabled for PWM usage, you also need specifies the timer output - channel {1,..,4} - -config STM32U5_TIM8_CHMODE - int "TIM8 Channel Mode" - default 0 - range 0 5 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM8_PWM - -config STM32U5_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32U5_TIM15 - select STM32U5_PWM - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM15_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM15_CH1NOUT - bool "TIM15 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM15_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM15_CHANNEL1 - -config STM32U5_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32U5_TIM15_CHANNEL2 - -config STM32U5_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32U5_TIM15_CHANNEL2 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32U5_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM15_PWM - -config STM32U5_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32U5_TIM16 - select STM32U5_PWM - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM16_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM16_CHANNEL1 - -config STM32U5_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM16_CH1NOUT - bool "TIM16 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM16_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM16_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM16_PWM - -config STM32U5_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32U5_TIM17 - select STM32U5_PWM - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32U5_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32U5_TIM17_PWM - -if STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32U5_TIM17_CHANNEL1 - -config STM32U5_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32U5_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -config STM32U5_TIM17_CH1NOUT - bool "TIM17 Channel 1 Complementary Output" - default n - depends on STM32U5_TIM17_CH1OUT - ---help--- - Enables channel 1 complementary output. - -endif # STM32U5_TIM17_CHANNEL1 - -endif # STM32U5_PWM_MULTICHAN - -if !STM32U5_PWM_MULTICHAN - -config STM32U5_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32U5_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32U5_PWM_MULTICHAN - -endif # STM32U5_TIM17_PWM - -config STM32U5_PWM_MULTICHAN - bool "PWM Multiple Output Channels" - default n - depends on STM32U5_PWM - ---help--- - Specifies that the PWM driver supports multiple output - channels per timer. - -config STM32U5_TIM1_ADC - bool "TIM1 ADC" - default n - depends on STM32U5_TIM1 && STM32U5_ADC - ---help--- - Reserve timer 1 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM1 ADC channel" - default STM32U5_TIM1_ADC1 - depends on STM32U5_TIM1_ADC - -config STM32U5_TIM1_ADC1 - bool "TIM1 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM1 to trigger ADC1 - -config STM32U5_TIM1_ADC2 - bool "TIM1 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM1 to trigger ADC2 - -config STM32U5_TIM1_ADC3 - bool "TIM1 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM1 to trigger ADC3 - -endchoice - -config STM32U5_TIM2_ADC - bool "TIM2 ADC" - default n - depends on STM32U5_TIM2 && STM32U5_ADC - ---help--- - Reserve timer 2 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM2 ADC channel" - default STM32U5_TIM2_ADC1 - depends on STM32U5_TIM2_ADC - -config STM32U5_TIM2_ADC1 - bool "TIM2 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM2 to trigger ADC1 - -config STM32U5_TIM2_ADC2 - bool "TIM2 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM2 to trigger ADC2 - -config STM32U5_TIM2_ADC3 - bool "TIM2 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM2 to trigger ADC3 - -endchoice - -config STM32U5_TIM3_ADC - bool "TIM3 ADC" - default n - depends on STM32U5_TIM3 && STM32U5_ADC - ---help--- - Reserve timer 3 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM3 ADC channel" - default STM32U5_TIM3_ADC1 - depends on STM32U5_TIM3_ADC - -config STM32U5_TIM3_ADC1 - bool "TIM3 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM3 to trigger ADC1 - -config STM32U5_TIM3_ADC2 - bool "TIM3 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM3 to trigger ADC2 - -config STM32U5_TIM3_ADC3 - bool "TIM3 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM3 to trigger ADC3 - -endchoice - -config STM32U5_TIM4_ADC - bool "TIM4 ADC" - default n - depends on STM32U5_TIM4 && STM32U5_ADC - ---help--- - Reserve timer 4 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM4 ADC channel" - default STM32U5_TIM4_ADC1 - depends on STM32U5_TIM4_ADC - -config STM32U5_TIM4_ADC1 - bool "TIM4 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM4 to trigger ADC1 - -config STM32U5_TIM4_ADC2 - bool "TIM4 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM4 to trigger ADC2 - -config STM32U5_TIM4_ADC3 - bool "TIM4 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM4 to trigger ADC3 - -endchoice - -config STM32U5_TIM6_ADC - bool "TIM6 ADC" - default n - depends on STM32U5_TIM6 && STM32U5_ADC - ---help--- - Reserve timer 6 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM6 ADC channel" - default STM32U5_TIM6_ADC1 - depends on STM32U5_TIM6_ADC - -config STM32U5_TIM6_ADC1 - bool "TIM6 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM6 to trigger ADC1 - -config STM32U5_TIM6_ADC2 - bool "TIM6 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM6 to trigger ADC2 - -config STM32U5_TIM6_ADC3 - bool "TIM6 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM6 to trigger ADC3 - -endchoice - -config STM32U5_TIM8_ADC - bool "TIM8 ADC" - default n - depends on STM32U5_TIM8 && STM32U5_ADC - ---help--- - Reserve timer 8 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM8 ADC channel" - default STM32U5_TIM8_ADC1 - depends on STM32U5_TIM8_ADC - -config STM32U5_TIM8_ADC1 - bool "TIM8 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM8 to trigger ADC1 - -config STM32U5_TIM8_ADC2 - bool "TIM8 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM8 to trigger ADC2 - -config STM32U5_TIM8_ADC3 - bool "TIM8 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM8 to trigger ADC3 - -endchoice - -config STM32U5_TIM15_ADC - bool "TIM15 ADC" - default n - depends on STM32U5_TIM15 && STM32U5_ADC - ---help--- - Reserve timer 15 for use by ADC - - Timer devices may be used for different purposes. If STM32U5_TIM15 is - defined then the following may also be defined to indicate that the - timer is intended to be used for ADC conversion. Note that ADC usage - requires two definition: Not only do you have to assign the timer - for used by the ADC, but then you also have to configure which ADC - channel it is assigned to. - -choice - prompt "Select TIM15 ADC channel" - default STM32U5_TIM15_ADC1 - depends on STM32U5_TIM15_ADC - -config STM32U5_TIM15_ADC1 - bool "TIM15 ADC channel 1" - depends on STM32U5_ADC1 - select STM32U5_HAVE_ADC1_TIMER - ---help--- - Reserve TIM15 to trigger ADC1 - -config STM32U5_TIM15_ADC2 - bool "TIM15 ADC channel 2" - depends on STM32U5_ADC2 - select STM32U5_HAVE_ADC2_TIMER - ---help--- - Reserve TIM15 to trigger ADC2 - -config STM32U5_TIM15_ADC3 - bool "TIM15 ADC channel 3" - depends on STM32U5_ADC3 - select STM32U5_HAVE_ADC3_TIMER - ---help--- - Reserve TIM15 to trigger ADC3 - -endchoice - -config STM32U5_HAVE_ADC1_TIMER - bool - -config STM32U5_HAVE_ADC2_TIMER - bool - -config STM32U5_HAVE_ADC3_TIMER - bool - -config STM32U5_ADC1_SAMPLE_FREQUENCY - int "ADC1 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - ADC1 sampling frequency. Default: 100Hz - -config STM32U5_ADC1_TIMTRIG - int "ADC1 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC1_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC2_SAMPLE_FREQUENCY - int "ADC2 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - ADC2 sampling frequency. Default: 100Hz - -config STM32U5_ADC2_TIMTRIG - int "ADC2 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC2_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_ADC3_SAMPLE_FREQUENCY - int "ADC3 Sampling Frequency" - default 100 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - ADC3 sampling frequency. Default: 100Hz - -config STM32U5_ADC3_TIMTRIG - int "ADC3 Timer Trigger" - default 0 - range 0 4 - depends on STM32U5_HAVE_ADC3_TIMER - ---help--- - Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO - -config STM32U5_TIM1_DAC - bool "TIM1 DAC" - default n - depends on STM32U5_TIM1 && STM32U5_DAC - ---help--- - Reserve timer 1 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM1 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM1 DAC channel" - default STM32U5_TIM1_DAC1 - depends on STM32U5_TIM1_DAC - -config STM32U5_TIM1_DAC1 - bool "TIM1 DAC channel 1" - ---help--- - Reserve TIM1 to trigger DAC1 - -config STM32U5_TIM1_DAC2 - bool "TIM1 DAC channel 2" - ---help--- - Reserve TIM1 to trigger DAC2 - -endchoice - -config STM32U5_TIM2_DAC - bool "TIM2 DAC" - default n - depends on STM32U5_TIM2 && STM32U5_DAC - ---help--- - Reserve timer 2 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM2 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM2 DAC channel" - default STM32U5_TIM2_DAC1 - depends on STM32U5_TIM2_DAC - -config STM32U5_TIM2_DAC1 - bool "TIM2 DAC channel 1" - ---help--- - Reserve TIM2 to trigger DAC1 - -config STM32U5_TIM2_DAC2 - bool "TIM2 DAC channel 2" - ---help--- - Reserve TIM2 to trigger DAC2 - -endchoice - -config STM32U5_TIM3_DAC - bool "TIM3 DAC" - default n - depends on STM32U5_TIM3 && STM32U5_DAC - ---help--- - Reserve timer 3 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM3 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM3 DAC channel" - default STM32U5_TIM3_DAC1 - depends on STM32U5_TIM3_DAC - -config STM32U5_TIM3_DAC1 - bool "TIM3 DAC channel 1" - ---help--- - Reserve TIM3 to trigger DAC1 - -config STM32U5_TIM3_DAC2 - bool "TIM3 DAC channel 2" - ---help--- - Reserve TIM3 to trigger DAC2 - -endchoice - -config STM32U5_TIM4_DAC - bool "TIM4 DAC" - default n - depends on STM32U5_TIM4 && STM32U5_DAC - ---help--- - Reserve timer 4 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM4 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM4 DAC channel" - default STM32U5_TIM4_DAC1 - depends on STM32U5_TIM4_DAC - -config STM32U5_TIM4_DAC1 - bool "TIM4 DAC channel 1" - ---help--- - Reserve TIM4 to trigger DAC1 - -config STM32U5_TIM4_DAC2 - bool "TIM4 DAC channel 2" - ---help--- - Reserve TIM4 to trigger DAC2 - -endchoice - -config STM32U5_TIM5_DAC - bool "TIM5 DAC" - default n - depends on STM32U5_TIM5 && STM32U5_DAC - ---help--- - Reserve timer 5 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM5 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM5 DAC channel" - default STM32U5_TIM5_DAC1 - depends on STM32U5_TIM5_DAC - -config STM32U5_TIM5_DAC1 - bool "TIM5 DAC channel 1" - ---help--- - Reserve TIM5 to trigger DAC1 - -config STM32U5_TIM5_DAC2 - bool "TIM5 DAC channel 2" - ---help--- - Reserve TIM5 to trigger DAC2 - -endchoice - -config STM32U5_TIM6_DAC - bool "TIM6 DAC" - default n - depends on STM32U5_TIM6 && STM32U5_DAC - ---help--- - Reserve timer 6 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM6 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM6 DAC channel" - default STM32U5_TIM6_DAC1 - depends on STM32U5_TIM6_DAC - -config STM32U5_TIM6_DAC1 - bool "TIM6 DAC channel 1" - ---help--- - Reserve TIM6 to trigger DAC1 - -config STM32U5_TIM6_DAC2 - bool "TIM6 DAC channel 2" - ---help--- - Reserve TIM6 to trigger DAC2 - -endchoice - -config STM32U5_TIM7_DAC - bool "TIM7 DAC" - default n - depends on STM32U5_TIM7 && STM32U5_DAC - ---help--- - Reserve timer 7 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM7 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM7 DAC channel" - default STM32U5_TIM7_DAC1 - depends on STM32U5_TIM7_DAC - -config STM32U5_TIM7_DAC1 - bool "TIM7 DAC channel 1" - ---help--- - Reserve TIM7 to trigger DAC1 - -config STM32U5_TIM7_DAC2 - bool "TIM7 DAC channel 2" - ---help--- - Reserve TIM7 to trigger DAC2 - -endchoice - -config STM32U5_TIM8_DAC - bool "TIM8 DAC" - default n - depends on STM32U5_TIM8 && STM32U5_DAC - ---help--- - Reserve timer 8 for use by DAC - - Timer devices may be used for different purposes. If STM32U5_TIM8 is - defined then the following may also be defined to indicate that the - timer is intended to be used for DAC conversion. Note that DAC usage - requires two definition: Not only do you have to assign the timer - for used by the DAC, but then you also have to configure which DAC - channel it is assigned to. - -choice - prompt "Select TIM8 DAC channel" - default STM32U5_TIM8_DAC1 - depends on STM32U5_TIM8_DAC - -config STM32U5_TIM8_DAC1 - bool "TIM8 DAC channel 1" - ---help--- - Reserve TIM8 to trigger DAC1 - -config STM32U5_TIM8_DAC2 - bool "TIM8 DAC channel 2" - ---help--- - Reserve TIM8 to trigger DAC2 - -endchoice - -config STM32U5_TIM1_CAP - bool "TIM1 Capture" - default n - depends on STM32U5_HAVE_TIM1 - ---help--- - Reserve timer 1 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM2_CAP - bool "TIM2 Capture" - default n - depends on STM32U5_HAVE_TIM2 - ---help--- - Reserve timer 2 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM3_CAP - bool "TIM3 Capture" - default n - depends on STM32U5_HAVE_TIM3 - ---help--- - Reserve timer 3 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM4_CAP - bool "TIM4 Capture" - default n - depends on STM32U5_HAVE_TIM4 - ---help--- - Reserve timer 4 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM5_CAP - bool "TIM5 Capture" - default n - depends on STM32U5_HAVE_TIM5 - ---help--- - Reserve timer 5 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -config STM32U5_TIM8_CAP - bool "TIM8 Capture" - default n - depends on STM32U5_HAVE_TIM8 - ---help--- - Reserve timer 8 for use by Capture - - Timer devices may be used for different purposes. One special purpose is - to capture input. - -endmenu # Timer Configuration - -menu "ADC Configuration" - depends on STM32U5_ADC - -config STM32U5_ADC1_DMA - bool "ADC1 DMA" - depends on STM32U5_ADC1 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC2_DMA - bool "ADC2 DMA" - depends on STM32U5_ADC2 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC3_DMA - bool "ADC3 DMA" - depends on STM32U5_ADC3 - default n - ---help--- - If DMA is selected, then the ADC may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -config STM32U5_ADC1_OUTPUT_DFSDM - bool "ADC1 output to DFSDM" - depends on STM32U5_ADC1 && STM32U5_DFSDM1 && (STM32U5_STM32U596XX || STM32U5_STM32U5XR) - default n - ---help--- - Route ADC1 output directly to DFSDM parallel inputs. - -config STM32U5_ADC2_OUTPUT_DFSDM - bool "ADC2 output to DFSDM" - depends on STM32U5_ADC2 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC2 output directly to DFSDM parallel inputs. - -config STM32U5_ADC3_OUTPUT_DFSDM - bool "ADC3 output to DFSDM" - depends on STM32U5_ADC3 && STM32U5_DFSDM1 && STM32U5_STM32U596XX - default n - ---help--- - Route ADC3 output directly to DFSDM parallel inputs. - -endmenu - -menu "DAC Configuration" - depends on STM32U5_DAC - -config STM32U5_DAC1_DMA - bool "DAC1 DMA" - depends on STM32U5_DAC1 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC1_DMA - -config STM32U5_DAC1_TIMER - int "DAC1 timer" - range 2 8 - -config STM32U5_DAC1_TIMER_FREQUENCY - int "DAC1 timer frequency" - default 100 - ---help--- - DAC1 output frequency. Default: 100Hz - -config STM32U5_DAC1_DMA_BUFFER_SIZE - int "DAC1 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC1_OUTPUT_ADC - bool "DAC1 output to ADC" - depends on STM32U5_DAC1 - default n - ---help--- - Route DAC1 output to ADC input instead of external pin. - -config STM32U5_DAC2_DMA - bool "DAC2 DMA" - depends on STM32U5_DAC2 - default n - ---help--- - If DMA is selected, then a timer and output frequency must also be - provided to support the DMA transfer. The DMA transfer could be - supported by an EXTI trigger, but this feature is not currently - supported by the driver. - -if STM32U5_DAC2_DMA - -config STM32U5_DAC2_TIMER - int "DAC2 timer" - default 0 - range 2 8 - -config STM32U5_DAC2_TIMER_FREQUENCY - int "DAC2 timer frequency" - default 100 - ---help--- - DAC2 output frequency. Default: 100Hz - -config STM32U5_DAC2_DMA_BUFFER_SIZE - int "DAC2 DMA buffer size" - default 1 - -endif - -config STM32U5_DAC2_OUTPUT_ADC - bool "DAC2 output to ADC" - depends on STM32U5_DAC2 - default n - ---help--- - Route DAC2 output to ADC input instead of external pin. - -endmenu - -menu "DFSDM Configuration" - depends on STM32U5_DFSDM1 - -config STM32U5_DFSDM1_FLT0 - bool "DFSDM1 Filter 0" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT1 - bool "DFSDM1 Filter 1" - default n - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT2 - bool "DFSDM1 Filter 2" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_FLT3 - bool "DFSDM1 Filter 3" - default n - depends on !STM32U5_STM32U5X3 - select STM32U5_DFSDM - -config STM32U5_DFSDM1_DMA - bool "DFSDM1 DMA" - depends on STM32U5_DFSDM - default n - ---help--- - If DMA is selected, then the DFSDM may be configured to support - DMA transfer, which is necessary if multiple channels are read - or if very high trigger frequencies are used. - -endmenu - -config STM32U5_SERIALDRIVER - bool - -config STM32U5_1WIREDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32U5_USART - -choice - prompt "LPUART1 Driver Configuration" - default STM32U5_LPUART1_SERIALDRIVER - depends on STM32U5_LPUART1 - -config STM32U5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_LPUART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32U5_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32U5_LPUART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32U5_USART1_SERIALDRIVER - depends on STM32U5_USART1 - -config STM32U5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART1_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32U5_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32U5_USART1 && (STM32U5_DMA1 || STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -choice - prompt "USART2 Driver Configuration" - default STM32U5_USART2_SERIALDRIVER - depends on STM32U5_USART2 - -config STM32U5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART2_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART2 Driver Configuration - -if USART2_SERIALDRIVER - -config USART2_RS485 - bool "RS-485 on USART2" - default n - depends on STM32U5_USART2 - ---help--- - Enable RS-485 interface on USART2. Your board config will have to - provide GPIO_USART2_RS485_DIR pin definition. Currently it cannot be - used with USART2_RXDMA. - -config USART2_RS485_DIR_POLARITY - int "USART2 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART2_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART2. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART2_RXDMA - bool "USART2 Rx DMA" - default n - depends on STM32U5_USART2 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART2_SERIALDRIVER - -choice - prompt "USART3 Driver Configuration" - default STM32U5_USART3_SERIALDRIVER - depends on STM32U5_USART3 - -config STM32U5_USART3_SERIALDRIVER - bool "Standard serial driver" - select USART3_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_USART3_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # USART3 Driver Configuration - -if USART3_SERIALDRIVER - -config USART3_RS485 - bool "RS-485 on USART3" - default n - depends on STM32U5_USART3 - ---help--- - Enable RS-485 interface on USART3. Your board config will have to - provide GPIO_USART3_RS485_DIR pin definition. Currently it cannot be - used with USART3_RXDMA. - -config USART3_RS485_DIR_POLARITY - int "USART3 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART3_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART3. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART3_RXDMA - bool "USART3 Rx DMA" - default n - depends on STM32U5_USART3 && (STM32U5_DMA1 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART3_SERIALDRIVER - -choice - prompt "UART4 Driver Configuration" - default STM32U5_UART4_SERIALDRIVER - depends on STM32U5_UART4 - -config STM32U5_UART4_SERIALDRIVER - bool "Standard serial driver" - select UART4_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART4_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART4 Driver Configuration - -if UART4_SERIALDRIVER - -config UART4_RS485 - bool "RS-485 on UART4" - default n - depends on STM32U5_UART4 - ---help--- - Enable RS-485 interface on UART4. Your board config will have to - provide GPIO_UART4_RS485_DIR pin definition. Currently it cannot be - used with UART4_RXDMA. - -config UART4_RS485_DIR_POLARITY - int "UART4 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART4_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART4. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART4_RXDMA - bool "UART4 Rx DMA" - default n - depends on STM32U5_UART4 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART4_SERIALDRIVER - -choice - prompt "UART5 Driver Configuration" - default STM32U5_UART5_SERIALDRIVER - depends on STM32U5_UART5 - -config STM32U5_UART5_SERIALDRIVER - bool "Standard serial driver" - select UART5_SERIALDRIVER - select STM32U5_SERIALDRIVER - -config STM32U5_UART5_1WIREDRIVER - bool "1-Wire driver" - select STM32U5_1WIREDRIVER - -endchoice # UART5 Driver Configuration - -if UART5_SERIALDRIVER - -config UART5_RS485 - bool "RS-485 on UART5" - default n - depends on STM32U5_UART5 - ---help--- - Enable RS-485 interface on UART5. Your board config will have to - provide GPIO_UART5_RS485_DIR pin definition. Currently it cannot be - used with UART5_RXDMA. - -config UART5_RS485_DIR_POLARITY - int "UART5 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on UART5_RS485 - ---help--- - Polarity of DIR pin for RS-485 on UART5. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config UART5_RXDMA - bool "UART5 Rx DMA" - default n - depends on STM32U5_UART5 && (STM32U5_DMA2 || STM32U5_DMAMUX) - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # UART5_SERIALDRIVER - -if STM32U5_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32U5_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA || USART2_RXDMA || USART3_RXDMA || UART4_RXDMA || UART5_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32U5_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32U5_USART1 || STM32U5_USART2 || STM32U5_USART3 || STM32U5_UART4 || STM32U5_UART5 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32U5_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32U5_USART - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32 have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32U5_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32U5_USART - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32 manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32U5_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32U5_USART && STM32U5_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32U5 U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32U5_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32U5_USART - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32U5 serial driver. - -config STM32U5_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32U5_USART - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32U5 serial driver. - -config STM32U5_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32U5_USART - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32U5 serial driver. - -if PM - -config STM32U5_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif -endif # STM32U5_SERIALDRIVER - -endmenu # U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32U5_SPI - -config STM32U5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32U5_SPI_DMA - bool "SPI DMA" - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32U5_SPI_INTERRUPT. - -endmenu - -config STM32U5_I2C - bool - default n - -menu "I2C Configuration" - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO - bool "Use dynamic timeouts" - default n - depends on STM32U5_I2C - -config STM32U5_I2C_DYNTIMEO_USECPERBYTE - int "Timeout Microseconds per Byte" - default 500 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2C_DYNTIMEO_STARTSTOP - int "Timeout for Start/Stop (Milliseconds)" - default 1000 - depends on STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOSEC - int "Timeout seconds" - default 0 - depends on STM32U5_I2C - -config STM32U5_I2CTIMEOMS - int "Timeout Milliseconds" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -config STM32U5_I2CTIMEOTICKS - int "Timeout for Done and Stop (ticks)" - default 500 - depends on STM32U5_I2C && !STM32U5_I2C_DYNTIMEO - -endmenu - -menu "SD/MMC Configuration" - depends on STM32U5_SDMMC - -config STM32U5_SDMMC_XFRDEBUG - bool "SDMMC transfer debug" - depends on DEBUG_FS_INFO - default n - ---help--- - Enable special debug instrumentation analyze SDMMC data transfers. - This logic is as non-invasive as possible: It samples SDMMC - registers at key points in the data transfer and then dumps all of - the registers at the end of the transfer. If DEBUG_DMA is also - enabled, then DMA register will be collected as well. Requires also - DEBUG_FS and CONFIG_DEBUG_INFO. - -config STM32U5_SDMMC_DMA - bool "Support DMA data transfers" - default n - select SDIO_DMA - depends on STM32U5_DMA - ---help--- - Support DMA data transfers. - -menu "SDMMC1 Configuration" - depends on STM32U5_SDMMC1 - -config STM32U5_SDMMC1_DMAPRIO - hex "SDMMC1 DMA priority" - default 0x00001000 - ---help--- - Select SDMMC1 DMA priority. - - Options are: 0x00000000 low, 0x00001000 medium, - 0x00002000 high, 0x00003000 very high. Default: medium. - -config SDMMC1_WIDTH_D1_ONLY - bool "Use D1 only on SDMMC1" - default n - ---help--- - Select 1-bit transfer mode. Default: 4-bit transfer mode. - -endmenu # SDMMC1 Configuration -endmenu # SD/MMC Configuration - -menu "CAN driver configuration" - depends on STM32U5_CAN1 || STM32U5_CAN2 - -config STM32U5_CAN1_BAUD - int "CAN1 BAUD" - default 250000 - depends on STM32U5_CAN1 - ---help--- - CAN1 BAUD rate. Required if CONFIG_STM32U5_CAN1 is defined. - -config STM32U5_CAN2_BAUD - int "CAN2 BAUD" - default 250000 - depends on STM32U5_CAN2 - ---help--- - CAN2 BAUD rate. Required if CONFIG_STM32U5_CAN2 is defined. - -config STM32U5_CAN_TSEG1 - int "TSEG1 quanta" - default 6 - ---help--- - The number of CAN time quanta in segment 1. Default: 6 - -config STM32U5_CAN_TSEG2 - int "TSEG2 quanta" - default 7 - ---help--- - The number of CAN time quanta in segment 2. Default: 7 - -config STM32U5_CAN_REGDEBUG - bool "CAN Register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level CAN device debug information. - Requires also CONFIG_DEBUG_CAN_INFO. - -endmenu - -menu "QEncoder Driver" - depends on SENSORS_QENCODER - depends on STM32U5_TIM1 || STM32U5_TIM2 || STM32U5_TIM3 || STM32U5_TIM4 || STM32U5_TIM5 || STM32U5_TIM8 - -config STM32U5_TIM1_QE - bool "TIM1" - default n - depends on STM32U5_TIM1 - ---help--- - Reserve TIM1 for use by QEncoder. - -if STM32U5_TIM1_QE - -config STM32U5_TIM1_QEPSC - int "TIM1 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM2_QE - bool "TIM2" - default n - depends on STM32U5_TIM2 - ---help--- - Reserve TIM2 for use by QEncoder. - -if STM32U5_TIM2_QE - -config STM32U5_TIM2_QEPSC - int "TIM2 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM3_QE - bool "TIM3" - default n - depends on STM32U5_TIM3 - ---help--- - Reserve TIM3 for use by QEncoder. - -if STM32U5_TIM3_QE - -config STM32U5_TIM3_QEPSC - int "TIM3 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM4_QE - bool "TIM4" - default n - depends on STM32U5_TIM4 - ---help--- - Reserve TIM4 for use by QEncoder. - -if STM32U5_TIM4_QE - -config STM32U5_TIM4_QEPSC - int "TIM4 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM5_QE - bool "TIM5" - default n - depends on STM32U5_TIM5 - ---help--- - Reserve TIM5 for use by QEncoder. - -if STM32U5_TIM5_QE - -config STM32U5_TIM5_QEPSC - int "TIM5 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_TIM8_QE - bool "TIM8" - default n - depends on STM32U5_TIM8 - ---help--- - Reserve TIM8 for use by QEncoder. - -if STM32U5_TIM8_QE - -config STM32U5_TIM8_QEPSC - int "TIM8 pulse prescaler" - default 1 - ---help--- - This prescaler divides the number of recorded encoder pulses, limiting the count rate at the expense of resolution. - -endif - -config STM32U5_QENCODER_FILTER - bool "Enable filtering on STM32 QEncoder input" - default y - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel sampling frequency" - default STM32U5_QENCODER_SAMPLE_FDTS_4 - -config STM32U5_QENCODER_SAMPLE_FDTS - bool "fDTS" - -config STM32U5_QENCODER_SAMPLE_CKINT - bool "fCK_INT" - -config STM32U5_QENCODER_SAMPLE_FDTS_2 - bool "fDTS/2" - -config STM32U5_QENCODER_SAMPLE_FDTS_4 - bool "fDTS/4" - -config STM32U5_QENCODER_SAMPLE_FDTS_8 - bool "fDTS/8" - -config STM32U5_QENCODER_SAMPLE_FDTS_16 - bool "fDTS/16" - -config STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "fDTS/32" - -endchoice - -choice - depends on STM32U5_QENCODER_FILTER - prompt "Input channel event count" - default STM32U5_QENCODER_SAMPLE_EVENT_6 - -config STM32U5_QENCODER_SAMPLE_EVENT_1 - depends on STM32U5_QENCODER_SAMPLE_FDTS - bool "1" - -config STM32U5_QENCODER_SAMPLE_EVENT_2 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "2" - -config STM32U5_QENCODER_SAMPLE_EVENT_4 - depends on STM32U5_QENCODER_SAMPLE_CKINT - bool "4" - -config STM32U5_QENCODER_SAMPLE_EVENT_5 - depends on STM32U5_QENCODER_SAMPLE_FDTS_16 || STM32U5_QENCODER_SAMPLE_FDTS_32 - bool "5" - -config STM32U5_QENCODER_SAMPLE_EVENT_6 - depends on !STM32U5_QENCODER_SAMPLE_FDTS && !STM32U5_QENCODER_SAMPLE_CKINT - bool "6" - -config STM32U5_QENCODER_SAMPLE_EVENT_8 - depends on !STM32U5_QENCODER_SAMPLE_FDTS - bool "8" - -endchoice - -endmenu - -menu "SAI Configuration" - depends on STM32U5_SAI - -choice - prompt "Operation mode" - default STM32U5_SAI_DMA - ---help--- - Select the operation mode the SAI driver should use. - -config STM32U5_SAI_POLLING - bool "Polling" - ---help--- - The SAI registers are polled for events. - -config STM32U5_SAI_INTERRUPTS - bool "Interrupt" - ---help--- - Select to enable interrupt driven SAI support. - -config STM32U5_SAI_DMA - bool "DMA" - ---help--- - Use DMA to improve SAI transfer performance. - -endchoice # Operation mode - -choice - prompt "SAI1 synchronization enable" - default STM32U5_SAI1_BOTH_ASYNC - depends on STM32U5_SAI1_A && STM32U5_SAI1_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI1_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI1_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI1_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI1 synchronization enable - -choice - prompt "SAI2 synchronization enable" - default STM32U5_SAI2_BOTH_ASYNC - depends on STM32U5_SAI2_A && STM32U5_SAI2_B - ---help--- - Select the synchronization mode of the SAI sub-blocks - -config STM32U5_SAI2_BOTH_ASYNC - bool "Both asynchronous" - -config STM32U5_SAI2_A_SYNC_WITH_B - bool "Block A is synchronous with Block B" - -config STM32U5_SAI2_B_SYNC_WITH_A - bool "Block B is synchronous with Block A" - -endchoice # SAI2 synchronization enable - -endmenu - endif # ARCH_CHIP_STM32U5 diff --git a/arch/arm/src/stm32u5/hardware/stm32_flash.h b/arch/arm/src/stm32u5/hardware/stm32_flash.h index 8d201546ad1..ea9a8b6990f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_flash.h +++ b/arch/arm/src/stm32u5/hardware/stm32_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32U5_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32U5_FLASH_OVERRIDE_x @@ -44,30 +44,30 @@ */ #if defined(CONFIG_ARCH_CHIP_STM32U585AI) -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32U5_FLASH_CONFIG_E) -# define CONFIG_STM32U5_FLASH_OVERRIDE_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" # endif /* Override of the Flash has been chosen */ -# if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32U5_FLASH_CONFIG_C -# undef CONFIG_STM32U5_FLASH_CONFIG_E -# if defined(CONFIG_STM32U5_FLASH_OVERRIDE_C) -# define CONFIG_STM32U5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32U5_FLASH_OVERRIDE_E) -# define CONFIG_STM32U5_FLASH_CONFIG_E +# if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E # endif # endif /* Define the valid configuration */ -# if defined(CONFIG_STM32U5_FLASH_CONFIG_I) /* 2048 kB */ +# if defined(CONFIG_STM32_FLASH_CONFIG_I) /* 2048 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 8192 # else @@ -79,7 +79,7 @@ # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) #endif -#if defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U5A5XX) # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 8192 # define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE) diff --git a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h index 90fe085d6ee..8655250979f 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_memorymap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_memorymap.h @@ -51,7 +51,7 @@ # define STM32_SRAM1_BASE 0x20000000 /* 0x20000000-0x2002ffff: 192k SRAM1 */ # define STM32_SRAM2_BASE 0x20030000 /* 0x20030000-0x2003ffff: 64k SRAM2 */ -#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) +#elif defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ @@ -60,7 +60,7 @@ # define STM32_SRAM3_BASE 0x20040000 /* 0x20040000-0x200bffff: 512k SRAM3 */ #elif defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ # define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x081fffff: FLASH memory */ diff --git a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h index b289ebb0c42..fd741826012 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_pinmap.h +++ b/arch/arm/src/stm32u5/hardware/stm32_pinmap.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_pinmap.h" #else # error "Unsupported STM32U5 pin map" diff --git a/arch/arm/src/stm32u5/hardware/stm32_spi.h b/arch/arm/src/stm32u5/hardware/stm32_spi.h index b13c0664234..e230964aff0 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32_spi.h @@ -31,9 +31,9 @@ #include "chip.h" #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) # include "hardware/stm32u5xx_spi.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h index 120cbc4f58e..e79236a1fce 100644 --- a/arch/arm/src/stm32u5/hardware/stm32_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32_syscfg.h @@ -30,7 +30,7 @@ #include #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_syscfg.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h index a106a9e574c..3e5ca6181a3 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_rcc.h @@ -30,9 +30,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h index e7d98a97aec..241b83dadc9 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_spi.h @@ -30,9 +30,9 @@ #include #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h index 20bb8da6654..a531723ba39 100644 --- a/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h +++ b/arch/arm/src/stm32u5/hardware/stm32u5xx_syscfg.h @@ -31,9 +31,9 @@ #include "chip.h" #if defined(CONFIG_STM32U5_STM32U535XX) || defined(CONFIG_STM32U5_STM32U545XX) || \ - defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \ + defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32_STM32U585XX) || \ defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \ - defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) + defined(CONFIG_STM32_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX) /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32u5/stm32_allocateheap.c b/arch/arm/src/stm32u5/stm32_allocateheap.c index ee0220c16d8..3e971fc2bc0 100644 --- a/arch/arm/src/stm32u5/stm32_allocateheap.c +++ b/arch/arm/src/stm32u5/stm32_allocateheap.c @@ -60,7 +60,7 @@ * FSMC. In order to use FSMC SRAM, the following additional things need to * be present in the NuttX configuration file: * - * CONFIG_STM32U5_FSMC=y : Enables the FSMC + * CONFIG_STM32_FSMC=y : Enables the FSMC * CONFIG_STM32U5_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC @@ -71,7 +71,7 @@ * include the additional regions. */ -#ifndef CONFIG_STM32U5_FSMC +#ifndef CONFIG_STM32_FSMC # undef CONFIG_STM32U5_FSMC_SRAM #endif @@ -121,16 +121,16 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32U5_SRAM2_HEAP) + \ - defined(CONFIG_STM32U5_SRAM3_HEAP) + \ - defined(CONFIG_STM32U5_SRAM5_HEAP) + \ +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + \ + defined(CONFIG_STM32_SRAM3_HEAP) + \ + defined(CONFIG_STM32_SRAM5_HEAP) + \ defined(CONFIG_STM32U5_FSMC_SRAM_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -319,7 +319,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32U5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -339,7 +339,7 @@ void arm_addregion(void) #endif /* SRAM2 */ -#ifdef CONFIG_STM32U5_SRAM3_HEAP +#ifdef CONFIG_STM32_SRAM3_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -359,7 +359,7 @@ void arm_addregion(void) #endif /* SRAM3 */ -#ifdef CONFIG_STM32U5_SRAM5_HEAP +#ifdef CONFIG_STM32_SRAM5_HEAP # if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32u5/stm32_dbgmcu.h b/arch/arm/src/stm32u5/stm32_dbgmcu.h index 0db98b7196c..7997e386cbc 100644 --- a/arch/arm/src/stm32u5/stm32_dbgmcu.h +++ b/arch/arm/src/stm32u5/stm32_dbgmcu.h @@ -31,7 +31,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_dbgmcu.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_exti.h b/arch/arm/src/stm32u5/stm32_exti.h index dd31b1946ef..6693179b0b5 100644 --- a/arch/arm/src/stm32u5/stm32_exti.h +++ b/arch/arm/src/stm32u5/stm32_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_flash.c b/arch/arm/src/stm32u5/stm32_flash.c index 586b3154561..526ba889c05 100644 --- a/arch/arm/src/stm32u5/stm32_flash.c +++ b/arch/arm/src/stm32u5/stm32_flash.c @@ -50,13 +50,13 @@ #include "stm32_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32U5_STM32U585XX) -#elif !defined(CONFIG_STM32U5_STM32U5A5XX) +#if !defined(CONFIG_STM32_STM32U585XX) +#elif !defined(CONFIG_STM32_STM32U5A5XX) #else # error "Unrecognized STM32 chip" #endif -#if !defined(CONFIG_STM32U5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32u5/stm32_gpio.h b/arch/arm/src/stm32u5/stm32_gpio.h index ad41d5f41b5..5f37922b482 100644 --- a/arch/arm/src/stm32u5/stm32_gpio.h +++ b/arch/arm/src/stm32u5/stm32_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_gpio.h" #else # error "Unsupported STM32U5 chip" diff --git a/arch/arm/src/stm32u5/stm32_i2c.c b/arch/arm/src/stm32u5/stm32_i2c.c index 5ce09917885..2f99e55a86f 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.c +++ b/arch/arm/src/stm32u5/stm32_i2c.c @@ -172,28 +172,28 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32U5_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32U5_I2C1 - * CONFIG_STM32U5_I2C2 - * CONFIG_STM32U5_I2C3 - * CONFIG_STM32U5_I2C4 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C2 + * CONFIG_STM32_I2C3 + * CONFIG_STM32_I2C4 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32U5_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32U5_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32U5_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32U5_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32U5_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop inmilliseconds) * * Debugging output enabled with: @@ -273,8 +273,8 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32U5_I2C1) || defined(CONFIG_STM32U5_I2C2) || \ - defined(CONFIG_STM32U5_I2C3) || defined(CONFIG_STM32U5_I2C4) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C2) || \ + defined(CONFIG_STM32_I2C3) || defined(CONFIG_STM32_I2C4) /**************************************************************************** * Pre-processor Definitions @@ -286,25 +286,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32U5_I2CTIMEOSEC) && !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 -# define CONFIG_STM32U5_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32U5_I2CTIMEOSEC) -# define CONFIG_STM32U5_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32U5_I2CTIMEOMS) -# define CONFIG_STM32U5_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32U5_I2CTIMEOTICKS -# define CONFIG_STM32U5_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32U5_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32U5_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32U5_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert a I2C pin to a GPIO output */ @@ -472,9 +472,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32U5_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -518,7 +518,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -554,7 +554,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 static const struct stm32_i2c_config_s stm32_i2c2_config = { .base = STM32_I2C2_BASE, @@ -590,7 +590,7 @@ static struct stm32_i2c_priv_s stm32_i2c2_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -626,7 +626,7 @@ static struct stm32_i2c_priv_s stm32_i2c3_priv = }; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 static const struct stm32_i2c_config_s stm32_i2c4_config = { .base = STM32_I2C4_BASE, @@ -759,7 +759,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -776,7 +776,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -834,12 +834,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32U5_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -878,10 +878,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -1023,10 +1023,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32U5_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32U5_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2367,7 +2367,7 @@ static int stm32_i2c_init(struct stm32_i2c_priv_s *priv) /* Enable power and reset the peripheral */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, 0, priv->config->clk_bit); @@ -2452,7 +2452,7 @@ static int stm32_i2c_deinit(struct stm32_i2c_priv_s *priv) /* Disable clocking */ -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 if (priv->config->base == STM32_I2C4_BASE) { modifyreg32(STM32_RCC_APB1ENR2, priv->config->clk_bit, 0); @@ -2957,22 +2957,22 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; #endif -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 case 4: priv = (struct stm32_i2c_priv_s *)&stm32_i2c4_priv; break; @@ -3058,4 +3058,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32U5_I2C1 || CONFIG_STM32U5_I2C2 || CONFIG_STM32U5_I2C3 || CONFIG_STM32U5_I2C4 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 || CONFIG_STM32_I2C4 */ diff --git a/arch/arm/src/stm32u5/stm32_i2c.h b/arch/arm/src/stm32u5/stm32_i2c.h index 5f31f8995ac..f34cf0166eb 100644 --- a/arch/arm/src/stm32u5/stm32_i2c.h +++ b/arch/arm/src/stm32u5/stm32_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32U5_I2C_DYNTIMEO -# if CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32U5_I2C_DYNTIMEO because of CONFIG_STM32U5_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32U5_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32u5/stm32_idle.c b/arch/arm/src/stm32u5/stm32_idle.c index 08a5d61d44c..f84145eca71 100644 --- a/arch/arm/src/stm32u5/stm32_idle.c +++ b/arch/arm/src/stm32u5/stm32_idle.c @@ -92,7 +92,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32U5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32u5/stm32_lse.c b/arch/arm/src/stm32u5/stm32_lse.c index 70438d4e8b0..ebac02e6c54 100644 --- a/arch/arm/src/stm32u5/stm32_lse.c +++ b/arch/arm/src/stm32u5/stm32_lse.c @@ -42,9 +42,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -53,7 +53,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -80,7 +80,7 @@ void stm32_rcc_enablelse(void) bool writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -108,19 +108,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32U5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -148,7 +148,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -177,7 +177,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32U5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.c b/arch/arm/src/stm32u5/stm32_rcc.c index 2b2972cde72..2e7ac13bb44 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.c +++ b/arch/arm/src/stm32u5/stm32_rcc.c @@ -83,7 +83,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * ****************************************************************************/ -#if defined(CONFIG_STM32U5_PWR) && defined(CONFIG_STM32U5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -148,7 +148,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -171,7 +171,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -205,7 +205,7 @@ void stm32_clockconfig(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -220,7 +220,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32u5/stm32_rcc.h b/arch/arm/src/stm32u5/stm32_rcc.h index b788f167de9..ae75e4a2356 100644 --- a/arch/arm/src/stm32u5/stm32_rcc.h +++ b/arch/arm/src/stm32u5/stm32_rcc.h @@ -32,7 +32,7 @@ #include "arm_internal.h" #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32u5xx_rcc.h" #else # error "Unsupported STM32U5 chip" @@ -97,7 +97,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -120,7 +120,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -135,7 +135,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -152,7 +152,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index a5aea799e96..13d539fdb78 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -82,14 +82,14 @@ */ # if defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART3_RXDMA) -# if !defined(CONFIG_STM32U5_DMA1) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32U5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif # if defined(CONFIG_UART4_RXDMA) || defined(CONFIG_UART5_RXDMA) -# if !defined(CONFIG_STM32U5_DMA2) && !defined(CONFIG_STM32U5_DMAMUX) -# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32U5_DMA2 +# if !defined(CONFIG_STM32_DMA2) && !defined(CONFIG_STM32_DMAMUX) +# error STM32U5 UART4/5 receive DMA requires CONFIG_STM32_DMA2 # endif # endif @@ -116,7 +116,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32U5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # define DMAMAP_USART3_RX DMACHAN_USART3_RX # define DMAMAP_UART4_RX DMACHAN_UART4_RX @@ -149,11 +149,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32U5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -185,8 +185,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32U5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32U5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* Keep track if a Break was set @@ -200,7 +200,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -395,7 +395,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -403,7 +403,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -411,7 +411,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -419,7 +419,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static char g_usart3rxbuffer[CONFIG_USART3_RXBUFSIZE]; static char g_usart3txbuffer[CONFIG_USART3_TXBUFSIZE]; # ifdef CONFIG_USART3_RXDMA @@ -427,7 +427,7 @@ static char g_usart3rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; # ifdef CONFIG_UART4_RXDMA @@ -435,7 +435,7 @@ static char g_uart4rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; # ifdef CONFIG_UART5_RXDMA @@ -445,7 +445,7 @@ static char g_uart5rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -505,7 +505,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -567,7 +567,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -629,7 +629,7 @@ static struct stm32_serial_s g_usart2priv = /* This describes the state of the STM32 USART3 port. */ -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER static struct stm32_serial_s g_usart3priv = { .dev = @@ -691,7 +691,7 @@ static struct stm32_serial_s g_usart3priv = /* This describes the state of the STM32 UART4 port. */ -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER static struct stm32_serial_s g_uart4priv = { .dev = @@ -753,7 +753,7 @@ static struct stm32_serial_s g_uart4priv = /* This describes the state of the STM32 UART5 port. */ -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER static struct stm32_serial_s g_uart5priv = { .dev = @@ -818,22 +818,22 @@ static struct stm32_serial_s g_uart5priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] = { -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER [3] = &g_usart3priv, #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER [4] = &g_uart4priv, #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER [5] = &g_uart5priv, #endif }; @@ -1125,7 +1125,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1329,37 +1329,37 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifdef CONFIG_STM32_USART3_SERIALDRIVER case STM32_USART3_BASE: rcc_en = RCC_APB1ENR1_USART3EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifdef CONFIG_STM32_UART4_SERIALDRIVER case STM32_UART4_BASE: rcc_en = RCC_APB1ENR1_UART4EN; regaddr = STM32_RCC_APB1ENR1; break; #endif -#ifdef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifdef CONFIG_STM32_UART5_SERIALDRIVER case STM32_UART5_BASE: rcc_en = RCC_APB1ENR1_UART5EN; regaddr = STM32_RCC_APB1ENR1; @@ -1428,7 +1428,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32U5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1779,8 +1779,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32U5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32U5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1923,7 +1923,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -2001,7 +2001,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -2052,7 +2052,7 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32U5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -2189,8 +2189,8 @@ static int stm32serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32U5_USART_BREAKS -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2418,7 +2418,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32U5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2770,7 +2770,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32U5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -3111,7 +3111,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -3140,7 +3140,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32U5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32u5/stm32_spi.c b/arch/arm/src/stm32u5/stm32_spi.c index bf4ded9c901..82ceb35c60d 100644 --- a/arch/arm/src/stm32u5/stm32_spi.c +++ b/arch/arm/src/stm32u5/stm32_spi.c @@ -74,8 +74,8 @@ #include "stm32_gpio.h" #include "stm32_spi.h" -#if defined(CONFIG_STM32U5_SPI1) || defined(CONFIG_STM32U5_SPI2) || \ - defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) /**************************************************************************** * Pre-processor Definitions @@ -85,19 +85,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32U5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32U5_SPI_INTERRUPTS) && defined(CONFIG_STM32U5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -135,21 +135,21 @@ # define SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI2_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI2_DMA_BUFFER > 0 -# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2_DMA_BUFFER > 0 +# define SPI2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2_DMA_BUFFER) # define SPI2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32U5_SPI3_DMA_BUFFER) && \ - CONFIG_STM32U5_SPI3_DMA_BUFFER > 0 -# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32U5_SPI3_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI3_DMA_BUFFER) && \ + CONFIG_STM32_SPI3_DMA_BUFFER > 0 +# define SPI3_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI3_DMA_BUFFER) # define SPI3_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,15 +160,15 @@ * - support for all kernel clock configuration */ -#if defined(CONFIG_STM32U5_SPI1) +#if defined(CONFIG_STM32_SPI1) # define SPI1_KERNEL_CLOCK_FREQ STM32_PCLK2_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI2) +#if defined(CONFIG_STM32_SPI2) # define SPI2_KERNEL_CLOCK_FREQ STM32_PCLK1_FREQUENCY #endif -#if defined(CONFIG_STM32U5_SPI3) +#if defined(CONFIG_STM32_SPI3) # define SPI3_KERNEL_CLOCK_FREQ STM32_PCLK3_FREQUENCY #endif @@ -190,7 +190,7 @@ struct stm32_spidev_s uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ uint8_t spiirq; /* SPI IRQ number */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -240,7 +240,7 @@ static inline void spi_dumpregs(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -306,7 +306,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -355,7 +355,7 @@ static struct stm32_spidev_s g_spi1dev = .spibase = STM32_SPI1_BASE, .spiclock = SPI1_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI1, -#ifdef CONFIG_STM32U5_SPI1_DMA +#ifdef CONFIG_STM32_SPI1_DMA .rxch = DMAMAP_SPI1_RX, .txch = DMAMAP_SPI1_TX, # if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -370,15 +370,15 @@ static struct stm32_spidev_s g_spi1dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI1_COMMTYPE - .config = CONFIG_STM32U5_SPI1_COMMTYPE, +#ifdef CONFIG_STM32_SPI1_COMMTYPE + .config = CONFIG_STM32_SPI1_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI1 */ +#endif /* CONFIG_STM32_SPI1 */ -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -427,7 +427,7 @@ static struct stm32_spidev_s g_spi2dev = .spibase = STM32_SPI2_BASE, .spiclock = SPI2_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI2, -#ifdef CONFIG_STM32U5_SPI2_DMA +#ifdef CONFIG_STM32_SPI2_DMA .rxch = DMAMAP_SPI2_RX, .txch = DMAMAP_SPI2_TX, # if defined(SPI2_DMABUFSIZE_ADJUSTED) @@ -442,15 +442,15 @@ static struct stm32_spidev_s g_spi2dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI2_COMMTYPE - .config = CONFIG_STM32U5_SPI2_COMMTYPE, +#ifdef CONFIG_STM32_SPI2_COMMTYPE + .config = CONFIG_STM32_SPI2_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI2 */ +#endif /* CONFIG_STM32_SPI2 */ -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 static const struct spi_ops_s g_sp3iops = { .lock = spi_lock, @@ -499,7 +499,7 @@ static struct stm32_spidev_s g_spi3dev = .spibase = STM32_SPI3_BASE, .spiclock = SPI3_KERNEL_CLOCK_FREQ, .spiirq = STM32_IRQ_SPI3, -#ifdef CONFIG_STM32U5_SPI3_DMA +#ifdef CONFIG_STM32_SPI3_DMA .rxch = DMAMAP_SPI3_RX, .txch = DMAMAP_SPI3_TX, # if defined(SPI3_DMABUFSIZE_ADJUSTED) @@ -514,13 +514,13 @@ static struct stm32_spidev_s g_spi3dev = #ifdef CONFIG_PM .pm_cb.prepare = spi_pm_prepare, #endif -#ifdef CONFIG_STM32U5_SPI3_COMMTYPE - .config = CONFIG_STM32U5_SPI3_COMMTYPE, +#ifdef CONFIG_STM32_SPI3_COMMTYPE + .config = CONFIG_STM32_SPI3_COMMTYPE, #else .config = FULL_DUPLEX, #endif }; -#endif /* CONFIG_STM32U5_SPI3 */ +#endif /* CONFIG_STM32_SPI3 */ /**************************************************************************** * Private Functions @@ -840,7 +840,7 @@ static int spi_interrupt(int irq, void *context, void *arg) spi_modifyreg(priv, STM32_SPI_IER_OFFSET, SPI_IER_EOTIE, 0); /* Set result and release wait semaphore */ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA priv->txresult = 0x80; nxsem_post(&priv->txsem); #endif @@ -857,7 +857,7 @@ static int spi_interrupt(int irq, void *context, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -897,7 +897,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -946,7 +946,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -961,7 +961,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -981,7 +981,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1043,7 +1043,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords, stm32_dmacfg_t *dmacfg) @@ -1103,7 +1103,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxstart(struct stm32_spidev_s *priv) { /* Can't receive in tx only mode */ @@ -1127,7 +1127,7 @@ static void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxstart(struct stm32_spidev_s *priv) { /* Can't transmit in rx only mode */ @@ -1662,9 +1662,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32U5_SPI_DMA) || defined(CONFIG_STM32U5_DMACAPABLE) || \ - defined(CONFIG_STM32U5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32U5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1753,8 +1753,8 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } -#endif /* !CONFIG_STM32U5_SPI_DMA || CONFIG_STM32U5_DMACAPABLE || - * CONFIG_STM32U5_SPI_DMATHRESHOLD +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || + * CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** @@ -1778,7 +1778,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1796,12 +1796,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32U5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32U5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1865,7 +1865,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, spi_dmatxsetup(priv, txbuffer, &txdummy, nwords, &txdmacfg); spi_dmarxsetup(priv, rxbuffer, (uint16_t *)rxdummy, nwords, &rxdmacfg); -#ifdef CONFIG_STM32U5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE /* Test for DMA capability of only callers buffers, internal buffers are * guaranteed capable. @@ -1995,7 +1995,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, priv->trigarmed = false; #endif } -#endif /* CONFIG_STM32U5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -2016,7 +2016,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -2250,7 +2250,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPOLY_OFFSET, 7); -#ifdef CONFIG_STM32U5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() will * block and wait until the channel becomes available. WARNING: If you @@ -2332,7 +2332,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) struct stm32_spidev_s *priv = NULL; irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -2357,7 +2357,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -2382,7 +2382,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 if (bus == 3) { /* Select SPI3 */ @@ -2415,5 +2415,5 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32U5_SPI1 || CONFIG_STM32U5_SPI2 || CONFIG_STM32U5_SPI3 +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 || CONFIG_STM32_SPI3 */ diff --git a/arch/arm/src/stm32u5/stm32_spi.h b/arch/arm/src/stm32u5/stm32_spi.h index 9734b18924f..485b6a5a9a1 100644 --- a/arch/arm/src/stm32u5/stm32_spi.h +++ b/arch/arm/src/stm32u5/stm32_spi.h @@ -114,21 +114,21 @@ struct spi_slave_ctrlr_s *stm32_spi_slave_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); @@ -156,17 +156,17 @@ int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32u5/stm32_start.c b/arch/arm/src/stm32u5/stm32_start.c index ee12901462f..87609e5c881 100644 --- a/arch/arm/src/stm32u5/stm32_start.c +++ b/arch/arm/src/stm32u5/stm32_start.c @@ -131,7 +131,7 @@ void __start(void) ("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32U5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32u5/stm32_tim.c b/arch/arm/src/stm32u5/stm32_tim.c index 7dbdba50ce4..bc4c4e1466b 100644 --- a/arch/arm/src/stm32u5/stm32_tim.c +++ b/arch/arm/src/stm32u5/stm32_tim.c @@ -73,118 +73,118 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32U5_TIM1_PWM) || defined (CONFIG_STM32U5_TIM1_ADC) || \ - defined(CONFIG_STM32U5_TIM1_DAC) || defined(CONFIG_STM32U5_TIM1_QE) -# undef CONFIG_STM32U5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32U5_TIM2_PWM) || defined (CONFIG_STM32U5_TIM2_ADC) || \ - defined(CONFIG_STM32U5_TIM2_DAC) || defined(CONFIG_STM32U5_TIM2_QE) -# undef CONFIG_STM32U5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32U5_TIM3_PWM) || defined (CONFIG_STM32U5_TIM3_ADC) || \ - defined(CONFIG_STM32U5_TIM3_DAC) || defined(CONFIG_STM32U5_TIM3_QE) -# undef CONFIG_STM32U5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32U5_TIM4_PWM) || defined (CONFIG_STM32U5_TIM4_ADC) || \ - defined(CONFIG_STM32U5_TIM4_DAC) || defined(CONFIG_STM32U5_TIM4_QE) -# undef CONFIG_STM32U5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32U5_TIM5_PWM) || defined (CONFIG_STM32U5_TIM5_ADC) || \ - defined(CONFIG_STM32U5_TIM5_DAC) || defined(CONFIG_STM32U5_TIM5_QE) -# undef CONFIG_STM32U5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32U5_TIM6_ADC) || \ - defined(CONFIG_STM32U5_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) -# undef CONFIG_STM32U5_TIM6 +#if defined(CONFIG_STM32U5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32U5_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32U5_TIM7_PWM) || defined (CONFIG_STM32U5_TIM7_ADC) || \ - defined(CONFIG_STM32U5_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) -# undef CONFIG_STM32U5_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32U5_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32U5_TIM8_PWM) || defined (CONFIG_STM32U5_TIM8_ADC) || \ - defined(CONFIG_STM32U5_TIM8_DAC) || defined(CONFIG_STM32U5_TIM8_QE) -# undef CONFIG_STM32U5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32U5_TIM15_PWM) || defined (CONFIG_STM32U5_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32U5_TIM15_DAC) || defined(CONFIG_STM32U5_TIM15_QE) -# undef CONFIG_STM32U5_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32U5_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32U5_TIM16_ADC) || \ defined(CONFIG_STM32U5_TIM16_DAC) || defined(CONFIG_STM32U5_TIM16_QE) -# undef CONFIG_STM32U5_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32U5_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32U5_TIM17_ADC) || \ defined(CONFIG_STM32U5_TIM17_DAC) || defined(CONFIG_STM32U5_TIM17_QE) -# undef CONFIG_STM32U5_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32U5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -195,12 +195,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -301,7 +301,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -309,7 +309,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -318,7 +318,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -327,7 +327,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -336,7 +336,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -345,7 +345,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -354,7 +354,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -363,7 +363,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -372,7 +372,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -381,7 +381,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -390,7 +390,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -654,66 +654,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -769,64 +769,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -875,13 +875,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32U5_TIM2) || defined(CONFIG_STM32U5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: #endif return counter; @@ -987,7 +987,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1020,7 +1020,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1053,7 +1053,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1086,7 +1086,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1118,7 +1118,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1151,7 +1151,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1184,7 +1184,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1217,7 +1217,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1250,7 +1250,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1366,65 +1366,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1509,76 +1509,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1616,66 +1616,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1692,4 +1692,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32U5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c index 7752a4fda1b..a564a8af525 100644 --- a/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c +++ b/arch/arm/src/stm32u5/stm32_tim_lowerhalf.c @@ -41,12 +41,12 @@ #include "stm32_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32U5_TIM1) || defined(CONFIG_STM32U5_TIM2) || \ - defined(CONFIG_STM32U5_TIM3) || defined(CONFIG_STM32U5_TIM4) || \ - defined(CONFIG_STM32U5_TIM5) || defined(CONFIG_STM32U5_TIM6) || \ - defined(CONFIG_STM32U5_TIM7) || defined(CONFIG_STM32U5_TIM8) || \ - defined(CONFIG_STM32U5_TIM15) || defined(CONFIG_STM32U5_TIM16) || \ - defined(CONFIG_STM32U5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32u5/stm32_uart.h b/arch/arm/src/stm32u5/stm32_uart.h index 198ef1e36a0..032d3609033 100644 --- a/arch/arm/src/stm32u5/stm32_uart.h +++ b/arch/arm/src/stm32u5/stm32_uart.h @@ -32,7 +32,7 @@ #include "chip.h" -#if defined(CONFIG_STM32U5_STM32U585XX) || defined(CONFIG_STM32U5_STM32U5A5XX) +#if defined(CONFIG_STM32_STM32U585XX) || defined(CONFIG_STM32_STM32U5A5XX) # include "hardware/stm32_uart.h" #else # error "Unsupported STM32U5 chip" @@ -46,63 +46,63 @@ * device. */ -#if !defined(CONFIG_STM32U5_HAVE_UART5) -# undef CONFIG_STM32U5_UART5 +#if !defined(CONFIG_STM32_HAVE_UART5) +# undef CONFIG_STM32_UART5 #endif -#if !defined(CONFIG_STM32U5_HAVE_UART4) -# undef CONFIG_STM32U5_UART4 +#if !defined(CONFIG_STM32_HAVE_UART4) +# undef CONFIG_STM32_UART4 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART3) -# undef CONFIG_STM32U5_USART3 +#if !defined(CONFIG_STM32_HAVE_USART3) +# undef CONFIG_STM32_USART3 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART2) -# undef CONFIG_STM32U5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32U5_HAVE_USART1) -# undef CONFIG_STM32U5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32U5_HAVE_LPUART1) -# undef CONFIG_STM32U5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32U5_LPUART1) -# undef CONFIG_STM32U5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32U5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART1) -# undef CONFIG_STM32U5_USART1_SERIALDRIVER -# undef CONFIG_STM32U5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART2) -# undef CONFIG_STM32U5_USART2_SERIALDRIVER -# undef CONFIG_STM32U5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_USART3) -# undef CONFIG_STM32U5_USART3_SERIALDRIVER -# undef CONFIG_STM32U5_USART3_1WIREDRIVER +#if !defined(CONFIG_STM32_USART3) +# undef CONFIG_STM32_USART3_SERIALDRIVER +# undef CONFIG_STM32_USART3_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART4) -# undef CONFIG_STM32U5_UART4_SERIALDRIVER -# undef CONFIG_STM32U5_UART4_1WIREDRIVER +#if !defined(CONFIG_STM32_UART4) +# undef CONFIG_STM32_UART4_SERIALDRIVER +# undef CONFIG_STM32_UART4_1WIREDRIVER #endif -#if !defined(CONFIG_STM32U5_UART5) -# undef CONFIG_STM32U5_UART5_SERIALDRIVER -# undef CONFIG_STM32U5_UART5_1WIREDRIVER +#if !defined(CONFIG_STM32_UART5) +# undef CONFIG_STM32_UART5_SERIALDRIVER +# undef CONFIG_STM32_UART5_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32U5_LPUART1) || defined(CONFIG_STM32U5_USART1) || \ - defined(CONFIG_STM32U5_USART2) || defined(CONFIG_STM32U5_USART3) || \ - defined(CONFIG_STM32U5_UART4) || defined(CONFIG_STM32U5_UART5) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \ + defined(CONFIG_STM32_UART4) || defined(CONFIG_STM32_UART5) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -110,7 +110,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -118,28 +118,28 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 3 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_USART3_SERIALDRIVER) +#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 4 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART4_SERIALDRIVER) +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 5 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32U5_UART5_SERIALDRIVER) +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -170,27 +170,27 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32U5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32U5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif -#ifndef CONFIG_STM32U5_USART3_SERIALDRIVER +#ifndef CONFIG_STM32_USART3_SERIALDRIVER # undef CONFIG_USART3_RXDMA #endif -#ifndef CONFIG_STM32U5_UART4_SERIALDRIVER +#ifndef CONFIG_STM32_UART4_SERIALDRIVER # undef CONFIG_UART4_RXDMA #endif -#ifndef CONFIG_STM32U5_UART5_SERIALDRIVER +#ifndef CONFIG_STM32_UART5_SERIALDRIVER # undef CONFIG_UART5_RXDMA #endif @@ -223,17 +223,17 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32U5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) +#elif defined(CONFIG_STM32_USART3_SERIALDRIVER) && !defined(CONFIG_USART3_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) +#elif defined(CONFIG_STM32_UART4_SERIALDRIVER) && !defined(CONFIG_UART4_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32U5_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) +#elif defined(CONFIG_STM32_UART5_SERIALDRIVER) && !defined(CONFIG_UART5_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/arch/arm/src/stm32u5/stm32u5xx_rcc.c b/arch/arm/src/stm32u5/stm32u5xx_rcc.c index 3fb5798bd7f..3a044f6a8ee 100644 --- a/arch/arm/src/stm32u5/stm32u5xx_rcc.c +++ b/arch/arm/src/stm32u5/stm32u5xx_rcc.c @@ -60,7 +60,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32U5_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -96,51 +96,51 @@ static inline void rcc_enableahb1(void) regval |= RCC_AHB1ENR_GPDMA1EN; #endif -#ifdef CONFIG_STM32U5_CORDIC +#ifdef CONFIG_STM32_CORDIC regval |= RCC_AHB1ENR_CORDIC; #endif -#ifdef CONFIG_STM32U5_FMAC +#ifdef CONFIG_STM32_FMAC regval |= RCC_AHB1ENR_FMACEN; #endif -#ifdef CONFIG_STM32U5_MDF1 +#ifdef CONFIG_STM32_MDF1 regval |= RCC_AHB1ENR_MDF1EN; #endif -#ifdef CONFIG_STM32U5_FLASH +#ifdef CONFIG_STM32_FLASH regval |= RCC_AHB1ENR_FLASHEN; #endif -#ifdef CONFIG_STM32U5_CRC +#ifdef CONFIG_STM32_CRC regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32U5_TSC +#ifdef CONFIG_STM32_TSC regval |= RCC_AHB1ENR_TSCEN; #endif -#ifdef CONFIG_STM32U5_RAMCFG +#ifdef CONFIG_STM32_RAMCFG regval |= RCC_AHB1ENR_RAMCFGEN; #endif -#ifdef CONFIG_STM32U5_DMA2D +#ifdef CONFIG_STM32_DMA2D regval |= RCC_AHB1ENR_DMA2DEN; #endif -#ifdef CONFIG_STM32U5_GTZC1 +#ifdef CONFIG_STM32_GTZC1 regval |= RCC_AHB1ENR_GTZC1EN; #endif -#ifdef CONFIG_STM32U5_BKPSRAM +#ifdef CONFIG_STM32_BKPSRAM regval |= RCC_AHB1ENR_BKPSRAMEN; #endif -#ifdef CONFIG_STM32U5_DCACHE1 +#ifdef CONFIG_STM32_DCACHE1 regval |= RCC_AHB1ENR_DCACHE1EN; #endif -#ifdef CONFIG_STM32U5_SRAM1 +#ifdef CONFIG_STM32_SRAM1 regval |= RCC_AHB1ENR_SRAM1EN; #endif @@ -194,51 +194,51 @@ static inline void rcc_enableahb2(void) ); #endif -#if defined(CONFIG_STM32U5_ADC1) +#if defined(CONFIG_STM32_ADC1) regval |= RCC_AHB2ENR1_ADC1EN; #endif -#if defined(CONFIG_STM32U5_DCMI_PSSI) +#if defined(CONFIG_STM32_DCMI_PSSI) regval |= RCC_AHB2ENR1_DCMI_PSSIEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGEN; #endif -#ifdef CONFIG_STM32U5_OTGHS +#ifdef CONFIG_STM32_OTGHS regval |= RCC_AHB2ENR1_OTGPHYEN; #endif -#ifdef CONFIG_STM32U5_AES +#ifdef CONFIG_STM32_AES regval |= RCC_AHB2ENR1_AESEN; #endif -#ifdef CONFIG_STM32U5_HASH +#ifdef CONFIG_STM32_HASH regval |= RCC_AHB2ENR1_HASHEN #endif -#ifdef CONFIG_STM32U5_RNG +#ifdef CONFIG_STM32_RNG regval |= RCC_AHB2ENR1_RNGEN; #endif -#ifdef CONFIG_STM32U5_PKA +#ifdef CONFIG_STM32_PKA regval |= RCC_AHB2ENR_PKAEN; #endif -#ifdef CONFIG_STM32U5_SAES +#ifdef CONFIG_STM32_SAES regval |= RCC_AHB2ENR1_SAES; #endif -#ifdef CONFIG_STM32U5_OCTOSPIM +#ifdef CONFIG_STM32_OCTOSPIM regval |= RCC_AHB2ENR1_OCTOSPIM; #endif -#ifdef CONFIG_STM32U5_OTFDEC1 +#ifdef CONFIG_STM32_OTFDEC1 regval |= RCC_AHB2ENR1_OTFDEC1; #endif -#ifdef CONFIG_STM32U5_OTFDEC2 +#ifdef CONFIG_STM32_OTFDEC2 regval |= RCC_AHB2ENR1_OTFDEC2; #endif @@ -250,11 +250,11 @@ static inline void rcc_enableahb2(void) regval |= RCC_AHB2ENR1_SDMMC2EN; #endif -#ifdef CONFIG_STM32U5_SRAM2 +#ifdef CONFIG_STM32_SRAM2 regval |= RCC_AHB2ENR1_SRAM2EN; #endif -#ifdef CONFIG_STM32U5_SRAM3 +#ifdef CONFIG_STM32_SRAM3 regval |= RCC_AHB2ENR1_SRAM3EN; #endif @@ -262,19 +262,19 @@ static inline void rcc_enableahb2(void) regval = getreg32(STM32_RCC_AHB2ENR2); -#ifdef CONFIG_STM32U5_FSMC +#ifdef CONFIG_STM32_FSMC regval |= RCC_AHB2ENR2_FSMCEN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI1 +#ifdef CONFIG_STM32_OCTOSPI1 regval |= RCC_AHB2ENR2_OCTOSPI1EN; #endif -#ifdef CONFIG_STM32U5_OCTOSPI2 +#ifdef CONFIG_STM32_OCTOSPI2 regval |= RCC_AHB2ENR2_OCTOSPI2EN; #endif -#ifdef CONFIG_STM32U5_SRAM5 +#ifdef CONFIG_STM32_SRAM5 regval |= RCC_AHB2ENR2_SRAM5EN; #endif @@ -299,31 +299,31 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32U5_LPGPIO1 +#ifdef CONFIG_STM32_LPGPIO1 regval |= RCC_AHB3ENR_LPGPIO1EN; #endif -#ifdef CONFIG_STM32U5_PWR +#ifdef CONFIG_STM32_PWR regval |= RCC_AHB3ENR_PWREN; #endif -#ifdef CONFIG_STM32U5_ADC4 +#ifdef CONFIG_STM32_ADC4 regval |= RCC_AHB3ENR_ADC4EN; #endif -#ifdef CONFIG_STM32U5_DAC1 +#ifdef CONFIG_STM32_DAC1 regval |= RCC_AHB3ENR_DAC1EN; #endif -#ifdef CONFIG_STM32U5_LPDMA1 +#ifdef CONFIG_STM32_LPDMA1 regval |= RCC_AHB3ENR_LPDMA1EN; #endif -#ifdef CONFIG_STM32U5_ADF1 +#ifdef CONFIG_STM32_ADF1 regval |= RCC_AHB3ENR_ADF1EN; #endif -#ifdef CONFIG_STM32U5_GTZC2 +#ifdef CONFIG_STM32_GTZC2 regval |= RCC_AHB3ENR_GTZC2EN; #endif @@ -352,63 +352,63 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32U5_TIM2 +#ifdef CONFIG_STM32_TIM2 regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32U5_TIM3 +#ifdef CONFIG_STM32_TIM3 regval |= RCC_APB1ENR1_TIM3EN; #endif -#ifdef CONFIG_STM32U5_TIM4 +#ifdef CONFIG_STM32_TIM4 regval |= RCC_APB1ENR1_TIM4EN; #endif -#ifdef CONFIG_STM32U5_TIM5 +#ifdef CONFIG_STM32_TIM5 regval |= RCC_APB1ENR1_TIM5EN; #endif -#ifdef CONFIG_STM32U5_TIM6 +#ifdef CONFIG_STM32_TIM6 regval |= RCC_APB1ENR1_TIM6EN; #endif -#ifdef CONFIG_STM32U5_TIM7 +#ifdef CONFIG_STM32_TIM7 regval |= RCC_APB1ENR1_TIM7EN; #endif -#ifdef CONFIG_STM32U5_WWDG +#ifdef CONFIG_STM32_WWDG regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32U5_USART2 +#ifdef CONFIG_STM32_USART2 regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32U5_USART3 +#ifdef CONFIG_STM32_USART3 regval |= RCC_APB1ENR1_USART3EN; #endif -#ifdef CONFIG_STM32U5_UART4 +#ifdef CONFIG_STM32_UART4 regval |= RCC_APB1ENR1_UART4EN; #endif -#ifdef CONFIG_STM32U5_UART5 +#ifdef CONFIG_STM32_UART5 regval |= RCC_APB1ENR1_UART5EN; #endif -#ifdef CONFIG_STM32U5_I2C1 +#ifdef CONFIG_STM32_I2C1 regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32U5_I2C2 +#ifdef CONFIG_STM32_I2C2 regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32U5_CRS +#ifdef CONFIG_STM32_CRS regval |= RCC_APB1ENR1_CRSEN; #endif @@ -418,19 +418,19 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32U5_I2C4 +#ifdef CONFIG_STM32_I2C4 regval |= RCC_APB1ENR2_I2C4EN; #endif -#ifdef CONFIG_STM32U5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32U5_FDCAN1 +#ifdef CONFIG_STM32_FDCAN1 regval |= RCC_APB1ENR2_FDCAN1EN; #endif -#ifdef CONFIG_STM32U5_UCPD1 +#ifdef CONFIG_STM32_UCPD1 regval |= RCC_APB1ENR2_UCPD1EN; #endif @@ -455,39 +455,39 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32U5_TIM1 +#ifdef CONFIG_STM32_TIM1 regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32U5_TIM8 +#ifdef CONFIG_STM32_TIM8 regval |= RCC_APB2ENR_TIM8EN; #endif -#ifdef CONFIG_STM32U5_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32U5_TIM15 +#ifdef CONFIG_STM32_TIM15 regval |= RCC_APB2ENR_TIM15EN; #endif -#ifdef CONFIG_STM32U5_TIM16 +#ifdef CONFIG_STM32_TIM16 regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32U5_TIM17 +#ifdef CONFIG_STM32_TIM17 regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32U5_SAI1 +#ifdef CONFIG_STM32_SAI1 regval |= RCC_APB2ENR_SAI1EN; #endif -#ifdef CONFIG_STM32U5_SAI2 +#ifdef CONFIG_STM32_SAI2 regval |= RCC_APB2ENR_SAI2EN; #endif @@ -512,15 +512,15 @@ static inline void rcc_enableapb3(void) regval = getreg32(STM32_RCC_APB3ENR); -#ifdef CONFIG_STM32U5_SYSCFG +#ifdef CONFIG_STM32_SYSCFG regval |= RCC_APB3ENR_SYSCFGEN; #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 regval |= RCC_APB3ENR_SPI3EN; #endif -#ifdef CONFIG_STM32U5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 regval |= RCC_APB3ENR_LPUART1EN; #endif @@ -528,31 +528,31 @@ static inline void rcc_enableapb3(void) regval |= RCC_APB3ENR_I2C3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 regval |= RCC_APB3ENR_LPTIM1EN; #endif -#ifdef CONFIG_STM32U5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 regval |= RCC_APB3ENR_LPTIM3EN; #endif -#ifdef CONFIG_STM32U5_LPTIM4 +#ifdef CONFIG_STM32_LPTIM4 regval |= RCC_APB3ENR_LPTIM4EN; #endif -#ifdef CONFIG_STM32U5_OPAMP +#ifdef CONFIG_STM32_OPAMP regval |= RCC_APB3ENR_OPAMPEN; #endif -#ifdef CONFIG_STM32U5_COMP +#ifdef CONFIG_STM32_COMP regval |= RCC_APB3ENR_COMPEN; #endif -#ifdef CONFIG_STM32U5_VREF +#ifdef CONFIG_STM32_VREF regval |= RCC_APB3ENR_VREFEN; #endif -#ifdef CONFIG_STM32U5_RTCAPB +#ifdef CONFIG_STM32_RTCAPB regval |= RCC_APB3ENR_RTCAPBEN; #endif @@ -604,7 +604,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -742,9 +742,9 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR3_PPRE3; putreg32(regval, STM32_RCC_CFGR3); -#ifdef CONFIG_STM32U5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK -# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK +# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32_RTC_HSECLOCK #endif @@ -799,7 +799,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32U5_IWDG) || defined(CONFIG_STM32U5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig index 74b6940237b..eabf176d3fd 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig +++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-u585i-iot02a" CONFIG_ARCH_BOARD_B_U585I_IOT02A=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U585AI=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -45,10 +46,10 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SPI1=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SPITOOL=y CONFIG_SYSTEM_STACKMONITOR=y diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt index a845f39aefe..150aef2e647 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile index 0a32978916a..915275f7e6f 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c index b6aa7c6a371..378c5ec51c7 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c index 4bea93db071..13bd3f79895 100644 --- a/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c +++ b/boards/arm/stm32u5/b-u585i-iot02a/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "b-u585i-iot02a.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig index a489a5a0284..62d5aa14537 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/configs/nsh/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-u5a5zj-q" CONFIG_ARCH_BOARD_NUCLEO_U5A5ZJ_Q=y CONFIG_ARCH_CHIP="stm32u5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32U5=y CONFIG_ARCH_CHIP_STM32U5A5ZJT=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -47,14 +48,14 @@ CONFIG_READLINE_TABCOMPLETION=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_STACK_COLORATION=y -CONFIG_STM32U5_PWR=y -CONFIG_STM32U5_SRAM2=y -CONFIG_STM32U5_SRAM2_HEAP=y -CONFIG_STM32U5_SRAM3=y -CONFIG_STM32U5_SRAM3_HEAP=y -CONFIG_STM32U5_SRAM5=y -CONFIG_STM32U5_SRAM5_HEAP=y -CONFIG_STM32U5_USART1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SRAM2=y +CONFIG_STM32_SRAM2_HEAP=y +CONFIG_STM32_SRAM3=y +CONFIG_STM32_SRAM3_HEAP=y +CONFIG_STM32_SRAM5=y +CONFIG_STM32_SRAM5_HEAP=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=2048 CONFIG_SYSTEM_TEE=y diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt index fa6b58b12dc..0ab477f5946 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt @@ -22,7 +22,7 @@ set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) -if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +if(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) list(APPEND SRCS stm32_clockconfig.c) endif() diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile index 1fa94c46e61..93d9723add3 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/Makefile @@ -25,7 +25,7 @@ ASRCS = CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c -ifeq ($(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG),y) +ifeq ($(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG),y) CSRCS += stm32_clockconfig.c endif diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c index 24afdb388ba..976a515f7b4 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_clockconfig.c @@ -38,12 +38,12 @@ * NuttX in the Non-Secure domain together with TrustedFirmware-M (TFM). * In this setup the clock configuration is done by TFM, not by NuttX. * Thus, the board's configuration sets - * CONFIG_ARCH_BOARD_STM32L5_CUSTOM_CLOCKCONFIG to avoid the standard clock + * CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG to avoid the standard clock * config logic to run and instead do just nothing in this function. * ****************************************************************************/ -#if defined(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) void stm32_board_clockconfig(void) { } diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c index efae2e53942..34e5a5352dd 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/stm32_spi.c @@ -41,7 +41,7 @@ #include "nucleo-u5a5zj-q.h" #include -#ifdef CONFIG_STM32U5_SPI +#ifdef CONFIG_STM32_SPI /**************************************************************************** * Public Functions @@ -64,7 +64,7 @@ void stm32_spidev_initialize(void) * architecture. */ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 stm32_configgpio(GPIO_SPI1_NSS); #endif } @@ -95,7 +95,7 @@ void stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -111,7 +111,7 @@ uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -125,7 +125,7 @@ uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -162,25 +162,25 @@ uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) ****************************************************************************/ #ifdef CONFIG_SPI_CMDDATA -#ifdef CONFIG_STM32U5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif -#ifdef CONFIG_STM32U5_SPI3 +#ifdef CONFIG_STM32_SPI3 int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) { return -ENODEV; } #endif #endif /* CONFIG_SPI_CMDDATA */ -#endif /* CONFIG_STM32U5_SPI */ +#endif /* CONFIG_STM32_SPI */ From 4dadf28cfbcc6c2afe51142334154ddd3eb51f66 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:42 +0200 Subject: [PATCH 092/268] !arch/stm32wb: use common STM32 Kconfig symbols BREAKING CHANGE: STM32WB Kconfig symbols were renamed from CONFIG_STM32WB_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. The custom clock option is a special breaking case that does not follow the family-to-common pattern: CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG was renamed to CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 1 + arch/arm/include/stm32wb/chip.h | 20 +- arch/arm/include/stm32wb/stm32wb_irq.h | 42 +- arch/arm/src/stm32wb/CMakeLists.txt | 18 +- arch/arm/src/stm32wb/Kconfig | 1132 ++--------------- arch/arm/src/stm32wb/Make.defs | 18 +- arch/arm/src/stm32wb/hardware/stm32wb_flash.h | 66 +- arch/arm/src/stm32wb/hardware/stm32wb_gpio.h | 4 +- arch/arm/src/stm32wb/hardware/stm32wb_i2c.h | 2 +- .../arm/src/stm32wb/hardware/stm32wb_pinmap.h | 6 +- arch/arm/src/stm32wb/hardware/stm32wb_spi.h | 2 +- .../src/stm32wb/hardware/stm32wbxx_pinmap.h | 54 +- arch/arm/src/stm32wb/stm32wb_allocateheap.c | 30 +- arch/arm/src/stm32wb/stm32wb_blehci.c | 48 +- arch/arm/src/stm32wb/stm32wb_dma.c | 30 +- arch/arm/src/stm32wb/stm32wb_dma.h | 4 +- arch/arm/src/stm32wb/stm32wb_dumpgpio.c | 4 +- arch/arm/src/stm32wb/stm32wb_flash.c | 2 +- arch/arm/src/stm32wb/stm32wb_freerun.c | 4 +- arch/arm/src/stm32wb/stm32wb_freerun.h | 4 +- arch/arm/src/stm32wb/stm32wb_gpio.h | 8 +- arch/arm/src/stm32wb/stm32wb_i2c.c | 78 +- arch/arm/src/stm32wb/stm32wb_i2c.h | 8 +- arch/arm/src/stm32wb/stm32wb_idle.c | 2 +- arch/arm/src/stm32wb/stm32wb_mbox.c | 30 +- arch/arm/src/stm32wb/stm32wb_oneshot.c | 12 +- arch/arm/src/stm32wb/stm32wb_oneshot.h | 20 +- arch/arm/src/stm32wb/stm32wb_rcc.c | 88 +- arch/arm/src/stm32wb/stm32wb_rcc.h | 7 +- arch/arm/src/stm32wb/stm32wb_rcc_lse.c | 26 +- arch/arm/src/stm32wb/stm32wb_rtc.c | 36 +- arch/arm/src/stm32wb/stm32wb_rtc.h | 20 +- arch/arm/src/stm32wb/stm32wb_serial.c | 58 +- arch/arm/src/stm32wb/stm32wb_spi.c | 68 +- arch/arm/src/stm32wb/stm32wb_spi.h | 8 +- arch/arm/src/stm32wb/stm32wb_start.c | 16 +- arch/arm/src/stm32wb/stm32wb_tickless.c | 18 +- arch/arm/src/stm32wb/stm32wb_tim.c | 112 +- arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c | 20 +- arch/arm/src/stm32wb/stm32wb_timerisr.c | 6 +- arch/arm/src/stm32wb/stm32wb_uart.h | 26 +- .../stm32wb/flipperzero/configs/nsh/defconfig | 11 +- .../arm/stm32wb/flipperzero/src/stm32_boot.c | 4 +- .../arm/stm32wb/flipperzero/src/stm32_spi.c | 2 +- .../nucleo-wb55rg/configs/ble/defconfig | 11 +- .../nucleo-wb55rg/configs/nimble/defconfig | 11 +- .../nucleo-wb55rg/configs/nsh/defconfig | 9 +- .../stm32wb/nucleo-wb55rg/src/stm32_boot.c | 4 +- 48 files changed, 653 insertions(+), 1557 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index febe16549dc..2a74fa07038 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -733,6 +733,7 @@ config ARCH_CHIP_STM32U5 config ARCH_CHIP_STM32WB bool "STMicro STM32 WB" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_FPU select ARCH_HAVE_MPU diff --git a/arch/arm/include/stm32wb/chip.h b/arch/arm/include/stm32wb/chip.h index 61ffe8eb774..6945832aab6 100644 --- a/arch/arm/include/stm32wb/chip.h +++ b/arch/arm/include/stm32wb/chip.h @@ -40,14 +40,14 @@ #define STM32_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */ #define STM32_NGTIMNDMA 0 /* No general timers without DMA */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_NGTIM16 2 /* 16-bit general timers TIM16-17 with DMA */ #else # define STM32_NGTIM16 0 /* No 16-bit general timers */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_NDMA 2 /* DMA1-2 with 7 channels each */ # define STM32_NI2S 1 /* SAI1 (dual channel high quality audio) */ # define STM32_NI2C 2 /* I2C1, I2C3 */ @@ -67,8 +67,8 @@ # define STM32_NSPI 1 /* SPI1 */ #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) \ - || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) \ + || defined(CONFIG_STM32_STM32WB55) # define STM32_NLPUART 1 /* LPUART1 */ #else # define STM32_NLPUART 0 /* No LPUART */ @@ -80,7 +80,7 @@ # define STM32_NCAPSENSE 0 /* No Capacitive sensing */ #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_NLCD 1 /* One LCD controller with up to 8x40 * terminals, depending on subfamily. * 55Cx: 4x13 @@ -138,20 +138,20 @@ * 3) 32 KiB of SRAM2b beginning at address 0x2003:8000 - 0x2004:0000 */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define STM32_SRAM1_SIZE (12*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (4*1024) -#elif defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) +#elif defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) # define STM32_SRAM1_SIZE (32*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) -#elif (defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55)) \ +#elif (defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55)) \ && defined(CONFIG_STM32WB_IO_CONFIG_C) # define STM32_SRAM1_SIZE (64*1024) # define STM32_SRAM2A_SIZE (32*1024) # define STM32_SRAM2B_SIZE (32*1024) -#elif defined(CONFIG_STM32WB_STM32WB55) && \ +#elif defined(CONFIG_STM32_STM32WB55) && \ (defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V)) # define STM32_SRAM1_SIZE (192*1024) # define STM32_SRAM2A_SIZE (32*1024) diff --git a/arch/arm/include/stm32wb/stm32wb_irq.h b/arch/arm/include/stm32wb/stm32wb_irq.h index f61881f6a7c..88eba8470cb 100644 --- a/arch/arm/include/stm32wb/stm32wb_irq.h +++ b/arch/arm/include/stm32wb/stm32wb_irq.h @@ -54,12 +54,12 @@ #define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI[16] Line detection interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_PVM1 (STM32_IRQ_FIRST + 1) /* 1: PVM1 through EXTI[31] Line detection interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_PVM3 (STM32_IRQ_FIRST + 1) /* 1: PVM3 through EXTI[33] Line detection interrupt */ #endif @@ -83,15 +83,15 @@ #define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */ #define STM32_IRQ_ADC1 (STM32_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define STM32_IRQ_USB_HP (STM32_IRQ_FIRST + 19) /* 19: USB High Priority Interrupt */ #define STM32_IRQ_USB_LP (STM32_IRQ_FIRST + 20) /* 20: USB Low Priority Interrupt */ #endif #define STM32_IRQ_C2SEV (STM32_IRQ_FIRST + 21) /* 21: CPU2 SEV Interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_COMP (STM32_IRQ_FIRST + 22) /* 22: COMP1/COMP2 Interrupts */ #endif @@ -100,8 +100,8 @@ #define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */ #define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Communication Interrupts */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_TIM16 (STM32_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */ # define STM32_IRQ_TIM17 (STM32_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */ #endif @@ -112,37 +112,37 @@ #define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 30) /* 30: I2C1 event interrupt */ #define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 31) /* 31: I2C1 error interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 32) /* 32: I2C3 event interrupt */ # define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 33) /* 33: I2C3 error interrupt */ #endif #define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 34) /* 34: SPI1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 35) /* 35: SPI2 global interrupt */ #endif #define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 36) /* 36: USART1 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) \ - || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) \ + || defined(CONFIG_STM32_STM32WB15) # define STM32_IRQ_LPUART1 (STM32_IRQ_FIRST + 37) /* 37: LPUART1 global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 38) /* 38: SAI1 A/B global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) \ - || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) \ + || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_TSC (STM32_IRQ_FIRST + 39) /* 39: TSC global interrupt */ #endif #define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */ #define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm A/B interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_CRS (STM32_IRQ_FIRST + 42) /* 42: CRS interrupt */ #endif @@ -150,8 +150,8 @@ #define STM32_IRQ_PWRBLEACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of BLE activity interrupt */ #define STM32_IRQ_PWRRFPHASE (STM32_IRQ_FIRST + 43) /* 43: PWR end of critical radio phase interrupt */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_PWR802ACT (STM32_IRQ_FIRST + 43) /* 43: PWR end of 802.15.4 activity interrupt */ #endif @@ -161,11 +161,11 @@ #define STM32_IRQ_LPTIM1 (STM32_IRQ_FIRST + 47) /* 47: LPTIM1 global interrupt */ #define STM32_IRQ_LPTIM2 (STM32_IRQ_FIRST + 48) /* 48: LPTIM2 global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_LCD (STM32_IRQ_FIRST + 49) /* 49: LCD global interrupt */ #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 50) /* 50: QUADSPI global interrupt */ # define STM32_IRQ_AES1 (STM32_IRQ_FIRST + 51) /* 51: AES1 crypto global interrupt */ #endif @@ -174,7 +174,7 @@ #define STM32_IRQ_RNG (STM32_IRQ_FIRST + 53) /* 53: RNG global interrupt */ #define STM32_IRQ_FPU (STM32_IRQ_FIRST + 54) /* 54: FPU global interrupt */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define STM32_IRQ_DMA2CH1 (STM32_IRQ_FIRST + 55) /* 55: DMA2 Channel 1 global interrupt */ # define STM32_IRQ_DMA2CH2 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Channel 2 global interrupt */ # define STM32_IRQ_DMA2CH3 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Channel 3 global interrupt */ diff --git a/arch/arm/src/stm32wb/CMakeLists.txt b/arch/arm/src/stm32wb/CMakeLists.txt index 79f82cf8573..c9646782740 100644 --- a/arch/arm/src/stm32wb/CMakeLists.txt +++ b/arch/arm/src/stm32wb/CMakeLists.txt @@ -55,11 +55,11 @@ else() list(APPEND SRCS stm32wb_tickless.c) endif() -if(CONFIG_STM32WB_ONESHOT) +if(CONFIG_STM32_ONESHOT) list(APPEND SRCS stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c) endif() -if(CONFIG_STM32WB_FREERUN) +if(CONFIG_STM32_FREERUN) list(APPEND SRCS stm32wb_freerun.c) endif() @@ -67,11 +67,11 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32wb_userspace.c stm32wb_mpuinit.c) endif() -if(CONFIG_STM32WB_HAVE_HSI48) +if(CONFIG_STM32_HAVE_HSI48) list(APPEND SRCS stm32wb_rcc_hsi48.c) endif() -if(CONFIG_STM32WB_DMA) +if(CONFIG_STM32_DMA) list(APPEND SRCS stm32wb_dma.c) endif() @@ -84,11 +84,11 @@ if(CONFIG_PM) endif() endif() -if(CONFIG_STM32WB_PWR) +if(CONFIG_STM32_PWR) list(APPEND SRCS stm32wb_exti_pwr.c) endif() -if(CONFIG_STM32WB_RTC) +if(CONFIG_STM32_RTC) if(CONFIG_RTC_ALARM) list(APPEND SRCS stm32wb_exti_alarm.c) endif() @@ -100,15 +100,15 @@ if(CONFIG_STM32WB_RTC) endif() endif() -if(CONFIG_STM32WB_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wb_ipcc.c) endif() -if(CONFIG_STM32WB_MBOX) +if(CONFIG_STM32_MBOX) list(APPEND SRCS stm32wb_mbox.c) endif() -if(CONFIG_STM32WB_BLE) +if(CONFIG_STM32_BLE) list(APPEND SRCS stm32wb_blehci.c) endif() diff --git a/arch/arm/src/stm32wb/Kconfig b/arch/arm/src/stm32wb/Kconfig index aba177dfed9..70a74724de2 100644 --- a/arch/arm/src/stm32wb/Kconfig +++ b/arch/arm/src/stm32wb/Kconfig @@ -7,6 +7,27 @@ if ARCH_CHIP_STM32WB comment "STM32WB Configuration Options" +config STM32_WB_PERIPHERALS + bool + default ARCH_CHIP_STM32WB + select STM32_HAVE_BLE + select STM32_HAVE_DMA1 + select STM32_HAVE_MBOX + select STM32_HAVE_IPCC + select STM32_HAVE_SRAM2A + select STM32_HAVE_SRAM2B + select STM32_HAVE_I2C1 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 if STM32_HAVE_LPUART + select STM32_HAVE_RTC_SUBSECONDS + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + choice prompt "STM32 WB Chip Selection" default ARCH_CHIP_STM32WB55RG @@ -14,129 +35,129 @@ choice config ARCH_CHIP_STM32WB10CC bool "STM32WB10CC" - select STM32WB_STM32WB10 + select STM32_STM32WB10 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB15CC bool "STM32WB15CC" - select STM32WB_STM32WB15 + select STM32_STM32WB15 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_320 + select STM32_FLASH_CONFIG_C_320 ---help--- STM32 WB Cortex M4, 320 Kb FLASH, 12+32+4 Kb SRAM config ARCH_CHIP_STM32WB30CE bool "STM32WB30CE" - select STM32WB_STM32WB30 + select STM32_STM32WB30 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB50CG bool "STM32WB50CG" - select STM32WB_STM32WB50 + select STM32_STM32WB50 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CC bool "STM32WB35CC" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB35CE bool "STM32WB35CE" - select STM32WB_STM32WB35 + select STM32_STM32WB35 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 32+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CC bool "STM32WB55CC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RC bool "STM32WB55RC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VC bool "STM32WB55VC" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_C_256 + select STM32_FLASH_CONFIG_C ---help--- STM32 WB Cortex M4, 256 Kb FLASH, 64+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CE bool "STM32WB55CE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RE bool "STM32WB55RE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VE bool "STM32WB55VE" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_E_512 + select STM32_FLASH_CONFIG_E ---help--- STM32 WB Cortex M4, 512 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VY bool "STM32WB55VY" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_Y_640 + select STM32_FLASH_CONFIG_Y ---help--- STM32 WB Cortex M4, 640 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55CG bool "STM32WB55CG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_C - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55RG bool "STM32WB55RG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_R - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM config ARCH_CHIP_STM32WB55VG bool "STM32WB55VG" - select STM32WB_STM32WB55 + select STM32_STM32WB55 select STM32WB_IO_CONFIG_V - select STM32WB_FLASH_CONFIG_G_1024 + select STM32_FLASH_CONFIG_G ---help--- STM32 WB Cortex M4, 1024 Kb FLASH, 192+32+32 Kb SRAM @@ -144,137 +165,81 @@ endchoice # STM32 WB Chip Selection # Chip product lines -config STM32WB_STM32WB10 +config STM32_STM32WB10 # STM32WB10 Value Line bool default n - select STM32WB_HAVE_TSC + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC -config STM32WB_STM32WB15 +config STM32_STM32WB15 # STM32WB15 Standard Line bool default n - select STM32WB_HAVE_TSC - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TSC + select STM32_HAVE_LPUART + select STM32_HAVE_SMPS if !ARCH_CHIP_STM32WB15CCUXE -config STM32WB_STM32WB30 +config STM32_STM32WB30 # STM32WB30 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB50 +config STM32_STM32WB50 # STM32WB50 Value Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 + select STM32_HAVE_HSI48 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 -config STM32WB_STM32WB35 +config STM32_STM32WB35 # STM32WB35 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_SMPS + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_SMPS -config STM32WB_STM32WB55 +config STM32_STM32WB55 # STM32WB55 Standard Line bool default n - select STM32WB_HAVE_HSI48 - select STM32WB_HAVE_DMA2 - select STM32WB_HAVE_TIM16 - select STM32WB_HAVE_TIM17 - select STM32WB_HAVE_I2C3 - select STM32WB_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_QSPI - select STM32WB_HAVE_USB - select STM32WB_HAVE_SAI - select STM32WB_HAVE_COMP - select STM32WB_HAVE_LPUART - select STM32WB_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V - select STM32WB_HAVE_LCD - select STM32WB_HAVE_SMPS - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WB - default STM32WB_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WB series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - C 256 or 320 - E 512 - Y 640 - G 1024 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32WB Chip Selection. - - Examples: - If the STM32WB55RG is chosen, the Flash configuration would be 'G', if a variant of - the part with a 2048 KiB Flash is released in the future one could simply select - the 'I' designator here. - - If an STM32WB Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WB_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WB_FLASH_OVERRIDE_C_256 - bool "C 256 KB" - -config STM32WB_FLASH_OVERRIDE_C_320 - bool "C 320 KB" - -config STM32WB_FLASH_OVERRIDE_E_512 - bool "E 512 KB" - -config STM32WB_FLASH_OVERRIDE_Y_640 - bool "Y 640 KB" - -config STM32WB_FLASH_OVERRIDE_G_1024 - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WB_FLASH_CONFIG_C_256 - bool - default n - -config STM32WB_FLASH_CONFIG_C_320 - bool - default n - -config STM32WB_FLASH_CONFIG_E_512 - bool - default n - -config STM32WB_FLASH_CONFIG_Y_640 - bool - default n - -config STM32WB_FLASH_CONFIG_G_1024 - bool - default n + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_QSPI + select STM32_HAVE_USB + select STM32_HAVE_SAI + select STM32_HAVE_COMP + select STM32_HAVE_LPUART + select STM32_HAVE_TSC if STM32WB_IO_CONFIG_R || STM32WB_IO_CONFIG_V + select STM32_HAVE_LCD + select STM32_HAVE_SMPS # Pin/package configurations @@ -282,13 +247,13 @@ config STM32WB_IO_CONFIG_C # UFQFPN48 package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_48E # UFQFPN48E package bool default n - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_C_49 # WLCSP49 package @@ -299,889 +264,14 @@ config STM32WB_IO_CONFIG_R # VFQFPN68 package bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE config STM32WB_IO_CONFIG_V # WLCSP100 and UFBGA129 packages bool default n - select STM32WB_GPIO_HAVE_PORTD - select STM32WB_GPIO_HAVE_PORTE - -comment "STM32WB SRAM2a and SRAM2b Options" - -config STM32WB_SRAM2A_HEAP - bool "SRAM2a is used for heap" - default n - -config STM32WB_SRAM2A_USER_BASE_OFFSET - int "SRAM2a user application base offset" - default 2048 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The beginning part of the SRAM2a memory can be used by RF stack. The - available space for the user application can be obtained from the - release notes for STM32WB coprocessor wireless binaries. - -config STM32WB_SRAM2A_USER_SIZE - int "SRAM2a user application size" - default 8192 - range 0 32768 - depends on STM32WB_SRAM2A_HEAP - ---help--- - The ending part of the SRAM2a memory contains a secure section, which - cannot be read nor written by CPU1. The secure start address for the - SRAM2a memory can be read from the SBRSA option byte. When CPU2 update - support required, there must be some free sectors just below the secure - memory to support CPU2 firmware updates requiring more sectors to be - secure. - -config STM32WB_SRAM2A_INIT - bool "SRAM2a is initialized to zero" - default y - depends on STM32WB_SRAM2A_HEAP - ---help--- - The STM32WB SRAM2a region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - However, if the SRAM2a is being retained in Standby mode, this may be - undesirable (because it will destroy the contents). In that case, the board - should handle the initialization itself at the appropriate time. - -config STM32WB_SRAM2B_HEAP - bool "SRAM2b is used for heap" - default n - -config STM32WB_SRAM2B_USER_SIZE - int "SRAM2b user application size" - default 32768 - range 0 32768 - depends on STM32WB_SRAM2B_HEAP - ---help--- - For any CPU2 firmware supporting the BLE protocol the ending part of - the SRAM2b memory contains a secure section, which cannot be read nor - written by CPU1. The secure start address for the SRAM2b memory can be - read from the SNBRSA option byte. When CPU2 update support required, - there must be some free sectors just below the secure memory to support - CPU2 firmware updates requiring more sectors to be secure. The SRAM2b - memory is all secure for any CPU2 firmware supporting the Thread protocol. - -config STM32WB_SRAM2B_INIT - bool "SRAM2b is initialized to zero" - default y - depends on STM32WB_SRAM2B_HEAP - ---help--- - The STM32WB SRAM2b region has parity checking. However, when the system - powers on, the memory is in an unknown state, and reads from uninitialized - memory can trigger parity faults from the random data. This can be - avoided by first writing to all locations to force the parity into a valid - state. - -comment "STM32WB Peripherals" - -menu "STM32WB Peripheral Support" - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WB_GPIO_HAVE_PORTD - bool - default n - -config STM32WB_GPIO_HAVE_PORTE - bool - default n - -config STM32WB_HAVE_COMP - bool - default n - -config STM32WB_HAVE_LPUART - bool - default n - -config STM32WB_HAVE_DMA2 - bool - default n - -config STM32WB_HAVE_TIM16 - bool - default n - -config STM32WB_HAVE_TIM17 - bool - default n - -config STM32WB_HAVE_SPI2 - bool - default n - -config STM32WB_HAVE_I2C3 - bool - default n - -config STM32WB_HAVE_SAI - bool - default n - -config STM32WB_HAVE_LCD - bool - default n - -config STM32WB_HAVE_TSC - bool - default n - -config STM32WB_HAVE_USB - bool - default n - -config STM32WB_HAVE_QSPI - bool - default n - -config STM32WB_HAVE_SMPS - bool - default n - -# These are the peripheral selections proper - -config STM32WB_RTC - bool "RTC" - default n - select RTC - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WB_ADC - bool - default n - -config STM32WB_DMAMUX - bool - default n - -config STM32WB_DMA - bool - default n - select STM32WB_DMAMUX - -config STM32WB_IPCC - bool - default n - -config STM32WB_I2C - bool - default n - -config STM32WB_SAI - bool - default n - -config STM32WB_SPI - bool - default n - -config STM32WB_USART - bool - default n - -config STM32WB_LPTIM - bool - default n - -# These are the peripheral selections proper - -comment "AHB1 Peripherals" - -config STM32WB_DMA1 - bool "DMA1" - default n - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_DMA2 - bool "DMA2" - default n - depends on STM32WB_HAVE_DMA2 - select ARCH_DMA - select STM32WB_DMA - -config STM32WB_CRC - bool "CRC" - default n - -comment "APB1 Peripherals" - -config STM32WB_PWR - bool "PWR" - default n - -config STM32WB_TIM2 - bool "TIM2" - default n - -config STM32WB_SPI2 - bool "SPI2" - default n - depends on STM32WB_HAVE_SPI2 - select SPI - select STM32WB_SPI - -config STM32WB_LPTIM1 - bool "LPTIM1" - default n - select STM32WB_LPTIM - -config STM32WB_LPTIM2 - bool "LPTIM2" - default n - select STM32WB_LPTIM - -config STM32WB_LPUART1 - bool "LPUART1" - default n - depends on STM32WB_HAVE_LPUART - select ARCH_HAVE_SERIAL_TERMIOS - select ARCH_HAVE_LPUART1 - select STM32WB_USART - -config STM32WB_I2C1 - bool "I2C1" - default n - select I2C - select STM32WB_I2C - -config STM32WB_I2C3 - bool "I2C3" - default n - depends on STM32WB_HAVE_I2C3 - select I2C - select STM32WB_I2C - -comment "APB2 Peripherals" - -config STM32WB_SYSCFG - bool "SYSCFG" - default y - -config STM32WB_TIM1 - bool "TIM1" - default n - -config STM32WB_SPI1 - bool "SPI1" - default n - select SPI - select STM32WB_SPI - -config STM32WB_USART1 - bool "USART1" - default n - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WB_USART - -config STM32WB_TIM16 - bool "TIM16" - default n - depends on STM32WB_HAVE_TIM16 - -config STM32WB_TIM17 - bool "TIM17" - default n - depends on STM32WB_HAVE_TIM17 - -endmenu - -config STM32WB_FLASH_PREFETCH - bool "Enable FLASH Pre-fetch" - default y - ---help--- - Enable FLASH prefetch - -config STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG - bool "Disable IDLE Sleep (WFI) in debug mode" - default n - ---help--- - In debug configuration, disables the WFI instruction in the IDLE loop - to prevent the JTAG from disconnecting. With some JTAG debuggers, such - as the ST-LINK2 with OpenOCD, if the ARM is put to sleep via the WFI - instruction, the debugger will disconnect, terminating the debug session. - -config ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG - bool "Custom clock configuration" - default n - ---help--- - Enables special, board-specific STM32WB clock configuration. - -config STM32WB_HAVE_RTC_SUBSECONDS - bool - select ARCH_HAVE_RTC_SUBSECONDS - default y - -menu "RTC Configuration" - depends on STM32WB_RTC - -config STM32WB_RTC_MAGIC_REG - int "BKP register" - default 0 - range 0 31 - ---help--- - The BKP register used to store/check the Magic value to determine if - RTC is already setup - -config STM32WB_RTC_MAGIC - hex "RTC Magic 1" - default 0xfacefeed - ---help--- - Value used as Magic to determine if the RTC is already setup - -config STM32WB_RTC_MAGIC_TIME_SET - hex "RTC Magic 2" - default 0xf00dface - ---help--- - Value used as Magic to determine if the RTC has been setup and has - time set - -choice - prompt "RTC clock source" - default STM32WB_RTC_LSECLOCK - depends on STM32WB_RTC - -config STM32WB_RTC_LSECLOCK - bool "LSE clock" - ---help--- - Drive the RTC with the LSE clock - -config STM32WB_RTC_LSICLOCK - bool "LSI clock" - ---help--- - Drive the RTC with the LSI clock - -config STM32WB_RTC_HSECLOCK - bool "HSE clock" - ---help--- - Drive the RTC with the HSE clock, divided down to 1MHz. - -endchoice - -if STM32WB_RTC_LSECLOCK - -config STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY - int "LSE oscillator drive capability level at LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -config STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY - int "LSE oscillator drive capability level after LSE start-up" - default 0 - range 0 3 - ---help--- - 0 = Low drive capability (default) - 1 = Medium low drive capability - 2 = Medium high drive capability - 3 = High drive capability - -endif # STM32WB_RTC_LSECLOCK - -endmenu # RTC Configuration - -menu "Timer Configuration" - -if SCHED_TICKLESS - -config STM32WB_TICKLESS_TIMER - int "Tickless hardware timer" - default 2 - range 1 17 - ---help--- - If the Tickless OS feature is enabled, then one clock must be - assigned to provided the timer needed by the OS. - -config STM32WB_TICKLESS_CHANNEL - int "Tickless timer channel" - default 1 - range 1 4 - ---help--- - If the Tickless OS feature is enabled, the one clock must be - assigned to provided the free-running timer needed by the OS - and one channel on that clock is needed to handle intervals. - -endif # SCHED_TICKLESS - -config STM32WB_ONESHOT - bool "TIM one-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config STM32WB_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -config STM32WB_ONESHOT_MAXTIMERS - int "Maximum number of oneshot timers" - default 1 - range 1 8 - depends on STM32WB_ONESHOT - ---help--- - Determines the maximum number of oneshot timers that can be - supported. This setting pre-allocates some minimal support for each - of the timers and places an upper limit on the number of oneshot - timers that you can use. - -endmenu # Timer Configuration - -config STM32WB_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WB_LPUART1 || STM32WB_USART1 - -choice - prompt "LPUART1 Driver Configuration" - default STM32WB_LPUART1_SERIALDRIVER - depends on STM32WB_LPUART1 - -config STM32WB_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -if LPUART1_SERIALDRIVER - -config LPUART1_RS485 - bool "RS-485 on LPUART1" - default n - depends on STM32WB_LPUART1 - ---help--- - Enable RS-485 interface on LPUART1. Your board config will have to - provide GPIO_LPUART1_RS485_DIR pin definition. Currently it cannot be - used with LPUART1_RXDMA. - -config LPUART1_RS485_DIR_POLARITY - int "LPUART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on LPUART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on LPUART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config LPUART1_RXDMA - bool "LPUART1 Rx DMA" - default n - depends on STM32WB_LPUART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # LPUART1_SERIALDRIVER - -choice - prompt "USART1 Driver Configuration" - default STM32WB_USART1_SERIALDRIVER - depends on STM32WB_USART1 - -config STM32WB_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WB_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -if USART1_SERIALDRIVER - -config USART1_RS485 - bool "RS-485 on USART1" - default n - depends on STM32WB_USART1 - ---help--- - Enable RS-485 interface on USART1. Your board config will have to - provide GPIO_USART1_RS485_DIR pin definition. Currently it cannot be - used with USART1_RXDMA. - -config USART1_RS485_DIR_POLARITY - int "USART1 RS-485 DIR pin polarity" - default 1 - range 0 1 - depends on USART1_RS485 - ---help--- - Polarity of DIR pin for RS-485 on USART1. Set to state on DIR pin which - enables TX (0 - low / nTXEN, 1 - high / TXEN). - -config USART1_RXDMA - bool "USART1 Rx DMA" - default n - depends on STM32WB_USART1 && STM32WB_DMA - ---help--- - In high data rate usage, Rx DMA may eliminate Rx overrun errors - -endif # USART1_SERIALDRIVER - -if STM32WB_SERIALDRIVER - -comment "Serial Driver Configuration" - -config STM32WB_SERIAL_RXDMA_BUFFER_SIZE - int "Rx DMA buffer size" - default 32 - depends on USART1_RXDMA - ---help--- - The DMA buffer size when using RX DMA to emulate a FIFO. - - When streaming data, the generic serial layer will be called - every time the FIFO receives half this number of bytes. - - Value given here will be rounded up to next multiple of 32 bytes. - -config STM32WB_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32WB_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to another - UART. This is in particular relevant if a project uses the USB console - in some boards and a serial console in other boards, but does not - want the side effect of having all serial port names change when just - the console is moved from serial to USB. - -config STM32WB_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - depends on STM32WB_USART1 - default n - ---help--- - Enable UART RTS flow control using Software. Because STM - Current STM32WB have broken HW based RTS behavior (they assert - nRTS after every byte received) Enable this setting workaround - this issue by using software based management of RTS - -config STM32WB_USART_BREAKS - bool "Add TIOxSBRK to support sending Breaks" - depends on STM32WB_USART1 - default n - ---help--- - Add TIOCxBRK routines to send a line break per the STM32WB manual, the - break will be a pulse based on the value M. This is not a BSD compatible - break. - -config STM32WB_SERIALBRK_BSDCOMPAT - bool "Use GPIO To send Break" - depends on STM32WB_USART1 && STM32WB_USART_BREAKS - default n - ---help--- - Enable using GPIO on the TX pin to send a BSD compatible break: - TIOCSBRK will start the break and TIOCCBRK will end the break. - The current STM32WB U[S]ARTS have no way to leave the break on - (TX=LOW) because software starts the break and then the hardware - automatically clears the break. This makes it difficult to send - a long break. - -config STM32WB_USART_SINGLEWIRE - bool "Single Wire Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable single wire UART support. The option enables support for the - TIOCSSINGLEWIRE ioctl in the STM32WB serial driver. - -config STM32WB_USART_INVERT - bool "Signal Invert Support" - default n - depends on STM32WB_USART1 - ---help--- - Enable signal inversion UART support. The option enables support for the - TIOCSINVERT ioctl in the STM32WB serial driver. - -config STM32WB_USART_SWAP - bool "Swap RX/TX pins support" - default n - depends on STM32WB_USART1 - ---help--- - Enable RX/TX pin swapping support. The option enables support for the - TIOCSSWAP ioctl in the STM32WB serial driver. - -if PM - -config STM32WB_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif - -endif # STM32WB_SERIALDRIVER - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WB_SPI1 || STM32WB_SPI2 - -config STM32WB_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WB_SPI_DMA - bool "SPI DMA" - depends on STM32WB_DMA - default n - ---help--- - Use DMA to improve SPI transfer performance. Cannot be used with STM32WB_SPI_INTERRUPT. - -endmenu - -config STM32WB_MBOX - bool - default n - select STM32WB_IPCC - -menuconfig STM32WB_BLE - bool "BLE" - default n - select STM32WB_MBOX - ---help--- - Enable BLE support. - -if STM32WB_BLE - -config STM32WB_BLE_C2HOST - bool "Enable CPU2 HOST stack" - default n - ---help--- - The full stack version of CPU2 firmware allows to enable CPU2 HOST stack and - control it using vendor ACL protocol. However, it is not expected to enable - this option in the current implementation. - -config STM32WB_BLE_MAX_CONN - int "Maximum BLE simultaneous connections" - range 1 8 - default 2 - -config STM32WB_BLE_GATT_MAX_ATTR_NUM - int "GATT attributes max count" - range 9 255 - default 64 - -config STM32WB_BLE_GATT_MAX_SVC_NUM - int "GATT services max count" - range 2 64 - default 8 - -config STM32WB_BLE_GATT_ATTR_BUF_SIZE - int "GATT attributes storage buf size" - default 1344 - ---help--- - Size of the storage area for attribute values. Hardcoded in CPU2 firmware. - -config STM32WB_BLE_DLE - bool "Support Data Length Extension (DLE)" - default y - -config STM32WB_BLE_MAX_ATT_MTU - int "Maximum supported attribute MTU" - range 23 512 - default 156 - -config STM32WB_BLE_SLAVE_SCA - int "Sleep clock accuracy in slave mode [PPM]" - default 500 - ---help--- - Sleep clock accuracy (ppm value) in slave mode. - -choice - prompt "Sleep clock accuracy in master mode" - default STM32WB_BLE_MASTER_SCA_0 - ---help--- - Sleep clock accuracy in master mode. - -config STM32WB_BLE_MASTER_SCA_0 - bool "251-500 ppm" - -config STM32WB_BLE_MASTER_SCA_1 - bool "151-250 ppm" - -config STM32WB_BLE_MASTER_SCA_2 - bool "101-150 ppm" - -config STM32WB_BLE_MASTER_SCA_3 - bool "76-100 ppm" - -config STM32WB_BLE_MASTER_SCA_4 - bool "51-75 ppm" - -config STM32WB_BLE_MASTER_SCA_5 - bool "31-50 ppm" - -config STM32WB_BLE_MASTER_SCA_6 - bool "21-30 ppm" - -config STM32WB_BLE_MASTER_SCA_7 - bool "0-20 ppm" - -endchoice # Sleep clock accuracy in master mode - -config STM32WB_BLE_MASTER_SCA - int - default 7 if STM32WB_BLE_MASTER_SCA_7 - default 6 if STM32WB_BLE_MASTER_SCA_6 - default 5 if STM32WB_BLE_MASTER_SCA_5 - default 4 if STM32WB_BLE_MASTER_SCA_4 - default 3 if STM32WB_BLE_MASTER_SCA_3 - default 2 if STM32WB_BLE_MASTER_SCA_2 - default 1 if STM32WB_BLE_MASTER_SCA_1 - default 0 - -choice - prompt "Low speed clock source" - default STM32WB_BLE_LS_CLK_SRC_LSE - ---help--- - Low speed 32 kHz clock source. - -config STM32WB_BLE_LS_CLK_SRC_LSE - bool "LSE" - -config STM32WB_BLE_LS_CLK_SRC_HSE - bool "HSE" - -endchoice # Low speed clock source - -config STM32WB_BLE_LS_CLK_SRC - int - default 1 if STM32WB_BLE_LS_CLKSRC_HSE - default 0 - -config STM32WB_BLE_MAX_CONN_EVT_LENGTH - hex "Max connection event length" - default 0xffffffff - ---help--- - Maximum duration of a slave connection event in units of 625/256us (~2.44us). - -config STM32WB_BLE_HSE_STARTUP - hex "HSE startup time" - default 0x148 - ---help--- - HSE startup time in units of 625/256us (~2.44us). - -config STM32WB_BLE_VITERBI - bool "Enable Viterbi algorithm" - default y - ---help--- - Enable Viterbi algorithm implementation - -config STM32WB_BLE_MAX_INITOR_COC_NUM - int "Max number of connection-oriented channels" - range 0 64 - default 32 - ---help--- - Maximum number of connection-oriented channels in initiator mode. - -config STM32WB_BLE_SVC_CHANGED_CHAR - bool "Enable service changed characteristic" - default n - -config STM32WB_BLE_WRITABLE_DEVICE_NAME - bool "Writable device name" - default y - -config STM32WB_BLE_CHAN_SEL_ALG2 - bool "Enable channel selection algorithm 2" - default n - -choice - prompt "Power class" - default STM32WB_BLE_POWER_CLASS_2_3 - -config STM32WB_BLE_POWER_CLASS_2_3 - bool "Power Class 2-3" - -config STM32WB_BLE_POWER_CLASS_1 - bool "Power Class 1" - -endchoice # Power class - -config STM32WB_BLE_MIN_TX_POWER - int "Minimum transmit power [dBm]" - range -127 20 - default 0 - -config STM32WB_BLE_MAX_TX_POWER - int "Maximum transmit power [dBm]" - range -127 20 - default 0 - -choice - prompt "AGC RSSI model" - default STM32WB_BLE_AGC_RSSI_LEGACY - -config STM32WB_BLE_AGC_RSSI_LEGACY - bool "AGC RSSI Legacy" - -config STM32WB_BLE_AGC_RSSI_IMPROVED - bool "AGC RSSI Improved" - -endchoice # AGC RSSI model - -config STM32WB_BLE_ADVERTISING - bool "Support advertising" - default y - -config STM32WB_BLE_SCANNING - bool "Support scanning" - default y - -config STM32WB_BLE_LE_2M_PHY - bool "Support LE 2M PHY" - default y - -config STM32WB_BLE_LE_CODED_PHY - bool "Support LE Coded PHY" - default STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - depends on STM32WB_STM32WB15 || STM32WB_STM32WB35 || STM32WB_STM32WB55 - -config STM32WB_BLE_FICR_STATIC_ADDR - bool "Configure factory generated static random address" - default n - -config STM32WB_BLE_PUB_ADDR - hex "Configure BT public address" - default 0x0000000000 - -endif # STM32WB_BLE - -if STM32WB_MBOX - -config STM32WB_MBOX_TX_CMD_QUEUE_LEN - int "Mailbox TX command queue length" - default 2 - -config STM32WB_MBOX_RX_EVT_QUEUE_LEN - int "Mailbox RX event queue length" - default 5 - -endif # STM32WB_MBOX + select STM32_GPIO_HAVE_PORTD + select STM32_GPIO_HAVE_PORTE endif # ARCH_CHIP_STM32WB diff --git a/arch/arm/src/stm32wb/Make.defs b/arch/arm/src/stm32wb/Make.defs index a8ff0d7afa9..2bf29ecfd14 100644 --- a/arch/arm/src/stm32wb/Make.defs +++ b/arch/arm/src/stm32wb/Make.defs @@ -50,11 +50,11 @@ else CHIP_CSRCS += stm32wb_tickless.c endif -ifeq ($(CONFIG_STM32WB_ONESHOT),y) +ifeq ($(CONFIG_STM32_ONESHOT),y) CHIP_CSRCS += stm32wb_oneshot.c stm32wb_oneshot_lowerhalf.c endif -ifeq ($(CONFIG_STM32WB_FREERUN),y) +ifeq ($(CONFIG_STM32_FREERUN),y) CHIP_CSRCS += stm32wb_freerun.c endif @@ -62,11 +62,11 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32wb_userspace.c stm32wb_mpuinit.c endif -ifeq ($(CONFIG_STM32WB_HAVE_HSI48),y) +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) CHIP_CSRCS += stm32wb_rcc_hsi48.c endif -ifeq ($(CONFIG_STM32WB_DMA),y) +ifeq ($(CONFIG_STM32_DMA),y) CHIP_CSRCS += stm32wb_dma.c endif @@ -79,11 +79,11 @@ CHIP_CSRCS += stm32wb_pminitialize.c endif endif -ifeq ($(CONFIG_STM32WB_PWR),y) +ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32wb_exti_pwr.c endif -ifeq ($(CONFIG_STM32WB_RTC),y) +ifeq ($(CONFIG_STM32_RTC),y) ifeq ($(CONFIG_RTC_ALARM),y) CHIP_CSRCS += stm32wb_exti_alarm.c endif @@ -95,15 +95,15 @@ CHIP_CSRCS += stm32wb_rtc.c stm32wb_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_STM32WB_IPCC),y) +ifeq ($(CONFIG_STM32_IPCC),y) CHIP_CSRCS += stm32wb_ipcc.c endif -ifeq ($(CONFIG_STM32WB_MBOX),y) +ifeq ($(CONFIG_STM32_MBOX),y) CHIP_CSRCS += stm32wb_mbox.c endif -ifeq ($(CONFIG_STM32WB_BLE),y) +ifeq ($(CONFIG_STM32_BLE),y) CHIP_CSRCS += stm32wb_blehci.c endif diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h index 90991b1ee21..0aad9fd84aa 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_flash.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32WB_FLASH_CONFIG_x selects the default FLASH size based on * the chip part number. This value can be overridden with * CONFIG_STM32WB_FLASH_OVERRIDE_x @@ -50,38 +50,38 @@ * N.B. Only Single bank mode is supported */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) && \ - !defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_Y) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C_320) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_Y) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) # error "Flash size not defined" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WB_FLASH_CONFIG_C_256 -# undef CONFIG_STM32WB_FLASH_CONFIG_C_320 -# undef CONFIG_STM32WB_FLASH_CONFIG_E_512 -# undef CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# undef CONFIG_STM32WB_FLASH_CONFIG_G_1024 -# if defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_256) -# define CONFIG_STM32WB_FLASH_CONFIG_C_256 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_C_320) -# define CONFIG_STM32WB_FLASH_CONFIG_C_320 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_E_512) -# define CONFIG_STM32WB_FLASH_CONFIG_E_512 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_Y_640) -# define CONFIG_STM32WB_FLASH_CONFIG_Y_640 -# elif defined(CONFIG_STM32WB_FLASH_OVERRIDE_G_1024) -# define CONFIG_STM32WB_FLASH_CONFIG_G_1024 +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_C_320 +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_Y +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C_320) +# define CONFIG_STM32_FLASH_CONFIG_C_320 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_Y) +# define CONFIG_STM32_FLASH_CONFIG_Y +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif @@ -89,15 +89,15 @@ #define STM32_FLASH_PAGESIZE 4096 -#if defined(CONFIG_STM32WB_FLASH_CONFIG_C_256) /* 256 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 64 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_C_320) /* 320 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_C_320) /* 320 kB */ # define STM32_FLASH_NPAGES 80 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_E_512) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 128 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_Y_640) /* 640 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_Y) /* 640 kB */ # define STM32_FLASH_NPAGES 160 -#elif defined(CONFIG_STM32WB_FLASH_CONFIG_G_1024) /* 1 MB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ # define STM32_FLASH_NPAGES 256 #else # error "Unknown flash configuration!" diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h index 390dc47c2e0..180972f07a7 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_gpio.h @@ -79,7 +79,7 @@ #define STM32_GPIOC_AFRH (STM32_GPIOC_BASE + STM32_GPIO_AFRH_OFFSET) #define STM32_GPIOC_BRR (STM32_GPIOC_BASE + STM32_GPIO_BRR_OFFSET) -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) # define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET) @@ -93,7 +93,7 @@ # define STM32_GPIOD_BRR (STM32_GPIOD_BASE + STM32_GPIO_BRR_OFFSET) #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET) # define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET) # define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h index d5e25cae2f5..a16c5a97dff 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_i2c.h @@ -55,7 +55,7 @@ #define STM32_I2C1_RXDR (STM32_I2C1_BASE + STM32_I2C_RXDR_OFFSET) #define STM32_I2C1_TXDR (STM32_I2C1_BASE + STM32_I2C_TXDR_OFFSET) -#ifdef CONFIG_STM32WB_HAVE_I2C3 +#ifdef CONFIG_STM32_HAVE_I2C3 # define STM32_I2C3_CR1 (STM32_I2C3_BASE + STM32_I2C_CR1_OFFSET) # define STM32_I2C3_CR2 (STM32_I2C3_BASE + STM32_I2C_CR2_OFFSET) # define STM32_I2C3_OAR1 (STM32_I2C3_BASE + STM32_I2C_OAR1_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h index 5b364b57164..547d650589c 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_pinmap.h @@ -30,9 +30,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || \ - defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB35) || \ - defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || \ + defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB35) || \ + defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB55) # include "hardware/stm32wbxx_pinmap.h" #else # error "Unsupported STM32WB Pin map" diff --git a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h index ddf8e305d01..fd433817a3d 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/hardware/stm32wb_spi.h @@ -58,7 +58,7 @@ #define STM32_SPI1_RXCRCR (STM32_SPI1_BASE + STM32_SPI_RXCRCR_OFFSET) #define STM32_SPI1_TXCRCR (STM32_SPI1_BASE + STM32_SPI_TXCRCR_OFFSET) -#if CONFIG_STM32WB_HAVE_SPI2 +#if CONFIG_STM32_HAVE_SPI2 # define STM32_SPI2_CR1 (STM32_SPI2_BASE + STM32_SPI_CR1_OFFSET) # define STM32_SPI2_CR2 (STM32_SPI2_BASE + STM32_SPI_CR2_OFFSET) # define STM32_SPI2_SR (STM32_SPI2_BASE + STM32_SPI_SR_OFFSET) diff --git a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h index ab8255bba6b..7c9a15dd045 100644 --- a/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h +++ b/arch/arm/src/stm32wb/hardware/stm32wbxx_pinmap.h @@ -58,7 +58,7 @@ /* ADC */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_ADC1_IN2_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN3_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN4_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -77,8 +77,8 @@ #define GPIO_ADC1_IN10_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5) #define GPIO_ADC1_IN11_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN6) -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_ADC1_IN12_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN7) # define GPIO_ADC1_IN15_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN8) # define GPIO_ADC1_IN16_0 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN9) @@ -95,7 +95,7 @@ /* Comparators */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_COMP1_INP_1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN1) #define GPIO_COMP1_INP_2 (GPIO_ANALOG | GPIO_PORTB | GPIO_PIN2) @@ -128,7 +128,7 @@ # define GPIO_COMP2_OUT_4 (GPIO_ALT | GPIO_AF12 | GPIO_PORTB | GPIO_PIN11) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* I2C */ @@ -145,7 +145,7 @@ # define GPIO_I2C1_SDA_2 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN9) #endif -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_I2C3_SDA_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN4) #define GPIO_I2C3_SCL_1 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN7) @@ -161,7 +161,7 @@ # define GPIO_I2C3_SDA_4 (GPIO_ALT | GPIO_AF4 | GPIO_OPENDRAIN | GPIO_PORTC | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* JTAG/SWD */ @@ -176,7 +176,7 @@ /* QUADSPI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_QSPI_NCS_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN2) #define GPIO_QSPI_CLK_1 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN3) @@ -198,7 +198,7 @@ # define GPIO_QSPI_BK1_IO3_2 (GPIO_ALT | GPIO_AF10 | GPIO_PORTD | GPIO_PIN7) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* RTC */ @@ -215,7 +215,7 @@ /* SAI */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_SAI1_EXTCLK_1 (GPIO_ALT | GPIO_AF13 | GPIO_PORTA | GPIO_PIN0) #define GPIO_SAI1_EXTCLK_2 (GPIO_ALT | GPIO_AF13 | GPIO_PORTB | GPIO_PIN2) @@ -257,7 +257,7 @@ # define GPIO_SAI1_PDMDI1_3 (GPIO_ALT | GPIO_AF3 | GPIO_PORTD | GPIO_PIN6) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* SPI */ @@ -277,14 +277,14 @@ # define GPIO_SPI1_SCK_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_SPI1_MOSI_4 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN5) # define GPIO_SPI1_MOSI_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN13) # define GPIO_SPI1_NSS_4 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN14) # define GPIO_SPI1_NSS_5 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN6) #endif -#if defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB55) #define GPIO_SPI2_NSS_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN9) #define GPIO_SPI2_NSS_2 (GPIO_ALT | GPIO_AF5 | GPIO_PORTB | GPIO_PIN12) @@ -305,7 +305,7 @@ # define GPIO_SPI2_MISO_3 (GPIO_ALT | GPIO_AF5 | GPIO_PORTD | GPIO_PIN3) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB55) */ /* Timers */ @@ -346,7 +346,7 @@ # define GPIO_TIM1_CH2OUT_2 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTD | GPIO_PIN15) #endif -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) # define GPIO_TIM1_CH3IN_2 (GPIO_ALT | GPIO_AF12 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN7) # define GPIO_TIM1_CH3OUT_2 (GPIO_ALT | GPIO_AF12 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN7) #endif @@ -393,8 +393,8 @@ # define GPIO_TIM2_CH3OUT_3 (GPIO_ALT | GPIO_AF1 | GPIO_PUSHPULL | GPIO_PORTB | GPIO_PIN13) #endif -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_TIM16_BKIN_0 (GPIO_ALT | GPIO_AF14 | GPIO_PORTB | GPIO_PIN5) #define GPIO_TIM16_CH1IN_1 (GPIO_ALT | GPIO_AF14 | GPIO_FLOAT | GPIO_PORTB | GPIO_PIN8) @@ -420,7 +420,7 @@ # define GPIO_TIM17_CH1OUT_3 (GPIO_ALT | GPIO_AF14 | GPIO_PUSHPULL | GPIO_PORTE | GPIO_PIN1) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #define GPIO_LPTIM1_ETR_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6) #define GPIO_LPTIM1_OUT_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN14) @@ -453,7 +453,7 @@ /* Touch Screen Controller */ -#if defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) #if defined(CONFIG_STM32WB_IO_CONFIG_R) || defined(CONFIG_STM32WB_IO_CONFIG_V) # define GPIO_TSC_SYNC_1 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN10) @@ -523,7 +523,7 @@ # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTE | GPIO_PIN2) #endif -#if defined(CONFIG_STM32WB_STM32WB15) +#if defined(CONFIG_STM32_STM32WB15) # define GPIO_TSC_G7_IO1_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN13) # define GPIO_TSC_G7_IO2_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTA | GPIO_PIN10) # define GPIO_TSC_G7_IO3_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN8) @@ -531,12 +531,12 @@ #define GPIO_TSC_G7_IO4_0 (GPIO_ALT | GPIO_AF9 | GPIO_PORTB | GPIO_PIN9) -#endif /* defined(CONFIG_STM32WB_STM32WB10) || defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB10) || defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB55) */ /* IR interface (with timers 16 and 17) */ -#if defined(CONFIG_STM32WB_STM32WB30) || defined(CONFIG_STM32WB_STM32WB50) \ - || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB30) || defined(CONFIG_STM32_STM32WB50) \ + || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) # define GPIO_IR_OUT_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN13) # define GPIO_IR_OUT_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN9) #endif @@ -570,7 +570,7 @@ # define GPIO_USART1_RTS_DE_2 (GPIO_ALT | GPIO_AF7 | GPIO_PORTB | GPIO_PIN3) #endif -#if defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_LPUART1_TX_1 (GPIO_ALT | GPIO_AF8 | GPIO_PORTA | GPIO_PIN2) #define GPIO_LPUART1_TX_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN5) @@ -588,11 +588,11 @@ # define GPIO_LPUART1_RTS_DE_2 (GPIO_ALT | GPIO_AF8 | GPIO_PORTB | GPIO_PIN12) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB15) || defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB15) || defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ /* USB */ -#if defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) +#if defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) #define GPIO_USB_CRS_SYNC_0 (GPIO_ALT | GPIO_AF10 | GPIO_PORTA | GPIO_PIN10) #define GPIO_USB_DM_0 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN11) @@ -603,6 +603,6 @@ # define GPIO_USB_NOE_2 (GPIO_ALT | GPIO_AF10 | GPIO_PUSHPULL | GPIO_PORTC | GPIO_PIN9) #endif -#endif /* defined(CONFIG_STM32WB_STM32WB35) || defined(CONFIG_STM32WB_STM32WB55) */ +#endif /* defined(CONFIG_STM32_STM32WB35) || defined(CONFIG_STM32_STM32WB55) */ #endif /* __ARCH_ARM_SRC_STM32WB_HARDWARE_STM32WBXX_PINMAP_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_allocateheap.c b/arch/arm/src/stm32wb/stm32wb_allocateheap.c index d22ff6b51de..6b94fcd1402 100644 --- a/arch/arm/src/stm32wb/stm32wb_allocateheap.c +++ b/arch/arm/src/stm32wb/stm32wb_allocateheap.c @@ -65,16 +65,16 @@ /* Set the range of SRAM2a as well, requires a second memory region */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif /* Set the range of SRAM2b as well, requires a third memory region */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # define SRAM2B_START STM32_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* Some sanity checking. If multiple memory regions are defined, verify @@ -82,25 +82,25 @@ * that we have been asked to add to the heap. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP # if SRAM2A_END > STM32_SRAM2A_BASE + STM32_SRAM2A_SIZE # error "SRAM2a heap memory region is out of it's physical address space" # endif #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # if SRAM2B_END > STM32_SRAM2B_BASE + STM32_SRAM2B_SIZE # error "SRAM2b heap memory region is out of it's physical address space" # endif #endif -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WB_SRAM2A_HEAP) + \ - defined(CONFIG_STM32WB_SRAM2B_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2A_HEAP) + \ + defined(CONFIG_STM32_SRAM2B_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -283,7 +283,7 @@ void arm_addregion(void) * from the release notes for STM32WB coprocessor wireless binaries. */ -#ifdef CONFIG_STM32WB_SRAM2A_HEAP +#ifdef CONFIG_STM32_SRAM2A_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -301,9 +301,9 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2A_START, SRAM2A_END - SRAM2A_START); -#endif /* CONFIG_STM32WB_SRAM2A_HEAP */ +#endif /* CONFIG_STM32_SRAM2A_HEAP */ -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) @@ -321,6 +321,6 @@ void arm_addregion(void) kumm_addregion((void *)SRAM2B_START, SRAM2B_END - SRAM2B_START); -#endif /* CONFIG_STM32WB_SRAM2B_HEAP */ +#endif /* CONFIG_STM32_SRAM2B_HEAP */ } #endif diff --git a/arch/arm/src/stm32wb/stm32wb_blehci.c b/arch/arm/src/stm32wb/stm32wb_blehci.c index 7b69d9b314f..3df0927bd0e 100644 --- a/arch/arm/src/stm32wb/stm32wb_blehci.c +++ b/arch/arm/src/stm32wb/stm32wb_blehci.c @@ -54,38 +54,38 @@ /* BLE init configuration params */ #define STM32_BLE_PREP_WRITE_NUM \ - STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU) + STM32_MBOX_DEFAULT_BLE_PREP_WRITE_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU) #define STM32_C2_MEM_BLOCK_NUM \ - STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32WB_BLE_MAX_ATT_MTU, \ - CONFIG_STM32WB_BLE_MAX_CONN, \ + STM32_MBOX_DEFAULT_C2_MEM_BLOCK_NUM(CONFIG_STM32_BLE_MAX_ATT_MTU, \ + CONFIG_STM32_BLE_MAX_CONN, \ STM32_BLE_PREP_WRITE_NUM) -#ifdef CONFIG_STM32WB_BLE_C2HOST +#ifdef CONFIG_STM32_BLE_C2HOST # define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL_HOST #else # define STM32_BLE_C2HOST STM32_SHCI_BLE_INIT_OPT_STACK_LL #endif -#ifdef CONFIG_STM32WB_BLE_SVC_CHANGED_CHAR +#ifdef CONFIG_STM32_BLE_SVC_CHANGED_CHAR # define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_ENABLED #else # define STM32_BLE_SVC_CHANGED_CHAR STM32_SHCI_BLE_INIT_OPT_SVC_CHCHAR_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_WRITABLE_DEVICE_NAME +#ifdef CONFIG_STM32_BLE_WRITABLE_DEVICE_NAME # define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RW #else # define STM32_BLE_DEVICE_NAME_MODE STM32_SHCI_BLE_INIT_OPT_DEVICE_NAME_MODE_RO #endif -#ifdef CONFIG_STM32WB_BLE_CHAN_SEL_ALG2 +#ifdef CONFIG_STM32_BLE_CHAN_SEL_ALG2 # define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_ENABLED #else # define STM32_BLE_CS_ALG2 STM32_SHCI_BLE_INIT_OPT_CS_ALG2_DISABLED #endif -#ifdef CONFIG_STM32WB_BLE_POWER_CLASS_1 +#ifdef CONFIG_STM32_BLE_POWER_CLASS_1 # define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_1 #else # define STM32_BLE_POWER_CLASS STM32_SHCI_BLE_INIT_OPT_POWER_CLASS_2_3 @@ -96,7 +96,7 @@ STM32_BLE_DEVICE_NAME_MODE | STM32_BLE_CS_ALG2 | \ STM32_BLE_POWER_CLASS) -#ifdef CONFIG_STM32WB_BLE_AGC_RSSI_IMPROVED +#ifdef CONFIG_STM32_BLE_AGC_RSSI_IMPROVED # define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_IMPROVED #else # define STM32_BLE_RXMOD_AGC_RSSI STM32_SHCI_BLE_INIT_RXMOD_AGC_RSSI_LEGACY @@ -299,25 +299,25 @@ static void stm32_blehci_bleinit(void) { .ble_buf = NULL, .ble_buf_size = 0, - .gatt_attr_num = CONFIG_STM32WB_BLE_GATT_MAX_ATTR_NUM, - .gatt_srv_num = CONFIG_STM32WB_BLE_GATT_MAX_SVC_NUM, - .gatt_attr_buf_size = CONFIG_STM32WB_BLE_GATT_ATTR_BUF_SIZE, - .max_conn = CONFIG_STM32WB_BLE_MAX_CONN, - .dle_enable = CONFIG_STM32WB_BLE_DLE, + .gatt_attr_num = CONFIG_STM32_BLE_GATT_MAX_ATTR_NUM, + .gatt_srv_num = CONFIG_STM32_BLE_GATT_MAX_SVC_NUM, + .gatt_attr_buf_size = CONFIG_STM32_BLE_GATT_ATTR_BUF_SIZE, + .max_conn = CONFIG_STM32_BLE_MAX_CONN, + .dle_enable = CONFIG_STM32_BLE_DLE, .prep_write_op_num = STM32_BLE_PREP_WRITE_NUM, .mem_block_num = STM32_C2_MEM_BLOCK_NUM, - .att_max_mtu_size = CONFIG_STM32WB_BLE_MAX_ATT_MTU, - .slave_sca = CONFIG_STM32WB_BLE_SLAVE_SCA, - .master_sca_range = CONFIG_STM32WB_BLE_MASTER_SCA, - .ls_clock_source = CONFIG_STM32WB_BLE_LS_CLK_SRC, - .conn_event_length = CONFIG_STM32WB_BLE_MAX_CONN_EVT_LENGTH, - .hse_startup = CONFIG_STM32WB_BLE_HSE_STARTUP, - .viterbi_enable = CONFIG_STM32WB_BLE_VITERBI, + .att_max_mtu_size = CONFIG_STM32_BLE_MAX_ATT_MTU, + .slave_sca = CONFIG_STM32_BLE_SLAVE_SCA, + .master_sca_range = CONFIG_STM32_BLE_MASTER_SCA, + .ls_clock_source = CONFIG_STM32_BLE_LS_CLK_SRC, + .conn_event_length = CONFIG_STM32_BLE_MAX_CONN_EVT_LENGTH, + .hse_startup = CONFIG_STM32_BLE_HSE_STARTUP, + .viterbi_enable = CONFIG_STM32_BLE_VITERBI, .options = STM32_BLE_INIT_OPTIONS, .hw_version = 0, - .max_initor_coc_num = CONFIG_STM32WB_BLE_MAX_INITOR_COC_NUM, - .tx_power_min = CONFIG_STM32WB_BLE_MIN_TX_POWER, - .tx_power_max = CONFIG_STM32WB_BLE_MAX_TX_POWER, + .max_initor_coc_num = CONFIG_STM32_BLE_MAX_INITOR_COC_NUM, + .tx_power_min = CONFIG_STM32_BLE_MIN_TX_POWER, + .tx_power_max = CONFIG_STM32_BLE_MAX_TX_POWER, .rx_model_config = STM32_BLE_RXMOD_AGC_RSSI }; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.c b/arch/arm/src/stm32wb/stm32wb_dma.c index d8674fd279c..2ba7cdd517d 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.c +++ b/arch/arm/src/stm32wb/stm32wb_dma.c @@ -42,19 +42,19 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_STM32WB_DMAMUX -# error "Configuration error, CONFIG_STM32WB_DMAMUX not defined!" +#ifndef CONFIG_STM32_DMAMUX +# error "Configuration error, CONFIG_STM32_DMAMUX not defined!" #endif #define DMAMUX_NUM 1 #define DMA_CONTROLLERS 2 -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 # define DMA1_NCHAN 7 #else # define DMA1_NCHAN 0 #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 # define DMA2_NCHAN 7 #else # define DMA2_NCHAN 0 @@ -159,7 +159,7 @@ struct stm32_dma_ops_s * Private Functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) static void stm32_dma12_disable(DMA_CHANNEL dmachan); static int stm32_dma12_interrupt(int irq, void *context, void *arg); static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, @@ -205,7 +205,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* 0 - DMA1 */ { @@ -225,7 +225,7 @@ static const struct stm32_dma_ops_s g_dma_ops[DMA_CONTROLLERS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* 1 - DMA2 */ { @@ -286,7 +286,7 @@ static const struct stm32_dma_s g_dma[DMA_NCHANNELS] = static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = { -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA1 */ { @@ -346,7 +346,7 @@ static struct stm32_dmach_s g_dmach[DMA_NCHANNELS] = }, #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA2 */ { @@ -564,7 +564,7 @@ static void stm32_gdma_limits_get(uint8_t controller, uint8_t *first, * DMA controller functions ****************************************************************************/ -#if defined(CONFIG_STM32WB_DMA1) || defined(CONFIG_STM32WB_DMA2) +#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2) /**************************************************************************** * Name: stm32_dma12_disable @@ -616,14 +616,14 @@ static int stm32_dma12_interrupt(int irq, void *context, void *arg) if (0) { } -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 else if (irq >= STM32_IRQ_DMA1CH1 && irq <= STM32_IRQ_DMA1CH7) { channel = irq - STM32_IRQ_DMA1CH1; controller = DMA1; } #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 else if (irq >= STM32_IRQ_DMA2CH1 && irq <= STM32_IRQ_DMA2CH5) { channel = irq - STM32_IRQ_DMA2CH1; @@ -689,7 +689,7 @@ static void stm32_dma12_setup(DMA_HANDLE handle, uint32_t paddr, " ntransfers: %zd ccr: %08" PRIx32 "\n", paddr, maddr, ntransfers, ccr); -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE DEBUGASSERT(g_dma_ops[dmachan->ctrl].dma_capable(maddr, ntransfers, ccr)); #endif @@ -878,7 +878,7 @@ static void stm32_dma12_dump(DMA_HANDLE handle, } #endif -#endif /* CONFIG_STM32WB_DMA1 || CONFIG_STM32WB_DMA2 */ +#endif /* CONFIG_STM32_DMA1 || CONFIG_STM32_DMA2 */ /**************************************************************************** * Name: stm32_dmamux_sample @@ -1270,7 +1270,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uint32_t maddr, uint32_t count, uint32_t ccr) { unsigned int msize_shift; diff --git a/arch/arm/src/stm32wb/stm32wb_dma.h b/arch/arm/src/stm32wb/stm32wb_dma.h index baf212c4dbd..b8ac1d99217 100644 --- a/arch/arm/src/stm32wb/stm32wb_dma.h +++ b/arch/arm/src/stm32wb/stm32wb_dma.h @@ -78,7 +78,7 @@ struct stm32_dmaregs_s uint32_t cndtr; /* Channel Count Register; determines number of transfers */ uint32_t cpar; /* Channel Peripheral Address Register; determines start */ uint32_t cmar; /* Channel Memory Address Register; determines start */ -#ifndef CONFIG_STM32WB_HAVE_DMAMUX +#ifndef CONFIG_STM32_HAVE_DMAMUX uint32_t cselr; /* Channel Selection Register; chooses peripheral bound */ #else struct @@ -233,7 +233,7 @@ size_t stm32_dmaresidual(DMA_HANDLE handle); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); #else # define stm32_dmacapable(maddr, count, ccr) (true) diff --git a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c index 2b33764174a..6d3a9fddd60 100644 --- a/arch/arm/src/stm32wb/stm32wb_dumpgpio.c +++ b/arch/arm/src/stm32wb/stm32wb_dumpgpio.c @@ -52,10 +52,10 @@ static const char g_portchar[STM32_NPORTS] = { 'A', 'B', 'C', -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) 'D', #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) 'E', #endif 'H' diff --git a/arch/arm/src/stm32wb/stm32wb_flash.c b/arch/arm/src/stm32wb/stm32wb_flash.c index 4d6432f6af5..4b1baf8a7ae 100644 --- a/arch/arm/src/stm32wb/stm32wb_flash.c +++ b/arch/arm/src/stm32wb/stm32wb_flash.c @@ -48,7 +48,7 @@ #include "stm32wb_waste.h" #include "stm32wb_flash.h" -#if !defined(CONFIG_STM32WB_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.c b/arch/arm/src/stm32wb/stm32wb_freerun.c index 570f3b3f2f1..c308a611db3 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.c +++ b/arch/arm/src/stm32wb/stm32wb_freerun.c @@ -37,7 +37,7 @@ #include "stm32wb_freerun.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Private Functions @@ -297,4 +297,4 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) return OK; } -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ diff --git a/arch/arm/src/stm32wb/stm32wb_freerun.h b/arch/arm/src/stm32wb/stm32wb_freerun.h index 9f1a86dc817..ae4dd49ba9c 100644 --- a/arch/arm/src/stm32wb/stm32wb_freerun.h +++ b/arch/arm/src/stm32wb/stm32wb_freerun.h @@ -35,7 +35,7 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_FREERUN +#ifdef CONFIG_STM32_FREERUN /**************************************************************************** * Public Types @@ -158,5 +158,5 @@ int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); } #endif -#endif /* CONFIG_STM32WB_FREERUN */ +#endif /* CONFIG_STM32_FREERUN */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_FREERUN_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_gpio.h b/arch/arm/src/stm32wb/stm32wb_gpio.h index 1103b50cbc2..3e2a3f73e1e 100644 --- a/arch/arm/src/stm32wb/stm32wb_gpio.h +++ b/arch/arm/src/stm32wb/stm32wb_gpio.h @@ -44,9 +44,9 @@ * Pre-Processor Declarations ****************************************************************************/ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_NPORTS 6 -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define STM32_NPORTS 5 #else # define STM32_NPORTS 4 @@ -195,11 +195,11 @@ # define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */ # define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */ # define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */ -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) && defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) && defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */ # define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (5 << GPIO_PORT_SHIFT) /* GPIOH */ -#elif defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#elif defined(CONFIG_STM32_GPIO_HAVE_PORTE) # define GPIO_PORTE (3 << GPIO_PORT_SHIFT) /* GPIOE */ # define GPIO_PORTH (4 << GPIO_PORT_SHIFT) /* GPIOH */ #else diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.c b/arch/arm/src/stm32wb/stm32wb_i2c.c index 85d42440330..50fdb01b3fd 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.c +++ b/arch/arm/src/stm32wb/stm32wb_i2c.c @@ -111,26 +111,26 @@ * * To use this driver, enable the following configuration variable: * - * CONFIG_STM32WB_I2C + * CONFIG_STM32_I2C * * and one or more interfaces: * - * CONFIG_STM32WB_I2C1 - * CONFIG_STM32WB_I2C3 + * CONFIG_STM32_I2C1 + * CONFIG_STM32_I2C3 * * To configure the ISR timeout using fixed values - * (CONFIG_STM32WB_I2C_DYNTIMEO=n): + * (CONFIG_STM32_I2C_DYNTIMEO=n): * - * CONFIG_STM32WB_I2CTIMEOSEC (Timeout in seconds) - * CONFIG_STM32WB_I2CTIMEOMS (Timeout in milliseconds) - * CONFIG_STM32WB_I2CTIMEOTICKS (Timeout in ticks) + * CONFIG_STM32_I2CTIMEOSEC (Timeout in seconds) + * CONFIG_STM32_I2CTIMEOMS (Timeout in milliseconds) + * CONFIG_STM32_I2CTIMEOTICKS (Timeout in ticks) * * To configure the ISR timeout using dynamic values - * (CONFIG_STM32WB_I2C_DYNTIMEO=y): + * (CONFIG_STM32_I2C_DYNTIMEO=y): * - * CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE + * CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * (Timeout in microseconds per byte) - * CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP + * CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP * (Timeout for start/stop in milliseconds) * * Debugging output enabled with: @@ -190,7 +190,7 @@ /* At least one I2C peripheral must be enabled */ -#if defined(CONFIG_STM32WB_I2C1) || defined(CONFIG_STM32WB_I2C3) +#if defined(CONFIG_STM32_I2C1) || defined(CONFIG_STM32_I2C3) /**************************************************************************** * Pre-processor Definitions @@ -202,25 +202,25 @@ /* Interrupt wait timeout in seconds and milliseconds */ -#if !defined(CONFIG_STM32WB_I2CTIMEOSEC) && !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 -# define CONFIG_STM32WB_I2CTIMEOMS 500 /* Default is 500 milliseconds */ +#if !defined(CONFIG_STM32_I2CTIMEOSEC) && !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOSEC 0 +# define CONFIG_STM32_I2CTIMEOMS 500 /* Default is 500 milliseconds */ # warning "Using Default 500 Ms Timeout" -#elif !defined(CONFIG_STM32WB_I2CTIMEOSEC) -# define CONFIG_STM32WB_I2CTIMEOSEC 0 /* User provided milliseconds */ -#elif !defined(CONFIG_STM32WB_I2CTIMEOMS) -# define CONFIG_STM32WB_I2CTIMEOMS 0 /* User provided seconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOSEC) +# define CONFIG_STM32_I2CTIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_STM32_I2CTIMEOMS) +# define CONFIG_STM32_I2CTIMEOMS 0 /* User provided seconds */ #endif /* Interrupt wait time timeout in system timer ticks */ -#ifndef CONFIG_STM32WB_I2CTIMEOTICKS -# define CONFIG_STM32WB_I2CTIMEOTICKS \ - (SEC2TICK(CONFIG_STM32WB_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32WB_I2CTIMEOMS)) +#ifndef CONFIG_STM32_I2CTIMEOTICKS +# define CONFIG_STM32_I2CTIMEOTICKS \ + (SEC2TICK(CONFIG_STM32_I2CTIMEOSEC) + MSEC2TICK(CONFIG_STM32_I2CTIMEOMS)) #endif -#ifndef CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP -# define CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32WB_I2CTIMEOTICKS) +#ifndef CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP +# define CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP TICK2USEC(CONFIG_STM32_I2CTIMEOTICKS) #endif /* Macros to convert an I2C pin to a GPIO output */ @@ -383,9 +383,9 @@ static inline void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, uint8_t offset, uint32_t clearbits, uint32_t setbits); -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs); -#endif /* CONFIG_STM32WB_I2C_DYNTIMEO */ +#endif /* CONFIG_STM32_I2C_DYNTIMEO */ static inline int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv); static inline @@ -429,7 +429,7 @@ static int stm32_i2c_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 static const struct stm32_i2c_config_s stm32_i2c1_config = { .base = STM32_I2C1_BASE, @@ -465,7 +465,7 @@ static struct stm32_i2c_priv_s stm32_i2c1_priv = }; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 static const struct stm32_i2c_config_s stm32_i2c3_config = { .base = STM32_I2C3_BASE, @@ -598,7 +598,7 @@ void stm32_i2c_modifyreg32(struct stm32_i2c_priv_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) { size_t bytecount = 0; @@ -615,7 +615,7 @@ static uint32_t stm32_i2c_toticks(int msgc, struct i2c_msg_s *msgs) * factor. */ - return USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE * bytecount); + return USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE * bytecount); } #endif @@ -673,12 +673,12 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) { /* Wait until either the transfer is complete or the timeout expires */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, stm32_i2c_toticks(priv->msgc, priv->msgv)); #else ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, - CONFIG_STM32WB_I2CTIMEOTICKS); + CONFIG_STM32_I2CTIMEOTICKS); #endif if (ret < 0) { @@ -717,10 +717,10 @@ int stm32_i2c_sem_waitdone(struct stm32_i2c_priv_s *priv) /* Get the timeout value */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO timeout = stm32_i2c_toticks(priv->msgc, priv->msgv); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Signal the interrupt handler that we are waiting. NOTE: Interrupts @@ -863,10 +863,10 @@ void stm32_i2c_sem_waitstop(struct stm32_i2c_priv_s *priv) /* Select a timeout */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO - timeout = USEC2TICK(CONFIG_STM32WB_I2C_DYNTIMEO_STARTSTOP); +#ifdef CONFIG_STM32_I2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_STM32_I2C_DYNTIMEO_STARTSTOP); #else - timeout = CONFIG_STM32WB_I2CTIMEOTICKS; + timeout = CONFIG_STM32_I2CTIMEOTICKS; #endif /* Wait as stop might still be in progress */ @@ -2561,12 +2561,12 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port) switch (port) { -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 case 3: priv = (struct stm32_i2c_priv_s *)&stm32_i2c3_priv; break; @@ -2651,4 +2651,4 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) kmm_free(dev); return OK; } -#endif /* CONFIG_STM32WB_I2C1 || CONFIG_STM32WB_I2C3 */ +#endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32wb/stm32wb_i2c.h b/arch/arm/src/stm32wb/stm32wb_i2c.h index adb5a001e6e..299eb53b686 100644 --- a/arch/arm/src/stm32wb/stm32wb_i2c.h +++ b/arch/arm/src/stm32wb/stm32wb_i2c.h @@ -41,10 +41,10 @@ * seconds per byte value must be provided as well. */ -#ifdef CONFIG_STM32WB_I2C_DYNTIMEO -# if CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32WB_I2C_DYNTIMEO because of CONFIG_STM32WB_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32WB_I2C_DYNTIMEO +#ifdef CONFIG_STM32_I2C_DYNTIMEO +# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 +# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" +# undef CONFIG_STM32_I2C_DYNTIMEO # endif #endif diff --git a/arch/arm/src/stm32wb/stm32wb_idle.c b/arch/arm/src/stm32wb/stm32wb_idle.c index 0a0e6d1ad06..4001f8210e5 100644 --- a/arch/arm/src/stm32wb/stm32wb_idle.c +++ b/arch/arm/src/stm32wb/stm32wb_idle.c @@ -184,7 +184,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); __asm__ volatile ("wfi"); END_IDLE(); diff --git a/arch/arm/src/stm32wb/stm32wb_mbox.c b/arch/arm/src/stm32wb/stm32wb_mbox.c index f92be7547f5..b066a6a804d 100644 --- a/arch/arm/src/stm32wb/stm32wb_mbox.c +++ b/arch/arm/src/stm32wb/stm32wb_mbox.c @@ -64,7 +64,7 @@ #define STM32_MBOX_ACLPKT_BUF_SIZE 264 #define STM32_MBOX_RX_BUF_SIZE \ - (CONFIG_STM32WB_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) + (CONFIG_STM32_MBOX_RX_EVT_QUEUE_LEN * STM32_MBOX_CMDPKT_BUF_SIZE) /**************************************************************************** * Private Types @@ -150,18 +150,18 @@ struct stm32_mbox_shared_buffer_s aligned_data(4) struct stm32_mbox_mem_manager_table_s mm_table; aligned_data(4) stm32_mbox_list_t evtfree_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) stm32_mbox_list_t ble_evt_queue; #endif aligned_data(4) stm32_mbox_list_t sys_evt_queue; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) uint8_t ble_cs_buffer[STM32_MBOX_CS_BUF_SIZE]; #endif aligned_data(4) uint8_t evtpool_buffer[STM32_MBOX_RX_BUF_SIZE]; aligned_data(4) uint8_t sys_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t sys_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE aligned_data(4) uint8_t ble_spare_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t ble_cmd_buffer[STM32_MBOX_CMDPKT_BUF_SIZE]; aligned_data(4) uint8_t ble_acl_buffer[STM32_MBOX_ACLPKT_BUF_SIZE]; @@ -204,12 +204,12 @@ static struct work_s g_tx_cmd_work; static stm32_mbox_list_t g_rx_evt_queue; static stm32_mbox_list_t g_tx_evtfree_queue; -static uint8_t g_free_buffers[CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN] +static uint8_t g_free_buffers[CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN] [STM32_MBOX_CMDPKT_BUF_SIZE]; static stm32_mbox_list_t g_free_buffers_pool; static struct stm32_mbox_channel_s g_syscmd_channel; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE static struct stm32_mbox_channel_s g_blecmd_channel; static struct stm32_mbox_channel_s g_bleacl_channel; #endif @@ -243,7 +243,7 @@ static void stm32_ipcc_rxoisr(int irq, uint32_t *regs, void *arg) clrmask |= IPCC_C1SCR_CLR_BIT(STM32_MBOX_SYSEVT_CHANNEL); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Pull events from BLE channel into processing queue */ @@ -363,7 +363,7 @@ static void stm32_mbox_txworker(void *arg) handled = stm32_mbox_txnext(&g_syscmd_channel); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE if (!stm32_ipcc_txactive(STM32_MBOX_BLECMD_CHANNEL)) { handled |= stm32_mbox_txnext(&g_blecmd_channel); @@ -628,7 +628,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_list_initialize(&stm32_mbox_shared.sys_evt_queue); stm32_mbox_list_initialize(&stm32_mbox_shared.evtfree_buffer); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_list_initialize(&stm32_mbox_shared.ble_evt_queue); #endif @@ -648,12 +648,12 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) .evtfree_buffer; stm32_mbox_mm_table.sys_spare_buffer = &stm32_mbox_shared .sys_spare_buffer; -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_mm_table.ble_spare_buffer = &stm32_mbox_shared .ble_spare_buffer; #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE stm32_mbox_ble_table.cmd_buffer = &stm32_mbox_shared.ble_cmd_buffer; stm32_mbox_ble_table.acl_buffer = &stm32_mbox_shared.ble_acl_buffer; stm32_mbox_ble_table.cs_buffer = &stm32_mbox_shared.ble_cs_buffer; @@ -667,7 +667,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_shared.sys_cmd_buffer; stm32_mbox_list_initialize(&g_syscmd_channel.cmd_buf_queue); -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Init BLE command channel data */ g_blecmd_channel.ch_num = STM32_MBOX_BLECMD_CHANNEL; @@ -689,7 +689,7 @@ void stm32_mboxinitialize(stm32_mbox_evt_handler_t evt_handler) stm32_mbox_list_initialize(&g_tx_evtfree_queue); stm32_mbox_list_initialize(&g_free_buffers_pool); - for (i = 0; i < CONFIG_STM32WB_MBOX_TX_CMD_QUEUE_LEN; i++) + for (i = 0; i < CONFIG_STM32_MBOX_TX_CMD_QUEUE_LEN; i++) { stm32_mbox_list_add_tail(&g_free_buffers_pool, (stm32_mbox_list_t *)g_free_buffers[i]); @@ -751,7 +751,7 @@ int stm32_mbox_syscmd(void *data, size_t len) data, len); } -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /**************************************************************************** * Name: stm32_mbox_blecmd * @@ -812,4 +812,4 @@ void stm32_mbox_bleinit(struct stm32_shci_ble_init_cfg_s *params) stm32_ipcc_unmaskrxo(STM32_MBOX_BLEEVT_CHANNEL); } -#endif /* CONFIG_STM32WB_BLE */ +#endif /* CONFIG_STM32_BLE */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.c b/arch/arm/src/stm32wb/stm32wb_oneshot.c index 9666c714bda..80e63c4b4e9 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.c +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.c @@ -39,7 +39,7 @@ #include "stm32wb_oneshot.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Private Function Prototypes @@ -51,7 +51,7 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg); * Private Data ****************************************************************************/ -static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32WB_ONESHOT_MAXTIMERS]; +static struct stm32_oneshot_s *g_oneshot[CONFIG_STM32_ONESHOT_MAXTIMERS]; /**************************************************************************** * Private Functions @@ -117,19 +117,19 @@ static int stm32_oneshot_handler(int irq, void *context, void *arg) * * Returned Value: * Returns zero (OK) on success. This can only fail if the number of - * timers exceeds CONFIG_STM32WB_ONESHOT_MAXTIMERS. + * timers exceeds CONFIG_STM32_ONESHOT_MAXTIMERS. * ****************************************************************************/ static inline int stm32_allocate_handler(struct stm32_oneshot_s *oneshot) { -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 int ret = -EBUSY; int i; /* Search for an unused handler */ - for (i = 0; i < CONFIG_STM32WB_ONESHOT_MAXTIMERS; i++) + for (i = 0; i < CONFIG_STM32_ONESHOT_MAXTIMERS; i++) { /* Is this handler available? */ @@ -456,4 +456,4 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, return OK; } -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32wb/stm32wb_oneshot.h b/arch/arm/src/stm32wb/stm32wb_oneshot.h index d84e8f15b1c..9b02e37ca1c 100644 --- a/arch/arm/src/stm32wb/stm32wb_oneshot.h +++ b/arch/arm/src/stm32wb/stm32wb_oneshot.h @@ -36,22 +36,22 @@ #include "stm32wb_tim.h" -#ifdef CONFIG_STM32WB_ONESHOT +#ifdef CONFIG_STM32_ONESHOT /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_STM32WB_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32WB_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 1 +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 #endif -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 8 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 # warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32WB_ONESHOT_MAXTIMERS -# define CONFIG_STM32WB_ONESHOT_MAXTIMERS 8 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 #endif /**************************************************************************** @@ -75,7 +75,7 @@ typedef void (*oneshot_handler_t)(void *arg); struct stm32_oneshot_s { uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32WB_ONESHOT_MAXTIMERS > 1 +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 uint8_t cbndx; /* Timer callback handler index */ #endif volatile bool running; /* True: the timer is running */ @@ -194,5 +194,5 @@ int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, } #endif -#endif /* CONFIG_STM32WB_ONESHOT */ +#endif /* CONFIG_STM32_ONESHOT */ #endif /* __ARCH_ARM_SRC_STM32WB_STM32WB_ONESHOT_H */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.c b/arch/arm/src/stm32wb/stm32wb_rcc.c index 5a7bb4f22ba..d7dd502e49b 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc.c @@ -61,7 +61,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Determine if board wants to use HSI48 as 48 MHz oscillator. */ -#if defined(CONFIG_STM32WB_HAVE_HSI48) && defined(STM32_USE_CLK48) +#if defined(CONFIG_STM32_HAVE_HSI48) && defined(STM32_USE_CLK48) # if STM32_CLK48_SEL == RCC_CCIPR_CLK48SEL_HSI48 # define STM32_USE_HSI48 # endif @@ -150,31 +150,31 @@ static inline void rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WB_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WB_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WB_DMAMUX +#ifdef CONFIG_STM32_DMAMUX /* DMAMUX 1 clock enable */ regval |= RCC_AHB1ENR_DMAMUX1EN; #endif -#ifdef CONFIG_STM32WB_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; #endif -#ifdef CONFIG_STM32WB_TSC +#ifdef CONFIG_STM32_TSC /* TSC clock enable */ regval |= RCC_AHB1ENR_TSCEN; @@ -204,15 +204,15 @@ static inline void rcc_enableahb2(void) /* Enable GPIO ports A-E, H */ regval |= (RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | RCC_AHB2ENR_GPIOCEN -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTD) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTD) | RCC_AHB2ENR_GPIODEN #endif -#if defined(CONFIG_STM32WB_GPIO_HAVE_PORTE) +#if defined(CONFIG_STM32_GPIO_HAVE_PORTE) | RCC_AHB2ENR_GPIOEEN #endif | RCC_AHB2ENR_GPIOHEN); -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADCEN; @@ -245,13 +245,13 @@ static inline void rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WB_QSPI +#ifdef CONFIG_STM32_QSPI /* QuadSPI module clock enable */ regval |= RCC_AHB3ENR_QSPIEN; #endif -#ifdef CONFIG_STM32WB_PKA +#ifdef CONFIG_STM32_PKA /* Public key accelerator clock enable */ regval |= RCC_AHB3ENR_PKAEN; @@ -263,25 +263,25 @@ static inline void rcc_enableahb3(void) regval |= RCC_AHB3ENR_AES2EN; #endif -#ifdef CONFIG_STM32WB_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB3ENR_RNGEN; #endif -#ifdef CONFIG_STM32WB_HSEM +#ifdef CONFIG_STM32_HSEM /* Hardware semaphore clock enable */ regval |= RCC_AHB3ENR_HSEMEN; #endif -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC /* Inter-processor communication controller clock enable */ regval |= RCC_AHB3ENR_IPCCEN; #endif -#ifdef CONFIG_STM32WB_FLASH +#ifdef CONFIG_STM32_FLASH /* Flash memory interface clock enable */ regval |= RCC_AHB3ENR_FLASHEN; @@ -308,43 +308,43 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WB_LCD +#ifdef CONFIG_STM32_LCD /* LCD clock enable */ regval |= RCC_APB1ENR1_LCDEN; #endif -#if defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_RTC) /* RTC APB clock enable */ regval |= RCC_APB1ENR1_RTCAPBEN; #endif -#if defined(CONFIG_STM32WB_WWDG) +#if defined(CONFIG_STM32_WWDG) /* Window watchdog clock enable */ regval |= RCC_APB1ENR1_WWDGEN; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; @@ -359,13 +359,13 @@ static inline void rcc_enableapb1(void) } #endif -#if defined(CONFIG_STM32WB_USB) +#if defined(CONFIG_STM32_USB) /* USB clock enable */ regval |= RCC_APB1ENR1_USBEN; #endif -#ifdef CONFIG_STM32WB_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -377,13 +377,13 @@ static inline void rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WB_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WB_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; @@ -410,37 +410,37 @@ static inline void rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WB_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM17 clock enable */ regval |= RCC_APB2ENR_TIM17EN; #endif -#ifdef CONFIG_STM32WB_SAI1 +#ifdef CONFIG_STM32_SAI1 /* SAI1 clock enable */ regval |= RCC_APB2ENR_SAI1EN; @@ -469,13 +469,13 @@ static inline void rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32WB_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval &= ~RCC_CCIPR_I2C1SEL_MASK; regval |= RCC_CCIPR_I2C1SEL_HSI16; #endif -#ifdef CONFIG_STM32WB_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval &= ~RCC_CCIPR_I2C3SEL_MASK; @@ -493,7 +493,7 @@ static inline void rcc_enableccip(void) regval |= RCC_CCIPR_CLK48SEL_HSI48; #endif -#if defined(CONFIG_STM32WB_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval &= ~RCC_CCIPR_ADCSEL_MASK; @@ -513,7 +513,7 @@ static inline void rcc_enableccip(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG static void stm32_stdclockconfig(void) { uint32_t regval; @@ -713,7 +713,7 @@ static void stm32_stdclockconfig(void) { } -#ifdef CONFIG_STM32WB_SAI1PLL +#ifdef CONFIG_STM32_SAI1PLL /* Configure SAI1 PLL */ regval = getreg32(STM32_RCC_PLLSAI1CFG); @@ -764,7 +764,7 @@ static void stm32_stdclockconfig(void) /* Enable FLASH prefetch, instruction cache and data cache */ -#ifdef CONFIG_STM32WB_FLASH_PREFETCH +#ifdef CONFIG_STM32_FLASH_PREFETCH regval |= FLASH_ACR_PRFTEN; #else regval &= ~FLASH_ACR_PRFTEN; @@ -786,7 +786,7 @@ static void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32WB_IWDG) || defined(CONFIG_STM32WB_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enable_lsi(); @@ -871,7 +871,7 @@ static inline void rcc_enableperipherals(void) * ****************************************************************************/ -#if defined(CONFIG_STM32WB_PWR) && defined(CONFIG_STM32WB_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void rcc_resetbkp(void) { bool init_stat; @@ -930,7 +930,7 @@ static inline void rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -952,7 +952,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -987,7 +987,7 @@ void stm32_clockconfig(void) * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -1002,7 +1002,7 @@ void stm32_clockconfig(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ diff --git a/arch/arm/src/stm32wb/stm32wb_rcc.h b/arch/arm/src/stm32wb/stm32wb_rcc.h index a8cd788caeb..438138e0de7 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc.h +++ b/arch/arm/src/stm32wb/stm32wb_rcc.h @@ -29,6 +29,7 @@ #include +#include "arm_internal.h" #include "chip.h" #include "hardware/stm32wb_rcc.h" @@ -115,7 +116,7 @@ static inline void stm32_mcoconfig(uint32_t source, uint32_t divider) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -138,7 +139,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -156,7 +157,7 @@ void stm32_board_clockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WB_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c index 1e56d0e3cd8..8a830216564 100644 --- a/arch/arm/src/stm32wb/stm32wb_rcc_lse.c +++ b/arch/arm/src/stm32wb/stm32wb_rcc_lse.c @@ -35,16 +35,16 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -86,11 +86,11 @@ void stm32_rcc_enable_lse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; #endif @@ -103,18 +103,18 @@ void stm32_rcc_enable_lse(void) stm32_waste(); } -#if defined(CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ - CONFIG_STM32WB_RTC_LSECLOCK_START_DRV_CAPABILITY != \ - CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY +#if defined(CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY) && \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY != \ + CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY -# if CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 +# if CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY != 0 # error "STM32WB only allows lowering LSE drive capability to zero" # endif /* Set running drive capability for LSE oscillator. */ regval &= ~RCC_BDCR_LSEDRV_MASK; - regval |= CONFIG_STM32WB_RTC_LSECLOCK_RUN_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_RUN_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.c b/arch/arm/src/stm32wb/stm32wb_rtc.c index 2b849fd12c2..ed057295c69 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.c +++ b/arch/arm/src/stm32wb/stm32wb_rtc.c @@ -43,7 +43,7 @@ #include "stm32wb_rtc.h" #include "stm32wb_exti.h" -#ifdef CONFIG_STM32WB_RTC +#ifdef CONFIG_STM32_RTC /**************************************************************************** * Pre-processor Definitions @@ -64,8 +64,8 @@ # error "CONFIG_RTC_HIRES must NOT be set with this driver" #endif -#ifndef CONFIG_STM32WB_PWR -# error "CONFIG_STM32WB_PWR must selected to use this driver" +#ifndef CONFIG_STM32_PWR +# error "CONFIG_STM32_PWR must selected to use this driver" #endif /* Constants ****************************************************************/ @@ -860,13 +860,13 @@ int up_rtc_initialize(void) stm32_pwr_enablebkp(true); -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_HSE); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSI); -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE); #else @@ -909,7 +909,7 @@ int up_rtc_initialize(void) /* Configure RTC pre-scaler with the required values */ -#ifdef CONFIG_STM32WB_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* The HSE is divided by 32 prior to the prescaler we set here. * 1953 * NOTE: max HSE/32 is 4 MHz if it is to be used with RTC @@ -922,7 +922,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)7812 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) /* Suitable values for 32.000 KHz LSI clock (29.5 - 34 KHz, * though) */ @@ -930,7 +930,7 @@ int up_rtc_initialize(void) putreg32(((uint32_t)0xf9 << RTC_PRER_PREDIV_S_SHIFT) | ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), STM32_RTC_PRER); -#else /* defined(CONFIG_STM32WB_RTC_LSECLOCK) */ +#else /* defined(CONFIG_STM32_RTC_LSECLOCK) */ /* Correct values for 32.768 KHz LSE clock */ putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | @@ -1012,7 +1012,7 @@ int up_rtc_initialize(void) int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS uint32_t ssr; #endif uint32_t dr; @@ -1031,7 +1031,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, { dr = getreg32(STM32_RTC_DR); tr = getreg32(STM32_RTC_TR); -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS ssr = getreg32(STM32_RTC_SSR); tmp = getreg32(STM32_RTC_TR); if (tmp != tr) @@ -1089,7 +1089,7 @@ int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, * of nsec has been provided to receive the sub-second value. */ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS if (nsec) { uint32_t prediv_s; @@ -1169,8 +1169,8 @@ int up_rtc_getdatetime(struct tm *tp) ****************************************************************************/ #ifdef CONFIG_ARCH_HAVE_RTC_SUBSECONDS -# ifndef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS -# error "Invalid config, enable CONFIG_STM32WB_HAVE_RTC_SUBSECONDS." +# ifndef CONFIG_STM32_HAVE_RTC_SUBSECONDS +# error "Invalid config, enable CONFIG_STM32_HAVE_RTC_SUBSECONDS." # endif int up_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec) { @@ -1655,11 +1655,11 @@ int stm32_rtc_setperiodic(const struct timespec *period, uint32_t secs; uint32_t millisecs; -#if defined(CONFIG_STM32WB_RTC_HSECLOCK) +#if defined(CONFIG_STM32_RTC_HSECLOCK) # error "Periodic wakeup not available for HSE" -#elif defined(CONFIG_STM32WB_RTC_LSICLOCK) +#elif defined(CONFIG_STM32_RTC_LSICLOCK) # error "Periodic wakeup not available for LSI (and it is too inaccurate!)" -#elif defined(CONFIG_STM32WB_RTC_LSECLOCK) +#elif defined(CONFIG_STM32_RTC_LSECLOCK) const uint32_t rtc_div16_max_msecs = 16 * 1000 * 0xffffu / STM32_LSE_FREQUENCY; #else @@ -1830,4 +1830,4 @@ int stm32_rtc_cancelperiodic(void) } #endif -#endif /* CONFIG_STM32WB_RTC */ +#endif /* CONFIG_STM32_RTC */ diff --git a/arch/arm/src/stm32wb/stm32wb_rtc.h b/arch/arm/src/stm32wb/stm32wb_rtc.h index 65a8edf5387..500d5dfcd4d 100644 --- a/arch/arm/src/stm32wb/stm32wb_rtc.h +++ b/arch/arm/src/stm32wb/stm32wb_rtc.h @@ -43,21 +43,21 @@ #define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed * of 16384 Hz */ -#if !defined(CONFIG_STM32WB_RTC_MAGIC) -# define CONFIG_STM32WB_RTC_MAGIC (0xfacefeee) +#if !defined(CONFIG_STM32_RTC_MAGIC) +# define CONFIG_STM32_RTC_MAGIC (0xfacefeee) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_TIME_SET) -# define CONFIG_STM32WB_RTC_MAGIC_TIME_SET (0xf00dface) +#if !defined(CONFIG_STM32_RTC_MAGIC_TIME_SET) +# define CONFIG_STM32_RTC_MAGIC_TIME_SET (0xf00dface) #endif -#if !defined(CONFIG_STM32WB_RTC_MAGIC_REG) -# define CONFIG_STM32WB_RTC_MAGIC_REG (0) +#if !defined(CONFIG_STM32_RTC_MAGIC_REG) +# define CONFIG_STM32_RTC_MAGIC_REG (0) #endif -#define RTC_MAGIC CONFIG_STM32WB_RTC_MAGIC -#define RTC_MAGIC_TIME_SET CONFIG_STM32WB_RTC_MAGIC_TIME_SET -#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32WB_RTC_MAGIC_REG) +#define RTC_MAGIC CONFIG_STM32_RTC_MAGIC +#define RTC_MAGIC_TIME_SET CONFIG_STM32_RTC_MAGIC_TIME_SET +#define RTC_MAGIC_REG STM32_RTC_BKPR(CONFIG_STM32_RTC_MAGIC_REG) /**************************************************************************** * Public Types @@ -158,7 +158,7 @@ bool stm32_rtc_is_initialized(void); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_HAVE_RTC_SUBSECONDS +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(struct tm *tp, long *nsec); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 78bd2aaef33..a67006f7cf9 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -87,11 +87,11 @@ * The buffer size should be an even multiple of ARMV7M_DCACHE_LINESIZE. */ -# if !defined(CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WB_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -123,8 +123,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WB_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WB_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -141,7 +141,7 @@ * See stm32_serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -335,7 +335,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -343,7 +343,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -353,7 +353,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32WB LPUART1 port. */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -415,7 +415,7 @@ static struct stm32_serial_s g_lpuart1priv = /* This describes the state of the STM32WB USART1 port. */ -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -480,10 +480,10 @@ static struct stm32_serial_s g_usart1priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif }; @@ -727,7 +727,7 @@ static void stm32_serial_setbaud_usart(struct stm32_serial_s *priv) ****************************************************************************/ #ifndef CONFIG_SUPPRESS_UART_CONFIG -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static void stm32_serial_setbaud_lpuart(struct stm32_serial_s *priv) { uint32_t brr; @@ -771,7 +771,7 @@ static void stm32_serial_setformat(struct uart_dev_s *dev) /* Set baud rate */ -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER if (priv->usartbase == STM32_LPUART1_BASE) { stm32_serial_setbaud_lpuart(priv); @@ -841,7 +841,7 @@ static void stm32_serial_setformat(struct uart_dev_s *dev) regval = stm32_serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1044,13 +1044,13 @@ static void stm32_serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; @@ -1118,7 +1118,7 @@ static int stm32_serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WB_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1463,8 +1463,8 @@ static int up_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WB_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WB_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1608,7 +1608,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1677,7 +1677,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1728,7 +1728,7 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WB_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1865,8 +1865,8 @@ static int stm32_serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WB_USART_BREAKS -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2093,7 +2093,7 @@ static bool stm32_serial_rxflowcontrol(struct uart_dev_s *dev, struct stm32_serial_s *priv = (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WB_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2444,7 +2444,7 @@ static void stm32_serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WB_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2767,7 +2767,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2796,7 +2796,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WB_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32wb/stm32wb_spi.c b/arch/arm/src/stm32wb/stm32wb_spi.c index 84e96d003b6..515f98920ab 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.c +++ b/arch/arm/src/stm32wb/stm32wb_spi.c @@ -80,7 +80,7 @@ #include -#if defined(CONFIG_STM32WB_SPI1) || defined(CONFIG_STM32WB_SPI2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) /**************************************************************************** * Pre-processor Definitions @@ -90,19 +90,19 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WB_SPI_INTERRUPTS) && defined(CONFIG_STM32WB_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO @@ -136,10 +136,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -183,7 +183,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv); /* DMA support */ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -243,7 +243,7 @@ static int spi_pm_prepare(struct pm_callback_s *cb, int domain, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_spi1ops = { .lock = spi_lock, @@ -283,10 +283,10 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* lines must be configured in board.h */ .rxch = DMAMAP_SPI1_RX, @@ -301,7 +301,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 static const struct spi_ops_s g_spi2ops = { .lock = spi_lock, @@ -341,10 +341,10 @@ static struct stm32_spidev_s g_spi2dev = }, .spibase = STM32_SPI2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WB_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2, #endif -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA .rxch = DMACHAN_SPI2_RX, .txch = DMACHAN_SPI2_TX, .rxsem = SEM_INITIALIZER(0), @@ -575,7 +575,7 @@ static inline bool spi_16bitmode(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -608,7 +608,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -641,7 +641,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -656,7 +656,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -671,7 +671,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -691,7 +691,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -711,7 +711,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) { @@ -761,7 +761,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -812,7 +812,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -828,7 +828,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1290,8 +1290,8 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WB_SPI_DMA) || defined(CONFIG_STM32WB_DMACAPABLE) -#if !defined(CONFIG_STM32WB_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1374,7 +1374,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WB_SPI_DMA || CONFIG_STM32WB_DMACAPABLE */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1397,14 +1397,14 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; int ret; -#ifdef CONFIG_STM32WB_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && !stm32_dmacapable((uint32_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && @@ -1466,7 +1466,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WB_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1487,7 +1487,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1688,7 +1688,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WB_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA /* Get DMA channels. NOTE: stm32_dmachannel() will always assign the DMA * channel. If the channel is not available, then stm32_dmachannel() * will block and wait until the channel becomes available. WARNING: If @@ -1742,7 +1742,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1767,7 +1767,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 if (bus == 2) { /* Select SPI2 */ @@ -1800,4 +1800,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WB_SPI1 || CONFIG_STM32WB_SPI2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/arch/arm/src/stm32wb/stm32wb_spi.h b/arch/arm/src/stm32wb/stm32wb_spi.h index 79fb78f1dee..59e20e91e18 100644 --- a/arch/arm/src/stm32wb/stm32wb_spi.h +++ b/arch/arm/src/stm32wb/stm32wb_spi.h @@ -104,14 +104,14 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); @@ -139,12 +139,12 @@ int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WB_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif diff --git a/arch/arm/src/stm32wb/stm32wb_start.c b/arch/arm/src/stm32wb/stm32wb_start.c index eade4167de7..6e80fa7f6d8 100644 --- a/arch/arm/src/stm32wb/stm32wb_start.c +++ b/arch/arm/src/stm32wb/stm32wb_start.c @@ -63,14 +63,14 @@ #define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) -#ifdef CONFIG_STM32WB_SRAM2A_HEAP -# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32WB_SRAM2A_USER_BASE_OFFSET) -# define SRAM2A_END (SRAM2A_START + CONFIG_STM32WB_SRAM2A_USER_SIZE) +#ifdef CONFIG_STM32_SRAM2A_HEAP +# define SRAM2A_START (STM32_SRAM2A_BASE + CONFIG_STM32_SRAM2A_USER_BASE_OFFSET) +# define SRAM2A_END (SRAM2A_START + CONFIG_STM32_SRAM2A_USER_SIZE) #endif -#ifdef CONFIG_STM32WB_SRAM2B_HEAP +#ifdef CONFIG_STM32_SRAM2B_HEAP # define SRAM2B_START STM32_SRAM2B_BASE -# define SRAM2B_END (SRAM2B_START + CONFIG_STM32WB_SRAM2B_USER_SIZE) +# define SRAM2B_END (SRAM2B_START + CONFIG_STM32_SRAM2B_USER_SIZE) #endif /* g_idle_topstack: _sbss is the start of the BSS region as defined by the @@ -148,14 +148,14 @@ void __start(void) * using this memory for, say, additional heap space, then this is handy. */ -#ifdef CONFIG_STM32WB_SRAM2A_INIT +#ifdef CONFIG_STM32_SRAM2A_INIT for (dest = (uint32_t *)SRAM2A_START; dest < (uint32_t *)SRAM2A_END; ) { *dest++ = 0; } #endif -#ifdef CONFIG_STM32WB_SRAM2B_INIT +#ifdef CONFIG_STM32_SRAM2B_INIT for (dest = (uint32_t *)SRAM2B_START; dest < (uint32_t *)SRAM2B_END; ) { *dest++ = 0; @@ -165,7 +165,7 @@ void __start(void) /* Configure the UART so that we can get debug output as soon as possible */ stm32_clockconfig(); -#ifdef CONFIG_STM32WB_IPCC +#ifdef CONFIG_STM32_IPCC stm32_ipccreset(); #endif arm_fpuconfig(); diff --git a/arch/arm/src/stm32wb/stm32wb_tickless.c b/arch/arm/src/stm32wb/stm32wb_tickless.c index 7d99e9082c9..a8ae84dc54e 100644 --- a/arch/arm/src/stm32wb/stm32wb_tickless.c +++ b/arch/arm/src/stm32wb/stm32wb_tickless.c @@ -84,8 +84,8 @@ #undef HAVE_32BIT_TICKLESS -#ifdef CONFIG_STM32WB_TICKLESS_TIMER -# if CONFIG_STM32WB_TICKLESS_TIMER == 2 +#ifdef CONFIG_STM32_TICKLESS_TIMER +# if CONFIG_STM32_TICKLESS_TIMER == 2 # define HAVE_32BIT_TICKLESS 1 # endif #else @@ -360,27 +360,27 @@ static int stm32_tickless_handler(int irq, void *context, void *arg) void up_timer_initialize(void) { - switch (CONFIG_STM32WB_TICKLESS_TIMER) + switch (CONFIG_STM32_TICKLESS_TIMER) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: g_tickless.base = STM32_TIM1_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: g_tickless.base = STM32_TIM2_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: g_tickless.base = STM32_TIM16_BASE; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: g_tickless.base = STM32_TIM17_BASE; break; @@ -393,8 +393,8 @@ void up_timer_initialize(void) /* Get the TC frequency that corresponds to the requested resolution */ g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; - g_tickless.timer = CONFIG_STM32WB_TICKLESS_TIMER; - g_tickless.channel = CONFIG_STM32WB_TICKLESS_CHANNEL; + g_tickless.timer = CONFIG_STM32_TICKLESS_TIMER; + g_tickless.channel = CONFIG_STM32_TICKLESS_CHANNEL; g_tickless.pending = false; g_tickless.period = 0; g_tickless.overflow = 0; diff --git a/arch/arm/src/stm32wb/stm32wb_tim.c b/arch/arm/src/stm32wb/stm32wb_tim.c index 2e7b56cf817..acccf75792a 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim.c +++ b/arch/arm/src/stm32wb/stm32wb_tim.c @@ -67,48 +67,48 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WB_TIM1_PWM) || defined (CONFIG_STM32WB_TIM1_ADC) || \ - defined(CONFIG_STM32WB_TIM1_QE) -# undef CONFIG_STM32WB_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WB_TIM2_PWM) || defined (CONFIG_STM32WB_TIM2_ADC) || \ - defined(CONFIG_STM32WB_TIM2_QE) -# undef CONFIG_STM32WB_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WB_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WB_TIM16_ADC) || \ defined(CONFIG_STM32WB_TIM16_QE) -# undef CONFIG_STM32WB_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WB_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WB_TIM17_ADC) || \ defined(CONFIG_STM32WB_TIM17_QE) -# undef CONFIG_STM32WB_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WB_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) || defined(GPIO_TIM1_CH2OUT) || \ defined(GPIO_TIM1_CH3OUT) || defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) || defined(GPIO_TIM2_CH2OUT) || \ defined(GPIO_TIM2_CH3OUT) || defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) || defined(GPIO_TIM16_CH2OUT) || \ defined(GPIO_TIM16_CH3OUT) || defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) || defined(GPIO_TIM17_CH2OUT) || \ defined(GPIO_TIM17_CH3OUT) || defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -119,8 +119,8 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -221,7 +221,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .dump_regs = stm32_tim_dumpregs, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -229,7 +229,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -238,7 +238,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -247,7 +247,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -465,17 +465,17 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, /* The modes DOWN and UPDOWN are not supported on TIM16 and TIM17. */ -#if defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17) if ((mode == STM32_TIM_MODE_DOWN || mode == STM32_TIM_MODE_UPDOWN)) { -#if defined(CONFIG_STM32WB_TIM16) +#if defined(CONFIG_STM32_TIM16) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM16_BASE) { return -EINVAL; } #endif -#if defined(CONFIG_STM32WB_TIM17) +#if defined(CONFIG_STM32_TIM17) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM17_BASE) { return -EINVAL; @@ -496,7 +496,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, val = GTIM_CR1_CEN | GTIM_CR1_ARPE; break; -#if defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) case STM32_TIM_MODE_DOWN: val = GTIM_CR1_CEN | GTIM_CR1_ARPE | TIM_1_2_CR1_DIR; break; @@ -522,7 +522,7 @@ static int stm32_tim_setmode(struct stm32_tim_dev_s *dev, stm32_tim_reload_counter(dev); stm32_putreg16(dev, STM32_TIM_CR1_OFFSET, val); -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 /* Advanced registers require Main Output Enable */ if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE) @@ -563,25 +563,25 @@ static int stm32_tim_setfreq(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -680,25 +680,25 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, uint32_t freq) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -753,25 +753,25 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -818,7 +818,7 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) /* TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return counter; @@ -836,7 +836,7 @@ static uint32_t stm32_tim_getwidth(struct stm32_tim_dev_s *dev) { /* Only TIM2 is a 32-bit timer. */ -#if defined(CONFIG_STM32WB_TIM2) +#if defined(CONFIG_STM32_TIM2) if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM2_BASE) { return 32; @@ -913,7 +913,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -946,7 +946,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -979,7 +979,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -994,7 +994,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1092,25 +1092,25 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1192,28 +1192,28 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1251,25 +1251,25 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1286,4 +1286,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32WB_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c index 37e35b0f985..38e8db5b4aa 100644 --- a/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c +++ b/arch/arm/src/stm32wb/stm32wb_tim_lowerhalf.c @@ -37,8 +37,8 @@ #include "stm32wb_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WB_TIM1) || defined(CONFIG_STM32WB_TIM2) || \ - defined(CONFIG_STM32WB_TIM16) || defined(CONFIG_STM32WB_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM16) || defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -103,7 +103,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -111,7 +111,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -119,7 +119,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -127,7 +127,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -426,25 +426,25 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32WB_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WB_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32wb/stm32wb_timerisr.c b/arch/arm/src/stm32wb/stm32wb_timerisr.c index 7a9f118a595..ea28a500667 100644 --- a/arch/arm/src/stm32wb/stm32wb_timerisr.c +++ b/arch/arm/src/stm32wb/stm32wb_timerisr.c @@ -56,9 +56,9 @@ * And I don't know now to re-configure it yet */ -#undef CONFIG_STM32WB_SYSTICK_HCLKd8 +#undef CONFIG_STM32_SYSTICK_HCLKd8 -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1) #else # define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1) @@ -121,7 +121,7 @@ void up_timer_initialize(void) #if 0 /* Does not work. Comes up with HCLK source and I can't change it */ regval = getreg32(NVIC_SYSTICK_CTRL); -#ifdef CONFIG_STM32WB_SYSTICK_HCLKd8 +#ifdef CONFIG_STM32_SYSTICK_HCLKd8 regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE; #else regval |= NVIC_SYSTICK_CTRL_CLKSOURCE; diff --git a/arch/arm/src/stm32wb/stm32wb_uart.h b/arch/arm/src/stm32wb/stm32wb_uart.h index 2fd4f3019d1..8733ba88da4 100644 --- a/arch/arm/src/stm32wb/stm32wb_uart.h +++ b/arch/arm/src/stm32wb/stm32wb_uart.h @@ -39,28 +39,28 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32WB_LPUART1) -# undef CONFIG_STM32WB_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WB_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WB_USART1) -# undef CONFIG_STM32WB_USART1_SERIALDRIVER -# undef CONFIG_STM32WB_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WB_LPUART1) || defined(CONFIG_STM32WB_USART1) +#if defined(CONFIG_STM32_LPUART1) || defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WB_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 @@ -82,11 +82,11 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WB_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WB_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif @@ -109,9 +109,9 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WB_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WB_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig index c127e72875f..d1a1619b32a 100644 --- a/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig +++ b/boards/arm/stm32wb/flipperzero/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="flipperzero" CONFIG_ARCH_BOARD_FLIPPERZERO=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_ST7565_MIRROR_Y=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_SPI2=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c index 334cf54abbe..2f549b32aac 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_boot.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -183,7 +183,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32_blehci_initialize(); diff --git a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c index 9e4e5fd13be..fedf459ecee 100644 --- a/boards/arm/stm32wb/flipperzero/src/stm32_spi.c +++ b/boards/arm/stm32wb/flipperzero/src/stm32_spi.c @@ -85,7 +85,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32WB_SPI2 +#ifdef CONFIG_STM32_SPI2 void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { #ifdef CONFIG_LCD_ST7565 diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig index ff3325b96d8..cb0bc5bb913 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/ble/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -41,11 +42,11 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig index 7e9dcb33872..73b3510b415 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nimble/defconfig @@ -13,6 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -46,11 +47,11 @@ CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y -CONFIG_STM32WB_BLE=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_BLE=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig index 0738f6cea58..cdd024ed73b 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig +++ b/boards/arm/stm32wb/nucleo-wb55rg/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-wb55rg" CONFIG_ARCH_BOARD_NUCLEO_WB55RG=y CONFIG_ARCH_CHIP="stm32wb" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WB55RG=y CONFIG_ARCH_CHIP_STM32WB=y CONFIG_ARCH_INTERRUPTSTACK=2048 @@ -30,10 +31,10 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32WB_DISABLE_IDLE_SLEEP_DURING_DEBUG=y -CONFIG_STM32WB_DMA1=y -CONFIG_STM32WB_PWR=y -CONFIG_STM32WB_USART1=y +CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_STM32_DMA1=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TESTING_OSTEST=y diff --git a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c index 140f2dbb255..ff849aff0db 100644 --- a/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c +++ b/boards/arm/stm32wb/nucleo-wb55rg/src/stm32_boot.c @@ -47,7 +47,7 @@ # include "stm32wb_rtc.h" #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE # include "stm32wb_blehci.h" #endif @@ -164,7 +164,7 @@ void board_late_initialize(void) } #endif -#ifdef CONFIG_STM32WB_BLE +#ifdef CONFIG_STM32_BLE /* Initialize and register BLE HCI driver */ stm32_blehci_initialize(); From 0d783007003a70af934b90b2a051e37b5f6b3d04 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 14:28:43 +0200 Subject: [PATCH 093/268] !arch/stm32wl5: use common STM32 Kconfig symbols BREAKING CHANGE: STM32WL5 Kconfig symbols were renamed from CONFIG_STM32WL5_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 1 + arch/arm/include/stm32wl5/chip.h | 6 +- arch/arm/include/stm32wl5/irq.h | 2 +- arch/arm/src/stm32wl5/CMakeLists.txt | 2 +- arch/arm/src/stm32wl5/Kconfig | 394 +----------------- arch/arm/src/stm32wl5/Make.defs | 2 +- .../src/stm32wl5/hardware/stm32wl5_flash.h | 68 +-- arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_allocateheap.c | 6 +- arch/arm/src/stm32wl5/stm32wl5_exti.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_flash.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_gpio.h | 2 +- arch/arm/src/stm32wl5/stm32wl5_idle.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_ipcc.h | 34 +- arch/arm/src/stm32wl5/stm32wl5_lse.c | 20 +- arch/arm/src/stm32wl5/stm32wl5_rcc.c | 74 ++-- arch/arm/src/stm32wl5/stm32wl5_rcc.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_serial.c | 68 +-- arch/arm/src/stm32wl5/stm32wl5_spi.c | 100 ++--- arch/arm/src/stm32wl5/stm32wl5_spi.h | 8 +- arch/arm/src/stm32wl5/stm32wl5_start.c | 2 +- arch/arm/src/stm32wl5/stm32wl5_tim.c | 246 +++++------ .../arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c | 56 +-- arch/arm/src/stm32wl5/stm32wl5_uart.h | 54 +-- boards/arm/stm32wl5/nucleo-wl55jc/Kconfig | 12 +- .../nucleo-wl55jc/configs/demo/defconfig | 3 +- .../nucleo-wl55jc/configs/fb/defconfig | 9 +- .../nucleo-wl55jc/configs/nsh/defconfig | 3 +- .../stm32wl5/nucleo-wl55jc/src/stm32_boot.c | 2 +- .../stm32wl5/nucleo-wl55jc/src/stm32_spi.c | 16 +- 30 files changed, 427 insertions(+), 779 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2a74fa07038..36c1510839b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -750,6 +750,7 @@ config ARCH_CHIP_STM32WB config ARCH_CHIP_STM32WL5 bool "STMicro STM32 WL5" + select ARCH_CHIP_STM32 select ARCH_CORTEXM4 select ARCH_HAVE_MPU select ARCH_HAVE_FETCHADD diff --git a/arch/arm/include/stm32wl5/chip.h b/arch/arm/include/stm32wl5/chip.h index 48c3f837a6b..95761ec558f 100644 --- a/arch/arm/include/stm32wl5/chip.h +++ b/arch/arm/include/stm32wl5/chip.h @@ -33,14 +33,14 @@ * Pre-processor Prototypes ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX) +#if defined(CONFIG_STM32_STM32WL5XXX) # define STM32_SRAM1_SIZE (32*1024) /* 32kB SRAM1 on AHB bus Matrix */ # define STM32_SRAM2_SIZE (32*1024) /* 32kB SRAM2 on AHB bus Matrix */ #else # error "Unsupported STM32L5 chip" #endif -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # define STM32_NATIM 1 /* One advanced timer TIM1 */ # define STM32_NGTIM32 1 /* 32-bit general timer TIM2 with DMA */ # define STM32_NGTIM16 2 /* 16-bit general timers TIM16 and 17 with DMA */ @@ -56,7 +56,7 @@ # define STM32_NDAC 1 /* DAC1 */ # define STM32_NCRC 1 /* CRC1 */ # define STM32_NCOMP 1 /* COMP1 */ -#endif /* CONFIG_STM32WL5_STM32WL5XXX */ +#endif /* CONFIG_STM32_STM32WL5XXX */ /* NVIC priority levels *****************************************************/ diff --git a/arch/arm/include/stm32wl5/irq.h b/arch/arm/include/stm32wl5/irq.h index 08bbc522c55..500a3b957c3 100644 --- a/arch/arm/include/stm32wl5/irq.h +++ b/arch/arm/include/stm32wl5/irq.h @@ -69,7 +69,7 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # include #else # error "Unsupported STM32 L5 chip" diff --git a/arch/arm/src/stm32wl5/CMakeLists.txt b/arch/arm/src/stm32wl5/CMakeLists.txt index 86a13b68e1e..cfee3e8c42e 100644 --- a/arch/arm/src/stm32wl5/CMakeLists.txt +++ b/arch/arm/src/stm32wl5/CMakeLists.txt @@ -42,7 +42,7 @@ set(SRCS stm32wl5_timerisr.c stm32wl5_spi.c) -if(CONFIG_STM32WL5_IPCC) +if(CONFIG_STM32_IPCC) list(APPEND SRCS stm32wl5_ipcc.c) endif() diff --git a/arch/arm/src/stm32wl5/Kconfig b/arch/arm/src/stm32wl5/Kconfig index 99e5a6cd68b..9ef01fbd783 100644 --- a/arch/arm/src/stm32wl5/Kconfig +++ b/arch/arm/src/stm32wl5/Kconfig @@ -7,6 +7,12 @@ if ARCH_CHIP_STM32WL5 comment "STM32WL5 Configuration Options" +config STM32_WL5_PERIPHERALS + bool + default ARCH_CHIP_STM32WL5 + select STM32_HAVE_SYSCFG + select STM32_HAVE_IPCC + choice prompt "STM32 WL5 Chip Selection" default ARCH_CHIP_STM32WL55JC_CPU1 @@ -14,396 +20,34 @@ choice config ARCH_CHIP_STM32WL55JC_CPU1 bool "STM32WL55JC (cpu1)" - select STM32WL5_STM32WL5XXX_CPU1 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU1 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M4 (cpu1), 256kiB FLASH, 64kiB SRAM config ARCH_CHIP_STM32WL55JC_CPU2 bool "STM32WL55JC (cpu2)" - select STM32WL5_STM32WL5XXX_CPU2 - select STM32WL5_STM32WL5XXX - select STM32WL5_FLASH_CONFIG_C + select STM32_STM32WL5XXX_CPU2 + select STM32_STM32WL5XXX + select STM32_FLASH_CONFIG_C ---help--- STM32 WL5 Cortex M0 (cpu2), 256kiB FLASH, 64kiB SRAM - endchoice # STM32 WL5 Chip Selection # Chip product lines -config STM32WL5_STM32WL5XXX +config STM32_STM32WL5XXX bool -config STM32WL5_STM32WL5XXX_CPU1 +config STM32_STM32WL5XXX_CPU1 bool default y - select STM32WL5_HAVE_USART1 - select STM32WL5_HAVE_USART2 - select STM32WL5_HAVE_LPUART1 - select STM32WL5_HAVE_SPI1 - select STM32WL5_HAVE_SPI2S2 - - -comment "STM32WL5 Peripherals" - -menu "STM32WL5 Peripheral Support" - -choice - prompt "Override Flash Size Designator" - depends on ARCH_CHIP_STM32WL5 - default STM32WL5_FLASH_OVERRIDE_DEFAULT - ---help--- - STM32WL5 series parts numbering (sans the package type) ends with a letter - that designates the FLASH size. - - Designator Size in KiB - 8 64 - B 128 - C 256 - E 512 - G 1024 - I 2048 - - This configuration option defaults to using the configuration based on that designator - or the default smaller size if there is no last character designator is present in the - STM32 Chip Selection. - - Examples: - If the STM32WL55JC is chosen, the Flash configuration would be 'C', if a variant of - the part with a 1024 KiB Flash is released in the future one could simply select - the 'G' designator here. - - If an STM32WL5xxx Series parts is chosen the default Flash configuration will be set - herein and can be changed. - -config STM32WL5_FLASH_OVERRIDE_DEFAULT - bool "Default" - -config STM32WL5_FLASH_OVERRIDE_8 - bool "8 64 KB" - -config STM32WL5_FLASH_OVERRIDE_B - bool "B 128 KB" - -config STM32WL5_FLASH_OVERRIDE_C - bool "C 256 KB" - -config STM32WL5_FLASH_OVERRIDE_E - bool "E 512 KB" - -config STM32WL5_FLASH_OVERRIDE_G - bool "G 1024 KB" - -endchoice # "Override Flash Size Designator" - -# Flash configurations - -config STM32WL5_FLASH_CONFIG_8 - bool - default n - -config STM32WL5_FLASH_CONFIG_B - bool - default n - -config STM32WL5_FLASH_CONFIG_C - bool - default n - -config STM32WL5_FLASH_CONFIG_E - bool - default n - -config STM32WL5_FLASH_CONFIG_G - bool - default n - -# These "hidden" settings determine whether a peripheral option is available -# for the selected MCU - -config STM32WL5_HAVE_USART1 - bool - default n - -config STM32WL5_HAVE_USART2 - bool - default n - -config STM32WL5_HAVE_LPUART1 - bool - default n - -config STM32WL5_HAVE_SPI1 - bool - default n - -config STM32WL5_HAVE_SPI2S2 - bool - default n - -# These "hidden" settings are the OR of individual peripheral selections -# indicating that the general capability is required. - -config STM32WL5_USART - bool - default n - -config STM32WL5_SPI - bool - default n - -config STM32WL5_SPI_DMA - bool - default n - -# These are the peripheral selections proper - -comment "APB1 Peripherals" - -config STM32WL5_USART2 - bool "USART2" - default n - depends on STM32WL5_HAVE_USART2 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_LPUART1 - bool "LPUART1" - default n - depends on STM32WL5_HAVE_LPUART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI2S2 - bool "SPI2S2" - default n - depends on STM32WL5_HAVE_SPI2S2 - select STM32WL5_SPI - -comment "APB2 Peripherals" - -config STM32WL5_SYSCFG - bool "SYSCFG" - default y - -config STM32WL5_USART1 - bool "USART1" - default n - depends on STM32WL5_HAVE_USART1 - select ARCH_HAVE_SERIAL_TERMIOS - select STM32WL5_USART - -config STM32WL5_SPI1 - bool "SPI1" - default n - depends on STM32WL5_HAVE_SPI1 - select STM32WL5_SPI - -comment "AHB3 Peripherals" - -config STM32WL5_IPCC - bool "IPCC" - select IPCC - default n - ---help--- - IPCC - Inter Processor Communication Controller. A very simple - character device stream driver to exchange data between - CM0 and CM4. - -endmenu # STM32WL5 Peripheral Support - - -config STM32WL5_SERIALDRIVER - bool - -menu "[LP]U[S]ART Configuration" - depends on STM32WL5_USART - -choice - prompt "USART1 Driver Configuration" - default STM32WL5_USART1_SERIALDRIVER - depends on STM32WL5_USART1 - -config STM32WL5_USART1_SERIALDRIVER - bool "Standard serial driver" - select USART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART1 Driver Configuration - -choice - prompt "USART2 Driver Configuration" - default STM32WL5_USART2_SERIALDRIVER - depends on STM32WL5_USART2 - -config STM32WL5_USART2_SERIALDRIVER - bool "Standard serial driver" - select USART2_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # USART2 Driver Configuration - -choice - prompt "LPUART1 Driver Configuration" - default STM32WL5_LPUART1_SERIALDRIVER - depends on STM32WL5_LPUART1 - -config STM32WL5_LPUART1_SERIALDRIVER - bool "Standard serial driver" - select LPUART1_SERIALDRIVER - select STM32WL5_SERIALDRIVER - -endchoice # LPUART1 Driver Configuration - -endmenu # [LP]U[S]ART Configuration - -menu "SPI Configuration" - depends on STM32WL5_SPI - -config STM32WL5_SPI_INTERRUPTS - bool "Interrupt driver SPI" - default n - ---help--- - Select to enable interrupt driven SPI support. Non-interrupt-driven, - poll-waiting is recommended if the interrupt rate would be to high in - the interrupt driven case. - -config STM32WL5_SPI1_DMA - bool "SPI1 DMA" - default n - depends on STM32WL5_SPI1 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI1 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI1_DMA_BUFFER - int "SPI1 DMA buffer size" - default 0 - depends on STM32WL5_SPI1_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI1. - -config STM32WL5_SPI_DMATHRESHOLD - int "SPI DMA threshold" - default 4 - depends on STM32WL5_SPI_DMA - ---help--- - When SPI DMA is enabled, small DMA transfers will still be performed - by polling logic. But we need a threshold value to determine what - is small. - -config STM32WL5_SPI2S2_DMA - bool "SPI2S2 DMA" - default n - depends on STM32WL5_SPI2 && !STM32WL5_SPI_INTERRUPT - select STM32WL5_SPI_DMA - ---help--- - Use DMA to improve SPI2S2 transfer performance. Cannot be used with STM32WL5_SPI_INTERRUPT. - -config STM32WL5_SPI2S2_DMA_BUFFER - int "SPI2S2 DMA buffer size" - default 0 - depends on STM32WL5_SPI2S2_DMA - ---help--- - Add a properly aligned DMA buffer for RX and TX DMA for SPI2S2. - -endmenu # SPI Configuration - -menu "IPCC Configuration" - depends on STM32WL5_IPCC - -config STM32WL5_IPCC_CHAN1_RX_SIZE - int "Channel 1 RX size" - default 256 - ---help--- - Size of the receive buffer. Another CPU will write to this - buffer and currently running CPU will read from it. - -config STM32WL5_IPCC_CHAN1_TX_SIZE - int "Channel 1 TX size" - default 256 - ---help--- - Size of the send buffer. Another CPU will read from this - buffer and currently running CPU will write to it. - -config STM32WL5_IPCC_CHAN2 - bool "Enable channel 2" - default n - -if STM32WL5_IPCC_CHAN2 - -config STM32WL5_IPCC_CHAN2_RX_SIZE - int "Channel 2 RX size" - default 256 - -config STM32WL5_IPCC_CHAN2_TX_SIZE - int "Channel 2 TX size" - default 256 - -config STM32WL5_IPCC_CHAN3 - bool "Enable channel 3" - default n - -if STM32WL5_IPCC_CHAN3 - -config STM32WL5_IPCC_CHAN3_RX_SIZE - int "Channel 3 RX size" - default 256 - -config STM32WL5_IPCC_CHAN3_TX_SIZE - int "Channel 3 TX size" - default 256 - -config STM32WL5_IPCC_CHAN4 - bool "Enable channel 4" - default n - -if STM32WL5_IPCC_CHAN4 - -config STM32WL5_IPCC_CHAN4_RX_SIZE - int "Channel 4 RX size" - default 256 - -config STM32WL5_IPCC_CHAN4_TX_SIZE - int "Channel 4 TX size" - default 256 - -config STM32WL5_IPCC_CHAN5 - bool "Enable channel 5" - default n - -if STM32WL5_IPCC_CHAN5 - -config STM32WL5_IPCC_CHAN5_RX_SIZE - int "Channel 5 RX size" - default 256 - -config STM32WL5_IPCC_CHAN5_TX_SIZE - int "Channel 5 TX size" - default 256 - -config STM32WL5_IPCC_CHAN6 - bool "Enable channel 6" - default n - -if STM32WL5_IPCC_CHAN6 - -config STM32WL5_IPCC_CHAN6_RX_SIZE - int "Channel 6 RX size" - default 256 - -config STM32WL5_IPCC_CHAN6_TX_SIZE - int "Channel 6 TX size" - default 256 - -endif # STM32WL5_IPCC_CHAN2 -endif # STM32WL5_IPCC_CHAN3 -endif # STM32WL5_IPCC_CHAN4 -endif # STM32WL5_IPCC_CHAN5 -endif # STM32WL5_IPCC_CHAN6 - -endmenu # IPCC Configuration + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_LPUART1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2S2 endif # ARCH_CHIP_STM32WL5 diff --git a/arch/arm/src/stm32wl5/Make.defs b/arch/arm/src/stm32wl5/Make.defs index fc265b697ae..e0df51091d0 100644 --- a/arch/arm/src/stm32wl5/Make.defs +++ b/arch/arm/src/stm32wl5/Make.defs @@ -36,6 +36,6 @@ CHIP_CSRCS += stm32wl5_lse.c stm32wl5_lsi.c stm32wl5_idle.c CHIP_CSRCS += stm32wl5_pwr.c stm32wl5_tim.c stm32wl5_flash.c stm32wl5_timerisr.c CHIP_CSRCS += stm32wl5_spi.c -CSRCS-$(CONFIG_STM32WL5_IPCC) = stm32wl5_ipcc.c +CSRCS-$(CONFIG_STM32_IPCC) = stm32wl5_ipcc.c CHIP_CSRCS += $(CSRCS-y) diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h index e7d57753c2b..cc11030bdd3 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_flash.h @@ -35,7 +35,7 @@ /* Flash size is known from the chip selection: * - * When CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT is set the + * When CONFIG_STM32_FLASH_OVERRIDE_DEFAULT is set the * CONFIG_STM32WL5_FLASH_CONFIG_x selects the default FLASH size based * on the chip part number. This value can be overridden with * CONFIG_STM32WL5_FLASH_OVERRIDE_x. For example: @@ -47,57 +47,57 @@ * STM32WL5xxx has only single bank flash and page size 2KiB */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) && \ - !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_8) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_B) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_C) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_E) && \ - !defined(CONFIG_STM32WL5_FLASH_CONFIG_G) -# define CONFIG_STM32WL5_FLASH_OVERRIDE_E +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_8) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_B) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_C) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_E) && \ + !defined(CONFIG_STM32_FLASH_OVERRIDE_G) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_8) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_B) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_C) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_E) && \ + !defined(CONFIG_STM32_FLASH_CONFIG_G) +# define CONFIG_STM32_FLASH_OVERRIDE_E # warning "Flash size not defined defaulting to 512KiB (E)" #endif /* Override of the Flash has been chosen */ -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) -# undef CONFIG_STM32WL5_FLASH_CONFIG_8 -# undef CONFIG_STM32WL5_FLASH_CONFIG_B -# undef CONFIG_STM32WL5_FLASH_CONFIG_C -# undef CONFIG_STM32WL5_FLASH_CONFIG_E -# undef CONFIG_STM32WL5_FLASH_CONFIG_G -# if defined(CONFIG_STM32WL5_FLASH_OVERRIDE_8) -# define CONFIG_STM32WL5_FLASH_CONFIG_8 -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_B) -# define CONFIG_STM32WL5_FLASH_CONFIG_B -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_C) -# define CONFIG_STM32WL5_FLASH_CONFIG_C -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_E) -# define CONFIG_STM32WL5_FLASH_CONFIG_E -# elif defined(CONFIG_STM32WL5_FLASH_OVERRIDE_G) -# define CONFIG_STM32WL5_FLASH_CONFIG_G +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) +# undef CONFIG_STM32_FLASH_CONFIG_8 +# undef CONFIG_STM32_FLASH_CONFIG_B +# undef CONFIG_STM32_FLASH_CONFIG_C +# undef CONFIG_STM32_FLASH_CONFIG_E +# undef CONFIG_STM32_FLASH_CONFIG_G +# if defined(CONFIG_STM32_FLASH_OVERRIDE_8) +# define CONFIG_STM32_FLASH_CONFIG_8 +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_B) +# define CONFIG_STM32_FLASH_CONFIG_B +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_C) +# define CONFIG_STM32_FLASH_CONFIG_C +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_E) +# define CONFIG_STM32_FLASH_CONFIG_E +# elif defined(CONFIG_STM32_FLASH_OVERRIDE_G) +# define CONFIG_STM32_FLASH_CONFIG_G # endif #endif /* Define the valid configuration */ -#if defined(CONFIG_STM32WL5_FLASH_CONFIG_8) /* 64 kB */ +#if defined(CONFIG_STM32_FLASH_CONFIG_8) /* 64 kB */ # define STM32_FLASH_NPAGES 32 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_B) /* 128 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_B) /* 128 kB */ # define STM32_FLASH_NPAGES 64 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_C) /* 256 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_C) /* 256 kB */ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_E) /* 512 kB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_E) /* 512 kB */ # define STM32_FLASH_NPAGES 256 # define STM32_FLASH_PAGESIZE 2048 -#elif defined(CONFIG_STM32WL5_FLASH_CONFIG_G) /* 1 MB */ +#elif defined(CONFIG_STM32_FLASH_CONFIG_G) /* 1 MB */ # define STM32_FLASH_NPAGES 512 # define STM32_FLASH_PAGESIZE 2048 #else diff --git a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h index aaeac357315..9e3afea3506 100644 --- a/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/hardware/stm32wl5_spi.h @@ -74,7 +74,7 @@ /* Maximum allowed speed as per specifications for all SPIs */ -#if defined(CONFIG_STM32WL5_STM32F4XXX) +#if defined(CONFIG_STM32_STM32F4XXX) # define STM32_SPI_CLK_MAX 37500000UL #else # define STM32_SPI_CLK_MAX 18000000UL diff --git a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c index 162ec9e3e51..29422cc4b0b 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c +++ b/arch/arm/src/stm32wl5/stm32wl5_allocateheap.c @@ -83,11 +83,11 @@ * that we have been asked to add to the heap. */ -#if CONFIG_MM_REGIONS < defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS < defined(CONFIG_STM32_SRAM2_HEAP) + 1 # error "You need more memory manager regions to support selected heap components" #endif -#if CONFIG_MM_REGIONS > defined(CONFIG_STM32WL5_SRAM2_HEAP) + 1 +#if CONFIG_MM_REGIONS > defined(CONFIG_STM32_SRAM2_HEAP) + 1 # warning "CONFIG_MM_REGIONS large enough but I do not know what some of the region(s) are" #endif @@ -264,7 +264,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void arm_addregion(void) { -#ifdef CONFIG_STM32WL5_SRAM2_HEAP +#ifdef CONFIG_STM32_SRAM2_HEAP #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP) diff --git a/arch/arm/src/stm32wl5/stm32wl5_exti.h b/arch/arm/src/stm32wl5/stm32wl5_exti.h index 79308c15432..f3c296dd409 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_exti.h +++ b/arch/arm/src/stm32wl5/stm32wl5_exti.h @@ -141,7 +141,7 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_COMP +#ifdef CONFIG_STM32_COMP int stm32_exti_comp(int cmp, bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_flash.c b/arch/arm/src/stm32wl5/stm32wl5_flash.c index d26cac244cc..40737cbe801 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_flash.c +++ b/arch/arm/src/stm32wl5/stm32wl5_flash.c @@ -50,7 +50,7 @@ #include "stm32wl5_flash.h" #include "arm_internal.h" -#if !defined(CONFIG_STM32WL5_FLASH_OVERRIDE_DEFAULT) +#if !defined(CONFIG_STM32_FLASH_OVERRIDE_DEFAULT) # warning "Flash Configuration has been overridden - make sure it is correct" #endif diff --git a/arch/arm/src/stm32wl5/stm32wl5_gpio.h b/arch/arm/src/stm32wl5/stm32wl5_gpio.h index 6d75dfd10cb..0d0093baef6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_gpio.h +++ b/arch/arm/src/stm32wl5/stm32wl5_gpio.h @@ -39,7 +39,7 @@ #include "chip.h" -#if defined(CONFIG_STM32WL5_STM32WL5XXX) +#if defined(CONFIG_STM32_STM32WL5XXX) # include "hardware/stm32wl5_gpio.h" #else # error "Unsupported STM32WL5 chip" diff --git a/arch/arm/src/stm32wl5/stm32wl5_idle.c b/arch/arm/src/stm32wl5/stm32wl5_idle.c index ec70f83270f..ab1fb4d073d 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_idle.c +++ b/arch/arm/src/stm32wl5/stm32wl5_idle.c @@ -88,7 +88,7 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power. */ -#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32WL5_DISABLE_IDLE_SLEEP_DURING_DEBUG)) +#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG)) BEGIN_IDLE(); asm("WFI"); END_IDLE(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h index bbee1c57eb8..bd420571efc 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_ipcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_ipcc.h @@ -41,17 +41,17 @@ /* channel 1 configuration **************************************************/ -#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_RX_SIZE) -#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN1_TX_SIZE) +#define IPCC_CHAN1_RX_SIZE (CONFIG_STM32_IPCC_CHAN1_RX_SIZE) +#define IPCC_CHAN1_TX_SIZE (CONFIG_STM32_IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1_START (IPCC_START) #define IPCC_CHAN1_SIZE (IPCC_CHAN1_RX_SIZE + IPCC_CHAN1_TX_SIZE) #define IPCC_CHAN1 (1) /* channel 2 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN2) -# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_RX_SIZE) -# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN2_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN2) +# define IPCC_CHAN2_RX_SIZE (CONFIG_STM32_IPCC_CHAN2_RX_SIZE) +# define IPCC_CHAN2_TX_SIZE (CONFIG_STM32_IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2_START (IPCC_CHAN1_START + IPCC_CHAN1_SIZE) # define IPCC_CHAN2_SIZE (IPCC_CHAN2_RX_SIZE + IPCC_CHAN2_TX_SIZE) # define IPCC_CHAN2 (1) @@ -62,9 +62,9 @@ /* channel 3 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN3) -# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_RX_SIZE) -# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN3_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN3) +# define IPCC_CHAN3_RX_SIZE (CONFIG_STM32_IPCC_CHAN3_RX_SIZE) +# define IPCC_CHAN3_TX_SIZE (CONFIG_STM32_IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3_START (IPCC_CHAN2_START + IPCC_CHAN2_SIZE) # define IPCC_CHAN3_SIZE (IPCC_CHAN3_RX_SIZE + IPCC_CHAN3_TX_SIZE) # define IPCC_CHAN3 (1) @@ -75,9 +75,9 @@ /* channel 4 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN4) -# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_RX_SIZE) -# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN4_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN4) +# define IPCC_CHAN4_RX_SIZE (CONFIG_STM32_IPCC_CHAN4_RX_SIZE) +# define IPCC_CHAN4_TX_SIZE (CONFIG_STM32_IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4_START (IPCC_CHAN3_START + IPCC_CHAN3_SIZE) # define IPCC_CHAN4_SIZE (IPCC_CHAN4_RX_SIZE + IPCC_CHAN4_TX_SIZE) # define IPCC_CHAN4 (1) @@ -88,9 +88,9 @@ /* channel 5 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN5) -# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_RX_SIZE) -# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN5_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN5) +# define IPCC_CHAN5_RX_SIZE (CONFIG_STM32_IPCC_CHAN5_RX_SIZE) +# define IPCC_CHAN5_TX_SIZE (CONFIG_STM32_IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5_START (IPCC_CHAN4_START + IPCC_CHAN4_SIZE) # define IPCC_CHAN5_SIZE (IPCC_CHAN5_RX_SIZE + IPCC_CHAN5_TX_SIZE) # define IPCC_CHAN5 (1) @@ -101,9 +101,9 @@ /* channel 6 configuration **************************************************/ -#if defined(CONFIG_STM32WL5_IPCC_CHAN6) -# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_RX_SIZE) -# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32WL5_IPCC_CHAN6_TX_SIZE) +#if defined(CONFIG_STM32_IPCC_CHAN6) +# define IPCC_CHAN6_RX_SIZE (CONFIG_STM32_IPCC_CHAN6_RX_SIZE) +# define IPCC_CHAN6_TX_SIZE (CONFIG_STM32_IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6_START (IPCC_CHAN5_START + IPCC_CHAN5_SIZE) # define IPCC_CHAN6_SIZE (IPCC_CHAN6_RX_SIZE + IPCC_CHAN6_TX_SIZE) # define IPCC_CHAN6 (1) diff --git a/arch/arm/src/stm32wl5/stm32wl5_lse.c b/arch/arm/src/stm32wl5/stm32wl5_lse.c index 2225bf11e1c..4ab6997b283 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_lse.c +++ b/arch/arm/src/stm32wl5/stm32wl5_lse.c @@ -43,9 +43,9 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, #define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC) -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY -# if CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ - CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY +# if CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \ + CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY > 3 # error "Invalid LSE drive capability setting" # endif #endif @@ -54,7 +54,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY static const uint32_t drives[4] = { RCC_BDCR_LSEDRV_LOW, @@ -81,7 +81,7 @@ void stm32_rcc_enablelse(void) int writable; uint32_t regval; volatile int32_t timeout; -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY volatile int32_t drive = 0; #endif @@ -109,19 +109,19 @@ void stm32_rcc_enablelse(void) regval |= RCC_BDCR_LSEON; -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY /* Set start-up drive capability for LSE oscillator. LSE must be OFF * to change drive strength. */ regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); - regval |= CONFIG_STM32WL5_RTC_LSECLOCK_START_DRV_CAPABILITY << + regval |= CONFIG_STM32_RTC_LSECLOCK_START_DRV_CAPABILITY << RCC_BDCR_LSEDRV_SHIFT; putreg32(regval, STM32_RCC_BDCR); regval |= RCC_BDCR_LSEON; #endif -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY do { regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON); @@ -149,7 +149,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32WL5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY if (timeout != 0) { break; @@ -178,7 +178,7 @@ void stm32_rcc_enablelse(void) } } -#ifdef CONFIG_STM32WL5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY +#ifdef CONFIG_STM32_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY /* Set running drive capability for LSE oscillator. */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.c b/arch/arm/src/stm32wl5/stm32wl5_rcc.c index 78699514946..832c71e1ff0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.c +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.c @@ -74,7 +74,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32WL5_PWR) && defined(CONFIG_STM32WL5_RTC) +#if defined(CONFIG_STM32_PWR) && defined(CONFIG_STM32_RTC) static inline void stm32_rcc_resetbkp(void) { bool init_stat; @@ -139,7 +139,7 @@ static inline void stm32_rcc_resetbkp(void) * and enable peripheral clocking for all peripherals enabled in the NuttX * configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -162,7 +162,7 @@ void stm32_clockconfig(void) rcc_resetbkp(); #endif -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -201,19 +201,19 @@ static void stm32_rcc_enableahb1(void) regval = getreg32(STM32_RCC_AHB1ENR); -#ifdef CONFIG_STM32WL5_DMA1 +#ifdef CONFIG_STM32_DMA1 /* DMA 1 clock enable */ regval |= RCC_AHB1ENR_DMA1EN; #endif -#ifdef CONFIG_STM32WL5_DMA2 +#ifdef CONFIG_STM32_DMA2 /* DMA 2 clock enable */ regval |= RCC_AHB1ENR_DMA2EN; #endif -#ifdef CONFIG_STM32WL5_CRC +#ifdef CONFIG_STM32_CRC /* CRC clock enable */ regval |= RCC_AHB1ENR_CRCEN; @@ -277,13 +277,13 @@ static inline void stm32_rcc_enableahb3(void) regval = getreg32(STM32_RCC_AHB3ENR); -#ifdef CONFIG_STM32WL5_AES +#ifdef CONFIG_STM32_AES /* Cryptographic modules clock enable */ regval |= RCC_AHB2ENR_AESEN; #endif -#ifdef CONFIG_STM32WL5_RNG +#ifdef CONFIG_STM32_RNG /* Random number generator clock enable */ regval |= RCC_AHB2ENR_RNGEN; @@ -295,7 +295,7 @@ static inline void stm32_rcc_enableahb3(void) regval |= RCC_AHB3ENR_FLASHEN; #endif -#ifdef CONFIG_STM32WL5_IPCC +#ifdef CONFIG_STM32_IPCC /* IPCC interface clock enable */ regval |= RCC_AHB3ENR_IPCCEN; @@ -322,49 +322,49 @@ static inline void stm32_rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR1); -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 /* TIM2 clock enable */ regval |= RCC_APB1ENR1_TIM2EN; #endif -#ifdef CONFIG_STM32WL5_SPI2 +#ifdef CONFIG_STM32_SPI2 /* SPI2 clock enable */ regval |= RCC_APB1ENR1_SPI2EN; #endif -#ifdef CONFIG_STM32WL5_USART2 +#ifdef CONFIG_STM32_USART2 /* USART 2 clock enable */ regval |= RCC_APB1ENR1_USART2EN; #endif -#ifdef CONFIG_STM32WL5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* I2C1 clock enable */ regval |= RCC_APB1ENR1_I2C1EN; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* I2C2 clock enable */ regval |= RCC_APB1ENR1_I2C2EN; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* I2C3 clock enable */ regval |= RCC_APB1ENR1_I2C3EN; #endif -#if defined (CONFIG_STM32WL5_DAC1) +#if defined (CONFIG_STM32_DAC1) /* DAC interface clock enable */ regval |= RCC_APB1ENR1_DAC1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM1 +#ifdef CONFIG_STM32_LPTIM1 /* Low power timer 1 clock enable */ regval |= RCC_APB1ENR1_LPTIM1EN; @@ -376,19 +376,19 @@ static inline void stm32_rcc_enableapb1(void) regval = getreg32(STM32_RCC_APB1ENR2); -#ifdef CONFIG_STM32WL5_LPUART1 +#ifdef CONFIG_STM32_LPUART1 /* Low power uart clock enable */ regval |= RCC_APB1ENR2_LPUART1EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM2 +#ifdef CONFIG_STM32_LPTIM2 /* Low power timer 2 clock enable */ regval |= RCC_APB1ENR2_LPTIM2EN; #endif -#ifdef CONFIG_STM32WL5_LPTIM3 +#ifdef CONFIG_STM32_LPTIM3 /* Low power timer 3 clock enable */ regval |= RCC_APB1ENR2_LPTIM3EN; @@ -415,37 +415,37 @@ static inline void stm32_rcc_enableapb2(void) regval = getreg32(STM32_RCC_APB2ENR); -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* ADC clock enable */ regval |= RCC_AHB2ENR_ADC1EN; #endif -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 /* TIM1 clock enable */ regval |= RCC_APB2ENR_TIM1EN; #endif -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* SPI1 clock enable */ regval |= RCC_APB2ENR_SPI1EN; #endif -#ifdef CONFIG_STM32WL5_USART1 +#ifdef CONFIG_STM32_USART1 /* USART1 clock enable */ regval |= RCC_APB2ENR_USART1EN; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM16EN; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 /* TIM16 clock enable */ regval |= RCC_APB2ENR_TIM17EN; @@ -474,17 +474,17 @@ static inline void stm32_rcc_enableccip(void) regval = getreg32(STM32_RCC_CCIPR); #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C1 +#ifdef CONFIG_STM32_I2C1 /* Select HSI16 as I2C1 clock source. */ regval |= RCC_CCIPR_I2C1SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C2 +#ifdef CONFIG_STM32_I2C2 /* Select HSI16 as I2C2 clock source. */ regval |= RCC_CCIPR_I2C2SEL_HSI; #endif -#ifdef CONFIG_STM32WL5_I2C3 +#ifdef CONFIG_STM32_I2C3 /* Select HSI16 as I2C3 clock source. */ regval |= RCC_CCIPR_I2C3SEL_HSI; @@ -500,13 +500,13 @@ static inline void stm32_rcc_enableccip(void) regval |= STM32_CLK48_SEL; #endif -#if defined(CONFIG_STM32WL5_ADC1) +#if defined(CONFIG_STM32_ADC1) /* Select SYSCLK as ADC clock source */ regval |= RCC_CCIPR_ADCSEL_SYSCLK; #endif -#ifdef CONFIG_STM32WL5_DFSDM1 +#ifdef CONFIG_STM32_DFSDM1 /* Select SYSCLK as DFSDM clock source */ /* RM0394 Rev 3, p. 525 is confused about DFSDM clock source. @@ -523,7 +523,7 @@ static inline void stm32_rcc_enableccip(void) /* I2C4 alone has their clock selection in CCIPR2 register. */ #if defined(STM32_I2C_USE_HSI16) -#ifdef CONFIG_STM32WL5_I2C4 +#ifdef CONFIG_STM32_I2C4 regval = getreg32(STM32_RCC_CCIPR2); /* Select HSI16 as I2C4 clock source. */ @@ -548,7 +548,7 @@ static inline void stm32_rcc_enableccip(void) * stm32_clockconfig() * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -563,7 +563,7 @@ static inline void stm32_rcc_enableccip(void) #ifdef CONFIG_PM void stm32_clockenable(void) { -#if defined(CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG) +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) /* Invoke Board Custom Clock Configuration */ @@ -605,7 +605,7 @@ void stm32_rcc_enableperipherals(void) * power clocking modes! ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void) { uint32_t regval; @@ -759,7 +759,7 @@ void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_STM32WL5_RTC_HSECLOCK +#ifdef CONFIG_STM32_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -849,7 +849,7 @@ void stm32_stdclockconfig(void) { } -#if defined(CONFIG_STM32WL5_IWDG) || defined(CONFIG_STM32WL5_RTC_LSICLOCK) +#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_STM32_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); diff --git a/arch/arm/src/stm32wl5/stm32wl5_rcc.h b/arch/arm/src/stm32wl5/stm32wl5_rcc.h index 6524b3232af..eea97c6d240 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_rcc.h +++ b/arch/arm/src/stm32wl5/stm32wl5_rcc.h @@ -96,7 +96,7 @@ static inline void stm32_mcoconfig(uint32_t source) * and enable peripheral clocking for all periperipherals enabled in the * NuttX configuration file. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * @@ -119,7 +119,7 @@ void stm32_clockconfig(void); * ****************************************************************************/ -#ifdef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_board_clockconfig(void); #endif @@ -134,7 +134,7 @@ void stm32_board_clockconfig(void); * ****************************************************************************/ -#ifndef CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG +#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG void stm32_stdclockconfig(void); #endif @@ -151,7 +151,7 @@ void stm32_stdclockconfig(void); * stm32_clockconfig(): It does not reset any devices, and it does not * reset the currently enabled peripheral clocks. * - * If CONFIG_ARCH_BOARD_STM32WL5_CUSTOM_CLOCKCONFIG is defined, then + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then * clocking will be enabled by an externally provided, board-specific * function called stm32_board_clockconfig(). * diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 3bc1cb4ab5f..75705535333 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -82,8 +82,8 @@ */ # if defined(CONFIG_USART2_RXDMA) -# if !defined(CONFIG_STM32WL5_DMA1) && !defined(CONFIG_STM32WL5_DMAMUX) -# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32WL5_DMA1 +# if !defined(CONFIG_STM32_DMA1) && !defined(CONFIG_STM32_DMAMUX) +# error STM32WL5 USART2/3 receive DMA requires CONFIG_STM32_DMA1 # endif # endif @@ -98,7 +98,7 @@ /* UART2-5 have no alternate channels without DMAMUX */ -# ifndef CONFIG_STM32WL5_HAVE_DMAMUX +# ifndef CONFIG_STM32_HAVE_DMAMUX # define DMAMAP_USART2_RX DMACHAN_USART2_RX # endif @@ -116,11 +116,11 @@ * can be individually invalidated. */ -# if !defined(CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE) || \ - CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE == 0 +# if !defined(CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE) || \ + CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE == 0 # define RXDMA_BUFFER_SIZE 32 # else -# define RXDMA_BUFFER_SIZE ((CONFIG_STM32WL5_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) +# define RXDMA_BUFFER_SIZE ((CONFIG_STM32_SERIAL_RXDMA_BUFFER_SIZE + 31) & ~31) # endif /* DMA priority */ @@ -152,8 +152,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32WL5_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32WL5_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif #if defined(CONFIG_PM) # define PM_IDLE_DOMAIN 0 /* Revisit */ @@ -170,7 +170,7 @@ * See stm32wl5serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -366,7 +366,7 @@ static const struct uart_ops_s g_uart_dma_ops = /* I/O buffers */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; static char g_lpuart1txbuffer[CONFIG_LPUART1_TXBUFSIZE]; # ifdef CONFIG_LPUART1_RXDMA @@ -374,7 +374,7 @@ static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; # ifdef CONFIG_USART1_RXDMA @@ -382,7 +382,7 @@ static char g_usart1rxfifo[RXDMA_BUFFER_SIZE]; # endif #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE]; static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE]; # ifdef CONFIG_USART2_RXDMA @@ -392,7 +392,7 @@ static char g_usart2rxfifo[RXDMA_BUFFER_SIZE]; /* This describes the state of the STM32 USART1 ports. */ -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER static struct stm32_serial_s g_lpuart1priv = { .dev = @@ -452,7 +452,7 @@ static struct stm32_serial_s g_lpuart1priv = }; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -514,7 +514,7 @@ static struct stm32_serial_s g_usart1priv = /* This describes the state of the STM32 USART2 port. */ -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER static struct stm32_serial_s g_usart2priv = { .dev = @@ -579,13 +579,13 @@ static struct stm32_serial_s g_usart2priv = static struct stm32_serial_s * const g_uart_devs[STM32_NLPUART + STM32_NUSART] = { -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER [0] = &g_lpuart1priv, #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [1] = &g_usart1priv, #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER [2] = &g_usart2priv, #endif }; @@ -892,7 +892,7 @@ static void stm32wl5serial_setformat(struct uart_dev_s *dev) regval = stm32wl5serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -1096,19 +1096,19 @@ static void stm32wl5serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifdef CONFIG_STM32_LPUART1_SERIALDRIVER case STM32_LPUART1_BASE: rcc_en = RCC_APB1ENR2_LPUART1EN; regaddr = STM32_RCC_APB1ENR2; break; #endif -#ifdef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr = STM32_RCC_APB2ENR; break; #endif -#ifdef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifdef CONFIG_STM32_USART2_SERIALDRIVER case STM32_USART2_BASE: rcc_en = RCC_APB1ENR1_USART2EN; regaddr = STM32_RCC_APB1ENR1; @@ -1177,7 +1177,7 @@ static int stm32wl5serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32WL5_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -1529,8 +1529,8 @@ static int stm32wl5serial_interrupt(int irq, void *context, /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32WL5_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32WL5_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1674,7 +1674,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WL5_USART_SINGLEWIRE +#ifdef CONFIG_STM32_USART_SINGLEWIRE case TIOCSSINGLEWIRE: { uint32_t cr1; @@ -1752,7 +1752,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WL5_USART_INVERT +#ifdef CONFIG_STM32_USART_INVERT case TIOCSINVERT: { uint32_t cr1; @@ -1803,7 +1803,7 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif -#ifdef CONFIG_STM32WL5_USART_SWAP +#ifdef CONFIG_STM32_USART_SWAP case TIOCSSWAP: { uint32_t cr1; @@ -1940,8 +1940,8 @@ static int stm32wl5serial_ioctl(struct file *filep, int cmd, break; #endif /* CONFIG_SERIAL_TERMIOS */ -#ifdef CONFIG_STM32WL5_USART_BREAKS -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_USART_BREAKS +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ { irqstate_t flags; @@ -2169,7 +2169,7 @@ static bool stm32wl5serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32WL5_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -2521,7 +2521,7 @@ static void stm32wl5serial_txint(struct uart_dev_s *dev, bool enable) } # endif -# ifdef CONFIG_STM32WL5_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -2862,7 +2862,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 (void)uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -2891,7 +2891,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32WL5_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.c b/arch/arm/src/stm32wl5/stm32wl5_spi.c index 45a5a2c2dda..9c7f0008af6 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.c +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.c @@ -69,12 +69,12 @@ #include "chip.h" #include "stm32.h" #include "stm32wl5_gpio.h" -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA #include "stm32wl5_dma.h" #endif #include "stm32wl5_spi.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -83,34 +83,34 @@ /* SPI interrupts */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS # error "Interrupt driven SPI not yet supported" #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # error "DMA driven SPI not yet supported" #endif /* Can't have both interrupt driven SPI and SPI DMA */ -#if defined(CONFIG_STM32WL5_SPI_INTERRUPTS) && defined(CONFIG_STM32WL5_SPI_DMA) +#if defined(CONFIG_STM32_SPI_INTERRUPTS) && defined(CONFIG_STM32_SPI_DMA) # error "Cannot enable both interrupt mode and DMA mode for SPI" #endif /* SPI DMA priority */ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA # if defined(CONFIG_SPI_DMAPRIO) # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO -# elif defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1 +# elif defined(CONFIG_STM32_STM32WL5XXX_CPU1 #warning "Verify, read doc and Implement" # define SPI_DMA_PRIO DMA_CCR_PRIMED # else # error "Unknown STM32WL5 DMA" # endif -# if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +# if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -120,7 +120,7 @@ /* DMA channel configuration */ -#if defined(CONFIG_STM32WL5_STM32WL5XXX_CPU1) +#if defined(CONFIG_STM32_STM32WL5XXX_CPU1) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_16BITS|DMA_CCR_PSIZE_16BITS|DMA_CCR_MINC ) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC ) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS ) @@ -137,15 +137,15 @@ # define SPIDMA_SIZE(b) (((b) + SPIDMA_BUFFER_MASK) & ~SPIDMA_BUFFER_MASK) # define SPIDMA_BUF_ALIGN aligned_data(4) -# if defined(CONFIG_STM32WL5_SPI1_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI1_DMA_BUFFER > 0 -# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI1_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI1_DMA_BUFFER) && \ + CONFIG_STM32_SPI1_DMA_BUFFER > 0 +# define SPI1_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI1_DMA_BUFFER) # define SPI1_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif -# if defined(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) && \ - CONFIG_STM32WL5_SPI2S2_DMA_BUFFER > 0 -# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32WL5_SPI2S2_DMA_BUFFER) +# if defined(CONFIG_STM32_SPI2S2_DMA_BUFFER) && \ + CONFIG_STM32_SPI2S2_DMA_BUFFER > 0 +# define SPI2S2_DMABUFSIZE_ADJUSTED SPIDMA_SIZE(CONFIG_STM32_SPI2S2_DMA_BUFFER) # define SPI2S2_DMABUFSIZE_ALGN SPIDMA_BUF_ALIGN # endif @@ -160,10 +160,10 @@ struct stm32_spidev_s struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ uint32_t spibase; /* SPIn base address */ uint32_t spiclock; /* Clocking for the SPI module */ -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS uint8_t spiirq; /* SPI IRQ number */ #endif -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA volatile uint8_t rxresult; /* Result of the RX DMA */ volatile uint8_t txresult; /* Result of the RX DMA */ #ifdef CONFIG_SPI_TRIGGER @@ -216,7 +216,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, /* DMA support */ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv); static int spi_dmatxwait(struct stm32_spidev_s *priv); static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv); @@ -273,7 +273,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv); * Private Data ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 static const struct spi_ops_s g_sp1iops = { .lock = spi_lock, @@ -318,11 +318,11 @@ static struct stm32_spidev_s g_spi1dev = }, .spibase = STM32_SPI1_BASE, .spiclock = STM32_PCLK2_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI1, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI1_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI1_DMA .rxch = DMACHAN_SPI1_RX, .txch = DMACHAN_SPI1_TX, #if defined(SPI1_DMABUFSIZE_ADJUSTED) @@ -341,7 +341,7 @@ static struct stm32_spidev_s g_spi1dev = }; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 static const struct spi_ops_s g_sp2iops = { .lock = spi_lock, @@ -388,11 +388,11 @@ static struct stm32_spidev_s g_spi2s2dev = }, .spibase = STM32_SPI2S2_BASE, .spiclock = STM32_PCLK1_FREQUENCY, -#ifdef CONFIG_STM32WL5_SPI_INTERRUPTS +#ifdef CONFIG_STM32_SPI_INTERRUPTS .spiirq = STM32_IRQ_SPI2S2, #endif -#ifdef CONFIG_STM32WL5_SPI_DMA -# ifdef CONFIG_STM32WL5_SPI2S2_DMA +#ifdef CONFIG_STM32_SPI_DMA +# ifdef CONFIG_STM32_SPI2S2_DMA .rxch = DMACHAN_SPI2S2_RX, .txch = DMACHAN_SPI2S2_TX, #if defined(SPI2S2_DMABUFSIZE_ADJUSTED) @@ -592,7 +592,7 @@ static inline void spi_writeword(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmarxwait(struct stm32_spidev_s *priv) { int ret; @@ -625,7 +625,7 @@ static int spi_dmarxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static int spi_dmatxwait(struct stm32_spidev_s *priv) { int ret; @@ -658,7 +658,7 @@ static int spi_dmatxwait(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->rxsem); @@ -673,7 +673,7 @@ static inline void spi_dmarxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) { nxsem_post(&priv->txsem); @@ -688,7 +688,7 @@ static inline void spi_dmatxwakeup(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -708,7 +708,7 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) { struct stm32_spidev_s *priv = (struct stm32_spidev_s *)arg; @@ -728,7 +728,7 @@ static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmarxsetup(struct stm32_spidev_s *priv, void *rxbuffer, void *rxdummy, size_t nwords) @@ -779,7 +779,7 @@ static void spi_dmarxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_dmatxsetup(struct stm32_spidev_s *priv, const void *txbuffer, const void *txdummy, size_t nwords) @@ -830,7 +830,7 @@ static void spi_dmatxsetup(struct stm32_spidev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmarxstart(struct stm32_spidev_s *priv) { priv->rxresult = 0; @@ -846,7 +846,7 @@ static inline void spi_dmarxstart(struct stm32_spidev_s *priv) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static inline void spi_dmatxstart(struct stm32_spidev_s *priv) { priv->txresult = 0; @@ -1348,9 +1348,9 @@ static uint32_t spi_send(struct spi_dev_s *dev, uint32_t wd) * ****************************************************************************/ -#if !defined(CONFIG_STM32WL5_SPI_DMA) || defined(CONFIG_STM32WL5_DMACAPABLE) || \ - defined(CONFIG_STM32WL5_SPI_DMATHRESHOLD) -#if !defined(CONFIG_STM32WL5_SPI_DMA) +#if !defined(CONFIG_STM32_SPI_DMA) || defined(CONFIG_STM32_DMACAPABLE) || \ + defined(CONFIG_STM32_SPI_DMATHRESHOLD) +#if !defined(CONFIG_STM32_SPI_DMA) static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) #else @@ -1433,7 +1433,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, } } } -#endif /* !CONFIG_STM32WL5_SPI_DMA || CONFIG_STM32WL5_DMACAPABLE || CONFIG_STM32WL5_SPI_DMATHRESHOLD */ +#endif /* !CONFIG_STM32_SPI_DMA || CONFIG_STM32_DMACAPABLE || CONFIG_STM32_SPI_DMATHRESHOLD */ /**************************************************************************** * Name: spi_exchange (with DMA capability) @@ -1456,7 +1456,7 @@ static void spi_exchange_nodma(struct spi_dev_s *dev, * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, void *rxbuffer, size_t nwords) { @@ -1470,12 +1470,12 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, size_t nbytes = (priv->nbits > 8) ? nwords << 1 : nwords; -#ifdef CONFIG_STM32WL5_SPI_DMATHRESHOLD +#ifdef CONFIG_STM32_SPI_DMATHRESHOLD /* If this is a small SPI transfer, then let spi_exchange_nodma() do the * work. */ - if (nbytes <= CONFIG_STM32WL5_SPI_DMATHRESHOLD) + if (nbytes <= CONFIG_STM32_SPI_DMATHRESHOLD) { spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); return; @@ -1493,7 +1493,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, return; } -#ifdef CONFIG_STM32WL5_DMACAPABLE +#ifdef CONFIG_STM32_DMACAPABLE if ((txbuffer != NULL && priv->txbuf == NULL && !stm32_dmacapable((uintptr_t)txbuffer, nwords, priv->txccr)) || (rxbuffer != NULL && priv->rxbuf == NULL && @@ -1580,7 +1580,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #endif } } -#endif /* CONFIG_STM32WL5_SPI_DMA */ +#endif /* CONFIG_STM32_SPI_DMA */ /**************************************************************************** * Name: spi_trigger @@ -1601,7 +1601,7 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, #ifdef CONFIG_SPI_TRIGGER static int spi_trigger(struct spi_dev_s *dev) { -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA struct stm32_spidev_s *priv = (struct stm32_spidev_s *)dev; if (!priv->trigarmed) @@ -1733,7 +1733,7 @@ static void spi_bus_initialize(struct stm32_spidev_s *priv) spi_putreg(priv, STM32_SPI_CRCPR_OFFSET, 7); -#ifdef CONFIG_STM32WL5_SPI_DMA +#ifdef CONFIG_STM32_SPI_DMA if (priv->rxch && priv->txch) { /* Get DMA channels. NOTE: stm32_dmachannel() will always assign @@ -1788,7 +1788,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) irqstate_t flags = enter_critical_section(); -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 if (bus == 1) { /* Select SPI1 */ @@ -1813,7 +1813,7 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) } else #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 if (bus == 2) { /* Select SPI2S2 */ @@ -1846,4 +1846,4 @@ struct spi_dev_s *stm32_spibus_initialize(int bus) return (struct spi_dev_s *)priv; } -#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_spi.h b/arch/arm/src/stm32wl5/stm32wl5_spi.h index 32b3d1c792b..c6bf1829f02 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_spi.h +++ b/arch/arm/src/stm32wl5/stm32wl5_spi.h @@ -107,14 +107,14 @@ struct spi_dev_s *stm32_spibus_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected); uint8_t stm32_spi2s2status(struct spi_dev_s *dev, uint32_t devid); @@ -142,12 +142,12 @@ int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); ****************************************************************************/ #ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 int stm32_spi2s2register(struct spi_dev_s *dev, spi_mediachange_t callback, void *arg); diff --git a/arch/arm/src/stm32wl5/stm32wl5_start.c b/arch/arm/src/stm32wl5/stm32wl5_start.c index e42585e0c82..24a7a9c240a 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_start.c +++ b/arch/arm/src/stm32wl5/stm32wl5_start.c @@ -133,7 +133,7 @@ void __start(void) "r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :); #endif -#ifdef CONFIG_STM32WL5_SRAM2_INIT +#ifdef CONFIG_STM32_SRAM2_INIT /* The SRAM2 region is parity checked, but upon power up, it will be in * a random state and probably invalid with respect to parity, potentially * generating faults if accessed. If elected, we will write zeros to the diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim.c b/arch/arm/src/stm32wl5/stm32wl5_tim.c index 3ca352fb788..4802a977b37 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim.c @@ -74,118 +74,118 @@ * In any of these cases, the timer will not be used by this timer module. */ -#if defined(CONFIG_STM32WL5_TIM1_PWM) || defined (CONFIG_STM32WL5_TIM1_ADC) || \ - defined(CONFIG_STM32WL5_TIM1_DAC) || defined(CONFIG_STM32WL5_TIM1_QE) -# undef CONFIG_STM32WL5_TIM1 +#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || \ + defined(CONFIG_STM32_TIM1_DAC) || defined(CONFIG_STM32_TIM1_QE) +# undef CONFIG_STM32_TIM1 #endif -#if defined(CONFIG_STM32WL5_TIM2_PWM) || defined (CONFIG_STM32WL5_TIM2_ADC) || \ - defined(CONFIG_STM32WL5_TIM2_DAC) || defined(CONFIG_STM32WL5_TIM2_QE) -# undef CONFIG_STM32WL5_TIM2 +#if defined(CONFIG_STM32_TIM2_PWM) || defined (CONFIG_STM32_TIM2_ADC) || \ + defined(CONFIG_STM32_TIM2_DAC) || defined(CONFIG_STM32_TIM2_QE) +# undef CONFIG_STM32_TIM2 #endif -#if defined(CONFIG_STM32WL5_TIM3_PWM) || defined (CONFIG_STM32WL5_TIM3_ADC) || \ - defined(CONFIG_STM32WL5_TIM3_DAC) || defined(CONFIG_STM32WL5_TIM3_QE) -# undef CONFIG_STM32WL5_TIM3 +#if defined(CONFIG_STM32_TIM3_PWM) || defined (CONFIG_STM32_TIM3_ADC) || \ + defined(CONFIG_STM32_TIM3_DAC) || defined(CONFIG_STM32_TIM3_QE) +# undef CONFIG_STM32_TIM3 #endif -#if defined(CONFIG_STM32WL5_TIM4_PWM) || defined (CONFIG_STM32WL5_TIM4_ADC) || \ - defined(CONFIG_STM32WL5_TIM4_DAC) || defined(CONFIG_STM32WL5_TIM4_QE) -# undef CONFIG_STM32WL5_TIM4 +#if defined(CONFIG_STM32_TIM4_PWM) || defined (CONFIG_STM32_TIM4_ADC) || \ + defined(CONFIG_STM32_TIM4_DAC) || defined(CONFIG_STM32_TIM4_QE) +# undef CONFIG_STM32_TIM4 #endif -#if defined(CONFIG_STM32WL5_TIM5_PWM) || defined (CONFIG_STM32WL5_TIM5_ADC) || \ - defined(CONFIG_STM32WL5_TIM5_DAC) || defined(CONFIG_STM32WL5_TIM5_QE) -# undef CONFIG_STM32WL5_TIM5 +#if defined(CONFIG_STM32_TIM5_PWM) || defined (CONFIG_STM32_TIM5_ADC) || \ + defined(CONFIG_STM32_TIM5_DAC) || defined(CONFIG_STM32_TIM5_QE) +# undef CONFIG_STM32_TIM5 #endif -#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32WL5_TIM6_ADC) || \ - defined(CONFIG_STM32WL5_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE) -# undef CONFIG_STM32WL5_TIM6 +#if defined(CONFIG_STM32WL5_TIM6_PWM) || defined (CONFIG_STM32_TIM6_ADC) || \ + defined(CONFIG_STM32_TIM6_DAC) || defined(CONFIG_STM32WL5_TIM6_QE) +# undef CONFIG_STM32_TIM6 #endif #if defined(CONFIG_STM32WL5_TIM7_PWM) || defined (CONFIG_STM32WL5_TIM7_ADC) || \ - defined(CONFIG_STM32WL5_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE) -# undef CONFIG_STM32WL5_TIM7 + defined(CONFIG_STM32_TIM7_DAC) || defined(CONFIG_STM32WL5_TIM7_QE) +# undef CONFIG_STM32_TIM7 #endif -#if defined(CONFIG_STM32WL5_TIM8_PWM) || defined (CONFIG_STM32WL5_TIM8_ADC) || \ - defined(CONFIG_STM32WL5_TIM8_DAC) || defined(CONFIG_STM32WL5_TIM8_QE) -# undef CONFIG_STM32WL5_TIM8 +#if defined(CONFIG_STM32_TIM8_PWM) || defined (CONFIG_STM32_TIM8_ADC) || \ + defined(CONFIG_STM32_TIM8_DAC) || defined(CONFIG_STM32_TIM8_QE) +# undef CONFIG_STM32_TIM8 #endif -#if defined(CONFIG_STM32WL5_TIM15_PWM) || defined (CONFIG_STM32WL5_TIM15_ADC) || \ +#if defined(CONFIG_STM32_TIM15_PWM) || defined (CONFIG_STM32_TIM15_ADC) || \ defined(CONFIG_STM32WL5_TIM15_DAC) || defined(CONFIG_STM32WL5_TIM15_QE) -# undef CONFIG_STM32WL5_TIM15 +# undef CONFIG_STM32_TIM15 #endif -#if defined(CONFIG_STM32WL5_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \ +#if defined(CONFIG_STM32_TIM16_PWM) || defined (CONFIG_STM32WL5_TIM16_ADC) || \ defined(CONFIG_STM32WL5_TIM16_DAC) || defined(CONFIG_STM32WL5_TIM16_QE) -# undef CONFIG_STM32WL5_TIM16 +# undef CONFIG_STM32_TIM16 #endif -#if defined(CONFIG_STM32WL5_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \ +#if defined(CONFIG_STM32_TIM17_PWM) || defined (CONFIG_STM32WL5_TIM17_ADC) || \ defined(CONFIG_STM32WL5_TIM17_DAC) || defined(CONFIG_STM32WL5_TIM17_QE) -# undef CONFIG_STM32WL5_TIM17 +# undef CONFIG_STM32_TIM17 #endif -#if defined(CONFIG_STM32WL5_TIM1) +#if defined(CONFIG_STM32_TIM1) # if defined(GPIO_TIM1_CH1OUT) ||defined(GPIO_TIM1_CH2OUT)||\ defined(GPIO_TIM1_CH3OUT) ||defined(GPIO_TIM1_CH4OUT) # define HAVE_TIM1_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM2) +#if defined(CONFIG_STM32_TIM2) # if defined(GPIO_TIM2_CH1OUT) ||defined(GPIO_TIM2_CH2OUT)||\ defined(GPIO_TIM2_CH3OUT) ||defined(GPIO_TIM2_CH4OUT) # define HAVE_TIM2_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM3) +#if defined(CONFIG_STM32_TIM3) # if defined(GPIO_TIM3_CH1OUT) ||defined(GPIO_TIM3_CH2OUT)||\ defined(GPIO_TIM3_CH3OUT) ||defined(GPIO_TIM3_CH4OUT) # define HAVE_TIM3_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM4) +#if defined(CONFIG_STM32_TIM4) # if defined(GPIO_TIM4_CH1OUT) ||defined(GPIO_TIM4_CH2OUT)||\ defined(GPIO_TIM4_CH3OUT) ||defined(GPIO_TIM4_CH4OUT) # define HAVE_TIM4_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM5) +#if defined(CONFIG_STM32_TIM5) # if defined(GPIO_TIM5_CH1OUT) ||defined(GPIO_TIM5_CH2OUT)||\ defined(GPIO_TIM5_CH3OUT) ||defined(GPIO_TIM5_CH4OUT) # define HAVE_TIM5_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM8) +#if defined(CONFIG_STM32_TIM8) # if defined(GPIO_TIM8_CH1OUT) ||defined(GPIO_TIM8_CH2OUT)||\ defined(GPIO_TIM8_CH3OUT) ||defined(GPIO_TIM8_CH4OUT) # define HAVE_TIM8_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM15) +#if defined(CONFIG_STM32_TIM15) # if defined(GPIO_TIM15_CH1OUT) ||defined(GPIO_TIM15_CH2OUT)||\ defined(GPIO_TIM15_CH3OUT) ||defined(GPIO_TIM15_CH4OUT) # define HAVE_TIM15_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM16) +#if defined(CONFIG_STM32_TIM16) # if defined(GPIO_TIM16_CH1OUT) ||defined(GPIO_TIM16_CH2OUT)||\ defined(GPIO_TIM16_CH3OUT) ||defined(GPIO_TIM16_CH4OUT) # define HAVE_TIM16_GPIOCONFIG 1 #endif #endif -#if defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM17) # if defined(GPIO_TIM17_CH1OUT) ||defined(GPIO_TIM17_CH2OUT)||\ defined(GPIO_TIM17_CH3OUT) ||defined(GPIO_TIM17_CH4OUT) # define HAVE_TIM17_GPIOCONFIG 1 @@ -196,12 +196,12 @@ * intended for some other purpose. */ -#if defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17) +#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17) /**************************************************************************** * Private Types @@ -302,7 +302,7 @@ static const struct stm32_tim_ops_s stm32_tim_ops = .checkint = stm32_tim_checkint, }; -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 struct stm32_tim_priv_s stm32_tim1_priv = { .ops = &stm32_tim_ops, @@ -310,7 +310,7 @@ struct stm32_tim_priv_s stm32_tim1_priv = .base = STM32_TIM1_BASE, }; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 struct stm32_tim_priv_s stm32_tim2_priv = { .ops = &stm32_tim_ops, @@ -319,7 +319,7 @@ struct stm32_tim_priv_s stm32_tim2_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 struct stm32_tim_priv_s stm32_tim3_priv = { .ops = &stm32_tim_ops, @@ -328,7 +328,7 @@ struct stm32_tim_priv_s stm32_tim3_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 struct stm32_tim_priv_s stm32_tim4_priv = { .ops = &stm32_tim_ops, @@ -337,7 +337,7 @@ struct stm32_tim_priv_s stm32_tim4_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 struct stm32_tim_priv_s stm32_tim5_priv = { .ops = &stm32_tim_ops, @@ -346,7 +346,7 @@ struct stm32_tim_priv_s stm32_tim5_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 struct stm32_tim_priv_s stm32_tim6_priv = { .ops = &stm32_tim_ops, @@ -355,7 +355,7 @@ struct stm32_tim_priv_s stm32_tim6_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 struct stm32_tim_priv_s stm32_tim7_priv = { .ops = &stm32_tim_ops, @@ -364,7 +364,7 @@ struct stm32_tim_priv_s stm32_tim7_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 struct stm32_tim_priv_s stm32_tim8_priv = { .ops = &stm32_tim_ops, @@ -373,7 +373,7 @@ struct stm32_tim_priv_s stm32_tim8_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 struct stm32_tim_priv_s stm32_tim15_priv = { .ops = &stm32_tim_ops, @@ -382,7 +382,7 @@ struct stm32_tim_priv_s stm32_tim15_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 struct stm32_tim_priv_s stm32_tim16_priv = { .ops = &stm32_tim_ops, @@ -391,7 +391,7 @@ struct stm32_tim_priv_s stm32_tim16_priv = }; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 struct stm32_tim_priv_s stm32_tim17_priv = { .ops = &stm32_tim_ops, @@ -656,66 +656,66 @@ static int stm32_tim_setclock(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -771,64 +771,64 @@ static uint32_t stm32_tim_getclock(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: freqin = BOARD_TIM1_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: freqin = BOARD_TIM2_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: freqin = BOARD_TIM3_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: freqin = BOARD_TIM4_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: freqin = BOARD_TIM5_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: freqin = BOARD_TIM6_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: freqin = BOARD_TIM7_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: freqin = BOARD_TIM8_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: freqin = BOARD_TIM15_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: freqin = BOARD_TIM16_FREQUENCY; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: freqin = BOARD_TIM17_FREQUENCY; break; @@ -877,13 +877,13 @@ static uint32_t stm32_tim_getcounter(struct stm32_tim_dev_s *dev) * reset it it result when not TIM2 or TIM5. */ -#if defined(CONFIG_STM32WL5_TIM2) || defined(CONFIG_STM32WL5_TIM5) +#if defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM5) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: #endif return counter; @@ -989,7 +989,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: switch (channel) { @@ -1022,7 +1022,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: switch (channel) { @@ -1055,7 +1055,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: switch (channel) { @@ -1088,7 +1088,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: switch (channel) { @@ -1120,7 +1120,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: switch (channel) { @@ -1153,7 +1153,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: switch (channel) { @@ -1186,7 +1186,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: switch (channel) { @@ -1219,7 +1219,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: switch (channel) { @@ -1252,7 +1252,7 @@ static int stm32_tim_setchannel(struct stm32_tim_dev_s *dev, } break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: switch (channel) { @@ -1368,65 +1368,65 @@ static int stm32_tim_setisr(struct stm32_tim_dev_s *dev, switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: vectorno = STM32_IRQ_TIM1UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: vectorno = STM32_IRQ_TIM2; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: vectorno = STM32_IRQ_TIM3; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: vectorno = STM32_IRQ_TIM4; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: vectorno = STM32_IRQ_TIM5; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: vectorno = STM32_IRQ_TIM6; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: vectorno = STM32_IRQ_TIM7; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: vectorno = STM32_IRQ_TIM8UP; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: vectorno = STM32_IRQ_TIM15; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: vectorno = STM32_IRQ_TIM16; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: vectorno = STM32_IRQ_TIM17; break; @@ -1511,76 +1511,76 @@ struct stm32_tim_dev_s *stm32_tim_init(int timer) switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM2EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM3EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM4EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM5EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM6EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv; modifyreg32(STM32_RCC_APB1ENR1, 0, RCC_APB1ENR1_TIM7EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: dev = (struct stm32_tim_dev_s *)&stm32_tim15_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM15EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: dev = (struct stm32_tim_dev_s *)&stm32_tim16_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM16EN); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: dev = (struct stm32_tim_dev_s *)&stm32_tim17_priv; modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM17EN); @@ -1618,66 +1618,66 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) switch (((struct stm32_tim_priv_s *)dev)->base) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case STM32_TIM1_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case STM32_TIM2_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM2EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case STM32_TIM3_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM3EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case STM32_TIM4_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM4EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case STM32_TIM5_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM5EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case STM32_TIM6_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM6EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case STM32_TIM7_BASE: modifyreg32(STM32_RCC_APB1ENR1, RCC_APB1ENR1_TIM7EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case STM32_TIM8_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case STM32_TIM15_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM15EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case STM32_TIM16_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM16EN, 0); break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case STM32_TIM17_BASE: modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM17EN, 0); break; @@ -1694,4 +1694,4 @@ int stm32_tim_deinit(struct stm32_tim_dev_s *dev) return OK; } -#endif /* defined(CONFIG_STM32WL5_TIM1 || ... || TIM17) */ +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM17) */ diff --git a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c index d32824d14ad..233008d82f0 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c +++ b/arch/arm/src/stm32wl5/stm32wl5_tim_lowerhalf.c @@ -41,12 +41,12 @@ #include "stm32wl5_tim.h" #if defined(CONFIG_TIMER) && \ - (defined(CONFIG_STM32WL5_TIM1) || defined(CONFIG_STM32WL5_TIM2) || \ - defined(CONFIG_STM32WL5_TIM3) || defined(CONFIG_STM32WL5_TIM4) || \ - defined(CONFIG_STM32WL5_TIM5) || defined(CONFIG_STM32WL5_TIM6) || \ - defined(CONFIG_STM32WL5_TIM7) || defined(CONFIG_STM32WL5_TIM8) || \ - defined(CONFIG_STM32WL5_TIM15) || defined(CONFIG_STM32WL5_TIM16) || \ - defined(CONFIG_STM32WL5_TIM17)) + (defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || \ + defined(CONFIG_STM32_TIM3) || defined(CONFIG_STM32_TIM4) || \ + defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \ + defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8) || \ + defined(CONFIG_STM32_TIM15) || defined(CONFIG_STM32_TIM16) || \ + defined(CONFIG_STM32_TIM17)) /**************************************************************************** * Pre-processor Definitions @@ -118,7 +118,7 @@ static const struct timer_ops_s g_timer_ops = .ioctl = NULL, }; -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 static struct stm32_lowerhalf_s g_tim1_lowerhalf = { .ops = &g_timer_ops, @@ -126,7 +126,7 @@ static struct stm32_lowerhalf_s g_tim1_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 static struct stm32_lowerhalf_s g_tim2_lowerhalf = { .ops = &g_timer_ops, @@ -134,7 +134,7 @@ static struct stm32_lowerhalf_s g_tim2_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 static struct stm32_lowerhalf_s g_tim3_lowerhalf = { .ops = &g_timer_ops, @@ -142,7 +142,7 @@ static struct stm32_lowerhalf_s g_tim3_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 static struct stm32_lowerhalf_s g_tim4_lowerhalf = { .ops = &g_timer_ops, @@ -150,7 +150,7 @@ static struct stm32_lowerhalf_s g_tim4_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 static struct stm32_lowerhalf_s g_tim5_lowerhalf = { .ops = &g_timer_ops, @@ -158,7 +158,7 @@ static struct stm32_lowerhalf_s g_tim5_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 static struct stm32_lowerhalf_s g_tim6_lowerhalf = { .ops = &g_timer_ops, @@ -166,7 +166,7 @@ static struct stm32_lowerhalf_s g_tim6_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 static struct stm32_lowerhalf_s g_tim7_lowerhalf = { .ops = &g_timer_ops, @@ -174,7 +174,7 @@ static struct stm32_lowerhalf_s g_tim7_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 static struct stm32_lowerhalf_s g_tim8_lowerhalf = { .ops = &g_timer_ops, @@ -182,7 +182,7 @@ static struct stm32_lowerhalf_s g_tim8_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 static struct stm32_lowerhalf_s g_tim15_lowerhalf = { .ops = &g_timer_ops, @@ -190,7 +190,7 @@ static struct stm32_lowerhalf_s g_tim15_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 static struct stm32_lowerhalf_s g_tim16_lowerhalf = { .ops = &g_timer_ops, @@ -198,7 +198,7 @@ static struct stm32_lowerhalf_s g_tim16_lowerhalf = }; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 static struct stm32_lowerhalf_s g_tim17_lowerhalf = { .ops = &g_timer_ops, @@ -503,66 +503,66 @@ int stm32_timer_initialize(const char *devpath, int timer) switch (timer) { -#ifdef CONFIG_STM32WL5_TIM1 +#ifdef CONFIG_STM32_TIM1 case 1: lower = &g_tim1_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM2 +#ifdef CONFIG_STM32_TIM2 case 2: lower = &g_tim2_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM3 +#ifdef CONFIG_STM32_TIM3 case 3: lower = &g_tim3_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM4 +#ifdef CONFIG_STM32_TIM4 case 4: lower = &g_tim4_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM5 +#ifdef CONFIG_STM32_TIM5 case 5: lower = &g_tim5_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM6 +#ifdef CONFIG_STM32_TIM6 case 6: lower = &g_tim6_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM7 +#ifdef CONFIG_STM32_TIM7 case 7: lower = &g_tim7_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM8 +#ifdef CONFIG_STM32_TIM8 case 8: lower = &g_tim8_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM15 +#ifdef CONFIG_STM32_TIM15 case 15: lower = &g_tim15_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM16 +#ifdef CONFIG_STM32_TIM16 case 16: lower = &g_tim16_lowerhalf; break; #endif -#ifdef CONFIG_STM32WL5_TIM17 +#ifdef CONFIG_STM32_TIM17 case 17: lower = &g_tim17_lowerhalf; break; diff --git a/arch/arm/src/stm32wl5/stm32wl5_uart.h b/arch/arm/src/stm32wl5/stm32wl5_uart.h index 00f859e2f68..b43e985024c 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_uart.h +++ b/arch/arm/src/stm32wl5/stm32wl5_uart.h @@ -42,42 +42,42 @@ * device. */ -#if !defined(CONFIG_STM32WL5_HAVE_USART2) -# undef CONFIG_STM32WL5_USART2 +#if !defined(CONFIG_STM32_HAVE_USART2) +# undef CONFIG_STM32_USART2 #endif -#if !defined(CONFIG_STM32WL5_HAVE_USART1) -# undef CONFIG_STM32WL5_USART1 +#if !defined(CONFIG_STM32_HAVE_USART1) +# undef CONFIG_STM32_USART1 #endif -#if !defined(CONFIG_STM32WL5_HAVE_LPUART1) -# undef CONFIG_STM32WL5_LPUART1 +#if !defined(CONFIG_STM32_HAVE_LPUART1) +# undef CONFIG_STM32_LPUART1 #endif /* Sanity checks */ -#if !defined(CONFIG_STM32WL5_LPUART1) -# undef CONFIG_STM32WL5_LPUART1_SERIALDRIVER -# undef CONFIG_STM32WL5_LPUART1_1WIREDRIVER +#if !defined(CONFIG_STM32_LPUART1) +# undef CONFIG_STM32_LPUART1_SERIALDRIVER +# undef CONFIG_STM32_LPUART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART1) -# undef CONFIG_STM32WL5_USART1_SERIALDRIVER -# undef CONFIG_STM32WL5_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif -#if !defined(CONFIG_STM32WL5_USART2) -# undef CONFIG_STM32WL5_USART2_SERIALDRIVER -# undef CONFIG_STM32WL5_USART2_1WIREDRIVER +#if !defined(CONFIG_STM32_USART2) +# undef CONFIG_STM32_USART2_SERIALDRIVER +# undef CONFIG_STM32_USART2_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32WL5_LPUART1) || \ - defined(CONFIG_STM32WL5_USART1) || \ - defined(CONFIG_STM32WL5_USART2) +#if defined(CONFIG_STM32_LPUART1) || \ + defined(CONFIG_STM32_USART1) || \ + defined(CONFIG_STM32_USART2) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_LPUART1_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -85,7 +85,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # undef CONFIG_LPUART1_SERIAL_CONSOLE # undef CONFIG_USART2_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE @@ -93,7 +93,7 @@ # undef CONFIG_UART5_SERIAL_CONSOLE # define CONSOLE_UART 2 # define HAVE_CONSOLE 1 -#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2_SERIALDRIVER) # undef CONFIG_USART1_SERIAL_CONSOLE # undef CONFIG_USART3_SERIAL_CONSOLE # undef CONFIG_UART4_SERIAL_CONSOLE @@ -121,15 +121,15 @@ /* Disable the DMA configuration on all unused USARTs */ -#ifndef CONFIG_STM32WL5_LPUART1_SERIALDRIVER +#ifndef CONFIG_STM32_LPUART1_SERIALDRIVER # undef CONFIG_LPUART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART1_SERIALDRIVER +#ifndef CONFIG_STM32_USART1_SERIALDRIVER # undef CONFIG_USART1_RXDMA #endif -#ifndef CONFIG_STM32WL5_USART2_SERIALDRIVER +#ifndef CONFIG_STM32_USART2_SERIALDRIVER # undef CONFIG_USART2_RXDMA #endif @@ -156,11 +156,11 @@ /* Is DMA used on all (enabled) USARTs */ #define SERIAL_HAVE_ONLY_DMA 1 -#if defined(CONFIG_STM32WL5_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) +#if defined(CONFIG_STM32_LPUART1_SERIALDRIVER) && !defined(CONFIG_LPUART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) +#elif defined(CONFIG_STM32_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_RXDMA) # undef SERIAL_HAVE_ONLY_DMA -#elif defined(CONFIG_STM32WL5_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) +#elif defined(CONFIG_STM32_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_RXDMA) # undef SERIAL_HAVE_ONLY_DMA #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig index 411801e17de..f66ff2ef2e6 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/Kconfig @@ -24,7 +24,7 @@ config ARCH_BOARD_ENABLE_CPU2 menuconfig ARCH_BOARD_IPCC bool "Enabled IPCC" select IPCC - select STM32WL5_IPCC + select STM32_IPCC default n ---help--- Enables IPCC (inter processor communication controller) @@ -52,7 +52,7 @@ config ARCH_BOARD_IPCC_CHAN1_TXBUF config ARCH_BOARD_IPCC_CHAN2 bool "Enable channel 2" default n - select STM32WL5_IPCC_CHAN2 + select STM32_IPCC_CHAN2 if ARCH_BOARD_IPCC_CHAN2 @@ -69,7 +69,7 @@ config ARCH_BOARD_IPCC_CHAN2_TXBUF config ARCH_BOARD_IPCC_CHAN3 bool "Enable channel 3" default n - select STM32WL5_IPCC_CHAN3 + select STM32_IPCC_CHAN3 if ARCH_BOARD_IPCC_CHAN3 @@ -86,7 +86,7 @@ config ARCH_BOARD_IPCC_CHAN3_TXBUF config ARCH_BOARD_IPCC_CHAN4 bool "Enable channel 4" default n - select STM32WL5_IPCC_CHAN4 + select STM32_IPCC_CHAN4 if ARCH_BOARD_IPCC_CHAN4 @@ -103,7 +103,7 @@ config ARCH_BOARD_IPCC_CHAN4_TXBUF config ARCH_BOARD_IPCC_CHAN5 bool "Enable channel 5" default n - select STM32WL5_IPCC_CHAN5 + select STM32_IPCC_CHAN5 if ARCH_BOARD_IPCC_CHAN5 @@ -120,7 +120,7 @@ config ARCH_BOARD_IPCC_CHAN5_TXBUF config ARCH_BOARD_IPCC_CHAN6 bool "Enable channel 6" default n - select STM32WL5_IPCC_CHAN6 + select STM32_IPCC_CHAN6 if ARCH_BOARD_IPCC_CHAN6 diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig index 1074e1f8d0b..7a097b223f4 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/demo/defconfig @@ -28,6 +28,7 @@ CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC_DEMO_LED_IRQ=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_ARCH_IRQBUTTONS=y @@ -48,7 +49,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_CFGDATA=y CONFIG_SYSTEM_NSH=y CONFIG_USERLED=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig index 3c5150dc6a9..ebc8bd12c3a 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/fb/defconfig @@ -12,6 +12,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -33,9 +34,9 @@ CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_SPI=y CONFIG_SPI_DRIVER=y -CONFIG_STM32WL5_LPUART1=y -CONFIG_STM32WL5_SPI1=y -CONFIG_STM32WL5_SPI2S2=y -CONFIG_STM32WL5_USART1=y +CONFIG_STM32_LPUART1=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_SPI2S2=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig index 9318532b4a1..7a7e9b2a68b 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig +++ b/boards/arm/stm32wl5/nucleo-wl55jc/configs/nsh/defconfig @@ -11,6 +11,7 @@ CONFIG_ARCH_BOARD="nucleo-wl55jc" CONFIG_ARCH_BOARD_NUCLEO_WL55JC=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_CHIP="stm32wl5" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32WL55JC_CPU1=y CONFIG_ARCH_CHIP_STM32WL5=y CONFIG_BOARD_LOOPSPERMSEC=0 @@ -20,5 +21,5 @@ CONFIG_LPUART1_SERIAL_CONSOLE=y CONFIG_RAM_SIZE=32768 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y -CONFIG_STM32WL5_LPUART1=y +CONFIG_STM32_LPUART1=y CONFIG_SYSTEM_NSH=y diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c index 1335387ce8d..86454d00062 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_boot.c @@ -108,7 +108,7 @@ void board_late_initialize(void) { int ret; -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) stm32_spidev_initialize(); #endif diff --git a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c index 7299f52ba57..a3748c2db24 100644 --- a/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c +++ b/boards/arm/stm32wl5/nucleo-wl55jc/src/stm32_spi.c @@ -40,7 +40,7 @@ #include "stm32.h" #include "nucleo-wl55jc.h" -#if defined(CONFIG_STM32WL5_SPI1) || defined(CONFIG_STM32WL5_SPI2S2) +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2S2) /**************************************************************************** * Public Data @@ -48,10 +48,10 @@ /* Global driver instances */ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 struct spi_dev_s *g_spi1; #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 struct spi_dev_s *g_spi2; #endif @@ -70,7 +70,7 @@ struct spi_dev_s *g_spi2; void weak_function stm32_spidev_initialize(void) { -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 /* Configure SPI-based devices */ g_spi1 = stm32_spibus_initialize(1); @@ -90,7 +90,7 @@ void weak_function stm32_spidev_initialize(void) #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 /* Configure SPI-based devices */ g_spi2 = stm32_spibus_initialize(2); @@ -123,7 +123,7 @@ void weak_function stm32_spidev_initialize(void) * ****************************************************************************/ -#ifdef CONFIG_STM32WL5_SPI1 +#ifdef CONFIG_STM32_SPI1 void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -178,7 +178,7 @@ int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif -#ifdef CONFIG_STM32WL5_SPI2S2 +#ifdef CONFIG_STM32_SPI2S2 void stm32_spi2s2select(struct spi_dev_s *dev, uint32_t devid, bool selected) { @@ -198,4 +198,4 @@ int stm32_spi2s2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) #endif -#endif /* CONFIG_STM32WL5_SPI1 || CONFIG_STM32WL5_SPI2S2 */ +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2S2 */ From 704815b2332f02562286b9ff5432ea0d8d290c73 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 20 May 2026 11:41:02 +0200 Subject: [PATCH 094/268] !arch/stm32n6: use common STM32 Kconfig symbols BREAKING CHANGE: STM32N6 Kconfig symbols were renamed from CONFIG_STM32N6_* to CONFIG_STM32_*. Out-of-tree code must update defconfigs and Kconfig references to the new CONFIG_STM32_* names. Signed-off-by: raiden00pl --- arch/arm/Kconfig | 1 + arch/arm/src/stm32n6/CMakeLists.txt | 4 +- arch/arm/src/stm32n6/Kconfig | 97 ++----------------- arch/arm/src/stm32n6/Make.defs | 2 +- arch/arm/src/stm32n6/stm32_serial.c | 30 +++--- arch/arm/src/stm32n6/stm32_start.c | 4 +- arch/arm/src/stm32n6/stm32_uart.h | 10 +- arch/arm/src/stm32n6/stm32n6xx_rcc.c | 2 +- .../nucleo-n657x0-q/configs/leds/defconfig | 3 +- .../nucleo-n657x0-q/configs/nsh/defconfig | 3 +- .../nucleo-n657x0-q/configs/ostest/defconfig | 3 +- 11 files changed, 42 insertions(+), 117 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 36c1510839b..603dab1a965 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -687,6 +687,7 @@ config ARCH_CHIP_STM32H5 config ARCH_CHIP_STM32N6 bool "STMicro STM32 N6" + select ARCH_CHIP_STM32 select ARCH_CORTEXM55 select ARCH_HAVE_FPU select ARCH_HAVE_MPU diff --git a/arch/arm/src/stm32n6/CMakeLists.txt b/arch/arm/src/stm32n6/CMakeLists.txt index afb34a68903..cd2b788424d 100644 --- a/arch/arm/src/stm32n6/CMakeLists.txt +++ b/arch/arm/src/stm32n6/CMakeLists.txt @@ -39,13 +39,13 @@ if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() -if(CONFIG_STM32N6_USART) +if(CONFIG_STM32_USART) list(APPEND SRCS stm32_serial.c) endif() # Chip-specific RCC -if(CONFIG_STM32N6_STM32N6XXXX) +if(CONFIG_STM32_STM32N6XXXX) list(APPEND SRCS stm32n6xx_rcc.c) endif() diff --git a/arch/arm/src/stm32n6/Kconfig b/arch/arm/src/stm32n6/Kconfig index 2e362795f5c..b90a6b0663c 100644 --- a/arch/arm/src/stm32n6/Kconfig +++ b/arch/arm/src/stm32n6/Kconfig @@ -1,27 +1,18 @@ -# arch/arm/src/stm32n6/Kconfig # -# SPDX-License-Identifier: Apache-2.0 +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. # -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. if ARCH_CHIP_STM32N6 comment "STM32N6 Configuration Options" -config STM32N6_STM32N6XXXX +config STM32_N6_PERIPHERALS + bool + default y + select STM32_HAVE_USART1 + +config STM32_STM32N6XXXX bool default y @@ -32,78 +23,8 @@ choice config ARCH_CHIP_STM32N657X0 bool "STM32N657X0" - select STM32N6_STM32N6XXXX + select STM32_STM32N6XXXX endchoice -menu "STM32N6 Peripheral Selection" - -config STM32N6_USART1 - bool "USART1" - default n - select STM32N6_USART - select USART1_SERIALDRIVER - select STM32N6_USART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config STM32N6_USART1_SERIALDRIVER - bool - default n - -config STM32N6_USART - bool - -if STM32N6_USART - -config STM32N6_SERIAL_DISABLE_REORDERING - bool "Disable reordering of ttySx devices." - depends on STM32N6_USART1 - default n - ---help--- - NuttX per default reorders the serial ports (/dev/ttySx) so that the - console is always on /dev/ttyS0. If more than one UART is in use this - can, however, have the side-effect that all port mappings - (hardware USART1 -> /dev/ttyS0) change if the console is moved to - another UART. This option disables that reordering so port names - stay stable when the console is moved. - -config STM32N6_FLOWCONTROL_BROKEN - bool "Use Software UART RTS flow control" - default n - ---help--- - Enable this option to use software RTS flow control rather than - the hardware RTS line. Useful in cases where the silicon RTS - behaviour does not match the application's needs. - -config STM32N6_SERIALBRK_BSDCOMPAT - bool "Use GPIO to send Break" - default n - ---help--- - Enable this option to send break by reconfiguring TX as a GPIO - held low for the requested duration, matching BSD-compatible - semantics. - -config STM32N6_PM_SERIAL_ACTIVITY - int "PM serial activity" - default 10 - ---help--- - PM activity reported to power management logic on every serial - interrupt. - -endif # STM32N6_USART - -if USART1_SERIALDRIVER - -config USART1_UNCONFIG_RX_ON_CLOSE - bool "Unconfigure USART1 RX pin on close" - default n - -config USART1_UNCONFIG_TX_ON_CLOSE - bool "Unconfigure USART1 TX pin on close" - default n - -endif # USART1_SERIALDRIVER - -endmenu - endif # ARCH_CHIP_STM32N6 diff --git a/arch/arm/src/stm32n6/Make.defs b/arch/arm/src/stm32n6/Make.defs index cecd24bbf69..7be078fc1ef 100644 --- a/arch/arm/src/stm32n6/Make.defs +++ b/arch/arm/src/stm32n6/Make.defs @@ -38,7 +38,7 @@ ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif -ifeq ($(CONFIG_STM32N6_USART),y) +ifeq ($(CONFIG_STM32_USART),y) CHIP_CSRCS += stm32_serial.c endif diff --git a/arch/arm/src/stm32n6/stm32_serial.c b/arch/arm/src/stm32n6/stm32_serial.c index 75dc8c8c857..7b053b9820f 100644 --- a/arch/arm/src/stm32n6/stm32_serial.c +++ b/arch/arm/src/stm32n6/stm32_serial.c @@ -62,8 +62,8 @@ /* Power management definitions */ -#if defined(CONFIG_PM) && !defined(CONFIG_STM32N6_PM_SERIAL_ACTIVITY) -# define CONFIG_STM32N6_PM_SERIAL_ACTIVITY 10 +#if defined(CONFIG_PM) && !defined(CONFIG_STM32_PM_SERIAL_ACTIVITY) +# define CONFIG_STM32_PM_SERIAL_ACTIVITY 10 #endif /* USART Unconfigure bits */ @@ -82,7 +82,7 @@ * See stm32serial_restoreusartint where the masking is done. */ -#ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +#ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT # define USART_CR1_IE_BREAK_INPROGRESS_SHFTS 15 # define USART_CR1_IE_BREAK_INPROGRESS (1 << USART_CR1_IE_BREAK_INPROGRESS_SHFTS) #endif @@ -210,14 +210,14 @@ static const struct uart_ops_s g_uart_ops = /* I/O buffers */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE]; static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE]; #endif /* This describes the state of the STM32N6 USART1 port. */ -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER static struct stm32_serial_s g_usart1priv = { .dev = @@ -276,7 +276,7 @@ static struct stm32_serial_s g_usart1priv = static struct stm32_serial_s * const g_uart_devs[STM32_NUSART] = { -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER [0] = &g_usart1priv, #endif }; @@ -542,7 +542,7 @@ static void stm32serial_setformat(struct uart_dev_s *dev) regval = stm32serial_getreg(priv, STM32_USART_CR3_OFFSET); regval &= ~(USART_CR3_CTSE | USART_CR3_RTSE); -#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && !defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { regval |= USART_CR3_RTSE; @@ -679,7 +679,7 @@ static void stm32serial_setapbclock(struct uart_dev_s *dev, bool on) { default: return; -#ifdef CONFIG_STM32N6_USART1_SERIALDRIVER +#ifdef CONFIG_STM32_USART1_SERIALDRIVER case STM32_USART1_BASE: rcc_en = RCC_APB2ENR_USART1EN; regaddr_set = STM32_RCC_APB2ENSR; @@ -752,7 +752,7 @@ static int stm32serial_setup(struct uart_dev_s *dev) { uint32_t config = priv->rts_gpio; -#ifdef CONFIG_STM32N6_FLOWCONTROL_BROKEN +#ifdef CONFIG_STM32_FLOWCONTROL_BROKEN /* Instead of letting hw manage this pin, we will bitbang */ config = (config & ~GPIO_MODE_MASK) | GPIO_OUTPUT; @@ -967,8 +967,8 @@ static int stm32serial_interrupt(int irq, void *context, void *arg) /* Report serial activity to the power management logic */ -#if defined(CONFIG_PM) && CONFIG_STM32N6_PM_SERIAL_ACTIVITY > 0 - pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32N6_PM_SERIAL_ACTIVITY); +#if defined(CONFIG_PM) && CONFIG_STM32_PM_SERIAL_ACTIVITY > 0 + pm_activity(PM_IDLE_DOMAIN, CONFIG_STM32_PM_SERIAL_ACTIVITY); #endif /* Loop until there are no characters to be transferred or, @@ -1321,7 +1321,7 @@ static bool stm32serial_rxflowcontrol(struct uart_dev_s *dev, (struct stm32_serial_s *)dev->priv; #if defined(CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS) && \ - defined(CONFIG_STM32N6_FLOWCONTROL_BROKEN) + defined(CONFIG_STM32_FLOWCONTROL_BROKEN) if (priv->iflow && (priv->rts_gpio != 0)) { /* Assert/de-assert nRTS set it high resume/stop sending */ @@ -1434,7 +1434,7 @@ static void stm32serial_txint(struct uart_dev_s *dev, bool enable) #ifndef CONFIG_SUPPRESS_SERIAL_INTS uint16_t ie = priv->ie | USART_CR1_TXEIE; -# ifdef CONFIG_STM32N6_SERIALBRK_BSDCOMPAT +# ifdef CONFIG_STM32_SERIALBRK_BSDCOMPAT if (priv->ie & USART_CR1_IE_BREAK_INPROGRESS) { leave_critical_section(flags); @@ -1679,7 +1679,7 @@ void arm_serialinit(void) #if CONSOLE_UART > 0 uart_register("/dev/console", &g_uart_devs[CONSOLE_UART - 1]->dev); -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* If not disabled, register the console UART to ttyS0 and exclude * it from initializing it further down */ @@ -1703,7 +1703,7 @@ void arm_serialinit(void) continue; } -#ifndef CONFIG_STM32N6_SERIAL_DISABLE_REORDERING +#ifndef CONFIG_STM32_SERIAL_DISABLE_REORDERING /* Don't create a device for the console - we did that above */ if (g_uart_devs[i]->dev.isconsole) diff --git a/arch/arm/src/stm32n6/stm32_start.c b/arch/arm/src/stm32n6/stm32_start.c index 3c7664921bb..c0f29e74371 100644 --- a/arch/arm/src/stm32n6/stm32_start.c +++ b/arch/arm/src/stm32n6/stm32_start.c @@ -205,7 +205,7 @@ void __start_c(void) STM32_RCC_BUSLPENSR); putreg32(RCC_MEMLPENR_ALLAXISRAM | RCC_MEMLPENR_CACHEAXIRAMLPEN, STM32_RCC_MEMLPENSR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 putreg32(RCC_APB2LPENR_USART1LPEN, STM32_RCC_APB2LPENSR); #endif @@ -233,7 +233,7 @@ void __start_c(void) (void)getreg32(STM32_SYSCFG_VDDCCCR); -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 /* Route USART1's kernel clock to HSI so the BRR computation is * independent of any later SYSCLK changes. */ diff --git a/arch/arm/src/stm32n6/stm32_uart.h b/arch/arm/src/stm32n6/stm32_uart.h index 2726f7fffaf..248e3f7d0af 100644 --- a/arch/arm/src/stm32n6/stm32_uart.h +++ b/arch/arm/src/stm32n6/stm32_uart.h @@ -40,20 +40,20 @@ /* Sanity checks */ -#if !defined(CONFIG_STM32N6_USART1) -# undef CONFIG_STM32N6_USART1_SERIALDRIVER -# undef CONFIG_STM32N6_USART1_1WIREDRIVER +#if !defined(CONFIG_STM32_USART1) +# undef CONFIG_STM32_USART1_SERIALDRIVER +# undef CONFIG_STM32_USART1_1WIREDRIVER #endif /* Is there a USART enabled? */ -#if defined(CONFIG_STM32N6_USART1) +#if defined(CONFIG_STM32_USART1) # define HAVE_UART 1 #endif /* Is there a serial console? */ -#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32N6_USART1_SERIALDRIVER) +#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1_SERIALDRIVER) # define CONSOLE_UART 1 # define HAVE_CONSOLE 1 #else diff --git a/arch/arm/src/stm32n6/stm32n6xx_rcc.c b/arch/arm/src/stm32n6/stm32n6xx_rcc.c index e1615178a76..e6ec3cad067 100644 --- a/arch/arm/src/stm32n6/stm32n6xx_rcc.c +++ b/arch/arm/src/stm32n6/stm32n6xx_rcc.c @@ -93,7 +93,7 @@ static inline void rcc_enableapb2(void) { uint32_t regval = 0; -#ifdef CONFIG_STM32N6_USART1 +#ifdef CONFIG_STM32_USART1 regval |= RCC_APB2ENR_USART1EN; #endif diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig index c5fb9d9dcbd..91975793f41 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/leds/defconfig @@ -10,6 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -30,7 +31,7 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y CONFIG_USERLED=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig index f18c05e1d62..0f35eb8c024 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/nsh/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -27,6 +28,6 @@ CONFIG_RAM_START=0x34000400 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig index 9e14513b6c7..772fa00937f 100644 --- a/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig +++ b/boards/arm/stm32n6/nucleo-n657x0-q/configs/ostest/defconfig @@ -9,6 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-n657x0-q" CONFIG_ARCH_BOARD_NUCLEO_N657X0_Q=y CONFIG_ARCH_CHIP="stm32n6" +CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32N657X0=y CONFIG_ARCH_CHIP_STM32N6=y CONFIG_ARCH_INTERRUPTSTACK=4096 @@ -30,7 +31,7 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y -CONFIG_STM32N6_USART1=y +CONFIG_STM32_USART1=y CONFIG_SYSTEM_NSH=y CONFIG_TESTING_OSTEST=y CONFIG_USART1_SERIAL_CONSOLE=y From 1282b94792767bf40cdb8fb50faf9051db0bda42 Mon Sep 17 00:00:00 2001 From: Serg Podtynnyi Date: Fri, 5 Jun 2026 00:01:37 +0700 Subject: [PATCH 095/268] arch/risc-v/rp23xx-rv: Add SMP support for dual Hazard3 Add SMP support to rp23xx risc-v port Signed-off-by: Serg Podtynnyi --- .../platforms/risc-v/rp23xx-rv/index.rst | 2 +- arch/risc-v/Kconfig | 4 +- arch/risc-v/src/common/riscv_cpuinfo.c | 6 + arch/risc-v/src/rp23xx-rv/CMakeLists.txt | 3 +- arch/risc-v/src/rp23xx-rv/Kconfig | 3 + arch/risc-v/src/rp23xx-rv/Make.defs | 2 +- arch/risc-v/src/rp23xx-rv/chip.h | 12 + .../src/rp23xx-rv/hardware/rp23xx_hazard3.h | 4 +- .../src/rp23xx-rv/hardware/rp23xx_memorymap.h | 2 - .../src/rp23xx-rv/hardware/rp23xx_psm.h | 2 +- .../src/rp23xx-rv/hardware/rp23xx_resets.h | 2 +- .../src/rp23xx-rv/hardware/rp23xx_sio.h | 2 +- .../hardware/rp23xx_usbctrl_dpsram.h | 2 +- .../rp23xx-rv/hardware/rp23xx_usbctrl_regs.h | 2 +- .../src/rp23xx-rv/rp23xx_cpuidlestack.c | 93 ----- arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c | 59 ++- arch/risc-v/src/rp23xx-rv/rp23xx_head.S | 5 +- arch/risc-v/src/rp23xx-rv/rp23xx_irq.c | 30 ++ arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c | 4 +- arch/risc-v/src/rp23xx-rv/rp23xx_start.c | 1 - arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c | 19 + arch/risc-v/src/rp23xx-rv/rp23xx_usbdev.c | 365 ++++++++++++------ .../configs/nsh-smp/defconfig | 52 +++ .../configs/nsh/defconfig | 7 +- .../configs/usbnsh-smp/defconfig | 58 +++ .../configs/usbnsh/defconfig | 10 +- 26 files changed, 487 insertions(+), 264 deletions(-) delete mode 100644 arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c create mode 100644 boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh-smp/defconfig create mode 100644 boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh-smp/defconfig diff --git a/Documentation/platforms/risc-v/rp23xx-rv/index.rst b/Documentation/platforms/risc-v/rp23xx-rv/index.rst index 01c6aac5ea2..22c5188a3f4 100644 --- a/Documentation/platforms/risc-v/rp23xx-rv/index.rst +++ b/Documentation/platforms/risc-v/rp23xx-rv/index.rst @@ -13,7 +13,7 @@ This is RISC-V version of the chip configuration. This port is experimental and still a work in progress. Use with caution. -SMP (dual core configuration not supported yet) +SMP is supported, two cores available. Peripheral Support ================== diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index a721da161db..9d07b61774d 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -448,13 +448,15 @@ config ARCH_CHIP_RP23XX_RV select ARCH_RV_ISA_C select ARCH_HAVE_RESET select ARCH_HAVE_MULTICPU + select ARCH_HAVE_MISALIGN_EXCEPTION select ARCH_HAVE_I2CRESET select ARCH_HAVE_TICKLESS + select ARCH_HAVE_DEBUG + select RISCV_STRING_FUNCTION select ONESHOT select ONESHOT_COUNT select ONESHOT_FAST_DIVISION select ALARM_ARCH - select ARCH_HAVE_I2CRESET select ARCH_BOARD_COMMON ---help--- Raspberry Pi RP23XX architectures (RISC-V dual Hazard3). diff --git a/arch/risc-v/src/common/riscv_cpuinfo.c b/arch/risc-v/src/common/riscv_cpuinfo.c index 3d1b8480e0c..aaf9e5170c2 100644 --- a/arch/risc-v/src/common/riscv_cpuinfo.c +++ b/arch/risc-v/src/common/riscv_cpuinfo.c @@ -46,6 +46,12 @@ ssize_t up_show_cpuinfo(char *buf, size_t buf_size, off_t file_off) { procfs_sprintf(buf, buf_size, &file_off, "processor\t: %d\n", i); procfs_sprintf(buf, buf_size, &file_off, "hart\t\t: %d\n", i); + procfs_sprintf(buf, buf_size, &file_off, "BogoMIPS\t: %u.%02u\n", + (CONFIG_BOARD_LOOPSPERMSEC / 1000), + (CONFIG_BOARD_LOOPSPERMSEC / 10) % 100); + procfs_sprintf(buf, buf_size, &file_off, "cpu MHz\t\t: %u.%03u\n", + CONFIG_ARCH_CPUINFO_FREQ_KHZ / 1000, + CONFIG_ARCH_CPUINFO_FREQ_KHZ % 1000); /* ISA */ diff --git a/arch/risc-v/src/rp23xx-rv/CMakeLists.txt b/arch/risc-v/src/rp23xx-rv/CMakeLists.txt index 7659ec5cbfa..898cd775f11 100644 --- a/arch/risc-v/src/rp23xx-rv/CMakeLists.txt +++ b/arch/risc-v/src/rp23xx-rv/CMakeLists.txt @@ -41,7 +41,8 @@ list( rp23xx_pll.c) if(CONFIG_SMP) - list(APPEND SRCS rp23xx_cpustart.c rp23xx_smpcall.c rp23xx_cpuidlestack.c) + list(REMOVE_ITEM SRCS riscv_smpcall.c riscv_cpustart.c) + list(APPEND SRCS rp23xx_cpustart.c rp23xx_smpcall.c) endif() if(CONFIG_RP23XX_RV_DMAC) diff --git a/arch/risc-v/src/rp23xx-rv/Kconfig b/arch/risc-v/src/rp23xx-rv/Kconfig index 5ff2509a777..86ae8bff0cc 100644 --- a/arch/risc-v/src/rp23xx-rv/Kconfig +++ b/arch/risc-v/src/rp23xx-rv/Kconfig @@ -5,6 +5,9 @@ comment "RP23XX Configuration Options" +config ARCH_RV_ISA_VENDOR_EXTENSIONS + default "zba_zbb_zbs_zbkb_zcb_zcmp" + config RP23XX_RV_RP2350B bool "Use RP2350B variant (QFN-80)" default n diff --git a/arch/risc-v/src/rp23xx-rv/Make.defs b/arch/risc-v/src/rp23xx-rv/Make.defs index faee3864e6d..5ed35797837 100644 --- a/arch/risc-v/src/rp23xx-rv/Make.defs +++ b/arch/risc-v/src/rp23xx-rv/Make.defs @@ -42,9 +42,9 @@ CHIP_CSRCS += rp23xx_xosc.c CHIP_CSRCS += rp23xx_pll.c ifeq ($(CONFIG_SMP),y) +CMN_CSRCS := $(filter-out riscv_smpcall.c riscv_cpustart.c, $(CMN_CSRCS)) CHIP_CSRCS += rp23xx_cpustart.c CHIP_CSRCS += rp23xx_smpcall.c -CHIP_CSRCS += rp23xx_cpuidlestack.c endif ifeq ($(CONFIG_RP23XX_RV_DMAC),y) diff --git a/arch/risc-v/src/rp23xx-rv/chip.h b/arch/risc-v/src/rp23xx-rv/chip.h index 975d1a87ec1..541b6553136 100644 --- a/arch/risc-v/src/rp23xx-rv/chip.h +++ b/arch/risc-v/src/rp23xx-rv/chip.h @@ -37,11 +37,23 @@ #include +#include "riscv_internal.h" + /**************************************************************************** * Macro Definitions ****************************************************************************/ #ifdef __ASSEMBLY__ +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 +.macro setintstack tmp0, tmp1 + up_cpu_index \tmp0 + li \tmp1, STACKFRAME_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK) + mul \tmp1, \tmp0, \tmp1 + la \tmp0, g_intstacktop + sub sp, \tmp0, \tmp1 +.endm +#endif /* CONFIG_SMP && CONFIG_ARCH_INTERRUPTSTACK > 15 */ + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_RISCV_SRC_RP23XX_RV_CHIP_H */ diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h index ae8bfdb0c1a..e0d040fc8b1 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_hazard3.h @@ -27,11 +27,13 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +#define hazard3_block() __asm__ volatile ("slt x0, x0, x0" ::: "memory") +#define hazard3_unblock() __asm__ volatile ("slt x0, x0, x1" ::: "memory") #define hazard3_irqarray_read(csr, index) (READ_AND_SET_CSR(csr, (index)) >> 16) #define hazard3_irqarray_write(csr, index, data) (WRITE_CSR(csr, (index) | ((uint32_t)(data) << 16))) diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h index cfbf668803c..7446fe301f9 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_memorymap.h @@ -26,8 +26,6 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h index e31a12408e8..725f8e5baed 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_psm.h @@ -27,7 +27,7 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h index 0f8f7020f78..a39d5b52209 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_resets.h @@ -27,7 +27,7 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h index c4bc859e6a1..60efe7c38c9 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_sio.h @@ -27,7 +27,7 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h index ed6f8569aeb..df941b7a213 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_dpsram.h @@ -27,7 +27,7 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h index 31ac8085fae..4390de3b1e4 100644 --- a/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h +++ b/arch/risc-v/src/rp23xx-rv/hardware/rp23xx_usbctrl_regs.h @@ -27,7 +27,7 @@ * Included Files ****************************************************************************/ -#include "hardware/rp23xx_memorymap.h" +#include "rp23xx_memorymap.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c b/arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c deleted file mode 100644 index 62e3de7cdbe..00000000000 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c +++ /dev/null @@ -1,93 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/rp23xx-rv/rp23xx_cpuidlestack.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "riscv_internal.h" - -#ifdef CONFIG_SMP - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_cpu_idlestack - * - * Description: - * Allocate a stack for the CPU[n] IDLE task (n > 0) if appropriate and - * setup up stack-related information in the IDLE task's TCB. This - * function is always called before up_cpu_start(). This function is - * only called for the CPU's initial IDLE task; up_create_task is used for - * all normal tasks, pthreads, and kernel threads for all CPUs. - * - * The initial IDLE task is a special case because the CPUs can be started - * in different wans in different environments: - * - * 1. The CPU may already have been started and waiting in a low power - * state for up_cpu_start(). In this case, the IDLE thread's stack - * has already been allocated and is already in use. Here - * up_cpu_idlestack() only has to provide information about the - * already allocated stack. - * - * 2. The CPU may be disabled but started when up_cpu_start() is called. - * In this case, a new stack will need to be created for the IDLE - * thread and this function is then equivalent to: - * - * return up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); - * - * The following TCB fields must be initialized by this function: - * - * - adj_stack_size: Stack size after adjustment for hardware, processor, - * etc. This value is retained only for debug purposes. - * - stack_alloc_ptr: Pointer to allocated stack - * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and - * Arguments has been removed from the stack allocation. - * - * Input Parameters: - * - cpu: CPU index that indicates which CPU the IDLE task is - * being created for. - * - tcb: The TCB of new CPU IDLE task - * - stack_size: The requested stack size for the IDLE task. At least - * this much must be allocated. This should be - * CONFIG_SMP_STACK_SIZE. - * - ****************************************************************************/ - -int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) -{ -#if CONFIG_SMP_NCPUS > 1 - up_create_stack(tcb, stack_size, TCB_FLAG_TTYPE_KERNEL); -#endif - return OK; -} - -#endif /* CONFIG_SMP */ diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c b/arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c index 9d0b4db808f..493ba5e9fd7 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_cpustart.c @@ -26,21 +26,15 @@ #include -#include -#include #include -#include -#include -#include #include +#include #include -#include "nvic.h" #include "sched/sched.h" #include "init/init.h" -#include "riscv_internal.h" -#include "hardware/rp23xx_memorymap.h" +#include "hardware/rp23xx_hazard3.h" #include "hardware/rp23xx_sio.h" #include "hardware/rp23xx_psm.h" @@ -62,14 +56,14 @@ # define showprogress(c) #endif +#define CORE1_BOOT_MSG_LEN 6 + /**************************************************************************** * Public Data ****************************************************************************/ static volatile bool g_core1_boot; -extern int rp23xx_smp_call_handler(int irq, void *c, void *arg); - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -90,7 +84,7 @@ static void fifo_drain(void) getreg32(RP23XX_SIO_FIFO_RD); } - __asm__ volatile ("sev"); + hazard3_unblock(); } /**************************************************************************** @@ -114,14 +108,14 @@ static int fifo_comm(uint32_t msg) while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_RDY)) ; putreg32(msg, RP23XX_SIO_FIFO_WR); - __asm__ volatile ("sev"); + hazard3_unblock(); while (!(getreg32(RP23XX_SIO_FIFO_ST) & RP23XX_SIO_FIFO_ST_VLD)) - __asm__ volatile ("wfe"); + hazard3_block(); rcv = getreg32(RP23XX_SIO_FIFO_RD); - return msg == rcv; + return (msg == rcv); } /**************************************************************************** @@ -138,25 +132,23 @@ static int fifo_comm(uint32_t msg) static void core1_boot(void) { -#if CONFIG_ARCH_INTERRUPTSTACK > 3 - /* Initializes the stack pointer */ - - riscv_initialize_stack(); -#endif - fifo_drain(); - /* Setup NVIC */ - up_irqinitialize(); + /* Per-core timer: enable MTIMER interrupt */ + + up_timer_initialize(); + /* Enable inter-processor FIFO interrupt */ - irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL); + irq_attach(RP23XX_SIO_IRQ_FIFO, riscv_smp_call_handler, NULL); up_enable_irq(RP23XX_SIO_IRQ_FIFO); g_core1_boot = true; + UP_DMB(); + #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that this CPU has started */ @@ -203,7 +195,7 @@ int up_cpu_start(int cpu) { int i; struct tcb_s *tcb = current_task(cpu); - uint32_t core1_boot_msg[5]; + uint32_t core1_boot_msg[CORE1_BOOT_MSG_LEN]; DPRINTF("cpu=%d\n", cpu); @@ -220,19 +212,18 @@ int up_cpu_start(int cpu) ; clrbits_reg32(RP23XX_PSM_PROC1, RP23XX_PSM_FRCE_OFF); - /* Send initial VTOR, MSP, PC for Core 1 boot */ - core1_boot_msg[0] = 0; - core1_boot_msg[1] = 1; - core1_boot_msg[2] = getreg32(NVIC_VECTAB); - core1_boot_msg[3] = (uint32_t)tcb->stack_base_ptr + + core1_boot_msg[1] = 0; + core1_boot_msg[2] = 1; + core1_boot_msg[3] = READ_CSR(CSR_MTVEC); + core1_boot_msg[4] = (uint32_t)tcb->stack_base_ptr + tcb->adj_stack_size; - core1_boot_msg[4] = (uint32_t)core1_boot; + core1_boot_msg[5] = (uint32_t)core1_boot; do { fifo_drain(); - for (i = 0; i < 5; i++) + for (i = 0; i < CORE1_BOOT_MSG_LEN; i++) { if (!fifo_comm(core1_boot_msg[i])) { @@ -240,15 +231,17 @@ int up_cpu_start(int cpu) } } } - while (i < 5); + while (i < CORE1_BOOT_MSG_LEN); fifo_drain(); /* Enable inter-processor FIFO interrupt */ - irq_attach(RP23XX_SIO_IRQ_FIFO, rp23xx_smp_call_handler, NULL); + irq_attach(RP23XX_SIO_IRQ_FIFO, riscv_smp_call_handler, NULL); up_enable_irq(RP23XX_SIO_IRQ_FIFO); + /* Spin until Core 1 signals that it has finished its initialisation */ + while (!g_core1_boot); /* CPU Core 1 boot done */ diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_head.S b/arch/risc-v/src/rp23xx-rv/rp23xx_head.S index 64eb67ab340..772545d8004 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_head.S +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_head.S @@ -30,14 +30,13 @@ #include "chip.h" #include "hardware/rp23xx_memorymap.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols ****************************************************************************/ - /* Imported symbols */ - - .extern __trap_vec + /* Exported Symbols */ .section .text .global __start diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_irq.c b/arch/risc-v/src/rp23xx-rv/rp23xx_irq.c index 4d706fd95bb..f9e40cc3cb1 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_irq.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_irq.c @@ -47,6 +47,10 @@ * Public Data ****************************************************************************/ +#ifdef CONFIG_SMP +extern void rp23xx_send_irqreq(int irqreq); +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -91,6 +95,17 @@ void up_irqinitialize(void) void up_enable_irq(int irq) { +#ifdef CONFIG_SMP + if (irq >= RP23XX_IRQ_EXTINT && irq != RP23XX_SIO_IRQ_FIFO && + this_cpu() != 0) + { + /* Must be handled by Core 0 */ + + rp23xx_send_irqreq(irq); + return; + } +#endif + if (irq == RISCV_IRQ_MSOFT) { /* Read mstatus & set machine software interrupt enable in mie */ @@ -114,6 +129,8 @@ void up_enable_irq(int irq) hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); hazard3_irqarray_set(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); } + + UP_DMB(); } /**************************************************************************** @@ -126,6 +143,17 @@ void up_enable_irq(int irq) void up_disable_irq(int irq) { +#ifdef CONFIG_SMP + if (irq >= RP23XX_IRQ_EXTINT && irq != RP23XX_SIO_IRQ_FIFO && + this_cpu() != 0) + { + /* Must be handled by Core 0 */ + + rp23xx_send_irqreq(-irq); + return; + } +#endif + if (irq == RISCV_IRQ_MSOFT) { /* Read mstatus & clear machine software interrupt enable in mie */ @@ -147,6 +175,8 @@ void up_disable_irq(int irq) hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n, mask & 0xffffu); hazard3_irqarray_clear(RVCSR_MEIEA_OFFSET, 2 * n + 1, mask >> 16); } + + UP_DMB(); } /**************************************************************************** diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c b/arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c index 7a4774b3f50..0ac60dbf852 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_smpcall.c @@ -83,7 +83,7 @@ static void rp23xx_handle_irqreq(int irqreq) ****************************************************************************/ /**************************************************************************** - * Name: rp23xx_smp_call_handler + * Name: riscv_smp_call_handler * * Description: * This is the handler for SMP_CALL. @@ -93,7 +93,7 @@ static void rp23xx_handle_irqreq(int irqreq) * ****************************************************************************/ -int rp23xx_smp_call_handler(int irq, void *c, void *arg) +int riscv_smp_call_handler(int irq, void *c, void *arg) { int cpu = this_cpu(); int irqreq; diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_start.c b/arch/risc-v/src/rp23xx-rv/rp23xx_start.c index 12669a62fd8..58dbb7def13 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_start.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_start.c @@ -34,7 +34,6 @@ #include #include -#include "riscv_internal.h" #include "rp23xx_config.h" #include "rp23xx_clock.h" #include "rp23xx_uart.h" diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c b/arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c index 2a0ae5dcd81..364e25e272a 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_timerisr.c @@ -64,9 +64,26 @@ void up_timer_initialize(void) { +#ifdef CONFIG_SMP + if (this_cpu() != 0) + { + up_enable_irq(RISCV_IRQ_MTIMER); + return; + } +#endif + + /* Core 0: full timer initialisation */ + + /* Stop the timer and reset the counter while we configure it */ + putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIME_CTRL_OFFSET); putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIME_OFFSET); putreg32(0, RP23XX_SIO_BASE + RP23XX_SIO_MTIMEH_OFFSET); + + /* Initialise compare registers to maximum so no interrupts fire + * before the alarm subsystem sets the first real deadline. + */ + putreg32(RP23XX_SIO_MTIMECMP_MASK, RP23XX_SIO_BASE + RP23XX_SIO_MTIMECMP_OFFSET); putreg32(RP23XX_SIO_MTIMECMPH_MASK, @@ -81,6 +98,8 @@ void up_timer_initialize(void) up_alarm_set_lowerhalf(lower); + /* Start the counter at full system-clock rate */ + putreg32(RP23XX_SIO_MTIME_CTRL_EN | RP23XX_SIO_MTIME_CTRL_FULLSPEED, RP23XX_SIO_BASE + RP23XX_SIO_MTIME_CTRL_OFFSET); } diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_usbdev.c b/arch/risc-v/src/rp23xx-rv/rp23xx_usbdev.c index 5718ae7a1af..01d69f0937f 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_usbdev.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_usbdev.c @@ -33,11 +33,13 @@ #include #include #include +#include #include #include #include #include + #include #include #include @@ -45,6 +47,7 @@ #include "chip.h" #include "riscv_internal.h" #include "rp23xx_usbdev.h" +#include "hardware/rp23xx_hazard3.h" #include "hardware/rp23xx_resets.h" @@ -320,7 +323,10 @@ static int rp23xx_epread(struct rp23xx_ep_s *privep, uint16_t nbytes); static void rp23xx_abortrequest(struct rp23xx_ep_s *privep, struct rp23xx_req_s *privreq, int16_t result); -static void rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result); +static struct rp23xx_req_s * +rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result); +static void rp23xx_callback(struct rp23xx_ep_s *privep, + struct rp23xx_req_s *callback_req); static void rp23xx_txcomplete(struct rp23xx_ep_s *privep); static int rp23xx_wrrequest(struct rp23xx_ep_s *privep); static void rp23xx_rxcomplete(struct rp23xx_ep_s *privep); @@ -471,19 +477,15 @@ static void rp23xx_update_buffer_control(struct rp23xx_ep_s *privep, uint32_t and_mask, uint32_t or_mask) { - uint32_t value = 0; - - if (and_mask) + if (and_mask == 0) { - value = getreg32(privep->buf_ctrl) & and_mask; + putreg32(or_mask, privep->buf_ctrl); } - - if (or_mask) + else { - value |= or_mask; + uint32_t value = getreg32(privep->buf_ctrl); + putreg32((value & and_mask) | or_mask, privep->buf_ctrl); } - - putreg32(value, privep->buf_ctrl); } /**************************************************************************** @@ -498,11 +500,15 @@ static int rp23xx_epwrite(struct rp23xx_ep_s *privep, uint8_t *buf, uint16_t nbytes) { uint32_t val; - irqstate_t flags; /* Copy the transmit data into DPSRAM */ - memcpy(privep->data_buf, buf, nbytes); + if (nbytes > 0) + { + memcpy(privep->data_buf, buf, nbytes); + } + + UP_DMB(); val = nbytes | RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL | @@ -510,13 +516,11 @@ static int rp23xx_epwrite(struct rp23xx_ep_s *privep, uint8_t *buf, (privep->next_pid ? RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID : 0); - privep->next_pid = 1 - privep->next_pid; /* Invert DATA0 <-> DATA1 */ - /* Start the transfer */ - flags = spin_lock_irqsave(&g_usbdev.lock); + privep->next_pid = 1 - privep->next_pid; + rp23xx_update_buffer_control(privep, 0, val); - spin_unlock_irqrestore(&g_usbdev.lock, flags); return nbytes; } @@ -532,20 +536,17 @@ static int rp23xx_epwrite(struct rp23xx_ep_s *privep, uint8_t *buf, static int rp23xx_epread(struct rp23xx_ep_s *privep, uint16_t nbytes) { uint32_t val; - irqstate_t flags; val = nbytes | RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_AVAIL | (privep->next_pid ? RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_DATA1_PID : 0); - privep->next_pid = 1 - privep->next_pid; /* Invert DATA0 <-> DATA1 */ - /* Start the transfer */ - flags = spin_lock_irqsave(&g_usbdev.lock); + privep->next_pid = 1 - privep->next_pid; + rp23xx_update_buffer_control(privep, 0, val); - spin_unlock_irqrestore(&g_usbdev.lock, flags); return OK; } @@ -582,29 +583,17 @@ static void rp23xx_abortrequest(struct rp23xx_ep_s *privep, * ****************************************************************************/ -static void rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result) +static struct rp23xx_req_s * +rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result) { struct rp23xx_req_s *privreq; - int stalled = privep->stalled; - irqstate_t flags; /* Remove the completed request at the head of the endpoint request list */ - flags = enter_critical_section(); privreq = rp23xx_rqdequeue(privep); - leave_critical_section(flags); if (privreq) { - /* If endpoint 0, temporarily reflect the state of protocol stalled - * in the callback. - */ - - if (privep->epphy == 0) - { - privep->stalled = privep->dev->stalled; - } - /* Save the result in the request structure */ privreq->req.result = result; @@ -612,12 +601,9 @@ static void rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result) /* Callback to the request completion handler */ privreq->flink = NULL; - privreq->req.callback(&privep->ep, &privreq->req); - - /* Restore the stalled indication */ - - privep->stalled = stalled; } + + return privreq; } /**************************************************************************** @@ -631,8 +617,14 @@ static void rp23xx_reqcomplete(struct rp23xx_ep_s *privep, int16_t result) static void rp23xx_txcomplete(struct rp23xx_ep_s *privep) { struct rp23xx_req_s *privreq; + irqstate_t flags; + + flags = spin_lock_irqsave(&g_usbdev.lock); privreq = rp23xx_rqpeek(privep); + + struct rp23xx_req_s *callback_req = NULL; + if (!privreq) { usbtrace(TRACE_DEVERROR(RP23XX_TRACEERR_TXREQLOST), privep->epphy); @@ -646,11 +638,42 @@ static void rp23xx_txcomplete(struct rp23xx_ep_s *privep) { usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); privep->txnullpkt = 0; - rp23xx_reqcomplete(privep, OK); + callback_req = rp23xx_reqcomplete(privep, OK); } } rp23xx_wrrequest(privep); + spin_unlock_irqrestore(&g_usbdev.lock, flags); + + rp23xx_callback(privep, callback_req); +} + +/**************************************************************************** + * Name: rp23xx_callback + * + * Description: + * Call req callback + * + ****************************************************************************/ + +static void rp23xx_callback(struct rp23xx_ep_s *privep, + struct rp23xx_req_s *callback_req) +{ + irqstate_t flags; + + if (callback_req && callback_req->req.callback) + { + /* Pass protocol stall state to EP0 callbacks */ + + if (privep->epphy == 0) + { + flags = spin_lock_irqsave(&g_usbdev.lock); + privep->stalled = privep->dev->stalled; + spin_unlock_irqrestore(&g_usbdev.lock, flags); + } + + callback_req->req.callback(&privep->ep, &callback_req->req); + } } /**************************************************************************** @@ -677,22 +700,6 @@ static int rp23xx_wrrequest(struct rp23xx_ep_s *privep) return OK; } - /* Ignore any attempt to send a zero length packet on anything but EP0IN */ - - if (privreq->req.len == 0) - { - if (privep->epphy == 0) - { - rp23xx_epwrite(privep, NULL, 0); - } - else - { - usbtrace(TRACE_DEVERROR(RP23XX_TRACEERR_NULLPACKET), 0); - } - - return OK; - } - /* Get the number of bytes left to be sent in the packet */ bytesleft = privreq->req.len - privreq->req.xfrd; @@ -702,7 +709,7 @@ static int rp23xx_wrrequest(struct rp23xx_ep_s *privep) */ usbtrace(TRACE_WRITE(privep->epphy), (uint16_t)bytesleft); - if (bytesleft > 0 || privep->txnullpkt) + if (bytesleft > 0 || privep->txnullpkt || privreq->req.len == 0) { /* Try to send maxpacketsize -- unless we don't have that many * bytes to send. @@ -743,29 +750,48 @@ static void rp23xx_rxcomplete(struct rp23xx_ep_s *privep) { struct rp23xx_req_s *privreq; uint16_t nrxbytes; + uint16_t available; + uint16_t copy_len; + irqstate_t flags; + struct rp23xx_req_s *callback_req = NULL; nrxbytes = getreg32(privep->buf_ctrl) & RP23XX_USBCTRL_DPSRAM_EP_BUFF_CTRL_LEN_MASK; + flags = spin_lock_irqsave(&g_usbdev.lock); + privreq = rp23xx_rqpeek(privep); if (!privreq) { + spin_unlock_irqrestore(&g_usbdev.lock, flags); usbtrace(TRACE_DEVERROR(RP23XX_TRACEERR_RXREQLOST), privep->epphy); return; } - memcpy(privreq->req.buf + privreq->req.xfrd, privep->data_buf, nrxbytes); + available = privreq->req.len - privreq->req.xfrd; + copy_len = MIN(nrxbytes, available); - privreq->req.xfrd += nrxbytes; + memcpy(privreq->req.buf + privreq->req.xfrd, privep->data_buf, copy_len); + privreq->req.xfrd += copy_len; + + if (nrxbytes > available) + { + usbtrace(TRACE_DEVERROR(RP23XX_TRACEERR_EPREAD), privep->epphy); + privreq->req.result = -EIO; + } if (privreq->req.xfrd >= privreq->req.len || nrxbytes < privep->ep.maxpacket) { usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); - rp23xx_reqcomplete(privep, OK); + callback_req = + rp23xx_reqcomplete(privep, privreq->req.result == -EIO ? -EIO : OK); } rp23xx_rdrequest(privep); + spin_unlock_irqrestore(&g_usbdev.lock, flags); + + rp23xx_callback(privep, callback_req); } /**************************************************************************** @@ -846,6 +872,35 @@ static void rp23xx_handle_zlp(struct rp23xx_usbdev_s *priv) priv->zlp_stat = RP23XX_ZLP_NONE; } +static void rp23xx_drain_queue(struct rp23xx_ep_s *privep, + struct rp23xx_req_s **list_head) +{ + struct rp23xx_req_s *privreq; + struct rp23xx_req_s *tail = NULL; + + while (!rp23xx_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (rp23xx_rqpeek(privep))->req.xfrd); + privreq = rp23xx_rqdequeue(privep); + if (privreq) + { + privreq->req.result = -ESHUTDOWN; + privreq->flink = NULL; + if (!*list_head) + { + *list_head = privreq; + } + else + { + tail->flink = privreq; + } + + tail = privreq; + } + } +} + /**************************************************************************** * Name: rp23xx_cancelrequests * @@ -856,11 +911,23 @@ static void rp23xx_handle_zlp(struct rp23xx_usbdev_s *priv) static void rp23xx_cancelrequests(struct rp23xx_ep_s *privep) { - while (!rp23xx_rqempty(privep)) + struct rp23xx_req_s *local_list = NULL; + struct rp23xx_req_s *next; + irqstate_t flags; + + flags = spin_lock_irqsave(&g_usbdev.lock); + rp23xx_drain_queue(privep, &local_list); + spin_unlock_irqrestore(&g_usbdev.lock, flags); + + while (local_list) { - usbtrace(TRACE_COMPLETE(privep->epphy), - (rp23xx_rqpeek(privep))->req.xfrd); - rp23xx_reqcomplete(privep, -ESHUTDOWN); + next = local_list->flink; + if (local_list->req.callback) + { + local_list->req.callback(&privep->ep, &local_list->req); + } + + local_list = next; } } @@ -1209,16 +1276,17 @@ static void rp23xx_usbintr_setup(struct rp23xx_usbdev_s *priv) /* Read USB control request data */ + UP_DMB(); memcpy(&priv->ctrl, (void *)RP23XX_USBCTRL_DPSRAM_SETUP_PACKET, USB_SIZEOF_CTRLREQ); len = GETUINT16(priv->ctrl.len); /* Reset PID and stall status in setup stage */ + rp23xx_epstall(&priv->eplist[0].ep, true); + rp23xx_epstall(&priv->eplist[1].ep, true); priv->eplist[0].next_pid = 1; priv->eplist[1].next_pid = 1; - priv->eplist[0].stalled = false; - priv->eplist[1].stalled = false; /* ZLP type in status stage */ @@ -1264,6 +1332,7 @@ static void rp23xx_usbintr_ep0out(struct rp23xx_usbdev_s *priv, return; } + UP_DMB(); memcpy(priv->ep0data + priv->ep0datlen, privep->data_buf, len); priv->ep0datlen += len; @@ -1307,7 +1376,7 @@ static bool rp23xx_usbintr_buffstat(struct rp23xx_usbdev_s *priv) { if (stat & bit) { - clrbits_reg32(bit, RP23XX_USBCTRL_REGS_BUFF_STATUS); + putreg32(bit, RP23XX_USBCTRL_REGS_BUFF_STATUS); privep = &priv->eplist[RP23XX_DPTOEP(i)]; if (i == 1) @@ -1382,7 +1451,7 @@ static void rp23xx_usbintr_busreset(struct rp23xx_usbdev_s *priv) CLASS_DISCONNECT(priv->driver, &priv->usbdev); } - clrbits_reg32(RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET, + putreg32(RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET, RP23XX_USBCTRL_REGS_SIE_STATUS); } @@ -1411,7 +1480,7 @@ static int rp23xx_usbinterrupt(int irq, void *context, void *arg) if (stat & RP23XX_USBCTRL_REGS_INTR_SETUP_REQ) { - clrbits_reg32(RP23XX_USBCTRL_REGS_SIE_STATUS_SETUP_REC, + putreg32(RP23XX_USBCTRL_REGS_SIE_STATUS_SETUP_REC, RP23XX_USBCTRL_REGS_SIE_STATUS); rp23xx_usbintr_setup(priv); @@ -1419,7 +1488,7 @@ static int rp23xx_usbinterrupt(int irq, void *context, void *arg) if (stat & RP23XX_USBCTRL_REGS_INTR_BUS_RESET) { - clrbits_reg32(RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET, + putreg32(RP23XX_USBCTRL_REGS_SIE_STATUS_BUS_RESET, RP23XX_USBCTRL_REGS_SIE_STATUS); rp23xx_usbintr_busreset(priv); @@ -1466,10 +1535,7 @@ static int rp23xx_epconfigure(struct usbdev_ep_s *ep, uinfo("config: EP%d %s %d maxpacket=%d\n", privep->epphy, privep->in ? "IN" : "OUT", eptype, maxpacket); - if (desc) - { - privep->ep.maxpacket = GETUINT16(desc->mxpacketsize); - } + privep->ep.maxpacket = GETUINT16(desc->mxpacketsize); if (privep->epphy != 0) { @@ -1477,10 +1543,14 @@ static int rp23xx_epconfigure(struct usbdev_ep_s *ep, * (No need for EP0 because it has the dedicated buffer) */ - privep->data_buf = (uint8_t *)(RP23XX_USBCTRL_DPSRAM_BASE + - priv->next_offset); - priv->next_offset = - (priv->next_offset + privep->ep.maxpacket + 63) & ~63; + if (privep->data_buf == NULL) + { + privep->data_buf = (uint8_t *)(RP23XX_USBCTRL_DPSRAM_BASE + + priv->next_offset); + priv->next_offset = + (priv->next_offset + + privep->ep.maxpacket + 63) & ~63; + } /* Enable EP */ @@ -1506,6 +1576,8 @@ static int rp23xx_epconfigure(struct usbdev_ep_s *ep, static int rp23xx_epdisable(struct usbdev_ep_s *ep) { struct rp23xx_ep_s *privep = (struct rp23xx_ep_s *)ep; + struct rp23xx_req_s *local_list = NULL; + struct rp23xx_req_s *next; irqstate_t flags; #ifdef CONFIG_DEBUG_FEATURES @@ -1519,18 +1591,28 @@ static int rp23xx_epdisable(struct usbdev_ep_s *ep) usbtrace(TRACE_EPDISABLE, privep->epphy); uinfo("EP%d\n", privep->epphy); - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_usbdev.lock); - privep->ep.maxpacket = 64; + privep->ep.maxpacket = RP23XX_EP0MAXPACKET; privep->stalled = false; privep->next_pid = 0; putreg32(0, privep->buf_ctrl); /* Cancel all queued requests */ - rp23xx_cancelrequests(privep); + rp23xx_drain_queue(privep, &local_list); + spin_unlock_irqrestore(&g_usbdev.lock, flags); - leave_critical_section(flags); + while (local_list) + { + next = local_list->flink; + if (local_list->req.callback) + { + local_list->req.callback(&privep->ep, &local_list->req); + } + + local_list = next; + } return OK; } @@ -1623,12 +1705,13 @@ static int rp23xx_epsubmit(struct usbdev_ep_s *ep, req->result = -EINPROGRESS; req->xfrd = 0; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&g_usbdev.lock); if (privep->stalled && privep->in) { + spin_unlock_irqrestore(&g_usbdev.lock, flags); rp23xx_abortrequest(privep, privreq, -EBUSY); - ret = -EBUSY; + return -EBUSY; } /* Handle IN (device-to-host) requests */ @@ -1668,7 +1751,7 @@ static int rp23xx_epsubmit(struct usbdev_ep_s *ep, } } - leave_critical_section(flags); + spin_unlock_irqrestore(&g_usbdev.lock, flags); return ret; } @@ -1676,14 +1759,18 @@ static int rp23xx_epsubmit(struct usbdev_ep_s *ep, * Name: rp23xx_epcancel * * Description: - * Cancel an I/O request previously sent to an endpoint + * Cancel an I/O request previously sent to an endpoint * ****************************************************************************/ -static int rp23xx_epcancel(struct usbdev_ep_s *ep, - struct usbdev_req_s *req) +static int rp23xx_epcancel(struct usbdev_ep_s *ep, struct usbdev_req_s *req) { struct rp23xx_ep_s *privep = (struct rp23xx_ep_s *)ep; + struct rp23xx_req_s *privreq = (struct rp23xx_req_s *)req; + struct rp23xx_req_s *curr; + struct rp23xx_req_s *prev = NULL; + bool found = false; + bool is_head = false; irqstate_t flags; #ifdef CONFIG_DEBUG_FEATURES @@ -1696,12 +1783,64 @@ static int rp23xx_epcancel(struct usbdev_ep_s *ep, usbtrace(TRACE_EPCANCEL, privep->epphy); - /* Remove request from req_queue */ + flags = spin_lock_irqsave(&g_usbdev.lock); - flags = enter_critical_section(); - rp23xx_cancelrequests(privep); - leave_critical_section(flags); - return OK; + for (curr = privep->head; curr != NULL; prev = curr, curr = curr->flink) + { + if (curr == privreq) + { + found = true; + break; + } + } + + if (found) + { + if (curr == privep->head) + { + is_head = true; + + putreg32(0, privep->buf_ctrl); + + privep->head = curr->flink; + if (!privep->head) + { + privep->tail = NULL; + } + } + else + { + prev->flink = curr->flink; + if (privep->tail == curr) + { + privep->tail = prev; + } + } + + curr->flink = NULL; + curr->req.result = -ECANCELED; + + if (is_head && privep->head != NULL) + { + if (privep->in) + { + rp23xx_wrrequest(privep); + } + else + { + rp23xx_rdrequest(privep); + } + } + } + + spin_unlock_irqrestore(&g_usbdev.lock, flags); + + if (found && privreq->req.callback) + { + privreq->req.callback(&privep->ep, &privreq->req); + } + + return found ? OK : -ENOENT; } /**************************************************************************** @@ -1985,7 +2124,7 @@ static int rp23xx_pullup(struct usbdev_s *dev, bool enable) ****************************************************************************/ /**************************************************************************** - * Name: riscv_usbinitialize + * Name: rp23xx_usbinitialize * * Description: * Initialize the USB driver @@ -2020,7 +2159,7 @@ void rp23xx_usbinitialize(void) for (i = 0; i < RP23XX_NENDPOINTS; i++) { g_usbdev.eplist[i].ep.ops = &g_epops; - g_usbdev.eplist[i].ep.maxpacket = 64; + g_usbdev.eplist[i].ep.maxpacket = RP23XX_EP0MAXPACKET; g_usbdev.eplist[i].dev = &g_usbdev; g_usbdev.eplist[i].epphy = 0; g_usbdev.eplist[i].head = NULL; @@ -2075,13 +2214,29 @@ int usbdev_register(struct usbdevclass_driver_s *driver) memset((void *)RP23XX_USBCTRL_DPSRAM_BASE, 0, 0x1000); - putreg32(RP23XX_USBCTRL_REGS_USB_MUXING_SOFTCON | + /* Enable interrupt */ + + up_enable_irq(RP23XX_USBCTRL_IRQ); + + setbits_reg32(RP23XX_USBCTRL_REGS_USB_MUXING_SOFTCON | RP23XX_USBCTRL_REGS_USB_MUXING_TO_PHY, RP23XX_USBCTRL_REGS_USB_MUXING); - putreg32(RP23XX_USBCTRL_REGS_USB_PWR_VBUS_DETECT | + + setbits_reg32(RP23XX_USBCTRL_REGS_USB_PWR_VBUS_DETECT | RP23XX_USBCTRL_REGS_USB_PWR_VBUS_DETECT_OVERRIDE_EN, RP23XX_USBCTRL_REGS_USB_PWR); + setbits_reg32(RP23XX_USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN, + RP23XX_USBCTRL_REGS_MAIN_CTRL); + + setbits_reg32(RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF, + RP23XX_USBCTRL_REGS_SIE_CTRL); + + setbits_reg32(RP23XX_USBCTRL_REGS_INTR_BUFF_STATUS | + RP23XX_USBCTRL_REGS_INTR_BUS_RESET | + RP23XX_USBCTRL_REGS_INTR_SETUP_REQ, + RP23XX_USBCTRL_REGS_INTE); + rp23xx_allocep(&g_usbdev.usbdev, 0x00, 0, USB_EP_ATTR_XFER_CONTROL); rp23xx_allocep(&g_usbdev.usbdev, 0x80, 1, USB_EP_ATTR_XFER_CONTROL); @@ -2100,20 +2255,6 @@ int usbdev_register(struct usbdevclass_driver_s *driver) modifyreg32(RP23XX_USBCTRL_REGS_MAIN_CTRL, RP23XX_USBCTRL_REGS_MAIN_CTRL_PHY_ISO, 0); - putreg32(RP23XX_USBCTRL_REGS_MAIN_CTRL_CONTROLLER_EN, - RP23XX_USBCTRL_REGS_MAIN_CTRL); - - /* Enable interrupt */ - - putreg32(RP23XX_USBCTRL_REGS_SIE_CTRL_EP0_INT_1BUF, - RP23XX_USBCTRL_REGS_SIE_CTRL); - putreg32(RP23XX_USBCTRL_REGS_INTR_BUFF_STATUS | - RP23XX_USBCTRL_REGS_INTR_BUS_RESET | - RP23XX_USBCTRL_REGS_INTR_SETUP_REQ, - RP23XX_USBCTRL_REGS_INTE); - - up_enable_irq(RP23XX_USBCTRL_IRQ); - return OK; } diff --git a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh-smp/defconfig b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh-smp/defconfig new file mode 100644 index 00000000000..26495face95 --- /dev/null +++ b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh-smp/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="raspberrypi-pico-2-rv" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO_2_RV=y +CONFIG_ARCH_CHIP="rp23xx-rv" +CONFIG_ARCH_CHIP_RP23XX_RV=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb_zcmp" +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=532480 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RISCV_TOOLCHAIN_GNU_RV32=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSLOG_CONSOLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh/defconfig b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh/defconfig index 85c48d36f41..2323dfad0a4 100644 --- a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh/defconfig +++ b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/nsh/defconfig @@ -17,20 +17,19 @@ CONFIG_ARCH_BOARD_RASPBERRYPI_PICO_2_RV=y CONFIG_ARCH_CHIP="rp23xx-rv" CONFIG_ARCH_CHIP_RP23XX_RV=y CONFIG_ARCH_RISCV=y -CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb" +CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb_zcmp" CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_IRQ_WORK_STACKSIZE=4096 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y diff --git a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh-smp/defconfig b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh-smp/defconfig new file mode 100644 index 00000000000..c8c6e91c7b2 --- /dev/null +++ b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh-smp/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_RP23XX_RV_UART0 is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="raspberrypi-pico-2-rv" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO_2_RV=y +CONFIG_ARCH_CHIP="rp23xx-rv" +CONFIG_ARCH_CHIP_RP23XX_RV=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb_zcmp" +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_DISABLE_RXBUF=y +CONFIG_CDCACM_DISABLE_TXBUF=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_RAM_SIZE=532480 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RISCV_TOOLCHAIN_GNU_RV32=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh/defconfig b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh/defconfig index 91bbda7cf49..5bfb01cf93d 100644 --- a/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh/defconfig +++ b/boards/risc-v/rp23xx-rv/raspberrypi-pico-2-rv/configs/usbnsh/defconfig @@ -18,21 +18,23 @@ CONFIG_ARCH_BOARD_RASPBERRYPI_PICO_2_RV=y CONFIG_ARCH_CHIP="rp23xx-rv" CONFIG_ARCH_CHIP_RP23XX_RV=y CONFIG_ARCH_RISCV=y -CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb" +CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS="zba_zbb_zbs_zbkb_zcb_zcmp" +CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_CDCACM=y CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_DISABLE_RXBUF=y +CONFIG_CDCACM_DISABLE_TXBUF=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y -CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=4096 -CONFIG_IRQ_WORK_STACKSIZE=4096 CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y From ca73f0e9e50b35cdc4a6077d1c96a020c13024fd Mon Sep 17 00:00:00 2001 From: Catalin Visinescu Date: Sun, 14 Jun 2026 10:39:01 -0400 Subject: [PATCH 096/268] drivers/can/ctucanfd_pci: Stack Overflow When Malformed CAN Data Is Received A malformed packet can trigger memory corruption in the kernel leading to a system crash or potentially arbitrary code execution in the kernel. The CAN driver for the CTU CAN FD IP Core connected to the NuttX device via a PCI / PCI Express (PCIe) bus shows a lack of consideration for malformed data, assuming the CAN frames are always correct. Ensure `frame->fmt.rwcnt` is 21 or less before it is used in the `for` loop. A similar change was done in ctucanfd_sock_recv(). Tested locally, builds fine. Signed-off-by: Catalin Visinescu --- drivers/can/ctucanfd_pci.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/can/ctucanfd_pci.c b/drivers/can/ctucanfd_pci.c index 647a9bce493..62382c3cbbb 100644 --- a/drivers/can/ctucanfd_pci.c +++ b/drivers/can/ctucanfd_pci.c @@ -760,6 +760,14 @@ static void ctucanfd_chardev_receive(FAR struct ctucanfd_can_s *priv) buff[0] = ctucanfd_getreg(priv, CTUCANFD_RXDATA); + /* buff[0] populated the frame->fmt.rwcnt. Check before use. */ + + if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0])) + { + canerr("ERROR: CAN read/write count is too large. Dropped\n"); + return; + } + /* Read the rest of data */ for (i = 0; i < frame->fmt.rwcnt; i++) @@ -1249,6 +1257,14 @@ static FAR netpkt_t *ctucanfd_sock_recv(FAR struct netdev_lowerhalf_s *dev) buff[0] = ctucanfd_getreg(priv, CTUCANFD_RXDATA); + /* buff[0] populated the frame->fmt.rwcnt. Check before use. */ + + if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0])) + { + canerr("ERROR: CAN read/write count is too large. Dropped\n"); + return NULL; + } + /* Read the rest of data */ for (i = 0; i < rxframe->fmt.rwcnt; i++) From ba4f774d8c08f3ae90e5ad786a3e6bc412a63b73 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 15 Jun 2026 12:00:16 +0200 Subject: [PATCH 097/268] arch/arm/src/common/stm32/Kconfig.i2c: add missing new line kconfig-frontends doesnt handle missing newlines at the end of the file. Signed-off-by: raiden00pl --- arch/arm/src/common/stm32/Kconfig.i2c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/src/common/stm32/Kconfig.i2c b/arch/arm/src/common/stm32/Kconfig.i2c index e3af19f3c7b..cd1832efced 100644 --- a/arch/arm/src/common/stm32/Kconfig.i2c +++ b/arch/arm/src/common/stm32/Kconfig.i2c @@ -310,4 +310,4 @@ config STM32_I2C_SLAVE_RETRANSFER endmenu -endif # !STM32_HAVE_I2C_H5 \ No newline at end of file +endif # !STM32_HAVE_I2C_H5 From 944a653e675f6e018cec5f840ed30d583f02caa3 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Wed, 13 May 2026 11:39:51 +0200 Subject: [PATCH 098/268] Documentation: update references to nrfjprog nrfjprog is no longer maintained. Change all nrfjprog commands to equivalent nrfutil commands Signed-off-by: raiden00pl --- Documentation/platforms/arm/nrf53/index.rst | 10 ++++++---- .../platforms/arm/nrf91/boards/nrf9160-dk/index.rst | 7 ++++--- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/Documentation/platforms/arm/nrf53/index.rst b/Documentation/platforms/arm/nrf53/index.rst index 4ea834de622..e6bf3c70b53 100644 --- a/Documentation/platforms/arm/nrf53/index.rst +++ b/Documentation/platforms/arm/nrf53/index.rst @@ -167,19 +167,21 @@ Flashing locked device 1. Unlock the network core:: - nrfjprog --recover --coprocessor CP_NETWORK + nrfutil device recover --core network 2. Unlock the application core:: - nrfjprog --recover + nrfutil device recover --core application 3. Flash the network core:: - nrfjprog --coprocessor CP_NETWORK --program nuttx_net.hex --verify --chiperase + nrfutil device erase --core network + nrfutil device program --firmware nuttx_net.hex --core network 4. Flash the application core:: - nrfjprog --program nuttx_app.hex --verify --chiperase + nrfutil device erase --core application + nrfutil device program --firmware nuttx_app.hex --core application Supported Boards diff --git a/Documentation/platforms/arm/nrf91/boards/nrf9160-dk/index.rst b/Documentation/platforms/arm/nrf91/boards/nrf9160-dk/index.rst index 0f552ccfbd0..ccae7a72ccf 100644 --- a/Documentation/platforms/arm/nrf91/boards/nrf9160-dk/index.rst +++ b/Documentation/platforms/arm/nrf91/boards/nrf9160-dk/index.rst @@ -113,13 +113,14 @@ To get this configuration working with miniboot bootloader follow these steps: #. flash bootloader:: - nrfjprog --program build_boot/nuttx.hex --chiperase --verify + nrfutil device erase + nrfutil device program --firmware build_boot/nuttx.hex #. flash modem image:: - nrfjprog --program build_modem/nuttx.hex + nrfutil device program --firmware build_modem/nuttx.hex #. reset chip:: - nrfjprog --reset + nrfutil device reset From 82fb723bdec599a02ffad66934d6096ede826af1 Mon Sep 17 00:00:00 2001 From: alexcekay Date: Tue, 2 Jun 2026 13:44:01 +0200 Subject: [PATCH 099/268] fs/littlefs: add block_size_factor mount option When a board switches storage technology but wants to mount a littlefs filesystem onto this storage it is desired to still use the same firmware. This almost works out of the box in NuttX with the exception of setting the correct block size, which may be different depending on the used storage. An incorrect block size may lead to suboptimal performance or worse. To avoid writing a firmware variant that only differs by CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR this adds the option to pass the intended block size at the mount call. To still enable the usage of the existing options this adds a parser for comma-separated mount options, allowing multiple options to be passed simultaneously. Example: "autoformat,block_size_factor=4", "autoformat,block_size_factor=1" This is backwards compatible: single options passed without commas continue to work as before. Signed-off-by: alexcekay --- fs/littlefs/lfs_vfs.c | 46 +++++++++++++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 6 deletions(-) diff --git a/fs/littlefs/lfs_vfs.c b/fs/littlefs/lfs_vfs.c index 780c0d8a10f..1a4208e3364 100644 --- a/fs/littlefs/lfs_vfs.c +++ b/fs/littlefs/lfs_vfs.c @@ -28,6 +28,7 @@ #include #include +#include #include #include @@ -1342,6 +1343,9 @@ static int littlefs_bind(FAR struct inode *driver, FAR const void *data, { FAR struct littlefs_mountpt_s *fs; int ret; + int block_size_factor = CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR; + bool autoformat = false; + bool forceformat = false; /* Open the block driver */ @@ -1415,6 +1419,38 @@ static int littlefs_bind(FAR struct inode *driver, FAR const void *data, goto errout_with_fs; } + /* Parse comma-separated mount options. Recognised tokens: + * autoformat - format if mount fails + * forceformat - always format before mounting + * block_size_factor=N - override CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR + */ + + if (data != NULL) + { + FAR const char *p = data; + + while (*p != '\0') + { + FAR const char *end = strchrnul(p, ','); + size_t len = end - p; + + if (strncmp(p, "autoformat", len) == 0) + { + autoformat = true; + } + else if (strncmp(p, "forceformat", len) == 0) + { + forceformat = true; + } + else + { + sscanf(p, "block_size_factor=%d", &block_size_factor); + } + + p = (*end != '\0') ? end + 1 : end; + } + } + /* Initialize lfs_config structure */ fs->cfg.context = fs; @@ -1426,10 +1462,8 @@ static int littlefs_bind(FAR struct inode *driver, FAR const void *data, CONFIG_FS_LITTLEFS_READ_SIZE_FACTOR; fs->cfg.prog_size = fs->geo.blocksize * CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR; - fs->cfg.block_size = fs->geo.erasesize * - CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR; - fs->cfg.block_count = fs->geo.neraseblocks / - CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR; + fs->cfg.block_size = fs->geo.erasesize * block_size_factor; + fs->cfg.block_count = fs->geo.neraseblocks / block_size_factor; fs->cfg.block_cycles = CONFIG_FS_LITTLEFS_BLOCK_CYCLE; fs->cfg.cache_size = fs->geo.blocksize * CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR; @@ -1451,7 +1485,7 @@ static int littlefs_bind(FAR struct inode *driver, FAR const void *data, /* Force format the device if -o forceformat */ - if (data && strcmp(data, "forceformat") == 0) + if (forceformat) { ret = littlefs_convert_result(lfs_format(&fs->lfs, &fs->cfg)); if (ret < 0) @@ -1470,7 +1504,7 @@ static int littlefs_bind(FAR struct inode *driver, FAR const void *data, { /* Auto format the device if -o autoformat */ - if (ret != -EFAULT || !data || strcmp(data, "autoformat")) + if (ret != -EFAULT || !autoformat) { goto errout_with_fs; } From cbfaa7c3b0dd041d63a67f4faa3faf94ea85fead Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Mon, 15 Jun 2026 16:57:15 +0300 Subject: [PATCH 100/268] drivers/mtd: Make compile time check for sane mtd isbad/markbad configuration This removes the DEBUGASSERT in ftl_initialize_by_path. Instead, check compile time that FTL is enabled in case some of the drivers implement the isbad and markbad functions. Also select the FTL_BBM for those drivers as they require it. Signed-off-by: Jukka Laitinen --- arch/arm/src/rp2040/rp2040_flash_mtd.c | 2 ++ drivers/mtd/Kconfig | 6 ++++-- drivers/mtd/ftl.c | 9 --------- drivers/mtd/mtd_partition.c | 6 ++++++ drivers/mtd/mtd_progmem.c | 2 ++ include/nuttx/mtd/mtd.h | 12 ++++++++++-- 6 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/rp2040/rp2040_flash_mtd.c b/arch/arm/src/rp2040/rp2040_flash_mtd.c index 01531484e65..68bbb772b82 100644 --- a/arch/arm/src/rp2040/rp2040_flash_mtd.c +++ b/arch/arm/src/rp2040/rp2040_flash_mtd.c @@ -185,8 +185,10 @@ static struct rp2040_flash_dev_s my_dev = NULL, #endif rp2040_flash_ioctl, +#ifdef CONFIG_FTL_BBM NULL, NULL, +#endif "rp_flash" }, .lock = NXMUTEX_INITIALIZER, diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 343693c8ffd..b30e4f64fc6 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -51,8 +51,8 @@ config FTL_READAHEAD depends on DRVR_READAHEAD config FTL_BBM - bool "Enable bad block management in the FTL layer" - default y if MTD_NAND + bool + default n ---help--- Enable logical to physical erase-block mapping in the FTL layer for MTD devices that expose bad blocks via the MTD isbad/markbad methods. @@ -240,6 +240,7 @@ menuconfig MTD_NAND bool "MTD NAND support" depends on ALLOW_BSD_COMPONENTS default n + select FTL_BBM ---help--- Enable support for NAND FLASH devices. @@ -419,6 +420,7 @@ endif # RAMMTD config FILEMTD bool "File-based MTD driver" default n + select FTL_BBM ---help--- Build support for a File-based MTD driver. diff --git a/drivers/mtd/ftl.c b/drivers/mtd/ftl.c index f175f4f5076..eee562c787d 100644 --- a/drivers/mtd/ftl.c +++ b/drivers/mtd/ftl.c @@ -951,15 +951,6 @@ int ftl_initialize_by_path(FAR const char *path, FAR struct mtd_dev_s *mtd, finfo("path=\"%s\"\n", path); -#ifndef CONFIG_FTL_BBM - /* It is likely a configuration error if the mtd driver implements - * the bad block management, but it is still disabled by the - * configuration. - */ - - DEBUGASSERT(mtd->isbad == NULL && mtd->markbad == NULL); -#endif - /* Allocate a FTL device structure */ dev = kmm_zalloc(sizeof(struct ftl_struct_s)); diff --git a/drivers/mtd/mtd_partition.c b/drivers/mtd/mtd_partition.c index 7de1c64db3e..bd271949d8a 100644 --- a/drivers/mtd/mtd_partition.c +++ b/drivers/mtd/mtd_partition.c @@ -116,8 +116,10 @@ static ssize_t part_write(FAR struct mtd_dev_s *dev, off_t offset, #endif static int part_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); +#ifdef CONFIG_FTL_BBM static int part_isbad(FAR struct mtd_dev_s *dev, off_t block); static int part_markbad(FAR struct mtd_dev_s *dev, off_t block); +#endif /* File system methods */ @@ -495,6 +497,7 @@ static int part_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ +#ifdef CONFIG_FTL_BBM static int part_isbad(FAR struct mtd_dev_s *dev, off_t block) { FAR struct mtd_partition_s *priv = (FAR struct mtd_partition_s *)dev; @@ -540,6 +543,7 @@ static int part_markbad(FAR struct mtd_dev_s *dev, off_t block) return -ENOSYS; } +#endif #if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_PROCFS_EXCLUDE_PARTITIONS) @@ -906,8 +910,10 @@ FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, part->child.bwrite = part_bwrite; part->child.read = mtd->read ? part_read : NULL; part->child.ioctl = part_ioctl; +#ifdef CONFIG_FTL_BBM part->child.isbad = part_isbad; part->child.markbad = part_markbad; +#endif #ifdef CONFIG_MTD_BYTE_WRITE part->child.write = mtd->write ? part_write : NULL; #endif diff --git a/drivers/mtd/mtd_progmem.c b/drivers/mtd/mtd_progmem.c index e48e5d0fdfd..e265d89e960 100644 --- a/drivers/mtd/mtd_progmem.c +++ b/drivers/mtd/mtd_progmem.c @@ -103,8 +103,10 @@ static struct progmem_dev_s g_progmem = progmem_write, #endif progmem_ioctl, +#ifdef CONFIG_FTL_BBM NULL, NULL, +#endif "progmem", } }; diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index aec16db1e3a..961ffd2ddd9 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -97,8 +97,14 @@ #define MTD_READ(d,s,n,b) ((d)->read ? (d)->read(d,s,n,b) : (-ENOSYS)) #define MTD_WRITE(d,s,n,b) ((d)->write ? (d)->write(d,s,n,b) : (-ENOSYS)) #define MTD_IOCTL(d,c,a) ((d)->ioctl ? (d)->ioctl(d,c,a) : (-ENOSYS)) -#define MTD_ISBAD(d,b) ((d)->isbad ? (d)->isbad(d,b) : (-ENOSYS)) -#define MTD_MARKBAD(d,b) ((d)->markbad ? (d)->markbad(d,b) : (-ENOSYS)) + +#ifdef CONFIG_FTL_BBM +# define MTD_ISBAD(d,b) ((d)->isbad ? (d)->isbad(d,b) : (-ENOSYS)) +# define MTD_MARKBAD(d,b) ((d)->markbad ? (d)->markbad(d,b) : (-ENOSYS)) +#else +# define MTD_ISBAD(d,b) (-ENOSYS) +# define MTD_MARKBAD(d,b) (-ENOSYS) +#endif /* If any of the low-level device drivers declare they want sub-sector erase * support, then define MTD_SUBSECTOR_ERASE. @@ -220,8 +226,10 @@ struct mtd_dev_s /* Check/Mark bad block for the specified block number */ +#ifdef CONFIG_FTL_BBM CODE int (*isbad)(FAR struct mtd_dev_s *dev, off_t block); CODE int (*markbad)(FAR struct mtd_dev_s *dev, off_t block); +#endif /* Name of this MTD device */ From 5e5137adee2e6fc838df9cb52fcdac579bf78266 Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Sun, 14 Jun 2026 06:12:03 +0800 Subject: [PATCH 101/268] Documentation/applications/system/critmon: add critmon man page Add documentation for the critmon command including: - critmon (one-shot dump) - critmon_start (start daemon) - critmon_stop (stop daemon) - Output format explanation - Configuration options Signed-off-by: hanzhijian --- .../applications/system/critmon/index.rst | 91 +++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 Documentation/applications/system/critmon/index.rst diff --git a/Documentation/applications/system/critmon/index.rst b/Documentation/applications/system/critmon/index.rst new file mode 100644 index 00000000000..49a6db41a0c --- /dev/null +++ b/Documentation/applications/system/critmon/index.rst @@ -0,0 +1,91 @@ +==================================== +``critmon`` critical section monitor +==================================== + +The ``critmon`` command displays critical section and pre-emption timing +information for all tasks and threads in the system. It reads from the +procfs ``critmon`` and ``status`` files for each process/thread. + +Three commands are provided: + +- ``critmon``: One-shot dump of critical section timing data. +- ``critmon_start``: Start the background monitoring daemon. +- ``critmon_stop``: Stop the background monitoring daemon. + +The daemon periodically samples critical section usage at a configurable +interval (default: 2 seconds) and prints the timing information. + +Configuration +============= + +- ``CONFIG_SCHED_CRITMONITOR``: Enable the critical section monitor + in the kernel (required dependency). +- ``CONFIG_FS_PROCFS``: Enable procfs filesystem support. +- ``CONFIG_SYSTEM_CRITMONITOR``: Enable the critmon system tool. + +The following additional options are available: + +- ``CONFIG_SYSTEM_CRITMONITOR_DAEMON_STACKSIZE`` - Stack size for the + daemon task (default: 2048). +- ``CONFIG_SYSTEM_CRITMONITOR_DAEMON_PRIORITY`` - Priority for the + daemon task (default: 50). +- ``CONFIG_SYSTEM_CRITMONITOR_INTERVAL`` - Sampling interval in + seconds (default: 2). +- ``CONFIG_SYSTEM_CRITMONITOR_MOUNTPOINT`` - procfs mount point + (default: ``/proc``). + +Usage +===== + +.. code-block:: text + + critmon + critmon_start + critmon_stop + +Output Format +============= + +The output shows a table with the following columns: + +- **PRE-EMPTION CALLER**: The function that most recently enabled + pre-emption for this task. +- **CSECTION CALLER**: The function that most recently entered a + critical section. +- **RUN**: Maximum time spent in a critical section. +- **TIME**: Total accumulated critical section time. +- **PID**: Process/thread ID. +- **DESCRIPTION**: Task name (if ``CONFIG_TASK_NAME_SIZE > 0``). + +Examples +======== + +One-shot dump of critical section timing: + +.. code-block:: text + + nsh> critmon + PRE-EMPTION CALLER CSECTION CALLER RUN TIME PID DESCRIPTION + nxtask_exit nxtask_init 0.000010000 0.000010000 0 Idle_Task + nxtask_init up_irq_save 0.000005000 0.000015000 1 hpwork 0x10001000 + +Start the monitoring daemon (prints every 2 seconds): + +.. code-block:: text + + nsh> critmon_start + Csection Monitor: Started: 5 + +Stop the monitoring daemon: + +.. code-block:: text + + nsh> critmon_stop + Csection Monitor: Stopping: 5 + Csection Monitor: Stopped: 5 + +See Also +======== + +- :doc:`../stackmonitor/index` +- :doc:`../gprof/index` From a21c8aaa0b444c1c2527fe58442231932d714f12 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Fri, 12 Jun 2026 14:18:59 +0300 Subject: [PATCH 102/268] boards/nucleo-f302r8 : Set CONFIG_DISABLE_ALL_SIGNALS=y for ihm07m1_f32 This small board doesn't use the signals, so it is safe to disable them to save flash. Signed-off-by: Jukka Laitinen --- boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig index 4a8b23fe7b9..e51931b5d9e 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -32,6 +32,7 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_SMALL=y CONFIG_DEFAULT_TASK_STACKSIZE=1024 +CONFIG_DISABLE_ALL_SIGNALS=y CONFIG_EXAMPLES_FOC=y CONFIG_EXAMPLES_FOC_ADC_MAX=4095 CONFIG_EXAMPLES_FOC_ADC_VREF=3300 From 0d93f2eb20fba22bf8ab6a7ffa1aee60a2fadd70 Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Fri, 12 Jun 2026 14:27:42 +0300 Subject: [PATCH 103/268] drivers/input/button_upper.c: Fix compilation with CONFIG_DISABLE_ALL_SIGNALS The optional signal delivery should be disabled when signals support is disabled for the board. Signed-off-by: Jukka Laitinen --- drivers/input/button_upper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/input/button_upper.c b/drivers/input/button_upper.c index eeb9a67cb93..2375f9cf972 100644 --- a/drivers/input/button_upper.c +++ b/drivers/input/button_upper.c @@ -186,8 +186,10 @@ static void btn_enable(FAR struct btn_upperhalf_s *priv) /* OR in the signal events */ +#ifndef CONFIG_DISABLE_ALL_SIGNALS press |= opriv->bo_notify.bn_press; release |= opriv->bo_notify.bn_release; +#endif } /* Enable/disable button interrupts */ @@ -430,7 +432,9 @@ static int btn_close(FAR struct file *filep) /* Cancel any pending notification */ +#ifndef CONFIG_DISABLE_ALL_SIGNALS nxsig_cancel_notification(&opriv->bo_work); +#endif /* And free the open structure */ @@ -629,6 +633,7 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg) case BTNIOC_REGISTER: { +#ifndef CONFIG_DISABLE_ALL_SIGNALS FAR struct btn_notify_s *notify = (FAR struct btn_notify_s *)((uintptr_t)arg); @@ -646,6 +651,9 @@ static int btn_ioctl(FAR struct file *filep, int cmd, unsigned long arg) btn_enable(priv); ret = OK; } +#else + ret = -ENOSYS; +#endif } break; From 7f8f800e63aa0ee3233ff2a0539d67471857f30a Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Wed, 10 Jun 2026 11:14:26 +0300 Subject: [PATCH 104/268] arch, sched/signal: Fix compilation with ENABLE_PARTIAL_SIGNALS=y Correct build errors when CONFIG_ENABLE_ALL_SIGNALS is not defined - sched makefiles: Move pending-signal helpers from the ENABLE_ALL_SIGNALS-only list to the !DISABLE_ALL_SIGNALS list so signal dispatch is available in PARTIAL builds sched: make SIG_PREALLOC_ACTIONS, SIG_ALLOC_ACTIONS and SIG_DEFAULT depend on ENABLE_ALL_SIGNALS - sched: fix ifdefs around pending-signal queue access and signal-mask for PARTIAL/DISABLE modes - arch: gate SYS_signal_handler / _return calls and SYSCALL_LOOKUP(signal) with ENABLE_ALL_SIGNALS Signed-off-by: Jukka Laitinen --- arch/arm/src/armv6-m/arm_svcall.c | 4 +- arch/arm/src/armv7-m/arm_svcall.c | 4 +- arch/arm/src/armv8-m/arm_svcall.c | 4 +- arch/arm/src/armv8-r/arm_syscall.c | 4 +- arch/arm64/src/common/arm64_syscall.c | 3 +- arch/risc-v/src/common/riscv_swint.c | 4 +- arch/xtensa/src/common/xtensa_swint.c | 4 +- include/nuttx/sched.h | 4 +- include/sys/syscall_lookup.h | 4 ++ libs/libc/pthread/CMakeLists.txt | 4 +- libs/libc/pthread/Make.defs | 3 -- libs/libc/pthread/pthread_mutex_destroy.c | 2 - sched/Kconfig | 19 ++++--- sched/group/group_leave.c | 2 +- sched/init/nx_start.c | 2 +- sched/sched/sched_suspend.c | 4 ++ sched/semaphore/sem_wait.c | 6 +-- sched/signal/CMakeLists.txt | 21 ++++---- sched/signal/Make.defs | 13 +++-- sched/signal/sig_cleanup.c | 9 +++- sched/signal/sig_dispatch.c | 62 ++++++++++++----------- sched/signal/sig_initialize.c | 15 ++++-- sched/signal/sig_kill.c | 13 ++++- sched/signal/sig_procmask.c | 2 - sched/signal/sig_tgkill.c | 13 ++++- sched/signal/sig_timedwait.c | 4 -- sched/signal/signal.h | 11 ++-- sched/task/task_exithook.c | 2 +- sched/task/task_restart.c | 4 +- sched/task/task_setup.c | 3 +- 30 files changed, 147 insertions(+), 102 deletions(-) diff --git a/arch/arm/src/armv6-m/arm_svcall.c b/arch/arm/src/armv6-m/arm_svcall.c index 0167f86d12e..b004d252018 100644 --- a/arch/arm/src/armv6-m/arm_svcall.c +++ b/arch/arm/src/armv6-m/arm_svcall.c @@ -238,7 +238,7 @@ int arm_svcall(int irq, void *context, void *arg) * R4 = ucontext */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler: { struct tcb_s *rtcb = this_task(); @@ -280,7 +280,7 @@ int arm_svcall(int irq, void *context, void *arg) * R0 = SYS_signal_handler_return */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler_return: { struct tcb_s *rtcb = this_task(); diff --git a/arch/arm/src/armv7-m/arm_svcall.c b/arch/arm/src/armv7-m/arm_svcall.c index 9f77ce5cf93..956f1b95b52 100644 --- a/arch/arm/src/armv7-m/arm_svcall.c +++ b/arch/arm/src/armv7-m/arm_svcall.c @@ -240,7 +240,7 @@ int arm_svcall(int irq, void *context, void *arg) * R4 = ucontext */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler: { struct tcb_s *rtcb = this_task(); @@ -282,7 +282,7 @@ int arm_svcall(int irq, void *context, void *arg) * R0 = SYS_signal_handler_return */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler_return: { struct tcb_s *rtcb = this_task(); diff --git a/arch/arm/src/armv8-m/arm_svcall.c b/arch/arm/src/armv8-m/arm_svcall.c index f3c3dc16f93..03ab17d0ce3 100644 --- a/arch/arm/src/armv8-m/arm_svcall.c +++ b/arch/arm/src/armv8-m/arm_svcall.c @@ -240,7 +240,7 @@ int arm_svcall(int irq, void *context, void *arg) * R4 = ucontext */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler: { struct tcb_s *rtcb = this_task(); @@ -282,7 +282,7 @@ int arm_svcall(int irq, void *context, void *arg) * R0 = SYS_signal_handler_return */ -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler_return: { struct tcb_s *rtcb = this_task(); diff --git a/arch/arm/src/armv8-r/arm_syscall.c b/arch/arm/src/armv8-r/arm_syscall.c index bf0c64a6cd5..e9b54c382b7 100644 --- a/arch/arm/src/armv8-r/arm_syscall.c +++ b/arch/arm/src/armv8-r/arm_syscall.c @@ -356,7 +356,7 @@ uint32_t *arm_syscall(uint32_t *regs) break; #endif -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) /* R0=SYS_signal_handler: This a user signal handler callback * * void signal_handler(_sa_sigaction_t sighand, int signo, @@ -438,7 +438,7 @@ uint32_t *arm_syscall(uint32_t *regs) break; #endif -#ifdef CONFIG_BUILD_PROTECTED +#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_ENABLE_ALL_SIGNALS) /* R0=SYS_signal_handler_return: This a user signal handler callback * * void signal_handler_return(void); diff --git a/arch/arm64/src/common/arm64_syscall.c b/arch/arm64/src/common/arm64_syscall.c index fec098c92ed..8d503aa64e3 100644 --- a/arch/arm64/src/common/arm64_syscall.c +++ b/arch/arm64/src/common/arm64_syscall.c @@ -159,7 +159,8 @@ uint64_t *arm64_syscall(uint64_t *regs) struct tcb_s **running_task = &g_running_tasks[cpu]; struct tcb_s *tcb = this_task(); uint64_t cmd; -#if defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_BUILD_PROTECTED) +#if (defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_BUILD_PROTECTED)) \ + && defined(CONFIG_ENABLE_ALL_SIGNALS) uint64_t spsr; #endif diff --git a/arch/risc-v/src/common/riscv_swint.c b/arch/risc-v/src/common/riscv_swint.c index c41f4448218..b5dc855484f 100644 --- a/arch/risc-v/src/common/riscv_swint.c +++ b/arch/risc-v/src/common/riscv_swint.c @@ -195,7 +195,7 @@ int riscv_swint(int irq, void *context, void *arg) * A4 = ucontext */ -#ifndef CONFIG_BUILD_FLAT +#if !defined(CONFIG_BUILD_FLAT) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler: { struct tcb_s *rtcb = this_task(); @@ -272,7 +272,7 @@ int riscv_swint(int irq, void *context, void *arg) * R0 = SYS_signal_handler_return */ -#ifndef CONFIG_BUILD_FLAT +#if !defined(CONFIG_BUILD_FLAT) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler_return: { struct tcb_s *rtcb = this_task(); diff --git a/arch/xtensa/src/common/xtensa_swint.c b/arch/xtensa/src/common/xtensa_swint.c index 1a4b3aa8ee9..4b38987e17e 100644 --- a/arch/xtensa/src/common/xtensa_swint.c +++ b/arch/xtensa/src/common/xtensa_swint.c @@ -261,7 +261,7 @@ int xtensa_swint(int irq, void *context, void *arg) * A6 = ucontext */ -#ifndef CONFIG_BUILD_FLAT +#if !defined(CONFIG_BUILD_FLAT) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler: { struct tcb_s *rtcb = this_task(); @@ -300,7 +300,7 @@ int xtensa_swint(int irq, void *context, void *arg) * A2 = SYS_signal_handler_return */ -#ifndef CONFIG_BUILD_FLAT +#if !defined(CONFIG_BUILD_FLAT) && defined(CONFIG_ENABLE_ALL_SIGNALS) case SYS_signal_handler_return: { struct tcb_s *rtcb = this_task(); diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index 9f40db43828..76630d3f101 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -519,8 +519,10 @@ struct task_group_s #ifdef CONFIG_ENABLE_ALL_SIGNALS sq_queue_t tg_sigactionq; /* List of actions for signals */ - sq_queue_t tg_sigpendingq; /* List of pending signals */ #endif /* CONFIG_ENABLE_ALL_SIGNALS */ +#ifndef CONFIG_DISABLE_ALL_SIGNALS + sq_queue_t tg_sigpendingq; /* List of pending signals */ +#endif /* !CONFIG_DISABLE_ALL_SIGNALS */ #ifdef CONFIG_SIG_DEFAULT sigset_t tg_sigdefault; /* Set of signals set to the default action */ #endif diff --git a/include/sys/syscall_lookup.h b/include/sys/syscall_lookup.h index c83fa657e66..7a1f37284c8 100644 --- a/include/sys/syscall_lookup.h +++ b/include/sys/syscall_lookup.h @@ -217,8 +217,10 @@ SYSCALL_LOOKUP(pwrite, 4) #endif SYSCALL_LOOKUP(poll, 3) SYSCALL_LOOKUP(select, 5) +#ifndef CONFIG_DISABLE_ALL_SIGNALS SYSCALL_LOOKUP(ppoll, 4) SYSCALL_LOOKUP(pselect, 6) +#endif #ifdef CONFIG_EVENT_FD SYSCALL_LOOKUP(eventfd, 2) #endif @@ -397,7 +399,9 @@ SYSCALL_LOOKUP(settimeofday, 2) /* ANSI C signal handling */ +#ifdef CONFIG_ENABLE_ALL_SIGNALS SYSCALL_LOOKUP(signal, 2) +#endif #ifdef CONFIG_SCHED_INSTRUMENTATION_DUMP SYSCALL_LOOKUP(sched_note_vprintf_ip, 5) diff --git a/libs/libc/pthread/CMakeLists.txt b/libs/libc/pthread/CMakeLists.txt index 96ff96e8225..523f2818f7e 100644 --- a/libs/libc/pthread/CMakeLists.txt +++ b/libs/libc/pthread/CMakeLists.txt @@ -131,9 +131,7 @@ if(NOT CONFIG_DISABLE_PTHREAD) list(APPEND SRCS pthread_spinlock.c) endif() - if(NOT CONFIG_DISABLE_ALL_SIGNALS) - list(APPEND SRCS pthread_kill.c) - endif() + list(APPEND SRCS pthread_kill.c) if(NOT CONFIG_TLS_NCLEANUP EQUAL 0) list(APPEND SRCS pthread_cleanup.c) diff --git a/libs/libc/pthread/Make.defs b/libs/libc/pthread/Make.defs index 14a4200d0c8..25869be1a04 100644 --- a/libs/libc/pthread/Make.defs +++ b/libs/libc/pthread/Make.defs @@ -68,10 +68,7 @@ CSRCS += pthread_setcancelstate.c pthread_setcanceltype.c CSRCS += pthread_testcancel.c pthread_getcpuclockid.c CSRCS += pthread_self.c pthread_gettid_np.c CSRCS += pthread_concurrency.c - -ifneq ($(CONFIG_DISABLE_ALL_SIGNALS),y) CSRCS += pthread_kill.c -endif ifeq ($(CONFIG_SMP),y) CSRCS += pthread_attr_getaffinity.c pthread_attr_setaffinity.c diff --git a/libs/libc/pthread/pthread_mutex_destroy.c b/libs/libc/pthread/pthread_mutex_destroy.c index 45b6a2e000b..6432bb6782b 100644 --- a/libs/libc/pthread/pthread_mutex_destroy.c +++ b/libs/libc/pthread/pthread_mutex_destroy.c @@ -90,7 +90,6 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) * nxsched_get_tcb() does. */ -#ifndef CONFIG_DISABLE_ALL_SIGNALS if (pthread_kill(pid, 0) != 0) { /* The thread associated with the PID no longer exists */ @@ -122,7 +121,6 @@ int pthread_mutex_destroy(FAR pthread_mutex_t *mutex) } } else -#endif { ret = EBUSY; } diff --git a/sched/Kconfig b/sched/Kconfig index 3b5808a4417..5532fc4114b 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -1601,6 +1601,16 @@ config DISABLE_ALL_SIGNALS endchoice +config SIG_PREALLOC_IRQ_ACTIONS + int "Number of pre-allocated irq actions" + default 4 if DEFAULT_SMALL + default 8 if !DEFAULT_SMALL + depends on !DISABLE_ALL_SIGNALS + ---help--- + The number of pre-allocated irq action structures. + +if ENABLE_ALL_SIGNALS + config SIG_PREALLOC_ACTIONS int "Number of pre-allocated sigactions" default 4 @@ -1615,13 +1625,6 @@ config SIG_ALLOC_ACTIONS if this number is larger than 1, the allocation won't be returned to the heap but kept in a free list for reuse. -config SIG_PREALLOC_IRQ_ACTIONS - int "Number of pre-allocated irq actions" - default 4 if DEFAULT_SMALL - default 8 if !DEFAULT_SMALL - ---help--- - The number of pre-allocated irq action structures. - config SIG_EVTHREAD bool "Support SIGEV_THREAD" default n @@ -1736,6 +1739,8 @@ config SIG_SIGURG_ACTION endif # SIG_DEFAULT +endif # ENABLE_ALL_SIGNALS + endmenu # Signal Configuration menu "Message Queue Options" diff --git a/sched/group/group_leave.c b/sched/group/group_leave.c index a4ff9eab12e..afe62da8c07 100644 --- a/sched/group/group_leave.c +++ b/sched/group/group_leave.c @@ -86,7 +86,7 @@ static inline void group_release(FAR struct task_group_s *group) /* Release pending signals */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS +#ifndef CONFIG_DISABLE_ALL_SIGNALS nxsig_release(group); #endif diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c index 418619bdd74..b9bcb07fb2f 100644 --- a/sched/init/nx_start.c +++ b/sched/init/nx_start.c @@ -643,7 +643,7 @@ void nx_start(void) /* Initialize the signal facility (if in link) */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS +#ifndef CONFIG_DISABLE_ALL_SIGNALS nxsig_initialize(); #endif diff --git a/sched/sched/sched_suspend.c b/sched/sched/sched_suspend.c index e67d8bfe804..c2b38b21d92 100644 --- a/sched/sched/sched_suspend.c +++ b/sched/sched/sched_suspend.c @@ -103,12 +103,15 @@ void nxsched_suspend(FAR struct tcb_s *tcb) { irqstate_t flags; bool switch_needed; +#ifdef CONFIG_ENABLE_ALL_SIGNALS FAR sq_entry_t *entry; +#endif DEBUGASSERT(tcb != NULL); flags = enter_critical_section(); +#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Check if received SIGCONT */ sq_for_every(&tcb->sigpendactionq, entry) @@ -120,6 +123,7 @@ void nxsched_suspend(FAR struct tcb_s *tcb) return; } } +#endif /* Check the current state of the task */ diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index aac400ddd32..e4c065bfb47 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -34,9 +34,7 @@ #include #include #include -#ifdef CONFIG_ENABLE_ALL_SIGNALS #include -#endif #include "sched/sched.h" #include "semaphore/semaphore.h" @@ -74,7 +72,7 @@ int nxsem_wait_slow(FAR sem_t *sem) { -#ifdef CONFIG_ENABLE_ALL_SIGNALS +#ifndef CONFIG_DISABLE_ALL_SIGNALS sigset_t pendingset; #endif FAR struct tcb_s *rtcb = this_task(); @@ -93,7 +91,7 @@ int nxsem_wait_slow(FAR sem_t *sem) /* Make sure we were supplied with a valid semaphore. */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS +#ifndef CONFIG_DISABLE_ALL_SIGNALS /* A signal can arrive before sem_wait transitions the task to * TSTATE_WAIT_SEM. In that window, the wait cannot yet be aborted by * sem_wait_irq(). If sem_wait then blocks without re-checking unmasked diff --git a/sched/signal/CMakeLists.txt b/sched/signal/CMakeLists.txt index a9595309737..1fa0eeb49af 100644 --- a/sched/signal/CMakeLists.txt +++ b/sched/signal/CMakeLists.txt @@ -20,7 +20,8 @@ # # ############################################################################## -set(SRCS sig_nanosleep.c sig_usleep.c sig_sleep.c sig_clockwait.c) +set(SRCS sig_nanosleep.c sig_usleep.c sig_sleep.c sig_clockwait.c sig_kill.c + sig_tgkill.c) if(NOT CONFIG_DISABLE_ALL_SIGNALS) list( @@ -28,8 +29,6 @@ if(NOT CONFIG_DISABLE_ALL_SIGNALS) SRCS sig_procmask.c sig_suspend.c - sig_kill.c - sig_tgkill.c sig_queue.c sig_waitinfo.c sig_timedwait.c @@ -38,7 +37,13 @@ if(NOT CONFIG_DISABLE_ALL_SIGNALS) sig_dispatch.c sig_pause.c sig_ppoll.c - sig_pselect.c) + sig_pselect.c + sig_cleanup.c + sig_initialize.c + sig_pending.c + sig_releasependingsignal.c + sig_removependingsignal.c + sig_unmaskpendingsignal.c) endif() if(CONFIG_ENABLE_ALL_SIGNALS) @@ -47,15 +52,9 @@ if(CONFIG_ENABLE_ALL_SIGNALS) SRCS sig_action.c sig_allocpendingsigaction.c - sig_cleanup.c sig_deliver.c sig_findaction.c - sig_initialize.c - sig_pending.c - sig_releasependingsigaction.c - sig_releasependingsignal.c - sig_removependingsignal.c - sig_unmaskpendingsignal.c) + sig_releasependingsigaction.c) endif() if(CONFIG_SIG_DEFAULT) diff --git a/sched/signal/Make.defs b/sched/signal/Make.defs index e1099a4ebc1..079ffe58af3 100644 --- a/sched/signal/Make.defs +++ b/sched/signal/Make.defs @@ -21,18 +21,21 @@ ############################################################################ CSRCS += sig_nanosleep.c sig_sleep.c sig_usleep.c sig_clockwait.c +CSRCS += sig_kill.c sig_tgkill.c ifneq ($(CONFIG_DISABLE_ALL_SIGNALS),y) -CSRCS += sig_dispatch.c sig_kill.c sig_lowest.c +CSRCS += sig_dispatch.c sig_lowest.c CSRCS += sig_notification.c sig_pause.c sig_ppoll.c sig_procmask.c -CSRCS += sig_pselect.c sig_queue.c sig_suspend.c sig_tgkill.c +CSRCS += sig_pselect.c sig_queue.c sig_suspend.c CSRCS += sig_timedwait.c sig_waitinfo.c +CSRCS += sig_cleanup.c sig_initialize.c sig_pending.c +CSRCS += sig_releasependingsignal.c sig_removependingsignal.c +CSRCS += sig_unmaskpendingsignal.c endif ifeq ($(CONFIG_ENABLE_ALL_SIGNALS),y) -CSRCS += sig_action.c sig_allocpendingsigaction.c sig_cleanup.c sig_deliver.c -CSRCS += sig_findaction.c sig_initialize.c sig_pending.c sig_releasependingsigaction.c -CSRCS += sig_releasependingsignal.c sig_removependingsignal.c sig_unmaskpendingsignal.c +CSRCS += sig_action.c sig_allocpendingsigaction.c sig_deliver.c +CSRCS += sig_findaction.c sig_releasependingsigaction.c endif ifeq ($(CONFIG_SIG_DEFAULT),y) diff --git a/sched/signal/sig_cleanup.c b/sched/signal/sig_cleanup.c index df63a2d783f..0947c0e63bb 100644 --- a/sched/signal/sig_cleanup.c +++ b/sched/signal/sig_cleanup.c @@ -46,6 +46,7 @@ void nxsig_cleanup(FAR struct tcb_s *stcb) { +#ifdef CONFIG_ENABLE_ALL_SIGNALS FAR sigq_t *sigq; /* Deallocate all entries in the list of pending signal actions */ @@ -61,6 +62,7 @@ void nxsig_cleanup(FAR struct tcb_s *stcb) { nxsig_release_pendingsigaction(sigq); } +#endif /* Misc. signal-related clean-up */ @@ -81,13 +83,17 @@ void nxsig_cleanup(FAR struct tcb_s *stcb) void nxsig_release(FAR struct task_group_s *group) { +#ifdef CONFIG_ENABLE_ALL_SIGNALS FAR sigactq_t *sigact; +#endif FAR sigpendq_t *sigpend; irqstate_t flags; + flags = spin_lock_irqsave(&group->tg_lock); + +#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Deallocate all entries in the list of signal actions */ - flags = spin_lock_irqsave(&group->tg_lock); while ((sigact = (FAR sigactq_t *)sq_remfirst(&group->tg_sigactionq)) != NULL) { @@ -95,6 +101,7 @@ void nxsig_release(FAR struct task_group_s *group) nxsig_release_action(sigact); flags = spin_lock_irqsave(&group->tg_lock); } +#endif /* Deallocate all entries in the list of pending signals */ diff --git a/sched/signal/sig_dispatch.c b/sched/signal/sig_dispatch.c index 0596c80a413..79dc91a1da6 100644 --- a/sched/signal/sig_dispatch.c +++ b/sched/signal/sig_dispatch.c @@ -204,6 +204,25 @@ static int nxsig_queue_action(FAR struct tcb_s *stcb, return ret; } +/**************************************************************************** + * Name: nxsig_dispatch_kernel_action + ****************************************************************************/ + +static void nxsig_dispatch_kernel_action(FAR struct tcb_s *stcb, + FAR siginfo_t *info) +{ + FAR struct task_group_s *group = stcb->group; + FAR sigactq_t *sigact; + + sigact = nxsig_find_action(group, info->si_signo); + if (sigact && (sigact->act.sa_flags & SA_KERNELHAND)) + { + info->si_user = sigact->act.sa_user; + (sigact->act.sa_sigaction)(info->si_signo, info, NULL); + } +} +#endif /* CONFIG_ENABLE_ALL_SIGNALS */ + /**************************************************************************** * Name: nxsig_alloc_pendingsignal * @@ -275,24 +294,6 @@ nxsig_find_pendingsignal(FAR struct task_group_s *group, int signo) return sigpend; } -/**************************************************************************** - * Name: nxsig_dispatch_kernel_action - ****************************************************************************/ - -static void nxsig_dispatch_kernel_action(FAR struct tcb_s *stcb, - FAR siginfo_t *info) -{ - FAR struct task_group_s *group = stcb->group; - FAR sigactq_t *sigact; - - sigact = nxsig_find_action(group, info->si_signo); - if (sigact && (sigact->act.sa_flags & SA_KERNELHAND)) - { - info->si_user = sigact->act.sa_user; - (sigact->act.sa_sigaction)(info->si_signo, info, NULL); - } -} - /**************************************************************************** * Name: nxsig_add_pendingsignal * @@ -381,12 +382,18 @@ static int nxsig_alloc_dyn_pending(FAR irqstate_t *flags) { int ret = OK; bool alloc_signal = sq_empty(&g_sigpendingsignal); +#ifdef CONFIG_ENABLE_ALL_SIGNALS bool alloc_sigact = sq_empty(&g_sigpendingaction); if (alloc_signal || alloc_sigact) +#else + if (alloc_signal) +#endif { FAR sigpendq_t *sigpend = NULL; +#ifdef CONFIG_ENABLE_ALL_SIGNALS FAR sigq_t *sigq = NULL; +#endif /* We can't do memory allocations in idle task or interrupt */ @@ -406,12 +413,14 @@ static int nxsig_alloc_dyn_pending(FAR irqstate_t *flags) sigpend = kmm_malloc(sizeof(sigpendq_t)); } +#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Allocate more pending signal actions if there are no more */ if (alloc_sigact) { sigq = kmm_malloc(sizeof(sigq_t)); } +#endif /* Restore critical section and add the allocated structures to * the free pending queues @@ -432,6 +441,7 @@ static int nxsig_alloc_dyn_pending(FAR irqstate_t *flags) } } +#ifdef CONFIG_ENABLE_ALL_SIGNALS if (alloc_sigact) { if (sigq) @@ -444,11 +454,11 @@ static int nxsig_alloc_dyn_pending(FAR irqstate_t *flags) ret = -EAGAIN; } } +#endif } return ret; } -#endif /**************************************************************************** * Public Functions @@ -483,9 +493,9 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info, irqstate_t flags; int masked; int ret = OK; + FAR sigpendq_t *sigpend = NULL; #ifdef CONFIG_ENABLE_ALL_SIGNALS FAR sigactq_t *sigact; - FAR sigpendq_t *sigpend = NULL; #endif sinfo("TCB=%p pid=%d signo=%d code=%d value=%d masked=%s\n", @@ -519,14 +529,12 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info, * needs to be done here before using the task state or sigprocmask. */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS ret = nxsig_alloc_dyn_pending(&flags); if (ret < 0) { leave_critical_section(flags); return ret; } -#endif masked = nxsig_ismember(&stcb->sigprocmask, info->si_signo); @@ -594,19 +602,16 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info, up_switch_context(this_task(), rtcb); } -#ifdef CONFIG_ENABLE_ALL_SIGNALS -# ifdef CONFIG_LIB_SYSCALL +#if defined(CONFIG_LIB_SYSCALL) && defined(CONFIG_ENABLE_ALL_SIGNALS) /* Must also add signal action if in system call */ if (masked == 0) { sigpend = nxsig_add_pendingsignal(stcb, info, group_dispatch); } -# endif #endif } -#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Its not one we are waiting for... Add it to the list of pending * signals. */ @@ -615,7 +620,6 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info, { sigpend = nxsig_add_pendingsignal(stcb, info, group_dispatch); } -#endif } /************************* UNMASKED SIGNAL ACTIONS ************************/ @@ -727,14 +731,14 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info, leave_critical_section(flags); -#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Dispatch kernel action, if needed, in case a pending signal was added */ if (sigpend != NULL) { +#ifdef CONFIG_ENABLE_ALL_SIGNALS nxsig_dispatch_kernel_action(stcb, &sigpend->info); - } #endif + } /* In case nxsig_ismember failed due to an invalid signal number */ diff --git a/sched/signal/sig_initialize.c b/sched/signal/sig_initialize.c index 3bb977a784c..4582df1ecc3 100644 --- a/sched/signal/sig_initialize.c +++ b/sched/signal/sig_initialize.c @@ -41,8 +41,10 @@ struct sigpool_s { +#ifdef CONFIG_ENABLE_ALL_SIGNALS sigq_t sigq[NUM_PENDING_ACTIONS + CONFIG_SIG_PREALLOC_IRQ_ACTIONS]; +#endif sigpendq_t sigpendq[NUM_SIGNALS_PENDING + CONFIG_SIG_PREALLOC_IRQ_ACTIONS]; }; @@ -53,9 +55,8 @@ struct sigpool_s /* This is a pool of pre-allocated signal action structures buffers */ -#if CONFIG_SIG_PREALLOC_ACTIONS > 0 +#if defined(CONFIG_ENABLE_ALL_SIGNALS) && CONFIG_SIG_PREALLOC_ACTIONS > 0 sigactq_t g_sigactions[CONFIG_SIG_PREALLOC_ACTIONS]; -#endif /* The g_sigfreeaction data structure is a list of available signal * action structures. @@ -74,6 +75,7 @@ sq_queue_t g_sigpendingaction; */ sq_queue_t g_sigpendingirqaction; +#endif /* The g_sigpendingsignal data structure is a list of available pending * signal structures. @@ -100,7 +102,7 @@ static struct sigpool_s g_sigpool; * Private Functions ****************************************************************************/ -#if CONFIG_SIG_PREALLOC_ACTIONS > 0 +#if defined(CONFIG_ENABLE_ALL_SIGNALS) && CONFIG_SIG_PREALLOC_ACTIONS > 0 static void nxsig_init_signalactionblock(sq_queue_t *siglist, FAR sigactq_t *sigact, uint16_t nsigs) @@ -125,6 +127,7 @@ static void nxsig_init_signalactionblock(sq_queue_t *siglist, * ****************************************************************************/ +#ifdef CONFIG_ENABLE_ALL_SIGNALS static void *nxsig_init_block(sq_queue_t *siglist, FAR sigq_t *sigq, uint16_t nsigs, uint8_t sigtype) { @@ -138,6 +141,7 @@ static void *nxsig_init_block(sq_queue_t *siglist, FAR sigq_t *sigq, return sigq; } +#endif /**************************************************************************** * Name: nxsig_init_pendingsignalblock @@ -184,12 +188,15 @@ void nxsig_initialize(void) /* Initialize free lists */ +#if defined(CONFIG_ENABLE_ALL_SIGNALS) && CONFIG_SIG_PREALLOC_ACTIONS > 0 sq_init(&g_sigfreeaction); sq_init(&g_sigpendingaction); sq_init(&g_sigpendingirqaction); +#endif sq_init(&g_sigpendingsignal); sq_init(&g_sigpendingirqsignal); +#ifdef CONFIG_ENABLE_ALL_SIGNALS nxsig_init_signalactionblock(&g_sigfreeaction, g_sigactions, CONFIG_SIG_PREALLOC_ACTIONS); @@ -198,6 +205,8 @@ void nxsig_initialize(void) sigpool = nxsig_init_block(&g_sigpendingirqaction, sigpool, CONFIG_SIG_PREALLOC_IRQ_ACTIONS, SIG_ALLOC_IRQ); +#endif + sigpool = nxsig_init_pendingsignalblock(&g_sigpendingsignal, sigpool, NUM_SIGNALS_PENDING, SIG_ALLOC_FIXED); diff --git a/sched/signal/sig_kill.c b/sched/signal/sig_kill.c index bff39d81724..16927138eb8 100644 --- a/sched/signal/sig_kill.c +++ b/sched/signal/sig_kill.c @@ -77,10 +77,12 @@ int nxsig_kill(pid_t pid, int signo) { -#ifdef CONFIG_SCHED_HAVE_PARENT +#if !defined(CONFIG_DISABLE_ALL_SIGNALS) && defined(CONFIG_SCHED_HAVE_PARENT) FAR struct tcb_s *rtcb = this_task(); #endif +#ifndef CONFIG_DISABLE_ALL_SIGNALS siginfo_t info; +#endif /* We do not support sending signals to process groups */ @@ -89,6 +91,14 @@ int nxsig_kill(pid_t pid, int signo) return -ENOSYS; } + if (signo == 0) + { + return (nxsched_get_tcb(pid) != NULL) ? 0 : -ESRCH; + } + +#ifdef CONFIG_DISABLE_ALL_SIGNALS + return -ENOSYS; +#else /* Make sure that the signal is valid */ if (!GOOD_SIGNO(signo)) @@ -110,6 +120,7 @@ int nxsig_kill(pid_t pid, int signo) /* Send the signal */ return nxsig_dispatch(pid, &info, false); +#endif } /**************************************************************************** diff --git a/sched/signal/sig_procmask.c b/sched/signal/sig_procmask.c index cfc8d625077..529e07a939a 100644 --- a/sched/signal/sig_procmask.c +++ b/sched/signal/sig_procmask.c @@ -145,9 +145,7 @@ int nxsig_procmask(int how, FAR const sigset_t *set, FAR sigset_t *oset) /* Now, process any pending signals that were just unmasked */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS nxsig_unmask_pendingsignal(); -#endif } return ret; diff --git a/sched/signal/sig_tgkill.c b/sched/signal/sig_tgkill.c index 284738a6143..c1d09be9cae 100644 --- a/sched/signal/sig_tgkill.c +++ b/sched/signal/sig_tgkill.c @@ -75,12 +75,22 @@ int nxsig_tgkill(pid_t pid, pid_t tid, int signo) * will just deliver the signal to the thread ID it is requested to use. */ -#ifdef CONFIG_SCHED_HAVE_PARENT +#if !defined(CONFIG_DISABLE_ALL_SIGNALS) && defined(CONFIG_SCHED_HAVE_PARENT) FAR struct tcb_s *rtcb = this_task(); #endif +#ifndef CONFIG_DISABLE_ALL_SIGNALS siginfo_t info; int ret; +#endif + if (signo == 0) + { + return (nxsched_get_tcb(tid) != NULL) ? 0 : -ESRCH; + } + +#ifdef CONFIG_DISABLE_ALL_SIGNALS + return -ENOSYS; +#else /* Make sure that the signal is valid */ if (!GOOD_SIGNO(signo)) @@ -104,6 +114,7 @@ int nxsig_tgkill(pid_t pid, pid_t tid, int signo) errout: return ret; +#endif } /**************************************************************************** diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index 720f89c3f2a..19412b87474 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -103,10 +103,8 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, FAR const struct timespec *timeout) { FAR struct tcb_s *rtcb; -#ifdef CONFIG_ENABLE_ALL_SIGNALS sigset_t intersection; FAR sigpendq_t *sigpend; -#endif irqstate_t flags; siginfo_t unbinfo; int ret; @@ -122,7 +120,6 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, flags = enter_critical_section(); rtcb = this_task(); -#ifdef CONFIG_ENABLE_ALL_SIGNALS /* Check if there is a pending signal corresponding to one of the * signals in the pending signal set argument. */ @@ -159,7 +156,6 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, /* We will have to wait for a signal to be posted to this task. */ else -#endif { rtcb->sigunbinfo = (info == NULL) ? &unbinfo : info; diff --git a/sched/signal/signal.h b/sched/signal/signal.h index 549745c659f..46f64d56a52 100644 --- a/sched/signal/signal.h +++ b/sched/signal/signal.h @@ -166,9 +166,7 @@ struct task_group_s; /* sig_initializee.c */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS void nxsig_initialize(void); -#endif /* sig_action.c */ @@ -194,10 +192,8 @@ int nxsig_dispatch(pid_t pid, FAR siginfo_t *info, /* sig_cleanup.c */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS void nxsig_cleanup(FAR struct tcb_s *stcb); void nxsig_release(FAR struct task_group_s *group); -#endif /* sig_timedwait.c */ @@ -215,6 +211,13 @@ void nxsig_release_pendingsigaction(FAR sigq_t *sigq); void nxsig_release_pendingsignal(FAR sigpendq_t *sigpend); FAR sigpendq_t *nxsig_remove_pendingsignal(FAR struct tcb_s *stcb, int signo); +#ifndef CONFIG_DISABLE_ALL_SIGNALS bool nxsig_unmask_pendingsignal(void); +#else +static inline bool nxsig_unmask_pendingsignal(void) +{ + return false; +} +#endif #endif /* __SCHED_SIGNAL_SIGNAL_H */ diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index caece6bd99b..30703cd7862 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -455,7 +455,7 @@ void nxtask_exithook(FAR struct tcb_s *tcb, int status) /* Deallocate anything left in the TCB's queues */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS +#ifndef CONFIG_DISABLE_ALL_SIGNALS nxsig_cleanup(tcb); /* Deallocate Signal lists */ #endif diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index d129945e89d..753b40c451f 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -119,10 +119,8 @@ static void nxtask_reset_task(FAR struct tcb_s *tcb, bool remove) /* Deallocate anything left in the TCB's signal queues */ -#ifdef CONFIG_ENABLE_ALL_SIGNALS - nxsig_cleanup(tcb); /* Deallocate Signal lists */ -#endif #ifndef CONFIG_DISABLE_ALL_SIGNALS + nxsig_cleanup(tcb); /* Deallocate Signal lists */ sigemptyset(&tcb->sigprocmask); /* Reset sigprocmask */ #endif diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index ad82567192f..65ee13e7f1c 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -403,7 +403,6 @@ static int nxthread_setup_scheduler(FAR struct tcb_s *tcb, int priority, start_t start, CODE void *entry, uint8_t ttype) { - FAR struct tcb_s *rtcb = this_task(); irqstate_t flags; int ret; @@ -462,7 +461,7 @@ static int nxthread_setup_scheduler(FAR struct tcb_s *tcb, int priority, */ #ifndef CONFIG_DISABLE_ALL_SIGNALS - tcb->sigprocmask = rtcb->sigprocmask; + tcb->sigprocmask = this_task()->sigprocmask; #endif /* Initialize the task state. It does not get a valid state From 18b67b3de899cb95a92a7858d14abc2724127092 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 11 Jun 2026 20:14:46 +0200 Subject: [PATCH 105/268] arch/nrf91: implement LTE PSM/eDRX via the LAPI Add LTE_CMDID_SETPSM / LTE_CMDID_SETEDRX handling that encodes the requested PSM (T3412/T3324) and eDRX timers to AT+CPSMS / AT+CEDRXS, so the LTE power saving modes are controllable through the common LTE API. Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_sock.c | 134 ++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm/src/nrf91/nrf91_modem_sock.c b/arch/arm/src/nrf91/nrf91_modem_sock.c index c85557e32d2..2b190ee2d2a 100644 --- a/arch/arm/src/nrf91/nrf91_modem_sock.c +++ b/arch/arm/src/nrf91/nrf91_modem_sock.c @@ -606,6 +606,124 @@ static int nrf91_modem_actpdn(FAR lte_apn_setting_t *apn, return OK; } +/**************************************************************************** + * Name: nrf91_modem_bits + * + * Description: + * Format the low 'nbits' of 'value' as a binary string (MSB first), as + * used by the 3GPP timer fields of AT+CPSMS and AT+CEDRXS. + * + * Input Parameters: + * value - Value to format. + * nbits - Number of low-order bits to emit. + * out - Output buffer (must hold at least nbits + 1 bytes). + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void nrf91_modem_bits(uint8_t value, int nbits, FAR char *out) +{ + int i; + + for (i = 0; i < nbits; i++) + { + out[i] = (value & (1 << (nbits - 1 - i))) ? '1' : '0'; + } + + out[nbits] = '\0'; +} + +/**************************************************************************** + * Name: nrf91_modem_setpsm + * + * Description: + * Apply PSM settings (LTE_CMDID_SETPSM) by translating the LAPI + * lte_psm_setting_t into the AT+CPSMS command. + * + * Input Parameters: + * psm - PSM settings to apply. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int nrf91_modem_setpsm(FAR lte_psm_setting_t *psm) +{ + /* LAPI timer-unit enums -> 3GPP encoded unit bits (TS 24.008 GPRS timers). + * T3412 extended (periodic TAU) and T3324 (active time). + */ + + static const uint8_t t3412[] = + { + 3, 4, 5, 0, 1, 2, 6, 7 /* 2s,30s,1m,10m,1h,10h,320h,deact */ + }; + + static const uint8_t t3324[] = + { + 0, 1, 2, 7 /* 2s,1m,6m,deact */ + }; + + char tau[9]; + char act[9]; + uint8_t b; + + if (!psm->enable) + { + return nrf_modem_at_printf("AT+CPSMS=0"); + } + + b = (uint8_t)((t3412[psm->ext_periodic_tau_time.unit & 0x7] << 5) | + (psm->ext_periodic_tau_time.time_val & 0x1f)); + nrf91_modem_bits(b, 8, tau); + + b = (uint8_t)((t3324[psm->req_active_time.unit & 0x3] << 5) | + (psm->req_active_time.time_val & 0x1f)); + nrf91_modem_bits(b, 8, act); + + return nrf_modem_at_printf("AT+CPSMS=1,,,\"%s\",\"%s\"", tau, act); +} + +/**************************************************************************** + * Name: nrf91_modem_setedrx + * + * Description: + * Apply eDRX settings (LTE_CMDID_SETEDRX) by translating the LAPI + * lte_edrx_setting_t into the AT+CEDRXS command. + * + * Input Parameters: + * edrx - eDRX settings to apply. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int nrf91_modem_setedrx(FAR lte_edrx_setting_t *edrx) +{ + char value[5]; + int acttype; + + if (!edrx->enable || edrx->act_type == LTE_EDRX_ACTTYPE_NOTUSE) + { + /* Disable eDRX and discard any stored value */ + + return nrf_modem_at_printf("AT+CEDRXS=3"); + } + + /* AT+CEDRXS access technology: 4 = E-UTRAN WB-S1 (LTE-M), + * 5 = E-UTRAN NB-S1 (NB-IoT). The LAPI eDRX cycle enum matches the 4-bit + * 3GPP requested-eDRX value directly. + */ + + acttype = (edrx->act_type == LTE_EDRX_ACTTYPE_NBS1) ? 5 : 4; + nrf91_modem_bits((uint8_t)(edrx->edrx_cycle & 0xf), 4, value); + + return nrf_modem_at_printf("AT+CEDRXS=2,%d,\"%s\"", acttype, value); +} + /**************************************************************************** * Name: nrf91_ioctl_ltecmd ****************************************************************************/ @@ -719,6 +837,22 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) break; } + case LTE_CMDID_SETPSM: + { + lte_psm_setting_t **psm = + (lte_psm_setting_t **)(ltecmd->inparam); + ret = nrf91_modem_setpsm(*psm); + break; + } + + case LTE_CMDID_SETEDRX: + { + lte_edrx_setting_t **edrx = + (lte_edrx_setting_t **)(ltecmd->inparam); + ret = nrf91_modem_setedrx(*edrx); + break; + } + /* TODO: commands from include/nuttx/wireless/lte/lte.h */ default: From 78682572afd2b4bd2e68a78074163435dd5c0c31 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 12 Jun 2026 13:34:20 +0200 Subject: [PATCH 106/268] arch/arm/nrf91: improve LTE_CMDID_GETQUAL handling 1. Don't fail LTE GETQUAL on AT+CSQ error The LTE_CMDID_GETQUAL handler queried the modem with AT+CESQ (RSRP/RSRQ) and then AT+CSQ (RSSI), returning the result of the last command. Set 'valid' only when AT+CESQ parses, treat AT+CSQ as optional, zero the metrics up front, and return OK so the caller inspects 'valid'. 2. get SNIR Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_sock.c | 39 +++++++++++++++++---------- 1 file changed, 25 insertions(+), 14 deletions(-) diff --git a/arch/arm/src/nrf91/nrf91_modem_sock.c b/arch/arm/src/nrf91/nrf91_modem_sock.c index 2b190ee2d2a..5b89201fc11 100644 --- a/arch/arm/src/nrf91/nrf91_modem_sock.c +++ b/arch/arm/src/nrf91/nrf91_modem_sock.c @@ -801,10 +801,19 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) { lte_quality_t **quality = (lte_quality_t **)(ltecmd->outparam + 1); + bool valid = false; + int cresult; int tmp; int rsrp; int rsrq; - int rssi; + int snr; + + (*quality)->rsrp = 0; + (*quality)->rsrq = 0; + (*quality)->rssi = 0; + (*quality)->sinr = 0; + + /* RSRP/RSRQ via AT+CESQ - available whenever the modem is camped. */ ret = nrf_modem_at_scanf("AT+CESQ", "+CESQ: %d,%d,%d,%d,%d,%d", @@ -812,28 +821,30 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) &rsrq, &rsrp); if (ret > 0) { - (*quality)->rsrq = (rsrq / 2) - 19; - (*quality)->rsrp = rsrp - 140; + (*quality)->rsrq = (rsrq / 2) - 19; + (*quality)->rsrp = rsrp - 140; + valid = true; } else { nerr("AT+CESQ failed %d\n", ret); } - ret = nrf_modem_at_scanf("AT+CSQ", - "+CSQ: %d,%d", - &rssi, &tmp); - if (ret > 0) + /* SNR via AT%CONEVAL - the only SNR source on this modem (AT+CSQ is + * not answered and carries no SNR). Reported SNR is the raw + * value - 24. + */ + + ret = nrf_modem_at_scanf("AT%CONEVAL", + "%%CONEVAL: %d,%d,%d,%d,%d,%d", + &cresult, &tmp, &tmp, &tmp, &tmp, &snr); + if (ret >= 6 && cresult == 0) { - (*quality)->rssi = rssi; - (*quality)->sinr = 0; - } - else - { - nerr("AT+CSQ failed %d\n", ret); + (*quality)->sinr = snr - 24; } - (*quality)->valid = true; + (*quality)->valid = valid; + ret = OK; break; } From 1b600bd282dd058be40232ca6c989e651f83f09e Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Fri, 12 Jun 2026 14:20:46 +0200 Subject: [PATCH 107/268] arch/arm/nrf91: add support for LTE_CMDID_GETCELL add support for LTE_CMDID_GETCELL ioctl call Signed-off-by: raiden00pl --- arch/arm/src/nrf91/nrf91_modem_sock.c | 32 +++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm/src/nrf91/nrf91_modem_sock.c b/arch/arm/src/nrf91/nrf91_modem_sock.c index 5b89201fc11..4a10e1e9b4d 100644 --- a/arch/arm/src/nrf91/nrf91_modem_sock.c +++ b/arch/arm/src/nrf91/nrf91_modem_sock.c @@ -848,6 +848,38 @@ static int nrf91_ioctl_ltecmd(int fd, int cmd, unsigned long arg) break; } + case LTE_CMDID_GETCELL: + { + lte_cellinfo_t **cell = + (lte_cellinfo_t **)(ltecmd->outparam + 1); + int band = 0; + + (*cell)->valid = false; + (*cell)->phycell_id = 0; + (*cell)->earfcn = 0; + (*cell)->option = 0; + (*cell)->nr_neighbor = 0; + + /* The modem AT set does not expose the raw EARFCN in a form the + * scanf parser here can extract from AT%XMONITOR (quoted fields), so + * report the serving band number via AT%XCBAND in the earfcn field. + */ + + ret = nrf_modem_at_scanf("AT%XCBAND", "%%XCBAND: %d", &band); + if (ret > 0) + { + (*cell)->earfcn = (uint32_t)band; + (*cell)->valid = true; + } + else + { + nerr("AT%%XCBAND failed %d\n", ret); + } + + ret = OK; + break; + } + case LTE_CMDID_SETPSM: { lte_psm_setting_t **psm = From dc830cefdd03efadfeae254c7f4b305256a61af5 Mon Sep 17 00:00:00 2001 From: nicolasWDC Date: Wed, 10 Jun 2026 12:58:30 +0000 Subject: [PATCH 108/268] include/pthread : initialize wait_count in PTHREAD_COND_INITIALIZER struct pthread_cond_s contains three fields: sem, clockid, and wait_count. However, PTHREAD_COND_INITIALIZER only initialized the first two fields, which triggers -Wmissing-field-initializers when a condition variable is statically initialized. Initialize wait_count explicitly to zero so the macro matches the structure definition and remains warning-free with strict compiler flags. Validated with a minimal compile test using: pthread_cond_t cond = PTHREAD_COND_INITIALIZER; Signed-off-by: nicolasWDC --- include/pthread.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pthread.h b/include/pthread.h index 561b6070b96..201d593051b 100644 --- a/include/pthread.h +++ b/include/pthread.h @@ -279,7 +279,7 @@ typedef struct pthread_cond_s pthread_cond_t; # define __PTHREAD_COND_T_DEFINED 1 #endif -#define PTHREAD_COND_INITIALIZER {SEM_INITIALIZER(0), CLOCK_REALTIME } +#define PTHREAD_COND_INITIALIZER {SEM_INITIALIZER(0), CLOCK_REALTIME, 0} struct pthread_mutexattr_s { From b82ceb62a7a45ab46ce4201fd5ca4b77caad16f6 Mon Sep 17 00:00:00 2001 From: Catalin Visinescu Date: Mon, 15 Jun 2026 00:35:53 -0400 Subject: [PATCH 109/268] arch/arm/src/at32/at32_can: Division by Zero in CAN Bit Timing Commands An unchecked integer assignment in the CAN driver may result in a division-by-zero which would result in a kernel crash (denial of service). Tested locally, builds fine. An unchecked integer assignment in the CAN driver may result in a division-by-zero which would result in a kernel crash (denial of service). The CAN driver `can_ioctl` function, shown below (drivers/can/can.c), receives commands from user processes. Its received arguments `cmd` and content of `arg` are under attacker's control. In the CAN driver, some `ioctl` commands are hardware specific and are processed by calling `dev_ioctl()`. Subsequently, depending on the hardware (STM32 or AT32), this function calls `fdcan_ioctl` or `at32can_ioctl`, as shown in the snippets that follow. ```c static int can_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { FAR struct inode *inode = filep->f_inode; FAR struct can_dev_s *dev = inode->i_private; FAR struct can_reader_s *reader = filep->f_priv; ... flags = enter_critical_section(); /* Handle built-in ioctl commands */ switch (cmd) { ... /* Not a "built-in" ioctl command.. perhaps it is unique to this * lower-half, device driver. */ default: { ret = dev_ioctl(dev, cmd, arg); } break; } leave_critical_section(flags); return ret; } ``` There are a few instances where the user can trigger a kernel crash, caused by a division by zero on `CANIOC_SET_BITTIMING` command. On STM32 platforms (arch/arm/src/stm32/stm32_fdcan.c), while there is a `DEBUGASSERT` assertion for `bt->bt_baud`, the check does not cover value `0`. ```c static const struct can_ops_s g_fdcanops = { ... .co_ioctl = fdcan_ioctl, ... }; static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) { ... switch (cmd) { ... case CANIOC_SET_BITTIMING: { const struct canioc_bittiming_s *bt = (const struct canioc_bittiming_s *)arg; uint32_t nbrp; uint32_t ntseg1; uint32_t ntseg2; uint32_t nsjw; uint32_t ie; uint8_t state; DEBUGASSERT(bt != NULL); DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); // <- not valid DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); /* Extract bit timing data */ ntseg1 = bt->bt_tseg1 - 1; ntseg2 = bt->bt_tseg2 - 1; nsjw = bt->bt_sjw - 1; nbrp = (uint32_t) ( ((float) STM32_FDCANCLK_FREQUENCY / ((float)(ntseg1 + ntseg2 + 3) * (float)bt->bt_baud)) - 1 ); // <- div by 0 ``` Similarly, another division by zero was found in Artery Technology AT32 (arch/arm/src/stm32/stm32_can.c) driver: ```c static const struct can_ops_s g_canops = { ... .co_ioctl = at32can_ioctl, ... }; static int at32can_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) { ... /* Handle the command */ switch (cmd) { ... case CANIOC_SET_BITTIMING: { const struct canioc_bittiming_s *bt = (const struct canioc_bittiming_s *)arg; ... uint32_t tmp; uint32_t regval; DEBUGASSERT(bt != NULL); DEBUGASSERT(bt->bt_baud < AT32_PCLK1_FREQUENCY); // <- not valid DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); regval = at32can_getreg(priv, AT32_CAN_BTMG_OFFSET); /* Extract bit timing data tmp is in clocks per bit time */ tmp = AT32_PCLK1_FREQUENCY / bt->bt_baud; // <- div by 0 ``` Instances found are listed in the *Location* section below. They are not shown in detail to reduce the length of the issue. Ensure the attacker-controlled data is properly validated before use, to stop division by zero situations. For instance: ```c DEBUGASSERT(bt->bt_baud > 0 && bt->bt_baud < AT32_PCLK1_FREQUENCY); ``` * arch/arm/src/stm32/stm32_fdcan.c * arch/arm/src/stm32/stm32_can.c * arch/arm/src/sama5/sam_mcan.c * arch/arm/src/at32/at32_can.c * arch/arm/src/samv7/sam_mcan.c * arch/arm/src/stm32f0l0g0/stm32_fdcan.c * arch/arm/src/stm32f7/stm32_can.c * arch/arm/src/stm32h5/stm32_fdcan.c * arch/arm/src/stm32l4/stm32l4_can.c * arch/arm/src/tiva/common/tiva_can.c * drivers/can/mcp2515.c Signed-off-by: Catalin Visinescu --- arch/arm/src/at32/at32_can.c | 2 +- arch/arm/src/sama5/sam_mcan.c | 3 ++- arch/arm/src/samv7/sam_mcan.c | 3 ++- arch/arm/src/stm32/stm32_can.c | 3 ++- arch/arm/src/stm32/stm32_fdcan.c | 3 ++- arch/arm/src/stm32f0l0g0/stm32_fdcan.c | 3 ++- arch/arm/src/stm32f7/stm32_can.c | 3 ++- arch/arm/src/stm32h5/stm32_fdcan.c | 3 ++- arch/arm/src/stm32l4/stm32l4_can.c | 3 ++- arch/arm/src/tiva/common/tiva_can.c | 8 +++++--- drivers/can/mcp2515.c | 3 ++- 11 files changed, 24 insertions(+), 13 deletions(-) diff --git a/arch/arm/src/at32/at32_can.c b/arch/arm/src/at32/at32_can.c index 89b6dc43dab..1865f9cf97b 100644 --- a/arch/arm/src/at32/at32_can.c +++ b/arch/arm/src/at32/at32_can.c @@ -973,7 +973,7 @@ static int at32can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < AT32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && bt->bt_baud < AT32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); diff --git a/arch/arm/src/sama5/sam_mcan.c b/arch/arm/src/sama5/sam_mcan.c index 7860c0a5afa..0b515fec719 100644 --- a/arch/arm/src/sama5/sam_mcan.c +++ b/arch/arm/src/sama5/sam_mcan.c @@ -2721,7 +2721,8 @@ static int mcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) uint8_t state; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < SAMA5_MCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < SAMA5_MCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 847a25d31c5..164bba5d0a4 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -2789,7 +2789,8 @@ static int mcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) uint8_t state; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < SAMV7_MCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < SAMV7_MCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index d0e8373aa36..35bc9e71781 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -971,7 +971,8 @@ static int stm32can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/stm32/stm32_fdcan.c index 519b77626e9..2e2574217eb 100644 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ b/arch/arm/src/stm32/stm32_fdcan.c @@ -2136,7 +2136,8 @@ static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) uint8_t state; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_FDCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c index 02d2c0f773d..d32259614db 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/stm32f0l0g0/stm32_fdcan.c @@ -1832,7 +1832,8 @@ static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) uint8_t state; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_FDCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); diff --git a/arch/arm/src/stm32f7/stm32_can.c b/arch/arm/src/stm32f7/stm32_can.c index 2d571c61b8d..2df5a048649 100644 --- a/arch/arm/src/stm32f7/stm32_can.c +++ b/arch/arm/src/stm32f7/stm32_can.c @@ -912,7 +912,8 @@ static int stm32can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); diff --git a/arch/arm/src/stm32h5/stm32_fdcan.c b/arch/arm/src/stm32h5/stm32_fdcan.c index 639f0e7e1d9..1be0ff65cbc 100644 --- a/arch/arm/src/stm32h5/stm32_fdcan.c +++ b/arch/arm/src/stm32h5/stm32_fdcan.c @@ -2007,7 +2007,8 @@ static int fdcan_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) uint8_t state; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_FDCANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_FDCANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 16); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 64); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 16); diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 9d6231f4f1f..84225c4cc56 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -848,7 +848,8 @@ static int stm32l4can_ioctl(struct can_dev_s *dev, int cmd, uint32_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < STM32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < STM32_PCLK1_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); diff --git a/arch/arm/src/tiva/common/tiva_can.c b/arch/arm/src/tiva/common/tiva_can.c index 57e5a96cec7..a28eb70f3e3 100644 --- a/arch/arm/src/tiva/common/tiva_can.c +++ b/arch/arm/src/tiva/common/tiva_can.c @@ -971,11 +971,13 @@ static int tivacan_ioctl(struct can_dev_s *dev, int cmd, timing.tseg1 = bt->bt_tseg1; timing.tseg2 = bt->bt_tseg2; timing.sjw = bt->bt_sjw; + DEBUGASSERT(timing.tseg1 <= 16 && timing.tseg1 >= 1); + DEBUGASSERT(timing.tseg2 <= 8 && timing.tseg2 >= 1); + DEBUGASSERT(timing.sjw <= 4 && timing.sjw >= 1); + DEBUGASSERT(bt->bt_baud > 0); + timing.prescaler = SYSCLK_FREQUENCY / (bt->bt_baud * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); - DEBUGASSERT(timing.tseg1 <= 16 && timing.tseg1 >= 1); - DEBUGASSERT(timing.tseg2 <= 8 && timing.tseg1 >= 1); - DEBUGASSERT(timing.sjw <= 4 && timing.sjw >= 1); DEBUGASSERT(timing.prescaler <= 1024 && timing.prescaler >= 1); tivacan_bittiming_set(dev, &timing); diff --git a/drivers/can/mcp2515.c b/drivers/can/mcp2515.c index 3246da490d3..e31b49fbee3 100644 --- a/drivers/can/mcp2515.c +++ b/drivers/can/mcp2515.c @@ -1526,7 +1526,8 @@ static int mcp2515_ioctl(FAR struct can_dev_s *dev, int cmd, uint8_t regval; DEBUGASSERT(bt != NULL); - DEBUGASSERT(bt->bt_baud < MCP2515_CANCLK_FREQUENCY); + DEBUGASSERT(bt->bt_baud > 0 && + bt->bt_baud < MCP2515_CANCLK_FREQUENCY); DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); DEBUGASSERT(bt->bt_tseg1 > 1 && bt->bt_tseg1 <= 16); DEBUGASSERT(bt->bt_tseg2 > 1 && bt->bt_tseg2 <= 8); From 6d52766ea3f0291bbe95173ce014c0f61f109b7d Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Wed, 10 Jun 2026 08:34:35 -0300 Subject: [PATCH 110/268] boards/risc-v/esp32p4: Enable NuttX Web Panel for ESP32-P4 This commit adds a defconfig for enabling the NuttX Web Panel on ESP32-P4. It also create entries to automatically call the Web panel application after system's boot up. The `webpanel` is removed from regular ESP32-P4 CI testing because it ships with Python and that would overload CI infrastructure. Signed-off-by: Tiago Medicci Serrano --- boards/risc-v/esp32p4/common/src/Make.defs | 4 + .../esp32p4/common/src/etc/init.d/rc.sysinit | 23 +++ .../risc-v/esp32p4/common/src/etc/init.d/rcS | 35 +++++ .../configs/webpanel/defconfig | 148 ++++++++++++++++++ tools/ci/testlist/risc-v-03.dat | 1 + tools/ci/testlist/risc-v-07.dat | 1 + 6 files changed, 212 insertions(+) create mode 100644 boards/risc-v/esp32p4/common/src/etc/init.d/rc.sysinit create mode 100644 boards/risc-v/esp32p4/common/src/etc/init.d/rcS create mode 100644 boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/webpanel/defconfig diff --git a/boards/risc-v/esp32p4/common/src/Make.defs b/boards/risc-v/esp32p4/common/src/Make.defs index 640235bcb10..7436d237a20 100644 --- a/boards/risc-v/esp32p4/common/src/Make.defs +++ b/boards/risc-v/esp32p4/common/src/Make.defs @@ -80,6 +80,10 @@ ifeq ($(CONFIG_ESPRESSIF_ULP_USE_TEST_BIN),y) include $(TOPDIR)$(DELIM)arch$(DELIM)risc-v$(DELIM)src$(DELIM)common$(DELIM)espressif$(DELIM)ulp_makefile endif +ifeq ($(CONFIG_ETC_ROMFS),y) + RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/risc-v/esp32p4/common/src/etc/init.d/rc.sysinit b/boards/risc-v/esp32p4/common/src/etc/init.d/rc.sysinit new file mode 100644 index 00000000000..0d263ee2222 --- /dev/null +++ b/boards/risc-v/esp32p4/common/src/etc/init.d/rc.sysinit @@ -0,0 +1,23 @@ +/**************************************************************************** + * boards/risc-v/esp32p4/common/src/etc/init.d/rc.sysinit + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include diff --git a/boards/risc-v/esp32p4/common/src/etc/init.d/rcS b/boards/risc-v/esp32p4/common/src/etc/init.d/rcS new file mode 100644 index 00000000000..e46d0109336 --- /dev/null +++ b/boards/risc-v/esp32p4/common/src/etc/init.d/rcS @@ -0,0 +1,35 @@ +/**************************************************************************** + * boards/risc-v/esp32p4/common/src/etc/init.d/rcS + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +#ifdef CONFIG_SYSTEM_HOSTNAME +hostname webpanel +#endif + +#ifdef CONFIG_EXAMPLES_WEBPANEL +webpanel & +#endif + +#ifdef CONFIG_EXAMPLES_MDNSD +mdnsd_event & +#endif diff --git a/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/webpanel/defconfig b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/webpanel/defconfig new file mode 100644 index 00000000000..4c90b61be34 --- /dev/null +++ b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/webpanel/defconfig @@ -0,0 +1,148 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32p4-function-ev-board" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32P4_FUNCTION_EV_BOARD=y +CONFIG_ARCH_CHIP="esp32p4" +CONFIG_ARCH_CHIP_ESP32P4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=17 +CONFIG_ARCH_RISCV=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_COVERAGE_DEFAULT_PREFIX="/mnt" +CONFIG_DEV_GPIO=y +CONFIG_DEV_URANDOM=y +CONFIG_ESPRESSIF_EMAC=y +CONFIG_ESPRESSIF_ETH_DMA_BUFFER_SIZE=512 +CONFIG_ESPRESSIF_FLASH_16M=y +CONFIG_ESPRESSIF_FLASH_MODE_QIO=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_ESPRESSIF_LEDC=y +CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN=6 +CONFIG_ESPRESSIF_LEDC_TIMER0=y +CONFIG_ESPRESSIF_MERGE_BINS=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_FS_MOUNT_PT="/mnt" +CONFIG_ESPRESSIF_SPIFLASH_SMARTFS=y +CONFIG_ESPRESSIF_SPIRAM=y +CONFIG_ESPRESSIF_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY=y +CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET=0xFCA000 +CONFIG_ESPRESSIF_STORAGE_MTD_SIZE=0x36000 +CONFIG_ETC_ROMFS=y +CONFIG_EVENT_FD=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_EXAMPLES_MDNSD=y +CONFIG_EXAMPLES_MDNS_SERVICE="_http._tcp.local." +CONFIG_EXAMPLES_MDNS_SERVICE_PORT="80" +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_WEBPANEL=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_BINFS=y +CONFIG_FS_HEAPBUF_SECTION=".ext_ram.bss.buf" +CONFIG_FS_HEAPSIZE=2097152 +CONFIG_FS_LARGEFILE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_TMPFS=y +CONFIG_FS_UNIONFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_INTERPRETERS_CPYTHON=y +CONFIG_INTERPRETERS_CPYTHON_ENABLE_PIP=y +CONFIG_INTERPRETERS_CPYTHON_PYTHONPATH="/mnt" +CONFIG_INTERPRETERS_CPYTHON_STACKSIZE=512000 +CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_LOCALE=y +CONFIG_LIBC_LOCALE_GETTEXT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIB_LIBFFI=y +CONFIG_LIB_MDNS=y +CONFIG_LIB_ZLIB=y +CONFIG_LINE_MAX=200 +CONFIG_MM_KERNEL_HEAP=y +CONFIG_MM_REGIONS=2 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETLINK_ROUTE=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_LIBWEBSOCKETS=y +CONFIG_NETUTILS_LIBWEBSOCKETS_SERVER=y +CONFIG_NETUTILS_MDNS=y +CONFIG_NETUTILS_MDNS_DAEMON=y +CONFIG_NETUTILS_MDNS_STACKSIZE=4096 +CONFIG_NETUTILS_THTTPD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_NETLINK=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PSEUDOTERM=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_HOSTNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_SYSTEM_SYSTEM_STACKSIZE=4096 +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_TESTING_HEAP=y +CONFIG_THTTPD_CGI_PATH="/data/www/cgi-bin" +CONFIG_THTTPD_CGI_PATTERN="/data/www/cgi-bin/*" +CONFIG_THTTPD_CGI_STACKSIZE=4096 +CONFIG_THTTPD_CHARSET="utf-8" +CONFIG_THTTPD_INDEX_NAMES="index.html" +CONFIG_THTTPD_IOBUFFERSIZE=2048 +CONFIG_THTTPD_IPADDR=0x00000000 +CONFIG_THTTPD_PATH="/data/www" +CONFIG_THTTPD_SERVER_ADDRESS="http://nuttx.local" +CONFIG_THTTPD_SERVER_SOFTWARE="NuttX-WebPanel/1.0" +CONFIG_TIMER=y +CONFIG_TIMER_FD=y +CONFIG_TLS_NELEM=4 +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WEBCLIENT_MAXFILENAME=300 diff --git a/tools/ci/testlist/risc-v-03.dat b/tools/ci/testlist/risc-v-03.dat index 2d220201225..c36d9781348 100644 --- a/tools/ci/testlist/risc-v-03.dat +++ b/tools/ci/testlist/risc-v-03.dat @@ -1,3 +1,4 @@ /risc-v/esp32c[6-z]* /risc-v/esp32[d-z]* -esp32p4-function-ev-board:python +-esp32p4-function-ev-board:webpanel diff --git a/tools/ci/testlist/risc-v-07.dat b/tools/ci/testlist/risc-v-07.dat index 45aca82670f..5a800fb0623 100644 --- a/tools/ci/testlist/risc-v-07.dat +++ b/tools/ci/testlist/risc-v-07.dat @@ -1,2 +1,3 @@ /risc-v/qemu-rv/rv-virt/configs/python /risc-v/esp32p4/esp32p4-function-ev-board/configs/python +/risc-v/esp32p4/esp32p4-function-ev-board/configs/webpanel From adc3d4c40824465ea2d05acd8a6fbe14eaea351e Mon Sep 17 00:00:00 2001 From: Tiago Medicci Serrano Date: Tue, 16 Jun 2026 14:32:45 -0300 Subject: [PATCH 111/268] Documentation: Add NuttX Web Panel documentation entry This commits adds an example of the NuttX Web Panel documentation along with its usage on ESP32-P4. Signed-off-by: Tiago Medicci Serrano --- .../applications/examples/webpanel/index.rst | 112 ++++++++++++++++++ .../examples/webpanel/nuttx-webpanel-home.png | Bin 0 -> 91859 bytes .../esp32p4-function-ev-board/index.rst | 6 + 3 files changed, 118 insertions(+) create mode 100644 Documentation/applications/examples/webpanel/index.rst create mode 100644 Documentation/applications/examples/webpanel/nuttx-webpanel-home.png diff --git a/Documentation/applications/examples/webpanel/index.rst b/Documentation/applications/examples/webpanel/index.rst new file mode 100644 index 00000000000..7562ab7393a --- /dev/null +++ b/Documentation/applications/examples/webpanel/index.rst @@ -0,0 +1,112 @@ +.. _nuttx-webpanel: + +==================================== +``webpanel`` NuttX Web Panel +==================================== + +This guide explains how to run the NuttX Web Panel. + +The NuttX Web Panel is a self-hosted web interface for device management. It +provides a browser-based dashboard with system information, an NSH terminal, +file management on SmartFS, and network configuration. The application is +implemented in ``apps/examples/webpanel/`` and is inspired by consumer IoT +management panels. + +.. figure:: nuttx-webpanel-home.png + :align: center + :alt: NuttX Web Panel home page on ESP32-P4 + + NuttX Web Panel home page on ESP32-P4 (``esp32p4-function-ev-board:webpanel``) + +How Does it Work? +================= + +The web panel combines several NuttX components: + +1. **THTTPD** serves static HTML/CSS/JavaScript from a ROMFS image mounted at + ``/data/www``. +2. **BINFS** and **UNIONFS** expose built-in CGI programs under + ``/data/www/cgi-bin`` for dynamic requests (system info, file listing, + upload, and DHCP renew). +3. **libwebsockets** provides a WebSocket server (TCP port 8080) that spawns + an NSH session over a POSIX pseudo-terminal for the browser terminal. +4. **mDNS** advertises the HTTP service as ``webpanel.local`` (``_http._tcp`` + on port 80). The ``mdnsd_event`` application starts the mDNS daemon when + an IP address is assigned. +5. **SmartFS** on SPI flash (mounted at ``/mnt``) stores user files, including + uploaded Python scripts. + +On boot, ``/etc/init.d/rcS`` (enabled via ``CONFIG_ETC_ROMFS``) sets the +hostname to ``webpanel``, starts ``webpanel`` in the background, and launches +``mdnsd_event`` to register the HTTP service once DHCP completes. + +Building and Running the Web Panel +================================== + +ESP32-P4-Function-EV-Board +-------------------------- + +For this example, use the ESP32-P4-Function-EV-Board with Ethernet connected +to the board PHY port. The ``esp32p4-function-ev-board:webpanel`` defconfig +requires **16 MB** flash (see ``CONFIG_ESPRESSIF_FLASH_16M``). + +This defconfig includes the CPython interpreter and produces a large firmware +image. A full clean build may take several minutes. + +Build and flash the board with the following commands: + +.. code:: console + + $ cd nuttx + $ make distclean + $ ./tools/configure.sh esp32p4-function-ev-board:webpanel + $ make -j$(nproc) flash ESPTOOL_PORT=/dev/ttyACM0 + +On **v1.5.2**, use ``/dev/ttyACM0`` (USB Serial/JTAG) for flashing. UART0 +(GPIO37/GPIO38) remains the serial console; attach an external USB-to-UART +adapter to monitor NSH while the web panel runs. + +After flashing, connect the Ethernet cable and wait for DHCP. Then open a browser +on the same LAN: + +.. code:: text + + http://webpanel.local + +If mDNS is unavailable, check the assigned address on the serial console: + +.. code:: console + + nsh> ifconfig + eth0 Link encap:Ethernet HWaddr 30:ed:a0:ec:f1:60 at RUNNING mtu 1500 + inet addr:10.0.10.50 DRaddr:10.0.10.1 Mask:255.255.255.0 + +and browse to ``http://`` instead. + +The interface provides four sections: + +* **Home** — live system and network information +* **Terminal** — browser NSH shell over WebSocket +* **Files** — browse, upload, and run scripts on ``/mnt`` +* **Network** — interface details and DHCP lease renewal + +Python scripts can be uploaded through the **Files** tab and executed from the +**Terminal** tab or via the **Run** button for ``.py`` files. See also the +:doc:`Python Interpreter ` page. + +Configuration +============= + +The web panel is enabled with ``CONFIG_EXAMPLES_WEBPANEL``. The defconfig also +enables the dependencies selected by that option, including THTTPD, +libwebsockets (server mode), BINFS, UNIONFS, and pseudo-terminal support. + +Key Kconfig options (under ``Application Configuration`` → +``Examples`` → ``Web Panel for device management``): + +* ``CONFIG_EXAMPLES_WEBPANEL_NETIF`` — network interface name (default + ``eth0``) +* ``CONFIG_EXAMPLES_WEBPANEL_WS_PORT`` — WebSocket terminal port (default + ``8080``) +* ``CONFIG_EXAMPLES_MDNS_SERVICE`` / ``CONFIG_EXAMPLES_MDNS_SERVICE_PORT`` — + mDNS service type and port advertised by ``mdnsd_event`` diff --git a/Documentation/applications/examples/webpanel/nuttx-webpanel-home.png b/Documentation/applications/examples/webpanel/nuttx-webpanel-home.png new file mode 100644 index 0000000000000000000000000000000000000000..1e3e680503749e6a829397ba567de79647f7fba3 GIT binary patch literal 91859 zcmeFZ2UwG9w;^{^pZe;Pz4ft?;S;YCj^kt zq!(#YL_uJp|2hBOXU_TWJoC(%`^>$w-?Wu)t#`GzeCuuB)u*e^fcs!YkRssPH2~lm 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zHf@371%Ijmp$*BekDj!e{PBcP*{7Ws^N124ikgn3mE>s3dp%F3S#vSvAlyj(BR9Z_ zy`EOo6Ylp%GGd{vTXnf_bOCd!?xK%AXW^A#zbB)%o#As+^e-c5O<#XBJ1ckcM>4_j z2D8;ff`^15QtxJ4n!^tNNM=*&**401?#(4KpYoQV=Ty7DC&Meq{y`xL%Yk{&^(%K) zeosd52R&B-w9w5C5_5}WUX;@2Ske>S%eY^$f~8QMxTOg@jkBqpUh z`_>x2;VU}`0Gy*UU%;3k%pcI~{Rq$=t9nsI`a6#J#b%u(6QBPPxJc8`8sZNSzwkFd z)c)~ojAPQU_SK)u! zWe#z5IS|ZHbS+P=%>&YyLOo*cOA+FcsdcP{sR!H-cJk`p_S|@kDJdJg@8iP%E` page. + Related Documentation ===================== From 6cda50bf81c13b28ad877bb9f886881c567c7936 Mon Sep 17 00:00:00 2001 From: Catalin Visinescu Date: Wed, 17 Jun 2026 17:33:10 -0400 Subject: [PATCH 112/268] drivers/eeprom/i2c_xx24xx: Integer Overflow in I2C EEPROM ee24xx_seek() The function seek which allows the user to move the cursor to a particular offset in order to read and write from EEPROM storage does not validate the offset is valid. Later, this can cause an out-of-bounds reads or writes. Note that newpos may store a large value, larger than the size of the EEPROM. Similar change in the SPI driver. Tested locally, builds fine. Signed-off-by: Catalin Visinescu --- drivers/eeprom/i2c_xx24xx.c | 17 ++++++++++++++++- drivers/eeprom/spi_xx25xx.c | 17 ++++++++++++++++- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/eeprom/i2c_xx24xx.c b/drivers/eeprom/i2c_xx24xx.c index 9cdaab9c0ca..fe9ef045a2f 100644 --- a/drivers/eeprom/i2c_xx24xx.c +++ b/drivers/eeprom/i2c_xx24xx.c @@ -570,20 +570,35 @@ static off_t ee24xx_seek(FAR struct file *filep, off_t offset, int whence) return ret; } - /* Determine the new, requested file position */ + /* Determine the new, requested file position + * For EEPROM sparse files are not allowed. + * "offset" can be negative, "newpos" must be between 0 and eedev->size + */ switch (whence) { case SEEK_CUR: newpos = filep->f_pos + offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; case SEEK_SET: newpos = offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; case SEEK_END: newpos = eedev->size + offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; default: diff --git a/drivers/eeprom/spi_xx25xx.c b/drivers/eeprom/spi_xx25xx.c index 4076c186e86..f4bb68dd915 100644 --- a/drivers/eeprom/spi_xx25xx.c +++ b/drivers/eeprom/spi_xx25xx.c @@ -929,20 +929,35 @@ static off_t ee25xx_seek(FAR struct file *filep, off_t offset, int whence) return ret; } - /* Determine the new, requested file position */ + /* Determine the new, requested file position + * For EEPROM sparse files are not allowed. + * "offset" can be negative, "newpos" must be between 0 and eedev->size + */ switch (whence) { case SEEK_CUR: newpos = filep->f_pos + offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; case SEEK_SET: newpos = offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; case SEEK_END: newpos = eedev->size + offset; + if (newpos < 0 || newpos > eedev->size) + { + return -EINVAL; + } break; default: From 8e843b22e628ccbd0a0d12cae72030caafa3ff4b Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Wed, 17 Jun 2026 17:15:19 +0000 Subject: [PATCH 113/268] docs/nsh: document id, su, whoami, and privilege prompt markers Document NSH identity commands and how login/su update the prompt (# for effective root, $ for non-root). Cover flat-build euid semantics, related Kconfig options, and session identity behavior after login. --- Documentation/applications/nsh/commands.rst | 144 ++++++++++++++++++++ Documentation/applications/nsh/login.rst | 52 +++++++ 2 files changed, 196 insertions(+) diff --git a/Documentation/applications/nsh/commands.rst b/Documentation/applications/nsh/commands.rst index bc6abcafc23..e21c6e80044 100644 --- a/Documentation/applications/nsh/commands.rst +++ b/Documentation/applications/nsh/commands.rst @@ -740,6 +740,50 @@ supported: ifup eth0 +.. _cmdid: + +``id`` Show User and Group Identity +=================================== + +**Command Syntax**:: + + id + +**Synopsis**. Print the real and effective user and group IDs for the +current NSH session in the form:: + + uid= euid= gid= egid= + +File permission checks use the effective UID and GID. + +On flat builds where NSH retains a real UID of zero, ``id`` may report +``uid=0`` even when the session is running as a non-root user. The +``euid`` and ``egid`` fields reflect the active session identity, and +the prompt marker (``#`` or ``$``) follows ``euid``. + +This command is available only when ``CONFIG_SCHED_USER_IDENTITY`` is +enabled. It may be disabled with ``CONFIG_NSH_DISABLE_ID``. + +**Related configuration** + +=============================== ======================================= +Option Purpose +=============================== ======================================= +``CONFIG_SCHED_USER_IDENTITY`` Enable UID/GID tracking +``CONFIG_NSH_LOGIN_SETUID`` Set identity after login +``CONFIG_LIBC_PASSWD_FILE`` User database for name lookup +=============================== ======================================= + +**Example**:: + + nsh> su testuser + nsh$ id + uid=0 euid=1000 gid=0 egid=1000 + nsh$ su root + Password: + nsh# id + uid=0 euid=0 gid=0 egid=0 + .. _cmdinsmod: ``insmod`` Install an OS module @@ -1663,6 +1707,75 @@ NOTE: The ``shutdown`` command duplicates the behavior of the **Synopsis**. Pause execution (sleep) for ```` seconds. +.. _cmdsu: + +``su`` Switch User Identity +=========================== + +**Command Syntax**:: + + su [] + +**Synopsis**. Switch the NSH session to the credentials of ````. +If no user name is provided, ``su`` defaults to ``root``. + +Users with root privileges (effective UID or GID of zero) may switch to +any user without a password. Other users may switch to their own +identity without a password, or to another user after entering that +user's password (when login support is enabled). + +When the real UID is still zero, NSH changes only the effective UID and +GID so that a later ``su root`` can restore root privileges after +password verification. + +**Prompt update.** After a successful ``su``, NSH calls +``nsh_update_prompt()`` and changes the privilege marker in the prompt: + +=================== ================================================ +Marker Session +=================== ================================================ +``#`` Effective UID is zero (root) +``$`` Effective UID is non-zero (non-root) +=================== ================================================ + +For the default prompt ``nsh>``, the marker replaces the character +before ``>`` (for example ``nsh$`` or ``nsh#``). + +This command is available only when ``CONFIG_SCHED_USER_IDENTITY`` is +enabled. It may be disabled with ``CONFIG_NSH_DISABLE_SU``. User names +are looked up from the passwd database when ``CONFIG_LIBC_PASSWD_FILE`` +is enabled. Password verification requires one of the NSH login options +(``CONFIG_NSH_LOGIN_PASSWD``, ``CONFIG_NSH_LOGIN_PLATFORM``, or +``CONFIG_NSH_LOGIN_FIXED``). + +**Related configuration** + +=============================== ======================================= +Option Purpose +=============================== ======================================= +``CONFIG_SCHED_USER_IDENTITY`` Enable UID/GID identity commands +``CONFIG_LIBC_PASSWD_FILE`` Resolve user names from ``/etc/passwd`` +``CONFIG_NSH_LOGIN_SETUID`` Apply identity after login +``CONFIG_NSH_DISABLE_SU`` Disable the ``su`` command +=============================== ======================================= + +**Example**:: + + nsh> su testuser + nsh$ whoami + testuser + nsh$ su newuser + Password: + nsh$ whoami + newuser + nsh$ su root + Password: + nsh# whoami + root + nsh# su testuser + nsh$ whoami + testuser + .. _cmdtelnetd: ``telnetd`` Time Start the Telnet Daemon @@ -1933,6 +2046,37 @@ directory. unless is provided. =================== ================================================= +.. _cmdwhoami: + +``whoami`` Show Effective User Name +=================================== + +**Command Syntax**:: + + whoami + +**Synopsis**. Print the user name associated with the effective UID of +the current NSH session. If the name cannot be resolved from the passwd +database, ``whoami`` prints ``root`` when the effective UID is zero, or +the numeric UID otherwise. + +The result should match the privilege marker shown in the NSH prompt +(``#`` for root, ``$`` for non-root) when +``CONFIG_SCHED_USER_IDENTITY`` is enabled. + +This command is available only when ``CONFIG_SCHED_USER_IDENTITY`` is +enabled. It may be disabled with ``CONFIG_NSH_DISABLE_WHOAMI``. + +**Example**:: + + nsh> su testuser + nsh$ whoami + testuser + nsh$ su root + Password: + nsh# whoami + root + .. _cmdxd: ``xd`` Hexadecimal Dump of Memory diff --git a/Documentation/applications/nsh/login.rst b/Documentation/applications/nsh/login.rst index d433b874855..b499a0ff4b4 100644 --- a/Documentation/applications/nsh/login.rst +++ b/Documentation/applications/nsh/login.rst @@ -25,6 +25,58 @@ login, the user will have access to the NSH session:: NuttShell (NSH) nsh> +When ``CONFIG_NSH_LOGIN_SETUID`` is enabled (the default when +``CONFIG_SCHED_USER_IDENTITY`` is selected), NSH looks up the +authenticated user name in the passwd database and sets the session +identity after a successful login. See also ```id`` <#cmdid>`__, +```su`` <#cmdsu>`__, and ```whoami`` <#cmdwhoami>`__. + +Session Identity and Prompt +=========================== + +When ``CONFIG_SCHED_USER_IDENTITY`` is enabled, NSH tracks the calling +task's real and effective UID/GID for the shell session. File +permission checks use the **effective** identity. + +**Prompt markers.** After login or a successful ``su``, NSH updates the +command prompt to show the effective privilege level of the session: + +=================== ================================================ +Prompt marker Meaning +=================== ================================================ +``#`` Effective UID is zero (root session) +``$`` Effective UID is non-zero (non-root session) +=================== ================================================ + +The marker replaces the character before the closing ``>`` in the +default prompt (for example, ``nsh>`` becomes ``nsh#`` or ``nsh$``), or +is appended when the configured prompt does not end with ``>``. The +prompt is refreshed by ``nsh_update_prompt()`` after ``su`` and after +login when ``CONFIG_NSH_LOGIN_SETUID`` is enabled. + +**Flat builds.** NSH may retain a real UID of zero while only the +effective UID/GID are changed. In that case ``id`` can report +``uid=0 euid=1000`` after logging in as a normal user. Permission +checks and the prompt marker follow the effective identity. + +**Example**:: + + login: testuser + password: + User Logged-in! + + NuttShell (NSH) + nsh$ id + uid=0 euid=1000 gid=0 egid=1000 + nsh$ whoami + testuser + nsh$ su root + Password: + nsh# id + uid=0 euid=0 gid=0 egid=0 + nsh# whoami + root + After each failed login attempt, a delay can be set up. The purpose of this delay is to discourage attempts to crack the password by brute force. That delay is configured with:: From e17d776357f3c982edd8ec64311fc1906df78d3a Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Wed, 17 Jun 2026 13:42:23 -0400 Subject: [PATCH 114/268] docs/guides/customboards: Mention special Kconfig settings This change mentions the special Kconfig settings for custom boards to tell the build system about properties that are defined using the `HAVE` options for in-tree boards. It also specifically mentions to avoid using Kconfig `if` guards around the custom board Kconfig, which would be a gotcha for people copying from in-tree boards. Signed-off-by: Matteo Golin fix --- Documentation/guides/customboards.rst | 41 +++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/Documentation/guides/customboards.rst b/Documentation/guides/customboards.rst index b8624426a5e..76c3b3afb48 100644 --- a/Documentation/guides/customboards.rst +++ b/Documentation/guides/customboards.rst @@ -96,3 +96,44 @@ They should be set to suit your board name and directory location. .. Note:: If you subsequently run a ``make distclean`` operation, then these settings will be lost. They should be added back before building, and/or before running ``make menuconfig``. + +Kconfig flags +------------- + +Some boards make using of Kconfig ``ARCH_HAVE_*`` flags in order to be able to +select certain features. For example, ``ARCH_HAVE_LEDS`` is a necessary flag for +enabling ``CONFIG_ARCH_LEDS=y`` because it tells the build system that the board +has LEDs. Selecting ``ARCH_HAVE_*`` flags happens inside the NuttX build +system, so it is not accessible to custom boards. If you need to enable these +flags, then you should select them manually with the ``BOARD_CUSTOM_*`` options: + +* ``BOARD_CUSTOM_LEDS`` selects ``ARCH_HAVE_LEDS`` +* ``BOARD_CUSTOM_BUTTONS`` selects ``ARCH_HAVE_BUTTONS`` +* ``BOARD_CUSTOM_IRQBUTTONS`` selects ``ARCH_HAVE_IRQBUTTONS`` +* ``BOARD_CUSTOM_INTERRUPT`` selects ``ARCH_PHY_INTERRUPT`` + +If there are any other ``ARCH_HAVE_*`` selectors you cannot access but need for +your custom board, please open an issue! + +Kconfig file +------------ + +You may have noticed that in-tree boards typically surround their board-level +Kconfig logic with something like: + +.. code:: kconfig + + if ARCH_BOARD_BOARDNAME + endif # ARCH_BOARD_BOARDAME + +You should **not** do this for custom boards; just write your Kconfig logic +without the guard. However, it is still good practice to prefix your custom +Kconfig options with the board name: + +.. code:: kconfig + + config BOARDNAME_MYOPTION + bool "My custom option" + default n + ---help--- + This is my custom option for my custom board. From a8f55fbfd8ee4729da5bd253d6a9bc42bdb8e6bd Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Thu, 18 Jun 2026 01:15:48 +0800 Subject: [PATCH 115/268] drivers/clk: use uintptr_t for register addresses Change the 'reg' field type from uint32_t to uintptr_t in all clock provider structs (clk_gate_s, clk_divider_s, clk_phase_s, clk_fractional_divider_s, clk_multiplier_s, clk_mux_s) and their corresponding clk_register_*() function prototypes. Also update clk_write() and clk_read() inline functions to take uintptr_t parameter and remove the now-redundant (uintptr_t) cast. On 32-bit embedded platforms uintptr_t equals uint32_t so there is no functional change. On 64-bit targets (e.g. sim) this fixes -Wint-to-pointer-cast warnings that GCC15 promotes to errors. Fixes: #16896 Signed-off-by: hanzhijian --- drivers/clk/clk.h | 8 ++++---- include/nuttx/clk/clk_provider.h | 24 ++++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/clk/clk.h b/drivers/clk/clk.h index 320ed1e39c4..dd82ddcf5d1 100644 --- a/drivers/clk/clk.h +++ b/drivers/clk/clk.h @@ -49,14 +49,14 @@ * Inline Functions ****************************************************************************/ -static inline void clk_write(uint32_t reg, uint32_t value) +static inline void clk_write(uintptr_t reg, uint32_t value) { - *((volatile uint32_t *)(uintptr_t)reg) = value; + *((volatile uint32_t *)reg) = value; } -static inline uint32_t clk_read(uint32_t reg) +static inline uint32_t clk_read(uintptr_t reg) { - return *((volatile uint32_t *)(uintptr_t)reg); + return *((volatile uint32_t *)reg); } static inline bool clk_is_best_rate_closest(uint32_t rate, uint32_t now, diff --git a/include/nuttx/clk/clk_provider.h b/include/nuttx/clk/clk_provider.h index c64b174d4d4..a18e8fd09ea 100644 --- a/include/nuttx/clk/clk_provider.h +++ b/include/nuttx/clk/clk_provider.h @@ -134,7 +134,7 @@ struct clk_ops_s struct clk_gate_s { - uint32_t reg; + uintptr_t reg; uint8_t bit_idx; uint8_t flags; }; @@ -153,7 +153,7 @@ struct clk_fixed_factor_s struct clk_divider_s { - uint32_t reg; + uintptr_t reg; uint8_t shift; uint8_t width; uint16_t flags; @@ -161,7 +161,7 @@ struct clk_divider_s struct clk_phase_s { - uint32_t reg; + uintptr_t reg; uint8_t shift; uint8_t width; uint8_t flags; @@ -169,7 +169,7 @@ struct clk_phase_s struct clk_fractional_divider_s { - uint32_t reg; + uintptr_t reg; uint8_t mwidth; uint8_t nwidth; uint8_t mshift; @@ -179,7 +179,7 @@ struct clk_fractional_divider_s struct clk_multiplier_s { - uint32_t reg; + uintptr_t reg; uint8_t shift; uint8_t width; uint8_t flags; @@ -187,7 +187,7 @@ struct clk_multiplier_s struct clk_mux_s { - uint32_t reg; + uintptr_t reg; uint8_t width; uint8_t shift; uint8_t flags; @@ -205,7 +205,7 @@ FAR struct clk_s *clk_register(FAR const char *name, FAR struct clk_s *clk_register_gate(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t bit_idx, uint8_t clk_gate_flags); @@ -221,34 +221,34 @@ FAR struct clk_s *clk_register_fixed_factor(FAR const char *name, FAR struct clk_s *clk_register_divider(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint16_t clk_divider_flags); FAR struct clk_s *clk_register_phase(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_phase_flags); FAR struct clk_s * clk_register_fractional_divider(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t mshift, uint8_t mwidth, uint8_t nshift, uint8_t nwidth, uint8_t clk_divider_flags); FAR struct clk_s *clk_register_multiplier(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_multiplier_flags); FAR struct clk_s *clk_register_mux(FAR const char *name, FAR const char * const *parent_names, uint8_t num_parents, uint8_t flags, - uint32_t reg, uint8_t shift, + uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_mux_flags); #ifdef CONFIG_CLK_RPMSG From 8857d3673f0de6733596726733da9b7f0f6ff56b Mon Sep 17 00:00:00 2001 From: hanzhijian Date: Thu, 18 Jun 2026 09:39:05 +0800 Subject: [PATCH 116/268] drivers/clk: fix conflicting types in clk_register_* definitions Update the function definitions in all 6 clk implementation files to match the uintptr_t parameter type already declared in clk_provider.h. Fixes CI error: error: conflicting types for 'clk_register_divider' Signed-off-by: hanzhijian --- drivers/clk/clk_divider.c | 2 +- drivers/clk/clk_fractional_divider.c | 2 +- drivers/clk/clk_gate.c | 2 +- drivers/clk/clk_multiplier.c | 2 +- drivers/clk/clk_mux.c | 2 +- drivers/clk/clk_phase.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/clk_divider.c b/drivers/clk/clk_divider.c index ab22125e94b..78aca2c0dc6 100644 --- a/drivers/clk/clk_divider.c +++ b/drivers/clk/clk_divider.c @@ -363,7 +363,7 @@ const struct clk_ops_s g_clk_divider_ops = FAR struct clk_s *clk_register_divider(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint16_t clk_divider_flags) { diff --git a/drivers/clk/clk_fractional_divider.c b/drivers/clk/clk_fractional_divider.c index 784123da707..06101928f1e 100644 --- a/drivers/clk/clk_fractional_divider.c +++ b/drivers/clk/clk_fractional_divider.c @@ -159,7 +159,7 @@ const struct clk_ops_s g_clk_fractional_divider_ops = FAR struct clk_s * clk_register_fractional_divider(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t mshift, uint8_t mwidth, uint8_t nshift, uint8_t nwidth, uint8_t clk_divider_flags) diff --git a/drivers/clk/clk_gate.c b/drivers/clk/clk_gate.c index f7a78d849e6..eaedba088f5 100644 --- a/drivers/clk/clk_gate.c +++ b/drivers/clk/clk_gate.c @@ -119,7 +119,7 @@ const struct clk_ops_s g_clk_gate_ops = FAR struct clk_s *clk_register_gate(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t bit_idx, uint8_t clk_gate_flags) { diff --git a/drivers/clk/clk_multiplier.c b/drivers/clk/clk_multiplier.c index f86492ae840..6df9cf9096c 100644 --- a/drivers/clk/clk_multiplier.c +++ b/drivers/clk/clk_multiplier.c @@ -227,7 +227,7 @@ const struct clk_ops_s g_clk_multiplier_ops = FAR struct clk_s *clk_register_multiplier(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_multiplier_flags) diff --git a/drivers/clk/clk_mux.c b/drivers/clk/clk_mux.c index d982b6da8d2..e6fe865e3db 100644 --- a/drivers/clk/clk_mux.c +++ b/drivers/clk/clk_mux.c @@ -177,7 +177,7 @@ const struct clk_ops_s g_clk_mux_ro_ops = FAR struct clk_s *clk_register_mux(FAR const char *name, FAR const char * const *parent_names, uint8_t num_parents, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_mux_flags) { diff --git a/drivers/clk/clk_phase.c b/drivers/clk/clk_phase.c index 8a96d745336..9e995aac45c 100644 --- a/drivers/clk/clk_phase.c +++ b/drivers/clk/clk_phase.c @@ -92,7 +92,7 @@ const struct clk_ops_s g_clk_phase_ops = FAR struct clk_s *clk_register_phase(FAR const char *name, FAR const char *parent_name, - uint8_t flags, uint32_t reg, + uint8_t flags, uintptr_t reg, uint8_t shift, uint8_t width, uint8_t clk_phase_flags) { From b941a715ea392d1764f87e0e3c391f33c4250126 Mon Sep 17 00:00:00 2001 From: Michael Rogov Papernov Date: Sun, 12 Apr 2026 14:20:56 +0100 Subject: [PATCH 117/268] ci/testing: Add MemBrowse Integration Tracking memory footprint with MemBrowse Signed-off-by: Michael Rogov Papernov / michael@membrowse.com --- .github/membrowse-targets.json | 83 +++++++++ .github/workflows/membrowse-comment.yml | 42 +++++ .github/workflows/membrowse-onboard.yml | 98 ++++++++++ .github/workflows/membrowse-report.yml | 232 ++++++++++++++++++++++++ README.md | 1 + 5 files changed, 456 insertions(+) create mode 100644 .github/membrowse-targets.json create mode 100644 .github/workflows/membrowse-comment.yml create mode 100644 .github/workflows/membrowse-onboard.yml create mode 100644 .github/workflows/membrowse-report.yml diff --git a/.github/membrowse-targets.json b/.github/membrowse-targets.json new file mode 100644 index 00000000000..f0a227f4dbb --- /dev/null +++ b/.github/membrowse-targets.json @@ -0,0 +1,83 @@ +[ + { + "target_name": "stm32-nucleo-f103rb", + "board_config": "nucleo-f103rb:nsh", + "elf": "nuttx", + "ld": "boards/arm/stm32/nucleo-f103rb/scripts/ld.script", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "arduino-mega2560", + "board_config": "arduino-mega2560:nsh", + "elf": "nuttx.elf", + "ld": "boards/avr/atmega/arduino-mega2560/scripts/flash.ld", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "qemu-armv8a", + "board_config": "qemu-armv8a:nsh", + "elf": "nuttx", + "ld": "", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "mirtoo", + "board_config": "mirtoo:nsh", + "elf": "nuttx", + "ld": "boards/mips/pic32mx/mirtoo/scripts/pinguino-debug.ld", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "-d MIPS32_TOOLCHAIN_GNU_ELF -e MIPS32_TOOLCHAIN_PINGUINOL" + }, + { + "target_name": "hifive1-revb", + "board_config": "hifive1-revb:nsh", + "elf": "nuttx", + "ld": "boards/risc-v/fe310/hifive1-revb/scripts/ld.script", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "rx65n-rsk2mb", + "board_config": "rx65n-rsk2mb:nsh", + "elf": "nuttx", + "ld": "boards/renesas/rx65n/rx65n-rsk2mb/scripts/linker_script.ld", + "map_file": "", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "s698pm-dkit", + "board_config": "s698pm-dkit:nsh", + "elf": "nuttx", + "ld": "", + "map_file": "", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "qemu-intel64", + "board_config": "qemu-intel64:nsh", + "elf": "nuttx", + "ld": "", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + }, + { + "target_name": "esp32-devkitc", + "board_config": "esp32-devkitc:nsh", + "elf": "nuttx", + "ld": "boards/xtensa/esp32/common/scripts/flat_memory.ld.tmp boards/xtensa/esp32/common/scripts/esp32_sections.ld.tmp", + "map_file": "nuttx.map", + "linker_vars": "", + "config_overrides": "" + } +] diff --git a/.github/workflows/membrowse-comment.yml b/.github/workflows/membrowse-comment.yml new file mode 100644 index 00000000000..05a578a533c --- /dev/null +++ b/.github/workflows/membrowse-comment.yml @@ -0,0 +1,42 @@ +name: MemBrowse PR Comment + +on: + workflow_run: + workflows: [MemBrowse Memory Report] + types: + - completed + +jobs: + comment: + runs-on: ubuntu-latest + if: > + github.event.workflow_run.event == 'pull_request' && + github.event.workflow_run.conclusion != 'cancelled' + permissions: + contents: read + pull-requests: write + steps: + - name: Checkout repository + uses: actions/checkout@v5 + + - uses: actions/setup-python@v6 + with: + python-version: '3.11' + + - name: Install membrowse + run: pip install --no-cache-dir membrowse + + - name: Post combined PR comment + if: ${{ env.MEMBROWSE_API_KEY != '' }} + env: + MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} + MEMBROWSE_API_URL: ${{ vars.MEMBROWSE_API_URL }} + GH_TOKEN: ${{ secrets.GITHUB_TOKEN }} + HEAD_SHA: ${{ github.event.workflow_run.head_sha }} + run: | + SUMMARY_ARGS=("$HEAD_SHA" --api-key "$MEMBROWSE_API_KEY" --json) + if [ -n "$MEMBROWSE_API_URL" ]; then + SUMMARY_ARGS+=(--api-url "$MEMBROWSE_API_URL") + fi + membrowse summary "${SUMMARY_ARGS[@]}" > /tmp/membrowse-summary.json + python -m membrowse.utils.github_comment --summary-json /tmp/membrowse-summary.json diff --git a/.github/workflows/membrowse-onboard.yml b/.github/workflows/membrowse-onboard.yml new file mode 100644 index 00000000000..3ae7af7c421 --- /dev/null +++ b/.github/workflows/membrowse-onboard.yml @@ -0,0 +1,98 @@ +name: Onboard to MemBrowse + +on: + workflow_dispatch: + inputs: + num_commits: + description: 'Number of commits to process' + required: true + default: '100' + type: string + +jobs: + load-targets: + runs-on: ubuntu-latest + outputs: + matrix: ${{ steps.set-matrix.outputs.matrix }} + steps: + - uses: actions/checkout@v6 + - id: set-matrix + run: echo "matrix=$(jq -c '.' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT + + onboard: + needs: load-targets + runs-on: ubuntu-latest + container: + image: ghcr.io/apache/nuttx/apache-nuttx-ci-linux + credentials: + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + strategy: + fail-fast: false + matrix: + include: ${{ fromJson(needs.load-targets.outputs.matrix) }} + + steps: + - name: Checkout nuttx + uses: actions/checkout@v6 + with: + fetch-depth: 0 + + - name: Clone nuttx-apps + run: | + git config --global --add safe.directory '*' + git clone --depth=1 https://github.com/apache/nuttx-apps.git ../apps + + - name: Install membrowse + run: python3 -m pip install --no-cache-dir membrowse + + - name: Fetch full git history + run: | + git fetch --unshallow || true + git fetch --all + + - name: Run MemBrowse Onboard + env: + MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} + MEMBROWSE_API_URL: ${{ vars.MEMBROWSE_API_URL }} + NUM_COMMITS: ${{ github.event.inputs.num_commits }} + TARGET_NAME: ${{ matrix.target_name }} + ELF: ${{ matrix.elf }} + LD: ${{ matrix.ld }} + MAP_FILE: ${{ matrix.map_file }} + LINKER_VARS: ${{ matrix.linker_vars }} + run: | + BUILD_SCRIPT=$(cat <<'BUILD_EOF' + ./tools/configure.sh -l ${{ matrix.board_config }} + echo CONFIG_DEBUG_SYMBOLS=y >> .config + echo CONFIG_DEBUG_LINK_MAP=y >> .config + if [ -n "${{ matrix.config_overrides }}" ]; then + kconfig-tweak ${{ matrix.config_overrides }} + fi + make olddefconfig + find arch -name Makefile -exec sed -i '/DELFILE, $(addsuffix .tmp,$(ARCHSCRIPT))/d' {} + + trap 'git checkout -- arch/' EXIT + make -j$(nproc) + BUILD_EOF + ) + + ARGS=("$NUM_COMMITS" "$BUILD_SCRIPT" "$ELF" "$TARGET_NAME" "$MEMBROWSE_API_KEY") + if [ -n "$MEMBROWSE_API_URL" ]; then + ARGS+=(--api-url "$MEMBROWSE_API_URL") + fi + if [ -n "$LD" ]; then + ARGS+=(--ld-scripts "$LD") + fi + if [ -n "$LINKER_VARS" ]; then + set -f + for var in $LINKER_VARS; do + ARGS+=(--def "$var") + done + set +f + fi + if [ -n "$MAP_FILE" ]; then + ARGS+=(--map-file "$MAP_FILE") + fi + ARGS+=(--binary-search) + + membrowse onboard "${ARGS[@]}" diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml new file mode 100644 index 00000000000..04e61f57541 --- /dev/null +++ b/.github/workflows/membrowse-report.yml @@ -0,0 +1,232 @@ +name: MemBrowse Memory Report + +on: + pull_request: + push: + branches: + - master + - "releases/*" + +permissions: + contents: read + +concurrency: + group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} + cancel-in-progress: ${{ github.event_name == 'pull_request' }} + +jobs: + # Detect whether any source files (i.e. non-doc/CODEOWNERS) changed. + # When only docs/CODEOWNERS change we skip the build and post an "identical" + # MemBrowse report instead. + changes-filter: + runs-on: ubuntu-latest + outputs: + source: ${{ steps.filter.outputs.source }} + steps: + # Shallow checkout; the base commit needed for the diff is fetched + # explicitly below instead of cloning the repo's full history. + - uses: actions/checkout@v6 + with: + fetch-depth: 2 + # Detect whether any non-doc/CODEOWNERS source files changed. + # Implemented with plain git instead of a third-party paths-filter + # action, since Apache's GitHub Actions allowlist forbids actions that + # aren't GitHub-created or explicitly permitted. + - id: filter + env: + BASE_SHA: ${{ github.event_name == 'pull_request' && github.event.pull_request.base.sha || github.event.before }} + HEAD_SHA: ${{ github.event_name == 'pull_request' && github.event.pull_request.head.sha || github.sha }} + run: | + # On the very first push to a branch, github.event.before is all-zeros. + if [ -z "$BASE_SHA" ] || [ "$BASE_SHA" = "0000000000000000000000000000000000000000" ]; then + echo "source=true" >> "$GITHUB_OUTPUT" + echo "No usable base SHA; treating as source change." + exit 0 + fi + # The shallow checkout may not contain BASE_SHA (multi-commit pushes, + # long-lived PR branches). Fetch just that commit; fall back to a full + # unshallow only if the targeted fetch fails. + if ! git cat-file -e "$BASE_SHA^{commit}" 2>/dev/null; then + git fetch --depth=1 origin "$BASE_SHA" 2>/dev/null \ + || git fetch --unshallow origin 2>/dev/null \ + || git fetch --unshallow 2>/dev/null || true + fi + changed=$(git diff --name-only "$BASE_SHA" "$HEAD_SHA") + echo "Changed files:" + echo "$changed" + # Drop paths that should NOT count as source changes; if anything + # survives, real source changed. + source=$(echo "$changed" | grep -vE \ + -e '^AUTHORS$' \ + -e '^CONTRIBUTING\.md$' \ + -e '(^|/)CODEOWNERS$' \ + -e '^Documentation/' \ + -e '^tools/ci/docker/linux/' \ + -e '^tools/codeowners/[^/]+$' \ + || true) + if [ -n "$source" ]; then + echo "source=true" >> "$GITHUB_OUTPUT" + else + echo "source=false" >> "$GITHUB_OUTPUT" + fi + + load-targets: + runs-on: ubuntu-latest + outputs: + matrix: ${{ steps.set-matrix.outputs.matrix }} + steps: + - uses: actions/checkout@v6 + - id: set-matrix + run: echo "matrix=$(jq -c '.' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT + + # Post an "identical" MemBrowse report when only docs/CODEOWNERS changed. + # Only runs on push events (master/releases/tags) to keep the baseline + # complete; PR events don't produce identical markers. + identical: + needs: [changes-filter, load-targets] + if: needs.changes-filter.outputs.source == 'false' && github.event_name == 'push' + runs-on: ubuntu-latest + strategy: + fail-fast: false + matrix: + include: ${{ fromJson(needs.load-targets.outputs.matrix) }} + steps: + - uses: actions/checkout@v6 + with: + fetch-depth: 2 + - uses: actions/setup-python@v6 + with: + python-version: '3.11' + - name: Install membrowse + run: pip install --no-cache-dir membrowse + - name: Upload identical - ${{ matrix.target_name }} + env: + MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} + MEMBROWSE_API_URL: ${{ vars.MEMBROWSE_API_URL }} + TARGET_NAME: ${{ matrix.target_name }} + run: | + ARGS=(--upload --github + --target-name "$TARGET_NAME" + --api-key "$MEMBROWSE_API_KEY" + --identical) + if [ -n "$MEMBROWSE_API_URL" ]; then + ARGS+=(--api-url "$MEMBROWSE_API_URL") + fi + membrowse report "${ARGS[@]}" + + # Build target with debug symbols + linker map, then upload MemBrowse report. + # Uses the NuttX CI Docker image so toolchains, kconfig-frontends, etc. are + # already installed. + analyze: + needs: [changes-filter, load-targets] + if: needs.changes-filter.outputs.source == 'true' + runs-on: ubuntu-latest + env: + DOCKER_BUILDKIT: 1 + strategy: + fail-fast: false + matrix: + include: ${{ fromJson(needs.load-targets.outputs.matrix) }} + steps: + - name: Checkout nuttx repo + uses: actions/checkout@v6 + with: + path: sources/nuttx + fetch-depth: 2 + + - name: Checkout nuttx-apps repo + uses: actions/checkout@v6 + with: + repository: apache/nuttx-apps + path: sources/apps + fetch-depth: 1 + + - name: Docker Login + uses: docker/login-action@b45d80f862d83dbcd57f89517bcf500b2ab88fb2 # v4.0.0 + with: + registry: ghcr.io + username: ${{ github.actor }} + password: ${{ secrets.GITHUB_TOKEN }} + + - name: Docker Pull + run: docker pull ghcr.io/apache/nuttx/apache-nuttx-ci-linux + + - name: Build ${{ matrix.target_name }} + uses: ./sources/nuttx/.github/actions/ci-container + with: + run: | + git config --global --add safe.directory /github/workspace/sources/nuttx + git config --global --add safe.directory /github/workspace/sources/apps + cd /github/workspace/sources/nuttx + ./tools/configure.sh -l ${{ matrix.board_config }} + echo CONFIG_DEBUG_SYMBOLS=y >> .config + echo CONFIG_DEBUG_LINK_MAP=y >> .config + if [ -n "${{ matrix.config_overrides }}" ]; then + kconfig-tweak ${{ matrix.config_overrides }} + fi + make olddefconfig + # Preserve preprocessed linker scripts (.ld.tmp) so MemBrowse can + # read them. Arch Makefiles delete these immediately after linking. + find arch -name Makefile -exec sed -i '/DELFILE, $(addsuffix .tmp,$(ARCHSCRIPT))/d' {} + + make -j$(nproc) + + # MemBrowse action runs from $GITHUB_WORKSPACE and discovers git via CWD, + # but nuttx is checked out to sources/nuttx/ (so apps can sit beside it). + # Expose the repo's .git at the workspace root so git metadata resolves. + - name: Expose nuttx .git to workspace root + run: ln -sfn sources/nuttx/.git .git + + - name: Prefix linker script paths + id: ld + run: | + prefixed="" + for p in ${{ matrix.ld }}; do + prefixed="$prefixed sources/nuttx/$p" + done + paths=$(echo $prefixed | xargs) + echo "paths=$paths" >> "$GITHUB_OUTPUT" + echo "Resolved ld paths: [$paths]" + for p in $paths; do + if [ -e "$p" ]; then + echo " OK $p ($(stat -c '%s bytes, owner=%U:%G' "$p" 2>/dev/null))" + else + echo " MISS $p" + echo " ls dir:" + ls -la "$(dirname "$p")" 2>&1 | head -30 + fi + done + + - uses: actions/setup-python@v6 + with: + python-version: '3.11' + - name: Install membrowse + run: pip install --no-cache-dir membrowse + - name: MemBrowse analysis - ${{ matrix.target_name }} + env: + MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} + MEMBROWSE_API_URL: ${{ vars.MEMBROWSE_API_URL }} + TARGET_NAME: ${{ matrix.target_name }} + ELF: sources/nuttx/${{ matrix.elf }} + LD_PATHS: ${{ steps.ld.outputs.paths }} + MAP_FILE: ${{ matrix.map_file != '' && format('sources/nuttx/{0}', matrix.map_file) || '' }} + LINKER_VARS: ${{ matrix.linker_vars }} + run: | + set -o pipefail + ARGS=("$ELF" "$LD_PATHS" + --upload --github + --target-name "$TARGET_NAME" + --api-key "$MEMBROWSE_API_KEY") + if [ -n "$MEMBROWSE_API_URL" ]; then + ARGS+=(--api-url "$MEMBROWSE_API_URL") + fi + if [ -n "$MAP_FILE" ]; then + ARGS+=(--map-file "$MAP_FILE") + fi + if [ -n "$LINKER_VARS" ]; then + set -f + for var in $LINKER_VARS; do + ARGS+=(--def "$var") + done + set +f + fi + membrowse --verbose INFO report "${ARGS[@]}" diff --git a/README.md b/README.md index 3ec5eba255e..40d6c07114e 100644 --- a/README.md +++ b/README.md @@ -8,6 +8,7 @@ [![Contributors](https://img.shields.io/github/contributors/apache/nuttx)](https://github.com/apache/nuttx/graphs/contributors) [![GitHub Build Badge](https://github.com/apache/nuttx/workflows/Build/badge.svg)](https://github.com/apache/nuttx/actions/workflows/build.yml) [![Documentation Badge](https://github.com/apache/nuttx/workflows/Build%20Documentation/badge.svg)](https://nuttx.apache.org/docs/latest/index.html) +[![MemBrowse](https://membrowse.com/badge.svg)](https://membrowse.com/public/apache/nuttx) Apache NuttX is a real-time operating system (RTOS) with an emphasis on standards compliance and small footprint. Scalable from 8-bit to 64-bit From 57eed4d904c03cb221ab6d2d3ca1d4528bf4f105 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Wed, 17 Jun 2026 22:34:55 +0000 Subject: [PATCH 118/268] build(deps): bump starlette from 1.0.1 to 1.3.1 in /Documentation Bumps [starlette](https://github.com/Kludex/starlette) from 1.0.1 to 1.3.1. - [Release notes](https://github.com/Kludex/starlette/releases) - [Changelog](https://github.com/Kludex/starlette/blob/main/docs/release-notes.md) - [Commits](https://github.com/Kludex/starlette/compare/1.0.1...1.3.1) --- updated-dependencies: - dependency-name: starlette dependency-version: 1.3.1 dependency-type: indirect ... Signed-off-by: dependabot[bot] --- Documentation/Pipfile.lock | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/Pipfile.lock b/Documentation/Pipfile.lock index d4441b7c2a0..95848a7a7a3 100644 --- a/Documentation/Pipfile.lock +++ b/Documentation/Pipfile.lock @@ -24,11 +24,11 @@ }, "anyio": { "hashes": [ - "sha256:08b310f9e24a9594186fd75b4f73f4a4152069e3853f1ed8bfbf58369f4ad708", - "sha256:334b70e641fd2221c1505b3890c69882fe4a2df910cba14d97019b90b24439dc" + "sha256:b47c1f9ccf73e67021df785332508f99379c68fa7d0684e8e3492cb1d4b23f89", + "sha256:dd9b7a2a9799ed6552fde617b2c5df02b7fdd7d88392fc48101e51bae46164d9" ], "markers": "python_version >= '3.10'", - "version": "==4.13.0" + "version": "==4.14.0" }, "babel": { "hashes": [ @@ -633,12 +633,12 @@ }, "starlette": { "hashes": [ - "sha256:512399c5f1de7fac99c88572212ded9ddeddef2fb32afa82d724000e88b38f4f", - "sha256:7c0e69b2ee1c848bd54669d908500117a3ee13de603a21427e5c6fc1adf98dcd" + "sha256:05d0213193f2fbaae60e2ecb593b4add4262ad4e46536b54abe36f11a71724e0", + "sha256:c7372aae11c3c3f26a42df7bd626cec2f47d03483d261d369516a615a53714c6" ], "index": "pypi", "markers": "python_version >= '3.10'", - "version": "==1.0.1" + "version": "==1.3.1" }, "urllib3": { "hashes": [ From 3804e3d82ec3384699aa153ae90d4ed36d00735d Mon Sep 17 00:00:00 2001 From: Michael Rogov Papernov Date: Thu, 18 Jun 2026 21:11:01 +0100 Subject: [PATCH 119/268] Documentation/testing: Document MemBrowse integration Add a Memory Footprint Tracking section with a dashboard screenshot. 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P73tkH`nBYS{gZzK=w$4Q literal 0 HcmV?d00001 diff --git a/Documentation/testing/nuttx-ci.rst b/Documentation/testing/nuttx-ci.rst index e4b40dac943..b238bd57043 100644 --- a/Documentation/testing/nuttx-ci.rst +++ b/Documentation/testing/nuttx-ci.rst @@ -41,6 +41,8 @@ When a PR is opened, the following CI actions take place: * Build tests are performed based on which files were modified * Some CI runtime tests are performed on simulators/emulators through :doc:`/testing/ntfc`. +* Memory footprint of a set of representative targets is tracked using + `MemBrowse `_ (see `Memory Footprint Tracking`_). Pull Request Labelling ====================== @@ -148,3 +150,25 @@ resulting ``nuttx.bin``, ``nuttx.elf``, ``nuttx.hex``, etc., binaries. You should be able to download the artifact, flash the NuttX image(s) to your target device and test them that way if you'd like to avoid building all of the images yourself! + +Memory Footprint Tracking +========================= + +Dashboard: ``_ + +The memory footprint of a set of representative targets is tracked over time +using `MemBrowse `_. This makes flash/RAM usage changes +visible on a per-section and per-symbol basis and helps catch unintended size +regressions. It: + +* provides a trend graph of the builds across commits +* lets you compare the footprint between any two uploaded commits +* posts a footprint summary comment on each pull request + +.. image:: image/membrowse-targets.png + :alt: MemBrowse targets page showing the current memory usage of each tracked NuttX target + +The integration consists of: + +* the set of tracked targets, configured in ``.github/membrowse-targets.json`` +* the ``membrowse-*.yml`` workflows under ``.github/workflows/`` that drive it From 92d83aaf5ed60380783d72c7670fe91826603f1e Mon Sep 17 00:00:00 2001 From: leisiji <2265215145@qq.com> Date: Wed, 17 Jun 2026 11:41:01 +0800 Subject: [PATCH 120/268] arch/arm/armv7-a: Fix L1 page table entry double-offset in addrenv create region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In arm_addrenv_create_region(), the inner loop already advances vaddr by MM_PGSIZE for each mapped page, so after filling one L2 page table (i.e., ENTRIES_PER_L2TABLE pages), vaddr has naturally advanced to the start of the next 1MB section. The old code additionally added i * SECTION_SIZE, causing the L1 entry for the second and subsequent sections to skip one section each iteration—leaving virtual address holes in the mapping. Remove the redundant i * SECTION_SIZE offset so that the L1 entry tracks the vaddr already maintained by the inner loop, producing contiguous section mappings. Signed-off-by: leisiji <2265215145@qq.com> --- arch/arm/src/armv7-a/arm_addrenv_utils.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/src/armv7-a/arm_addrenv_utils.c b/arch/arm/src/armv7-a/arm_addrenv_utils.c index 02fed5d5bc4..6a9f1ea0dd4 100644 --- a/arch/arm/src/armv7-a/arm_addrenv_utils.c +++ b/arch/arm/src/armv7-a/arm_addrenv_utils.c @@ -107,8 +107,7 @@ int arm_addrenv_create_region(uintptr_t *l1table, unsigned int listlen, DEBUGASSERT(MM_ISALIGNED(paddr)); - mmu_l1table_setentry(l1table, paddr, vaddr + i * SECTION_SIZE, - MMU_L1_PGTABFLAGS); + mmu_l1table_setentry(l1table, paddr, vaddr, MMU_L1_PGTABFLAGS); /* Get the virtual address corresponding to the physical page address */ From 111f3fff4fb56ccfa20eb2a234a97b7deabce255 Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Wed, 17 Jun 2026 13:05:07 +0000 Subject: [PATCH 121/268] fs/inode: Add shared permission helpers and pseudoFS open checks Add fs_checkmode() and fs_checkopenperm() for reuse across filesystems. Enforce pseudoFS mode bits in inode_checkperm() and allow world-readable open of passwd/group entries so getpwnam() works after seteuid(). Signed-off-by: Abhishek Mishra --- fs/inode/fs_inode.c | 177 +++++++++++++++++++++++--------------------- fs/inode/inode.h | 42 ++++++----- fs/vfs/fs_mkdir.c | 2 +- fs/vfs/fs_open.c | 2 +- fs/vfs/fs_rename.c | 4 +- fs/vfs/fs_unlink.c | 2 +- 6 files changed, 121 insertions(+), 108 deletions(-) diff --git a/fs/inode/fs_inode.c b/fs/inode/fs_inode.c index 2505fbc2e3e..bb04ea0d65b 100644 --- a/fs/inode/fs_inode.c +++ b/fs/inode/fs_inode.c @@ -53,57 +53,46 @@ static rw_semaphore_t g_inode_lock = RWSEM_INITIALIZER; * Private Functions ****************************************************************************/ +#ifdef CONFIG_FS_PERMISSION /**************************************************************************** - * Name: _inode_checkmode + * Name: fs_checkmode * * Description: - * Test effective credentials against 'inode' for 'amode' access. - * Kernel threads always pass. - * - * Returned Value: - * Zero (OK) or -EACCES. + * Test the calling task's effective credentials against the owner, group, + * and mode of a file or directory. Kernel threads always pass. * ****************************************************************************/ -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) -static int _inode_checkmode(FAR struct inode *inode, int amode) +int fs_checkmode(uid_t owner, gid_t group, mode_t mode, int amode) { FAR struct tcb_s *rtcb; mode_t perm; uid_t uid; gid_t gid; - /* Kernel threads are always granted access */ - rtcb = nxsched_self(); if ((rtcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) { return OK; } - /* Use effective credentials */ - DEBUGASSERT(rtcb->group != NULL); uid = rtcb->group->tg_euid; gid = rtcb->group->tg_egid; - /* Select the applicable permission-bit triplet */ - - if (uid == inode->i_owner) + if (uid == owner) { - perm = (inode->i_mode >> 6) & 7; + perm = (mode >> 6) & 7; } - else if (gid == inode->i_group) + else if (gid == group) { - perm = (inode->i_mode >> 3) & 7; + perm = (mode >> 3) & 7; } else { - perm = inode->i_mode & 7; + perm = mode & 7; } - /* Every requested bit must be present in the selected triplet */ - if ((amode & perm) != amode) { return -EACCES; @@ -111,7 +100,45 @@ static int _inode_checkmode(FAR struct inode *inode, int amode) return OK; } -#endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ + +/**************************************************************************** + * Name: fs_open_amode + * + * Description: + * Map open flags to a permission access mode bitmask. + * + ****************************************************************************/ + +int fs_open_amode(int oflags) +{ + int amode = 0; + + if ((oflags & O_RDOK) != 0) + { + amode |= R_OK; + } + + if ((oflags & O_WROK) != 0) + { + amode |= W_OK; + } + + return amode; +} + +/**************************************************************************** + * Name: fs_checkopenperm + * + * Description: + * Test open access for the calling task against owner, group, and mode. + * + ****************************************************************************/ + +int fs_checkopenperm(uid_t owner, gid_t group, mode_t mode, int oflags) +{ + return fs_checkmode(owner, group, mode, fs_open_amode(oflags)); +} +#endif /* CONFIG_FS_PERMISSION */ /**************************************************************************** * Public Functions @@ -189,6 +216,43 @@ void inode_runlock(void) * Name: inode_checkperm * * Description: + * Check 'inode' for 'amode' access on pseudo-filesystem inodes. + * NULL 'inode' (root) and mountpoints are exempt. + * + * Input Parameters: + * inode - Inode to check, or NULL for a root-level path + * amode - Access mode bitmask (R_OK / W_OK / X_OK) + * + * Returned Value: + * Zero (OK) on success, or -EACCES if permission is denied. + * + ****************************************************************************/ + +int inode_checkperm(FAR struct inode *inode, int amode) +{ +#ifdef CONFIG_FS_PERMISSION + + if (inode == NULL) + { + return OK; + } + + if (INODE_IS_MOUNTPT(inode)) + { + return OK; + } + + return fs_checkmode(inode->i_owner, inode->i_group, inode->i_mode, amode); + +#else + return OK; +#endif /* CONFIG_FS_PERMISSION */ +} + +/**************************************************************************** + * Name: inode_checkopenperm + * + * Description: * Validate open access to 'inode' for 'oflags'. Checks driver operation * support, then pseudo-filesystem mode bits when enabled. Mountpoints * are exempt from mode checks. @@ -202,29 +266,14 @@ void inode_runlock(void) * ****************************************************************************/ -int inode_checkperm(FAR struct inode *inode, int oflags) +int inode_checkopenperm(FAR struct inode *inode, int oflags) { -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - int amode = 0; -#endif FAR const struct file_operations *ops; -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - if ((oflags & O_RDOK) != 0) - { - amode |= R_OK; - } - - if ((oflags & O_WROK) != 0) - { - amode |= W_OK; - } -#endif - if (INODE_IS_PSEUDODIR(inode)) { -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - return _inode_checkmode(inode, amode); +#ifdef CONFIG_FS_PERMISSION + return inode_checkperm(inode, fs_open_amode(oflags)); #else return OK; #endif @@ -244,53 +293,11 @@ int inode_checkperm(FAR struct inode *inode, int oflags) return -EACCES; } -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) +#ifdef CONFIG_FS_PERMISSION - if (INODE_IS_MOUNTPT(inode)) - { - return OK; - } - - return _inode_checkmode(inode, amode); - -#endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ - - return OK; -} - -/**************************************************************************** - * Name: inode_checkdirperm - * - * Description: - * Check parent directory 'dir' for 'amode' access on pseudo-filesystem - * inodes. NULL 'dir' (root) and mountpoints are exempt. - * - * Input Parameters: - * dir - Parent directory inode, or NULL for a root-level path - * amode - Access mode bitmask (R_OK / W_OK / X_OK) - * - * Returned Value: - * Zero (OK) on success, or -EACCES if permission is denied. - * - ****************************************************************************/ - -int inode_checkdirperm(FAR struct inode *dir, int amode) -{ -#if defined(CONFIG_PSEUDOFS_ATTRIBUTES) && defined(CONFIG_SCHED_USER_IDENTITY) - - if (dir == NULL) - { - return OK; - } - - if (INODE_IS_MOUNTPT(dir)) - { - return OK; - } - - return _inode_checkmode(dir, amode); + return inode_checkperm(inode, fs_open_amode(oflags)); #else return OK; -#endif /* CONFIG_PSEUDOFS_ATTRIBUTES && CONFIG_SCHED_USER_IDENTITY */ +#endif /* CONFIG_FS_PERMISSION */ } diff --git a/fs/inode/inode.h b/fs/inode/inode.h index 3735d9a566c..7cacd0697f3 100644 --- a/fs/inode/inode.h +++ b/fs/inode/inode.h @@ -422,6 +422,24 @@ void inode_release(FAR struct inode *inode); * Name: inode_checkperm * * Description: + * Check 'inode' for 'amode' access on pseudo-filesystem inodes. + * NULL 'inode' (root) and mountpoints are exempt. + * + * Input Parameters: + * inode - Inode to check, or NULL for a root-level path + * amode - Access mode bitmask (R_OK / W_OK / X_OK) + * + * Returned Value: + * Zero (OK) on success, or -EACCES if permission is denied. + * + ****************************************************************************/ + +int inode_checkperm(FAR struct inode *inode, int amode); + +/**************************************************************************** + * Name: inode_checkopenperm + * + * Description: * Validate open access to 'inode' for 'oflags'. Checks driver operation * support, then pseudo-filesystem mode bits when enabled. Mountpoints * are exempt from mode checks. @@ -435,25 +453,13 @@ void inode_release(FAR struct inode *inode); * ****************************************************************************/ -int inode_checkperm(FAR struct inode *inode, int oflags); +int inode_checkopenperm(FAR struct inode *inode, int oflags); -/**************************************************************************** - * Name: inode_checkdirperm - * - * Description: - * Check parent directory 'dir' for 'amode' access on pseudo-filesystem - * inodes. NULL 'dir' (root) and mountpoints are exempt. - * - * Input Parameters: - * dir - Parent directory inode, or NULL for a root-level path - * amode - Access mode bitmask (R_OK / W_OK / X_OK) - * - * Returned Value: - * Zero (OK) on success, or -EACCES if permission is denied. - * - ****************************************************************************/ - -int inode_checkdirperm(FAR struct inode *dir, int amode); +#ifdef CONFIG_FS_PERMISSION +int fs_checkmode(uid_t owner, gid_t group, mode_t mode, int amode); +int fs_open_amode(int oflags); +int fs_checkopenperm(uid_t owner, gid_t group, mode_t mode, int oflags); +#endif /**************************************************************************** * Name: foreach_inode diff --git a/fs/vfs/fs_mkdir.c b/fs/vfs/fs_mkdir.c index bfd66a25834..65b0fdb1f1b 100644 --- a/fs/vfs/fs_mkdir.c +++ b/fs/vfs/fs_mkdir.c @@ -142,7 +142,7 @@ int mkdir(const char *pathname, mode_t mode) * both W_OK and X_OK to create a directory entry. */ - ret = inode_checkdirperm(desc.parent, W_OK | X_OK); + ret = inode_checkperm(desc.parent, W_OK | X_OK); if (ret < 0) { errcode = -ret; diff --git a/fs/vfs/fs_open.c b/fs/vfs/fs_open.c index 4131d14b36e..d1944bc184c 100644 --- a/fs/vfs/fs_open.c +++ b/fs/vfs/fs_open.c @@ -172,7 +172,7 @@ static int file_vopen(FAR struct file *filep, FAR const char *path, /* Validate operation support and pseudo-filesystem permissions */ - ret = inode_checkperm(inode, oflags); + ret = inode_checkopenperm(inode, oflags); if (ret < 0) { goto errout_with_inode; diff --git a/fs/vfs/fs_rename.c b/fs/vfs/fs_rename.c index 11ea28a3b3f..8d9840aeb4a 100644 --- a/fs/vfs/fs_rename.c +++ b/fs/vfs/fs_rename.c @@ -86,7 +86,7 @@ static int pseudorename(FAR const char *oldpath, FAR struct inode *oldinode, /* Verify source parent write permission. */ - ret = inode_checkdirperm(oldparent, W_OK); + ret = inode_checkperm(oldparent, W_OK); if (ret < 0) { goto errout; @@ -177,7 +177,7 @@ static int pseudorename(FAR const char *oldpath, FAR struct inode *oldinode, inode_find(&pardesc); /* pardesc.parent valid even if node not found */ parnode = pardesc.node; - ret = inode_checkdirperm(pardesc.parent, W_OK); + ret = inode_checkperm(pardesc.parent, W_OK); /* inode_find() holds a reference on parnode; RELEASE_SEARCH() only * frees pardesc.buffer. diff --git a/fs/vfs/fs_unlink.c b/fs/vfs/fs_unlink.c index a8c70f66b86..7f4d3ffaadf 100644 --- a/fs/vfs/fs_unlink.c +++ b/fs/vfs/fs_unlink.c @@ -123,7 +123,7 @@ int nx_unlink(FAR const char *pathname) /* Verify parent-directory write permission before unlink. */ - ret = inode_checkdirperm(desc.parent, W_OK); + ret = inode_checkperm(desc.parent, W_OK); if (ret < 0) { goto errout_with_inode; From 33f5cf9525fc23b3cf2e4a7872c39aedd460f0db Mon Sep 17 00:00:00 2001 From: Alan Carvalho de Assis Date: Sat, 20 Jun 2026 11:43:23 -0300 Subject: [PATCH 122/268] ci/test: Remove FTDI from CI to avoid failure Even after installing the ftdi library on CI it doesn't work to compile the sim:ft2232h_gpio, so remove it from CI test. Signed-off-by: Alan C. Assis --- tools/ci/testlist/sim-02.dat | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/ci/testlist/sim-02.dat b/tools/ci/testlist/sim-02.dat index 56e85274ea1..552af99592a 100644 --- a/tools/ci/testlist/sim-02.dat +++ b/tools/ci/testlist/sim-02.dat @@ -1,6 +1,9 @@ /sim/*/*/*/c[j-z]* /sim/*/*/*/[d-n]* +# FTDI lib doesn't work on CI +-sim:ft2232h_gpio + # cURL error 60 SSL certificate expired -sim:cxxtest From 0e662be70ae1ae49c13ca2b969b795cf7dceac00 Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Wed, 17 Jun 2026 16:47:08 +0000 Subject: [PATCH 123/268] fs/tmpfs: Add user identity and permission enforcement Store uid/gid/mode on tmpfs objects, support chstat, enforce open and path permissions via fs_checkmode()/fs_checkopenperm(), and inherit creator identity on file creation. Signed-off-by: Abhishek Mishra --- fs/tmpfs/fs_tmpfs.c | 339 ++++++++++++++++++++++++++++++++++++++++---- fs/tmpfs/fs_tmpfs.h | 17 +++ 2 files changed, 326 insertions(+), 30 deletions(-) diff --git a/fs/tmpfs/fs_tmpfs.c b/fs/tmpfs/fs_tmpfs.c index 99b01d04f26..80e2e04e5b6 100644 --- a/fs/tmpfs/fs_tmpfs.c +++ b/fs/tmpfs/fs_tmpfs.c @@ -106,13 +106,15 @@ static int tmpfs_remove_dirent(FAR struct tmpfs_directory_s *tdo, static int tmpfs_add_dirent(FAR struct tmpfs_directory_s *tdo, FAR struct tmpfs_object_s *to, FAR const char *name); static FAR struct tmpfs_file_s * -tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent); +tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent, mode_t mode); static int tmpfs_create_file(FAR struct tmpfs_s *fs, - FAR const char *relpath, FAR struct tmpfs_file_s **tfo); + FAR const char *relpath, mode_t mode, + FAR struct tmpfs_file_s **tfo); static FAR struct tmpfs_directory_s * -tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent); +tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent, mode_t mode); static int tmpfs_create_directory(FAR struct tmpfs_s *fs, - FAR const char *relpath, FAR struct tmpfs_directory_s **tdo); + FAR const char *relpath, mode_t mode, + FAR struct tmpfs_directory_s **tdo); static int tmpfs_find_object(FAR struct tmpfs_s *fs, FAR const char *relpath, size_t len, FAR struct tmpfs_object_s **object, @@ -146,6 +148,8 @@ static int tmpfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static int tmpfs_sync(FAR struct file *filep); static int tmpfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int tmpfs_fstat(FAR const struct file *filep, FAR struct stat *buf); +static int tmpfs_fchstat(FAR const struct file *filep, + FAR const struct stat *buf, int flags); static int tmpfs_truncate(FAR struct file *filep, off_t length); static int tmpfs_mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map); @@ -174,6 +178,8 @@ static void tmpfs_stat_common(FAR struct tmpfs_object_s *to, FAR struct stat *buf); static int tmpfs_stat(FAR struct inode *mountpt, FAR const char *relpath, FAR struct stat *buf); +static int tmpfs_chstat(FAR struct inode *mountpt, FAR const char *relpath, + FAR const struct stat *buf, int flags); /**************************************************************************** * Public Data @@ -196,7 +202,7 @@ const struct mountpt_operations g_tmpfs_operations = tmpfs_sync, /* sync */ tmpfs_dup, /* dup */ tmpfs_fstat, /* fstat */ - NULL, /* fchstat */ + tmpfs_fchstat, /* fchstat */ tmpfs_opendir, /* opendir */ tmpfs_closedir, /* closedir */ @@ -212,7 +218,7 @@ const struct mountpt_operations g_tmpfs_operations = tmpfs_rmdir, /* rmdir */ tmpfs_rename, /* rename */ tmpfs_stat, /* stat */ - NULL /* chstat */ + tmpfs_chstat /* chstat */ }; /**************************************************************************** @@ -555,12 +561,162 @@ static int tmpfs_add_dirent(FAR struct tmpfs_directory_s *tdo, return OK; } +#ifdef CONFIG_FS_PERMISSION + +/**************************************************************************** + * Name: tmpfs_init_object + ****************************************************************************/ + +static void tmpfs_init_object(FAR struct tmpfs_object_s *to, mode_t mode) +{ + FAR struct tcb_s *rtcb; + + to->to_mode = mode & 07777; + rtcb = nxsched_self(); + if ((rtcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL || + rtcb->group == NULL) + { + to->to_uid = 0; + to->to_gid = 0; + } + else + { + to->to_uid = rtcb->group->tg_euid; + to->to_gid = rtcb->group->tg_egid; + } +} + +/**************************************************************************** + * Name: tmpfs_check_pathperm + ****************************************************************************/ + +static int tmpfs_check_pathperm(FAR struct tmpfs_s *fs, + FAR const char *relpath, size_t relpathlen, + int final_amode) +{ + FAR struct tmpfs_directory_s *tdo; + FAR struct tmpfs_object_s *to; + size_t begin = 0; + size_t end; + int ret; + + while (begin < relpathlen && relpath[begin] == '/') + { + begin++; + } + + if (begin >= relpathlen) + { + to = fs->tfs_root.tde_object; + return fs_checkmode(to->to_uid, to->to_gid, + to->to_mode | S_IFDIR, final_amode); + } + + for (end = begin; end <= relpathlen; end++) + { + if (end < relpathlen && relpath[end] != '/') + { + continue; + } + + ret = tmpfs_find_directory(fs, relpath, end, &tdo, NULL); + if (ret < 0) + { + return ret; + } + + to = (FAR struct tmpfs_object_s *)tdo; + ret = fs_checkmode(to->to_uid, to->to_gid, + to->to_mode | S_IFDIR, + end >= relpathlen ? final_amode : X_OK); + tdo->tdo_refs--; + tmpfs_unlock_directory(tdo); + if (ret < 0) + { + return ret; + } + } + + return OK; +} + +/**************************************************************************** + * Name: tmpfs_check_parentperm + ****************************************************************************/ + +static int tmpfs_check_parentperm(FAR struct tmpfs_s *fs, + FAR const char *relpath, int amode) +{ + FAR const char *slash; + FAR struct tmpfs_object_s *to; + size_t parentlen; + + slash = strrchr(relpath, '/'); + if (slash == NULL || slash == relpath) + { + to = fs->tfs_root.tde_object; + return fs_checkmode(to->to_uid, to->to_gid, + to->to_mode | S_IFDIR, amode); + } + + parentlen = slash - relpath; + return tmpfs_check_pathperm(fs, relpath, parentlen, amode); +} + +/**************************************************************************** + * Name: tmpfs_chstat_object + ****************************************************************************/ + +static int tmpfs_chstat_object(FAR struct tmpfs_object_s *to, + FAR const struct stat *buf, int flags) +{ + FAR struct tcb_s *rtcb; + uid_t euid; + + rtcb = nxsched_self(); + if ((rtcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL && + rtcb->group != NULL) + { + euid = rtcb->group->tg_euid; + + if ((flags & (CH_STAT_UID | CH_STAT_GID)) != 0 && euid != 0) + { + return -EPERM; + } + + if ((flags & CH_STAT_MODE) != 0 && + euid != 0 && euid != to->to_uid) + { + return -EPERM; + } + } + + if ((flags & CH_STAT_MODE) != 0) + { + to->to_mode = buf->st_mode & 07777; + } + + if ((flags & CH_STAT_UID) != 0) + { + to->to_uid = buf->st_uid; + } + + if ((flags & CH_STAT_GID) != 0) + { + to->to_gid = buf->st_gid; + } + + return OK; +} + +#endif /* CONFIG_FS_PERMISSION */ + /**************************************************************************** * Name: tmpfs_alloc_file ****************************************************************************/ static FAR struct tmpfs_file_s * -tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent) +tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent, mode_t mode) { FAR struct tmpfs_file_s *tfo; @@ -584,6 +740,12 @@ tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent) tfo->tfo_size = 0; tfo->tfo_data = NULL; +#ifdef CONFIG_FS_PERMISSION + tmpfs_init_object((FAR struct tmpfs_object_s *)tfo, mode); +#else + UNUSED(mode); +#endif + nxrmutex_init(&tfo->tfo_lock); tmpfs_lock_file(tfo); @@ -595,7 +757,7 @@ tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent) ****************************************************************************/ static int tmpfs_create_file(FAR struct tmpfs_s *fs, - FAR const char *relpath, + FAR const char *relpath, mode_t mode, FAR struct tmpfs_file_s **tfo) { FAR struct tmpfs_directory_s *parent; @@ -670,7 +832,7 @@ static int tmpfs_create_file(FAR struct tmpfs_s *fs, * one reference count. */ - newtfo = tmpfs_alloc_file(parent); + newtfo = tmpfs_alloc_file(parent, mode); if (newtfo == NULL) { ret = -ENOMEM; @@ -712,7 +874,7 @@ errout_with_parent: ****************************************************************************/ static FAR struct tmpfs_directory_s * -tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent) +tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent, mode_t mode) { FAR struct tmpfs_directory_s *tdo; @@ -733,6 +895,12 @@ tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent) tdo->tdo_nentries = 0; tdo->tdo_entry = NULL; +#ifdef CONFIG_FS_PERMISSION + tmpfs_init_object((FAR struct tmpfs_object_s *)tdo, mode); +#else + UNUSED(mode); +#endif + nxrmutex_init(&tdo->tdo_lock); return tdo; @@ -743,7 +911,7 @@ tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent) ****************************************************************************/ static int tmpfs_create_directory(FAR struct tmpfs_s *fs, - FAR const char *relpath, + FAR const char *relpath, mode_t mode, FAR struct tmpfs_directory_s **tdo) { FAR struct tmpfs_directory_s *parent; @@ -817,7 +985,7 @@ static int tmpfs_create_directory(FAR struct tmpfs_s *fs, * the new directory and the object is not locked. */ - newtdo = tmpfs_alloc_directory(parent); + newtdo = tmpfs_alloc_directory(parent, mode); if (newtdo == NULL) { ret = -ENOMEM; @@ -1369,6 +1537,9 @@ static int tmpfs_open(FAR struct file *filep, FAR const char *relpath, FAR struct inode *inode; FAR struct tmpfs_s *fs; FAR struct tmpfs_file_s *tfo; +#ifdef CONFIG_FS_PERMISSION + FAR struct tmpfs_object_s *to; +#endif off_t offset; int ret; @@ -1392,10 +1563,6 @@ static int tmpfs_open(FAR struct file *filep, FAR const char *relpath, return ret; } - /* Skip over any leading directory separators (shouldn't be any) */ - - for (; *relpath == '/'; relpath++); - /* Find the file object associated with this relative path. * If successful, this action will lock both the parent directory and * the file object, adding one to the reference count of both. @@ -1420,9 +1587,23 @@ static int tmpfs_open(FAR struct file *filep, FAR const char *relpath, goto errout_with_filelock; } - /* Check if the caller has sufficient privileges to open the file. - * REVISIT: No file protection implemented - */ + /* Check if the caller has sufficient privileges to open the file. */ + +#ifdef CONFIG_FS_PERMISSION + to = (FAR struct tmpfs_object_s *)tfo; + ret = tmpfs_check_parentperm(fs, relpath, X_OK); + if (ret < 0) + { + goto errout_with_filelock; + } + + ret = fs_checkopenperm(to->to_uid, to->to_gid, + to->to_mode | S_IFREG, oflags); + if (ret < 0) + { + goto errout_with_filelock; + } +#endif /* If O_TRUNC is specified and the file is opened for writing, * then truncate the file. This operation requires that the file is @@ -1467,7 +1648,15 @@ static int tmpfs_open(FAR struct file *filep, FAR const char *relpath, * on the new file object. */ - ret = tmpfs_create_file(fs, relpath, &tfo); +#ifdef CONFIG_FS_PERMISSION + ret = tmpfs_check_parentperm(fs, relpath, W_OK | X_OK); + if (ret < 0) + { + goto errout_with_fslock; + } +#endif + + ret = tmpfs_create_file(fs, relpath, mode, &tfo); if (ret < 0) { goto errout_with_fslock; @@ -1936,6 +2125,36 @@ static int tmpfs_fstat(FAR const struct file *filep, FAR struct stat *buf) return OK; } +/**************************************************************************** + * Name: tmpfs_fchstat + ****************************************************************************/ + +static int tmpfs_fchstat(FAR const struct file *filep, + FAR const struct stat *buf, int flags) +{ + DEBUGASSERT(filep->f_priv != NULL && buf != NULL); + +#ifdef CONFIG_FS_PERMISSION + FAR struct tmpfs_file_s *tfo; + int ret; + + tfo = filep->f_priv; + + ret = tmpfs_lock_file(tfo); + if (ret < 0) + { + return ret; + } + + ret = tmpfs_chstat_object((FAR struct tmpfs_object_s *)tfo, buf, flags); + tmpfs_unlock_file(tfo); + return ret; +#else + UNUSED(flags); + return -ENOSYS; +#endif +} + /**************************************************************************** * Name: tmpfs_truncate ****************************************************************************/ @@ -2031,10 +2250,6 @@ static int tmpfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, return ret; } - /* Skip over any leading directory separators (shouldn't be any) */ - - for (; *relpath == '/'; relpath++); - /* Find the directory object associated with this relative path. * If successful, this action will lock both the parent directory and * the file object, adding one to the reference count of both. @@ -2045,10 +2260,21 @@ static int tmpfs_opendir(FAR struct inode *mountpt, FAR const char *relpath, ret = tmpfs_find_directory(fs, relpath, strlen(relpath), &tdo, NULL); if (ret >= 0) { - tdir->tf_tdo = tdo; - tdir->tf_index = tdo->tdo_nentries; - *dir = &tdir->tf_base; - tmpfs_unlock_directory(tdo); +#ifdef CONFIG_FS_PERMISSION + ret = tmpfs_check_pathperm(fs, relpath, strlen(relpath), R_OK | X_OK); + if (ret < 0) + { + tdo->tdo_refs--; + tmpfs_unlock_directory(tdo); + } + else +#endif + { + tdir->tf_tdo = tdo; + tdir->tf_index = tdo->tdo_nentries; + *dir = &tdir->tf_base; + tmpfs_unlock_directory(tdo); + } } /* Release the lock on the file system and return the result */ @@ -2212,7 +2438,7 @@ static int tmpfs_bind(FAR struct inode *blkdriver, FAR const void *data, * the file system structure. */ - tdo = tmpfs_alloc_directory(NULL); + tdo = tmpfs_alloc_directory(NULL, 0777); if (tdo == NULL) { fs_heap_free(fs); @@ -2481,7 +2707,7 @@ static int tmpfs_mkdir(FAR struct inode *mountpt, FAR const char *relpath, /* Create the directory. */ - ret = tmpfs_create_directory(fs, relpath, NULL); + ret = tmpfs_create_directory(fs, relpath, mode, NULL); tmpfs_unlock(fs); return ret; } @@ -2768,9 +2994,15 @@ static void tmpfs_stat_common(FAR struct tmpfs_object_s *to, FAR struct tmpfs_file_s *tfo = (FAR struct tmpfs_file_s *)to; +#ifdef CONFIG_FS_PERMISSION + buf->st_mode = (to->to_mode & 07777) | S_IFREG; + buf->st_uid = to->to_uid; + buf->st_gid = to->to_gid; +#else /* -rwxrwxrwx */ buf->st_mode = S_IRWXO | S_IRWXG | S_IRWXU | S_IFREG; +#endif /* Get the size of the object */ @@ -2781,9 +3013,15 @@ static void tmpfs_stat_common(FAR struct tmpfs_object_s *to, FAR struct tmpfs_directory_s *tdo = (FAR struct tmpfs_directory_s *)to; +#ifdef CONFIG_FS_PERMISSION + buf->st_mode = (to->to_mode & 07777) | S_IFDIR; + buf->st_uid = to->to_uid; + buf->st_gid = to->to_gid; +#else /* drwxrwxrwx */ buf->st_mode = S_IRWXO | S_IRWXG | S_IRWXU | S_IFDIR; +#endif /* Get the size of the object */ @@ -2853,6 +3091,47 @@ errout_with_fslock: return ret; } +/**************************************************************************** + * Name: tmpfs_chstat + ****************************************************************************/ + +static int tmpfs_chstat(FAR struct inode *mountpt, FAR const char *relpath, + FAR const struct stat *buf, int flags) +{ + DEBUGASSERT(mountpt != NULL && relpath != NULL && buf != NULL); + +#ifdef CONFIG_FS_PERMISSION + FAR struct tmpfs_s *fs; + FAR struct tmpfs_object_s *to; + int ret; + + fs = mountpt->i_private; + DEBUGASSERT(fs != NULL); + + ret = tmpfs_lock(fs); + if (ret < 0) + { + return ret; + } + + ret = tmpfs_find_object(fs, relpath, strlen(relpath), &to, NULL); + if (ret < 0) + { + goto errout_with_fslock; + } + + ret = tmpfs_chstat_object(to, buf, flags); + tmpfs_release_lockedobject(to); + +errout_with_fslock: + tmpfs_unlock(fs); + return ret; +#else + UNUSED(flags); + return -ENOSYS; +#endif +} + /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/fs/tmpfs/fs_tmpfs.h b/fs/tmpfs/fs_tmpfs.h index 56a726adc99..b04b62628ca 100644 --- a/fs/tmpfs/fs_tmpfs.h +++ b/fs/tmpfs/fs_tmpfs.h @@ -30,6 +30,8 @@ #include #include +#include +#include #include #include @@ -82,6 +84,11 @@ struct tmpfs_object_s uint8_t to_type; /* See enum tmpfs_objtype_e */ uint8_t to_refs; /* Reference count */ FAR struct tmpfs_directory_s *to_parent; +#ifdef CONFIG_FS_PERMISSION + mode_t to_mode; /* File mode (permission bits) */ + uid_t to_uid; /* Owner user ID */ + gid_t to_gid; /* Owner group ID */ +#endif }; /* The form of a directory memory object */ @@ -96,6 +103,11 @@ struct tmpfs_directory_s uint8_t tdo_type; /* See enum tmpfs_objtype_e */ uint8_t tdo_refs; /* Reference count */ FAR struct tmpfs_directory_s *tdo_parent; +#ifdef CONFIG_FS_PERMISSION + mode_t tdo_mode; /* Directory mode (permission bits) */ + uid_t tdo_uid; /* Owner user ID */ + gid_t tdo_gid; /* Owner group ID */ +#endif /* Remaining fields are unique to a directory object */ @@ -123,6 +135,11 @@ struct tmpfs_file_s uint8_t tfo_type; /* See enum tmpfs_objtype_e */ uint8_t tfo_refs; /* Reference count */ FAR struct tmpfs_directory_s *tfo_parent; +#ifdef CONFIG_FS_PERMISSION + mode_t tfo_mode; /* File mode (permission bits) */ + uid_t tfo_uid; /* Owner user ID */ + gid_t tfo_gid; /* Owner group ID */ +#endif /* Remaining fields are unique to a directory object */ From 34dabfc4e7433b25f779698e6c511723453089d8 Mon Sep 17 00:00:00 2001 From: Abhishek Mishra Date: Wed, 17 Jun 2026 16:59:41 +0000 Subject: [PATCH 124/268] fs/littlefs: Enforce open permissions and set create ownership Check open access against file mode and owner via fs_checkmode(), verify parent directory permissions on create, and assign creator uid/gid to newly created files. Signed-off-by: Abhishek Mishra --- .../components/filesystem/littlefs.rst | 30 ++- fs/inode/inode.h | 6 + fs/littlefs/lfs_vfs.c | 231 +++++++++++++++++- 3 files changed, 265 insertions(+), 2 deletions(-) diff --git a/Documentation/components/filesystem/littlefs.rst b/Documentation/components/filesystem/littlefs.rst index 8e07e074818..35c042cc8f7 100644 --- a/Documentation/components/filesystem/littlefs.rst +++ b/Documentation/components/filesystem/littlefs.rst @@ -18,7 +18,7 @@ well as file operations (``fopen()``, ``fclose()``, etc). `_. -..note:: +.. note:: If your littlefs setup is experiencing crashes when you boot, try troubleshooting by tweaking the ``BLOCK_SIZE_FACTOR`` options in Kconfig. A @@ -29,3 +29,31 @@ well as file operations (``fopen()``, ``fclose()``, etc). The littlefs support on NuttX only works with mtd drivers, for storage devices such as flash chips, SD cards and eMMC. Performance on SD cards and eMMC devices is worse than flash. + +User identity and permissions +============================= + +When both ``CONFIG_FS_PERMISSION`` and ``CONFIG_FS_LITTLEFS_ATTR_UPDATE`` are +enabled, littlefs stores owner, group, and mode in per-file custom attributes. +This requires :ref:`user-identity` (``CONFIG_SCHED_USER_IDENTITY``). + +**Metadata.** ``chmod``/``chown`` (via ``chstat``) update the stored mode, +UID, and GID. ``stat`` and ``ls -l`` read them back. + +**Creation.** New files and directories are created with the effective UID and +GID of the creating task. + +**Open checks.** ``open()`` enforces POSIX permission bits using the caller's +effective identity: + +* Existing files: each path component must grant search (``X_OK``) permission; + the final component must grant the access requested by ``oflags``. +* ``O_CREAT`` on a non-existent file: the parent directory must grant write and + search permission. + +**Directory reads.** ``opendir()`` requires read and search permission on the +target directory. + +Files created before permission support was enabled, or without stored +attributes, default to mode ``0777`` until ``chmod``/``chown`` sets explicit +metadata. diff --git a/fs/inode/inode.h b/fs/inode/inode.h index 7cacd0697f3..b8280d91bb5 100644 --- a/fs/inode/inode.h +++ b/fs/inode/inode.h @@ -461,6 +461,12 @@ int fs_open_amode(int oflags); int fs_checkopenperm(uid_t owner, gid_t group, mode_t mode, int oflags); #endif +#ifdef CONFIG_FS_PERMISSION +int fs_checkmode(uid_t owner, gid_t group, mode_t mode, int amode); +int fs_open_amode(int oflags); +int fs_checkopenperm(uid_t owner, gid_t group, mode_t mode, int oflags); +#endif + /**************************************************************************** * Name: foreach_inode * diff --git a/fs/littlefs/lfs_vfs.c b/fs/littlefs/lfs_vfs.c index 1a4208e3364..39825440257 100644 --- a/fs/littlefs/lfs_vfs.c +++ b/fs/littlefs/lfs_vfs.c @@ -30,6 +30,8 @@ #include #include #include +#include +#include #include #include @@ -38,7 +40,6 @@ #include #include -#include #include #include "inode/inode.h" @@ -337,6 +338,193 @@ static FAR const char *littlefs_convert_path(FAR const char *path) return path; } +#if defined(CONFIG_FS_PERMISSION) && defined(CONFIG_FS_LITTLEFS_ATTR_UPDATE) + +/**************************************************************************** + * Name: littlefs_statbuf_locked + ****************************************************************************/ + +static int littlefs_statbuf_locked(FAR struct littlefs_mountpt_s *fs, + FAR const char *relpath, + FAR struct stat *buf) +{ + struct lfs_info info; + struct littlefs_attr_s attr; + int ret; + + memset(buf, 0, sizeof(*buf)); + + ret = lfs_stat(&fs->lfs, relpath, &info); + if (ret < 0) + { + return littlefs_convert_result(ret); + } + + ret = littlefs_convert_result(lfs_getattr(&fs->lfs, relpath, 0, + &attr, sizeof(attr))); + if (ret < 0) + { + if (ret != -ENODATA) + { + return ret; + } + + memset(&attr, 0, sizeof(attr)); + attr.at_mode = S_IRWXG | S_IRWXU | S_IRWXO; + } + + buf->st_mode = attr.at_mode; + buf->st_uid = attr.at_uid; + buf->st_gid = attr.at_gid; + buf->st_atim.tv_sec = attr.at_atim / 1000000000ull; + buf->st_atim.tv_nsec = attr.at_atim % 1000000000ull; + buf->st_mtim.tv_sec = attr.at_mtim / 1000000000ull; + buf->st_mtim.tv_nsec = attr.at_mtim % 1000000000ull; + buf->st_ctim.tv_sec = attr.at_ctim / 1000000000ull; + buf->st_ctim.tv_nsec = attr.at_ctim % 1000000000ull; + buf->st_blksize = fs->cfg.block_size; + + if (info.type == LFS_TYPE_REG) + { + buf->st_mode |= S_IFREG; + buf->st_size = info.size; + } + else + { + buf->st_mode |= S_IFDIR; + buf->st_size = 0; + } + + buf->st_blocks = (buf->st_size + buf->st_blksize - 1) / buf->st_blksize; + return OK; +} + +/**************************************************************************** + * Name: littlefs_check_pathperm_locked + ****************************************************************************/ + +static int littlefs_check_pathperm_locked(FAR struct littlefs_mountpt_s *fs, + FAR const char *relpath, + int final_amode) +{ + struct stat st; + char subpath[PATH_MAX]; + size_t begin = 0; + size_t end; + int ret; + + while (relpath[begin] == '/') + { + begin++; + } + + if (relpath[begin] == '\0') + { + return OK; + } + + for (end = begin; ; end++) + { + if (relpath[end] != '\0' && relpath[end] != '/') + { + continue; + } + + if (relpath[end] == '\0') + { + break; + } + + if (end - begin >= PATH_MAX) + { + return -ENAMETOOLONG; + } + + memcpy(subpath, relpath + begin, end - begin); + subpath[end - begin] = '\0'; + + ret = littlefs_statbuf_locked(fs, subpath, &st); + if (ret < 0) + { + return ret; + } + + ret = fs_checkmode(st.st_uid, st.st_gid, st.st_mode, X_OK); + if (ret < 0) + { + return ret; + } + } + + /* Check permission on the final path component */ + + ret = littlefs_statbuf_locked(fs, &relpath[begin], &st); + if (ret < 0) + { + return ret; + } + + return fs_checkmode(st.st_uid, st.st_gid, st.st_mode, final_amode); +} + +/**************************************************************************** + * Name: littlefs_check_openperm_locked + ****************************************************************************/ + +static int littlefs_check_openperm_locked(FAR struct littlefs_mountpt_s *fs, + FAR const char *relpath, + int oflags) +{ + return littlefs_check_pathperm_locked(fs, relpath, + fs_open_amode(oflags)); +} + +/**************************************************************************** + * Name: littlefs_check_parentperm_locked + ****************************************************************************/ + +static int littlefs_check_parentperm_locked( + FAR struct littlefs_mountpt_s *fs, + FAR const char *relpath, int amode) +{ + FAR const char *slash; + char parent[PATH_MAX + 1]; + struct stat st; + size_t pathlen; + int ret; + + slash = strrchr(relpath, '/'); + if (slash == NULL || slash == relpath) + { + ret = littlefs_statbuf_locked(fs, "/", &st); + if (ret < 0) + { + return ret; + } + + return fs_checkmode(st.st_uid, st.st_gid, st.st_mode, amode); + } + + pathlen = slash - relpath; + if (pathlen > PATH_MAX) + { + return -ENAMETOOLONG; + } + + memcpy(parent, relpath, pathlen); + parent[pathlen] = '\0'; + + ret = littlefs_statbuf_locked(fs, parent, &st); + if (ret < 0) + { + return ret; + } + + return fs_checkmode(st.st_uid, st.st_gid, st.st_mode, amode); +} + +#endif /* CONFIG_FS_PERMISSION && CONFIG_FS_LITTLEFS_ATTR_UPDATE */ + /**************************************************************************** * Name: littlefs_open ****************************************************************************/ @@ -347,6 +535,9 @@ static int littlefs_open(FAR struct file *filep, FAR const char *relpath, FAR struct littlefs_mountpt_s *fs; FAR struct littlefs_file_s *priv; FAR struct inode *inode; +#if defined(CONFIG_FS_PERMISSION) && defined(CONFIG_FS_LITTLEFS_ATTR_UPDATE) + struct lfs_info info; +#endif int ret; /* Get the mountpoint inode reference from the file structure and the @@ -377,6 +568,27 @@ static int littlefs_open(FAR struct file *filep, FAR const char *relpath, /* Try to open the file */ relpath = littlefs_convert_path(relpath); + +#if defined(CONFIG_FS_PERMISSION) && defined(CONFIG_FS_LITTLEFS_ATTR_UPDATE) + ret = lfs_stat(&fs->lfs, relpath, &info); + if (ret == 0) + { + ret = littlefs_check_openperm_locked(fs, relpath, oflags); + if (ret < 0) + { + goto errout; + } + } + else if (ret == LFS_ERR_NOENT && (oflags & O_CREAT) != 0) + { + ret = littlefs_check_parentperm_locked(fs, relpath, W_OK | X_OK); + if (ret < 0) + { + goto errout; + } + } +#endif + oflags = littlefs_convert_oflags(oflags); if (fs->readonly) { @@ -405,6 +617,10 @@ static int littlefs_open(FAR struct file *filep, FAR const char *relpath, clock_gettime(CLOCK_REALTIME, &time); memset(&attr, 0, sizeof(attr)); attr.at_mode = mode; +#ifdef CONFIG_FS_PERMISSION + attr.at_uid = geteuid(); + attr.at_gid = getegid(); +#endif attr.at_ctim = 1000000000ull * time.tv_sec + time.tv_nsec; attr.at_atim = attr.at_ctim; attr.at_mtim = attr.at_ctim; @@ -1019,6 +1235,15 @@ static int littlefs_opendir(FAR struct inode *mountpt, /* Call the LFS's opendir function */ relpath = littlefs_convert_path(relpath); + +#if defined(CONFIG_FS_PERMISSION) && defined(CONFIG_FS_LITTLEFS_ATTR_UPDATE) + ret = littlefs_check_pathperm_locked(fs, relpath, R_OK | X_OK); + if (ret < 0) + { + goto errout; + } +#endif + ret = littlefs_convert_result(lfs_dir_open(&fs->lfs, &ldir->dir, relpath)); if (ret < 0) { @@ -1740,6 +1965,10 @@ static int littlefs_mkdir(FAR struct inode *mountpt, FAR const char *relpath, clock_gettime(CLOCK_REALTIME, &time); memset(&attr, 0, sizeof(attr)); attr.at_mode = mode; +#ifdef CONFIG_FS_PERMISSION + attr.at_uid = geteuid(); + attr.at_gid = getegid(); +#endif attr.at_ctim = 1000000000ull * time.tv_sec + time.tv_nsec; attr.at_atim = attr.at_ctim; attr.at_mtim = attr.at_ctim; From c9caf2c5dcc034bb44f7f9a8a13cd061602dafb6 Mon Sep 17 00:00:00 2001 From: Sammy Tran Date: Fri, 19 Jun 2026 16:42:21 -0400 Subject: [PATCH 125/268] stm32h5/qspi: add QSPIMEM_QUADDATA flag for 1-1-4 transfers Add QSPIMEM_QUADDATA to the QSPI memory flags. This flag selects quad data width while keeping the address phase on a single line (1-1-4), which QSPIMEM_QUADIO cannot express (it forces quad on both address and data phases). Update stm32_qspi_memory() to honour the new flag by setting CCR_DMODE_QUAD without touching the address mode. Signed-off-by: Sammy Tran --- arch/arm/src/stm32h5/stm32_qspi.c | 9 ++++++++- include/nuttx/spi/qspi.h | 2 ++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/src/stm32h5/stm32_qspi.c b/arch/arm/src/stm32h5/stm32_qspi.c index fa0448187bd..208feef2bad 100644 --- a/arch/arm/src/stm32h5/stm32_qspi.c +++ b/arch/arm/src/stm32h5/stm32_qspi.c @@ -921,8 +921,15 @@ static int qspi_setupxctnfrommem(struct qspi_xctnspec_s *xctn, { xctn->datamode = CCR_DMODE_DUAL; } - else if (QSPIMEM_ISQUADIO(meminfo->flags)) + else if (QSPIMEM_ISQUADIO(meminfo->flags) || + QSPIMEM_ISQUADDATA(meminfo->flags)) { + /* QUADDATA selects quad data width while leaving the address phase + * single-line (1-1-4), which QUADIO cannot express. The address-mode + * block above intentionally ignores QUADDATA, so addrmode stays + * single. + */ + xctn->datamode = CCR_DMODE_QUAD; } else diff --git a/include/nuttx/spi/qspi.h b/include/nuttx/spi/qspi.h index eecce3bbc6c..77d8bdfcbe6 100644 --- a/include/nuttx/spi/qspi.h +++ b/include/nuttx/spi/qspi.h @@ -216,11 +216,13 @@ #define QSPIMEM_RANDOM (1 << 6) /* Bit 6: Use random key in scrambler */ #define QSPIMEM_IDUAL (1 << 7) /* Bit 7: Instruction on two lines */ #define QSPIMEM_IQUAD (1 << 0) /* Bit 0: Instruction on four lines */ +#define QSPIMEM_QUADDATA (1 << 1) /* Bit 1: Quad data, single-line addr */ #define QSPIMEM_ISREAD(f) (((f) & QSPIMEM_WRITE) == 0) #define QSPIMEM_ISWRITE(f) (((f) & QSPIMEM_WRITE) != 0) #define QSPIMEM_ISDUALIO(f) (((f) & QSPIMEM_DUALIO) != 0) #define QSPIMEM_ISQUADIO(f) (((f) & QSPIMEM_QUADIO) != 0) +#define QSPIMEM_ISQUADDATA(f) (((f) & QSPIMEM_QUADDATA) != 0) #define QSPIMEM_ISSCRAMBLE(f) (((f) & QSPIMEM_SCRAMBLE) != 0) #define QSPIMEM_ISIDUAL(f) (((f) & QSPIMEM_IDUAL) != 0) #define QSPIMEM_ISIQUAD(f) (((f) & QSPIMEM_IQUAD) != 0) From 2a7cf05a20820711f0e7f05e17858306b40a4fcb Mon Sep 17 00:00:00 2001 From: Sammy Tran Date: Fri, 19 Jun 2026 16:42:25 -0400 Subject: [PATCH 126/268] drivers/mtd/gd25: add QSPI support Add QSPI mode to the GD25 MTD driver alongside the existing SPI path. When CONFIG_GD25_QSPI is selected, sector erase, chip erase, byte read, page write, and byte write all use the QSPI command/memory interfaces instead of SPI. Reads use the quad I/O fast-read command (1-4-4) and writes use the quad page-program command (1-1-4) via QSPIMEM_QUADDATA. A new Kconfig option enables the QE bit in SR2 at initialisation so the quad I/O pins are active. Signed-off-by: Sammy Tran --- drivers/mtd/Kconfig | 24 ++- drivers/mtd/gd25.c | 452 ++++++++++++++++++++++++++++++++++------ include/nuttx/mtd/mtd.h | 5 + 3 files changed, 416 insertions(+), 65 deletions(-) diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index b30e4f64fc6..f7ff6462984 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -1393,19 +1393,39 @@ config W25_DEBUG endif # MTD_W25 config MTD_GD25 - bool "SPI-based GD25 FLASH" + bool "SPI/QuadSPI-based GigaDevice GD25 FLASH" default n - select SPI if MTD_GD25 +config GD25_QSPI + bool "Use QuadSPI interface for GD25" + default n + select QSPI + ---help--- + Enable to use the QuadSPI (QSPI) interface instead of SPI. + When enabled, gd25_initialize() accepts a qspi_dev_s pointer + and bool unprotect. When disabled (default), SPI is used. + config GD25_SPIMODE int "GD25 SPI Mode" default 0 + depends on !GD25_QSPI config GD25_SPIFREQUENCY int "GD25 SPI Frequency" default 20000000 + depends on !GD25_QSPI + +config GD25_QSPIMODE + int "GD25 QuadSPI Mode" + default 0 + depends on GD25_QSPI + +config GD25_QSPIFREQUENCY + int "GD25 QuadSPI Frequency" + default 20000000 + depends on GD25_QSPI config GD25_READONLY bool "GD25 Read-Only FLASH" diff --git a/drivers/mtd/gd25.c b/drivers/mtd/gd25.c index a97a6bcd4a2..b449f481dab 100644 --- a/drivers/mtd/gd25.c +++ b/drivers/mtd/gd25.c @@ -41,7 +41,11 @@ #include #include #include -#include +#ifdef CONFIG_GD25_QSPI +# include +#else +# include +#endif #include /*************************************************************************** @@ -56,6 +60,14 @@ # define CONFIG_GD25_SPIFREQUENCY 20000000 #endif +#ifndef CONFIG_GD25_QSPIMODE +# define CONFIG_GD25_QSPIMODE 0 +#endif + +#ifndef CONFIG_GD25_QSPIFREQUENCY +# define CONFIG_GD25_QSPIFREQUENCY 20000000 +#endif + /*************************************************************************** * GD25 Instructions ***************************************************************************/ @@ -65,20 +77,36 @@ #define GD25_WREN 0x06 /* Write enable */ #define GD25_WRDI 0x04 /* Write Disable */ #define GD25_RDSR 0x05 /* Read status register */ -#define GD25_RDSR1 0x35 /* Read status register-1 */ +#define GD25_RDSR1 0x35 /* Read status register-2 */ #define GD25_WRSR 0x01 /* Write Status Register */ #define GD25_RDDATA 0x03 /* Read data bytes */ -#define GD25_FRD 0x0b /* Higher speed read */ +#define GD25_FRD 0x0b /* Fast read (1-wire) */ #define GD25_FRDD 0x3b /* Fast read, dual output */ -#define GD25_PP 0x02 /* Program page */ -#define GD25_SE 0x20 /* Sector erase (4KB) */ -#define GD25_BE 0xd8 /* Block Erase (64KB) */ +#define GD25_QOFRD 0x6b /* Quad output fast read */ +#define GD25_QIOFRD 0xeb /* Quad I/O fast read, 3-byte */ +#define GD25_QIOFRD4B 0xec /* Quad I/O fast read, 4-byte */ +#define GD25_PP 0x02 /* Program page (1-1-1), 3-byte */ +#define GD25_PP4B 0x12 /* Program page (1-1-1), 4-byte */ +#define GD25_QPP 0x32 /* Quad page program (1-1-4), 3-byte */ +#define GD25_QPP4B 0x34 /* Quad page program (1-1-4), 4-byte */ +#define GD25_SE 0x20 /* Sector erase (4KB), 3-byte */ +#define GD25_SE4B 0x21 /* Sector erase (4KB), 4-byte */ +#define GD25_BE 0xd8 /* Block Erase (64KB), 3-byte */ +#define GD25_BE4B 0xdc /* Block Erase (64KB), 4-byte */ #define GD25_CE 0xc7 /* Chip erase */ #define GD25_PD 0xb9 /* Power down */ #define GD25_PURDID 0xab /* Release PD, Device ID */ #define GD25_RDMFID 0x90 /* Read Manufacturer / Device */ #define GD25_JEDEC_ID 0x9f /* JEDEC ID read */ #define GD25_4BEN 0xb7 /* Enable 4-byte Mode */ +#define GD25_4BEXT 0xe9 /* Exit 4-byte Mode */ + +/* Dummy clock cycles for Quad I/O Fast Read (EBh/ECh). + * Mode byte (2 clocks on 4-wire) + 4 additional = 6 total, matching + * the MX25RXX driver's default and safe up to ~80MHz at VCC=3.3V. + */ + +#define GD25_QIOFRD_DUMMIES 6 /*************************************************************************** * GD25 Registers @@ -112,6 +140,11 @@ #define GD25_SR1_EN4B (1 << 3) /* Bit 3: Enable 4byte address */ #define GD25Q_SR1_EN4B (1 << 0) /* Bit 0: Enable 4byte address GD25Q memories */ +/* Status Register 2 (SR2) bit definitions */ + +#define GD25_SR2_QE (1 << 1) /* Bit 1 of SR2 (S9): Quad Enable, non-volatile */ +#define GD25_SR2_PRESERVE_MASK 0x78 /* Preserve SRP1 (bit6) and LB3-LB1 (bits5-3) */ + #define GD25_DUMMY 0x00 /*************************************************************************** @@ -138,13 +171,18 @@ struct gd25_dev_s { - struct mtd_dev_s mtd; /* MTD interface */ - FAR struct spi_dev_s *spi; /* Saved SPI interface instance */ - uint32_t spi_devid; /* Chip select inputs */ - uint16_t nsectors; /* Number of erase sectors */ - uint8_t prev_instr; /* Previous instruction given to GD25 device */ - bool addr_4byte; /* True: Use Four-byte address */ - uint8_t memory; /* memory type read from device */ + struct mtd_dev_s mtd; /* MTD interface */ +#ifdef CONFIG_GD25_QSPI + FAR struct qspi_dev_s *qspi; /* Saved QSPI interface instance */ + FAR uint8_t *cmdbuf; /* DMA-safe command buffer */ +#else + FAR struct spi_dev_s *spi; /* Saved SPI interface instance */ + uint32_t spi_devid; /* Chip select inputs */ +#endif + uint16_t nsectors; /* Number of erase sectors */ + uint8_t prev_instr; /* Previous instruction given to GD25 device */ + bool addr_4byte; /* True: Use Four-byte address */ + uint8_t memory; /* memory type read from device */ }; /*************************************************************************** @@ -153,10 +191,13 @@ struct gd25_dev_s /* Helpers */ -static inline void gd25_purdid(FAR struct gd25_dev_s *priv); -static inline void gd25_pd(FAR struct gd25_dev_s *priv); +#ifdef CONFIG_GD25_QSPI +static void gd25_lock(FAR struct qspi_dev_s *qspi); +static inline void gd25_unlock(FAR struct qspi_dev_s *qspi); +#else static void gd25_lock(FAR struct spi_dev_s *spi); static inline void gd25_unlock(FAR struct spi_dev_s *spi); +#endif static inline int gd25_readid(FAR struct gd25_dev_s *priv); #ifndef CONFIG_GD25_READONLY static void gd25_unprotect(FAR struct gd25_dev_s *priv); @@ -198,33 +239,24 @@ static ssize_t gd25_write(FAR struct mtd_dev_s *dev, off_t offset, * Private Functions ***************************************************************************/ -/*************************************************************************** - * Name: gd25_purdid - ***************************************************************************/ - -static inline void gd25_purdid(FAR struct gd25_dev_s *priv) -{ - SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); - SPI_SEND(priv->spi, GD25_PURDID); - SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); - up_udelay(20); -} - -/*************************************************************************** - * Name: gd25_pd - ***************************************************************************/ - -static inline void gd25_pd(FAR struct gd25_dev_s *priv) -{ - SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); - SPI_SEND(priv->spi, GD25_PD); - SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); -} - /*************************************************************************** * Name: gd25_lock ***************************************************************************/ +#ifdef CONFIG_GD25_QSPI +static void gd25_lock(FAR struct qspi_dev_s *qspi) +{ + QSPI_LOCK(qspi, true); + QSPI_SETMODE(qspi, CONFIG_GD25_QSPIMODE); + QSPI_SETBITS(qspi, 8); + QSPI_SETFREQUENCY(qspi, CONFIG_GD25_QSPIFREQUENCY); +} + +static inline void gd25_unlock(FAR struct qspi_dev_s *qspi) +{ + QSPI_LOCK(qspi, false); +} +#else static void gd25_lock(FAR struct spi_dev_s *spi) { SPI_LOCK(spi, true); @@ -239,14 +271,11 @@ static void gd25_lock(FAR struct spi_dev_s *spi) #endif } -/*************************************************************************** - * Name: gd25_unlock - ***************************************************************************/ - static inline void gd25_unlock(FAR struct spi_dev_s *spi) { SPI_LOCK(spi, false); } +#endif /* CONFIG_GD25_QSPI */ /*************************************************************************** * Name: gd25_readid @@ -259,10 +288,26 @@ static inline int gd25_readid(FAR struct gd25_dev_s *priv) uint16_t capacity; int ret = -ENODEV; +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + + gd25_lock(priv->qspi); + + cmdinfo.flags = QSPICMD_READDATA; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_JEDEC_ID; + cmdinfo.buflen = 3; + cmdinfo.addr = 0; + cmdinfo.buffer = priv->cmdbuf; + QSPI_COMMAND(priv->qspi, &cmdinfo); + + manufacturer = priv->cmdbuf[0]; + memory = priv->cmdbuf[1]; + capacity = priv->cmdbuf[2]; +#else /* Lock and configure the SPI bus */ gd25_lock(priv->spi); - gd25_purdid(priv); /* Select this FLASH part. */ @@ -278,6 +323,7 @@ static inline int gd25_readid(FAR struct gd25_dev_s *priv) /* Deselect the FLASH and unlock the bus */ SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ finfo("manufacturer: %02x memory: %02x capacity: %02x\n", manufacturer, memory, capacity); @@ -344,8 +390,11 @@ out: * Or success. */ - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif return ret; } @@ -356,10 +405,39 @@ out: #ifndef CONFIG_GD25_READONLY static void gd25_unprotect(FAR struct gd25_dev_s *priv) { +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + uint8_t sr2; + + gd25_lock(priv->qspi); + gd25_waitwritecomplete(priv); + + /* Read SR2 to preserve OTP/SRP bits before writing */ + + sr2 = gd25_rdsr(priv, 1); + + gd25_wren(priv); + + /* SR1 = 0 (clear all block-protect bits); SR2 = preserve non-OTP bits, + * set QE (S9 = bit1 of SR2) so quad I/O pins are active. + */ + + priv->cmdbuf[0] = 0; + priv->cmdbuf[1] = (sr2 & GD25_SR2_PRESERVE_MASK) | GD25_SR2_QE; + cmdinfo.flags = QSPICMD_WRITEDATA; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_WRSR; + cmdinfo.buflen = 2; + cmdinfo.addr = 0; + cmdinfo.buffer = priv->cmdbuf; + QSPI_COMMAND(priv->qspi, &cmdinfo); + + gd25_waitwritecomplete(priv); + gd25_unlock(priv->qspi); +#else /* Lock and configure the SPI bus */ gd25_lock(priv->spi); - gd25_purdid(priv); /* Wait for any preceding write or erase operation to complete. */ @@ -384,8 +462,8 @@ static void gd25_unprotect(FAR struct gd25_dev_s *priv) /* Unlock the SPI bus */ - gd25_pd(priv); gd25_unlock(priv->spi); +#endif /* CONFIG_GD25_QSPI */ } #endif @@ -400,11 +478,19 @@ static uint8_t gd25_waitwritecomplete(FAR struct gd25_dev_s *priv) do { status = gd25_rdsr(priv, 0); - if (priv->prev_instr != GD25_PP && (status & GD25_SR_WIP) != 0) + if (priv->prev_instr != GD25_PP && priv->prev_instr != GD25_PP4B && + priv->prev_instr != GD25_QPP && priv->prev_instr != GD25_QPP4B && + (status & GD25_SR_WIP) != 0) { +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); + nxsig_usleep(1000); + gd25_lock(priv->qspi); +#else gd25_unlock(priv->spi); - nxsched_usleep(1000); + nxsig_usleep(1000); gd25_lock(priv->spi); +#endif } } while ((status & GD25_SR_WIP) != 0); @@ -418,18 +504,29 @@ static uint8_t gd25_waitwritecomplete(FAR struct gd25_dev_s *priv) static inline uint8_t gd25_rdsr(FAR struct gd25_dev_s *priv, uint32_t id) { - uint8_t status; uint8_t rdsr[2] = { GD25_RDSR, GD25_RDSR1 }; +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + cmdinfo.flags = QSPICMD_READDATA; + cmdinfo.addrlen = 0; + cmdinfo.cmd = rdsr[id]; + cmdinfo.buflen = 1; + cmdinfo.addr = 0; + cmdinfo.buffer = priv->cmdbuf; + QSPI_COMMAND(priv->qspi, &cmdinfo); + return priv->cmdbuf[0]; +#else + uint8_t status; SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); SPI_SEND(priv->spi, rdsr[id]); status = SPI_SEND(priv->spi, GD25_DUMMY); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); - return status; +#endif } /*************************************************************************** @@ -442,9 +539,20 @@ static inline uint8_t gd25_rdsr(FAR struct gd25_dev_s *priv, uint32_t id) static inline bool gd25_4ben(FAR struct gd25_dev_s *priv) { +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + cmdinfo.flags = 0; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_4BEN; + cmdinfo.buflen = 0; + cmdinfo.addr = 0; + cmdinfo.buffer = NULL; + QSPI_COMMAND(priv->qspi, &cmdinfo); +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); SPI_SEND(priv->spi, GD25_4BEN); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif if (priv->memory == GD25Q_JEDEC_MEMORY_TYPE) { return ((gd25_rdsr(priv, 1) & GD25Q_SR1_EN4B) == GD25Q_SR1_EN4B); @@ -461,9 +569,20 @@ static inline bool gd25_4ben(FAR struct gd25_dev_s *priv) static inline void gd25_wren(FAR struct gd25_dev_s *priv) { +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + cmdinfo.flags = 0; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_WREN; + cmdinfo.buflen = 0; + cmdinfo.addr = 0; + cmdinfo.buffer = NULL; + QSPI_COMMAND(priv->qspi, &cmdinfo); +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); SPI_SEND(priv->spi, GD25_WREN); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif } /*************************************************************************** @@ -472,9 +591,20 @@ static inline void gd25_wren(FAR struct gd25_dev_s *priv) static inline void gd25_wrdi(FAR struct gd25_dev_s *priv) { +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; + cmdinfo.flags = 0; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_WRDI; + cmdinfo.buflen = 0; + cmdinfo.addr = 0; + cmdinfo.buffer = NULL; + QSPI_COMMAND(priv->qspi, &cmdinfo); +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); SPI_SEND(priv->spi, GD25_WRDI); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif } /*************************************************************************** @@ -526,6 +656,9 @@ static bool gd25_is_erased(FAR struct gd25_dev_s *priv, off_t address, static void gd25_sectorerase(FAR struct gd25_dev_s *priv, off_t sector) { off_t address = sector << GD25_SECTOR_SHIFT; +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; +#endif finfo("sector: %08lx\n", (long)sector); @@ -546,6 +679,16 @@ static void gd25_sectorerase(FAR struct gd25_dev_s *priv, off_t sector) gd25_wren(priv); +#ifdef CONFIG_GD25_QSPI + cmdinfo.flags = QSPICMD_ADDRESS; + cmdinfo.addrlen = priv->addr_4byte ? 4 : 3; + cmdinfo.cmd = priv->addr_4byte ? GD25_SE4B : GD25_SE; + cmdinfo.buflen = 0; + cmdinfo.addr = address; + cmdinfo.buffer = NULL; + QSPI_COMMAND(priv->qspi, &cmdinfo); + priv->prev_instr = cmdinfo.cmd; +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); /* Send the "Sector Erase (SE)" instruction */ @@ -567,6 +710,7 @@ static void gd25_sectorerase(FAR struct gd25_dev_s *priv, off_t sector) SPI_SEND(priv->spi, address & 0xff); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ } /*************************************************************************** @@ -575,6 +719,10 @@ static void gd25_sectorerase(FAR struct gd25_dev_s *priv, off_t sector) static inline int gd25_chiperase(FAR struct gd25_dev_s *priv) { +#ifdef CONFIG_GD25_QSPI + struct qspi_cmdinfo_s cmdinfo; +#endif + /* Wait for any preceding write or erase operation to complete. */ gd25_waitwritecomplete(priv); @@ -583,6 +731,16 @@ static inline int gd25_chiperase(FAR struct gd25_dev_s *priv) gd25_wren(priv); +#ifdef CONFIG_GD25_QSPI + cmdinfo.flags = 0; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_CE; + cmdinfo.buflen = 0; + cmdinfo.addr = 0; + cmdinfo.buffer = NULL; + QSPI_COMMAND(priv->qspi, &cmdinfo); + priv->prev_instr = GD25_CE; +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); /* Send the "Chip Erase (CE)" instruction */ @@ -591,6 +749,7 @@ static inline int gd25_chiperase(FAR struct gd25_dev_s *priv) priv->prev_instr = GD25_CE; SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ return OK; } @@ -601,6 +760,10 @@ static inline int gd25_chiperase(FAR struct gd25_dev_s *priv) static void gd25_byteread(FAR struct gd25_dev_s *priv, FAR uint8_t *buffer, off_t address, size_t nbytes) { +#ifdef CONFIG_GD25_QSPI + struct qspi_meminfo_s meminfo; +#endif + finfo("address: %08lx nbytes: %d\n", (long)address, (int)nbytes); /* Wait for any preceding write or erase operation to complete. */ @@ -611,6 +774,17 @@ static void gd25_byteread(FAR struct gd25_dev_s *priv, FAR uint8_t *buffer, gd25_wrdi(priv); +#ifdef CONFIG_GD25_QSPI + meminfo.flags = QSPIMEM_READ | QSPIMEM_QUADIO; + meminfo.addrlen = priv->addr_4byte ? 4 : 3; + meminfo.dummies = GD25_QIOFRD_DUMMIES; + meminfo.buflen = nbytes; + meminfo.cmd = priv->addr_4byte ? GD25_QIOFRD4B : GD25_QIOFRD; + meminfo.addr = address; + meminfo.buffer = buffer; + QSPI_MEMORY(priv->qspi, &meminfo); + priv->prev_instr = meminfo.cmd; +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); /* Send "Read from Memory " instruction */ @@ -645,6 +819,7 @@ static void gd25_byteread(FAR struct gd25_dev_s *priv, FAR uint8_t *buffer, SPI_RECVBLOCK(priv->spi, buffer, nbytes); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ } /*************************************************************************** @@ -656,6 +831,17 @@ static void gd25_pagewrite(FAR struct gd25_dev_s *priv, FAR const uint8_t *buffer, off_t address, size_t nbytes) { +#ifdef CONFIG_GD25_QSPI + /* GD25 Quad Page Program (0x32/0x34) is a 1-1-4 transfer: the address + * is clocked on a single line and only the data is quad. + * QSPIMEM_QUADIO cannot express this (it forces the address quad too), + * so use QSPIMEM_QUADDATA, which sets the data phase quad while leaving + * the address phase single-line. + */ + + struct qspi_meminfo_s meminfo; +#endif + finfo("address: %08lx nwords: %d\n", (long)address, (int)nbytes); DEBUGASSERT(priv && buffer && (address & 0xff) == 0 && (nbytes & 0xff) == 0); @@ -670,6 +856,17 @@ static void gd25_pagewrite(FAR struct gd25_dev_s *priv, gd25_wren(priv); +#ifdef CONFIG_GD25_QSPI + meminfo.flags = QSPIMEM_WRITE | QSPIMEM_QUADDATA; + meminfo.cmd = priv->addr_4byte ? GD25_QPP4B : GD25_QPP; + meminfo.addrlen = priv->addr_4byte ? 4 : 3; + meminfo.buflen = GD25_PAGE_SIZE; + meminfo.dummies = 0; + meminfo.addr = address; + meminfo.buffer = (FAR void *)buffer; + QSPI_MEMORY(priv->qspi, &meminfo); + priv->prev_instr = meminfo.cmd; +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); /* Send the "Page Program (GD25_PP)" Command */ @@ -693,6 +890,7 @@ static void gd25_pagewrite(FAR struct gd25_dev_s *priv, SPI_SNDBLOCK(priv->spi, buffer, GD25_PAGE_SIZE); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ /* Update addresses */ @@ -711,6 +909,14 @@ static inline void gd25_bytewrite(FAR struct gd25_dev_s *priv, FAR const uint8_t *buffer, off_t offset, uint16_t count) { +#ifdef CONFIG_GD25_QSPI + /* See gd25_pagewrite: GD25 Quad Page Program (0x32/0x34) is 1-1-4. + * QSPIMEM_QUADDATA selects quad data with a single-line address. + */ + + struct qspi_meminfo_s meminfo; +#endif + finfo("offset: %08lx count:%d\n", (long)offset, count); /* Wait for any preceding write to complete. We could simplify things by @@ -725,6 +931,17 @@ static inline void gd25_bytewrite(FAR struct gd25_dev_s *priv, gd25_wren(priv); +#ifdef CONFIG_GD25_QSPI + meminfo.flags = QSPIMEM_WRITE | QSPIMEM_QUADDATA; + meminfo.cmd = priv->addr_4byte ? GD25_QPP4B : GD25_QPP; + meminfo.addrlen = priv->addr_4byte ? 4 : 3; + meminfo.buflen = count; + meminfo.dummies = 0; + meminfo.addr = offset; + meminfo.buffer = (FAR void *)buffer; + QSPI_MEMORY(priv->qspi, &meminfo); + priv->prev_instr = meminfo.cmd; +#else SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), true); /* Send "Page Program (PP)" command */ @@ -748,6 +965,7 @@ static inline void gd25_bytewrite(FAR struct gd25_dev_s *priv, SPI_SNDBLOCK(priv->spi, buffer, count); SPI_SELECT(priv->spi, SPIDEV_FLASH(priv->spi_devid), false); +#endif /* CONFIG_GD25_QSPI */ finfo("Written\n"); } #endif /* defined(CONFIG_MTD_BYTE_WRITE) && !defined(CONFIG_GD25_READONLY) */ @@ -767,10 +985,13 @@ static int gd25_erase(FAR struct mtd_dev_s *dev, off_t startblock, finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); - /* Lock access to the SPI bus until we complete the erase */ + /* Lock access to the bus until we complete the erase */ +#ifdef CONFIG_GD25_QSPI + gd25_lock(priv->qspi); +#else gd25_lock(priv->spi); - gd25_purdid(priv); +#endif while (blocksleft-- > 0) { @@ -780,8 +1001,11 @@ static int gd25_erase(FAR struct mtd_dev_s *dev, off_t startblock, startblock++; } - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif return (int)nblocks; #endif } @@ -821,14 +1045,20 @@ static ssize_t gd25_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); - /* Lock the SPI bus and write all of the pages to FLASH */ + /* Lock the bus and write all of the pages to FLASH */ +#ifdef CONFIG_GD25_QSPI + gd25_lock(priv->qspi); +#else gd25_lock(priv->spi); - gd25_purdid(priv); +#endif gd25_pagewrite(priv, buffer, startblock << GD25_PAGE_SHIFT, nblocks << GD25_PAGE_SHIFT); - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif return nblocks; #endif @@ -845,13 +1075,19 @@ static ssize_t gd25_read(FAR struct mtd_dev_s *dev, off_t offset, finfo("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes); - /* Lock the SPI bus and select this FLASH part */ + /* Lock the bus and select this FLASH part */ +#ifdef CONFIG_GD25_QSPI + gd25_lock(priv->qspi); +#else gd25_lock(priv->spi); - gd25_purdid(priv); +#endif gd25_byteread(priv, buffer, offset, nbytes); - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif finfo("return nbytes: %d,%x,%x\n", (int)nbytes, buffer[0], buffer[1]); return nbytes; @@ -885,8 +1121,11 @@ static ssize_t gd25_write(FAR struct mtd_dev_s *dev, off_t offset, startpage = offset / GD25_PAGE_SIZE; endpage = (offset + nbytes) / GD25_PAGE_SIZE; +#ifdef CONFIG_GD25_QSPI + gd25_lock(priv->qspi); +#else gd25_lock(priv->spi); - gd25_purdid(priv); +#endif if (startpage == endpage) { /* All bytes within one programmable page. Just do the write. */ @@ -928,8 +1167,11 @@ static ssize_t gd25_write(FAR struct mtd_dev_s *dev, off_t offset, } } - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif return nbytes; #endif } @@ -988,11 +1230,17 @@ static int gd25_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) { /* Erase the entire device */ +#ifdef CONFIG_GD25_QSPI + gd25_lock(priv->qspi); +#else gd25_lock(priv->spi); - gd25_purdid(priv); +#endif ret = gd25_chiperase(priv); - gd25_pd(priv); +#ifdef CONFIG_GD25_QSPI + gd25_unlock(priv->qspi); +#else gd25_unlock(priv->spi); +#endif } break; @@ -1028,6 +1276,83 @@ static int gd25_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg) * ***************************************************************************/ +#ifdef CONFIG_GD25_QSPI +FAR struct mtd_dev_s *gd25_initialize(FAR struct qspi_dev_s *qspi, + bool unprotect) +{ + FAR struct gd25_dev_s *priv; + int ret; + + priv = (FAR struct gd25_dev_s *)kmm_zalloc(sizeof(struct gd25_dev_s)); + if (priv) + { + priv->mtd.erase = gd25_erase; + priv->mtd.bread = gd25_bread; + priv->mtd.bwrite = gd25_bwrite; + priv->mtd.read = gd25_read; + priv->mtd.ioctl = gd25_ioctl; +#ifdef CONFIG_MTD_BYTE_WRITE + priv->mtd.write = gd25_write; +#endif + priv->mtd.name = "gd25"; + priv->qspi = qspi; + + priv->cmdbuf = (FAR uint8_t *)QSPI_ALLOC(qspi, 4); + if (!priv->cmdbuf) + { + kmm_free(priv); + return NULL; + } + + ret = gd25_readid(priv); + if (ret != OK) + { + ferr("ERROR: Unrecognized\n"); + QSPI_FREE(qspi, priv->cmdbuf); + kmm_free(priv); + return NULL; + } + + /* QE (Quad Enable) must be set before any quad I/O command is issued. + * It is non-volatile, so only write if currently clear to avoid + * unnecessary write cycles. + */ + + if (!(gd25_rdsr(priv, 1) & GD25_SR2_QE)) + { + uint8_t sr2 = gd25_rdsr(priv, 1); + + gd25_lock(priv->qspi); + gd25_waitwritecomplete(priv); + gd25_wren(priv); + + priv->cmdbuf[0] = 0; + priv->cmdbuf[1] = (sr2 & GD25_SR2_PRESERVE_MASK) | GD25_SR2_QE; + + struct qspi_cmdinfo_s cmdinfo; + cmdinfo.flags = QSPICMD_WRITEDATA; + cmdinfo.addrlen = 0; + cmdinfo.cmd = GD25_WRSR; + cmdinfo.buflen = 2; + cmdinfo.addr = 0; + cmdinfo.buffer = priv->cmdbuf; + QSPI_COMMAND(priv->qspi, &cmdinfo); + + gd25_waitwritecomplete(priv); + gd25_unlock(priv->qspi); + } + +#ifndef CONFIG_GD25_READONLY + if (unprotect) + { + gd25_unprotect(priv); + } +#endif + } + + return (FAR struct mtd_dev_s *)priv; +} +#else FAR struct mtd_dev_s *gd25_initialize(FAR struct spi_dev_s *spi, uint32_t spi_devid) { @@ -1082,3 +1407,4 @@ FAR struct mtd_dev_s *gd25_initialize(FAR struct spi_dev_s *spi, return (FAR struct mtd_dev_s *)priv; } +#endif /* CONFIG_GD25_QSPI */ diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index 961ffd2ddd9..eebb310cb31 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -649,8 +649,13 @@ FAR struct mtd_dev_s *w25_initialize(FAR struct spi_dev_s *dev); * ****************************************************************************/ +#ifdef CONFIG_GD25_QSPI +FAR struct mtd_dev_s *gd25_initialize(FAR struct qspi_dev_s *qspi, + bool unprotect); +#else FAR struct mtd_dev_s *gd25_initialize(FAR struct spi_dev_s *dev, uint32_t spi_devid); +#endif /**************************************************************************** * Name: gd55_initialize From 6a2eef788d4bb55a20ee632f1fffcbfbe5f68d22 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Fri, 19 Jun 2026 17:21:18 +0200 Subject: [PATCH 127/268] arch/risc-v/espressif: Add TWAI2 support for esp32p4 Enable TWAI2 support for esp32p4 Signed-off-by: Eren Terzioglu --- arch/risc-v/src/common/espressif/Kconfig | 50 ++++++++++++++++++++ arch/risc-v/src/common/espressif/esp_twai.c | 51 +++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index d983b2264e4..e4df0a5c2eb 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -1645,6 +1645,14 @@ config ESPRESSIF_TWAI1 select ARCH_HAVE_CAN_ERRORS select CAN +config ESPRESSIF_TWAI2 + bool "TWAI2 (CAN)" + default n + depends on ARCH_CHIP_ESP32P4 + select ESPRESSIF_TWAI + select ARCH_HAVE_CAN_ERRORS + select CAN + config ESPRESSIF_USBSERIAL bool "USB-Serial-JTAG Driver" default n @@ -3438,6 +3446,48 @@ config ESPRESSIF_TWAI1_SAM endif # ESPRESSIF_TWAI1 +if ESPRESSIF_TWAI2 + +config ESPRESSIF_TWAI2_TXPIN + int "TWAI2 TX Pin" + default 6 + +config ESPRESSIF_TWAI2_RXPIN + int "TWAI2 RX Pin" + default 7 + +choice ESPRESSIF_TWAI2_TIMING + prompt "TWAI2 Timing config" + default TWAI2_TIMING_100KBITS + ---help--- + These options control timing of TWAI2. + +config TWAI2_TIMING_100KBITS + bool "100 KBits" + +config TWAI2_TIMING_125KBITS + bool "125 KBits" + +config TWAI2_TIMING_250KBITS + bool "250 KBits" + +config TWAI2_TIMING_500KBITS + bool "500 KBits" + +config TWAI2_TIMING_800KBITS + bool "800 KBits" + +endchoice # ESPRESSIF_TWAI2_TIMING + +config ESPRESSIF_TWAI2_SAM + bool "TWAI2 sampling" + default n + ---help--- + The bus is sampled 3 times (recommended for low to medium speed buses + to spikes on the bus-line). + +endif # ESPRESSIF_TWAI2 + config ESPRESSIF_TWAI_TEST_MODE bool "TWAI character driver loopback test mode (for testing only)" default n diff --git a/arch/risc-v/src/common/espressif/esp_twai.c b/arch/risc-v/src/common/espressif/esp_twai.c index 77920410d3e..166c753d3ad 100644 --- a/arch/risc-v/src/common/espressif/esp_twai.c +++ b/arch/risc-v/src/common/espressif/esp_twai.c @@ -99,6 +99,20 @@ # endif #endif +#ifdef CONFIG_ESPRESSIF_TWAI2 +# ifdef CONFIG_TWAI2_TIMING_100KBITS +# define TWAI2_TIMING_CONFIG TWAI_TIMING_CONFIG_100KBITS() +# elif CONFIG_TWAI2_TIMING_125KBITS +# define TWAI2_TIMING_CONFIG TWAI_TIMING_CONFIG_125KBITS() +# elif CONFIG_TWAI2_TIMING_250KBITS +# define TWAI2_TIMING_CONFIG TWAI_TIMING_CONFIG_250KBITS() +# elif CONFIG_TWAI2_TIMING_500KBITS +# define TWAI2_TIMING_CONFIG TWAI_TIMING_CONFIG_500KBITS() +# else +# define TWAI2_TIMING_CONFIG TWAI_TIMING_CONFIG_800KBITS() +# endif +#endif + #if defined(CONFIG_ARCH_CHIP_ESP32C3) # define INT_ENA_REG(hw) hw->interrupt_enable_reg.val #elif defined(CONFIG_ARCH_CHIP_ESP32P4) @@ -226,6 +240,24 @@ static struct can_dev_s g_twai1dev = }; #endif /* CONFIG_ESPRESSIF_TWAI1 */ +#ifdef CONFIG_ESPRESSIF_TWAI2 +static struct esp_twai_dev_s g_twai2priv = +{ + .port = 2, + .cpuint = -ENOMEM, + .t_config = TWAI2_TIMING_CONFIG, +#ifdef CONFIG_PM + .pm_lock = NULL, +#endif +}; + +static struct can_dev_s g_twai2dev = +{ + .cd_ops = &g_twaiops, + .cd_priv = &g_twai2priv, +}; +#endif /* CONFIG_ESPRESSIF_TWAI2 */ + static const twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL(); /**************************************************************************** @@ -865,6 +897,25 @@ struct can_dev_s *esp_twaiinitialize(int port) else #endif +#ifdef CONFIG_ESPRESSIF_TWAI2 + if (port == 2) + { + int tx_sig = twai_periph_signals[2].tx_sig; + int rx_sig = twai_periph_signals[2].rx_sig; + + /* Configure CAN GPIO pins */ + + esp_gpio_matrix_out(CONFIG_ESPRESSIF_TWAI2_TXPIN, tx_sig, 0, 0); + esp_configgpio(CONFIG_ESPRESSIF_TWAI2_TXPIN, TX_PIN_ATTR); + + esp_gpio_matrix_in(CONFIG_ESPRESSIF_TWAI2_RXPIN, rx_sig, 0); + esp_configgpio(CONFIG_ESPRESSIF_TWAI2_RXPIN, RX_PIN_ATTR); + + dev = &g_twai2dev; + } + else +#endif + { canerr("ERROR: Unsupported port: %d\n", port); leave_critical_section(flags); From 66084dafb77d8da8aae3064ad58fdc879d6433f4 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Fri, 19 Jun 2026 17:49:49 +0200 Subject: [PATCH 128/268] boards/risc-v/esp32p4: Add TWAI2 support for esp32p4 Add TWAI2 support for esp32p4 Signed-off-by: Eren Terzioglu --- boards/risc-v/esp32p4/common/src/esp_board_twai.c | 11 +++++++++++ .../esp32p4-function-ev-board/src/esp32p4_bringup.c | 11 +++++++++++ 2 files changed, 22 insertions(+) diff --git a/boards/risc-v/esp32p4/common/src/esp_board_twai.c b/boards/risc-v/esp32p4/common/src/esp_board_twai.c index 936c2f9e454..a3cab7e2f1f 100644 --- a/boards/risc-v/esp32p4/common/src/esp_board_twai.c +++ b/boards/risc-v/esp32p4/common/src/esp_board_twai.c @@ -98,6 +98,17 @@ int board_twai_setup(int port) } #endif /* CONFIG_ESPRESSIF_TWAI1 */ +#ifdef CONFIG_ESPRESSIF_TWAI2 + /* Register the TWAI driver at "/dev/can2" */ + + ret = can_register("/dev/can2", twai); + if (ret < 0) + { + canerr("ERROR: TWAI2 register failed: %d\n", ret); + return ret; + } +#endif /* CONFIG_ESPRESSIF_TWAI2 */ + return OK; #else return -ENODEV; diff --git a/boards/risc-v/esp32p4/esp32p4-function-ev-board/src/esp32p4_bringup.c b/boards/risc-v/esp32p4/esp32p4-function-ev-board/src/esp32p4_bringup.c index d4cc36bd60b..44322a8222e 100644 --- a/boards/risc-v/esp32p4/esp32p4-function-ev-board/src/esp32p4_bringup.c +++ b/boards/risc-v/esp32p4/esp32p4-function-ev-board/src/esp32p4_bringup.c @@ -401,6 +401,17 @@ int esp_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_TWAI2 + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(2); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: TWAI2 board_twai_setup failed: %d\n", ret); + } +#endif + #ifdef CONFIG_DEV_GPIO ret = esp_gpio_init(); if (ret < 0) From 5b94c8031ed26cc87b116493f3b09ee0d2596df4 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Fri, 19 Jun 2026 17:50:58 +0200 Subject: [PATCH 129/268] Docs/platforms/risc-v: Add TWAI2 docs for esp32p4 Add TWAI2 docs for esp32p4 Signed-off-by: Eren Terzioglu --- Documentation/platforms/risc-v/esp32p4/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/platforms/risc-v/esp32p4/index.rst b/Documentation/platforms/risc-v/esp32p4/index.rst index 37e64b3ba61..86cb9583a38 100644 --- a/Documentation/platforms/risc-v/esp32p4/index.rst +++ b/Documentation/platforms/risc-v/esp32p4/index.rst @@ -341,7 +341,7 @@ Bit Scrambler No SD/MMC Host No H264 Encoder No 2D-DMA No -TWAI (CAN) Yes TWAI0/1 +TWAI (CAN) Yes TWAI0/1/2 Pulse Counter Yes Implemented as Quadrature Encoder RMT Yes USB Serial/JTAG Yes From 9e254e898d99bd8557105fd09d29f44fa24c94e2 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Fri, 19 Jun 2026 18:17:10 +0200 Subject: [PATCH 130/268] boards/risc-v/espressif: Fix twai initialization for esp32[-c6|-p4] Fix twai initialization when multiple twai devices enabled for esp32c6 and esp32p4 Signed-off-by: Eren Terzioglu --- .../esp32c6/common/src/esp_board_twai.c | 26 +++++-------- .../esp32p4/common/src/esp_board_twai.c | 37 +++++-------------- 2 files changed, 18 insertions(+), 45 deletions(-) diff --git a/boards/risc-v/esp32c6/common/src/esp_board_twai.c b/boards/risc-v/esp32c6/common/src/esp_board_twai.c index 05f22a94400..b7cfcead853 100644 --- a/boards/risc-v/esp32c6/common/src/esp_board_twai.c +++ b/boards/risc-v/esp32c6/common/src/esp_board_twai.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -40,6 +41,9 @@ * Pre-processor Definitions ****************************************************************************/ +#define DEVNAME_FMT "/dev/can%d" +#define DEVNAME_FMTLEN (8 + 3 + 1) + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -63,6 +67,7 @@ int board_twai_setup(int port) { #ifdef CONFIG_ESPRESSIF_TWAI struct can_dev_s *twai; + char devname[DEVNAME_FMTLEN]; int ret; /* Call esp_twaiinitialize() to get an instance of the TWAI @@ -72,31 +77,18 @@ int board_twai_setup(int port) twai = esp_twaiinitialize(port); if (twai == NULL) { - canerr("ERROR: Failed to get TWAI interface\n"); + canerr("ERROR: Failed to get TWAI interface for port %d\n", port); return -ENODEV; } -#ifdef CONFIG_ESPRESSIF_TWAI0 - /* Register the TWAI driver at "/dev/can0" */ + snprintf(devname, sizeof(devname), DEVNAME_FMT, port); - ret = can_register("/dev/can0", twai); + ret = can_register(devname, twai); if (ret < 0) { - canerr("ERROR: TWAI0 register failed: %d\n", ret); + canerr("ERROR: TWAI%d register failed: %d\n", port, ret); return ret; } -#endif /* CONFIG_ESPRESSIF_TWAI0 */ - -#ifdef CONFIG_ESPRESSIF_TWAI1 - /* Register the TWAI driver at "/dev/can1" */ - - ret = can_register("/dev/can1", twai); - if (ret < 0) - { - canerr("ERROR: TWAI1 register failed: %d\n", ret); - return ret; - } -#endif /* CONFIG_ESPRESSIF_TWAI1 */ return OK; #else diff --git a/boards/risc-v/esp32p4/common/src/esp_board_twai.c b/boards/risc-v/esp32p4/common/src/esp_board_twai.c index a3cab7e2f1f..d0a4851e628 100644 --- a/boards/risc-v/esp32p4/common/src/esp_board_twai.c +++ b/boards/risc-v/esp32p4/common/src/esp_board_twai.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -40,6 +41,9 @@ * Pre-processor Definitions ****************************************************************************/ +#define DEVNAME_FMT "/dev/can%d" +#define DEVNAME_FMTLEN (8 + 3 + 1) + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -63,6 +67,7 @@ int board_twai_setup(int port) { #ifdef CONFIG_ESPRESSIF_TWAI struct can_dev_s *twai; + char devname[DEVNAME_FMTLEN]; int ret; /* Call esp_twaiinitialize() to get an instance of the TWAI @@ -72,42 +77,18 @@ int board_twai_setup(int port) twai = esp_twaiinitialize(port); if (twai == NULL) { - canerr("ERROR: Failed to get TWAI interface\n"); + canerr("ERROR: Failed to get TWAI interface for port %d\n", port); return -ENODEV; } -#ifdef CONFIG_ESPRESSIF_TWAI0 - /* Register the TWAI driver at "/dev/can0" */ + snprintf(devname, sizeof(devname), DEVNAME_FMT, port); - ret = can_register("/dev/can0", twai); + ret = can_register(devname, twai); if (ret < 0) { - canerr("ERROR: TWAI0 register failed: %d\n", ret); + canerr("ERROR: TWAI%d register failed: %d\n", port, ret); return ret; } -#endif /* CONFIG_ESPRESSIF_TWAI0 */ - -#ifdef CONFIG_ESPRESSIF_TWAI1 - /* Register the TWAI driver at "/dev/can1" */ - - ret = can_register("/dev/can1", twai); - if (ret < 0) - { - canerr("ERROR: TWAI1 register failed: %d\n", ret); - return ret; - } -#endif /* CONFIG_ESPRESSIF_TWAI1 */ - -#ifdef CONFIG_ESPRESSIF_TWAI2 - /* Register the TWAI driver at "/dev/can2" */ - - ret = can_register("/dev/can2", twai); - if (ret < 0) - { - canerr("ERROR: TWAI2 register failed: %d\n", ret); - return ret; - } -#endif /* CONFIG_ESPRESSIF_TWAI2 */ return OK; #else From c43050ae80d34bbb9668e8dc0f1ecfbc3c522b8d Mon Sep 17 00:00:00 2001 From: simbit18 <101105604+simbit18@users.noreply.github.com> Date: Sun, 21 Jun 2026 14:48:32 +0200 Subject: [PATCH 131/268] ci/docker: fix No package 'libftdi1' found libftdi1-dev has been moved to the correct stage in the Dockerfile Fix https://github.com/apache/nuttx/pull/18951#issuecomment-4708056829 Signed-off-by: simbit18 --- tools/ci/docker/linux/Dockerfile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/ci/docker/linux/Dockerfile b/tools/ci/docker/linux/Dockerfile index 6ad5954d117..831ba92e5db 100644 --- a/tools/ci/docker/linux/Dockerfile +++ b/tools/ci/docker/linux/Dockerfile @@ -37,7 +37,6 @@ RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" apt-get install -y -q gawk \ git \ gperf \ - libftdi1-dev \ libncurses5-dev \ make \ ninja-build \ @@ -359,6 +358,7 @@ RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" TZ=Etc/UTC apt-get in libpython2.7 \ libtinfo5 \ libusb-1.0-0-dev libusb-1.0-0-dev:i386 \ + libftdi1-dev \ libv4l-dev libv4l-dev:i386 \ libx11-dev libx11-dev:i386 \ libxext-dev libxext-dev:i386 \ From 96a4778d599b938f5b12bcf115891e4d880f48f3 Mon Sep 17 00:00:00 2001 From: simbit18 <101105604+simbit18@users.noreply.github.com> Date: Sun, 21 Jun 2026 14:53:47 +0200 Subject: [PATCH 132/268] ci/testlist/sim-02.dat enabled sim:ft2232h_gpio enabled sim:ft2232h_gpio Signed-off-by: simbit18 --- tools/ci/testlist/sim-02.dat | 3 --- 1 file changed, 3 deletions(-) diff --git a/tools/ci/testlist/sim-02.dat b/tools/ci/testlist/sim-02.dat index 552af99592a..56e85274ea1 100644 --- a/tools/ci/testlist/sim-02.dat +++ b/tools/ci/testlist/sim-02.dat @@ -1,9 +1,6 @@ /sim/*/*/*/c[j-z]* /sim/*/*/*/[d-n]* -# FTDI lib doesn't work on CI --sim:ft2232h_gpio - # cURL error 60 SSL certificate expired -sim:cxxtest From c57836bff3b9641d3023fe215b17d975892c9ae6 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 22 Jun 2026 02:52:36 +0000 Subject: [PATCH 133/268] build(deps): bump docker/login-action from 4.0.0 to 4.2.0 Bumps [docker/login-action](https://github.com/docker/login-action) from 4.0.0 to 4.2.0. - [Release notes](https://github.com/docker/login-action/releases) - [Commits](https://github.com/docker/login-action/compare/v4...650006c6eb7dba73a995cc03b0b2d7f5ca915bee) --- updated-dependencies: - dependency-name: docker/login-action dependency-version: 4.2.0 dependency-type: direct:production update-type: version-update:semver-minor ... Signed-off-by: dependabot[bot] --- .github/workflows/membrowse-report.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml index 04e61f57541..25e096d47d9 100644 --- a/.github/workflows/membrowse-report.yml +++ b/.github/workflows/membrowse-report.yml @@ -142,7 +142,7 @@ jobs: fetch-depth: 1 - name: Docker Login - uses: docker/login-action@b45d80f862d83dbcd57f89517bcf500b2ab88fb2 # v4.0.0 + uses: docker/login-action@650006c6eb7dba73a995cc03b0b2d7f5ca915bee # v4.2.0 with: registry: ghcr.io username: ${{ github.actor }} From 6edb14b1f0e696f41172eec0cafbe4b448a64a6a Mon Sep 17 00:00:00 2001 From: Michael Rogov Papernov Date: Mon, 22 Jun 2026 12:08:18 +0100 Subject: [PATCH 134/268] ci/testing: MemBrowse support multi commit pushes Keep the commit chain intact in case of a multi commit push Signed-off-by: Michael Rogov Papernov --- .github/workflows/membrowse-report.yml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml index 25e096d47d9..a4ac3022f0c 100644 --- a/.github/workflows/membrowse-report.yml +++ b/.github/workflows/membrowse-report.yml @@ -104,6 +104,9 @@ jobs: MEMBROWSE_API_KEY: ${{ secrets.MEMBROWSE_API_KEY }} MEMBROWSE_API_URL: ${{ vars.MEMBROWSE_API_URL }} TARGET_NAME: ${{ matrix.target_name }} + # Base on the previous branch tip, not the (often unreported mid-PR) + # git parent. + BEFORE_SHA: ${{ github.event.before }} run: | ARGS=(--upload --github --target-name "$TARGET_NAME" @@ -112,6 +115,10 @@ jobs: if [ -n "$MEMBROWSE_API_URL" ]; then ARGS+=(--api-url "$MEMBROWSE_API_URL") fi + # Override parent with previous tip; skip on branch creation (0s). + if [ -n "$BEFORE_SHA" ] && [ "$BEFORE_SHA" != "0000000000000000000000000000000000000000" ]; then + ARGS+=(--base-sha "$BEFORE_SHA") + fi membrowse report "${ARGS[@]}" # Build target with debug symbols + linker map, then upload MemBrowse report. @@ -210,6 +217,10 @@ jobs: LD_PATHS: ${{ steps.ld.outputs.paths }} MAP_FILE: ${{ matrix.map_file != '' && format('sources/nuttx/{0}', matrix.map_file) || '' }} LINKER_VARS: ${{ matrix.linker_vars }} + # Push only: base on the previous branch tip, not the (often + # unreported mid-PR) git parent. Empty on PRs (--github bases on the + # PR target tip). + BEFORE_SHA: ${{ github.event_name == 'push' && github.event.before || '' }} run: | set -o pipefail ARGS=("$ELF" "$LD_PATHS" @@ -219,6 +230,10 @@ jobs: if [ -n "$MEMBROWSE_API_URL" ]; then ARGS+=(--api-url "$MEMBROWSE_API_URL") fi + # Override parent with previous tip; skip on branch creation (0s). + if [ -n "$BEFORE_SHA" ] && [ "$BEFORE_SHA" != "0000000000000000000000000000000000000000" ]; then + ARGS+=(--base-sha "$BEFORE_SHA") + fi if [ -n "$MAP_FILE" ]; then ARGS+=(--map-file "$MAP_FILE") fi From 280fbba5171b0e2049187a211c33b8b11cfe435d Mon Sep 17 00:00:00 2001 From: Joao Mario Lago Date: Tue, 23 Jun 2026 01:21:25 -0300 Subject: [PATCH 135/268] stm32h5/adc: Enable ADC1.OR.OP0 for INP0 and INN1. On STM32H5, ADC1.OR.OP0 (RM0481 26.6.23) enables the GPIO switch that routes PA0 to ADC mux (ADC1_INP0 or ADC1_INN1). Set ADC1.OR.OP0 during `adc_setup()` when ADC1 channel 0 is selected, or when channel 1 is configured in differential mode. Signed-off-by: Joao Mario Lago --- arch/arm/src/stm32h5/stm32_adc.c | 38 ++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index a6036132faa..7fe90ea6464 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -203,6 +203,7 @@ static uint32_t adc_sqrbits(struct stm32_dev_s *priv, int first, int last, int offset); static int adc_set_ch(struct adc_dev_s *dev, uint8_t ch); static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr); +static void adc_enable_optreg(struct stm32_dev_s * priv); static void adc_startconv(struct stm32_dev_s *priv, bool enable); #ifdef ADC_HAVE_WDG1 static void adc_wdog1_enable(struct stm32_dev_s *priv); @@ -1481,6 +1482,8 @@ static int adc_setup(struct adc_dev_s *dev) adc_set_ch(dev, 0); + adc_enable_optreg(priv); + /* ADC CCR configuration */ clrbits = ADC_CCR_PRESC_MASK | ADC_CCR_VREFEN | @@ -1647,6 +1650,41 @@ static bool adc_internal(struct stm32_dev_s * priv, uint32_t *adc_ccr) return internal; } +/**************************************************************************** + * Name: adc_enable_optreg + * + * Description: + * Connects ADC1_INP0/ADC1_INN1 to the ADC mux if necessary. + * + * Input Parameters: + * priv - A reference to the ADC block status + * + ****************************************************************************/ + +static void adc_enable_optreg(struct stm32_dev_s * priv) +{ + int i; + + /* ADC1.OR.OP0 (RM0481 26.6.23) + * Enables the GPIO switch connecting ADC1_INP0/ADC1_INN1 to the ADC mux. + * This bit must be set when channel ADC1_INP0 or ADCx_INN1 is selected. + */ + + if (priv->intf == 1) + { + for (i = 0; i < priv->cchannels; i++) + { + uint8_t ch = priv->chanlist[i]; + + if (ch == 0 || (ch == 1 && (priv->difsel & ADC_DIFSEL_CH(1)))) + { + adc_putreg(priv, STM32_ADC_OR_OFFSET, ADC_OR_OP0); + return; + } + } + } +} + /**************************************************************************** * Name: adc_set_ch * From 379dd1c5e0efd4860496ca6347005537498aa9e3 Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sat, 20 Jun 2026 12:53:50 -0400 Subject: [PATCH 136/268] bcm2711/i2c: Support I2C_M_NOSTOP/I2C_M_NOSTART properly This commit adds support for I2C transfers spread across multiple messages using the I2C_M_NOSTOP/I2C_M_NOSTART. The approach greedily merges as many sequential I2C messages together as possible and considers them as a single transfer. Signed-off-by: Matteo Golin --- arch/arm64/src/bcm2711/bcm2711_i2c.c | 247 +++++++++++++++++++-------- 1 file changed, 176 insertions(+), 71 deletions(-) diff --git a/arch/arm64/src/bcm2711/bcm2711_i2c.c b/arch/arm64/src/bcm2711/bcm2711_i2c.c index 67208f8d588..ab9fb9d81bb 100644 --- a/arch/arm64/src/bcm2711/bcm2711_i2c.c +++ b/arch/arm64/src/bcm2711/bcm2711_i2c.c @@ -51,8 +51,6 @@ #include "chip.h" #include "hardware/bcm2711_bsc.h" -#if defined(CONFIG_BCM2711_I2C) - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -210,13 +208,13 @@ static int bcm2711_i2c_interrupted(struct bcm2711_i2cdev_s *priv); static void bcm2711_i2c_disable(struct bcm2711_i2cdev_s *priv); static void bcm2711_i2c_enable(struct bcm2711_i2cdev_s *priv); static size_t bcm2711_i2c_drainrxfifo(struct bcm2711_i2cdev_s *priv, - FAR uint8_t *buf, size_t n); + uint8_t *buf, size_t n); static size_t bcm2711_i2c_filltxfifo(struct bcm2711_i2cdev_s *priv, - FAR uint8_t *buf, size_t n); -static int bcm2711_i2c_send(struct bcm2711_i2cdev_s *priv, FAR void *buf, - size_t n); -static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, FAR void *buf, - size_t n); + uint8_t *buf, size_t n); +static int bcm2711_i2c_send(struct bcm2711_i2cdev_s *priv, + struct i2c_msg_s *msgs, size_t n); +static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, + struct i2c_msg_s *msgs, size_t n); static int bcm2711_i2c_secondary_handler(struct bcm2711_i2cdev_s *priv); static int bcm2711_i2c_transfer(struct i2c_master_s *dev, @@ -389,6 +387,77 @@ static struct bcm2711_i2cdev_s *g_i2c_devices[BCM_BSCS_NUM] = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: merge_messages + * + * Description: + * The BCM2711 I2C interface does not natively support I2C_M_NOSTART and + * I2C_M_NOSTOP. However, the NuttX I2C driver requires that a message with + * the I2C_M_NOSTOP flag followed by a message with I2C_M_NOSTART should be + * sent as one, homogeneous message. + * + * This function greedily merges as many sequential I2C messages as + * possible that have these flags. This way, the I2C messages will be sent + * as one larger I2C message via the BCM2711. + * + * For two messages to be merged, they must: + * - Both have the same message type (READ/WRITE) + * - The first message must have the NOSTOP flag + * - The second message must have the NOSTART flag + * + * If we have three READ messages with the following flags: + * 1) NOSTOP + * 2) NOSTOP | NOSTART + * 3) NOSTART + * + * They will be merged as one message, with the size returned being their + * combined sizes. + * + * Input Parameters: + * msgs - A list of messages to try to merge, starting from the first + * message + * count - The number of messages in `msgs` (NOTE: assumed >= 1) + * + * Return Value: + * The total length (in bytes) of the full message (composed of + * fragments) starting from the first message component in `msg`. + * + ****************************************************************************/ + +static size_t merge_messages(struct i2c_msg_s *msgs, int count) +{ + const uint16_t type = msgs[0].flags & I2C_M_READ; + const uint16_t addr = msgs[0].addr; + const uint32_t freq = msgs[0].frequency; + size_t combined_size = msgs[0].length; + + for (int i = 1; i < count; i++) + { + /* Check that the message has the same core attributes or break */ + + if ((msgs[i].flags & I2C_M_READ) != type && msgs[i].addr != addr && + msgs[i].frequency != freq) + { + break; + } + + /* This message has the same core attributes as our merge. If it is + * NOSTART and the previous message was NOSTOP, add its length. + */ + + if (msgs[i].flags & I2C_M_NOSTART && msgs[i - 1].flags & I2C_M_NOSTOP) + { + combined_size += msgs[i].length; + } + else + { + break; /* We've reached the end of the merge */ + } + } + + return combined_size; +} + /**************************************************************************** * Name: bcm2711_i2c_clearfifos * @@ -559,7 +628,7 @@ static void bcm2711_i2c_enable(struct bcm2711_i2cdev_s *priv) ****************************************************************************/ static size_t bcm2711_i2c_drainrxfifo(struct bcm2711_i2cdev_s *priv, - FAR uint8_t *buf, size_t n) + uint8_t *buf, size_t n) { uint8_t to_read = n < FIFO_DEPTH ? n : FIFO_DEPTH; uint8_t i = 0; @@ -587,16 +656,17 @@ static size_t bcm2711_i2c_drainrxfifo(struct bcm2711_i2cdev_s *priv, * * Input Parameters: * dev - The I2C interface to receive on. - * buf - The buffer to receive into - * n - The buffer size in bytes - * stop - Whether to send a stop condition at the end of the transfer. + * buf - The I2C messages list + * n - The total transfer size in bytes ****************************************************************************/ -static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, FAR void *buf, - size_t n) +static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, + struct i2c_msg_s *msgs, size_t n) { - size_t remaining = n; + size_t total_remaining = n; size_t bread; + size_t msg_remaining = msgs->length; + void *buf = msgs->buffer; int ret = 0; /* Start transfer. */ @@ -607,7 +677,7 @@ static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, FAR void *buf, * indicated as done. */ - while (remaining > 0 || !priv->done) + while (total_remaining > 0 || !priv->done) { /* Wait here for interrupt handler to signal that RX FIFO has data * (RXR). We can then continue reading. @@ -625,23 +695,38 @@ static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, FAR void *buf, /* Check if we are done and there's no data left to read. */ - if (priv->done && remaining == 0) + if (priv->done && total_remaining == 0) { break; /* Leave loop and return */ } - /* The remaining message length is the current remainder minus how far - * into the message we are. We also move forward the buffer pointer by - * how many bytes were just read so it starts at the correct location - * next iteration. - * - * We still have to read this if we received the "DONE" indicator but - * have the tail-end of the data in the RX FIFO. + /* Drain as much as possible from the FIFO into the respective messages */ - bread = bcm2711_i2c_drainrxfifo(priv, buf, remaining); - remaining -= bread; - buf += bread; + do + { + if (msg_remaining == 0) + { + msgs++; + msg_remaining = msgs->length; + buf = msgs->buffer; + } + + /* The remaining message length is the current remainder minus how + * far into the message we are. We also move forward the buffer + * pointer by how many bytes were just read so it starts at the + * correct location next iteration. + * + * We still have to read this if we received the "DONE" indicator + * but have the tail-end of the data in the RX FIFO. + */ + + bread = bcm2711_i2c_drainrxfifo(priv, buf, msg_remaining); + msg_remaining -= bread; + total_remaining -= bread; + buf += bread; + } + while (msg_remaining == 0 && total_remaining > 0); } priv->done = false; /* Reset done indicator */ @@ -664,7 +749,7 @@ static int bcm2711_i2c_receive(struct bcm2711_i2cdev_s *priv, FAR void *buf, ****************************************************************************/ static size_t bcm2711_i2c_filltxfifo(struct bcm2711_i2cdev_s *priv, - FAR uint8_t *buf, size_t n) + uint8_t *buf, size_t n) { uint8_t to_send = n < FIFO_DEPTH ? n : FIFO_DEPTH; uint8_t i = 0; @@ -691,30 +776,67 @@ static size_t bcm2711_i2c_filltxfifo(struct bcm2711_i2cdev_s *priv, * * Input Parameters: * dev - The I2C interface to send on. - * buf - The buffer to send data from. - * n - The size of the buffer in bytes. - * stop - Whether to send a stop condition at the end of the transfer. + * msgs - The I2C messages list + * n - The total transfer size in bytes ****************************************************************************/ -static int bcm2711_i2c_send(struct bcm2711_i2cdev_s *priv, FAR void *buf, - size_t n) +static int bcm2711_i2c_send(struct bcm2711_i2cdev_s *priv, + struct i2c_msg_s *msgs, size_t n) { - size_t remaining = n; + size_t total_remaining = n; + size_t msg_remaining; size_t bwrote; + void *buf; int ret = OK; - DEBUGASSERT(buf != NULL || (buf == NULL && n == 0)); + DEBUGASSERT(msgs != NULL || (msgs == NULL && n == 0)); - while (remaining > 0 || !priv->done) + /* Populate vars with first message information */ + + msg_remaining = msgs->length; + buf = msgs->buffer; + + while (total_remaining > 0 || !priv->done) { - /* Write data to FIFO. The remaining message length is the total - * remaining before, minus how far into the message we are. The `buf` - * pointer is incremented to point to data that hasn't been sent yet. + /* Fill the TX FIFO as much as possible across all message components. + * + * This always executes for the first message. + * + * On subsequent messages, we continue to fill the FIFO with their data + * until we run out of space in the FIFO or data to send. + * + * Then, we start the transfer. If we need to send more data, after + * receiving the TXW interrupt we return here to complete the same + * process of maximally filling the FIFO. Otherwise, the transfer is + * done and we exit. */ - bwrote = bcm2711_i2c_filltxfifo(priv, buf, remaining); - remaining -= bwrote; - buf += bwrote; + do + { + /* Acquire the length and buffer of the next message if this one is + * done. + */ + + if (msg_remaining == 0) + { + msgs++; + msg_remaining = msgs->length; + buf = msgs->buffer; + } + + /* Write data to FIFO. The remaining message length is the total + * remaining before, minus how far into the message we are. The + * `buf` pointer is incremented to point to data that hasn't been + * sent yet. We also increment the `total_remaining` size of the + * overall transfer (could be multiple messages). + */ + + bwrote = bcm2711_i2c_filltxfifo(priv, buf, msg_remaining); + msg_remaining -= bwrote; + total_remaining -= bwrote; + buf += bwrote; + } + while (msg_remaining == 0 && total_remaining > 0); /* Start the transfer if it's not running already */ @@ -756,7 +878,7 @@ static int bcm2711_i2c_send(struct bcm2711_i2cdev_s *priv, FAR void *buf, * failure. */ - DEBUGASSERT(remaining == 0); + DEBUGASSERT(total_remaining == 0); break; } } @@ -783,7 +905,7 @@ static int bcm2711_i2c_transfer(struct i2c_master_s *dev, struct bcm2711_i2cdev_s *priv = (struct bcm2711_i2cdev_s *)dev; int i; int ret; - bool stop = true; + size_t transfer_size; DEBUGASSERT(dev != NULL); DEBUGASSERT(msgs != NULL); @@ -809,22 +931,15 @@ static int bcm2711_i2c_transfer(struct i2c_master_s *dev, bcm2711_i2c_clearfifos(priv); bcm2711_i2c_setfrequency(priv, msgs->frequency); bcm2711_i2c_setaddr(priv, msgs->addr); - putreg32(msgs->length, BCM_BSC_DLEN(priv->base)); /* Set transfer len */ + + /* Try to merge as many sequential messages as possible to respect + * I2C_M_NOSTOP/I2C_M_NOSTART. + */ + + transfer_size = merge_messages(msgs, count); + putreg32(transfer_size, BCM_BSC_DLEN(priv->base)); /* Set transfer len */ bcm2711_i2c_enable(priv); - /* TODO: do I need to support I2C_M_NOSTART? */ - - /* TODO: Support restart condition (no stop) */ - - if (msgs->flags & I2C_M_NOSTOP) - { - stop = false; - } - else - { - stop = true; - } - /* Perform the operation corresponding to whether the user wanted to * send or receive on this transfer. */ @@ -832,12 +947,12 @@ static int bcm2711_i2c_transfer(struct i2c_master_s *dev, if (msgs->flags & I2C_M_READ) { modreg32(BCM_BSC_C_READ, BCM_BSC_C_READ, BCM_BSC_C(priv->base)); - ret = bcm2711_i2c_receive(priv, msgs->buffer, msgs->length); + ret = bcm2711_i2c_receive(priv, msgs, transfer_size); } else { modreg32(0, BCM_BSC_C_READ, BCM_BSC_C(priv->base)); - ret = bcm2711_i2c_send(priv, msgs->buffer, msgs->length); + ret = bcm2711_i2c_send(priv, msgs, transfer_size); } /* Check if there was an error during the send/receive operation and @@ -856,15 +971,7 @@ static int bcm2711_i2c_transfer(struct i2c_master_s *dev, } } - /* If our last message had a stop condition, we can safely disable this I2C - * interface until it's used again. - */ - - if (stop) - { - bcm2711_i2c_disable(priv); - } - + bcm2711_i2c_disable(priv); /* Transfer done */ nxmutex_unlock(&priv->lock); return ret; } @@ -1170,5 +1277,3 @@ int bcm2711_i2cbus_uninitialize(struct i2c_master_s *dev) nxmutex_unlock(&priv->lock); return ret; } - -#endif // defined(CONFIG_BCM2711_I2C) From ff509c1dca64fb7da3b6490cb92fd0b559488f61 Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sat, 20 Jun 2026 13:02:24 -0400 Subject: [PATCH 137/268] rpi4b/bringup: Use correct CONFIG option for I2C char driver Change the I2C character device registration to depend on the correct CONFIG option for enabling character drivers. Signed-off-by: Matteo Golin --- boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c b/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c index 8742d588047..4f2299d2aed 100644 --- a/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c +++ b/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c @@ -75,7 +75,7 @@ int rpi4b_bringup(void) /* Initialize I2C character drivers. */ -#if defined(CONFIG_BCM2711_I2C) +#if defined(CONFIG_BCM2711_I2C_DRIVER) #if defined(CONFIG_BCM2711_I2C0) ret = bcm2711_i2cdev_initialize(0); From 14b02bd6dcc3c2c9a2952f65463bb36b5aa85a7e Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sat, 20 Jun 2026 13:11:50 -0400 Subject: [PATCH 138/268] raspberrypi-4b/i2c: Added I2C configuration Includes a new I2C configuration (and documentation for it) to use the I2C1 bus on the Raspberry Pi 4B. Signed-off-by: Matteo Golin --- .../bcm2711/boards/raspberrypi-4b/index.rst | 9 +++ .../raspberrypi-4b/configs/i2c1/defconfig | 59 +++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig diff --git a/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst b/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst index 06594075912..8c8c2d3178b 100644 --- a/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst +++ b/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst @@ -221,6 +221,15 @@ This configuration boots directly into the :doc:`coremark ` benchmark and displays the results of the test over the serial console. +i2c1 +---- + +This configuration enables the I2C1 bus on GPIO 2 and 3 (the standard I2C bus +for the Raspberry Pi 4B). It includes the :doc:`i2ctool +` application for playing with the bus. Note +that you will want to pass the `-b 1` flag to the tool the first time you use +it, as the default bus is 0. + ostest ------ diff --git a/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig b/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig new file mode 100644 index 00000000000..a60387663b2 --- /dev/null +++ b/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_ARCH="arm64" +CONFIG_ARCH_ARM64=y +CONFIG_ARCH_BOARD="raspberrypi-4b" +CONFIG_ARCH_BOARD_RASPBERRYPI_4B=y +CONFIG_ARCH_CHIP="bcm2711" +CONFIG_ARCH_CHIP_BCM2711=y +CONFIG_ARCH_EARLY_PRINT=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BCM2711_I2C1=y +CONFIG_BCM2711_I2C=y +CONFIG_BCM2711_I2C_DRIVER=y +CONFIG_BOARD_LOOPSPERMSEC=132954 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_MIN=8192 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=4227858432 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2022 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USERLED=y From cb892dd434e0e693862a97010574fb2517add47f Mon Sep 17 00:00:00 2001 From: Matteo Golin Date: Sat, 20 Jun 2026 13:24:32 -0400 Subject: [PATCH 139/268] raspberrypi-4b/bmp280: Include optional registration of BMP280 driver This commit includes BMP280 driver registration on I2C1 in the RPi4B bringup logic _if_ the user selects the board-level configuration option (so as to not interfere with any user's custom implementation of interfacing with this sensor). A configuration is added with the BMP280 registration, example program and `uorb_listener` that is also documented. Signed-off-by: Matteo Golin --- .../bcm2711/boards/raspberrypi-4b/index.rst | 8 +++ boards/arm64/bcm2711/raspberrypi-4b/Kconfig | 8 +++ .../raspberrypi-4b/configs/bmp280/defconfig | 67 +++++++++++++++++++ .../raspberrypi-4b/configs/i2c1/defconfig | 8 +++ .../raspberrypi-4b/src/rpi4b_bringup.c | 21 +++++- 5 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 boards/arm64/bcm2711/raspberrypi-4b/configs/bmp280/defconfig diff --git a/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst b/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst index 8c8c2d3178b..cbe8c809155 100644 --- a/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst +++ b/Documentation/platforms/arm64/bcm2711/boards/raspberrypi-4b/index.rst @@ -230,6 +230,14 @@ for the Raspberry Pi 4B). It includes the :doc:`i2ctool that you will want to pass the `-b 1` flag to the tool the first time you use it, as the default bus is 0. +bmp280 +------ + +This configuration is the same as the I2C1 configuration, but it registers the +BMP280 device driver on I2C1. You can use the :doc:`bmp280 +` example program or the ``uorb_listener`` +program to interact with the sensor. + ostest ------ diff --git a/boards/arm64/bcm2711/raspberrypi-4b/Kconfig b/boards/arm64/bcm2711/raspberrypi-4b/Kconfig index a20867c9f7b..6628e835924 100644 --- a/boards/arm64/bcm2711/raspberrypi-4b/Kconfig +++ b/boards/arm64/bcm2711/raspberrypi-4b/Kconfig @@ -60,4 +60,12 @@ config RPI4B_FRAMEBUFFER ---help--- Registers a frame buffer character driver for graphical output. +config RPI4B_BMP280 + bool "BMP280 driver registration" + default n + depends on BCM2711_I2C1 + depends on SENSORS_BMP280 + ---help--- + Registers the driver for the BMP280 sensor on I2C1 for experimenting. + endif # ARCH_BOARD_RASPBERRYPI_4B diff --git a/boards/arm64/bcm2711/raspberrypi-4b/configs/bmp280/defconfig b/boards/arm64/bcm2711/raspberrypi-4b/configs/bmp280/defconfig new file mode 100644 index 00000000000..62bbe39bc8d --- /dev/null +++ b/boards/arm64/bcm2711/raspberrypi-4b/configs/bmp280/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_ARCH="arm64" +CONFIG_ARCH_ARM64=y +CONFIG_ARCH_BOARD="raspberrypi-4b" +CONFIG_ARCH_BOARD_RASPBERRYPI_4B=y +CONFIG_ARCH_CHIP="bcm2711" +CONFIG_ARCH_CHIP_BCM2711=y +CONFIG_ARCH_EARLY_PRINT=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQPRIO=y +CONFIG_BCM2711_I2C1=y +CONFIG_BCM2711_I2C=y +CONFIG_BCM2711_I2C_DRIVER=y +CONFIG_BMP280_I2C_ADDR_77=y +CONFIG_BOARD_LOOPSPERMSEC=132954 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_EXAMPLES_BMP280=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_MIN=8192 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=4227858432 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RPI4B_BMP280=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP280=y +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2022 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UORB=y +CONFIG_UORB_LISTENER=y +CONFIG_USEC_PER_TICK=1000 +CONFIG_USENSOR=y +CONFIG_USERLED=y diff --git a/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig b/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig index a60387663b2..62bbe39bc8d 100644 --- a/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig +++ b/boards/arm64/bcm2711/raspberrypi-4b/configs/i2c1/defconfig @@ -18,11 +18,13 @@ CONFIG_ARCH_IRQPRIO=y CONFIG_BCM2711_I2C1=y CONFIG_BCM2711_I2C=y CONFIG_BCM2711_I2C_DRIVER=y +CONFIG_BMP280_I2C_ADDR_77=y CONFIG_BOARD_LOOPSPERMSEC=132954 CONFIG_BUILTIN=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_EXAMPLES_BMP280=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y @@ -42,9 +44,12 @@ CONFIG_RAM_SIZE=4227858432 CONFIG_RAM_START=0x00000000 CONFIG_RAW_BINARY=y CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RPI4B_BMP280=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP280=y CONFIG_SPINLOCK=y CONFIG_STACK_COLORATION=y CONFIG_START_MONTH=11 @@ -55,5 +60,8 @@ CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_SYSTEM=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y +CONFIG_UORB=y +CONFIG_UORB_LISTENER=y CONFIG_USEC_PER_TICK=1000 +CONFIG_USENSOR=y CONFIG_USERLED=y diff --git a/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c b/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c index 4f2299d2aed..98097cb031a 100644 --- a/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c +++ b/boards/arm64/bcm2711/raspberrypi-4b/src/rpi4b_bringup.c @@ -45,6 +45,11 @@ #include #endif +#ifdef CONFIG_RPI4B_BMP280 +#include +#include "bcm2711_i2c.h" +#endif + #include "rpi4b.h" /**************************************************************************** @@ -71,7 +76,7 @@ int rpi4b_bringup(void) { syslog(LOG_ERR, "Failed to initialize GPIO driver: %d\n.", ret); } -#endif // defined(CONFIG_DEV_GPIO) +#endif /* defined(CONFIG_DEV_GPIO) */ /* Initialize I2C character drivers. */ @@ -155,5 +160,19 @@ int rpi4b_bringup(void) } #endif +#ifdef CONFIG_RPI4B_BMP280 + struct i2c_master_s *i2c1 = bcm2711_i2cbus_initialize(1); + if (i2c1 == NULL) + { + syslog(LOG_ERR, "Couldn't register I2C1.\n"); + } + + ret = bmp280_register(0, i2c1); /* Devno = 0 */ + if (ret < 0) + { + syslog(LOG_ERR, "Couldn't register BMP280: %d\n", ret); + } +#endif + return ret; } From 1685e8ff7b86a4322153b65b7c56f3f8978ca077 Mon Sep 17 00:00:00 2001 From: Michal Lenc Date: Tue, 23 Jun 2026 09:28:41 +0200 Subject: [PATCH 140/268] syslog: avoid an infinite loop if one channel fails The current implementation exits syslog_write_foreach function if write to one channel fails, causing other channels not being written and returning negated errno. libc syslog functions then stay in an infinite loop, because error is returned and the same bytes are still passed to syslograwstream_flush and syslog_write_foreach. The channel write may fail for many reasons - disconnected USB if CDC ACM syslog is enabled, lost networking if telnet syslog is enabled, error on NOR flash etc. This shouldn't lead to an ininite loop in the code though. The solution ensures all channels in syslog_write_foreach are tried, therefore the user get the output to the working channels even if the first one is broken. It also updates syslograwstream_addchar and syslograwstream_addstring to skip the bytes if all channels fails. This ensures syslog call won't result in an infinite loop, but the user may lost the debugging output. Co-authored-by: Martin Krasula Signed-off-by: Michal Lenc --- drivers/syslog/syslog_write.c | 6 +++--- libs/libc/stream/lib_syslograwstream.c | 16 +++++++++++++--- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/syslog/syslog_write.c b/drivers/syslog/syslog_write.c index 8b3fefda709..94e6c0d330e 100644 --- a/drivers/syslog/syslog_write.c +++ b/drivers/syslog/syslog_write.c @@ -107,7 +107,7 @@ ssize_t syslog_write_foreach(FAR const char *buffer, syslog_write_t write; syslog_putc_t putc; size_t nwritten = 0; - size_t nwritten_max = 0; + ssize_t nwritten_max = -EIO; ssize_t ret; int i; @@ -153,7 +153,7 @@ ssize_t syslog_write_foreach(FAR const char *buffer, if (ret < 0) { - return ret; + continue; } nwritten = head + 1; @@ -166,7 +166,7 @@ ssize_t syslog_write_foreach(FAR const char *buffer, ret = write(channel, buffer + nwritten, buflen - nwritten); if (ret < 0) { - return ret; + continue; } else { diff --git a/libs/libc/stream/lib_syslograwstream.c b/libs/libc/stream/lib_syslograwstream.c index 76b149f1d3a..270205f83a4 100644 --- a/libs/libc/stream/lib_syslograwstream.c +++ b/libs/libc/stream/lib_syslograwstream.c @@ -123,7 +123,12 @@ static void syslograwstream_addchar(FAR struct lib_syslograwstream_s *stream, /* Yes.. then flush the buffer */ - syslograwstream_flush(&stream->common); + int ret = syslograwstream_flush(&stream->common); + if (ret < 0) + { + stream->offset = 0; + stream->common.nput = 0; + } } } @@ -136,7 +141,6 @@ syslograwstream_addstring(FAR struct lib_syslograwstream_s *stream, FAR const char *buff, size_t len) { ssize_t ret = 0; - do { size_t remain = CONFIG_SYSLOG_BUFSIZE - stream->offset; @@ -155,7 +159,13 @@ syslograwstream_addstring(FAR struct lib_syslograwstream_s *stream, /* Yes.. then flush the buffer */ - syslograwstream_flush(&stream->common); + int ret_flush = syslograwstream_flush(&stream->common); + if (ret_flush < 0) + { + stream->offset = 0; + stream->common.nput = 0; + break; + } } } while (ret < len); From a9b72ed796c515a1532c36ebccafb6f29978f248 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 21 Jun 2026 01:55:08 +0800 Subject: [PATCH 141/268] libc/grp: add getgrouplist() Add getgrouplist() to the C library. It scans the group database for a user's supplementary groups and always reports the primary group first. Without CONFIG_LIBC_GROUP_FILE only the primary group is returned, since no membership information is available. The group file is read through lib_get_tempbuffer()/lib_put_tempbuffer() to avoid a heap allocation on every lookup. Signed-off-by: Xiang Xiao --- include/grp.h | 2 + libs/libc/grp/CMakeLists.txt | 2 +- libs/libc/grp/Make.defs | 2 +- libs/libc/grp/lib_find_grpfile.c | 122 +++++++++++++++++++++++++++++++ libs/libc/grp/lib_getgrouplist.c | 95 ++++++++++++++++++++++++ libs/libc/grp/lib_grp.h | 2 + 6 files changed, 223 insertions(+), 2 deletions(-) create mode 100644 libs/libc/grp/lib_getgrouplist.c diff --git a/include/grp.h b/include/grp.h index d6297649eaf..1c4f215e54f 100644 --- a/include/grp.h +++ b/include/grp.h @@ -72,6 +72,8 @@ int getgrgid_r(gid_t gid, FAR struct group *grp, FAR char *buf, size_t buflen, FAR struct group **result); int initgroups(FAR const char *user, gid_t group); +int getgrouplist(FAR const char *user, gid_t group, FAR gid_t *groups, + FAR int *ngroups); #undef EXTERN #if defined(__cplusplus) diff --git a/libs/libc/grp/CMakeLists.txt b/libs/libc/grp/CMakeLists.txt index 83312f9b56f..62d98a9056a 100644 --- a/libs/libc/grp/CMakeLists.txt +++ b/libs/libc/grp/CMakeLists.txt @@ -20,7 +20,7 @@ # # ############################################################################## set(SRCS lib_getgrgid.c lib_getgrgidr.c lib_getgrnam.c lib_getgrnamr.c - lib_initgroups.c) + lib_initgroups.c lib_getgrouplist.c) if(CONFIG_LIBC_GROUP_FILE) list(APPEND SRCS lib_find_grpfile.c lib_grp_globals.c) diff --git a/libs/libc/grp/Make.defs b/libs/libc/grp/Make.defs index 7680a6f2ba0..2fe4e37fc05 100644 --- a/libs/libc/grp/Make.defs +++ b/libs/libc/grp/Make.defs @@ -23,7 +23,7 @@ # Add the grp C files to the build CSRCS += lib_getgrgid.c lib_getgrgidr.c lib_getgrnam.c lib_getgrnamr.c -CSRCS += lib_initgroups.c +CSRCS += lib_initgroups.c lib_getgrouplist.c ifeq ($(CONFIG_LIBC_GROUP_FILE),y) CSRCS += lib_find_grpfile.c lib_grp_globals.c diff --git a/libs/libc/grp/lib_find_grpfile.c b/libs/libc/grp/lib_find_grpfile.c index d0b90ca83a1..98c4cc48150 100644 --- a/libs/libc/grp/lib_find_grpfile.c +++ b/libs/libc/grp/lib_find_grpfile.c @@ -31,6 +31,9 @@ #include #include #include +#include + +#include #include "grp/lib_grp.h" @@ -41,6 +44,19 @@ typedef CODE int (grp_foreach_match_t)(FAR const struct group *entry, uintptr_t arg); +/* Context used by grp_match_user() to accumulate the group IDs of all the + * groups that a given user is a member of. + */ + +struct grp_user_s +{ + FAR const char *user; /* User name to search for */ + gid_t group; /* Primary group to skip (avoid duplicate) */ + FAR gid_t *grouplist; /* Output array of group IDs */ + int maxgroups; /* Number of slots in grouplist */ + int count; /* Number of group IDs found so far */ +}; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -93,6 +109,61 @@ static int grp_match_gid(FAR const struct group *entry, uintptr_t arg) return match_gid == entry->gr_gid ? 1 : 0; } +/**************************************************************************** + * Name: grp_match_user + * + * Description: + * Called for each record in the group file. If the user (passed via the + * context in arg) is a member of the group, its group ID is appended to + * the caller's output array. Always returns 0 so that every record in + * the file is visited and the total number of matching groups is counted. + * + * Input Parameters: + * entry - The parsed group file record + * arg - A pointer to the grp_user_s search context + * + * Returned Value: + * = 0 : Always, so that iteration continues to the end of the file. + * + ****************************************************************************/ + +static int grp_match_user(FAR const struct group *entry, uintptr_t arg) +{ + FAR struct grp_user_s *ctx = (FAR struct grp_user_s *)arg; + FAR char **member; + + /* The primary group has already been accounted for by the caller. Skip + * it here to avoid reporting it twice. + */ + + if (entry->gr_gid == ctx->group) + { + return 0; + } + + /* Check whether the user is listed as a member of this group. */ + + for (member = entry->gr_mem; *member != NULL; member++) + { + if (strcmp(*member, ctx->user) == 0) + { + /* Append the group ID if there is room in the output array. Keep + * counting regardless so the caller learns the required size. + */ + + if (ctx->count < ctx->maxgroups) + { + ctx->grouplist[ctx->count] = entry->gr_gid; + } + + ctx->count++; + break; + } + } + + return 0; +} + /**************************************************************************** * Name: grp_foreach * @@ -337,3 +408,54 @@ int grp_findby_gid(gid_t gid, FAR struct group *entry, FAR char *buffer, return grp_foreach(grp_match_gid, (uintptr_t)gid, entry, buffer, buflen); } + +/**************************************************************************** + * Name: grp_findby_user + * + * Description: + * Scan the group file and collect the group IDs of all groups that have + * 'user' as a member, excluding the primary group 'group'. + * + * Input Parameters: + * user - The user name to search for + * group - The primary group ID to exclude from the search + * grouplist - Location to return the matching group IDs + * maxgroups - The number of slots available in grouplist + * count - On input, the number of group IDs already stored in + * grouplist. On output, the total number of group IDs found + * (which may exceed maxgroups). + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int grp_findby_user(FAR const char *user, gid_t group, + FAR gid_t *grouplist, int maxgroups, FAR int *count) +{ + struct grp_user_s ctx; + struct group entry; + FAR char *buffer; + int ret; + + buffer = lib_get_tempbuffer(GRPBUF_RESERVE_SIZE); + if (buffer == NULL) + { + return -ENOMEM; + } + + ctx.user = user; + ctx.group = group; + ctx.grouplist = grouplist; + ctx.maxgroups = maxgroups; + ctx.count = *count; + + ret = grp_foreach(grp_match_user, (uintptr_t)&ctx, &entry, buffer, + GRPBUF_RESERVE_SIZE); + + *count = ctx.count; + lib_put_tempbuffer(buffer); + + return ret < 0 ? ret : 0; +} diff --git a/libs/libc/grp/lib_getgrouplist.c b/libs/libc/grp/lib_getgrouplist.c new file mode 100644 index 00000000000..a497434cdb1 --- /dev/null +++ b/libs/libc/grp/lib_getgrouplist.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * libs/libc/grp/lib_getgrouplist.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "grp/lib_grp.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: getgrouplist + * + * Description: + * The getgrouplist() function scans the group database to obtain the list + * of groups that 'user' belongs to. The group 'group' (typically the + * primary group ID from the password database) is always included in the + * returned list and is stored as the first element. + * + * Input Parameters: + * user - The user name whose group membership is queried. + * group - An additional group ID (the primary group) to include. + * groups - Location to return the list of group IDs. + * ngroups - On input, the number of slots available in groups. On output, + * the actual number of group IDs found. + * + * Returned Value: + * On success, the number of group IDs found is returned. If the number of + * groups exceeds the available space, -1 is returned and ngroups is set to + * the number of group IDs that would have been returned. + * + ****************************************************************************/ + +int getgrouplist(FAR const char *user, gid_t group, FAR gid_t *groups, + FAR int *ngroups) +{ + int maxgroups = *ngroups; + int count; + + /* The primary group is always reported first. */ + + if (maxgroups > 0) + { + groups[0] = group; + } + + count = 1; + +#ifdef CONFIG_LIBC_GROUP_FILE + /* Scan the group file for any supplementary groups that 'user' belongs to + * and append their group IDs to the list. + */ + + grp_findby_user(user, group, groups, maxgroups, &count); +#else + /* Without a group file there is no membership information, so only the + * primary group is reported. + */ + + UNUSED(user); +#endif + + /* If the caller's buffer was too small, report the required size and + * return failure. Otherwise, return the number of group IDs stored. + */ + + *ngroups = count; + return count > maxgroups ? -1 : count; +} diff --git a/libs/libc/grp/lib_grp.h b/libs/libc/grp/lib_grp.h index a7dbf0efb05..0d84dd39652 100644 --- a/libs/libc/grp/lib_grp.h +++ b/libs/libc/grp/lib_grp.h @@ -83,6 +83,8 @@ int grp_findby_name(FAR const char *gname, FAR struct group *entry, FAR char *buffer, size_t buflen); int grp_findby_gid(gid_t gid, FAR struct group *entry, FAR char *buffer, size_t buflen); +int grp_findby_user(FAR const char *user, gid_t group, + FAR gid_t *grouplist, int maxgroups, FAR int *count); #endif #undef EXTERN From b2ffa3e15e8d7f15b35b84be53c70e1a859bb448 Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 22 Jun 2026 02:52:31 +0000 Subject: [PATCH 142/268] build(deps): bump actions/checkout from 5 to 7 Bumps [actions/checkout](https://github.com/actions/checkout) from 5 to 7. - [Release notes](https://github.com/actions/checkout/releases) - [Commits](https://github.com/actions/checkout/compare/v5...v7) --- updated-dependencies: - dependency-name: actions/checkout dependency-version: '7' dependency-type: direct:production update-type: version-update:semver-major ... Signed-off-by: dependabot[bot] --- .github/workflows/build.yml | 8 ++++---- .github/workflows/check.yml | 2 +- .github/workflows/doc.yml | 2 +- .github/workflows/docker_linux.yml | 2 +- .github/workflows/labeler.yml | 2 +- .github/workflows/lint.yml | 2 +- .github/workflows/membrowse-comment.yml | 2 +- .github/workflows/membrowse-onboard.yml | 4 ++-- .github/workflows/membrowse-report.yml | 10 +++++----- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index dd54ff06116..6f114818b72 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -95,7 +95,7 @@ jobs: echo "apps_ref=$APPS_REF" >> $GITHUB_OUTPUT - name: Checkout nuttx repo - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: repository: apache/nuttx ref: ${{ steps.gittargets.outputs.os_ref }} @@ -105,7 +105,7 @@ jobs: run: git -C sources/nuttx fetch --tags - name: Checkout apps repo - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: repository: apache/nuttx-apps ref: ${{ steps.gittargets.outputs.apps_ref }} @@ -379,7 +379,7 @@ jobs: run: shell: msys2 {0} steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: msys2/setup-msys2@v2 with: msystem: MSYS @@ -453,7 +453,7 @@ jobs: if: ${{ needs.msvc-Arch.outputs.skip_all_builds != '1' }} runs-on: windows-2022 steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 # Set up Python environment and install kconfiglib - name: Set up Python and install kconfiglib uses: actions/setup-python@v6 diff --git a/.github/workflows/check.yml b/.github/workflows/check.yml index 422fc7927af..160212f4de7 100644 --- a/.github/workflows/check.yml +++ b/.github/workflows/check.yml @@ -30,7 +30,7 @@ jobs: steps: - name: Checkout nuttx repo - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: repository: apache/nuttx path: nuttx diff --git a/.github/workflows/doc.yml b/.github/workflows/doc.yml index f6c4e3a670f..c1678a7d9cc 100644 --- a/.github/workflows/doc.yml +++ b/.github/workflows/doc.yml @@ -35,7 +35,7 @@ jobs: build-html: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - uses: actions/setup-python@v6 with: python-version: '3.10' diff --git a/.github/workflows/docker_linux.yml b/.github/workflows/docker_linux.yml index 57cd8e0cff8..8d1d08824d7 100644 --- a/.github/workflows/docker_linux.yml +++ b/.github/workflows/docker_linux.yml @@ -47,7 +47,7 @@ jobs: IMAGE_TAG: ghcr.io/${{ github.repository }}/apache-nuttx-ci-linux steps: - name: Checkout repository - uses: actions/checkout@v6 + uses: actions/checkout@v7 - name: Free Disk Space (Ubuntu) uses: ./.github/actions/free-disk-space diff --git a/.github/workflows/labeler.yml b/.github/workflows/labeler.yml index 6db0312de47..7fb8bc2d97c 100644 --- a/.github/workflows/labeler.yml +++ b/.github/workflows/labeler.yml @@ -33,7 +33,7 @@ jobs: # Checkout one file from our trusted source: .github/labeler.yml # Never checkout and execute any untrusted code from the PR. - name: Checkout labeler config - uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd # v6.0.2 + uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0 # v7.0.0 with: repository: apache/nuttx ref: master diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index fbebfdc0af0..9a82b03625b 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -17,7 +17,7 @@ jobs: name: Lint runs-on: ubuntu-latest steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: fetch-depth: 0 - run: mkdir super-linter.report diff --git a/.github/workflows/membrowse-comment.yml b/.github/workflows/membrowse-comment.yml index 05a578a533c..9fa6ae1ff38 100644 --- a/.github/workflows/membrowse-comment.yml +++ b/.github/workflows/membrowse-comment.yml @@ -17,7 +17,7 @@ jobs: pull-requests: write steps: - name: Checkout repository - uses: actions/checkout@v5 + uses: actions/checkout@v7 - uses: actions/setup-python@v6 with: diff --git a/.github/workflows/membrowse-onboard.yml b/.github/workflows/membrowse-onboard.yml index 3ae7af7c421..139c42389a6 100644 --- a/.github/workflows/membrowse-onboard.yml +++ b/.github/workflows/membrowse-onboard.yml @@ -15,7 +15,7 @@ jobs: outputs: matrix: ${{ steps.set-matrix.outputs.matrix }} steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - id: set-matrix run: echo "matrix=$(jq -c '.' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT @@ -34,7 +34,7 @@ jobs: steps: - name: Checkout nuttx - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: fetch-depth: 0 diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml index a4ac3022f0c..c18c050a148 100644 --- a/.github/workflows/membrowse-report.yml +++ b/.github/workflows/membrowse-report.yml @@ -25,7 +25,7 @@ jobs: steps: # Shallow checkout; the base commit needed for the diff is fetched # explicitly below instead of cloning the repo's full history. - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: fetch-depth: 2 # Detect whether any non-doc/CODEOWNERS source files changed. @@ -75,7 +75,7 @@ jobs: outputs: matrix: ${{ steps.set-matrix.outputs.matrix }} steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 - id: set-matrix run: echo "matrix=$(jq -c '.' .github/membrowse-targets.json)" >> $GITHUB_OUTPUT @@ -91,7 +91,7 @@ jobs: matrix: include: ${{ fromJson(needs.load-targets.outputs.matrix) }} steps: - - uses: actions/checkout@v6 + - uses: actions/checkout@v7 with: fetch-depth: 2 - uses: actions/setup-python@v6 @@ -136,13 +136,13 @@ jobs: include: ${{ fromJson(needs.load-targets.outputs.matrix) }} steps: - name: Checkout nuttx repo - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: path: sources/nuttx fetch-depth: 2 - name: Checkout nuttx-apps repo - uses: actions/checkout@v6 + uses: actions/checkout@v7 with: repository: apache/nuttx-apps path: sources/apps From 970f2f226ad6c5893be8b42cd7af9da43cb81263 Mon Sep 17 00:00:00 2001 From: Brunocor26 Date: Tue, 23 Jun 2026 11:52:37 +0100 Subject: [PATCH 143/268] arch/risc-v/rp23xx-rv: Fix PWM frequency and duty cycle calculation. Fixed three bugs in the RP23XX (RISC-V) PWM driver, mirroring the fix previously applied to the ARM variant: * setup_period: The previous divisor calculation used integer arithmetic that caused overflow and loss of precision. The divider is now computed as a 16-bit fixed-point value (div16) using 64-bit arithmetic, and clamped to the valid hardware range (0x10 to 0xFFF). * setup_pulse: The compare value was incorrectly scaled by TOP instead of 65535, producing wrong duty cycles. The formula is now corrected to ((duty * (top + 1)) / 65535) with an overflow guard. * pwm_start: The driver was not updated as part of the breaking change introduced in commit 4df80e19 ("!drivers/pwm: remove PWM_MULTICHAN option"). Access to single channel API is now info->channels[0].duty instead of info[0].duty. Signed-off-by: Brunocor26 --- arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c | 124 +++++++++++++++++-------- 1 file changed, 87 insertions(+), 37 deletions(-) diff --git a/arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c b/arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c index 53ec6629303..8632dd951d0 100644 --- a/arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c +++ b/arch/risc-v/src/rp23xx-rv/rp23xx_pwm.c @@ -359,9 +359,9 @@ int pwm_start(struct pwm_lowerhalf_s * dev, } } #else - if (priv->duty != info[0].duty) + if (priv->duty != info->channels[0].duty) { - priv->duty = info[0].duty; + priv->duty = info->channels[0].duty; } #endif @@ -465,51 +465,77 @@ int pwm_ioctl(struct pwm_lowerhalf_s * dev, * ****************************************************************************/ -void setup_period(struct rp23xx_pwm_lowerhalf_s * priv) +void setup_period(struct rp23xx_pwm_lowerhalf_s *priv) { irqstate_t flags; - uint32_t max_freq = BOARD_SYS_FREQ / 0x10000; /* initially, with full range count */ uint32_t frequency = priv->frequency; + uint32_t top; + uint32_t div16; - /* If we are running phase correct we double the frequency value - * since the PWM will generate a pulse chain at half what it - * would be in normal (non-phase correct) mode - */ + /* Phase-correct mode halves output frequency */ if (priv->flags & RP23XX_RV_PWM_CSR_PH_CORRECT) { frequency *= 2; } - pwminfo("PWM%d freq %ld max %ld\n", priv->num, priv->frequency, max_freq); + /* Try to keep maximum resolution first */ - if (frequency <= max_freq) + top = 0xffff; + + /* Divider is 8.4 fixed-point: + * + * div16 = divider * 16 + * + * PWM frequency: + * + * f_pwm = clk_sys / (divider * (TOP + 1)) + * + * therefore: + * + * div16 = (16 * clk_sys) / (f_pwm * (TOP + 1)) + */ + + div16 = (16ULL * BOARD_SYS_FREQ) / + ((uint64_t)frequency * (top + 1)); + + /* Divider must be in valid hardware range: + * 1.0 -> 255.9375 + * represented as: + * 0x10 -> 0xFFF + */ + + if (div16 < 0x10) { - /* We can keep full range count and slow clock down with divisor */ + /* Divider too small: + * reduce TOP to increase frequency + */ - priv->top = 0xffff; + div16 = 0x10; + top = (BOARD_SYS_FREQ / + ((div16 / 16.0) * frequency)) - 1; + if (top > 0xffff) + { + top = 0xffff; + } } - else + else if (div16 > 0xfff) { - /* we need to speed things up by reducing top */ - - priv->top = 0xffff / (frequency / max_freq); - - /* compute new maximum frequency */ - - max_freq = BOARD_SYS_FREQ / (priv->top + 1); + div16 = 0xfff; } - priv->divisor = 16 * max_freq / frequency; + priv->top = top; + priv->divisor = div16; - pwminfo("PWM%d top 0x%08X div 0x%08lX\n", - priv->num, - priv->top, - priv->divisor); + pwminfo("PWM%d freq=%lu top=%lu div=%lu\n", + priv->num, + priv->frequency, + priv->top, + priv->divisor); flags = enter_critical_section(); - putreg32(priv->top, RP23XX_RV_PWM_TOP(priv->num)); + putreg32(priv->top, RP23XX_RV_PWM_TOP(priv->num)); putreg32(priv->divisor, RP23XX_RV_PWM_DIV(priv->num)); leave_critical_section(flags); @@ -526,19 +552,43 @@ void setup_period(struct rp23xx_pwm_lowerhalf_s * priv) * ****************************************************************************/ -void setup_pulse(struct rp23xx_pwm_lowerhalf_s * priv) +void setup_pulse(struct rp23xx_pwm_lowerhalf_s *priv) { irqstate_t flags; #if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS == 2 - uint32_t compare = - (0xffff * (uint32_t)priv->duty[0] / priv->top) - + ((0xffff * (uint32_t)priv->duty[1] / priv->top) << 16); + + uint32_t level_a = + ((uint64_t)priv->duty[0] * (priv->top + 1)) / 65535; + + uint32_t level_b = + ((uint64_t)priv->duty[1] * (priv->top + 1)) / 65535; + + if (level_a > priv->top) + { + level_a = priv->top; + } + + if (level_b > priv->top) + { + level_b = priv->top; + } + + uint32_t compare = level_a | (level_b << 16); + #else - uint32_t compare = 0xffff * (uint32_t)priv->duty / priv->top; + + uint32_t compare = + ((uint64_t)priv->duty * (priv->top + 1)) / 65535; + + if (compare > priv->top) + { + compare = priv->top; + } + #endif - pwminfo("PWM%d compare 0x%08lX flags 0x%08lX\n", + pwminfo("PWM%d compare=0x%08lx flags=0x%08lx\n", priv->num, compare, priv->flags); @@ -548,11 +598,11 @@ void setup_pulse(struct rp23xx_pwm_lowerhalf_s * priv) putreg32(compare, RP23XX_RV_PWM_CC(priv->num)); modreg32(priv->flags, - RP23XX_RV_PWM_CSR_DIVMODE_MASK - | RP23XX_RV_PWM_CSR_B_INV - | RP23XX_RV_PWM_CSR_A_INV - | RP23XX_RV_PWM_CSR_PH_CORRECT, - RP23XX_RV_PWM_CSR(priv->num)); + RP23XX_RV_PWM_CSR_DIVMODE_MASK | + RP23XX_RV_PWM_CSR_B_INV | + RP23XX_RV_PWM_CSR_A_INV | + RP23XX_RV_PWM_CSR_PH_CORRECT, + RP23XX_RV_PWM_CSR(priv->num)); leave_critical_section(flags); } From 95063bde1571673eafeb7fecef132474d24ce68a Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 21 Jun 2026 10:38:30 +0800 Subject: [PATCH 144/268] drivers/serial: add job-control TTY ioctls and libc wrappers NuttX has no real session/process-group abstraction, so the TTY layer collapses the foreground process group onto the single dev->pid field (pgrp == pid, one member per group). Extend the controlling-terminal support so portable software (e.g. dropbear, socat) that relies on job-control primitives works without losing the existing NuttX-specific behaviour. Driver (serial.c, pty.c): - TIOCSCTTY now accepts a flag: arg > 0 keeps the historical "target PID in arg" semantics (NSH registers the foreground command it just spawned), while arg == 0 selects the calling task via nxsched_getpid(), matching the POSIX flag convention used by dropbear/socat/apue. This preserves all existing callers and makes the previously-dead arg==0 path deliver SIGINT correctly. - Add TIOCGPGRP/TIOCGSID (return dev->pid) and TIOCSPGRP (set it). - pty.c gains the same handlers against pd_pid and includes nuttx/sched.h for nxsched_getpid(). ioctl numbers (tioctl.h): TIOCGPGRP/TIOCSPGRP/TIOCGSID at 0x37-0x39. libc wrappers: - termios: tcgetpgrp(), tcsetpgrp(), tcgetsid() over the new ioctls. - unistd: setsid()/getsid()/setpgid() stubs consistent with the existing getpgrp()/getpgid() single-session model (sid == pgid == pid; setpgid only succeeds for pgid == pid). Declare the new prototypes in unistd.h (tcgetsid was already in termios.h) and register all sources in the Make.defs/CMakeLists. Group-broadcast signalling (kill(-pgrp)) remains unsupported, so tty signals still target the single dev->pid; a real session/process group model is left as a follow-up. Signed-off-by: Xiang Xiao --- .../components/drivers/character/serial.rst | 28 ++++++ drivers/serial/pty.c | 29 ++++++- drivers/serial/serial.c | 35 +++++++- include/nuttx/serial/serial.h | 5 +- include/nuttx/serial/tioctl.h | 8 +- include/unistd.h | 5 ++ libs/libc/termios/CMakeLists.txt | 5 +- libs/libc/termios/Make.defs | 1 + libs/libc/termios/lib_tcgetpgrp.c | 67 ++++++++++++++ libs/libc/termios/lib_tcgetsid.c | 67 ++++++++++++++ libs/libc/termios/lib_tcsetpgrp.c | 59 +++++++++++++ libs/libc/unistd/CMakeLists.txt | 3 + libs/libc/unistd/Make.defs | 1 + libs/libc/unistd/lib_getsid.c | 75 ++++++++++++++++ libs/libc/unistd/lib_setpgid.c | 87 +++++++++++++++++++ libs/libc/unistd/lib_setsid.c | 57 ++++++++++++ 16 files changed, 523 insertions(+), 9 deletions(-) create mode 100644 libs/libc/termios/lib_tcgetpgrp.c create mode 100644 libs/libc/termios/lib_tcgetsid.c create mode 100644 libs/libc/termios/lib_tcsetpgrp.c create mode 100644 libs/libc/unistd/lib_getsid.c create mode 100644 libs/libc/unistd/lib_setpgid.c create mode 100644 libs/libc/unistd/lib_setsid.c diff --git a/Documentation/components/drivers/character/serial.rst b/Documentation/components/drivers/character/serial.rst index 7af619f1270..3b80938ba7c 100644 --- a/Documentation/components/drivers/character/serial.rst +++ b/Documentation/components/drivers/character/serial.rst @@ -35,6 +35,34 @@ Serial Device Drivers Also, you can customize: ``TTY_LAUNCH_ARGS`` ``TTY_LAUNCH_PRIORITY`` ``TTY_LAUNCH_STACKSIZE`` +- **Job control / controlling terminal**. When ``CONFIG_TTY_SIGINT`` + or ``CONFIG_TTY_SIGTSTP`` is enabled, the TTY layer can generate + ``SIGINT`` (Ctrl-C) and ``SIGTSTP`` (Ctrl-Z) for a foreground task. + NuttX does not implement POSIX sessions or process groups, so the + foreground process group is collapsed onto a single PID stored in + the driver (``pgrp == pid``, one member per group); the signal is + delivered with ``nxsig_kill(pid, signo)``. + + The following terminal ``ioctl`` commands manage this PID: + + - ``TIOCSCTTY`` makes the terminal the controlling terminal. The + ``arg`` is treated as a flag: a value of ``0`` selects the + calling task (the POSIX convention used by, e.g., dropbear and + socat), while a positive value is honored as the target PID (the + NuttX convention used by NSH to register a foreground command it + has just spawned). + - ``TIOCNOTTY`` gives up the controlling terminal. + - ``TIOCGPGRP`` / ``TIOCGSID`` return the foreground process group / + session leader PID. + - ``TIOCSPGRP`` sets the foreground process group PID (a value of + ``0`` selects the calling task). + + The C library exposes these through ``tcgetpgrp()``, ``tcsetpgrp()``, + ``tcgetsid()``, ``setsid()``, ``getsid()`` and ``setpgid()``. Because + sending a signal to a process group (``kill(-pgrp, signo)``) is not + supported, TTY signals always target the single foreground PID rather + than an entire group. + - **User Access**. Serial drivers are, ultimately, normal `character drivers <#chardrivers>`__ and are accessed as other character drivers. diff --git a/drivers/serial/pty.c b/drivers/serial/pty.c index bcefb1672fe..070e82980fb 100644 --- a/drivers/serial/pty.c +++ b/drivers/serial/pty.c @@ -43,6 +43,7 @@ #include #include #include +#include #include #include #include @@ -838,16 +839,21 @@ static int pty_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Make the controlling terminal of the calling process */ case TIOCSCTTY: + case TIOCSPGRP: { - /* Save the PID of the recipient of the SIGINT signal. */ + /* Save the PID of the foreground process group that is to receive + * tty-generated signals. A zero 'arg' selects the calling task + * (POSIX flag semantics); a positive 'arg' is honored as the + * target PID (NuttX historical semantics). + */ - if ((int)arg < 0 || dev->pd_pid >= 0) + if ((int)arg < 0) { ret = -EINVAL; } else { - dev->pd_pid = (pid_t)arg; + dev->pd_pid = arg > 0 ? (pid_t)arg : nxsched_getpid(); ret = 0; } } @@ -859,6 +865,23 @@ static int pty_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = 0; } break; + + /* Get the foreground process group / session leader. pgrp == pid. */ + + case TIOCGPGRP: + case TIOCGSID: + { + if (dev->pd_pid < 0) + { + ret = -ENOTTY; + } + else + { + *(FAR pid_t *)((uintptr_t)arg) = dev->pd_pid; + ret = 0; + } + } + break; #endif /* Any unrecognized IOCTL commands will be passed to the contained diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index a30fdcaa2fe..5f54d972a98 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -1749,16 +1749,25 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* Make the controlling terminal of the calling process */ case TIOCSCTTY: + case TIOCSPGRP: { - /* Save the PID of the recipient of the SIGINT signal. */ + /* Save the PID of the foreground process group that is to + * receive tty-generated signals (SIGINT/SIGTSTP). + * + * POSIX passes a flag in 'arg' and uses the caller's PID, so + * a zero 'arg' selects the calling task. NuttX historically + * passes the target PID directly in 'arg' (e.g. NSH registers + * the foreground command it just spawned), so a positive + * 'arg' is honored as the target PID. + */ - if ((int)arg < 0 || dev->pid >= 0) + if ((int)arg < 0) { ret = -EINVAL; } else { - dev->pid = (pid_t)arg; + dev->pid = arg > 0 ? (pid_t)arg : nxsched_getpid(); ret = 0; } } @@ -1770,6 +1779,26 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg) ret = 0; } break; + + /* Get the foreground process group. Since NuttX has no real + * process-group abstraction, the controlling task's PID doubles + * as the (single-member) foreground process group. + */ + + case TIOCGPGRP: + case TIOCGSID: + { + if (dev->pid < 0) + { + ret = -ENOTTY; + } + else + { + *(FAR pid_t *)((uintptr_t)arg) = dev->pid; + ret = 0; + } + } + break; #endif } } diff --git a/include/nuttx/serial/serial.h b/include/nuttx/serial/serial.h index 57eb81492f2..ee82a927e17 100644 --- a/include/nuttx/serial/serial.h +++ b/include/nuttx/serial/serial.h @@ -335,7 +335,10 @@ struct uart_dev_s #if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGTSTP) || \ defined(CONFIG_TTY_FORCE_PANIC) || defined(CONFIG_TTY_LAUNCH) - pid_t pid; /* Thread PID to receive signals (-1 if none) */ + pid_t pid; /* Foreground process group / controlling-tty + * owner that receives tty signals. With no + * process-group support, pgrp == pid. + * (-1 if none) */ #endif #ifdef CONFIG_TTY_FORCE_PANIC diff --git a/include/nuttx/serial/tioctl.h b/include/nuttx/serial/tioctl.h index 5ab751ffa32..b93c28c11ee 100644 --- a/include/nuttx/serial/tioctl.h +++ b/include/nuttx/serial/tioctl.h @@ -87,7 +87,7 @@ /* Controlling TTY */ -#define TIOCSCTTY _TIOC(0x0018) /* Make controlling TTY: int */ +#define TIOCSCTTY _TIOC(0x0018) /* Make controlling TTY: int (0 == caller) */ #define TIOCNOTTY _TIOC(0x0019) /* Give up controllinog TTY: void */ /* Exclusive mode */ @@ -200,6 +200,12 @@ #define SER_SWAP_ENABLED (1 << 0) /* Enable/disable RX/TX swap */ +/* Process group / session (job control) */ + +#define TIOCGPGRP _TIOC(0x0037) /* Get foreground process group: FAR pid_t* */ +#define TIOCSPGRP _TIOC(0x0038) /* Set foreground process group: FAR const pid_t* */ +#define TIOCGSID _TIOC(0x0039) /* Get session leader: FAR pid_t* */ + /**************************************************************************** * Public Type Definitions ****************************************************************************/ diff --git a/include/unistd.h b/include/unistd.h index acfc0e0bb48..6c7f7d1bcf3 100644 --- a/include/unistd.h +++ b/include/unistd.h @@ -354,6 +354,11 @@ pid_t getpgid(pid_t pid); pid_t getpgrp(void); pid_t gettid(void); pid_t getppid(void); +pid_t getsid(pid_t pid); +int setpgid(pid_t pid, pid_t pgid); +pid_t setsid(void); +pid_t tcgetpgrp(int fd); +int tcsetpgrp(int fd, pid_t pgrp); void _exit(int status) noreturn_function; unsigned int sleep(unsigned int seconds); int usleep(useconds_t usec); diff --git a/libs/libc/termios/CMakeLists.txt b/libs/libc/termios/CMakeLists.txt index 71b73819174..2f5a0e11c45 100644 --- a/libs/libc/termios/CMakeLists.txt +++ b/libs/libc/termios/CMakeLists.txt @@ -32,4 +32,7 @@ target_sources( lib_tcsetattr.c lib_tcsendbreak.c lib_ttyname.c - lib_ttynamer.c) + lib_ttynamer.c + lib_tcgetpgrp.c + lib_tcsetpgrp.c + lib_tcgetsid.c) diff --git a/libs/libc/termios/Make.defs b/libs/libc/termios/Make.defs index 3cf99568ac8..68546b82af3 100644 --- a/libs/libc/termios/Make.defs +++ b/libs/libc/termios/Make.defs @@ -25,6 +25,7 @@ CSRCS += lib_cfspeed.c lib_cfmakeraw.c lib_isatty.c lib_tcflush.c CSRCS += lib_tcdrain.c lib_tcflow.c lib_tcgetattr.c lib_tcsetattr.c CSRCS += lib_tcsendbreak.c lib_ttyname.c lib_ttynamer.c +CSRCS += lib_tcgetpgrp.c lib_tcsetpgrp.c lib_tcgetsid.c # Add the termios directory to the build diff --git a/libs/libc/termios/lib_tcgetpgrp.c b/libs/libc/termios/lib_tcgetpgrp.c new file mode 100644 index 00000000000..f85ec57e0bb --- /dev/null +++ b/libs/libc/termios/lib_tcgetpgrp.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * libs/libc/termios/lib_tcgetpgrp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tcgetpgrp + * + * Description: + * Return the value of the process group ID of the foreground process + * group associated with the terminal. + * + * Input Parameters: + * fd - The 'fd' argument is an open file descriptor associated with a + * terminal. + * + * Returned Value: + * Upon successful completion, the process group ID of the foreground + * process group is returned. Otherwise, (pid_t)-1 is returned and errno + * is set to indicate the error. + * + ****************************************************************************/ + +pid_t tcgetpgrp(int fd) +{ + pid_t pgrp; + + if (ioctl(fd, TIOCGPGRP, &pgrp) < 0) + { + return (pid_t)-1; + } + + return pgrp; +} diff --git a/libs/libc/termios/lib_tcgetsid.c b/libs/libc/termios/lib_tcgetsid.c new file mode 100644 index 00000000000..78162f0c14a --- /dev/null +++ b/libs/libc/termios/lib_tcgetsid.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * libs/libc/termios/lib_tcgetsid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tcgetsid + * + * Description: + * Obtain the process group ID of the session for which the terminal is + * the controlling terminal. + * + * Input Parameters: + * fd - The 'fd' argument is an open file descriptor associated with a + * terminal. + * + * Returned Value: + * Upon successful completion, the session leader's process group ID is + * returned. Otherwise, (pid_t)-1 is returned and errno is set to + * indicate the error. + * + ****************************************************************************/ + +pid_t tcgetsid(int fd) +{ + pid_t sid; + + if (ioctl(fd, TIOCGSID, &sid) < 0) + { + return (pid_t)-1; + } + + return sid; +} diff --git a/libs/libc/termios/lib_tcsetpgrp.c b/libs/libc/termios/lib_tcsetpgrp.c new file mode 100644 index 00000000000..8e1042cb09f --- /dev/null +++ b/libs/libc/termios/lib_tcsetpgrp.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * libs/libc/termios/lib_tcsetpgrp.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tcsetpgrp + * + * Description: + * Set the foreground process group ID associated with the terminal. + * + * Input Parameters: + * fd - The 'fd' argument is an open file descriptor associated with a + * terminal. + * pgrp - The process group ID to be made the foreground process group. + * + * Returned Value: + * Upon successful completion, 0 is returned. Otherwise, -1 is returned + * and errno is set to indicate the error. + * + ****************************************************************************/ + +int tcsetpgrp(int fd, pid_t pgrp) +{ + return ioctl(fd, TIOCSPGRP, &pgrp); +} diff --git a/libs/libc/unistd/CMakeLists.txt b/libs/libc/unistd/CMakeLists.txt index 0cef734cc7a..797ff8aba9e 100644 --- a/libs/libc/unistd/CMakeLists.txt +++ b/libs/libc/unistd/CMakeLists.txt @@ -64,6 +64,9 @@ set(SRCS lib_usleep.c lib_getpgrp.c lib_getpgid.c + lib_getsid.c + lib_setpgid.c + lib_setsid.c lib_lockf.c lib_flock.c lib_getpass.c diff --git a/libs/libc/unistd/Make.defs b/libs/libc/unistd/Make.defs index e5d8d248f60..e7852230ad7 100644 --- a/libs/libc/unistd/Make.defs +++ b/libs/libc/unistd/Make.defs @@ -32,6 +32,7 @@ CSRCS += lib_setrlimit.c lib_getrlimit.c lib_setpriority.c lib_getpriority.c CSRCS += lib_futimes.c lib_lutimes.c lib_gethostname.c lib_sethostname.c CSRCS += lib_fchownat.c lib_linkat.c lib_readlinkat.c lib_symlinkat.c CSRCS += lib_unlinkat.c lib_usleep.c lib_getpgrp.c lib_getpgid.c +CSRCS += lib_getsid.c lib_setpgid.c lib_setsid.c CSRCS += lib_lockf.c lib_flock.c lib_getpass.c CSRCS += lib_chdir.c lib_fchdir.c lib_confstr.c lib_ulimit.c diff --git a/libs/libc/unistd/lib_getsid.c b/libs/libc/unistd/lib_getsid.c new file mode 100644 index 00000000000..1a06613e8d8 --- /dev/null +++ b/libs/libc/unistd/lib_getsid.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * libs/libc/unistd/lib_getsid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: getsid + * + * Description: + * Get the session ID of the process whose process ID is pid. NuttX does + * not implement sessions, so the session ID is the same as the process + * ID, mirroring getpgid(). + * + * Input Parameters: + * pid - The process ID whose session ID is requested. A value of zero + * refers to the calling process. + * + * Returned Value: + * The session ID is returned on success. Otherwise, (pid_t)-1 is + * returned and errno is set: EINVAL if pid is negative, ESRCH if pid + * does not refer to an existing process. + * + ****************************************************************************/ + +pid_t getsid(pid_t pid) +{ + if (pid < 0) + { + set_errno(EINVAL); + return (pid_t)-1; + } + + if (pid == 0) + { + return _SCHED_GETPID(); + } + + if (_SIG_KILL(pid, 0) < 0) + { + return (pid_t)-1; + } + + return pid; +} diff --git a/libs/libc/unistd/lib_setpgid.c b/libs/libc/unistd/lib_setpgid.c new file mode 100644 index 00000000000..55d72659a68 --- /dev/null +++ b/libs/libc/unistd/lib_setpgid.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * libs/libc/unistd/lib_setpgid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setpgid + * + * Description: + * Set the process group ID of the process whose process ID is pid to + * pgid. NuttX does not implement process groups, so a process group + * always contains a single member and its ID equals the process ID. + * Consequently this stub only succeeds when the requested pgid matches + * the target pid (or is zero, which selects the target pid itself). + * + * Input Parameters: + * pid - The process whose process group ID is to be changed. A value of + * zero refers to the calling process. + * pgid - The new process group ID. A value of zero uses the target pid. + * + * Returned Value: + * Zero is returned on success. Otherwise, -1 is returned and errno is + * set: EINVAL if pgid is negative, ESRCH if pid does not exist, EPERM if + * the requested pgid cannot be honored by this single-member-group model. + * + ****************************************************************************/ + +int setpgid(pid_t pid, pid_t pgid) +{ + if (pgid < 0) + { + set_errno(EINVAL); + return -1; + } + + if (pid == 0) + { + pid = _SCHED_GETPID(); + } + else if (_SIG_KILL(pid, 0) < 0) + { + return -1; + } + + /* A process group can only contain the single member 'pid', so the only + * legal group ID is 'pid' itself (a zero pgid selects it implicitly). + */ + + if (pgid != 0 && pgid != pid) + { + set_errno(EPERM); + return -1; + } + + return 0; +} diff --git a/libs/libc/unistd/lib_setsid.c b/libs/libc/unistd/lib_setsid.c new file mode 100644 index 00000000000..86fc66ba2f4 --- /dev/null +++ b/libs/libc/unistd/lib_setsid.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * libs/libc/unistd/lib_setsid.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setsid + * + * Description: + * Create a new session, if the calling process is not already a process + * group leader. NuttX does not implement sessions or process groups, so + * each task is treated as its own session and process group. This stub + * therefore returns the caller's PID, which acts as the session ID. + * + * Input Parameters: + * None + * + * Returned Value: + * The session ID (the caller's PID) is returned. A failure return of + * (pid_t)-1 with errno set to EPERM is not possible here because there is + * no process-group leadership to conflict with. + * + ****************************************************************************/ + +pid_t setsid(void) +{ + return _SCHED_GETPID(); +} From d8a7dee73e76e9c73d1fecb097474edf83956d44 Mon Sep 17 00:00:00 2001 From: Felipe Moura Date: Mon, 22 Jun 2026 19:14:15 -0300 Subject: [PATCH 145/268] Documentation/netutils/dropbear: add Dropbear SSH server documentation Add application-level documentation for the Dropbear SSH server port, covering prerequisites, configuration options, usage and troubleshooting. Signed-off-by: Felipe Moura --- .../applications/netutils/dropbear/index.rst | 129 ++++++++++++++++++ 1 file changed, 129 insertions(+) create mode 100644 Documentation/applications/netutils/dropbear/index.rst diff --git a/Documentation/applications/netutils/dropbear/index.rst b/Documentation/applications/netutils/dropbear/index.rst new file mode 100644 index 00000000000..d0c86ac8776 --- /dev/null +++ b/Documentation/applications/netutils/dropbear/index.rst @@ -0,0 +1,129 @@ +===================================== +``dropbear`` SSH Server +===================================== + +`Dropbear `__ is a lightweight +SSH server well-suited for embedded environments. The NuttX port exposes an NSH +session over an encrypted SSH connection, enabling remote access to NuttX-based +hardware over a network. + +Overview +-------- + +The port runs Dropbear as a persistent NuttX task, accepting successive SSH +connections without restarting. It can be used to open interactive NSH sessions +remotely, inspect system state, run commands, or integrate into automated +workflows that require secure shell access to an embedded target. + +All cryptographic operations are routed through NuttX's native crypto stack, +replacing the bundled libtomcrypt modules and leveraging any available hardware +acceleration. + +Prerequisites +------------- + +Dropbear requires the board to have a reachable IP address. The underlying +network interface can be any transport supported by NuttX — Wi-Fi station mode, +Ethernet, or a point-to-point link — as long as the interface is up and has an +assigned address visible in ``ifconfig``:: + + nsh> ifconfig + wlan0 Link encap:Ethernet HWaddr 84:f7:03:xx:xx:xx at RUNNING mtu 1504 + inet addr:192.168.1.xx DRaddr:192.168.1.x Mask:255.255.255.0 + +The SSH client must be able to reach that address over TCP port 22 (or whichever +port is configured via ``CONFIG_NETUTILS_DROPBEAR_PORT``). + +A persistent writable filesystem (e.g. SPIFFS or LittleFS) must be mounted and +accessible at the path used by ``CONFIG_NETUTILS_DROPBEAR_HOSTKEY_PATH`` and +``CONFIG_FSUTILS_PASSWD_PATH``. These files are created automatically on the +first run, but the filesystem must already be mounted. + +Enabling Dropbear +----------------- + +Enable the following options in ``menuconfig``:: + + CONFIG_NETUTILS_DROPBEAR=y + +Key configuration options: + +- ``CONFIG_NETUTILS_DROPBEAR_PORT`` — TCP port to listen on (default: ``22``). +- ``CONFIG_NETUTILS_DROPBEAR_HOSTKEY_PATH`` — path where the ECDSA host key is + stored (default: ``/data/dropbear_ecdsa_host_key``). +- ``CONFIG_NETUTILS_DROPBEAR_STACKSIZE`` — task stack size. A minimum of + ``65536`` bytes is recommended; +- ``CONFIG_NETUTILS_DROPBEAR_PRIORITY`` — task priority. + +The user database is read from the path configured by +``CONFIG_FSUTILS_PASSWD_PATH`` (default ``/data/passwd``). + +Usage +----- + +Once the network is up, the daemon starts automatically. The first run +generates an ECDSA host key and writes it to ``CONFIG_NETUTILS_DROPBEAR_HOSTKEY_PATH``. +Add a user account from the NSH console before connecting:: + + nsh> useradd + +Check the board's IP address:: + + nsh> ifconfig + +Then open an SSH session from a host on the same network:: + + $ ssh @ + @'s password: + nsh> + +Notes +----- + +- The host key and the user database persist across reboots when stored on a + non-volatile partition (e.g. SPIFFS mounted at ``/data``). +- Only password authentication is supported; public-key authentication is + disabled. +- Only ECDSA P-256 host keys are supported. +- Enabled ciphers: ``chacha20-poly1305@openssh.com`` and ``aes128-ctr``. +- Port forwarding, agent forwarding, and X11 forwarding are disabled. +- Multiple clients can connect sequentially; the daemon re-enters the accept + loop after each session ends. + +Troubleshooting +--------------- + +**Lost password / cannot log in** + +The user database is stored in the file pointed to by ``CONFIG_FSUTILS_PASSWD_PATH`` +on the persistent partition (e.g. ``/data/passwd`` on SPIFFS). If the password +is lost and the board can still be reached over a serial console, remove the +file and recreate the account:: + + nsh> rm /data/passwd + nsh> useradd + +If the serial console is also inaccessible, the only recovery path is to erase +the persistent partition (or the full flash) and reflash the firmware. + +**Host key mismatch after reflashing** + +When the persistent partition is erased as part of a reflash, Dropbear generates +a new host key on the next boot. The SSH client on the host machine will then +refuse to connect because the key no longer matches the entry stored in +``~/.ssh/known_hosts``, printing a warning such as +``WARNING: REMOTE HOST IDENTIFICATION HAS CHANGED``. + +Remove the stale entry with:: + + $ ssh-keygen -R + +Then reconnect normally. The client will prompt to accept the new host key. + +**Connection refused** + +Check that the board has obtained an IP address and that the Dropbear task is +running:: + + nsh> ifconfig + nsh> ps From a74d8d5d02aee2563346edf4f95f7fda037b241e Mon Sep 17 00:00:00 2001 From: shichunma Date: Tue, 16 Jun 2026 15:44:45 +0800 Subject: [PATCH 146/268] mm/gran: reject pools with too many granules struct gran_s and struct graninfo_s store granule counts in uint16_t. Reject pools whose computed granule count exceeds UINT16_MAX, instead of truncating the count and creating an invalid handle. Signed-off-by: shichunma --- mm/mm_gran/mm_graninit.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/mm/mm_gran/mm_graninit.c b/mm/mm_gran/mm_graninit.c index 0ae0e4cf8b5..ade271c2c46 100644 --- a/mm/mm_gran/mm_graninit.c +++ b/mm/mm_gran/mm_graninit.c @@ -124,6 +124,14 @@ GRAN_HANDLE gran_initialize(FAR void *heapstart, size_t heapsize, alignedsize = (heapend - alignedstart) & ~mask; ngranules = alignedsize >> log2gran; + /* Reject oversized pools. */ + + DEBUGASSERT(ngranules > 0 && ngranules <= UINT16_MAX); + if (ngranules == 0 || ngranules > UINT16_MAX) + { + return NULL; + } + /* Allocate the information structure with a granule table of the * correct size. */ From e906add15c3b83096420700a86520e785caadb5a Mon Sep 17 00:00:00 2001 From: Nightt <87569709+nightt5879@users.noreply.github.com> Date: Wed, 24 Jun 2026 20:21:27 +0800 Subject: [PATCH 147/268] docs: add SCPI application documentation Document the SCPI parser application, including source location, basic Kconfig options, and the unit parser options introduced by apache/nuttx-apps#3556. Signed-off-by: Nightt <87569709+nightt5879@users.noreply.github.com> --- .../applications/industry/scpi/index.rst | 89 +++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/Documentation/applications/industry/scpi/index.rst b/Documentation/applications/industry/scpi/index.rst index fd42bdd5873..35329496f8d 100644 --- a/Documentation/applications/industry/scpi/index.rst +++ b/Documentation/applications/industry/scpi/index.rst @@ -1,3 +1,92 @@ ==================================== ``scpi`` SCPI instrument side parser ==================================== + +Overview +======== + +The ``scpi`` application integrates the +`scpi-parser `_ library with the +NuttX application build system. SCPI, the Standard Commands for Programmable +Instruments, is commonly used by test and measurement equipment to parse +instrument commands and responses. + +The application provides the SCPI parser library for NuttX applications and can +optionally build the upstream interactive demo program. + +Source Location +=============== + +The NuttX application wrapper is located in ``apps/industry/scpi``. It +downloads and builds ``scpi-parser`` version 2.2 unless an unpacked +``scpi-parser`` source tree is already present in that directory. + +Basic Configuration +=================== + +Enable the parser with: + +- ``CONFIG_SCPI_PARSER`` - Build the SCPI instrument-side parser library. + +Optional demo support is controlled by: + +- ``CONFIG_SCPI_PARSER_DEMO`` - Build the SCPI parser interactive demo program. +- ``CONFIG_SCPI_PARSER_DEMO_PRIORITY`` - Demo task priority. +- ``CONFIG_SCPI_PARSER_DEMO_STACKSIZE`` - Demo task stack size. + +Unit Parser Configuration +========================= + +``scpi-parser`` can include or exclude optional unit groups at compile time. +NuttX exposes these as Kconfig options and maps each option to the matching +upstream ``USE_UNITS_*`` compile-time define. + +The following unit groups are configurable: + +- ``CONFIG_SCPI_PARSER_UNITS_IMPERIAL`` - Imperial units. +- ``CONFIG_SCPI_PARSER_UNITS_ANGLE`` - Angle units. +- ``CONFIG_SCPI_PARSER_UNITS_PARTICLES`` - Particle units. +- ``CONFIG_SCPI_PARSER_UNITS_DISTANCE`` - Distance units. +- ``CONFIG_SCPI_PARSER_UNITS_MAGNETIC`` - Magnetic units. +- ``CONFIG_SCPI_PARSER_UNITS_LIGHT`` - Light units. +- ``CONFIG_SCPI_PARSER_UNITS_ENERGY_FORCE_MASS`` - Energy, force, and mass + units. +- ``CONFIG_SCPI_PARSER_UNITS_TIME`` - Time units. +- ``CONFIG_SCPI_PARSER_UNITS_TEMPERATURE`` - Temperature units. +- ``CONFIG_SCPI_PARSER_UNITS_RATIO`` - Ratio units. +- ``CONFIG_SCPI_PARSER_UNITS_POWER`` - Power units. +- ``CONFIG_SCPI_PARSER_UNITS_FREQUENCY`` - Frequency units. +- ``CONFIG_SCPI_PARSER_UNITS_ELECTRIC`` - Electric units. +- ``CONFIG_SCPI_PARSER_UNITS_ELECTRIC_CHARGE_CONDUCTANCE`` - Electric charge + and conductance units. + +By default, ``CONFIG_SCPI_PARSER_UNITS_POWER``, +``CONFIG_SCPI_PARSER_UNITS_FREQUENCY``, and +``CONFIG_SCPI_PARSER_UNITS_ELECTRIC`` are enabled. The other optional unit +groups are disabled by default and may be enabled individually. + +For example, enabling ``CONFIG_SCPI_PARSER_UNITS_TIME`` passes +``USE_UNITS_TIME=1`` to ``scpi-parser`` during compilation. + +Example Configuration +===================== + +A minimal parser configuration can enable only the library: + +.. code-block:: text + + CONFIG_SCPI_PARSER=y + +To build the parser with time-unit support: + +.. code-block:: text + + CONFIG_SCPI_PARSER=y + CONFIG_SCPI_PARSER_UNITS_TIME=y + +To include the interactive demo program: + +.. code-block:: text + + CONFIG_SCPI_PARSER=y + CONFIG_SCPI_PARSER_DEMO=y From 0e5d8d6c85e7ee78ecf6818a3d9951b23126738b Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 12:12:39 +0200 Subject: [PATCH 148/268] !boards/arm/stm32: move common board sources BREAKING CHANGE: Move the existing STM32 board common sources to boards/arm/common/stm32 and fold in the common STM32F0/L0/G0/C0 board helpers so split STM32 board families can share one source tree. Signed-off-by: raiden00pl --- .../drivers/character/input/keypad.rst | 2 +- .../drivers/character/input/mpr121.rst | 2 +- .../drivers/character/input/sbutton.rst | 2 +- boards/Kconfig | 4 +- .../src => common/stm32}/CMakeLists.txt | 20 +-- boards/arm/common/stm32/Kconfig | 71 ++++++++ .../src/Make.defs => common/stm32/Makefile} | 26 ++- .../stm32}/include/board_hall3ph.h | 8 +- .../stm32}/include/board_pwm.h | 8 +- .../stm32}/include/board_qencoder.h | 8 +- .../stm32}/include/board_sbutton.h | 8 +- .../stm32}/include/stm32_amg88xx.h | 8 +- .../stm32}/include/stm32_apa102.h | 8 +- .../stm32}/include/stm32_apds9960.h | 8 +- .../stm32}/include/stm32_bh1750.h | 8 +- .../stm32}/include/stm32_bmp180.h | 8 +- .../stm32}/include/stm32_bmp280.h | 8 +- .../stm32}/include/stm32_dhtxx.h | 8 +- .../stm32}/include/stm32_drv8266.h | 8 +- .../stm32}/include/stm32_ds1307.h | 8 +- .../stm32}/include/stm32_hcsr04.h | 8 +- .../stm32}/include/stm32_ihm07m1.h | 8 +- .../stm32}/include/stm32_ihm08m1.h | 8 +- .../stm32}/include/stm32_ihm16m1.h | 8 +- .../stm32}/include/stm32_ina219.h | 8 +- .../stm32}/include/stm32_kmatrix_gpio.h | 8 +- .../stm32}/include/stm32_kmatrix_i2c.h | 8 +- .../stm32}/include/stm32_l3gd20.h | 8 +- .../stm32}/include/stm32_lcd_backpack.h | 8 +- .../stm32}/include/stm32_lis3dsh.h | 8 +- .../stm32}/include/stm32_lm75.h | 8 +- .../stm32}/include/stm32_max31855.h | 8 +- .../stm32}/include/stm32_max6675.h | 8 +- .../stm32}/include/stm32_max7219_matrix.h | 8 +- .../stm32}/include/stm32_mfrc522.h | 8 +- .../stm32}/include/stm32_mlx90614.h | 8 +- .../stm32}/include/stm32_mpl115a.h | 8 +- .../stm32}/include/stm32_mpr121.h | 8 +- .../stm32}/include/stm32_ms5611.h | 6 +- .../stm32}/include/stm32_mt6816.h | 8 +- .../stm32}/include/stm32_nrf24l01.h | 8 +- .../stm32}/include/stm32_nunchuck.h | 8 +- .../stm32}/include/stm32_ssd1306.h | 8 +- .../stm32}/include/stm32_tone.h | 8 +- .../stm32}/include/stm32_veml6070.h | 8 +- .../stm32}/include/stm32_ws2812.h | 8 +- .../stm32}/include/stm32_xen1210.h | 8 +- .../stm32}/include/stm32_zerocross.h | 8 +- .../stm32}/src/CMakeLists.txt | 8 +- .../common => common/stm32}/src/Make.defs | 19 ++- .../stm32}/src/board_hall3ph.c | 2 +- .../common => common/stm32}/src/board_pwm.c | 2 +- .../stm32}/src/board_qencoder.c | 4 +- .../stm32}/src/stm32_amg88xx.c | 2 +- .../stm32}/src/stm32_apa102.c | 2 +- .../stm32}/src/stm32_apds9960.c | 2 +- .../stm32}/src/stm32_bh1750.c | 2 +- .../stm32}/src/stm32_bmp180.c | 2 +- .../stm32}/src/stm32_bmp280.c | 2 +- .../common => common/stm32}/src/stm32_dhtxx.c | 2 +- .../stm32}/src/stm32_drv8825.c | 2 +- .../stm32}/src/stm32_ds1307.c | 2 +- .../stm32}/src/stm32_hcsr04.c | 2 +- .../stm32}/src/stm32_ihm07m1.c | 2 +- .../stm32}/src/stm32_ihm08m1.c | 2 +- .../stm32}/src/stm32_ihm16m1.c | 2 +- .../stm32}/src/stm32_ina219.c | 2 +- .../stm32}/src/stm32_kmatrix_gpio.c | 2 +- .../stm32}/src/stm32_kmatrix_i2c.c | 2 +- .../stm32}/src/stm32_l3gd20.c | 2 +- .../stm32}/src/stm32_lcd_backpack.c | 2 +- .../stm32}/src/stm32_lis3dsh.c | 2 +- .../common => common/stm32}/src/stm32_lm75.c | 2 +- .../stm32}/src/stm32_max31855.c | 2 +- .../stm32}/src/stm32_max6675.c | 2 +- .../stm32}/src/stm32_max7219_matrix.c | 2 +- .../stm32}/src/stm32_mfrc522.c | 2 +- .../stm32}/src/stm32_mlx90614.c | 2 +- .../stm32}/src/stm32_mpl115a.c | 2 +- .../stm32}/src/stm32_mpr121.c | 2 +- .../stm32}/src/stm32_ms5611.c | 2 +- .../stm32}/src/stm32_mt6816.c | 2 +- .../stm32}/src/stm32_nrf24l01.c | 2 +- .../stm32}/src/stm32_nunchuck.c | 2 +- .../stm32}/src/stm32_sbutton.c | 2 +- .../stm32}/src/stm32_ssd1306.c | 8 +- .../common => common/stm32}/src/stm32_tone.c | 2 +- .../stm32}/src/stm32_veml6070.c | 2 +- .../stm32}/src/stm32_ws2812.c | 2 +- .../stm32}/src/stm32_xen1210.c | 2 +- .../stm32}/src/stm32_zerocross.c | 2 +- boards/arm/stm32/common/CMakeLists.txt | 5 +- boards/arm/stm32/common/Kconfig | 67 +------- boards/arm/stm32/common/Makefile | 7 +- boards/arm/stm32/common/src/stm32_qencoder.c | 68 -------- boards/arm/stm32/common/src/stm32_ssd1306.c | 160 ------------------ boards/arm/stm32f0l0g0/common/CMakeLists.txt | 5 +- boards/arm/stm32f0l0g0/common/Kconfig | 1 + boards/arm/stm32f0l0g0/common/Makefile | 7 +- .../common/include/board_qencoder.h | 63 ------- .../common/include/stm32_ssd1306.h | 82 --------- 101 files changed, 335 insertions(+), 700 deletions(-) rename boards/arm/{stm32f0l0g0/common/src => common/stm32}/CMakeLists.txt (74%) create mode 100644 boards/arm/common/stm32/Kconfig rename boards/arm/{stm32f0l0g0/common/src/Make.defs => common/stm32/Makefile} (71%) rename boards/arm/{stm32/common => common/stm32}/include/board_hall3ph.h (91%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/include/board_pwm.h (85%) rename boards/arm/{stm32/common => common/stm32}/include/board_qencoder.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/board_sbutton.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_amg88xx.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_apa102.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_apds9960.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bh1750.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bmp180.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_bmp280.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_dhtxx.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_drv8266.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ds1307.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_hcsr04.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm07m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm08m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ihm16m1.h (89%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ina219.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_kmatrix_gpio.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_kmatrix_i2c.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_l3gd20.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lcd_backpack.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lis3dsh.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_lm75.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max31855.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max6675.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_max7219_matrix.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mfrc522.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mlx90614.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mpl115a.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mpr121.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ms5611.h (94%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_mt6816.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_nrf24l01.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_nunchuck.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ssd1306.h (91%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_tone.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_veml6070.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_ws2812.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_xen1210.h (92%) rename boards/arm/{stm32/common => common/stm32}/include/stm32_zerocross.h (91%) rename boards/arm/{stm32/common => common/stm32}/src/CMakeLists.txt (95%) rename boards/arm/{stm32/common => common/stm32}/src/Make.defs (87%) rename boards/arm/{stm32/common => common/stm32}/src/board_hall3ph.c (98%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/board_pwm.c (98%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/board_qencoder.c (96%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_amg88xx.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_apa102.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_apds9960.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bh1750.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bmp180.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_bmp280.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_dhtxx.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_drv8825.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ds1307.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_hcsr04.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm07m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm08m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ihm16m1.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ina219.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_kmatrix_gpio.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_kmatrix_i2c.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_l3gd20.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lcd_backpack.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lis3dsh.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_lm75.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max31855.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max6675.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_max7219_matrix.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mfrc522.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mlx90614.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mpl115a.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mpr121.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ms5611.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_mt6816.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_nrf24l01.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_nunchuck.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_sbutton.c (99%) rename boards/arm/{stm32f0l0g0/common => common/stm32}/src/stm32_ssd1306.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_tone.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_veml6070.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_ws2812.c (98%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_xen1210.c (99%) rename boards/arm/{stm32/common => common/stm32}/src/stm32_zerocross.c (99%) delete mode 100644 boards/arm/stm32/common/src/stm32_qencoder.c delete mode 100644 boards/arm/stm32/common/src/stm32_ssd1306.c delete mode 100644 boards/arm/stm32f0l0g0/common/include/board_qencoder.h delete mode 100644 boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h diff --git a/Documentation/components/drivers/character/input/keypad.rst b/Documentation/components/drivers/character/input/keypad.rst index 93d357bc7ac..58425f4fd5e 100644 --- a/Documentation/components/drivers/character/input/keypad.rst +++ b/Documentation/components/drivers/character/input/keypad.rst @@ -62,7 +62,7 @@ kbd-codec layer. ``board_kmatrix_initialize("/dev/keypad0")``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_kmatrix_gpio.c``: +is in ``boards/arm/common/stm32/src/stm32_kmatrix_gpio.c``: - Rows: ``BOARD_KMATRIX_ROW0..3`` (outputs) - Columns: ``BOARD_KMATRIX_COL0..2`` (inputs with pull-up) diff --git a/Documentation/components/drivers/character/input/mpr121.rst b/Documentation/components/drivers/character/input/mpr121.rst index 9a24b3158fb..c8ccae10420 100644 --- a/Documentation/components/drivers/character/input/mpr121.rst +++ b/Documentation/components/drivers/character/input/mpr121.rst @@ -53,7 +53,7 @@ kbd-codec layer. ``board_mpr121_initialize(0, 1)`` for ``/dev/keymap0`` and ``i2c1``). **Reference Implementation (STM32F4Discovery)**. The current reference -is in ``boards/arm/stm32/common/src/stm32_mpr121.c``: +is in ``boards/arm/common/stm32/src/stm32_mpr121.c``: - Keymap: 4x3 keypad layout - Registration: ``board_mpr121_initialize()`` calls diff --git a/Documentation/components/drivers/character/input/sbutton.rst b/Documentation/components/drivers/character/input/sbutton.rst index 3281db7fd4a..ca118f95e74 100644 --- a/Documentation/components/drivers/character/input/sbutton.rst +++ b/Documentation/components/drivers/character/input/sbutton.rst @@ -23,7 +23,7 @@ It uses a kind of "polymorphism" in C to allow the driver to get access to the functions responsible to attach and enable the interrupt and to get the status of the pin. See ``include/nuttx/input/sbutton.h`` -and ``boards/arm/stm32/common/src/stm32_sbutton.c`` to understand +and ``boards/arm/common/stm32/src/stm32_sbutton.c`` to understand better how it works. But basically the board file (config data) creates a struct when the first field (variable) is the config struct used the but SButton driver (``drivers/input/sbutton.c``). diff --git a/boards/Kconfig b/boards/Kconfig index 5196f18cbc2..e2d689a9e0e 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5208,13 +5208,13 @@ if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif if ARCH_CHIP_STM32 -source "boards/arm/stm32/common/Kconfig" +source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_STM32F7 source "boards/arm/stm32f7/common/Kconfig" endif if ARCH_CHIP_STM32F0L0G0 -source "boards/arm/stm32f0l0g0/common/Kconfig" +source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 source "boards/arm/rp2040/common/Kconfig" diff --git a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt b/boards/arm/common/stm32/CMakeLists.txt similarity index 74% rename from boards/arm/stm32f0l0g0/common/src/CMakeLists.txt rename to boards/arm/common/stm32/CMakeLists.txt index 2b7dc2f3527..1c54914f408 100644 --- a/boards/arm/stm32f0l0g0/common/src/CMakeLists.txt +++ b/boards/arm/common/stm32/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/common/src/CMakeLists.txt +# boards/arm/common/stm32/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,19 +20,5 @@ # # ############################################################################## -if(CONFIG_ARCH_BOARD_COMMON) - - if(CONFIG_LCD_SSD1306) - list(APPEND SRCS stm32_ssd1306.c) - endif() - - if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS board_qencoder.c) - endif() - - if(CONFIG_PWM) - list(APPEND SRCS board_pwm.c) - endif() - -endif() -target_sources(board PRIVATE ${SRCS}) +add_subdirectory(src) +target_include_directories(board PRIVATE include) diff --git a/boards/arm/common/stm32/Kconfig b/boards/arm/common/stm32/Kconfig new file mode 100644 index 00000000000..3e611724880 --- /dev/null +++ b/boards/arm/common/stm32/Kconfig @@ -0,0 +1,71 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if STM32_FOC + +menuconfig BOARD_STM32_IHM07M1 + bool "X-NUCLEO-IHM07M1 board support" + default n + ---help--- + Board based on the L6230 DMOS driver. + +if BOARD_STM32_IHM07M1 + +config BOARD_STM32_IHM07M1_VBUS + bool "X-NUCLEO-IHM07M1 board VBUS sense" + default n + +config BOARD_STM32_IHM07M1_POT + bool "X-NUCLEO-IHM07M1 board POT support" + default n + +endif # BOARD_STM32_IHM07M1 + +menuconfig BOARD_STM32_IHM08M1 + bool "X-NUCLEO-IHM08M1 board support" + default n + select STM32_FOC_HAS_PWM_COMPLEMENTARY + ---help--- + Board based on the discrete L6398 gate drivers and STL220N6F7 POWER MOSFETs. + +if BOARD_STM32_IHM08M1 + +config BOARD_STM32_IHM08M1_VBUS + bool "X-NUCLEO-IHM08M1 board VBUS sense" + default n + +config BOARD_STM32_IHM08M1_POT + bool "X-NUCLEO-IHM08M1 board POT support" + default n + +endif # BOARD_STM32_IHM08M1 + +menuconfig BOARD_STM32_IHM16M1 + bool "X-NUCLEO-IHM16M1 board support" + default n + ---help--- + Board based on the STSPIN830 three-phase brushless motor driver. + +if BOARD_STM32_IHM16M1 + +config BOARD_STM32_IHM16M1_VBUS + bool "X-NUCLEO-IHM16M1 board VBUS sense" + default n + +config BOARD_STM32_IHM16M1_POT + bool "X-NUCLEO-IHM16M1 board POT support" + default n + +endif # BOARD_STM32_IHM16M1 + +endif # STM32_FOC + +if SENSORS_HALL3PHASE + +config BOARD_STM32_HALL3PHASE_SAMPLES + int "3-phase Hall effect sensor number of samples" + default 10 + +endif # SENSORS_HALL3PHASE diff --git a/boards/arm/stm32f0l0g0/common/src/Make.defs b/boards/arm/common/stm32/Makefile similarity index 71% rename from boards/arm/stm32f0l0g0/common/src/Make.defs rename to boards/arm/common/stm32/Makefile index 972383a6291..3ce135c1070 100644 --- a/boards/arm/stm32f0l0g0/common/src/Make.defs +++ b/boards/arm/common/stm32/Makefile @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32f0l0g0/common/src/Make.defs +# boards/arm/common/stm32/Makefile # # SPDX-License-Identifier: Apache-2.0 # @@ -20,22 +20,16 @@ # ############################################################################# -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) +include $(TOPDIR)/Make.defs -ifeq ($(CONFIG_LCD_SSD1306),y) - CSRCS += stm32_ssd1306.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - CSRCS += board_qencoder.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += board_pwm.c -endif +include board/Make.defs +include src/Make.defs +DEPPATH += --dep-path board DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src -endif +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/arm/stm32/common/include/board_hall3ph.h b/boards/arm/common/stm32/include/board_hall3ph.h similarity index 91% rename from boards/arm/stm32/common/include/board_hall3ph.h rename to boards/arm/common/stm32/include/board_hall3ph.h index 3cd1f2d819a..21ab10f8220 100644 --- a/boards/arm/stm32/common/include/board_hall3ph.h +++ b/boards/arm/common/stm32/include/board_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_hall3ph.h + * boards/arm/common/stm32/include/board_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H /**************************************************************************** * Included Files @@ -66,4 +66,4 @@ int board_hall3ph_initialize(int devno, int pha, int phb, int phc); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_HALL3PH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_HALL3PH_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/board_pwm.h b/boards/arm/common/stm32/include/board_pwm.h similarity index 85% rename from boards/arm/stm32f0l0g0/common/include/board_pwm.h rename to boards/arm/common/stm32/include/board_pwm.h index b86407e0aa5..2e673915733 100644 --- a/boards/arm/stm32f0l0g0/common/include/board_pwm.h +++ b/boards/arm/common/stm32/include/board_pwm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_pwm.h + * boards/arm/common/stm32/include/board_pwm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H /**************************************************************************** * Included Files @@ -37,4 +37,4 @@ int stm32_pwm_setup(void); #endif -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_PWM_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_PWM_H */ diff --git a/boards/arm/stm32/common/include/board_qencoder.h b/boards/arm/common/stm32/include/board_qencoder.h similarity index 91% rename from boards/arm/stm32/common/include/board_qencoder.h rename to boards/arm/common/stm32/include/board_qencoder.h index 5d6dbe19178..241f64d4ad0 100644 --- a/boards/arm/stm32/common/include/board_qencoder.h +++ b/boards/arm/common/stm32/include/board_qencoder.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_qencoder.h + * boards/arm/common/stm32/include/board_qencoder.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_qencoder_initialize(int devno, int timerno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_QENCODER_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32/common/include/board_sbutton.h b/boards/arm/common/stm32/include/board_sbutton.h similarity index 92% rename from boards/arm/stm32/common/include/board_sbutton.h rename to boards/arm/common/stm32/include/board_sbutton.h index 0dd67c11398..f123d0b4f57 100644 --- a/boards/arm/stm32/common/include/board_sbutton.h +++ b/boards/arm/common/stm32/include/board_sbutton.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/board_sbutton.h + * boards/arm/common/stm32/include/board_sbutton.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_sbutton_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_BOARD_SBUTTON_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_BOARD_SBUTTON_H */ diff --git a/boards/arm/stm32/common/include/stm32_amg88xx.h b/boards/arm/common/stm32/include/stm32_amg88xx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_amg88xx.h rename to boards/arm/common/stm32/include/stm32_amg88xx.h index c8cb6fb724f..e11cee5e7e8 100644 --- a/boards/arm/stm32/common/include/stm32_amg88xx.h +++ b/boards/arm/common/stm32/include/stm32_amg88xx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_amg88xx.h + * boards/arm/common/stm32/include/stm32_amg88xx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_amg88xx_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_AMG88XX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_AMG88XX_H */ diff --git a/boards/arm/stm32/common/include/stm32_apa102.h b/boards/arm/common/stm32/include/stm32_apa102.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apa102.h rename to boards/arm/common/stm32/include/stm32_apa102.h index 241fb474b07..ad36c2e6068 100644 --- a/boards/arm/stm32/common/include/stm32_apa102.h +++ b/boards/arm/common/stm32/include/stm32_apa102.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apa102.h + * boards/arm/common/stm32/include/stm32_apa102.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_apa102_initialize(int devno, int spino); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APA102_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APA102_H */ diff --git a/boards/arm/stm32/common/include/stm32_apds9960.h b/boards/arm/common/stm32/include/stm32_apds9960.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_apds9960.h rename to boards/arm/common/stm32/include/stm32_apds9960.h index c38b3a5bdf8..c2fe29bae60 100644 --- a/boards/arm/stm32/common/include/stm32_apds9960.h +++ b/boards/arm/common/stm32/include/stm32_apds9960.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_apds9960.h + * boards/arm/common/stm32/include/stm32_apds9960.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_apds9960_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_APDS9960_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_APDS9960_H */ diff --git a/boards/arm/stm32/common/include/stm32_bh1750.h b/boards/arm/common/stm32/include/stm32_bh1750.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bh1750.h rename to boards/arm/common/stm32/include/stm32_bh1750.h index b9de5a874dd..96be9db21f1 100644 --- a/boards/arm/stm32/common/include/stm32_bh1750.h +++ b/boards/arm/common/stm32/include/stm32_bh1750.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bh1750.h + * boards/arm/common/stm32/include/stm32_bh1750.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_bh1750_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BH1750_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BH1750_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp180.h b/boards/arm/common/stm32/include/stm32_bmp180.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp180.h rename to boards/arm/common/stm32/include/stm32_bmp180.h index 0e963442c9b..6b7865c6e9b 100644 --- a/boards/arm/stm32/common/include/stm32_bmp180.h +++ b/boards/arm/common/stm32/include/stm32_bmp180.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp180.h + * boards/arm/common/stm32/include/stm32_bmp180.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp180_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP180_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP180_H */ diff --git a/boards/arm/stm32/common/include/stm32_bmp280.h b/boards/arm/common/stm32/include/stm32_bmp280.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_bmp280.h rename to boards/arm/common/stm32/include/stm32_bmp280.h index cf558b6791f..22b375eaaa5 100644 --- a/boards/arm/stm32/common/include/stm32_bmp280.h +++ b/boards/arm/common/stm32/include/stm32_bmp280.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_bmp280.h + * boards/arm/common/stm32/include/stm32_bmp280.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_bmp280_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_BMP280_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_BMP280_H */ diff --git a/boards/arm/stm32/common/include/stm32_dhtxx.h b/boards/arm/common/stm32/include/stm32_dhtxx.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_dhtxx.h rename to boards/arm/common/stm32/include/stm32_dhtxx.h index 7c1b5d6a9f4..5b971aa41ae 100644 --- a/boards/arm/stm32/common/include/stm32_dhtxx.h +++ b/boards/arm/common/stm32/include/stm32_dhtxx.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_dhtxx.h + * boards/arm/common/stm32/include/stm32_dhtxx.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_dhtxx_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DHTXX_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DHTXX_H */ diff --git a/boards/arm/stm32/common/include/stm32_drv8266.h b/boards/arm/common/stm32/include/stm32_drv8266.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_drv8266.h rename to boards/arm/common/stm32/include/stm32_drv8266.h index f0252073074..ec0dc22b10c 100644 --- a/boards/arm/stm32/common/include/stm32_drv8266.h +++ b/boards/arm/common/stm32/include/stm32_drv8266.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_drv8266.h + * boards/arm/common/stm32/include/stm32_drv8266.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_drv8825_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DRV8825_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DRV8825_H */ diff --git a/boards/arm/stm32/common/include/stm32_ds1307.h b/boards/arm/common/stm32/include/stm32_ds1307.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ds1307.h rename to boards/arm/common/stm32/include/stm32_ds1307.h index 6baf58c63c4..2e39c16ffba 100644 --- a/boards/arm/stm32/common/include/stm32_ds1307.h +++ b/boards/arm/common/stm32/include/stm32_ds1307.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ds1307.h + * boards/arm/common/stm32/include/stm32_ds1307.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_ds1307_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_DS1307_H */ diff --git a/boards/arm/stm32/common/include/stm32_hcsr04.h b/boards/arm/common/stm32/include/stm32_hcsr04.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_hcsr04.h rename to boards/arm/common/stm32/include/stm32_hcsr04.h index d58e0e50356..59ab41da73b 100644 --- a/boards/arm/stm32/common/include/stm32_hcsr04.h +++ b/boards/arm/common/stm32/include/stm32_hcsr04.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_hcsr04.h + * boards/arm/common/stm32/include/stm32_hcsr04.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_hcsr04_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_HCSR04_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_HCSR04_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm07m1.h b/boards/arm/common/stm32/include/stm32_ihm07m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm07m1.h rename to boards/arm/common/stm32/include/stm32_ihm07m1.h index 6de00e3ec97..32c5601bc73 100644 --- a/boards/arm/stm32/common/include/stm32_ihm07m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm07m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm07m1.h + * boards/arm/common/stm32/include/stm32_ihm07m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm07m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM07M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM07M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm08m1.h b/boards/arm/common/stm32/include/stm32_ihm08m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm08m1.h rename to boards/arm/common/stm32/include/stm32_ihm08m1.h index 3f9738eadb3..eaee68a8875 100644 --- a/boards/arm/stm32/common/include/stm32_ihm08m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm08m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm08m1.h + * boards/arm/common/stm32/include/stm32_ihm08m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm08m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM08M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM08M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ihm16m1.h b/boards/arm/common/stm32/include/stm32_ihm16m1.h similarity index 89% rename from boards/arm/stm32/common/include/stm32_ihm16m1.h rename to boards/arm/common/stm32/include/stm32_ihm16m1.h index 442dc3bb386..76ff0c49b8e 100644 --- a/boards/arm/stm32/common/include/stm32_ihm16m1.h +++ b/boards/arm/common/stm32/include/stm32_ihm16m1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ihm16m1.h + * boards/arm/common/stm32/include/stm32_ihm16m1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H /**************************************************************************** * Included Files @@ -58,4 +58,4 @@ int board_ihm16m1_initialize(struct stm32_foc_adc_s *adc_cfg); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_IHM16M1_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_IHM16M1_H */ diff --git a/boards/arm/stm32/common/include/stm32_ina219.h b/boards/arm/common/stm32/include/stm32_ina219.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ina219.h rename to boards/arm/common/stm32/include/stm32_ina219.h index 4fa91899c3d..20b5a1e4656 100644 --- a/boards/arm/stm32/common/include/stm32_ina219.h +++ b/boards/arm/common/stm32/include/stm32_ina219.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ina219.h + * boards/arm/common/stm32/include/stm32_ina219.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_ina219_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_INA219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_INA219_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_gpio.h rename to boards/arm/common/stm32/include/stm32_kmatrix_gpio.h index 6615fcc9b36..bfad9923c9a 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_gpio.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_gpio.h + * boards/arm/common/stm32/include/stm32_kmatrix_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_GPIO_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_GPIO_H */ diff --git a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_kmatrix_i2c.h rename to boards/arm/common/stm32/include/stm32_kmatrix_i2c.h index 82669a943db..51f6295e5ec 100644 --- a/boards/arm/stm32/common/include/stm32_kmatrix_i2c.h +++ b/boards/arm/common/stm32/include/stm32_kmatrix_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_kmatrix_i2c.h + * boards/arm/common/stm32/include/stm32_kmatrix_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_kmatrix_i2c_initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_KMATRIX_I2C_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_KMATRIX_I2C_H */ diff --git a/boards/arm/stm32/common/include/stm32_l3gd20.h b/boards/arm/common/stm32/include/stm32_l3gd20.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_l3gd20.h rename to boards/arm/common/stm32/include/stm32_l3gd20.h index 8400e119345..edd5c6ca3b5 100644 --- a/boards/arm/stm32/common/include/stm32_l3gd20.h +++ b/boards/arm/common/stm32/include/stm32_l3gd20.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_l3gd20.h + * boards/arm/common/stm32/include/stm32_l3gd20.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_l3gd20_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_L3GD20_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_L3GD20_H */ diff --git a/boards/arm/stm32/common/include/stm32_lcd_backpack.h b/boards/arm/common/stm32/include/stm32_lcd_backpack.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lcd_backpack.h rename to boards/arm/common/stm32/include/stm32_lcd_backpack.h index f0923df0c2a..731e0ed039f 100644 --- a/boards/arm/stm32/common/include/stm32_lcd_backpack.h +++ b/boards/arm/common/stm32/include/stm32_lcd_backpack.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lcd_backpack.h + * boards/arm/common/stm32/include/stm32_lcd_backpack.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H /**************************************************************************** * Included Files @@ -82,4 +82,4 @@ int board_lcd_backpack_init(int devno, int busno, int rows, int cols); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LCD_BACKPACK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LCD_BACKPACK_H */ diff --git a/boards/arm/stm32/common/include/stm32_lis3dsh.h b/boards/arm/common/stm32/include/stm32_lis3dsh.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lis3dsh.h rename to boards/arm/common/stm32/include/stm32_lis3dsh.h index 6c28d6e8b1c..ea92bd41f57 100644 --- a/boards/arm/stm32/common/include/stm32_lis3dsh.h +++ b/boards/arm/common/stm32/include/stm32_lis3dsh.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lis3dsh.h + * boards/arm/common/stm32/include/stm32_lis3dsh.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lis3dsh_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LIS3DSH_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LIS3DSH_H */ diff --git a/boards/arm/stm32/common/include/stm32_lm75.h b/boards/arm/common/stm32/include/stm32_lm75.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_lm75.h rename to boards/arm/common/stm32/include/stm32_lm75.h index 74e846e3a13..339d91433d1 100644 --- a/boards/arm/stm32/common/include/stm32_lm75.h +++ b/boards/arm/common/stm32/include/stm32_lm75.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_lm75.h + * boards/arm/common/stm32/include/stm32_lm75.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_lm75_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_LM75_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_LM75_H */ diff --git a/boards/arm/stm32/common/include/stm32_max31855.h b/boards/arm/common/stm32/include/stm32_max31855.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max31855.h rename to boards/arm/common/stm32/include/stm32_max31855.h index 36196eb6602..243bd335ea9 100644 --- a/boards/arm/stm32/common/include/stm32_max31855.h +++ b/boards/arm/common/stm32/include/stm32_max31855.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max31855.h + * boards/arm/common/stm32/include/stm32_max31855.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_max31855_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX31855_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX31855_H */ diff --git a/boards/arm/stm32/common/include/stm32_max6675.h b/boards/arm/common/stm32/include/stm32_max6675.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_max6675.h rename to boards/arm/common/stm32/include/stm32_max6675.h index 01cdd85bc61..6386116c9df 100644 --- a/boards/arm/stm32/common/include/stm32_max6675.h +++ b/boards/arm/common/stm32/include/stm32_max6675.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max6675.h + * boards/arm/common/stm32/include/stm32_max6675.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H /**************************************************************************** * Included Files @@ -83,4 +83,4 @@ int board_max6675_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX6675_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX6675_H */ diff --git a/boards/arm/stm32/common/include/stm32_max7219_matrix.h b/boards/arm/common/stm32/include/stm32_max7219_matrix.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_max7219_matrix.h rename to boards/arm/common/stm32/include/stm32_max7219_matrix.h index a22addd8543..fea20cbaea3 100644 --- a/boards/arm/stm32/common/include/stm32_max7219_matrix.h +++ b/boards/arm/common/stm32/include/stm32_max7219_matrix.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_max7219_matrix.h + * boards/arm/common/stm32/include/stm32_max7219_matrix.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_max7219_matrix_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MAX7219_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MAX7219_H */ diff --git a/boards/arm/stm32/common/include/stm32_mfrc522.h b/boards/arm/common/stm32/include/stm32_mfrc522.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mfrc522.h rename to boards/arm/common/stm32/include/stm32_mfrc522.h index 6934ea3de6a..46a3956b264 100644 --- a/boards/arm/stm32/common/include/stm32_mfrc522.h +++ b/boards/arm/common/stm32/include/stm32_mfrc522.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mfrc522.h + * boards/arm/common/stm32/include/stm32_mfrc522.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int stm32_mfrc522initialize(const char *devpath); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MFRC522_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MFRC522_H */ diff --git a/boards/arm/stm32/common/include/stm32_mlx90614.h b/boards/arm/common/stm32/include/stm32_mlx90614.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mlx90614.h rename to boards/arm/common/stm32/include/stm32_mlx90614.h index 3f6bd970d8f..5115ae35de7 100644 --- a/boards/arm/stm32/common/include/stm32_mlx90614.h +++ b/boards/arm/common/stm32/include/stm32_mlx90614.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mlx90614.h + * boards/arm/common/stm32/include/stm32_mlx90614.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mlx90614_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MLX90614_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MLX90614_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpl115a.h b/boards/arm/common/stm32/include/stm32_mpl115a.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpl115a.h rename to boards/arm/common/stm32/include/stm32_mpl115a.h index 88c3e3cc5a5..309d39481fd 100644 --- a/boards/arm/stm32/common/include/stm32_mpl115a.h +++ b/boards/arm/common/stm32/include/stm32_mpl115a.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpl115a.h + * boards/arm/common/stm32/include/stm32_mpl115a.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpl115a_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPL115A_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPL115A_H */ diff --git a/boards/arm/stm32/common/include/stm32_mpr121.h b/boards/arm/common/stm32/include/stm32_mpr121.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_mpr121.h rename to boards/arm/common/stm32/include/stm32_mpr121.h index 185f2aac544..a35b1c02476 100644 --- a/boards/arm/stm32/common/include/stm32_mpr121.h +++ b/boards/arm/common/stm32/include/stm32_mpr121.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mpr121.h + * boards/arm/common/stm32/include/stm32_mpr121.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ int board_mpr121_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MPR121_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MPR121_H */ diff --git a/boards/arm/stm32/common/include/stm32_ms5611.h b/boards/arm/common/stm32/include/stm32_ms5611.h similarity index 94% rename from boards/arm/stm32/common/include/stm32_ms5611.h rename to boards/arm/common/stm32/include/stm32_ms5611.h index f5a27d33949..2e9c63e68b0 100644 --- a/boards/arm/stm32/common/include/stm32_ms5611.h +++ b/boards/arm/common/stm32/include/stm32_ms5611.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ms5611.h + * boards/arm/common/stm32/include/stm32_ms5611.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MS5611_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MS5611_H /**************************************************************************** * Included Files diff --git a/boards/arm/stm32/common/include/stm32_mt6816.h b/boards/arm/common/stm32/include/stm32_mt6816.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_mt6816.h rename to boards/arm/common/stm32/include/stm32_mt6816.h index 2497d13aa9a..ff6447fded5 100644 --- a/boards/arm/stm32/common/include/stm32_mt6816.h +++ b/boards/arm/common/stm32/include/stm32_mt6816.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_mt6816.h + * boards/arm/common/stm32/include/stm32_mt6816.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_mt6816_initialize(int devno, int spi_busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_MT6816_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_MT6816_H */ diff --git a/boards/arm/stm32/common/include/stm32_nrf24l01.h b/boards/arm/common/stm32/include/stm32_nrf24l01.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_nrf24l01.h rename to boards/arm/common/stm32/include/stm32_nrf24l01.h index e5207c6d16d..8a676add6ba 100644 --- a/boards/arm/stm32/common/include/stm32_nrf24l01.h +++ b/boards/arm/common/stm32/include/stm32_nrf24l01.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nrf24l01.h + * boards/arm/common/stm32/include/stm32_nrf24l01.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H /**************************************************************************** * Included Files @@ -78,4 +78,4 @@ int board_nrf24l01_initialize(int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NRF24L01_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NRF24L01_H */ diff --git a/boards/arm/stm32/common/include/stm32_nunchuck.h b/boards/arm/common/stm32/include/stm32_nunchuck.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_nunchuck.h rename to boards/arm/common/stm32/include/stm32_nunchuck.h index 138fab2feff..b08f8ee6b17 100644 --- a/boards/arm/stm32/common/include/stm32_nunchuck.h +++ b/boards/arm/common/stm32/include/stm32_nunchuck.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_nunchuck.h + * boards/arm/common/stm32/include/stm32_nunchuck.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_nunchuck_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_NUNCHUCK_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_NUNCHUCK_H */ diff --git a/boards/arm/stm32/common/include/stm32_ssd1306.h b/boards/arm/common/stm32/include/stm32_ssd1306.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_ssd1306.h rename to boards/arm/common/stm32/include/stm32_ssd1306.h index d5e2d527996..a23b2d776ad 100644 --- a/boards/arm/stm32/common/include/stm32_ssd1306.h +++ b/boards/arm/common/stm32/include/stm32_ssd1306.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ssd1306.h + * boards/arm/common/stm32/include/stm32_ssd1306.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ struct lcd_dev_s *board_ssd1306_getdev(void); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_SSD1306_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_SSD1306_H */ diff --git a/boards/arm/stm32/common/include/stm32_tone.h b/boards/arm/common/stm32/include/stm32_tone.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_tone.h rename to boards/arm/common/stm32/include/stm32_tone.h index 1834af76bab..5306c10f308 100644 --- a/boards/arm/stm32/common/include/stm32_tone.h +++ b/boards/arm/common/stm32/include/stm32_tone.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_tone.h + * boards/arm/common/stm32/include/stm32_tone.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H /**************************************************************************** * Included Files @@ -75,4 +75,4 @@ int board_tone_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_TONE_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_TONE_H */ diff --git a/boards/arm/stm32/common/include/stm32_veml6070.h b/boards/arm/common/stm32/include/stm32_veml6070.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_veml6070.h rename to boards/arm/common/stm32/include/stm32_veml6070.h index 3b3a6899971..ab73c1504dd 100644 --- a/boards/arm/stm32/common/include/stm32_veml6070.h +++ b/boards/arm/common/stm32/include/stm32_veml6070.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_veml6070.h + * boards/arm/common/stm32/include/stm32_veml6070.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_veml6070_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_VEML6070_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_VEML6070_H */ diff --git a/boards/arm/stm32/common/include/stm32_ws2812.h b/boards/arm/common/stm32/include/stm32_ws2812.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_ws2812.h rename to boards/arm/common/stm32/include/stm32_ws2812.h index ef6dfb8d8ab..76fa9b5724b 100644 --- a/boards/arm/stm32/common/include/stm32_ws2812.h +++ b/boards/arm/common/stm32/include/stm32_ws2812.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_ws2812.h + * boards/arm/common/stm32/include/stm32_ws2812.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H /**************************************************************************** * Included Files @@ -84,4 +84,4 @@ int board_ws2812_initialize(int devno, int spino, uint16_t nleds); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_WS2812_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_WS2812_H */ diff --git a/boards/arm/stm32/common/include/stm32_xen1210.h b/boards/arm/common/stm32/include/stm32_xen1210.h similarity index 92% rename from boards/arm/stm32/common/include/stm32_xen1210.h rename to boards/arm/common/stm32/include/stm32_xen1210.h index 19ed0c4246e..a6b8e30955d 100644 --- a/boards/arm/stm32/common/include/stm32_xen1210.h +++ b/boards/arm/common/stm32/include/stm32_xen1210.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_xen1210.h + * boards/arm/common/stm32/include/stm32_xen1210.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H /**************************************************************************** * Included Files @@ -80,4 +80,4 @@ int board_xen1210_initialize(int devno, int busno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_XEN1210_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_XEN1210_H */ diff --git a/boards/arm/stm32/common/include/stm32_zerocross.h b/boards/arm/common/stm32/include/stm32_zerocross.h similarity index 91% rename from boards/arm/stm32/common/include/stm32_zerocross.h rename to boards/arm/common/stm32/include/stm32_zerocross.h index ae07c6ddb5e..2d92fd900be 100644 --- a/boards/arm/stm32/common/include/stm32_zerocross.h +++ b/boards/arm/common/stm32/include/stm32_zerocross.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/include/stm32_zerocross.h + * boards/arm/common/stm32/include/stm32_zerocross.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H -#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H +#ifndef __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H +#define __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H /**************************************************************************** * Included Files @@ -72,4 +72,4 @@ int board_zerocross_initialize(int devno); } #endif -#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_ZEROCROSS_H */ +#endif /* __BOARDS_ARM_COMMON_STM32_INCLUDE_STM32_ZEROCROSS_H */ diff --git a/boards/arm/stm32/common/src/CMakeLists.txt b/boards/arm/common/stm32/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/common/src/CMakeLists.txt rename to boards/arm/common/stm32/src/CMakeLists.txt index c7d9426af29..1f9b3837368 100644 --- a/boards/arm/stm32/common/src/CMakeLists.txt +++ b/boards/arm/common/stm32/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/common/src/CMakeLists.txt +# boards/arm/common/stm32/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -92,10 +92,14 @@ endif() if(CONFIG_SENSORS_QENCODER) if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) + list(APPEND SRCS board_qencoder.c) endif() endif() +if(CONFIG_PWM AND NOT EXISTS ${NUTTX_BOARD_DIR}/src/stm32_pwm.c) + list(APPEND SRCS board_pwm.c) +endif() + if(CONFIG_SENSORS_INA219) list(APPEND SRCS stm32_ina219.c) endif() diff --git a/boards/arm/stm32/common/src/Make.defs b/boards/arm/common/stm32/src/Make.defs similarity index 87% rename from boards/arm/stm32/common/src/Make.defs rename to boards/arm/common/stm32/src/Make.defs index 5b1f8556d76..9470fe63aac 100644 --- a/boards/arm/stm32/common/src/Make.defs +++ b/boards/arm/common/stm32/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32/common/src/Make.defs +# boards/arm/common/stm32/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,6 +22,8 @@ ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 + ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += stm32_bmp180.c endif @@ -100,7 +102,13 @@ endif ifeq ($(CONFIG_SENSORS_QENCODER),y) ifeq ($(CONFIG_STM32_QE),y) - CSRCS += stm32_qencoder.c + CSRCS += board_qencoder.c + endif +endif + +ifeq ($(CONFIG_PWM),y) + ifeq (,$(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)stm32_pwm.c)) + CSRCS += board_pwm.c endif endif @@ -184,8 +192,9 @@ ifeq ($(CONFIG_INPUT_KMATRIX_I2C),y) CSRCS += stm32_kmatrix_i2c.c endif -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src +DEPPATH += --dep-path $(STM32_BOARD_COMMON_DIR)$(DELIM)src +VPATH += :$(STM32_BOARD_COMMON_DIR)$(DELIM)src +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_BOARD_COMMON_DIR)$(DELIM)src endif diff --git a/boards/arm/stm32/common/src/board_hall3ph.c b/boards/arm/common/stm32/src/board_hall3ph.c similarity index 98% rename from boards/arm/stm32/common/src/board_hall3ph.c rename to boards/arm/common/stm32/src/board_hall3ph.c index f96d5a953f3..3ce8efa7607 100644 --- a/boards/arm/stm32/common/src/board_hall3ph.c +++ b/boards/arm/common/stm32/src/board_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/board_hall3ph.c + * boards/arm/common/stm32/src/board_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/board_pwm.c b/boards/arm/common/stm32/src/board_pwm.c similarity index 98% rename from boards/arm/stm32f0l0g0/common/src/board_pwm.c rename to boards/arm/common/stm32/src/board_pwm.c index d26772a5dc1..fdc3ad58f42 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_pwm.c +++ b/boards/arm/common/stm32/src/board_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_pwm.c + * boards/arm/common/stm32/src/board_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c b/boards/arm/common/stm32/src/board_qencoder.c similarity index 96% rename from boards/arm/stm32f0l0g0/common/src/board_qencoder.c rename to boards/arm/common/stm32/src/board_qencoder.c index 6f7e6260977..f67c7d857f4 100644 --- a/boards/arm/stm32f0l0g0/common/src/board_qencoder.c +++ b/boards/arm/common/stm32/src/board_qencoder.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/board_qencoder.c + * boards/arm/common/stm32/src/board_qencoder.c * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,7 @@ #include #include -#include +#include #include #include diff --git a/boards/arm/stm32/common/src/stm32_amg88xx.c b/boards/arm/common/stm32/src/stm32_amg88xx.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_amg88xx.c rename to boards/arm/common/stm32/src/stm32_amg88xx.c index 4760fd947f1..995a28e1412 100644 --- a/boards/arm/stm32/common/src/stm32_amg88xx.c +++ b/boards/arm/common/stm32/src/stm32_amg88xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_amg88xx.c + * boards/arm/common/stm32/src/stm32_amg88xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_apa102.c b/boards/arm/common/stm32/src/stm32_apa102.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_apa102.c rename to boards/arm/common/stm32/src/stm32_apa102.c index 5b19432385c..5de33d0dc6b 100644 --- a/boards/arm/stm32/common/src/stm32_apa102.c +++ b/boards/arm/common/stm32/src/stm32_apa102.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_apa102.c + * boards/arm/common/stm32/src/stm32_apa102.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_apds9960.c b/boards/arm/common/stm32/src/stm32_apds9960.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_apds9960.c rename to boards/arm/common/stm32/src/stm32_apds9960.c index 902cac423d5..ff709d69497 100644 --- a/boards/arm/stm32/common/src/stm32_apds9960.c +++ b/boards/arm/common/stm32/src/stm32_apds9960.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_apds9960.c + * boards/arm/common/stm32/src/stm32_apds9960.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bh1750.c b/boards/arm/common/stm32/src/stm32_bh1750.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bh1750.c rename to boards/arm/common/stm32/src/stm32_bh1750.c index 4a21eee85c3..d8f742f357b 100644 --- a/boards/arm/stm32/common/src/stm32_bh1750.c +++ b/boards/arm/common/stm32/src/stm32_bh1750.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bh1750.c + * boards/arm/common/stm32/src/stm32_bh1750.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp180.c b/boards/arm/common/stm32/src/stm32_bmp180.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp180.c rename to boards/arm/common/stm32/src/stm32_bmp180.c index 35b6bf15a32..3301d4baf1b 100644 --- a/boards/arm/stm32/common/src/stm32_bmp180.c +++ b/boards/arm/common/stm32/src/stm32_bmp180.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp180.c + * boards/arm/common/stm32/src/stm32_bmp180.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_bmp280.c b/boards/arm/common/stm32/src/stm32_bmp280.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_bmp280.c rename to boards/arm/common/stm32/src/stm32_bmp280.c index c42be6b3ec8..2d748ac1128 100644 --- a/boards/arm/stm32/common/src/stm32_bmp280.c +++ b/boards/arm/common/stm32/src/stm32_bmp280.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_bmp280.c + * boards/arm/common/stm32/src/stm32_bmp280.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_dhtxx.c b/boards/arm/common/stm32/src/stm32_dhtxx.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_dhtxx.c rename to boards/arm/common/stm32/src/stm32_dhtxx.c index 017f7de8f14..24c82362750 100644 --- a/boards/arm/stm32/common/src/stm32_dhtxx.c +++ b/boards/arm/common/stm32/src/stm32_dhtxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_dhtxx.c + * boards/arm/common/stm32/src/stm32_dhtxx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_drv8825.c b/boards/arm/common/stm32/src/stm32_drv8825.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_drv8825.c rename to boards/arm/common/stm32/src/stm32_drv8825.c index e11b644d947..60187a9eb9f 100644 --- a/boards/arm/stm32/common/src/stm32_drv8825.c +++ b/boards/arm/common/stm32/src/stm32_drv8825.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_drv8825.c + * boards/arm/common/stm32/src/stm32_drv8825.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ds1307.c b/boards/arm/common/stm32/src/stm32_ds1307.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ds1307.c rename to boards/arm/common/stm32/src/stm32_ds1307.c index 6d34e5255ca..fb7cf4129b2 100644 --- a/boards/arm/stm32/common/src/stm32_ds1307.c +++ b/boards/arm/common/stm32/src/stm32_ds1307.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ds1307.c + * boards/arm/common/stm32/src/stm32_ds1307.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_hcsr04.c b/boards/arm/common/stm32/src/stm32_hcsr04.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_hcsr04.c rename to boards/arm/common/stm32/src/stm32_hcsr04.c index 7f8c235f0de..3f2d6ae229b 100644 --- a/boards/arm/stm32/common/src/stm32_hcsr04.c +++ b/boards/arm/common/stm32/src/stm32_hcsr04.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_hcsr04.c + * boards/arm/common/stm32/src/stm32_hcsr04.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm07m1.c b/boards/arm/common/stm32/src/stm32_ihm07m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm07m1.c rename to boards/arm/common/stm32/src/stm32_ihm07m1.c index 39e550affaa..6fa02180e41 100644 --- a/boards/arm/stm32/common/src/stm32_ihm07m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm07m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm07m1.c + * boards/arm/common/stm32/src/stm32_ihm07m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm08m1.c b/boards/arm/common/stm32/src/stm32_ihm08m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm08m1.c rename to boards/arm/common/stm32/src/stm32_ihm08m1.c index 97a12482b59..2c5b1b366a8 100644 --- a/boards/arm/stm32/common/src/stm32_ihm08m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm08m1.c + * boards/arm/common/stm32/src/stm32_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ihm16m1.c b/boards/arm/common/stm32/src/stm32_ihm16m1.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_ihm16m1.c rename to boards/arm/common/stm32/src/stm32_ihm16m1.c index d3d6ccb838e..6bf525ca0b7 100644 --- a/boards/arm/stm32/common/src/stm32_ihm16m1.c +++ b/boards/arm/common/stm32/src/stm32_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ihm16m1.c + * boards/arm/common/stm32/src/stm32_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ina219.c b/boards/arm/common/stm32/src/stm32_ina219.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ina219.c rename to boards/arm/common/stm32/src/stm32_ina219.c index 98968b1adbc..20b1e565dad 100644 --- a/boards/arm/stm32/common/src/stm32_ina219.c +++ b/boards/arm/common/stm32/src/stm32_ina219.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ina219.c + * boards/arm/common/stm32/src/stm32_ina219.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2018 Erle Robotics (Juan Flores Muñoz). diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_gpio.c rename to boards/arm/common/stm32/src/stm32_kmatrix_gpio.c index d76d94fa0f3..7f5a68d0acd 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_gpio.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_gpio.c + * boards/arm/common/stm32/src/stm32_kmatrix_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_kmatrix_i2c.c rename to boards/arm/common/stm32/src/stm32_kmatrix_i2c.c index 358c1d5584f..d4978eca0a5 100644 --- a/boards/arm/stm32/common/src/stm32_kmatrix_i2c.c +++ b/boards/arm/common/stm32/src/stm32_kmatrix_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_kmatrix_i2c.c + * boards/arm/common/stm32/src/stm32_kmatrix_i2c.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_l3gd20.c b/boards/arm/common/stm32/src/stm32_l3gd20.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_l3gd20.c rename to boards/arm/common/stm32/src/stm32_l3gd20.c index 5cbd5021d84..145060bd52d 100644 --- a/boards/arm/stm32/common/src/stm32_l3gd20.c +++ b/boards/arm/common/stm32/src/stm32_l3gd20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_l3gd20.c + * boards/arm/common/stm32/src/stm32_l3gd20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lcd_backpack.c b/boards/arm/common/stm32/src/stm32_lcd_backpack.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lcd_backpack.c rename to boards/arm/common/stm32/src/stm32_lcd_backpack.c index c288d2b4dd6..b65a3fcaaec 100644 --- a/boards/arm/stm32/common/src/stm32_lcd_backpack.c +++ b/boards/arm/common/stm32/src/stm32_lcd_backpack.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lcd_backpack.c + * boards/arm/common/stm32/src/stm32_lcd_backpack.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lis3dsh.c b/boards/arm/common/stm32/src/stm32_lis3dsh.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lis3dsh.c rename to boards/arm/common/stm32/src/stm32_lis3dsh.c index 03d3fa84ad4..f1cfaa31ce3 100644 --- a/boards/arm/stm32/common/src/stm32_lis3dsh.c +++ b/boards/arm/common/stm32/src/stm32_lis3dsh.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lis3dsh.c + * boards/arm/common/stm32/src/stm32_lis3dsh.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_lm75.c b/boards/arm/common/stm32/src/stm32_lm75.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_lm75.c rename to boards/arm/common/stm32/src/stm32_lm75.c index ce7c9f796e6..6f01942a00a 100644 --- a/boards/arm/stm32/common/src/stm32_lm75.c +++ b/boards/arm/common/stm32/src/stm32_lm75.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_lm75.c + * boards/arm/common/stm32/src/stm32_lm75.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max31855.c b/boards/arm/common/stm32/src/stm32_max31855.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max31855.c rename to boards/arm/common/stm32/src/stm32_max31855.c index b520888c597..ae21864b095 100644 --- a/boards/arm/stm32/common/src/stm32_max31855.c +++ b/boards/arm/common/stm32/src/stm32_max31855.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max31855.c + * boards/arm/common/stm32/src/stm32_max31855.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max6675.c b/boards/arm/common/stm32/src/stm32_max6675.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max6675.c rename to boards/arm/common/stm32/src/stm32_max6675.c index bd6b20d0e0f..4082eea356a 100644 --- a/boards/arm/stm32/common/src/stm32_max6675.c +++ b/boards/arm/common/stm32/src/stm32_max6675.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max6675.c + * boards/arm/common/stm32/src/stm32_max6675.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_max7219_matrix.c b/boards/arm/common/stm32/src/stm32_max7219_matrix.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_max7219_matrix.c rename to boards/arm/common/stm32/src/stm32_max7219_matrix.c index 4e5ac76473b..0ee46493a9c 100644 --- a/boards/arm/stm32/common/src/stm32_max7219_matrix.c +++ b/boards/arm/common/stm32/src/stm32_max7219_matrix.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_max7219_matrix.c + * boards/arm/common/stm32/src/stm32_max7219_matrix.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mfrc522.c b/boards/arm/common/stm32/src/stm32_mfrc522.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mfrc522.c rename to boards/arm/common/stm32/src/stm32_mfrc522.c index fc0d5bdf40e..0da85237c69 100644 --- a/boards/arm/stm32/common/src/stm32_mfrc522.c +++ b/boards/arm/common/stm32/src/stm32_mfrc522.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mfrc522.c + * boards/arm/common/stm32/src/stm32_mfrc522.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mlx90614.c b/boards/arm/common/stm32/src/stm32_mlx90614.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mlx90614.c rename to boards/arm/common/stm32/src/stm32_mlx90614.c index 3d6944c30fd..984422d9149 100644 --- a/boards/arm/stm32/common/src/stm32_mlx90614.c +++ b/boards/arm/common/stm32/src/stm32_mlx90614.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mlx90614.c + * boards/arm/common/stm32/src/stm32_mlx90614.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpl115a.c b/boards/arm/common/stm32/src/stm32_mpl115a.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mpl115a.c rename to boards/arm/common/stm32/src/stm32_mpl115a.c index ad467fd5d16..f246d171684 100644 --- a/boards/arm/stm32/common/src/stm32_mpl115a.c +++ b/boards/arm/common/stm32/src/stm32_mpl115a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpl115a.c + * boards/arm/common/stm32/src/stm32_mpl115a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mpr121.c b/boards/arm/common/stm32/src/stm32_mpr121.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_mpr121.c rename to boards/arm/common/stm32/src/stm32_mpr121.c index bd0d0d5ad5e..29a5049dfad 100644 --- a/boards/arm/stm32/common/src/stm32_mpr121.c +++ b/boards/arm/common/stm32/src/stm32_mpr121.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mpr121.c + * boards/arm/common/stm32/src/stm32_mpr121.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ms5611.c b/boards/arm/common/stm32/src/stm32_ms5611.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ms5611.c rename to boards/arm/common/stm32/src/stm32_ms5611.c index 9e230e86afb..b38b0097608 100644 --- a/boards/arm/stm32/common/src/stm32_ms5611.c +++ b/boards/arm/common/stm32/src/stm32_ms5611.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ms5611.c + * boards/arm/common/stm32/src/stm32_ms5611.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_mt6816.c b/boards/arm/common/stm32/src/stm32_mt6816.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_mt6816.c rename to boards/arm/common/stm32/src/stm32_mt6816.c index 834e1203850..41757f28677 100644 --- a/boards/arm/stm32/common/src/stm32_mt6816.c +++ b/boards/arm/common/stm32/src/stm32_mt6816.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_mt6816.c + * boards/arm/common/stm32/src/stm32_mt6816.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_nrf24l01.c b/boards/arm/common/stm32/src/stm32_nrf24l01.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_nrf24l01.c rename to boards/arm/common/stm32/src/stm32_nrf24l01.c index 62560e12443..9b086e8c3b3 100644 --- a/boards/arm/stm32/common/src/stm32_nrf24l01.c +++ b/boards/arm/common/stm32/src/stm32_nrf24l01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_nrf24l01.c + * boards/arm/common/stm32/src/stm32_nrf24l01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_nunchuck.c b/boards/arm/common/stm32/src/stm32_nunchuck.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_nunchuck.c rename to boards/arm/common/stm32/src/stm32_nunchuck.c index e25d7fe770a..27b4ba76b7f 100644 --- a/boards/arm/stm32/common/src/stm32_nunchuck.c +++ b/boards/arm/common/stm32/src/stm32_nunchuck.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_nunchuck.c + * boards/arm/common/stm32/src/stm32_nunchuck.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_sbutton.c b/boards/arm/common/stm32/src/stm32_sbutton.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_sbutton.c rename to boards/arm/common/stm32/src/stm32_sbutton.c index 5f2e52a9ac8..0659794a375 100644 --- a/boards/arm/stm32/common/src/stm32_sbutton.c +++ b/boards/arm/common/stm32/src/stm32_sbutton.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_sbutton.c + * boards/arm/common/stm32/src/stm32_sbutton.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c b/boards/arm/common/stm32/src/stm32_ssd1306.c similarity index 98% rename from boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c rename to boards/arm/common/stm32/src/stm32_ssd1306.c index cf14f06f943..1c73555da92 100644 --- a/boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c +++ b/boards/arm/common/stm32/src/stm32_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/common/src/stm32_ssd1306.c + * boards/arm/common/stm32/src/stm32_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * @@ -90,6 +90,9 @@ int board_ssd1306_initialize(int busno) /* And turn the OLED on */ g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); + + ssd1306_fill(g_lcddev, 0xff); + return OK; } } @@ -138,9 +141,6 @@ int board_ssd1306_initialize(int busno) /* And turn the OLED on */ g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - - ssd1306_fill(g_lcddev, 0xff); - return OK; } } diff --git a/boards/arm/stm32/common/src/stm32_tone.c b/boards/arm/common/stm32/src/stm32_tone.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_tone.c rename to boards/arm/common/stm32/src/stm32_tone.c index 58bbcd22242..178f8c1504c 100644 --- a/boards/arm/stm32/common/src/stm32_tone.c +++ b/boards/arm/common/stm32/src/stm32_tone.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_tone.c + * boards/arm/common/stm32/src/stm32_tone.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_veml6070.c b/boards/arm/common/stm32/src/stm32_veml6070.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_veml6070.c rename to boards/arm/common/stm32/src/stm32_veml6070.c index e5b38b9ac9b..b5e918973f2 100644 --- a/boards/arm/stm32/common/src/stm32_veml6070.c +++ b/boards/arm/common/stm32/src/stm32_veml6070.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_veml6070.c + * boards/arm/common/stm32/src/stm32_veml6070.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_ws2812.c b/boards/arm/common/stm32/src/stm32_ws2812.c similarity index 98% rename from boards/arm/stm32/common/src/stm32_ws2812.c rename to boards/arm/common/stm32/src/stm32_ws2812.c index 640fb1e6308..d206941ed91 100644 --- a/boards/arm/stm32/common/src/stm32_ws2812.c +++ b/boards/arm/common/stm32/src/stm32_ws2812.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_ws2812.c + * boards/arm/common/stm32/src/stm32_ws2812.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_xen1210.c b/boards/arm/common/stm32/src/stm32_xen1210.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_xen1210.c rename to boards/arm/common/stm32/src/stm32_xen1210.c index 1dcb2a2787e..4b4311933c7 100644 --- a/boards/arm/stm32/common/src/stm32_xen1210.c +++ b/boards/arm/common/stm32/src/stm32_xen1210.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_xen1210.c + * boards/arm/common/stm32/src/stm32_xen1210.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/src/stm32_zerocross.c b/boards/arm/common/stm32/src/stm32_zerocross.c similarity index 99% rename from boards/arm/stm32/common/src/stm32_zerocross.c rename to boards/arm/common/stm32/src/stm32_zerocross.c index c0a8a3900f4..660719d6fb9 100644 --- a/boards/arm/stm32/common/src/stm32_zerocross.c +++ b/boards/arm/common/stm32/src/stm32_zerocross.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/common/src/stm32_zerocross.c + * boards/arm/common/stm32/src/stm32_zerocross.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/common/CMakeLists.txt b/boards/arm/stm32/common/CMakeLists.txt index 48a2ca9e109..2d59a76459e 100644 --- a/boards/arm/stm32/common/CMakeLists.txt +++ b/boards/arm/stm32/common/CMakeLists.txt @@ -20,5 +20,6 @@ # # ############################################################################## -add_subdirectory(src) -target_include_directories(board PRIVATE include) +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32/common/Kconfig b/boards/arm/stm32/common/Kconfig index 3e611724880..5c48f62a025 100644 --- a/boards/arm/stm32/common/Kconfig +++ b/boards/arm/stm32/common/Kconfig @@ -3,69 +3,4 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if STM32_FOC - -menuconfig BOARD_STM32_IHM07M1 - bool "X-NUCLEO-IHM07M1 board support" - default n - ---help--- - Board based on the L6230 DMOS driver. - -if BOARD_STM32_IHM07M1 - -config BOARD_STM32_IHM07M1_VBUS - bool "X-NUCLEO-IHM07M1 board VBUS sense" - default n - -config BOARD_STM32_IHM07M1_POT - bool "X-NUCLEO-IHM07M1 board POT support" - default n - -endif # BOARD_STM32_IHM07M1 - -menuconfig BOARD_STM32_IHM08M1 - bool "X-NUCLEO-IHM08M1 board support" - default n - select STM32_FOC_HAS_PWM_COMPLEMENTARY - ---help--- - Board based on the discrete L6398 gate drivers and STL220N6F7 POWER MOSFETs. - -if BOARD_STM32_IHM08M1 - -config BOARD_STM32_IHM08M1_VBUS - bool "X-NUCLEO-IHM08M1 board VBUS sense" - default n - -config BOARD_STM32_IHM08M1_POT - bool "X-NUCLEO-IHM08M1 board POT support" - default n - -endif # BOARD_STM32_IHM08M1 - -menuconfig BOARD_STM32_IHM16M1 - bool "X-NUCLEO-IHM16M1 board support" - default n - ---help--- - Board based on the STSPIN830 three-phase brushless motor driver. - -if BOARD_STM32_IHM16M1 - -config BOARD_STM32_IHM16M1_VBUS - bool "X-NUCLEO-IHM16M1 board VBUS sense" - default n - -config BOARD_STM32_IHM16M1_POT - bool "X-NUCLEO-IHM16M1 board POT support" - default n - -endif # BOARD_STM32_IHM16M1 - -endif # STM32_FOC - -if SENSORS_HALL3PHASE - -config BOARD_STM32_HALL3PHASE_SAMPLES - int "3-phase Hall effect sensor number of samples" - default 10 - -endif # SENSORS_HALL3PHASE +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32/common/Makefile b/boards/arm/stm32/common/Makefile index c6b78fa6a47..801cf99b184 100644 --- a/boards/arm/stm32/common/Makefile +++ b/boards/arm/stm32/common/Makefile @@ -22,14 +22,17 @@ include $(TOPDIR)/Make.defs +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + include board/Make.defs -include src/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs DEPPATH += --dep-path board -DEPPATH += --dep-path src include $(TOPDIR)/boards/Board.mk ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src BOARDDIR = $(ARCHSRCDIR)$(DELIM)board CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32/common/src/stm32_qencoder.c b/boards/arm/stm32/common/src/stm32_qencoder.c deleted file mode 100644 index c701ecc0564..00000000000 --- a/boards/arm/stm32/common/src/stm32_qencoder.c +++ /dev/null @@ -1,68 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_qencoder.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "arm_internal.h" -#include "stm32_qencoder.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno) -{ - int ret; - char devpath[12]; - - /* Initialize a quadrature encoder interface. */ - - sninfo("Initializing the quadrature encoder using TIM%d\n", timerno); - snprintf(devpath, sizeof(devpath), "/dev/qe%d", devno); - ret = stm32_qeinitialize(devpath, timerno); - if (ret < 0) - { - snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); - } - - return ret; -} diff --git a/boards/arm/stm32/common/src/stm32_ssd1306.c b/boards/arm/stm32/common/src/stm32_ssd1306.c deleted file mode 100644 index 093699e26b8..00000000000 --- a/boards/arm/stm32/common/src/stm32_ssd1306.c +++ /dev/null @@ -1,160 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/common/src/stm32_ssd1306.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include -#include - -#include "stm32_i2c.h" -#include "stm32_spi.h" - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct lcd_dev_s *g_lcddev; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. I2C version. - * - * Input Parameters: - * busno - The I2C bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_I2C -int board_ssd1306_initialize(int busno) -{ - struct i2c_master_s *i2c; - const int devno = 0; - - /* Initialize I2C */ - - i2c = stm32_i2cbus_initialize(busno); - if (!i2c) - { - lcderr("ERROR: Failed to initialize I2C port %d\n", busno); - return -ENODEV; - } - - /* Bind the I2C port to the OLED */ - - g_lcddev = ssd1306_initialize(i2c, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind I2C port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound I2C port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device. SPI version. - * - * Input Parameters: - * busno - The SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ -#ifdef CONFIG_LCD_SSD1306_SPI -int board_ssd1306_initialize(int busno) -{ - struct spi_dev_s *spi; - const int devno = 0; - - /* Initialize SPI */ - - spi = stm32_spibus_initialize(busno); - if (!spi) - { - lcderr("ERROR: Failed to initialize SPI port %d\n", busno); - return -ENODEV; - } - - /* Bind the SPI port to the OLED */ - - g_lcddev = ssd1306_initialize(spi, NULL, devno); - if (!g_lcddev) - { - lcderr("ERROR: Failed to bind SPI port %d to OLED %d\n", busno, devno); - return -ENODEV; - } - else - { - lcdinfo("Bound SPI port %d to OLED %d\n", busno, devno); - - /* And turn the OLED on */ - - g_lcddev->setpower(g_lcddev, CONFIG_LCD_MAXPOWER); - return OK; - } -} -#endif - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void) -{ - return g_lcddev; -} diff --git a/boards/arm/stm32f0l0g0/common/CMakeLists.txt b/boards/arm/stm32f0l0g0/common/CMakeLists.txt index 4741419517f..3168617cea3 100644 --- a/boards/arm/stm32f0l0g0/common/CMakeLists.txt +++ b/boards/arm/stm32f0l0g0/common/CMakeLists.txt @@ -20,5 +20,6 @@ # # ############################################################################## -add_subdirectory(src) -target_include_directories(board PRIVATE include) +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32f0l0g0/common/Kconfig b/boards/arm/stm32f0l0g0/common/Kconfig index 18c7905aed7..5c48f62a025 100644 --- a/boards/arm/stm32f0l0g0/common/Kconfig +++ b/boards/arm/stm32f0l0g0/common/Kconfig @@ -3,3 +3,4 @@ # see the file kconfig-language.txt in the NuttX tools repository. # +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f0l0g0/common/Makefile b/boards/arm/stm32f0l0g0/common/Makefile index 7318baae08c..43855190fc6 100644 --- a/boards/arm/stm32f0l0g0/common/Makefile +++ b/boards/arm/stm32f0l0g0/common/Makefile @@ -22,14 +22,17 @@ include $(TOPDIR)/Make.defs +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + include board/Make.defs -include src/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs DEPPATH += --dep-path board -DEPPATH += --dep-path src include $(TOPDIR)/boards/Board.mk ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src BOARDDIR = $(ARCHSRCDIR)$(DELIM)board CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h b/boards/arm/stm32f0l0g0/common/include/board_qencoder.h deleted file mode 100644 index b16fbb020d0..00000000000 --- a/boards/arm/stm32f0l0g0/common/include/board_qencoder.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/board_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_qencoder_initialize - * - * Description: - * Initialize the quadrature encoder driver for the given timer - * - ****************************************************************************/ - -int board_qencoder_initialize(int devno, int timerno); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_BOARD_QENCODER_H */ diff --git a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h b/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h deleted file mode 100644 index 3831d23592b..00000000000 --- a/boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32f0l0g0/common/include/stm32_ssd1306.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H -#define __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ssd1306_initialize - * - * Description: - * Initialize and register the device - * - * Input Parameters: - * busno - The I2C or SPI bus number - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -int board_ssd1306_initialize(int busno); - -/**************************************************************************** - * Name: board_ssd1306_getdev - * - * Description: - * Get the SSD1306 device driver instance - * - * Returned Value: - * Pointer to the instance - * - ****************************************************************************/ - -struct lcd_dev_s *board_ssd1306_getdev(void); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __BOARDS_ARM_STM32F0L0G0_COMMON_INCLUDE_STM32_SSD1306_H */ From 699ffc3271ceb313aa091a41cbf440154053e7e2 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Sun, 31 May 2026 09:34:14 +0200 Subject: [PATCH 149/268] boards/arm/stm32l4: build through common STM32 board infrastructure Add boards/arm/stm32l4/common so STM32L4 boards build through the shared STM32 board-common tree (boards/arm/common/stm32), like the other split STM32 families. Convert each STM32L4 board's src/Makefile to src/Make.defs so the per-board sources are pulled in by the common board Makefile. Signed-off-by: raiden00pl --- .../src/{Makefile => Make.defs} | 4 +- boards/arm/stm32l4/common/CMakeLists.txt | 25 ++++++++++++ boards/arm/stm32l4/common/Kconfig | 6 +++ boards/arm/stm32l4/common/Makefile | 38 +++++++++++++++++++ .../nucleo-l432kc/src/{Makefile => Make.defs} | 4 +- .../nucleo-l452re/src/{Makefile => Make.defs} | 4 +- .../nucleo-l476rg/src/{Makefile => Make.defs} | 4 +- .../nucleo-l496zg/src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- .../stm32l476-mdk/src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- .../src/{Makefile => Make.defs} | 4 +- 12 files changed, 96 insertions(+), 9 deletions(-) rename boards/arm/stm32l4/b-l475e-iot01a/src/{Makefile => Make.defs} (89%) create mode 100644 boards/arm/stm32l4/common/CMakeLists.txt create mode 100644 boards/arm/stm32l4/common/Kconfig create mode 100644 boards/arm/stm32l4/common/Makefile rename boards/arm/stm32l4/nucleo-l432kc/src/{Makefile => Make.defs} (93%) rename boards/arm/stm32l4/nucleo-l452re/src/{Makefile => Make.defs} (90%) rename boards/arm/stm32l4/nucleo-l476rg/src/{Makefile => Make.defs} (94%) rename boards/arm/stm32l4/nucleo-l496zg/src/{Makefile => Make.defs} (92%) rename boards/arm/stm32l4/steval-stlcs01v1/src/{Makefile => Make.defs} (88%) rename boards/arm/stm32l4/stm32l476-mdk/src/{Makefile => Make.defs} (89%) rename boards/arm/stm32l4/stm32l476vg-disco/src/{Makefile => Make.defs} (92%) rename boards/arm/stm32l4/stm32l4r9ai-disco/src/{Makefile => Make.defs} (92%) diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs similarity index 89% rename from boards/arm/stm32l4/b-l475e-iot01a/src/Makefile rename to boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs index 4b6dba43ad1..f9a89b4acba 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/Makefile +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/Make.defs @@ -34,4 +34,6 @@ ifeq ($(CONFIG_SPIRIT_NETDEV),y) CSRCS += stm32_spirit.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/common/CMakeLists.txt b/boards/arm/stm32l4/common/CMakeLists.txt new file mode 100644 index 00000000000..96431ebea0e --- /dev/null +++ b/boards/arm/stm32l4/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32l4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32l4/common/Kconfig b/boards/arm/stm32l4/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32l4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l4/common/Makefile b/boards/arm/stm32l4/common/Makefile new file mode 100644 index 00000000000..d876734dd1e --- /dev/null +++ b/boards/arm/stm32l4/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32l4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs similarity index 93% rename from boards/arm/stm32l4/nucleo-l432kc/src/Makefile rename to boards/arm/stm32l4/nucleo-l432kc/src/Make.defs index 6f1745c753a..2cccd3b3d3c 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l432kc/src/Make.defs @@ -100,4 +100,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l452re/src/Makefile b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs similarity index 90% rename from boards/arm/stm32l4/nucleo-l452re/src/Makefile rename to boards/arm/stm32l4/nucleo-l452re/src/Make.defs index 4c04979e48a..95d5c9ae297 100644 --- a/boards/arm/stm32l4/nucleo-l452re/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l452re/src/Make.defs @@ -42,4 +42,6 @@ ifeq ($(CONFIG_DAC),y) CSRCS += stm32_dac.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs similarity index 94% rename from boards/arm/stm32l4/nucleo-l476rg/src/Makefile rename to boards/arm/stm32l4/nucleo-l476rg/src/Make.defs index d51f9740937..5950a0e16c5 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l476rg/src/Make.defs @@ -117,4 +117,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/nucleo-l496zg/src/Makefile rename to boards/arm/stm32l4/nucleo-l496zg/src/Make.defs index 4516af4433c..af3cc615e19 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l496zg/src/Make.defs @@ -71,4 +71,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs similarity index 88% rename from boards/arm/stm32l4/steval-stlcs01v1/src/Makefile rename to boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs index 80a41f0fa38..e67f020257e 100644 --- a/boards/arm/stm32l4/steval-stlcs01v1/src/Makefile +++ b/boards/arm/stm32l4/steval-stlcs01v1/src/Make.defs @@ -32,4 +32,6 @@ ifeq ($(CONFIG_STM32_OTGFS),y) CSRCS += stm32_usb.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs similarity index 89% rename from boards/arm/stm32l4/stm32l476-mdk/src/Makefile rename to boards/arm/stm32l4/stm32l476-mdk/src/Make.defs index 66a39c74229..4c2a02f3f1b 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/Makefile +++ b/boards/arm/stm32l4/stm32l476-mdk/src/Make.defs @@ -36,4 +36,6 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/stm32l476vg-disco/src/Makefile rename to boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs index aa94c8d033c..a2a0313ee24 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Make.defs @@ -64,4 +64,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs similarity index 92% rename from boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile rename to boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs index 377448e664a..fb0302f1b58 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Make.defs @@ -77,4 +77,6 @@ CSRCS += stm32_netinit.c endif endif -include $(TOPDIR)/boards/Board.mk +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board From f491361368910179b7bb9993f9e48d1b80aa6515 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Thu, 28 May 2026 20:50:38 +0200 Subject: [PATCH 150/268] !arch/stm32: move common sources to common/stm32 BREAKING CHANGE: Common STM32 source and private header files moved to arch/arm/src/common/stm32. Out-of-tree code that references family-local common source paths must update includes, build rules, and source paths to the new common STM32 location. Signed-off-by: raiden00pl --- .../nuttx_initialization_sequence.rst | 2 +- arch/arm/src/common/stm32/CMakeLists.txt | 504 ++++++++++++++++ arch/arm/src/common/stm32/Make.defs | 549 ++++++++++++++++++ .../{ => common}/stm32/hardware/stm32_adc.h | 36 +- .../stm32/hardware/stm32_adc_v1.h | 8 +- .../stm32/hardware/stm32_adc_v1l1.h | 8 +- .../stm32/hardware/stm32_adc_v2.h | 8 +- .../stm32/hardware/stm32_adc_v2_m0.h} | 8 +- .../stm32/hardware/stm32_adc_v2g4.h | 8 +- .../stm32}/hardware/stm32_aes.h | 8 +- .../{ => common}/stm32/hardware/stm32_bkp.h | 8 +- .../arm/src/common/stm32/hardware/stm32_can.h | 43 ++ .../stm32/hardware/stm32_can_bxcan.h} | 18 +- .../stm32/hardware/stm32_can_bxcan_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_comp.h | 45 ++ .../stm32/hardware/stm32_comp_m0.h} | 8 +- .../stm32/hardware/stm32_comp_v1v2.h} | 12 +- .../stm32}/hardware/stm32_crc.h | 8 +- .../stm32}/hardware/stm32_crs.h | 8 +- .../arm/src/common/stm32/hardware/stm32_dac.h | 45 ++ .../stm32/hardware/stm32_dac_m0.h} | 8 +- .../stm32/hardware/stm32_dac_v1.h | 8 +- .../stm32/hardware/stm32_dac_v1v2.h} | 8 +- .../src/common/stm32/hardware/stm32_dbgmcu.h | 47 ++ .../stm32/hardware/stm32_dbgmcu_m0.h} | 8 +- .../stm32/hardware/stm32_dbgmcu_v1.h} | 12 +- .../{ => common}/stm32/hardware/stm32_dma.h | 15 +- .../{ => common}/stm32/hardware/stm32_dma2d.h | 8 +- .../stm32/hardware/stm32_dma_v1.h} | 25 +- .../stm32/hardware/stm32_dma_v1_7ch.h} | 8 +- .../stm32/hardware/stm32_dma_v1_8ch.h} | 32 +- .../stm32/hardware/stm32_dma_v2.h | 8 +- .../stm32/hardware/stm32_dmamux.h} | 19 +- .../stm32/hardware/stm32_dmamux_16ch.h} | 8 +- .../stm32/hardware/stm32_dmamux_7ch.h} | 8 +- .../{ => common}/stm32/hardware/stm32_eth.h | 24 +- .../src/common/stm32/hardware/stm32_exti.h | 49 ++ .../stm32/hardware/stm32_exti_v1v2.h} | 12 +- .../stm32/hardware/stm32_exti_v1v2_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_fdcan.h | 43 ++ .../stm32/hardware/stm32_fdcan_mcan.h} | 8 +- .../stm32/hardware/stm32_fdcan_mcan_m0.h} | 8 +- .../src/common/stm32/hardware/stm32_flash.h | 43 ++ .../stm32/hardware/stm32_flash_m0.h} | 8 +- .../stm32/hardware/stm32_flash_v1v2.h} | 28 +- .../{ => common}/stm32/hardware/stm32_fmc.h | 8 +- .../{ => common}/stm32/hardware/stm32_fsmc.h | 10 +- .../stm32/hardware/stm32_gpio.h} | 36 +- .../stm32/hardware/stm32_gpio_v2_m0.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_i2c.h | 51 ++ .../stm32/hardware/stm32_i2c_v1.h | 8 +- .../stm32/hardware/stm32_i2c_v2.h | 8 +- .../stm32/hardware/stm32_i2c_v2_m0.h} | 8 +- .../{ => common}/stm32/hardware/stm32_lcd.h | 8 +- .../{ => common}/stm32/hardware/stm32_ltdc.h | 8 +- .../{ => common}/stm32/hardware/stm32_otghs.h | 8 +- .../arm/src/common/stm32/hardware/stm32_pwr.h | 45 ++ .../stm32/hardware/stm32_pwr_v1.h} | 12 +- .../stm32/hardware/stm32_pwr_v1_m0_g0.h} | 8 +- .../arm/src/common/stm32/hardware/stm32_rcc.h | 69 +++ .../arm/src/common/stm32/hardware/stm32_rng.h | 43 ++ .../stm32/hardware/stm32_rng_m0.h} | 8 +- .../stm32/hardware/stm32_rng_v1.h} | 8 +- .../{ => common}/stm32/hardware/stm32_rtc.h | 8 +- .../src/common/stm32/hardware/stm32_rtcc.h | 47 ++ .../stm32/hardware/stm32_rtcc_m0.h} | 8 +- .../stm32/hardware/stm32_rtcc_v1.h} | 8 +- .../{ => common}/stm32/hardware/stm32_sdio.h | 8 +- .../arm/src/common/stm32/hardware/stm32_spi.h | 54 ++ .../stm32/hardware/stm32_spi_v1v2_m0.h} | 16 +- .../stm32/hardware/stm32_spi_v2v3v4.h} | 14 +- .../stm32}/hardware/stm32_syscfg.h | 8 +- .../{ => common}/stm32/hardware/stm32_tim.h | 24 +- .../stm32/hardware/stm32_tim_v1v2.h | 8 +- .../stm32/hardware/stm32_tim_v3.h | 8 +- .../stm32/hardware/stm32_tim_v3_m0.h} | 8 +- .../stm32/hardware/stm32_uart.h} | 38 +- .../src/common/stm32/hardware/stm32_uart_v1.h | 206 +++++++ .../src/common/stm32/hardware/stm32_uart_v2.h | 236 ++++++++ .../stm32/hardware/stm32_uart_v3.h} | 36 +- .../stm32/hardware/stm32_uart_v4.h} | 46 +- .../src/common/stm32/hardware/stm32_usbdev.h | 43 ++ .../stm32/hardware/stm32_usbdev_m0.h} | 8 +- .../stm32/hardware/stm32_usbdev_v1.h} | 8 +- .../{ => common}/stm32/hardware/stm32_usbfs.h | 8 +- .../arm/src/common/stm32/hardware/stm32_wdg.h | 43 ++ .../stm32/hardware/stm32_wdg_m0.h} | 8 +- .../stm32/hardware/stm32_wdg_v1v2.h} | 8 +- .../stm32}/hardware/stm32_wdt.h | 8 +- .../stm32/hardware/stm32fxxxxx_otgfs.h | 8 +- .../stm32/hardware/stm32gxxxxx_dac.h | 8 +- arch/arm/src/{ => common}/stm32/stm32_1wire.h | 10 +- .../stm32/stm32_1wire_m3m4_v1.c} | 3 +- .../stm32/stm32_adc.h} | 20 +- .../stm32/stm32_adc_m0_v1.c} | 2 +- .../stm32/stm32_adc_m0_v1.h} | 10 +- .../stm32/stm32_adc_m3m4_v1v2.c} | 2 +- .../stm32/stm32_adc_m3m4_v1v2.h} | 10 +- arch/arm/src/{ => common}/stm32/stm32_aes.h | 24 +- .../stm32/stm32_aes_m0_v1.c} | 4 +- .../stm32/stm32_aes_m3m4_v1.c} | 4 +- arch/arm/src/{ => common}/stm32/stm32_alarm.h | 8 +- .../stm32/stm32_allocateheap_m3m4_v1.c} | 4 +- .../stm32/stm32_bbsram.h} | 17 +- .../stm32/stm32_bbsram_m3m4_v1.c} | 4 +- .../stm32/stm32_bbsram_m3m4_v1.h} | 10 +- arch/arm/src/{ => common}/stm32/stm32_bkp.h | 8 +- arch/arm/src/{ => common}/stm32/stm32_can.h | 90 +-- .../stm32/stm32_can_m3m4_v1.c} | 2 +- .../stm32/stm32_can_m3m4_v1_sock.c} | 2 +- .../src/{ => common}/stm32/stm32_capture.h | 85 +-- .../stm32/stm32_capture_m3m4_v1.c} | 2 +- .../stm32/stm32_capture_m3m4_v1_lowerhalf.c} | 2 +- .../stm32/stm32_ccm.h} | 15 +- .../stm32/stm32_ccm_m3m4_v1.c} | 4 +- .../stm32/stm32_ccm_m3m4_v1.h} | 10 +- .../stm32/stm32_comp.h} | 158 ++++- .../stm32/stm32_comp_m3m4_v1.c} | 19 +- .../stm32/stm32_comp_m3m4_v2.c} | 19 +- .../stm32/stm32_cordic.h} | 16 +- .../stm32/stm32_cordic_m3m4_v1.c} | 4 +- .../stm32/stm32_cordic_m3m4_v1.h} | 8 +- .../stm32/stm32_crypto_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_dac.h | 39 ++ .../stm32/stm32_dac_m3m4_v1.c} | 19 +- .../stm32/stm32_dac_m3m4_v1.h} | 13 +- .../arm/src/{ => common}/stm32/stm32_dbgmcu.h | 14 +- arch/arm/src/common/stm32/stm32_dfumode.h | 38 ++ .../stm32/stm32_dfumode_m3m4_v1.c} | 8 +- .../stm32/stm32_dfumode_m3m4_v1.h} | 10 +- arch/arm/src/common/stm32/stm32_dma.h | 39 ++ arch/arm/src/common/stm32/stm32_dma2d.h | 38 ++ .../stm32/stm32_dma2d_m3m4_v1.c} | 6 +- .../stm32/stm32_dma2d_m3m4_v1.h} | 8 +- .../stm32/stm32_dma_channel_stream.h} | 8 +- .../stm32/stm32_dma_m0_v1_7ch.c} | 2 +- .../stm32/stm32_dma_m0_v1_7ch_dmamux.c} | 4 +- .../stm32/stm32_dma_m3m4_v1_8ch.c} | 6 +- .../stm32/stm32_dma_m3m4_v1_8ch_dmamux.c} | 4 +- .../stm32/stm32_dma_m3m4_v2_stream.c} | 2 +- .../stm32/stm32_dumpgpio_m3m4_v1.c} | 4 +- arch/arm/src/common/stm32/stm32_eth.h | 38 ++ .../stm32/stm32_eth_m3m4_v1.c} | 14 +- .../stm32/stm32_eth_m3m4_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_exti.h | 12 +- .../stm32/stm32_exti_alarm_m3m4_v1.c} | 2 +- .../stm32/stm32_exti_gpio_m0_v1.c} | 2 +- .../stm32/stm32_exti_gpio_m3m4_v1v2.c} | 2 +- arch/arm/src/common/stm32/stm32_exti_pwr.h | 38 ++ .../stm32/stm32_exti_pwr_m3m4_v1.c} | 6 +- .../stm32/stm32_exti_pwr_m3m4_v1.h} | 8 +- .../stm32/stm32_exti_wakeup_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_fdcan.h | 80 +++ .../stm32/stm32_fdcan_m0_v1.c} | 2 +- .../stm32/stm32_fdcan_m0_v1_sock.c} | 2 +- .../stm32/stm32_fdcan_m3m4_v1.c} | 2 +- .../stm32/stm32_fdcan_m3m4_v1_sock.c} | 2 +- .../stm32}/stm32_flash.h | 37 +- .../stm32/stm32_flash_m0_g0c0.c} | 2 +- .../stm32/stm32_flash_m3m4_f1f3.c} | 2 +- .../stm32/stm32_flash_m3m4_f2f4.c} | 6 +- .../stm32/stm32_flash_m3m4_g4.c} | 2 +- .../stm32/stm32_flash_m3m4_l1.c} | 2 +- arch/arm/src/common/stm32/stm32_fmc.h | 38 ++ .../stm32/stm32_fmc_m3m4_v1.c} | 2 +- .../stm32/stm32_fmc_m3m4_v1.h} | 12 +- arch/arm/src/common/stm32/stm32_foc.h | 38 ++ .../stm32/stm32_foc_m3m4_v1.c} | 21 +- .../stm32/stm32_foc_m3m4_v1.h} | 8 +- .../stm32/stm32_freerun.h} | 67 ++- .../stm32/stm32_freerun_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_fsmc.h | 38 ++ .../stm32/stm32_fsmc_m3m4_v1.c} | 6 +- .../stm32/stm32_fsmc_m3m4_v1.h} | 12 +- arch/arm/src/common/stm32/stm32_gpio.h | 40 ++ .../stm32/stm32_gpio_m0_v1.c} | 4 +- .../stm32/stm32_gpio_m0_v1.h} | 10 +- .../stm32/stm32_gpio_m3m4_v1v2.c} | 2 +- .../stm32/stm32_gpio_m3m4_v1v2.h} | 8 +- .../src/{ => common}/stm32/stm32_hall3ph.c | 3 +- .../src/{ => common}/stm32/stm32_hall3ph.h | 12 +- arch/arm/src/common/stm32/stm32_hciuart.h | 52 ++ .../stm32/stm32_hciuart_m3m4_v1.c} | 13 +- arch/arm/src/common/stm32/stm32_hrtim.h | 38 ++ .../stm32/stm32_hrtim_m3m4_v1.c} | 6 +- .../stm32/stm32_hrtim_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_hsi48.h | 38 ++ .../stm32/stm32_hsi48_m0_v1.c} | 4 +- .../stm32/stm32_hsi48_m0_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_i2c.h | 27 +- .../stm32/stm32_i2c_m0_v1.c} | 2 +- .../stm32/stm32_i2c_m3m4_v1.c} | 10 +- .../stm32/stm32_i2c_m3m4_v1_alt.c} | 8 +- .../stm32/stm32_i2c_m3m4_v1_f40xxx.c} | 8 +- .../stm32/stm32_i2c_m3m4_v2.c} | 2 +- .../stm32/stm32_i2c_m3m4_v2_slave.c} | 2 +- arch/arm/src/{ => common}/stm32/stm32_i2s.h | 40 +- .../stm32/stm32_i2s_m3m4_v1.c} | 9 +- .../stm32/stm32_idle_m0_v1.c} | 2 +- .../stm32/stm32_idle_m3m4_v1.c} | 2 +- .../stm32/stm32_irq_m0_v1.c} | 2 +- .../stm32/stm32_irq_m3m4_v1.c} | 2 +- .../stm32/stm32_iwdg_m0_v1.c} | 160 ++++- .../stm32/stm32_iwdg_m3m4_v1.c} | 2 +- .../stm32}/stm32_lowputc.h | 8 +- .../stm32/stm32_lowputc_usart_m0_v3.c} | 2 +- .../stm32/stm32_lowputc_usart_m0_v4.c} | 2 +- .../stm32_lowputc_usart_m3m4_v1v2v3v4.c} | 2 +- .../stm32/stm32_lse_m0_v1.c} | 2 +- .../stm32/stm32_lse_m3m4_v1.c} | 2 +- .../stm32/stm32_lsi_m0_v1.c} | 8 +- .../stm32/stm32_lsi_m3m4_v1.c} | 10 +- arch/arm/src/common/stm32/stm32_ltdc.h | 38 ++ .../stm32/stm32_ltdc_m3m4_v1.c} | 6 +- .../stm32/stm32_ltdc_m3m4_v1.h} | 12 +- .../src/{ => common}/stm32/stm32_mpuinit.h | 8 +- .../stm32/stm32_mpuinit_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_oneshot.h | 94 +++ .../stm32/stm32_oneshot_m3m4_v1.c} | 2 +- .../stm32/stm32_oneshot_m3m4_v1_lowerhalf.c} | 2 +- arch/arm/src/common/stm32/stm32_opamp.h | 38 ++ .../stm32/stm32_opamp_m3m4_v1.c} | 6 +- .../stm32/stm32_opamp_m3m4_v1.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_otgfs.h | 8 +- .../stm32/stm32_otgfsdev_m3m4_v1.c} | 2 +- .../stm32/stm32_otgfshost_m3m4_v1.c} | 4 +- arch/arm/src/{ => common}/stm32/stm32_otghs.h | 8 +- .../stm32/stm32_otghsdev_m3m4_v1.c} | 2 +- .../stm32/stm32_otghshost_m3m4_v1.c} | 4 +- .../stm32_fdcan.h => common/stm32/stm32_pm.h} | 83 +-- .../stm32/stm32_pminitialize_m3m4_v1.c} | 2 +- .../stm32/stm32_pmsleep_m3m4_v1.c} | 2 +- .../stm32/stm32_pmstandby_m3m4_v1.c} | 2 +- .../stm32/stm32_pmstop_m3m4_v1.c} | 2 +- .../src/{ => common}/stm32/stm32_pulsecount.h | 8 +- .../stm32/stm32_pulsecount_m0_v1.c} | 2 +- .../stm32/stm32_pulsecount_m3m4_v1v2v3.c} | 2 +- arch/arm/src/common/stm32/stm32_pwm.h | 42 ++ .../stm32/stm32_pwm_m0_v1.c} | 2 +- .../stm32/stm32_pwm_m0_v1.h} | 8 +- .../stm32/stm32_pwm_m3m4_v1v2v3.c} | 2 +- .../stm32/stm32_pwm_m3m4_v1v2v3.h} | 8 +- arch/arm/src/{ => common}/stm32/stm32_pwr.h | 40 +- .../stm32/stm32_pwr_m0_g0.c} | 2 +- .../stm32/stm32_pwr_m0_v1.c} | 2 +- .../stm32/stm32_pwr_m3m4_v1.c} | 2 +- .../src/{ => common}/stm32/stm32_qencoder.h | 29 +- .../stm32/stm32_qencoder_m0_v1.c} | 2 +- .../stm32/stm32_qencoder_m3m4_v1v2v3.c} | 2 +- .../stm32_pwr.h => common/stm32/stm32_rcc.h} | 281 +++++---- .../stm32/stm32_rng_m0_v1.c} | 2 +- .../stm32/stm32_rng_m3m4_v1.c} | 14 +- arch/arm/src/{ => common}/stm32/stm32_rtc.h | 12 +- .../stm32/stm32_rtc_m3m4_v1_lowerhalf.c} | 2 +- .../stm32/stm32_rtcc_m3m4_f4.c} | 2 +- .../stm32/stm32_rtcc_m3m4_l1.c} | 2 +- .../stm32/stm32_rtcc_m3m4_v1.c} | 2 +- .../stm32/stm32_rtcounter_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_sdadc.h | 38 ++ .../stm32/stm32_sdadc_m3m4_v1.c} | 6 +- .../stm32/stm32_sdadc_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_sdio.h | 38 ++ .../stm32/stm32_sdio_m3m4_v1.c} | 14 +- .../stm32/stm32_sdio_m3m4_v1.h} | 13 +- .../stm32/stm32_serial_m0_v3.c} | 2 +- .../stm32/stm32_serial_m0_v4.c} | 2 +- .../stm32/stm32_serial_m3m4_v1v2v3v4.c} | 2 +- arch/arm/src/{ => common}/stm32/stm32_spi.h | 15 +- .../stm32/stm32_spi_m0_v1.c} | 2 +- .../stm32/stm32_spi_m3m4_v2v3v4.c} | 8 +- .../stm32}/stm32_start.h | 8 +- .../stm32/stm32_start_m0_v1.c} | 2 +- .../stm32/stm32_start_m3m4_v1.c} | 2 +- .../arm/src/{ => common}/stm32/stm32_syscfg.h | 8 +- .../stm32/stm32_tickless_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_tim.h | 42 ++ .../stm32/stm32_tim_m0_v1.c} | 2 +- .../stm32/stm32_tim_m0_v1.h} | 8 +- .../stm32/stm32_tim_m0_v1_lowerhalf.c} | 2 +- .../stm32/stm32_tim_m3m4_v1v2v3.c} | 2 +- .../stm32/stm32_tim_m3m4_v1v2v3.h} | 8 +- .../stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c} | 2 +- .../stm32/stm32_timerisr_armv6m.c} | 2 +- .../stm32/stm32_timerisr_armv7m.c} | 2 +- arch/arm/src/common/stm32/stm32_uart.h | 46 ++ .../stm32/stm32_uart_m0_v1.h} | 8 +- .../stm32/stm32_uart_m3m4_v1v2.h} | 26 +- .../{stm32f0l0g0 => common/stm32}/stm32_uid.h | 14 +- .../stm32/stm32_uid_m0_v1.c} | 2 +- .../stm32/stm32_uid_m3m4_v1v2.c} | 2 +- .../stm32}/stm32_usbdev.h | 18 +- .../stm32/stm32_usbdev_m0_v1.c} | 2 +- .../stm32/stm32_usbdev_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_usbfs.h | 38 ++ .../stm32/stm32_usbfs_m3m4_v1.c} | 6 +- .../stm32/stm32_usbfs_m3m4_v1.h} | 8 +- arch/arm/src/common/stm32/stm32_usbhost.h | 38 ++ .../stm32/stm32_usbhost_m3m4_v1.c} | 4 +- .../stm32/stm32_usbhost_m3m4_v1.h} | 8 +- .../stm32/stm32_userspace.h} | 58 +- .../stm32/stm32_userspace_m3m4_v1.c} | 2 +- arch/arm/src/common/stm32/stm32_waste.h | 45 ++ .../stm32/stm32_waste_m3m4_v1.c} | 2 +- .../{stm32f0l0g0 => common/stm32}/stm32_wdg.h | 8 +- .../stm32/stm32_wwdg_m0_v1.c} | 2 +- .../stm32/stm32_wwdg_m3m4_v1.c} | 177 +++++- arch/arm/src/stm32/CMakeLists.txt | 226 +------ arch/arm/src/stm32/Make.defs | 217 +------ arch/arm/src/stm32/hardware/stm32_pinmap.h | 136 ----- arch/arm/src/stm32/stm32_comp.c | 60 -- arch/arm/src/stm32/stm32_comp_v2.h | 99 ---- arch/arm/src/stm32/stm32_dma.c | 53 -- arch/arm/src/stm32/stm32_flash.c | 49 -- arch/arm/src/stm32/stm32_flash.h | 114 ---- arch/arm/src/stm32/stm32_freerun.h | 161 ----- arch/arm/src/stm32/stm32_hciuart.h | 96 --- arch/arm/src/stm32/stm32_oneshot.h | 197 ------- arch/arm/src/stm32/stm32_rtc.c | 61 -- arch/arm/src/stm32/stm32_uid.h | 52 -- arch/arm/src/stm32/stm32_usbdev.h | 92 --- arch/arm/src/stm32/stm32_wdg.h | 106 ---- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 84 +-- arch/arm/src/stm32f0l0g0/Make.defs | 79 +-- .../stm32f0l0g0/hardware/stm32_memorymap.h | 49 -- .../src/stm32f0l0g0/hardware/stm32_pinmap.h | 51 -- arch/arm/src/stm32f0l0g0/stm32_aes.h | 50 -- arch/arm/src/stm32f0l0g0/stm32_dma.h | 327 ----------- arch/arm/src/stm32f0l0g0/stm32_exti.h | 131 ----- arch/arm/src/stm32f0l0g0/stm32_fdcan.h | 112 ---- arch/arm/src/stm32f0l0g0/stm32_i2c.h | 91 --- arch/arm/src/stm32f0l0g0/stm32_pulsecount.h | 39 -- arch/arm/src/stm32f0l0g0/stm32_qencoder.h | 116 ---- arch/arm/src/stm32f0l0g0/stm32_spi.h | 171 ------ 333 files changed, 5163 insertions(+), 4414 deletions(-) create mode 100644 arch/arm/src/common/stm32/CMakeLists.txt create mode 100644 arch/arm/src/common/stm32/Make.defs rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc.h (63%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc_v1.h (99%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc_v1l1.h (99%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc_v2.h (99%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_adc.h => common/stm32/hardware/stm32_adc_v2_m0.h} (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_adc_v2g4.h (99%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/hardware/stm32_aes.h (95%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_bkp.h (97%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_can.h rename arch/arm/src/{stm32/hardware/stm32_can.h => common/stm32/hardware/stm32_can_bxcan.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_can.h => common/stm32/hardware/stm32_can_bxcan_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_comp.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_comp.h => common/stm32/hardware/stm32_comp_m0.h} (97%) rename arch/arm/src/{stm32/hardware/stm32_comp.h => common/stm32/hardware/stm32_comp_v1v2.h} (84%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/hardware/stm32_crc.h (94%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/hardware/stm32_crs.h (96%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dac.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dac.h => common/stm32/hardware/stm32_dac_m0.h} (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_dac_v1.h (98%) rename arch/arm/src/{stm32/hardware/stm32_dac.h => common/stm32/hardware/stm32_dac_v1v2.h} (88%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dbgmcu.h => common/stm32/hardware/stm32_dbgmcu_m0.h} (93%) rename arch/arm/src/{stm32/hardware/stm32_dbgmcu.h => common/stm32/hardware/stm32_dbgmcu_v1.h} (97%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_dma.h (77%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_dma2d.h (98%) rename arch/arm/src/{stm32/hardware/stm32_i2c.h => common/stm32/hardware/stm32_dma_v1.h} (67%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dma_v1.h => common/stm32/hardware/stm32_dma_v1_7ch.h} (99%) rename arch/arm/src/{stm32/hardware/stm32_dma_v1.h => common/stm32/hardware/stm32_dma_v1_8ch.h} (97%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_dma_v2.h (99%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_uart.h => common/stm32/hardware/stm32_dmamux.h} (72%) rename arch/arm/src/{stm32/hardware/stm32_dmamux.h => common/stm32/hardware/stm32_dmamux_16ch.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_dmamux.h => common/stm32/hardware/stm32_dmamux_7ch.h} (97%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_eth.h (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_exti.h rename arch/arm/src/{stm32/hardware/stm32_exti.h => common/stm32/hardware/stm32_exti_v1v2.h} (97%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_exti.h => common/stm32/hardware/stm32_exti_v1v2_m0.h} (85%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_fdcan.h rename arch/arm/src/{stm32/hardware/stm32_fdcan.h => common/stm32/hardware/stm32_fdcan_mcan.h} (99%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_fdcan.h => common/stm32/hardware/stm32_fdcan_mcan_m0.h} (99%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_flash.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_flash.h => common/stm32/hardware/stm32_flash_m0.h} (86%) rename arch/arm/src/{stm32/hardware/stm32_flash.h => common/stm32/hardware/stm32_flash_v1v2.h} (97%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_fmc.h (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_fsmc.h (98%) rename arch/arm/src/{stm32/hardware/stm32_memorymap.h => common/stm32/hardware/stm32_gpio.h} (61%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_gpio.h => common/stm32/hardware/stm32_gpio_v2_m0.h} (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_i2c.h rename arch/arm/src/{ => common}/stm32/hardware/stm32_i2c_v1.h (97%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_i2c_v2.h (98%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_i2c.h => common/stm32/hardware/stm32_i2c_v2_m0.h} (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_lcd.h (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_ltdc.h (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_otghs.h (99%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_pwr.h rename arch/arm/src/{stm32/hardware/stm32_pwr.h => common/stm32/hardware/stm32_pwr_v1.h} (95%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_pwr.h => common/stm32/hardware/stm32_pwr_v1_m0_g0.h} (85%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rcc.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rng.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rng.h => common/stm32/hardware/stm32_rng_m0.h} (92%) rename arch/arm/src/{stm32/hardware/stm32_rng.h => common/stm32/hardware/stm32_rng_v1.h} (91%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_rtc.h (94%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_rtcc.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rtcc.h => common/stm32/hardware/stm32_rtcc_m0.h} (98%) rename arch/arm/src/{stm32/hardware/stm32_rtcc.h => common/stm32/hardware/stm32_rtcc_v1.h} (99%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_sdio.h (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_spi.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_spi.h => common/stm32/hardware/stm32_spi_v1v2_m0.h} (96%) rename arch/arm/src/{stm32/hardware/stm32_spi.h => common/stm32/hardware/stm32_spi_v2v3v4.h} (97%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/hardware/stm32_syscfg.h (86%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_tim.h (64%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_tim_v1v2.h (99%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_tim_v3.h (99%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_tim.h => common/stm32/hardware/stm32_tim_v3_m0.h} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_serial.c => common/stm32/hardware/stm32_uart.h} (63%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v1.h create mode 100644 arch/arm/src/common/stm32/hardware/stm32_uart_v2.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_uart_v1.h => common/stm32/hardware/stm32_uart_v3.h} (91%) rename arch/arm/src/{stm32f0l0g0/hardware/stm32_uart_v2.h => common/stm32/hardware/stm32_uart_v4.h} (91%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_usbdev.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_usbdev.h => common/stm32/hardware/stm32_usbdev_m0.h} (98%) rename arch/arm/src/{stm32/hardware/stm32_usbdev.h => common/stm32/hardware/stm32_usbdev_v1.h} (98%) rename arch/arm/src/{ => common}/stm32/hardware/stm32_usbfs.h (98%) create mode 100644 arch/arm/src/common/stm32/hardware/stm32_wdg.h rename arch/arm/src/{stm32f0l0g0/hardware/stm32_wdg.h => common/stm32/hardware/stm32_wdg_m0.h} (96%) rename arch/arm/src/{stm32/hardware/stm32_wdg.h => common/stm32/hardware/stm32_wdg_v1v2.h} (96%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/hardware/stm32_wdt.h (96%) rename arch/arm/src/{ => common}/stm32/hardware/stm32fxxxxx_otgfs.h (99%) rename arch/arm/src/{ => common}/stm32/hardware/stm32gxxxxx_dac.h (99%) rename arch/arm/src/{ => common}/stm32/stm32_1wire.h (92%) rename arch/arm/src/{stm32/stm32_1wire.c => common/stm32/stm32_1wire_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lowputc.c => common/stm32/stm32_adc.h} (73%) rename arch/arm/src/{stm32f0l0g0/stm32_adc.c => common/stm32/stm32_adc_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_adc.h => common/stm32/stm32_adc_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_adc.c => common/stm32/stm32_adc_m3m4_v1v2.c} (99%) rename arch/arm/src/{stm32/stm32_adc.h => common/stm32/stm32_adc_m3m4_v1v2.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_aes.h (80%) rename arch/arm/src/{stm32/stm32_aes.c => common/stm32/stm32_aes_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_aes.c => common/stm32/stm32_aes_m3m4_v1.c} (98%) rename arch/arm/src/{ => common}/stm32/stm32_alarm.h (94%) rename arch/arm/src/{stm32/stm32_allocateheap.c => common/stm32/stm32_allocateheap_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_dma.c => common/stm32/stm32_bbsram.h} (78%) rename arch/arm/src/{stm32/stm32_bbsram.c => common/stm32/stm32_bbsram_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_bbsram.h => common/stm32/stm32_bbsram_m3m4_v1.h} (95%) rename arch/arm/src/{ => common}/stm32/stm32_bkp.h (90%) rename arch/arm/src/{ => common}/stm32/stm32_can.h (71%) rename arch/arm/src/{stm32/stm32_can.c => common/stm32/stm32_can_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_can_sock.c => common/stm32/stm32_can_m3m4_v1_sock.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_capture.h (81%) rename arch/arm/src/{stm32/stm32_capture.c => common/stm32/stm32_capture_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_capture_lowerhalf.c => common/stm32/stm32_capture_m3m4_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_flash.c => common/stm32/stm32_ccm.h} (76%) rename arch/arm/src/{stm32/stm32_ccm.c => common/stm32/stm32_ccm_m3m4_v1.c} (95%) rename arch/arm/src/{stm32/stm32_ccm.h => common/stm32/stm32_ccm_m3m4_v1.h} (93%) rename arch/arm/src/{stm32/stm32_comp_v1.h => common/stm32/stm32_comp.h} (51%) rename arch/arm/src/{stm32/stm32_comp_v1.c => common/stm32/stm32_comp_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_comp_v2.c => common/stm32/stm32_comp_m3m4_v2.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_serial.h => common/stm32/stm32_cordic.h} (75%) rename arch/arm/src/{stm32/stm32_cordic.c => common/stm32/stm32_cordic_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_cordic.h => common/stm32/stm32_cordic_m3m4_v1.h} (90%) rename arch/arm/src/{stm32/stm32_crypto.c => common/stm32/stm32_crypto_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_dac.h rename arch/arm/src/{stm32/stm32_dac.c => common/stm32/stm32_dac_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_dac.h => common/stm32/stm32_dac_m3m4_v1.h} (90%) rename arch/arm/src/{ => common}/stm32/stm32_dbgmcu.h (82%) create mode 100644 arch/arm/src/common/stm32/stm32_dfumode.h rename arch/arm/src/{stm32/stm32_dfumode.c => common/stm32/stm32_dfumode_m3m4_v1.c} (93%) rename arch/arm/src/{stm32/stm32_dfumode.h => common/stm32/stm32_dfumode_m3m4_v1.h} (87%) create mode 100644 arch/arm/src/common/stm32/stm32_dma.h create mode 100644 arch/arm/src/common/stm32/stm32_dma2d.h rename arch/arm/src/{stm32/stm32_dma2d.c => common/stm32/stm32_dma2d_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_dma2d.h => common/stm32/stm32_dma2d_m3m4_v1.h} (96%) rename arch/arm/src/{stm32/stm32_dma.h => common/stm32/stm32_dma_channel_stream.h} (97%) rename arch/arm/src/{stm32f0l0g0/stm32_dma_v1.c => common/stm32/stm32_dma_m0_v1_7ch.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_dma_v1mux.c => common/stm32/stm32_dma_m0_v1_7ch_dmamux.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v1.c => common/stm32/stm32_dma_m3m4_v1_8ch.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v1mux.c => common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c} (99%) rename arch/arm/src/{stm32/stm32_dma_v2.c => common/stm32/stm32_dma_m3m4_v2_stream.c} (99%) rename arch/arm/src/{stm32/stm32_dumpgpio.c => common/stm32/stm32_dumpgpio_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_eth.h rename arch/arm/src/{stm32/stm32_eth.c => common/stm32/stm32_eth_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_eth.h => common/stm32/stm32_eth_m3m4_v1.h} (94%) rename arch/arm/src/{ => common}/stm32/stm32_exti.h (94%) rename arch/arm/src/{stm32/stm32_exti_alarm.c => common/stm32/stm32_exti_alarm_m3m4_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_exti_gpio.c => common/stm32/stm32_exti_gpio_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_exti_gpio.c => common/stm32/stm32_exti_gpio_m3m4_v1v2.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_exti_pwr.h rename arch/arm/src/{stm32/stm32_exti_pwr.c => common/stm32/stm32_exti_pwr_m3m4_v1.c} (96%) rename arch/arm/src/{stm32/stm32_exti_pwr.h => common/stm32/stm32_exti_pwr_m3m4_v1.h} (90%) rename arch/arm/src/{stm32/stm32_exti_wakeup.c => common/stm32/stm32_exti_wakeup_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_fdcan.h rename arch/arm/src/{stm32f0l0g0/stm32_fdcan.c => common/stm32/stm32_fdcan_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_fdcan_sock.c => common/stm32/stm32_fdcan_m0_v1_sock.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan.c => common/stm32/stm32_fdcan_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan_sock.c => common/stm32/stm32_fdcan_m3m4_v1_sock.c} (99%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_flash.h (70%) rename arch/arm/src/{stm32f0l0g0/stm32g0c0_flash.c => common/stm32/stm32_flash_m0_g0c0.c} (99%) rename arch/arm/src/{stm32/stm32f10xxf30xx_flash.c => common/stm32/stm32_flash_m3m4_f1f3.c} (99%) rename arch/arm/src/{stm32/stm32f20xxf40xx_flash.c => common/stm32/stm32_flash_m3m4_f2f4.c} (97%) rename arch/arm/src/{stm32/stm32g4xxx_flash.c => common/stm32/stm32_flash_m3m4_g4.c} (99%) rename arch/arm/src/{stm32/stm32l15xx_flash.c => common/stm32/stm32_flash_m3m4_l1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_fmc.h rename arch/arm/src/{stm32/stm32_fmc.c => common/stm32/stm32_fmc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fmc.h => common/stm32/stm32_fmc_m3m4_v1.h} (93%) create mode 100644 arch/arm/src/common/stm32/stm32_foc.h rename arch/arm/src/{stm32/stm32_foc.c => common/stm32/stm32_foc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_foc.h => common/stm32/stm32_foc_m3m4_v1.h} (96%) rename arch/arm/src/{stm32/stm32_waste.h => common/stm32/stm32_freerun.h} (54%) rename arch/arm/src/{stm32/stm32_freerun.c => common/stm32/stm32_freerun_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_fsmc.h rename arch/arm/src/{stm32/stm32_fsmc.c => common/stm32/stm32_fsmc_m3m4_v1.c} (93%) rename arch/arm/src/{stm32/stm32_fsmc.h => common/stm32/stm32_fsmc_m3m4_v1.h} (88%) create mode 100644 arch/arm/src/common/stm32/stm32_gpio.h rename arch/arm/src/{stm32f0l0g0/stm32_gpio.c => common/stm32/stm32_gpio_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_gpio.h => common/stm32/stm32_gpio_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_gpio.c => common/stm32/stm32_gpio_m3m4_v1v2.c} (99%) rename arch/arm/src/{stm32/stm32_gpio.h => common/stm32/stm32_gpio_m3m4_v1v2.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_hall3ph.c (98%) rename arch/arm/src/{ => common}/stm32/stm32_hall3ph.h (85%) create mode 100644 arch/arm/src/common/stm32/stm32_hciuart.h rename arch/arm/src/{stm32/stm32_hciuart.c => common/stm32/stm32_hciuart_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_hrtim.h rename arch/arm/src/{stm32/stm32_hrtim.c => common/stm32/stm32_hrtim_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_hrtim.h => common/stm32/stm32_hrtim_m3m4_v1.h} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_hsi48.h rename arch/arm/src/{stm32f0l0g0/stm32_hsi48.c => common/stm32/stm32_hsi48_m0_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_hsi48.h => common/stm32/stm32_hsi48_m0_v1.h} (94%) rename arch/arm/src/{ => common}/stm32/stm32_i2c.h (84%) rename arch/arm/src/{stm32f0l0g0/stm32_i2c.c => common/stm32/stm32_i2c_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_i2c.c => common/stm32/stm32_i2c_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_i2c_alt.c => common/stm32/stm32_i2c_m3m4_v1_alt.c} (99%) rename arch/arm/src/{stm32/stm32f40xxx_i2c.c => common/stm32/stm32_i2c_m3m4_v1_f40xxx.c} (99%) rename arch/arm/src/{stm32/stm32_i2c_v2.c => common/stm32/stm32_i2c_m3m4_v2.c} (99%) rename arch/arm/src/{stm32/stm32_i2cslave_v2.c => common/stm32/stm32_i2c_m3m4_v2_slave.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_i2s.h (78%) rename arch/arm/src/{stm32/stm32_i2s.c => common/stm32/stm32_i2s_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_idle.c => common/stm32/stm32_idle_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_idle.c => common/stm32/stm32_idle_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_irq.c => common/stm32/stm32_irq_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_irq.c => common/stm32/stm32_irq_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_iwdg.c => common/stm32/stm32_iwdg_m0_v1.c} (80%) rename arch/arm/src/{stm32/stm32_iwdg.c => common/stm32/stm32_iwdg_m3m4_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_lowputc.h (90%) rename arch/arm/src/{stm32f0l0g0/stm32_lowputc_v1.c => common/stm32/stm32_lowputc_usart_m0_v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lowputc_v2.c => common/stm32/stm32_lowputc_usart_m0_v4.c} (99%) rename arch/arm/src/{stm32/stm32_lowputc.c => common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_lse.c => common/stm32/stm32_lse_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_lse.c => common/stm32/stm32_lse_m3m4_v1.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32_lsi.c => common/stm32/stm32_lsi_m0_v1.c} (94%) rename arch/arm/src/{stm32/stm32_lsi.c => common/stm32/stm32_lsi_m3m4_v1.c} (92%) create mode 100644 arch/arm/src/common/stm32/stm32_ltdc.h rename arch/arm/src/{stm32/stm32_ltdc.c => common/stm32/stm32_ltdc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_ltdc.h => common/stm32/stm32_ltdc_m3m4_v1.h} (91%) rename arch/arm/src/{ => common}/stm32/stm32_mpuinit.h (91%) rename arch/arm/src/{stm32/stm32_mpuinit.c => common/stm32/stm32_mpuinit_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_oneshot.h rename arch/arm/src/{stm32/stm32_oneshot.c => common/stm32/stm32_oneshot_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_oneshot_lowerhalf.c => common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_opamp.h rename arch/arm/src/{stm32/stm32_opamp.c => common/stm32/stm32_opamp_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_opamp.h => common/stm32/stm32_opamp_m3m4_v1.h} (96%) rename arch/arm/src/{ => common}/stm32/stm32_otgfs.h (95%) rename arch/arm/src/{stm32/stm32_otgfsdev.c => common/stm32/stm32_otgfsdev_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_otgfshost.c => common/stm32/stm32_otgfshost_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_otghs.h (95%) rename arch/arm/src/{stm32/stm32_otghsdev.c => common/stm32/stm32_otghsdev_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_otghshost.c => common/stm32/stm32_otghshost_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_fdcan.h => common/stm32/stm32_pm.h} (58%) rename arch/arm/src/{stm32/stm32_pminitialize.c => common/stm32/stm32_pminitialize_m3m4_v1.c} (97%) rename arch/arm/src/{stm32/stm32_pmsleep.c => common/stm32/stm32_pmsleep_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_pmstandby.c => common/stm32/stm32_pmstandby_m3m4_v1.c} (98%) rename arch/arm/src/{stm32/stm32_pmstop.c => common/stm32/stm32_pmstop_m3m4_v1.c} (98%) rename arch/arm/src/{ => common}/stm32/stm32_pulsecount.h (87%) rename arch/arm/src/{stm32f0l0g0/stm32_pulsecount.c => common/stm32/stm32_pulsecount_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_pulsecount.c => common/stm32/stm32_pulsecount_m3m4_v1v2v3.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_pwm.h rename arch/arm/src/{stm32f0l0g0/stm32_pwm.c => common/stm32/stm32_pwm_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwm.h => common/stm32/stm32_pwm_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_pwm.c => common/stm32/stm32_pwm_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32/stm32_pwm.h => common/stm32/stm32_pwm_m3m4_v1v2v3.h} (99%) rename arch/arm/src/{ => common}/stm32/stm32_pwr.h (94%) rename arch/arm/src/{stm32f0l0g0/stm32g0_pwr.c => common/stm32/stm32_pwr_m0_g0.c} (98%) rename arch/arm/src/{stm32f0l0g0/stm32f0l0_pwr.c => common/stm32/stm32_pwr_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_pwr.c => common/stm32/stm32_pwr_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_qencoder.h (84%) rename arch/arm/src/{stm32f0l0g0/stm32_qencoder.c => common/stm32/stm32_qencoder_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_qencoder.c => common/stm32/stm32_qencoder_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwr.h => common/stm32/stm32_rcc.h} (51%) rename arch/arm/src/{stm32/stm32_rng.c => common/stm32/stm32_rng_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_rng.c => common/stm32/stm32_rng_m3m4_v1.c} (96%) rename arch/arm/src/{ => common}/stm32/stm32_rtc.h (96%) rename arch/arm/src/{stm32/stm32_rtc_lowerhalf.c => common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32/stm32f40xxx_rtcc.c => common/stm32/stm32_rtcc_m3m4_f4.c} (99%) rename arch/arm/src/{stm32/stm32l15xxx_rtcc.c => common/stm32/stm32_rtcc_m3m4_l1.c} (99%) rename arch/arm/src/{stm32/stm32_rtcc.c => common/stm32/stm32_rtcc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_rtcounter.c => common/stm32/stm32_rtcounter_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_sdadc.h rename arch/arm/src/{stm32/stm32_sdadc.c => common/stm32/stm32_sdadc_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_sdadc.h => common/stm32/stm32_sdadc_m3m4_v1.h} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_sdio.h rename arch/arm/src/{stm32/stm32_sdio.c => common/stm32/stm32_sdio_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_sdio.h => common/stm32/stm32_sdio_m3m4_v1.h} (93%) rename arch/arm/src/{stm32f0l0g0/stm32_serial_v1.c => common/stm32/stm32_serial_m0_v3.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_serial_v2.c => common/stm32/stm32_serial_m0_v4.c} (99%) rename arch/arm/src/{stm32/stm32_serial.c => common/stm32/stm32_serial_m3m4_v1v2v3v4.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_spi.h (94%) rename arch/arm/src/{stm32f0l0g0/stm32_spi.c => common/stm32/stm32_spi_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_spi.c => common/stm32/stm32_spi_m3m4_v2v3v4.c} (99%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_start.h (91%) rename arch/arm/src/{stm32f0l0g0/stm32_start.c => common/stm32/stm32_start_m0_v1.c} (98%) rename arch/arm/src/{stm32/stm32_start.c => common/stm32/stm32_start_m3m4_v1.c} (99%) rename arch/arm/src/{ => common}/stm32/stm32_syscfg.h (90%) rename arch/arm/src/{stm32/stm32_tickless.c => common/stm32/stm32_tickless_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_tim.h rename arch/arm/src/{stm32f0l0g0/stm32_tim.c => common/stm32/stm32_tim_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_tim.h => common/stm32/stm32_tim_m0_v1.h} (97%) rename arch/arm/src/{stm32f0l0g0/stm32_tim_lowerhalf.c => common/stm32/stm32_tim_m0_v1_lowerhalf.c} (99%) rename arch/arm/src/{stm32/stm32_tim.c => common/stm32/stm32_tim_m3m4_v1v2v3.c} (99%) rename arch/arm/src/{stm32/stm32_tim.h => common/stm32/stm32_tim_m3m4_v1v2v3.h} (96%) rename arch/arm/src/{stm32/stm32_tim_lowerhalf.c => common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_timerisr.c => common/stm32/stm32_timerisr_armv6m.c} (98%) rename arch/arm/src/{stm32/stm32_timerisr.c => common/stm32/stm32_timerisr_armv7m.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_uart.h rename arch/arm/src/{stm32f0l0g0/stm32_uart.h => common/stm32/stm32_uart_m0_v1.h} (98%) rename arch/arm/src/{stm32/stm32_uart.h => common/stm32/stm32_uart_m3m4_v1v2.h} (96%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_uid.h (79%) rename arch/arm/src/{stm32f0l0g0/stm32_uid.c => common/stm32/stm32_uid_m0_v1.c} (97%) rename arch/arm/src/{stm32/stm32_uid.c => common/stm32/stm32_uid_m3m4_v1v2.c} (98%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_usbdev.h (85%) rename arch/arm/src/{stm32f0l0g0/stm32_usbdev.c => common/stm32/stm32_usbdev_m0_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbdev.c => common/stm32/stm32_usbdev_m3m4_v1.c} (99%) create mode 100644 arch/arm/src/common/stm32/stm32_usbfs.h rename arch/arm/src/{stm32/stm32_usbfs.c => common/stm32/stm32_usbfs_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbfs.h => common/stm32/stm32_usbfs_m3m4_v1.h} (92%) create mode 100644 arch/arm/src/common/stm32/stm32_usbhost.h rename arch/arm/src/{stm32/stm32_usbhost.c => common/stm32/stm32_usbhost_m3m4_v1.c} (99%) rename arch/arm/src/{stm32/stm32_usbhost.h => common/stm32/stm32_usbhost_m3m4_v1.h} (98%) rename arch/arm/src/{stm32/stm32_comp.h => common/stm32/stm32_userspace.h} (66%) rename arch/arm/src/{stm32/stm32_userspace.c => common/stm32/stm32_userspace_m3m4_v1.c} (98%) create mode 100644 arch/arm/src/common/stm32/stm32_waste.h rename arch/arm/src/{stm32/stm32_waste.c => common/stm32/stm32_waste_m3m4_v1.c} (97%) rename arch/arm/src/{stm32f0l0g0 => common/stm32}/stm32_wdg.h (94%) rename arch/arm/src/{stm32/stm32_wwdg.c => common/stm32/stm32_wwdg_m0_v1.c} (99%) rename arch/arm/src/{stm32f0l0g0/stm32_wwdg.c => common/stm32/stm32_wwdg_m3m4_v1.c} (80%) delete mode 100644 arch/arm/src/stm32/hardware/stm32_pinmap.h delete mode 100644 arch/arm/src/stm32/stm32_comp.c delete mode 100644 arch/arm/src/stm32/stm32_comp_v2.h delete mode 100644 arch/arm/src/stm32/stm32_dma.c delete mode 100644 arch/arm/src/stm32/stm32_flash.c delete mode 100644 arch/arm/src/stm32/stm32_flash.h delete mode 100644 arch/arm/src/stm32/stm32_freerun.h delete mode 100644 arch/arm/src/stm32/stm32_hciuart.h delete mode 100644 arch/arm/src/stm32/stm32_oneshot.h delete mode 100644 arch/arm/src/stm32/stm32_rtc.c delete mode 100644 arch/arm/src/stm32/stm32_uid.h delete mode 100644 arch/arm/src/stm32/stm32_usbdev.h delete mode 100644 arch/arm/src/stm32/stm32_wdg.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h delete mode 100644 arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_aes.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_dma.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_exti.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_fdcan.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_i2c.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_pulsecount.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_qencoder.h delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_spi.h diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index d3255a5e8ca..2538e7d3a4b 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -378,7 +378,7 @@ file and in that case those operations are not performed: * ``note_register()`` - Registers the standard ``/dev/note``. * ``arm_serialinit()`` - Initialize the **standard** serial driver - (found at ``nuttx/arch/arm/src/stm32/stm32_serial.c`` STM32 F4). + (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt new file mode 100644 index 00000000000..f7b24554c0f --- /dev/null +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -0,0 +1,504 @@ +# ############################################################################## +# arch/arm/src/common/stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_include_directories(arch BEFORE PUBLIC ${CMAKE_CURRENT_LIST_DIR}) + +if(CONFIG_BUILD_PROTECTED) + target_include_directories(arch_interface BEFORE + PUBLIC ${CMAKE_CURRENT_LIST_DIR}) +endif() + +set(SRCS) + +if(CONFIG_STM32_COMMON_LEGACY) + list( + APPEND + SRCS + stm32_allocateheap_m3m4_v1.c + stm32_start_m3m4_v1.c + stm32_lse_m3m4_v1.c + stm32_lsi_m3m4_v1.c + stm32_irq_m3m4_v1.c + stm32_waste_m3m4_v1.c + stm32_capture_m3m4_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) + list(APPEND SRCS stm32_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SPI_V1 + OR CONFIG_STM32_HAVE_IP_SPI_V2 + OR CONFIG_STM32_HAVE_IP_SPI_V3 + OR CONFIG_STM32_HAVE_IP_SPI_V4) + list(APPEND SRCS stm32_spi_m3m4_v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1) + list(APPEND SRCS stm32_i2s_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) + list(APPEND SRCS stm32_sdio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) + list(APPEND SRCS stm32_ccm_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) + list(APPEND SRCS stm32_uid_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) + list(APPEND SRCS stm32_dfumode_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m3m4_v1v2v3v4.c) + endif() + + if(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + + if(CONFIG_STM32_TICKLESS_TIMER) + list(APPEND SRCS stm32_tickless_m3m4_v1.c) + elseif(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + + if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace_m3m4_v1.c stm32_mpuinit_m3m4_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m3m4_v1.c) + endif() + + list(APPEND SRCS stm32_pmstop_m3m4_v1.c stm32_pmstandby_m3m4_v1.c + stm32_pmsleep_m3m4_v1.c) + + if(NOT CONFIG_ARCH_CUSTOM_PMINIT) + list(APPEND SRCS stm32_pminitialize_m3m4_v1.c) + endif() + + if(CONFIG_STM32_USART) + if(CONFIG_STM32_HAVE_IP_USART_V1 + OR CONFIG_STM32_HAVE_IP_USART_V2 + OR CONFIG_STM32_HAVE_IP_USART_V3 + OR CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_serial_m3m4_v1v2v3v4.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_TIMER AND CONFIG_STM32_HAVE_IP_TIMERS) + list(APPEND SRCS stm32_tim_m3m4_v1v2v3_lowerhalf.c) + endif() + + if(CONFIG_STM32_ONESHOT) + list(APPEND SRCS stm32_oneshot_m3m4_v1.c stm32_oneshot_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_FREERUN) + list(APPEND SRCS stm32_freerun_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + if(CONFIG_STM32_I2C_ALT) + list(APPEND SRCS stm32_i2c_m3m4_v1_alt.c) + elseif(CONFIG_STM32_STM32F4XXX) + list(APPEND SRCS stm32_i2c_m3m4_v1_f40xxx.c) + else() + list(APPEND SRCS stm32_i2c_m3m4_v1.c) + endif() + elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + list(APPEND SRCS stm32_i2c_m3m4_v2.c) + if(CONFIG_STM32_I2C_SLAVE) + list(APPEND SRCS stm32_i2c_m3m4_v2_slave.c) + endif() + endif() + + if(CONFIG_USBDEV) + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) + list(APPEND SRCS stm32_usbdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_USBFS AND CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) + list(APPEND SRCS stm32_usbfs_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfsdev_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghsdev_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_USBHOST) + if(CONFIG_STM32_OTGFS AND CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1) + list(APPEND SRCS stm32_otgfshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_OTGHS AND CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1) + list(APPEND SRCS stm32_otghshost_m3m4_v1.c) + endif() + if(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG AND (CONFIG_USBHOST_TRACE + OR CONFIG_DEBUG_USB)) + list(APPEND SRCS stm32_usbhost_m3m4_v1.c) + endif() + endif() + + if(CONFIG_STM32_ETHMAC AND CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) + list(APPEND SRCS stm32_eth_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWR AND CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) + list(APPEND SRCS stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RTC) + if(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1) + list(APPEND SRCS stm32_rtcounter_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + list(APPEND SRCS stm32_rtcc_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) + list(APPEND SRCS stm32_rtcc_m3m4_f4.c) + elseif(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + list(APPEND SRCS stm32_rtcc_m3m4_v1.c) + endif() + if(CONFIG_RTC_ALARM) + list(APPEND SRCS stm32_exti_alarm_m3m4_v1.c) + endif() + if(CONFIG_RTC_PERIODIC) + list(APPEND SRCS stm32_exti_wakeup_m3m4_v1.c) + endif() + if(CONFIG_RTC_DRIVER AND CONFIG_STM32_HAVE_IP_RTC_M3M4_V1) + list(APPEND SRCS stm32_rtc_m3m4_v1_lowerhalf.c) + endif() + endif() + + if(CONFIG_STM32_ADC + AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + list(APPEND SRCS stm32_adc_m3m4_v1v2.c) + endif() + + if(CONFIG_STM32_SDADC AND CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) + list(APPEND SRCS stm32_sdadc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DAC + AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + list(APPEND SRCS stm32_dac_m3m4_v1.c) + endif() + + if(CONFIG_STM32_COMP) + if(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + list(APPEND SRCS stm32_comp_m3m4_v1.c) + elseif(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + list(APPEND SRCS stm32_comp_m3m4_v2.c) + endif() + endif() + + if(CONFIG_STM32_OPAMP AND CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) + list(APPEND SRCS stm32_opamp_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HRTIM AND CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) + list(APPEND SRCS stm32_hrtim_m3m4_v1.c) + endif() + + if(CONFIG_STM32_1WIREDRIVER) + list(APPEND SRCS stm32_1wire_m3m4_v1.c) + endif() + + if(CONFIG_STM32_HCIUART) + list(APPEND SRCS stm32_hciuart_m3m4_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) + list(APPEND SRCS stm32_rng_m3m4_v1.c) + endif() + + if(CONFIG_STM32_LTDC AND CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + list(APPEND SRCS stm32_ltdc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_DMA2D AND CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1) + list(APPEND SRCS stm32_dma2d_m3m4_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAP) + list(APPEND SRCS stm32_capture_m3m4_v1_lowerhalf.c) + endif() + + if(CONFIG_SENSORS_QENCODER AND CONFIG_STM32_QE) + list(APPEND SRCS stm32_qencoder_m3m4_v1v2v3.c) + endif() + + if(CONFIG_STM32_CAN AND CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can_m3m4_v1.c) + endif() + if(CONFIG_STM32_CAN_SOCKET) + list(APPEND SRCS stm32_can_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m3m4_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m3m4_v1_sock.c) + endif() + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_iwdg_m3m4_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) + list(APPEND SRCS stm32_wwdg_m3m4_v1.c) + endif() + + if(CONFIG_DEBUG_FEATURES + AND (CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2 + OR CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) + list(APPEND SRCS stm32_dumpgpio_m3m4_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M3M4_V1) + list(APPEND SRCS stm32_aes_m3m4_v1.c) + endif() + + if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE AND CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1) + list(APPEND SRCS stm32_crypto_m3m4_v1.c) + endif() + + if(CONFIG_STM32_BBSRAM AND CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) + list(APPEND SRCS stm32_bbsram_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FMC AND CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + list(APPEND SRCS stm32_fmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FSMC AND CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + list(APPEND SRCS stm32_fsmc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_FOC) + list(APPEND SRCS stm32_foc_m3m4_v1.c) + endif() + + if(CONFIG_STM32_CORDIC AND CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) + list(APPEND SRCS stm32_cordic_m3m4_v1.c) + endif() +endif() + +if(CONFIG_ARCH_CORTEXM0) + list( + APPEND + SRCS + stm32_irq_m0_v1.c + stm32_start_m0_v1.c + stm32_lsi_m0_v1.c) + + if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) + list(APPEND SRCS stm32_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_EXTI_V1 OR CONFIG_STM32_HAVE_IP_EXTI_V2) + list(APPEND SRCS stm32_exti_gpio_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_UID_M0_V1) + list(APPEND SRCS stm32_uid_m0_v1.c) + endif() + + if(CONFIG_STM32_HAVE_IP_USART_V3) + list(APPEND SRCS stm32_lowputc_usart_m0_v3.c stm32_serial_m0_v3.c) + elseif(CONFIG_STM32_HAVE_IP_USART_V4) + list(APPEND SRCS stm32_lowputc_usart_m0_v4.c stm32_serial_m0_v4.c) + endif() + + if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) + list(APPEND SRCS stm32_lse_m0_v1.c) + endif() + + if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS stm32_idle_m0_v1.c) + endif() + + if(NOT CONFIG_SCHED_TICKLESS) + if(CONFIG_ARCH_ARMV6M) + list(APPEND SRCS stm32_timerisr_armv6m.c) + else() + list(APPEND SRCS stm32_timerisr_armv7m.c) + endif() + endif() + + if(CONFIG_STM32_PWR) + if(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + list(APPEND SRCS stm32_pwr_m0_v1.c) + elseif(CONFIG_STM32_HAVE_IP_PWR_G0) + list(APPEND SRCS stm32_pwr_m0_g0.c) + endif() + endif() + + if(CONFIG_STM32_DMA) + if(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) + list(APPEND SRCS stm32_dma_m0_v1_7ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) + list(APPEND SRCS stm32_dma_m0_v1_7ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch_dmamux.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) + list(APPEND SRCS stm32_dma_m3m4_v1_8ch.c) + elseif(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) + list(APPEND SRCS stm32_dma_m3m4_v2_stream.c) + endif() + endif() + + if(CONFIG_STM32_PROGMEM) + if(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0) + list(APPEND SRCS stm32_flash_m0_g0c0.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1) + list(APPEND SRCS stm32_flash_m3m4_l1.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3) + list(APPEND SRCS stm32_flash_m3m4_f1f3.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) + list(APPEND SRCS stm32_flash_m3m4_f2f4.c) + elseif(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4) + list(APPEND SRCS stm32_flash_m3m4_g4.c) + endif() + endif() + + if(CONFIG_STM32_HAVE_HSI48) + list(APPEND SRCS stm32_hsi48_m0_v1.c) + endif() + + if(CONFIG_STM32_USB AND CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + list(APPEND SRCS stm32_usbdev_m0_v1.c) + endif() + + if(CONFIG_STM32_I2C) + list(APPEND SRCS stm32_i2c_m0_v1.c) + endif() + + if(CONFIG_STM32_SPI) + list(APPEND SRCS stm32_spi_m0_v1.c) + endif() + + if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm_m0_v1.c) + endif() + + if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) + list(APPEND SRCS stm32_pulsecount_m0_v1.c) + endif() + + if(CONFIG_STM32_ADC AND CONFIG_STM32_HAVE_IP_ADC_M0_V1) + list(APPEND SRCS stm32_adc_m0_v1.c) + endif() + + if(CONFIG_STM32_AES AND CONFIG_STM32_HAVE_IP_AES_M0_V1) + list(APPEND SRCS stm32_aes_m0_v1.c) + endif() + + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1) + list(APPEND SRCS stm32_rng_m0_v1.c) + endif() + + if(CONFIG_STM32_TIM AND CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + list(APPEND SRCS stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c) + endif() + + if(CONFIG_STM32_IWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_iwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_WWDG AND CONFIG_STM32_HAVE_IP_WDG_M0_V1) + list(APPEND SRCS stm32_wwdg_m0_v1.c) + endif() + + if(CONFIG_STM32_FDCAN AND CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + if(CONFIG_STM32_FDCAN_CHARDRIVER) + list(APPEND SRCS stm32_fdcan_m0_v1.c) + endif() + if(CONFIG_STM32_FDCAN_SOCKET) + list(APPEND SRCS stm32_fdcan_m0_v1_sock.c) + endif() + endif() + + if(CONFIG_SENSORS_QENCODER) + list(APPEND SRCS stm32_qencoder_m0_v1.c) + endif() +endif() + +if(CONFIG_SENSORS_HALL3PHASE) + list(APPEND SRCS stm32_hall3ph.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs new file mode 100644 index 00000000000..1e51e181755 --- /dev/null +++ b/arch/arm/src/common/stm32/Make.defs @@ -0,0 +1,549 @@ +############################################################################ +# arch/arm/src/common/stm32/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +STM32_COMMON_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +VPATH += common$(DELIM)stm32 +INCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) +ARCHXXINCLUDES += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) + +# IP-core driver selection notes (see arch/arm/src/common/stm32/Kconfig.have): +# - Some peripherals use a "register-set" symbol that picks the hardware header +# plus a "driver-variant" symbol that picks the .c file below (e.g. FLASH: +# STM32_HAVE_IP_FLASH_M3M4_V1 header + STM32_HAVE_IP_FLASH_M3M4_F2F4 driver). +# - This file is split into a legacy Cortex-M3/M4 block (the F1/F2/F3/F4/G4/L1 +# families, STM32_COMMON_LEGACY) and a Cortex-M0 block (F0/L0/G0/C0, +# ARCH_CORTEXM0). STM32_COMMON_LEGACY -- not a plain Cortex symbol -- gates +# the M3/M4 block because the other Cortex-M4 families (L4/WB/WL5) include +# this file too but provide their own implementation. + +ifeq ($(CONFIG_STM32_COMMON_LEGACY),y) + +CHIP_CSRCS += stm32_allocateheap_m3m4_v1.c +CHIP_CSRCS += stm32_start_m3m4_v1.c +CHIP_CSRCS += stm32_lse_m3m4_v1.c +CHIP_CSRCS += stm32_lsi_m3m4_v1.c +CHIP_CSRCS += stm32_irq_m3m4_v1.c +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_lowputc_usart_m3m4_v1v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1),y) +CHIP_CSRCS += stm32_gpio_m3m4_v1v2.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m3m4_v1v2.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_SPI_V1) \ + $(CONFIG_STM32_HAVE_IP_SPI_V2) \ + $(CONFIG_STM32_HAVE_IP_SPI_V3) \ + $(CONFIG_STM32_HAVE_IP_SPI_V4)),) +CHIP_CSRCS += stm32_spi_m3m4_v2v3v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_I2S_M3M4_V1),y) +CHIP_CSRCS += stm32_i2s_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1),y) +CHIP_CSRCS += stm32_sdio_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_TIMERS),y) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3.c +endif +CHIP_CSRCS += stm32_waste_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1),y) +CHIP_CSRCS += stm32_ccm_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M3M4_V1),y) +CHIP_CSRCS += stm32_uid_m3m4_v1v2.c +endif +CHIP_CSRCS += stm32_capture_m3m4_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1),y) +CHIP_CSRCS += stm32_dfumode_m3m4_v1.c +endif + +ifdef CONFIG_STM32_TICKLESS_TIMER +CHIP_CSRCS += stm32_tickless_m3m4_v1.c +else +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace_m3m4_v1.c +CHIP_CSRCS += stm32_mpuinit_m3m4_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m3m4_v1.c +endif + +CHIP_CSRCS += stm32_pmstop_m3m4_v1.c +CHIP_CSRCS += stm32_pmstandby_m3m4_v1.c +CHIP_CSRCS += stm32_pmsleep_m3m4_v1.c + +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += stm32_pminitialize_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_USART),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_USART_V1) \ + $(CONFIG_STM32_HAVE_IP_USART_V2) \ + $(CONFIG_STM32_HAVE_IP_USART_V3) \ + $(CONFIG_STM32_HAVE_IP_USART_V4)),) +CHIP_CSRCS += stm32_serial_m3m4_v1v2v3v4.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_TIMER)$(CONFIG_STM32_HAVE_IP_TIMERS),yy) +CHIP_CSRCS += stm32_tim_m3m4_v1v2v3_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot_m3m4_v1.c +CHIP_CSRCS += stm32_oneshot_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) +ifeq ($(CONFIG_STM32_I2C_ALT),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_alt.c +else ifeq ($(CONFIG_STM32_STM32F4XXX),y) +CHIP_CSRCS += stm32_i2c_m3m4_v1_f40xxx.c +else +CHIP_CSRCS += stm32_i2c_m3m4_v1.c +endif +else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2.c +ifeq ($(CONFIG_STM32_I2C_SLAVE),y) +CHIP_CSRCS += stm32_i2c_m3m4_v2_slave.c +endif +endif + +ifeq ($(CONFIG_USBDEV),y) +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1),y) +CHIP_CSRCS += stm32_usbdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_USBFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1),y) +CHIP_CSRCS += stm32_usbfs_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfsdev_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghsdev_m3m4_v1.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_USBHOST),y) +ifeq ($(CONFIG_STM32_OTGFS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGFS_M3M4_V1),y) +CHIP_CSRCS += stm32_otgfshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_OTGHS),y) +ifeq ($(CONFIG_STM32_HAVE_IP_OTGHS_M3M4_V1),y) +CHIP_CSRCS += stm32_otghshost_m3m4_v1.c +endif +endif +ifeq ($(CONFIG_STM32_HAVE_COMMON_USBHOST_DEBUG),y) +ifeq ($(CONFIG_USBHOST_TRACE),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +else +ifeq ($(CONFIG_DEBUG_USB),y) +CHIP_CSRCS += stm32_usbhost_m3m4_v1.c +endif +endif +endif +endif + +ifeq ($(CONFIG_STM32_ETHMAC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1),y) +CHIP_CSRCS += stm32_eth_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR)$(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1),yy) +CHIP_CSRCS += stm32_pwr_m3m4_v1.c stm32_exti_pwr_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RTC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_RTC_COUNTER_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcounter_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4),y) +CHIP_CSRCS += stm32_rtcc_m3m4_f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1),y) +CHIP_CSRCS += stm32_rtcc_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_ALARM),y) +CHIP_CSRCS += stm32_exti_alarm_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_PERIODIC),y) +CHIP_CSRCS += stm32_exti_wakeup_m3m4_v1.c +endif +ifeq ($(CONFIG_RTC_DRIVER)$(CONFIG_STM32_HAVE_IP_RTC_M3M4_V1),yy) +CHIP_CSRCS += stm32_rtc_m3m4_v1_lowerhalf.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_ADC),y) +CHIP_CSRCS += stm32_adc_m3m4_v1v2.c +endif +endif + +ifeq ($(CONFIG_STM32_SDADC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1),y) +CHIP_CSRCS += stm32_sdadc_m3m4_v1.c +endif +endif + +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)),) +ifeq ($(CONFIG_STM32_DAC),y) +CHIP_CSRCS += stm32_dac_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_COMP),y) +ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1),y) +CHIP_CSRCS += stm32_comp_m3m4_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2),y) +CHIP_CSRCS += stm32_comp_m3m4_v2.c +endif +endif + +ifeq ($(CONFIG_STM32_OPAMP)$(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1),yy) +CHIP_CSRCS += stm32_opamp_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HRTIM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1),y) +CHIP_CSRCS += stm32_hrtim_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_1WIREDRIVER),y) +CHIP_CSRCS += stm32_1wire_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_HCIUART),y) +CHIP_CSRCS += stm32_hciuart_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1),yy) +CHIP_CSRCS += stm32_rng_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_LTDC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1),y) +CHIP_CSRCS += stm32_ltdc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA2D),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA2D_M3M4_V1),y) +CHIP_CSRCS += stm32_dma2d_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAP),y) +CHIP_CSRCS += stm32_capture_m3m4_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER)$(CONFIG_STM32_QE),yy) +CHIP_CSRCS += stm32_qencoder_m3m4_v1v2v3.c +endif + +ifeq ($(CONFIG_STM32_CAN)$(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1),yy) +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_can_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_CAN_SOCKET),y) +CHIP_CSRCS += stm32_can_m3m4_v1_sock.c +endif +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m3m4_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_iwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1),yy) +CHIP_CSRCS += stm32_wwdg_m3m4_v1.c +endif + +ifeq ($(CONFIG_DEBUG_FEATURES),y) +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) \ + $(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)),) +CHIP_CSRCS += stm32_dumpgpio_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M3M4_V1),yy) +CHIP_CSRCS += stm32_aes_m3m4_v1.c +endif + +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_HAVE_IP_CRYPTO_M3M4_V1),yy) +CHIP_CSRCS += stm32_crypto_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_BBSRAM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1),y) +CHIP_CSRCS += stm32_bbsram_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1),y) +CHIP_CSRCS += stm32_fsmc_m3m4_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_FOC),y) +CHIP_CSRCS += stm32_foc_m3m4_v1.c +endif + +ifeq ($(CONFIG_STM32_CORDIC)$(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1),yy) +CHIP_CSRCS += stm32_cordic_m3m4_v1.c +endif + +endif + +ifeq ($(CONFIG_ARCH_CORTEXM0),y) + +CHIP_CSRCS += stm32_irq_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_lowputc_usart_m0_v4.c +endif +CHIP_CSRCS += stm32_start_m0_v1.c +CHIP_CSRCS += stm32_lsi_m0_v1.c +ifeq ($(CONFIG_STM32_HAVE_IP_GPIO_M0_V1),y) +CHIP_CSRCS += stm32_gpio_m0_v1.c +endif +ifneq ($(filter y,$(CONFIG_STM32_HAVE_IP_EXTI_V1) \ + $(CONFIG_STM32_HAVE_IP_EXTI_V2)),) +CHIP_CSRCS += stm32_exti_gpio_m0_v1.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_USART_V3),y) +CHIP_CSRCS += stm32_serial_m0_v3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_USART_V4),y) +CHIP_CSRCS += stm32_serial_m0_v4.c +endif +ifeq ($(CONFIG_STM32_HAVE_IP_UID_M0_V1),y) +CHIP_CSRCS += stm32_uid_m0_v1.c +endif + +ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_LCD_LSECLOCK),) +CHIP_CSRCS += stm32_lse_m0_v1.c +endif + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CHIP_CSRCS += stm32_idle_m0_v1.c +endif + +ifneq ($(CONFIG_SCHED_TICKLESS),y) +ifeq ($(CONFIG_ARCH_ARMV6M),y) +CHIP_CSRCS += stm32_timerisr_armv6m.c +else +CHIP_CSRCS += stm32_timerisr_armv7m.c +endif +endif + +ifeq ($(CONFIG_STM32_PWR),y) +ifeq ($(CONFIG_STM32_HAVE_IP_PWR_M0_V1),y) +CHIP_CSRCS += stm32_pwr_m0_v1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_PWR_G0),y) +CHIP_CSRCS += stm32_pwr_m0_g0.c +endif +endif + +ifeq ($(CONFIG_STM32_DMA),y) +ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_7CH),y) +CHIP_CSRCS += stm32_dma_m0_v1_7ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch_dmamux.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V1_8CH),y) +CHIP_CSRCS += stm32_dma_m3m4_v1_8ch.c +else ifeq ($(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM),y) +CHIP_CSRCS += stm32_dma_m3m4_v2_stream.c +endif +endif + +ifeq ($(CONFIG_STM32_PROGMEM),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M0_G0C0),y) +CHIP_CSRCS += stm32_flash_m0_g0c0.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_L1),y) +CHIP_CSRCS += stm32_flash_m3m4_l1.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F1F3),y) +CHIP_CSRCS += stm32_flash_m3m4_f1f3.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4),y) +CHIP_CSRCS += stm32_flash_m3m4_f2f4.c +else ifeq ($(CONFIG_STM32_HAVE_IP_FLASH_M3M4_G4),y) +CHIP_CSRCS += stm32_flash_m3m4_g4.c +endif +endif + +ifeq ($(CONFIG_STM32_HAVE_HSI48),y) +CHIP_CSRCS += stm32_hsi48_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_USB),y) +ifeq ($(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1),y) +CHIP_CSRCS += stm32_usbdev_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_I2C),y) +CHIP_CSRCS += stm32_i2c_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_SPI),y) +CHIP_CSRCS += stm32_spi_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_PWM),y) +CHIP_CSRCS += stm32_pwm_m0_v1.c +endif + +ifeq ($(CONFIG_PULSECOUNT),y) +ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) +CHIP_CSRCS += stm32_pulsecount_m0_v1.c +endif +endif + +ifeq ($(CONFIG_STM32_ADC)$(CONFIG_STM32_HAVE_IP_ADC_M0_V1),yy) +CHIP_CSRCS += stm32_adc_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy) +CHIP_CSRCS += stm32_aes_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) +CHIP_CSRCS += stm32_rng_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_TIM)$(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1),yy) +CHIP_CSRCS += stm32_tim_m0_v1.c stm32_tim_m0_v1_lowerhalf.c +endif + +ifeq ($(CONFIG_STM32_IWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_iwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_WWDG)$(CONFIG_STM32_HAVE_IP_WDG_M0_V1),yy) +CHIP_CSRCS += stm32_wwdg_m0_v1.c +endif + +ifeq ($(CONFIG_STM32_FDCAN),y) +ifeq ($(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1),y) +ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) +CHIP_CSRCS += stm32_fdcan_m0_v1.c +endif +ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) +CHIP_CSRCS += stm32_fdcan_m0_v1_sock.c +endif +endif +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CHIP_CSRCS += stm32_qencoder_m0_v1.c +endif + +endif + +ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) +CHIP_CSRCS += stm32_hall3ph.c +endif diff --git a/arch/arm/src/stm32/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc.h similarity index 63% rename from arch/arm/src/stm32/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc.h index 49df6093b60..9ad1291ad40 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,31 +20,16 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H /**************************************************************************** * Included Files ****************************************************************************/ -#include - -#include "chip.h" - -/* There are 2 main types of ADC IP cores among STM32 chips: - * 1. STM32 ADC IPv1: - * a) basic version for F1 and F37x - * b) extended version for F2, F4, F7, L1: - * 2. STM32 ADC IPv2: - * a) basic version for F0 and L0 - * b) extended version for F3 (without F37x), G4, H7, L4, L4+ - * - * We also distinguish these variants: - * 1. The modified STM32 ADC IPv1 core for the L1 family, which differs - * too much to keep it in the same file as ADC IPv1. - * 2. The modified STM32 ADC IPv2 core for the G4 family, which differs - * too much to keep it in the same file as ADC IPv2. - */ +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "hardware/stm32_adc_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) #if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) && \ defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) @@ -53,18 +38,21 @@ #if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # if defined(CONFIG_STM32_STM32L15XX) -# include "stm32_adc_v1l1.h" /* Special case for L1 */ +# include "stm32_adc_v1l1.h" # else # include "stm32_adc_v1.h" # endif #elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32_adc_v2g4.h" /* Special case for G4 */ +# include "stm32_adc_v2g4.h" # else # include "stm32_adc_v2.h" # endif #else # error "STM32 ADC IP version not specified" #endif +#else +# error "Unsupported STM32 ADC" +#endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1.h index d1ba76649c3..ef09aabbac8 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H /**************************************************************************** * Included Files @@ -637,4 +637,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v1l1.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h index 68b5beacd86..919c9f57919 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v1l1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v1l1.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v1l1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H /**************************************************************************** * Included Files @@ -568,4 +568,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V1L1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V1L1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2.h index 6e62bb59a74..e8629afef80 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H /**************************************************************************** * Included Files @@ -732,4 +732,4 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h index f074647fe54..645174f4637 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -323,4 +323,4 @@ #define ADC_CCR_VLCDEN (1 << 24) /* Bit 24: VLCD enable */ #define ADC_CCR_LFMEN (1 << 25) /* Bit 25: Low Frequency Mode enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_adc_v2g4.h rename to arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h index 211bff7fe43..314244086db 100644 --- a/arch/arm/src/stm32/hardware/stm32_adc_v2g4.h +++ b/arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_adc_v2g4.h + * arch/arm/src/common/stm32/hardware/stm32_adc_v2g4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H /**************************************************************************** * Included Files @@ -866,4 +866,4 @@ #define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the Slave ADC */ #define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2G4_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ADC_V2G4_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h b/arch/arm/src/common/stm32/hardware/stm32_aes.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h rename to arch/arm/src/common/stm32/hardware/stm32_aes.h index d49e402abba..2f1342a7492 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h +++ b/arch/arm/src/common/stm32/hardware/stm32_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h + * arch/arm/src/common/stm32/hardware/stm32_aes.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H /**************************************************************************** * Included Files @@ -98,4 +98,4 @@ #define AES_SR_RDERR (1 << 1) /* Read Error Flag */ #define AES_SR_WRERR (1 << 2) /* Write Error Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_AES_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_bkp.h b/arch/arm/src/common/stm32/hardware/stm32_bkp.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_bkp.h rename to arch/arm/src/common/stm32/hardware/stm32_bkp.h index a06ed4085dc..f37ffd14f16 100644 --- a/arch/arm/src/stm32/hardware/stm32_bkp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_bkp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_bkp.h + * arch/arm/src/common/stm32/hardware/stm32_bkp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H /**************************************************************************** * Pre-processor Definitions @@ -174,4 +174,4 @@ #define BKP_DR_SHIFT (0) /* Bits 1510: Backup data */ #define BKP_DR_MASK (0xffff << BKP_DR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_BKP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_BKP_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can.h new file mode 100644 index 00000000000..6f8bdc2d273 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_can.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1)) > 1 +# error Only one STM32 CAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M0_V1) +# include "hardware/stm32_can_bxcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) +# include "hardware/stm32_can_bxcan.h" +#else +# error "Unsupported STM32 CAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h index f1c0fa67523..0de8ea6e5be 100644 --- a/arch/arm/src/stm32/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H /**************************************************************************** * Included Files @@ -437,14 +437,14 @@ /* CAN filter master register */ #define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FMR_CAN2SB_SHIFT (8) /* Bits 13-8: CAN2 start bank */ # define CAN_FMR_CAN2SB_MASK (0x3f << CAN_FMR_CAN2SB_SHIFT) #endif /* CAN filter mode register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ # define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) #else @@ -454,7 +454,7 @@ /* CAN filter scale register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ # define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) #else @@ -464,7 +464,7 @@ /* CAN filter FIFO assignment register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ # define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) #else @@ -474,7 +474,7 @@ /* CAN filter activation register */ -#if defined(CONFIG_STM32_CONNECTIVITYLINE) || defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) # define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ # define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) #else @@ -494,4 +494,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_can.h rename to arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h index 774855c7f8f..378e5a03df5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_can.h +++ b/arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_can.h + * arch/arm/src/common/stm32/hardware/stm32_can_bxcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H /**************************************************************************** * Included Files @@ -453,4 +453,4 @@ #define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ #define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CAN_BXCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp.h new file mode 100644 index 00000000000..364b1f8a418 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_comp.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_comp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2)) > 1 +# error Only one STM32 COMP IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M0_V1) +# include "hardware/stm32_comp_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) +# include "hardware/stm32_comp_v1v2.h" +#else +# error "Unsupported STM32 COMP" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_m0.h index 5d96fe86f47..06672e2ff1d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ #define COMP_CSR_COMP2OUT (1 << 14) /* Bit 14: Comparator 1 output */ #define COMP_CSR_COMP2LOCK (1 << 15) /* Bit 15: Comparator 1 lock */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_comp.h b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h similarity index 84% rename from arch/arm/src/stm32/hardware/stm32_comp.h rename to arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h index b950d622b07..94c93d429ba 100644 --- a/arch/arm/src/stm32/hardware/stm32_comp.h +++ b/arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_comp.h + * arch/arm/src/common/stm32/hardware/stm32_comp_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H /**************************************************************************** * Included Files @@ -41,13 +41,13 @@ #if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) # if defined(CONFIG_STM32_STM32F33XX) -# include "stm32f33xxx_comp.h" +# include "hardware/stm32f33xxx_comp.h" # else # error "Device not supported." # endif #elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) # if defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_comp.h" +# include "hardware/stm32g4xxxx_comp.h" # else # error "Device not supported." # endif @@ -57,4 +57,4 @@ #endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_COMP_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h b/arch/arm/src/common/stm32/hardware/stm32_crc.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h rename to arch/arm/src/common/stm32/hardware/stm32_crc.h index 8aa180ded0e..6b51ac8e12b 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h + * arch/arm/src/common/stm32/hardware/stm32_crc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h b/arch/arm/src/common/stm32/hardware/stm32_crs.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h rename to arch/arm/src/common/stm32/hardware/stm32_crs.h index 00e007a49cd..b544f9728c8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_crs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h + * arch/arm/src/common/stm32/hardware/stm32_crs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H /**************************************************************************** * Pre-processor Definitions @@ -100,4 +100,4 @@ #define CRS_ICR_ERRC (1 << 2) /* Bit 2: Error clear flag */ #define CRS_ICR_ESYNCC (1 << 3) /* Bit 3: Expected SYNC clear flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_CRS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_CRS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac.h new file mode 100644 index 00000000000..dd8df7ed9b1 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dac.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) > 1 +# error Only one STM32 DAC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M0_V1) +# include "hardware/stm32_dac_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "hardware/stm32_dac_v1v2.h" +#else +# error "Unsupported STM32 DAC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_m0.h index 7b5262432c0..f95f33e87c2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H /**************************************************************************** * Included Files @@ -208,4 +208,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_dac_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1.h index 74742ac2781..8e213a40b05 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H /**************************************************************************** * Included Files @@ -312,4 +312,4 @@ #define DAC_SR_DMAUDR1 (1 << 13) /* Bit 13: DAC channel 1 DMA underrun flag */ #define DAC_SR_DMAUDR2 (1 << 29) /* Bit 29: DAC channel 2 DMA underrun flag */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dac.h b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h similarity index 88% rename from arch/arm/src/stm32/hardware/stm32_dac.h rename to arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h index 34aa92ce260..9c8587dd4af 100644 --- a/arch/arm/src/stm32/hardware/stm32_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dac.h + * arch/arm/src/common/stm32/hardware/stm32_dac_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H /**************************************************************************** * Included Files @@ -53,4 +53,4 @@ # error "STM32 DAC IP version not specified" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DAC_V1V2_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h new file mode 100644 index 00000000000..23ef2b1fd8d --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3)) > 1 +# error Only one STM32 DBGMCU IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M0_V1) +# include "hardware/stm32_dbgmcu_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# include "hardware/stm32_dbgmcu_v1.h" +#else +# error "Unsupported STM32 DBGMCU" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h similarity index 93% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h index 0e5efadeaf7..d310e7c1ac7 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H /**************************************************************************** * Included Files @@ -77,4 +77,4 @@ # define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */ #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h index ce905d218d7..12628ae6ed6 100644 --- a/arch/arm/src/stm32/hardware/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dbgmcu.h + * arch/arm/src/common/stm32/hardware/stm32_dbgmcu_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H /**************************************************************************** * Included Files @@ -93,7 +93,7 @@ /* Debug MCU APB1 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ # define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ # define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ @@ -130,7 +130,7 @@ /* Debug MCU APB2 freeze register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) # define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ # define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ # define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ @@ -194,4 +194,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DBGMCU_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DBGMCU_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma.h b/arch/arm/src/common/stm32/hardware/stm32_dma.h similarity index 77% rename from arch/arm/src/stm32/hardware/stm32_dma.h rename to arch/arm/src/common/stm32/hardware/stm32_dma.h index a34478f9029..ee43743cd57 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma.h + * arch/arm/src/common/stm32/hardware/stm32_dma.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H /**************************************************************************** * Included Files @@ -41,12 +41,15 @@ # error Only one STM32 DMA IP version must be selected #endif -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) # include "stm32_dma_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2_STREAM) # include "stm32_dma_v2.h" #else # error "STM32 DMA IP version not specified" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma2d.h b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_dma2d.h rename to arch/arm/src/common/stm32/hardware/stm32_dma2d.h index 5f885095e2e..35abefb0915 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma2d.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma2d.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma2d.h + * arch/arm/src/common/stm32/hardware/stm32_dma2d.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H /**************************************************************************** * Included Files @@ -234,4 +234,4 @@ * Public Types ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA2D_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h similarity index 67% rename from arch/arm/src/stm32/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1.h index dd0a6f68872..1ddb8dcc46e 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,24 +20,21 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H /**************************************************************************** * Included Files ****************************************************************************/ -/* There are 2 main types of I2C IP cores among STM32 chips: - * 1. STM32 I2C IPv1 - F1, F2, F4 and L1 - * 2. STM32 I2C IPv2 - F0, F3, F7, G0, G4, H7, L0 and L4 - */ - -#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) -# include "stm32_i2c_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) -# include "stm32_i2c_v2.h" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dma_v1_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dma_v1_8ch.h" #else -# error STM32 I2C IP version not specified +# error "Unsupported STM32 DMA v1" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h index cdae49a53ee..6b3860db903 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H /**************************************************************************** * Pre-processor Definitions @@ -545,4 +545,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_7CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v1.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dma_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h index 0f73d267096..4d4cb3ed4e6 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v1.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v1_8ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H /**************************************************************************** * Pre-processor Definitions @@ -139,7 +139,7 @@ #define STM32_DMA1_CCR5 (STM32_DMA1_BASE+STM32_DMA_CCR5_OFFSET) #define STM32_DMA1_CCR6 (STM32_DMA1_BASE+STM32_DMA_CCR6_OFFSET) #define STM32_DMA1_CCR7 (STM32_DMA1_BASE+STM32_DMA_CCR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CCR8 (STM32_DMA1_BASE+STM32_DMA_CCR8_OFFSET) #endif @@ -151,7 +151,7 @@ #define STM32_DMA1_CNDTR5 (STM32_DMA1_BASE+STM32_DMA_CNDTR5_OFFSET) #define STM32_DMA1_CNDTR6 (STM32_DMA1_BASE+STM32_DMA_CNDTR6_OFFSET) #define STM32_DMA1_CNDTR7 (STM32_DMA1_BASE+STM32_DMA_CNDTR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CNDTR8 (STM32_DMA1_BASE+STM32_DMA_CNDTR8_OFFSET) #endif @@ -163,7 +163,7 @@ #define STM32_DMA1_CPAR5 (STM32_DMA1_BASE+STM32_DMA_CPAR5_OFFSET) #define STM32_DMA1_CPAR6 (STM32_DMA1_BASE+STM32_DMA_CPAR6_OFFSET) #define STM32_DMA1_CPAR7 (STM32_DMA1_BASE+STM32_DMA_CPAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CPAR8 (STM32_DMA1_BASE+STM32_DMA_CPAR8_OFFSET) #endif @@ -175,7 +175,7 @@ #define STM32_DMA1_CMAR5 (STM32_DMA1_BASE+STM32_DMA_CMAR5_OFFSET) #define STM32_DMA1_CMAR6 (STM32_DMA1_BASE+STM32_DMA_CMAR6_OFFSET) #define STM32_DMA1_CMAR7 (STM32_DMA1_BASE+STM32_DMA_CMAR7_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CMAR8 (STM32_DMA1_BASE+STM32_DMA_CMAR8_OFFSET) #endif @@ -188,7 +188,7 @@ #define STM32_DMA2_CCR3 (STM32_DMA2_BASE+STM32_DMA_CCR3_OFFSET) #define STM32_DMA2_CCR4 (STM32_DMA2_BASE+STM32_DMA_CCR4_OFFSET) #define STM32_DMA2_CCR5 (STM32_DMA2_BASE+STM32_DMA_CCR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CCR6 (STM32_DMA2_BASE+STM32_DMA_CCR6_OFFSET) # define STM32_DMA2_CCR7 (STM32_DMA2_BASE+STM32_DMA_CCR7_OFFSET) # define STM32_DMA2_CCR8 (STM32_DMA2_BASE+STM32_DMA_CCR8_OFFSET) @@ -200,7 +200,7 @@ #define STM32_DMA2_CNDTR3 (STM32_DMA2_BASE+STM32_DMA_CNDTR3_OFFSET) #define STM32_DMA2_CNDTR4 (STM32_DMA2_BASE+STM32_DMA_CNDTR4_OFFSET) #define STM32_DMA2_CNDTR5 (STM32_DMA2_BASE+STM32_DMA_CNDTR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CNDTR6 (STM32_DMA2_BASE+STM32_DMA_CNDTR6_OFFSET) # define STM32_DMA2_CNDTR7 (STM32_DMA2_BASE+STM32_DMA_CNDTR7_OFFSET) # define STM32_DMA2_CNDTR8 (STM32_DMA2_BASE+STM32_DMA_CNDTR8_OFFSET) @@ -212,7 +212,7 @@ #define STM32_DMA2_CPAR3 (STM32_DMA2_BASE+STM32_DMA_CPAR3_OFFSET) #define STM32_DMA2_CPAR4 (STM32_DMA2_BASE+STM32_DMA_CPAR4_OFFSET) #define STM32_DMA2_CPAR5 (STM32_DMA2_BASE+STM32_DMA_CPAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CPAR6 (STM32_DMA2_BASE+STM32_DMA_CPAR6_OFFSET) # define STM32_DMA2_CPAR7 (STM32_DMA2_BASE+STM32_DMA_CPAR7_OFFSET) # define STM32_DMA2_CPAR8 (STM32_DMA2_BASE+STM32_DMA_CPAR8_OFFSET) @@ -224,7 +224,7 @@ #define STM32_DMA2_CMAR3 (STM32_DMA2_BASE+STM32_DMA_CMAR3_OFFSET) #define STM32_DMA2_CMAR4 (STM32_DMA2_BASE+STM32_DMA_CMAR4_OFFSET) #define STM32_DMA2_CMAR5 (STM32_DMA2_BASE+STM32_DMA_CMAR5_OFFSET) -#if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CMAR6 (STM32_DMA2_BASE+STM32_DMA_CMAR6_OFFSET) # define STM32_DMA2_CMAR7 (STM32_DMA2_BASE+STM32_DMA_CMAR7_OFFSET) # define STM32_DMA2_CMAR8 (STM32_DMA2_BASE+STM32_DMA_CMAR8_OFFSET) @@ -286,7 +286,7 @@ #define DMA_IFCR_CHAN8_SHIFT (28) /* Bits 31-28: DMA Channel 8 interrupt flag clear */ #define DMA_IFCR_CHAN8_MASK (DMA_CHAN_MASK << DMA_IFCR_CHAN8_SHIFT) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) || defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) || defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA_IFCR_ALLCHANNELS (0xffffffff) #else # define DMA_IFCR_ALLCHANNELS (0x0fffffff) @@ -350,14 +350,14 @@ #define STM32_DMA1_CHAN5 (4) #define STM32_DMA1_CHAN6 (5) #define STM32_DMA1_CHAN7 (6) -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define STM32_DMA1_CHAN8 (7) # define STM32_DMA2_CHAN1 (8) # define STM32_DMA2_CHAN2 (9) # define STM32_DMA2_CHAN3 (10) # define STM32_DMA2_CHAN4 (11) # define STM32_DMA2_CHAN5 (12) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (13) # define STM32_DMA2_CHAN7 (14) # define STM32_DMA2_CHAN8 (15) @@ -368,7 +368,7 @@ # define STM32_DMA2_CHAN3 (9) # define STM32_DMA2_CHAN4 (10) # define STM32_DMA2_CHAN5 (11) -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define STM32_DMA2_CHAN6 (12) # define STM32_DMA2_CHAN7 (13) # define STM32_DMA2_CHAN8 (14) @@ -770,4 +770,4 @@ # error "Unknown DMA channel assignments" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V1_8CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dma_v2.h b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_dma_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_dma_v2.h index 916ddc13804..cff6393fb12 100644 --- a/arch/arm/src/stm32/hardware/stm32_dma_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dma_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dma_v2.h + * arch/arm/src/common/stm32/hardware/stm32_dma_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H /**************************************************************************** * Pre-processor Definitions @@ -558,4 +558,4 @@ #define DMAMAP_TIM8_TRIG STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) #define DMAMAP_TIM8_COM STM32_DMA_MAP(DMA2,DMA_STREAM7,DMA_CHAN7) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMA_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMA_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h similarity index 72% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux.h index 1a03d8f4dcd..1531e37123a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,22 +20,21 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "hardware/stm32_uart_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "hardware/stm32_uart_v2.h" +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1_7CH_DMAMUX) +# include "hardware/stm32_dmamux_7ch.h" +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V1_8CH_DMAMUX) +# include "hardware/stm32_dmamux_16ch.h" #else -# error "Unsupported STM32 M0 USART" +# error "Unsupported STM32 DMAMUX" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h index 18fd66b1498..bc0cc2d6832 100644 --- a/arch/arm/src/stm32/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_16ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H /**************************************************************************** * Included Files @@ -176,4 +176,4 @@ # error "Unsupported STM32 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_16CH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h rename to arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h index ccab2c6f14a..b7c36335c0a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h +++ b/arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h + * arch/arm/src/common/stm32/hardware/stm32_dmamux_7ch.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H /**************************************************************************** * Included Files @@ -159,4 +159,4 @@ # error "Unsupported STM32 M0 sub family" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_DMAMUX_7CH_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_eth.h b/arch/arm/src/common/stm32/hardware/stm32_eth.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_eth.h rename to arch/arm/src/common/stm32/hardware/stm32_eth.h index d95a6441c49..1d02920541c 100644 --- a/arch/arm/src/stm32/hardware/stm32_eth.h +++ b/arch/arm/src/common/stm32/hardware/stm32_eth.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_eth.h + * arch/arm/src/common/stm32/hardware/stm32_eth.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H /**************************************************************************** * Included Files @@ -51,7 +51,7 @@ #define STM32_ETH_MACVLANTR_OFFSET 0x001c /* Ethernet MAC VLAN tag register */ #define STM32_ETH_MACRWUFFR_OFFSET 0x0028 /* Ethernet MAC remote wakeup frame filter reg */ #define STM32_ETH_MACPMTCSR_OFFSET 0x002c /* Ethernet MAC PMT control and status register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define STM32_ETH_MACDBGR_OFFSET 0x0034 /* Ethernet MAC debug register */ #endif #define STM32_ETH_MACSR_OFFSET 0x0038 /* Ethernet MAC interrupt status register */ @@ -124,7 +124,7 @@ #define STM32_ETH_MACVLANTR (STM32_ETHERNET_BASE+STM32_ETH_MACVLANTR_OFFSET) #define STM32_ETH_MACRWUFFR (STM32_ETHERNET_BASE+STM32_ETH_MACRWUFFR_OFFSET) #define STM32_ETH_MACPMTCSR (STM32_ETHERNET_BASE+STM32_ETH_MACPMTCSR_OFFSET) -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define STM32_ETH_MACDBGR (STM32_ETHERNET_BASE+STM32_ETH_MACDBGR_OFFSET) #endif #define STM32_ETH_MACSR (STM32_ETHERNET_BASE+STM32_ETH_MACSR_OFFSET) @@ -213,7 +213,7 @@ #define ETH_MACCR_JD (1 << 22) /* Bit 22: Jabber disable */ #define ETH_MACCR_WD (1 << 23) /* Bit 23: Watchdog disable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_MACCR_CSTF (1 << 25) /* Bits 25: CRC stripping for Type frames */ #endif @@ -304,7 +304,7 @@ /* Ethernet MAC debug register */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define ETH_MACDBGR_MMRPEA (1 << 0) /* Bit 0: MAC MII receive protocol engine active */ #define ETH_MACDBGR_MSFRWCS_SHIFT (1) /* Bits 1-2: MAC small FIFO read / write controllers status */ @@ -432,7 +432,7 @@ #define ETH_MMCCR_ROR (1 << 2) /* Bit 2: Reset on read */ #define ETH_MMCCR_MCF (1 << 3) /* Bit 3: MMC counter freeze */ #define ETH_MMCCR_MCP (1 << 4) /* Bit 4: MMC counter preset */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_MMCCR_MCFHP (1 << 5) /* Bit 5: MMC counter Full-Half preset */ #endif @@ -469,7 +469,7 @@ #define ETH_PTPTSCR_TSITE (1 << 4) /* Bit 4: Time stamp interrupt trigger enable */ #define ETH_PTPTSCR_TSARU (1 << 5) /* Bit 5: Time stamp addend register update */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define ETH_PTPTSCR_TSSARFE (1 << 8) /* Bit 8: Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSSSR (1 << 9) /* Bit 9: Time stamp subsecond rollover: digital or binary rollover control */ #define ETH_PTPTSCR_TSPTPPSV2E (1 << 10) /* Bit 10: Time stamp PTP packet snooping for version2 format enable */ @@ -568,7 +568,7 @@ #define ETH_DMABMR_USP (1 << 23) /* Bit 23: Use separate PBL */ #define ETH_DMABMR_FPM (1 << 24) /* Bit 24: 4xPBL mode */ #define ETH_DMABMR_AAB (1 << 25) /* Bit 25: Address-aligned beats */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_DMABMR_MB (1 << 26) /* Bit 26: Mixed burst */ #endif @@ -743,7 +743,7 @@ /* RDES0: Receive descriptor Word0 */ #define ETH_RDES0_PCE (1 << 0) /* Bit 0: Payload checksum error */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # define ETH_RDES0_ESA (1 << 0) /* Bit 0: Extended status available */ #endif #define ETH_RDES0_CE (1 << 1) /* Bit 1: CRC error */ @@ -874,4 +874,4 @@ struct eth_rxdesc_s #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ETH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_ETH_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti.h new file mode 100644 index 00000000000..8b22f1abf70 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_exti.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_exti.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The EXTI IP version (V1/V2) is independent of the CPU core. The M0 and + * M3/M4 ports currently keep separate register headers, so the file is + * chosen by the standard NuttX core symbol (CONFIG_ARCH_CORTEXM0) while the + * version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_EXTI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) > 1 +# error Only one STM32 EXTI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_EXTI_V1) || defined(CONFIG_STM32_HAVE_IP_EXTI_V2)) +# error "Unsupported STM32 EXTI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_exti_v1v2_m0.h" +#else +# include "hardware/stm32_exti_v1v2.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h index 80d2d9c4bce..66af0a47a61 100644 --- a/arch/arm/src/stm32/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H /**************************************************************************** * Included Files @@ -55,7 +55,7 @@ # define STM32_EXTI1_MASK 0xffffffff # define STM32_NEXTI2 4 # define STM32_EXTI2_MASK 0x0000000f -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define STM32_NEXTI 23 # define STM32_EXTI_MASK 0x007fffff #endif @@ -132,7 +132,7 @@ # define EXTI_COMP1 (1 << 21) /* EXTI line 21 is connected to the Comparator 1 wakeup event */ # define EXTI_COMP2 (1 << 22) /* EXTI line 22 is connected to the Comparator 2 wakeup event */ # define EXTI_RTC_ACQUIRE (1 << 23) /* EXTI line 23 is connected to the channel acquisition interrupt */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) # define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */ # define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */ # define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */ @@ -228,4 +228,4 @@ # define STM32_EXTI_PR STM32_EXTI1_PR #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h rename to arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h index 82e7cff363d..3f147d2a17f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h +++ b/arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h + * arch/arm/src/common/stm32/hardware/stm32_exti_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unrecognized STM32 M0 EXTI" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_EXTI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_EXTI_V1V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h new file mode 100644 index 00000000000..6ce5e34f2aa --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1)) > 1 +# error Only one STM32 FDCAN IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M0_V1) +# include "hardware/stm32_fdcan_mcan_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# include "hardware/stm32_fdcan_mcan.h" +#else +# error "Unsupported STM32 FDCAN" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h index 11885bc6b57..be1f77a5d3a 100644 --- a/arch/arm/src/stm32/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H /**************************************************************************** * Included Files @@ -585,4 +585,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h rename to arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h index fa93956fc69..c8a0eba38e3 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h + * arch/arm/src/common/stm32/hardware/stm32_fdcan_mcan_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H /**************************************************************************** * Included Files @@ -579,4 +579,4 @@ # define EXTFILTER_F1_EFT_CLASSIC (2 << EXTFILTER_F1_EFT_SHIFT) /* Classic filter: SF1ID=filter SF2ID=mask */ # define EXTFILTER_F1_EFT_NOXIDAM (3 << EXTFILTER_F1_EFT_SHIFT) /* Range filter from EF1ID to EF2ID, no XIDAM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FDCAN_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FDCAN_MCAN_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash.h new file mode 100644 index 00000000000..acfe2f89b92 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_flash.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_flash.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1)) > 1 +# error Only one STM32 flash IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) +# include "hardware/stm32_flash_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) +# include "hardware/stm32_flash_v1v2.h" +#else +# error "Unsupported STM32 flash" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h similarity index 86% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_m0.h index 57193fbe896..17f642f71e6 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 FLASH" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_flash.h b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_flash.h rename to arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h index 2da31815084..3a3a5c796b1 100644 --- a/arch/arm/src/stm32/hardware/stm32_flash.h +++ b/arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_flash.h + * arch/arm/src/common/stm32/hardware/stm32_flash_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -45,7 +45,7 @@ #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # if defined(CONFIG_STM32_STM32L15XX) -# if defined(CONFIG_STM32_HIGHDENSITY) +# if defined(CONFIG_STM32L1_HIGHDENSITY) /* Different STM32L1xxx MCU version are now called by different 'categories' * instead of 'densities'. Cat.5 MCU can have up to 512KB of FLASH. @@ -102,7 +102,7 @@ # define STM32_FLASH_NPAGES 128 # define STM32_FLASH_PAGESIZE 2048 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_NPAGES 8 # define STM32_FLASH_SIZE _K((4 * 16) + (1 * 64) + (3 * 128)) # define STM32_FLASH_SIZES {_K(16), _K(16), _K(16), _K(16), \ @@ -125,7 +125,7 @@ /* Define the Valid Configuration the F2 and F4 */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # if defined(CONFIG_STM32_FLASH_CONFIG_B) # define STM32_FLASH_NPAGES 5 @@ -308,7 +308,7 @@ # define STM32_FLASH_AR_OFFSET 0x0014 # define STM32_FLASH_OBR_OFFSET 0x001c # define STM32_FLASH_WRPR_OFFSET 0x0020 -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR_OFFSET 0x0014 # endif #endif @@ -372,7 +372,7 @@ # define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET) # define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET) # define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET) -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) # endif # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ @@ -447,7 +447,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_ACR_PRFTBS (1 << 5) /* Bit 5: FLASH prefetch buffer status */ # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_ACR_PRFTEN (1 << 8) /* FLASH prefetch enable */ # define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */ # define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */ @@ -464,7 +464,7 @@ # define FLASH_SR_PGERR (1 << 2) /* Programming Error */ # define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */ # define FLASH_SR_EOP (1 << 5) /* End of Operation */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */ # define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */ # define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */ @@ -533,7 +533,7 @@ defined(CONFIG_STM32_STM32F37XX) # define FLASH_CR_OBL_LAUNCH (1 << 13) /* Bit 13: Force option byte loading */ # endif -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */ # define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */ # define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */ @@ -610,7 +610,7 @@ /* Flash Option Control Register (OPTCR) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) # define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */ # define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */ # define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */ @@ -786,8 +786,8 @@ int stm32_flash_lock(void); int stm32_flash_unlock(void); -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) int stm32_flash_writeprotect(size_t page, bool enabled); #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FLASH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FLASH_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fmc.h b/arch/arm/src/common/stm32/hardware/stm32_fmc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_fmc.h rename to arch/arm/src/common/stm32/hardware/stm32_fmc.h index 149b3ab6de9..4b72c82856e 100644 --- a/arch/arm/src/stm32/hardware/stm32_fmc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fmc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fmc.h + * arch/arm/src/common/stm32/hardware/stm32_fmc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H /**************************************************************************** * Included Files @@ -389,4 +389,4 @@ #define FMC_SDSR_MODES2_SELF_REFRESH (1 << 3) #define FMC_SDSR_MODES2_POWER_DOWN (2 << 3) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_fsmc.h b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_fsmc.h rename to arch/arm/src/common/stm32/hardware/stm32_fsmc.h index b53230f351c..703dbb1ab7f 100644 --- a/arch/arm/src/stm32/hardware/stm32_fsmc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_fsmc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_fsmc.h + * arch/arm/src/common/stm32/hardware/stm32_fsmc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H /**************************************************************************** * Included Files @@ -150,7 +150,7 @@ #define FSMC_BCR_WREN (1 << 12) /* Write enable bit */ #define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */ #define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) # define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */ #endif #define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */ @@ -298,4 +298,4 @@ #define FSMC_PIO4_IOHIZ_MASK (255 << FSMC_PIO4_IOHIZ_SHIFT) # define FSMC_PIO4_IOHIZ(n) ((n) << FSMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_FMSC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_FSMC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_memorymap.h b/arch/arm/src/common/stm32/hardware/stm32_gpio.h similarity index 61% rename from arch/arm/src/stm32/hardware/stm32_memorymap.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio.h index 5fd8733f4f6..ea028b5b223 100644 --- a/arch/arm/src/stm32/hardware/stm32_memorymap.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_memorymap.h + * arch/arm/src/common/stm32/hardware/stm32_gpio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,34 +20,30 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_memorymap.h" +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "hardware/stm32_gpio_v2_m0.h" +#elif defined(CONFIG_STM32_STM32L15XX) +# include "hardware/stm32l15xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_memorymap.h" +# include "hardware/stm32f10xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_memorymap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_memorymap.h" +# include "hardware/stm32f20xxx_gpio.h" +#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ + defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f30xxx_gpio.h" #elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_memorymap.h" +# include "hardware/stm32f40xxx_gpio.h" #elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_memorymap.h" +# include "hardware/stm32g4xxxx_gpio.h" #else -# error "Unsupported STM32 memory map" +# error "Unsupported STM32 GPIO" #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h rename to arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h index 11ecd42a32d..94637dfc7a1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h +++ b/arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h + * arch/arm/src/common/stm32/hardware/stm32_gpio_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -344,4 +344,4 @@ #define GPIO_BRR(n) (1 << (n)) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c.h new file mode 100644 index 00000000000..879ec20a764 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_i2c.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2)) > 1 +# error Only one STM32 I2C IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M0_V1) +# include "hardware/stm32_i2c_v2_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) + +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) +# include "stm32_i2c_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) +# include "stm32_i2c_v2.h" +#else +# error STM32 I2C IP version not specified +#endif +#else +# error "Unsupported STM32 I2C" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_i2c_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h index 85ef897b18c..9f3bbda52a4 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v1.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H /* This file provide definitions for the STM32 I2C IP core 1 *(F1, F2, F4 and L1) @@ -200,4 +200,4 @@ # define I2C_FLTR_DNF_MASK (0xf << I2C_FLTR_DNF_SHIFT) #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V1_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_i2c_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h index e1cf7490982..5f3212b26c3 100644 --- a/arch/arm/src/stm32/hardware/stm32_i2c_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_i2c_v2.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H /* This file provide definitions for the STM32 I2C IP core 2 (F0, F3, F7, G0, * G4, H7, L0 and L4). @@ -238,4 +238,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_I2C_V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h rename to arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h index aa10265f4a9..2f8d29fd1f9 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h +++ b/arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h + * arch/arm/src/common/stm32/hardware/stm32_i2c_v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H /**************************************************************************** * Pre-processor Definitions @@ -224,4 +224,4 @@ #define I2C_TXDR_MASK (0xff) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_I2C_V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_lcd.h b/arch/arm/src/common/stm32/hardware/stm32_lcd.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_lcd.h rename to arch/arm/src/common/stm32/hardware/stm32_lcd.h index 806fbe38b5a..d23ab4d41e7 100644 --- a/arch/arm/src/stm32/hardware/stm32_lcd.h +++ b/arch/arm/src/common/stm32/hardware/stm32_lcd.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_lcd.h + * arch/arm/src/common/stm32/hardware/stm32_lcd.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H /**************************************************************************** * Included Files @@ -206,4 +206,4 @@ #define LCD_RAMH_S(n) (1 << ((n)-32)) #endif /* STM32_NLCD */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LCD_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LCD_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_ltdc.h b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_ltdc.h rename to arch/arm/src/common/stm32/hardware/stm32_ltdc.h index 3d7b9fd3d02..9d7be41f439 100644 --- a/arch/arm/src/stm32/hardware/stm32_ltdc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_ltdc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_ltdc.h + * arch/arm/src/common/stm32/hardware/stm32_ltdc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H /**************************************************************************** * Included Files @@ -365,4 +365,4 @@ * Public Types ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_LTDC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_otghs.h b/arch/arm/src/common/stm32/hardware/stm32_otghs.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_otghs.h rename to arch/arm/src/common/stm32/hardware/stm32_otghs.h index 59583ad9699..42e0fdab7c6 100644 --- a/arch/arm/src/stm32/hardware/stm32_otghs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_otghs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_otghs.h + * arch/arm/src/common/stm32/hardware/stm32_otghs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H /**************************************************************************** * Included Files @@ -1108,4 +1108,4 @@ #define OTGHS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ /* Bits 5-31: Reserved, must be kept at reset value */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_OTGHS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_OTGHS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr.h new file mode 100644 index 00000000000..cbd743564b8 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) + \ + defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1)) > 1 +# error Only one STM32 PWR IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_PWR_M0_V1) || \ + defined(CONFIG_STM32_HAVE_IP_PWR_G0) +# include "hardware/stm32_pwr_v1_m0_g0.h" +#elif defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) +# include "hardware/stm32_pwr_v1.h" +#else +# error "Unsupported STM32 PWR" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h similarity index 95% rename from arch/arm/src/stm32/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h index 18598c77167..e2fc5e05621 100644 --- a/arch/arm/src/stm32/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H /**************************************************************************** * Included Files @@ -77,7 +77,7 @@ # endif #define PWR_CR_DBP (1 << 8) /* Bit 8: Disable Backup Domain write protection */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CR_FPDS (1 << 9) /* Bit 9: Flash power down in Stop mode */ # if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F469) || \ @@ -151,7 +151,7 @@ # define PWR_CSR_EWUP (1 << 8) /* Bit 8: Enable WKUP pin */ #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_PWR_M3M4_V1) # define PWR_CSR_BRE (1 << 9) /* Bit 9: Backup regulator enable */ # define PWR_CSR_VOSRDY (1 << 14) /* Bit 14: Regulator voltage scaling output selection ready bite */ #endif @@ -162,4 +162,4 @@ # define PWR_CSR_ODSWRDY (1 << 17) /* Bit 17: Over Drive Switch ready */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h rename to arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h index bdb173a17cb..66a345f6d82 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h +++ b/arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h + * arch/arm/src/common/stm32/hardware/stm32_pwr_v1_m0_g0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H /**************************************************************************** * Included Files @@ -42,4 +42,4 @@ # error "Unsupported STM32 M0 PWR" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PWR_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_PWR_V1_M0_G0_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rcc.h b/arch/arm/src/common/stm32/hardware/stm32_rcc.h new file mode 100644 index 00000000000..308cd4d9df9 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rcc.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_ARCH_CHIP_STM32F0) +# include "hardware/stm32f0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L0) +# include "hardware/stm32l0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G0) +# include "hardware/stm32g0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32C0) +# include "hardware/stm32c0_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F1) +# include "hardware/stm32f10xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F2) +# include "hardware/stm32f20xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F3) +# if defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F302X8) || \ + defined(CONFIG_STM32_STM32F302XC) || \ + defined(CONFIG_STM32_STM32F303XC) || \ + defined(CONFIG_STM32_STM32F303XE) +# include "hardware/stm32f30xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_rcc.h" +# elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_rcc.h" +# else +# error "Unsupported STM32F3 RCC" +# endif +#elif defined(CONFIG_ARCH_CHIP_STM32F4) +# include "hardware/stm32f40xxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32G4) +# include "hardware/stm32g4xxxx_rcc.h" +#elif defined(CONFIG_ARCH_CHIP_STM32L1) +# include "hardware/stm32l15xxx_rcc.h" +#else +# error "Unsupported STM32 RCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RCC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng.h new file mode 100644 index 00000000000..5b81e5116b6 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rng.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rng.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1)) > 1 +# error Only one STM32 RNG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RNG_M0_V1) +# include "hardware/stm32_rng_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RNG_M3M4_V1) +# include "hardware/stm32_rng_v1.h" +#else +# error "Unsupported STM32 RNG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h similarity index 92% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_m0.h index 7155e947581..1fc3c863998 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rng.h b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h similarity index 91% rename from arch/arm/src/stm32/hardware/stm32_rng.h rename to arch/arm/src/common/stm32/hardware/stm32_rng_v1.h index 645994e2f66..51a829ed5dc 100644 --- a/arch/arm/src/stm32/hardware/stm32_rng.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rng_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rng.h + * arch/arm/src/common/stm32/hardware/stm32_rng_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H /**************************************************************************** * Included Files @@ -61,4 +61,4 @@ #define RNG_SR_CEIS (1 << 5) /* Bit 5: Clock error interrupt status */ #define RNG_SR_SEIS (1 << 6) /* Bit 6: Seed error interrupt status */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RNG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RNG_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtc.h b/arch/arm/src/common/stm32/hardware/stm32_rtc.h similarity index 94% rename from arch/arm/src/stm32/hardware/stm32_rtc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtc.h index fc768d7aa02..b80f73f118f 100644 --- a/arch/arm/src/stm32/hardware/stm32_rtc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtc.h + * arch/arm/src/common/stm32/hardware/stm32_rtc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H /**************************************************************************** * Pre-processor Definitions @@ -80,4 +80,4 @@ #define RTC_DIVH_RTC_DIV_SHIFT (0) /* Bits 3-0: RTC Clock Divider High */ #define RTC_DIVH_RTC_DIV_MASK (0x0f << RTC_DIVH_RTC_DIV_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h new file mode 100644 index 00000000000..7431435f80f --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_rtcc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) + \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4)) > 1 +# error Only one STM32 RTCC IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_RTCC_M0_V1) +# include "hardware/stm32_rtcc_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_L1) || \ + defined(CONFIG_STM32_HAVE_IP_RTCC_M3M4_F4) +# include "hardware/stm32_rtcc_v1.h" +#else +# error "Unsupported STM32 RTCC" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h index 78145ffc5ca..e90b3270896 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H /**************************************************************************** * Pre-processor Definitions @@ -311,4 +311,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTCC_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_rtcc.h b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_rtcc.h rename to arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h index e939a1214ea..278f432ecd8 100644 --- a/arch/arm/src/stm32/hardware/stm32_rtcc.h +++ b/arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_rtcc.h + * arch/arm/src/common/stm32/hardware/stm32_rtcc_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H /**************************************************************************** * Pre-processor Definitions @@ -405,4 +405,4 @@ #define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ #define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_RTCC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_RTC_V1C_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_sdio.h b/arch/arm/src/common/stm32/hardware/stm32_sdio.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_sdio.h rename to arch/arm/src/common/stm32/hardware/stm32_sdio.h index 4c732893275..d9c18c5b7d5 100644 --- a/arch/arm/src/stm32/hardware/stm32_sdio.h +++ b/arch/arm/src/common/stm32/hardware/stm32_sdio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_sdio.h + * arch/arm/src/common/stm32/hardware/stm32_sdio.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H /**************************************************************************** * Pre-processor Definitions @@ -276,4 +276,4 @@ #define SDIO_FIFOCNT_SHIFT (0) #define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SDIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SDIO_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi.h new file mode 100644 index 00000000000..2d9836336ef --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_spi.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_spi.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* The SPI IP version (V1..V4) is independent of the CPU core. The register + * layout is the same, but the M0 and M3/M4 ports currently keep separate + * register headers, so the file is chosen by the standard NuttX core symbol + * (CONFIG_ARCH_CORTEXM0) while the version is core-agnostic. + */ + +#if (defined(CONFIG_STM32_HAVE_IP_SPI_V1) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) + \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) > 1 +# error Only one STM32 SPI IP version must be selected +#endif + +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#elif defined(CONFIG_ARCH_CORTEXM0) +# include "hardware/stm32_spi_v1v2_m0.h" +#else +# include "hardware/stm32_spi_v2v3v4.h" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h index fd63397093e..8d730e7b21f 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v1v2_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H /**************************************************************************** * Included Files @@ -32,14 +32,12 @@ /* Select STM32 SPI IP core */ -#if defined(CONFIG_STM32_STM32F0) || \ - defined(CONFIG_STM32_STM32G0) || \ - defined(CONFIG_STM32_STM32C0) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_IP_SPI_V2 -#elif defined(CONFIG_STM32_STM32L0) +#elif defined(CONFIG_STM32_HAVE_IP_SPI_V1) # define HAVE_IP_SPI_V1 #else -# error Unsupported family +# error Unsupported STM32 F0/L0/G0/C0 SPI IP #endif /**************************************************************************** @@ -229,4 +227,4 @@ #define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */ #define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V1V2_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_spi.h b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32_spi.h rename to arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h index b52e278e380..187df078bf5 100644 --- a/arch/arm/src/stm32/hardware/stm32_spi.h +++ b/arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_spi.h + * arch/arm/src/common/stm32/hardware/stm32_spi_v2v3v4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H /**************************************************************************** * Included Files @@ -45,7 +45,7 @@ #undef HAVE_SPI_FIFOS /* No Tx/Rx FIFOs */ #undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ -#if defined(STM32_HAVE_IP_SPI_V2) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V2) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -54,7 +54,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V3) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V3) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # undef HAVE_SPI_I2S_ASTRT /* No I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -63,7 +63,7 @@ # undef HAVE_SPI_NSSP /* No NSS Pulse Management in master mode */ #endif -#if defined(STM32_HAVE_IP_SPI_V4) +#if defined(CONFIG_STM32_HAVE_IP_SPI_V4) # define HAVE_SPI_I2S /* Some SPI peripherals have I2S mode */ # define HAVE_SPI_I2S_ASTRT /* Supports I2S asynchronous start capability */ # define HAVE_SPI_TI_MODE /* Have Motorola and TI frame modes */ @@ -280,4 +280,4 @@ # define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */ #endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SPI_V2V3V4_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h similarity index 86% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h rename to arch/arm/src/common/stm32/hardware/stm32_syscfg.h index f8966bbbcb3..7ed634e52b2 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h + * arch/arm/src/common/stm32/hardware/stm32_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -40,4 +40,4 @@ # error "Unsupported STM32 M0 SYSCFG" #endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim.h similarity index 64% rename from arch/arm/src/stm32/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_tim.h index 3815bf402db..4db3706e889 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_tim.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,13 +20,26 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H /**************************************************************************** * Included Files ****************************************************************************/ +#if (defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) + \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3)) > 1 +# error Only one STM32 TIMER IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "hardware/stm32_tim_v3_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) + #if defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) # include "stm32_tim_v1v2.h" @@ -35,5 +48,8 @@ #else # error "STM32 TIMER IP version not specified" #endif +#else +# error "Unsupported STM32 TIM" +#endif -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v1v2.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h index 44b35d1140f..d519a4df68e 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v1v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v1v2.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H /**************************************************************************** * Pre-processor Definitions @@ -1304,4 +1304,4 @@ #define BTIM_EGR_UG (1 << 0) /* Bit 0: Update generation */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V1V2_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V1V2_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_tim_v3.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32_tim_v3.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3.h index eb6e5421394..d4bd858b591 100644 --- a/arch/arm/src/stm32/hardware/stm32_tim_v3.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_tim_v3.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -1437,4 +1437,4 @@ #define BTIM_ARR_MASK_16 (0xffff << BTIM_ARR_SHIFT) /* Bits 0-15: Auto reload register */ #define BTIM_ARR_MASK_20 (0xfffff << BTIM_ARR_SHIFT) /* Bits 0-19: Auto reload register when BTIM_CR1_DITHEN */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_TIM_V3_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h rename to arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h index 7149293388a..211e43f7d51 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h +++ b/arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h + * arch/arm/src/common/stm32/hardware/stm32_tim_v3_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H /**************************************************************************** * Included Files @@ -1148,4 +1148,4 @@ #define BTIM_CNT_UIFCPY (1 << 31) /* Bit 31: UIF copy */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_TIM_V3_M0_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.c b/arch/arm/src/common/stm32/hardware/stm32_uart.h similarity index 63% rename from arch/arm/src/stm32f0l0g0/stm32_serial.c rename to arch/arm/src/common/stm32/hardware/stm32_uart.h index 5edb01036ef..471eb707aef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.c +++ b/arch/arm/src/common/stm32/hardware/stm32_uart.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.c + * arch/arm/src/common/stm32/hardware/stm32_uart.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,6 +20,9 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H + /**************************************************************************** * Included Files ****************************************************************************/ @@ -27,20 +30,23 @@ #include #include "chip.h" -/* This file is only a thin shell that includes the correct serial - * implementation for the selected STM32 IP core: - * - STM32 UART IP version 1 - F0, L0 - * - STM32 UART IP version 2 - G0 - */ - -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_serial_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_serial_v2.c" -#else -# error "Unsupported STM32 M0 serial" +#if (defined(CONFIG_STM32_HAVE_IP_USART_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) + \ + defined(CONFIG_STM32_HAVE_IP_USART_V4)) > 1 +# error Only one STM32 USART IP version must be selected #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_USART_V1) +# include "hardware/stm32_uart_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) +# include "hardware/stm32_uart_v2.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V3) +# include "hardware/stm32_uart_v3.h" +#elif defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "hardware/stm32_uart_v4.h" +#else +# error "Unsupported STM32 USART core" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h new file mode 100644 index 00000000000..3938a7f13fd --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v1.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v1.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V1_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h new file mode 100644 index 00000000000..02f3811c221 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v2.h @@ -0,0 +1,236 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_uart_v2.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ +#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ +#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ +#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ +#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ +#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ +#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ + +/* Register Addresses *******************************************************/ + +#if STM32_NUSART > 0 +# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 1 +# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 2 +# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 3 +# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 4 +# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 5 +# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) +# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) +# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) +# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) +# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) +# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) +# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) +#endif + +#if STM32_NUSART > 6 +# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) +#endif + +#if STM32_NUSART > 7 +# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) +# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) +# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) +# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) +# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) +# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* Status register */ + +#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ +#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ +#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ +#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ +#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ +#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ +#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ +#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ +#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ +#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ + +#define USART_SR_ALLBITS (0x03ff) +#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ + +/* Data register */ + +#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ +#define USART_DR_MASK (0xff << USART_DR_SHIFT) + +/* Baud Rate Register */ + +#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ +#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) +#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ +#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) + +/* Control register 1 */ + +#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ +#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ +#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ +#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ +#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ +#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ +#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ +#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ +#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ +#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ +#define USART_CR1_M (1 << 12) /* Bit 12: word length */ +#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ +#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ + +#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) + +/* Control register 2 */ + +#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ +#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) +#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ +#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ +#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ +#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ +#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ +#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ +#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) +# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ +# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ +# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ +# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ + +#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ + +/* Control register 3 */ + +#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ +#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ +#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ +#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ +#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ +#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ +#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ +#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ +#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ +#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ +#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ +#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ + +/* Guard time and prescaler register */ + +#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ +#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) +#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ +#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) + +/* Compatibility definitions ************************************************/ + +/* F3 Transmit/Read registers */ + +#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ +#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h rename to arch/arm/src/common/stm32/hardware/stm32_uart_v3.h index 41bc90b3ae5..be5e3970c92 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h + * arch/arm/src/common/stm32/hardware/stm32_uart_v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H /**************************************************************************** * Included Files @@ -192,6 +192,8 @@ #define USART_CR2_ADD_SHIFT (24) /* Bits 24-31: Address of the USART node */ #define USART_CR2_ADD_MASK (0xff << USART_CR2_ADD_SHIFT) +#define USART_CR2_ADD8_SHIFT USART_CR2_ADD_SHIFT /* F1/F2/F4-compatible name */ +#define USART_CR2_ADD8_MASK USART_CR2_ADD_MASK /* Control register 3 */ @@ -275,6 +277,8 @@ #define USART_ISR_TEACK (1 << 21) /* Bit 20: Transmit enable acknowledge Flag */ #define USART_ISR_REACK (1 << 22) /* Bit 21: Receive enable acknowledge Flag */ +#define USART_ISR_ALLBITS (0x007fdfff) + /* ICR */ #define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ @@ -300,4 +304,28 @@ #define USART_TDR_SHIFT (0) /* Bits 8:0: Data value */ #define USART_TDR_MASK (0xff << USART_TDR_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V1_H */ +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h rename to arch/arm/src/common/stm32/hardware/stm32_uart_v4.h index 82dbcfdcc2f..8f8f0900c93 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h +++ b/arch/arm/src/common/stm32/hardware/stm32_uart_v4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h + * arch/arm/src/common/stm32/hardware/stm32_uart_v4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H /**************************************************************************** * Included Files @@ -153,6 +153,14 @@ USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE |\ USART_CR1_TXFEIE | USART_CR1_RXFFIE) +/* LPUART shares the USART CR1 layout but has no receiver-timeout or + * end-of-block interrupts. + */ + +#define LPUART_CR1_ALLINTS \ + (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ + USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) + /* Control register 2 */ #define USART_CR2_SLVEN (1 << 0) /* Bit 0: Synchronous Slave mode enable */ @@ -216,6 +224,12 @@ #define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ #define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) # define USART_CR3_SCARCNT(n) ((uint32_t)(n) << USART_CR3_SCARCNT_SHIFT) +#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup interrupt flag selection */ +#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_ADDR (0 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) +# define USART_CR3_WUS_RXFNE (3 << USART_CR3_WUS_SHIFT) +#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup interrupt enable */ #define USART_CR3_RXFTCFG_SHIFT (25) /* Bit 25-27: Receive FIFO threshold configuration */ #define USART_CR3_RXFTCFG_MASK (7 << USART_CR3_RXFTCFG_SHIFT) # define USART_CR3_RXFTCFG(n) ((uint32_t)(n) << USART_CR3_RXFTCFG_SHIFT) @@ -349,4 +363,28 @@ # define USART_PRESC_DIV128 (10 << USART_PRESC_SHIFT) /* Input clock divided by 128 */ # define USART_PRESC_DIV256 (11 << USART_PRESC_SHIFT) /* Input clock divided by 256 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_UART_V2_H */ +/* Compatibility definitions ************************************************/ + +/* Compatibility with F1/F2/F4 Status Register names. This USART IP replaces + * the SR register with separate ISR/ICR registers; alias the legacy SR names + * so the shared M3/M4 serial driver keeps working on these parts. + */ + +#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET + +#define USART_SR_PE USART_ISR_PE /* Parity Error */ +#define USART_SR_FE USART_ISR_FE /* Framing error */ +#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ +#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ +#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ +#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ +#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ +#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ +#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ +#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ + +#define USART_SR_ALLBITS USART_ISR_ALLBITS + +#define USART_CR1_M USART_CR1_M0 + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_UART_V4_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h new file mode 100644 index 00000000000..ae78216c98a --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_usbdev.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1)) > 1 +# error Only one STM32 USB device IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_USBDEV_M0_V1) +# include "hardware/stm32_usbdev_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_USBDEV_M3M4_V1) +# include "hardware/stm32_usbdev_v1.h" +#else +# error "Unsupported STM32 USB device" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h index 52f0df5aef2..d40fb53b23a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H /**************************************************************************** * Included Files @@ -252,4 +252,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_HAVE_USBDEV */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbdev.h b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_usbdev.h rename to arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h index a2c0e400294..2a7b97f4936 100644 --- a/arch/arm/src/stm32/hardware/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbdev.h + * arch/arm/src/common/stm32/hardware/stm32_usbdev_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H /**************************************************************************** * Included Files @@ -224,4 +224,4 @@ #define USB_COUNT_RX_MASK (0x03ff << USB_COUNT_RX_SHIFT) #endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F30XX || CONFIG_STM32_STM32F37XX */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBDEV_V1_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_usbfs.h b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32_usbfs.h rename to arch/arm/src/common/stm32/hardware/stm32_usbfs.h index 1d83a91e3f0..cd0fc280184 100644 --- a/arch/arm/src/stm32/hardware/stm32_usbfs.h +++ b/arch/arm/src/common/stm32/hardware/stm32_usbfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_usbfs.h + * arch/arm/src/common/stm32/hardware/stm32_usbfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H /**************************************************************************** * Included Files @@ -247,4 +247,4 @@ #define USB_BCDR_DPPU (1 << 15) /* Bit 15: DP pull-up control */ #endif /* CONFIG_STM32_USBFS */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_USBFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg.h new file mode 100644 index 00000000000..2a24642f307 --- /dev/null +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/hardware/stm32_wdg.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if (defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) + \ + defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1)) > 1 +# error Only one STM32 WDG IP version must be selected +#endif + +#if defined(CONFIG_STM32_HAVE_IP_WDG_M0_V1) +# include "hardware/stm32_wdg_m0.h" +#elif defined(CONFIG_STM32_HAVE_IP_WDG_M3M4_V1) +# include "hardware/stm32_wdg_v1v2.h" +#else +# error "Unsupported STM32 WDG" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h index 824bf9c6a7d..eb366fccc37 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_m0.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H /**************************************************************************** * Included Files @@ -138,4 +138,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_M0_H */ diff --git a/arch/arm/src/stm32/hardware/stm32_wdg.h b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32_wdg.h rename to arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h index 55ac57d3b64..8febf5740cb 100644 --- a/arch/arm/src/stm32/hardware/stm32_wdg.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_wdg.h + * arch/arm/src/common/stm32/hardware/stm32_wdg_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H /**************************************************************************** * Included Files @@ -147,4 +147,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDG_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h b/arch/arm/src/common/stm32/hardware/stm32_wdt.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h rename to arch/arm/src/common/stm32/hardware/stm32_wdt.h index 54c6a345b3a..d99695aa858 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h +++ b/arch/arm/src/common/stm32/hardware/stm32_wdt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h + * arch/arm/src/common/stm32/hardware/stm32_wdt.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H /**************************************************************************** * Included Files @@ -126,4 +126,4 @@ #define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32_WDT_H */ diff --git a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h rename to arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h index 199b4098af4..610531a01d8 100644 --- a/arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h +++ b/arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32fxxxxx_otgfs.h + * arch/arm/src/common/stm32/hardware/stm32fxxxxx_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H /**************************************************************************** * Included Files @@ -1112,4 +1112,4 @@ #define OTGFS_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ /* Bits 5-31: Reserved, must be kept at reset value */ -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32FXXXXX_OTGFS_H */ diff --git a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h rename to arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h index 0b412885c97..d48838484d9 100644 --- a/arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h +++ b/arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h + * arch/arm/src/common/stm32/hardware/stm32gxxxxx_dac.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H /**************************************************************************** * Included Files @@ -522,4 +522,4 @@ #define DAC_STR_STINCDATA_SHIFT (16) /* DAC channel 1 Sawtooth increment value (12.4 bit format) */ #define DAC_STR_STINCDATA_MASK (0xffff << DAC_STR_STINCDATA_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32GXXXXX_DAC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_HARDWARE_STM32GXXXXX_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.h b/arch/arm/src/common/stm32/stm32_1wire.h similarity index 92% rename from arch/arm/src/stm32/stm32_1wire.h rename to arch/arm/src/common/stm32/stm32_1wire.h index dbd2ed588d7..79f9f6d47e4 100644 --- a/arch/arm/src/stm32/stm32_1wire.h +++ b/arch/arm/src/common/stm32/stm32_1wire.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.h + * arch/arm/src/common/stm32/stm32_1wire.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_1WIRE_H -#define __ARCH_ARM_SRC_STM32_STM32_1WIRE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#include + #include "stm32_uart.h" /**************************************************************************** @@ -71,4 +73,4 @@ struct onewire_dev_s *stm32_1wireinitialize(int port); int stm32_1wireuninitialize(struct onewire_dev_s *dev); -#endif /* __ARCH_ARM_SRC_STM32_STM32_1WIRE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_1WIRE_H */ diff --git a/arch/arm/src/stm32/stm32_1wire.c b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_1wire.c rename to arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c index e3c27f32354..595136c6c65 100644 --- a/arch/arm/src/stm32/stm32_1wire.c +++ b/arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_1wire.c + * arch/arm/src/common/stm32/stm32_1wire_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -52,6 +52,7 @@ #include "arm_internal.h" #include "stm32_rcc.h" #include "stm32_1wire.h" +#include "stm32_rcc.h" #ifdef HAVE_1WIREDRIVER diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_adc.h similarity index 73% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_adc.h index 91bd0cfbeae..fce412ef2ef 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_adc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,21 +20,21 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" -#if defined(CONFIG_STM32_HAVE_IP_USART_V1) -# include "stm32_lowputc_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_USART_V2) -# include "stm32_lowputc_v2.c" +#if defined(CONFIG_STM32_HAVE_IP_ADC_M0_V1) +# include "stm32_adc_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V2) +# include "stm32_adc_m3m4_v1v2.h" #else -# error "Unsupported STM32 M0 serial" +# error "Unsupported STM32 ADC" #endif -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_ADC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.c index 6366eb0ed32..cfa4e5c8cf1 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m0_v1.h index 579d1ffc21c..1cd50f60f7c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H /**************************************************************************** * Included Files @@ -165,7 +165,7 @@ /* TRG5 and TRG6 reserved */ # define ADC1_EXTSEL_EXTI11 ADC12_CFGR1_EXTSEL_TRG7 #else -# error +# error "Unrecognized STM32 M0 sub-family for ADC EXTSEL" #endif /* EXTSEL configuration *****************************************************/ @@ -445,4 +445,4 @@ const struct stm32_adc_ops_s #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_ADC1 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_adc.c b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_adc.c rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c index 331b4f1b795..b53e2b6a071 100644 --- a/arch/arm/src/stm32/stm32_adc.c +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.c + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_adc.h b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_adc.h rename to arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h index 05c5bdf4801..b6317b5e32d 100644 --- a/arch/arm/src/stm32/stm32_adc.h +++ b/arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_adc.h + * arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ADC_H -#define __ARCH_ARM_SRC_STM32_STM32_ADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H /**************************************************************************** * Included Files @@ -134,7 +134,7 @@ # undef CONFIG_STM32_TIM4_ADC4 #endif -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ADC_M3M4_V1) # ifndef CONFIG_STM32_TIM5 # undef CONFIG_STM32_TIM5_ADC # undef CONFIG_STM32_TIM5_ADC1 @@ -2342,4 +2342,4 @@ struct adc_dev_s *stm32_adcinitialize(int intf, const uint8_t *chanlist, #endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || * CONFIG_STM32_ADC3 || CONFIG_STM32_ADC4 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ADC_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_aes.h b/arch/arm/src/common/stm32/stm32_aes.h similarity index 80% rename from arch/arm/src/stm32/stm32_aes.h rename to arch/arm/src/common/stm32/stm32_aes.h index f0de4f59720..8e0a90c4424 100644 --- a/arch/arm/src/stm32/stm32_aes.h +++ b/arch/arm/src/common/stm32/stm32_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.h + * arch/arm/src/common/stm32/stm32_aes.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_AES_H -#define __ARCH_ARM_SRC_STM32_STM32_AES_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H /**************************************************************************** * Included Files @@ -33,14 +33,14 @@ #include "chip.h" -/* Only the STM32L162 devices have AES, but we don't bother with exact macros - * for simplicity. - */ - -#ifdef CONFIG_STM32_STM32L15XX -# include "hardware/stm32l15xxx_aes.h" -#else -# error "Unknown chip for AES" +#if defined(CONFIG_STM32_HAVE_IP_AES_M0_V1) +# include "hardware/stm32_aes.h" +#elif defined(CONFIG_STM32_HAVE_IP_AES_M3M4_V1) +# ifdef CONFIG_STM32_STM32L15XX +# include "hardware/stm32l15xxx_aes.h" +# else +# error "Unknown chip for AES" +# endif #endif /**************************************************************************** @@ -55,4 +55,4 @@ * Inline Functions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_AES_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_AES_H */ diff --git a/arch/arm/src/stm32/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m0_v1.c index ae58ed82c17..4348d1c4f0b 100644 --- a/arch/arm/src/stm32/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ #include #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.c b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_aes.c rename to arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c index 746047df3d7..96ff3b7cbf6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.c +++ b/arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.c + * arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -71,7 +71,7 @@ static int stm32aes_setup_cr(int mode, int encrypt); ****************************************************************************/ static mutex_t g_stm32aes_lock = NXMUTEX_INITIALIZER; -static bool g_stm32aes_initdone; +static bool g_stm32aes_initdone = false; /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32/stm32_alarm.h b/arch/arm/src/common/stm32/stm32_alarm.h similarity index 94% rename from arch/arm/src/stm32/stm32_alarm.h rename to arch/arm/src/common/stm32/stm32_alarm.h index 2660dfd8a05..0d192e8e847 100644 --- a/arch/arm/src/stm32/stm32_alarm.h +++ b/arch/arm/src/common/stm32/stm32_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_alarm.h + * arch/arm/src/common/stm32/stm32_alarm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ALARM_H -#define __ARCH_ARM_SRC_STM32_STM32_ALARM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H /**************************************************************************** * Included Files @@ -121,4 +121,4 @@ int stm32_rtc_rdalarm(FAR struct alm_rdalarm_s *alminfo); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_RTC_ALARM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ALARM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ALARM_H */ diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_allocateheap.c rename to arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c index 69d5a18bb7b..010ede1eeb3 100644 --- a/arch/arm/src/stm32/stm32_allocateheap.c +++ b/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_allocateheap.c + * arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -342,7 +342,7 @@ * In addition, external FSMC SRAM may be available. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) /* The STM32 F2 and the STM32 F401/F411/F412 have no CCM SRAM */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.c b/arch/arm/src/common/stm32/stm32_bbsram.h similarity index 78% rename from arch/arm/src/stm32f0l0g0/stm32_dma.c rename to arch/arm/src/common/stm32/stm32_bbsram.h index 3e3b9af30ea..8c8658f963f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.c +++ b/arch/arm/src/common/stm32/stm32_bbsram.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.c + * arch/arm/src/common/stm32/stm32_bbsram.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,20 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" - -#if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) +# include "stm32_bbsram_m3m4_v1.h" #else -# include "stm32_dma_v1.c" +# error "Unsupported STM32 stm32_bbsram" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_bbsram.c rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c index b595b377611..14c132dc8ea 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.c + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,7 +46,7 @@ #include #include -#include "stm32_bbsram.h" +#include "stm32_bbsram_m3m4_v1.h" #include "chip.h" #include "stm32_pwr.h" #include "stm32_rtc.h" diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h similarity index 95% rename from arch/arm/src/stm32/stm32_bbsram.h rename to arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h index bca2251088f..3f8abefa83e 100644 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ b/arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bbsram.h + * arch/arm/src/common/stm32/stm32_bbsram_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H -#define __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H /**************************************************************************** * The purpose of this driver is to add battery backup file to the file @@ -45,7 +45,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_BBSRAM_M3M4_V1) # define STM32_BBSRAM_SIZE 4096 #else # error No backup SRAM on this STM32 @@ -149,4 +149,4 @@ int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BBSRAM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BBSRAM_H */ diff --git a/arch/arm/src/stm32/stm32_bkp.h b/arch/arm/src/common/stm32/stm32_bkp.h similarity index 90% rename from arch/arm/src/stm32/stm32_bkp.h rename to arch/arm/src/common/stm32/stm32_bkp.h index 1d2c3cc858d..ab84719310e 100644 --- a/arch/arm/src/stm32/stm32_bkp.h +++ b/arch/arm/src/common/stm32/stm32_bkp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_bkp.h + * arch/arm/src/common/stm32/stm32_bkp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_BKP_H -#define __ARCH_ARM_SRC_STM32_STM32_BKP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_BKP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_BKP_H */ diff --git a/arch/arm/src/stm32/stm32_can.h b/arch/arm/src/common/stm32/stm32_can.h similarity index 71% rename from arch/arm/src/stm32/stm32_can.h rename to arch/arm/src/common/stm32/stm32_can.h index e9f906a92e1..ef931423e57 100644 --- a/arch/arm/src/stm32/stm32_can.h +++ b/arch/arm/src/common/stm32/stm32_can.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.h + * arch/arm/src/common/stm32/stm32_can.h * * SPDX-License-Identifier: Apache-2.0 * @@ -23,16 +23,18 @@ #ifndef __ARCH_ARM_SRC_STM32_STM32_CAN_H #define __ARCH_ARM_SRC_STM32_STM32_CAN_H +#if defined(CONFIG_STM32_HAVE_IP_CAN_BXCAN_M3M4_V1) + /**************************************************************************** * Included Files ****************************************************************************/ -#include +# include -#include "chip.h" -#include "hardware/stm32_can.h" +# include "chip.h" +# include "hardware/stm32_can.h" -#include +# include /**************************************************************************** * Pre-processor Definitions @@ -42,23 +44,23 @@ /* Up to 2 CAN interfaces are supported */ -#if STM32_NCAN < 2 -# undef CONFIG_STM32_CAN2 -#endif +# if STM32_NCAN < 2 +# undef CONFIG_STM32_CAN2 +# endif -#if STM32_NCAN < 1 -# undef CONFIG_STM32_CAN1 -#endif +# if STM32_NCAN < 1 +# undef CONFIG_STM32_CAN1 +# endif /* CAN BAUD */ -#if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) -# error "CONFIG_STM32_CAN1_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN1_BAUD) +# error "CONFIG_STM32_CAN1_BAUD is not defined" +# endif -#if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) -# error "CONFIG_STM32_CAN2_BAUD is not defined" -#endif +# if defined(CONFIG_STM32_CAN2) && !defined(CONFIG_STM32_CAN2_BAUD) +# error "CONFIG_STM32_CAN2_BAUD is not defined" +# endif /* User-defined TSEG1 and TSEG2 settings may be used. * @@ -67,46 +69,46 @@ * CAN_BIT_QUANTA = The number of CAN time quanta in on bit time */ -#ifndef CONFIG_STM32_CAN_TSEG1 -# define CONFIG_STM32_CAN_TSEG1 6 -#endif +# ifndef CONFIG_STM32_CAN_TSEG1 +# define CONFIG_STM32_CAN_TSEG1 6 +# endif -#if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX -# error "CONFIG_STM32_CAN_TSEG1 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG1 < 1 || CONFIG_STM32_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_STM32_CAN_TSEG1 is out of range" +# endif -#ifndef CONFIG_STM32_CAN_TSEG2 -# define CONFIG_STM32_CAN_TSEG2 7 -#endif +# ifndef CONFIG_STM32_CAN_TSEG2 +# define CONFIG_STM32_CAN_TSEG2 7 +# endif -#if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX -# error "CONFIG_STM32_CAN_TSEG2 is out of range" -#endif +# if CONFIG_STM32_CAN_TSEG2 < 1 || CONFIG_STM32_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_STM32_CAN_TSEG2 is out of range" +# endif /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_CAN_CHARDRIVER +# ifdef CONFIG_STM32_CAN_CHARDRIVER /**************************************************************************** * Name: stm32_caninitialize @@ -124,9 +126,9 @@ extern "C" struct can_dev_s; struct can_dev_s *stm32_caninitialize(int port); -#endif +# endif -#ifdef CONFIG_STM32_CAN_SOCKET +# ifdef CONFIG_STM32_CAN_SOCKET /**************************************************************************** * Name: stm32_cansockinitialize @@ -143,12 +145,14 @@ struct can_dev_s *stm32_caninitialize(int port); ****************************************************************************/ int stm32_cansockinitialize(int port); -#endif +# endif -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } +# endif + +# endif /* __ASSEMBLY__ */ #endif -#endif /* __ASSEMBLY__ */ #endif /* __ARCH_ARM_SRC_STM32_STM32_CAN_H */ diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_can.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1.c index 35bc9e71781..10fe28be2c8 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_can_sock.c b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_can_sock.c rename to arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c index 433ec29e153..60561620cfa 100644 --- a/arch/arm/src/stm32/stm32_can_sock.c +++ b/arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_can_sock.c + * arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/common/stm32/stm32_capture.h similarity index 81% rename from arch/arm/src/stm32/stm32_capture.h rename to arch/arm/src/common/stm32/stm32_capture.h index 33f2a3157a1..ab80b5c4c1f 100644 --- a/arch/arm/src/stm32/stm32_capture.h +++ b/arch/arm/src/common/stm32/stm32_capture.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.h + * arch/arm/src/common/stm32/stm32_capture.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H -#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H /**************************************************************************** * Included Files @@ -29,6 +29,12 @@ #include +#include +#include + +#include +#include + #include "chip.h" #include #include "hardware/stm32_tim.h" @@ -64,48 +70,28 @@ extern "C" #define EXTERN extern #endif -/* Capture Device Structure */ - struct stm32_cap_dev_s { struct stm32_cap_ops_s *ops; }; -/* Capture input EDGE sources */ - typedef enum { - /* Mapped */ - STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK), STM32_CAP_MAPPED_TI1 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI2 = (GTIM_CCMR_CCS_CCIN2), STM32_CAP_MAPPED_TI3 = (GTIM_CCMR_CCS_CCIN1), STM32_CAP_MAPPED_TI4 = (GTIM_CCMR_CCS_CCIN2), - -/* TODO STM32_CAP_MAPPED_TRC = (GTIM_CCMR_CCS_CCINTRC), */ - - /* Event prescaler */ - STM32_CAP_INPSC_MASK = (GTIM_CCMR1_IC1PSC_MASK), STM32_CAP_INPSC_NO = (0 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_2EVENTS = (1 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_4EVENTS = (2 << GTIM_CCMR1_IC1PSC_SHIFT), STM32_CAP_INPSC_8EVENTS = (3 << GTIM_CCMR1_IC1PSC_SHIFT), - - /* Event prescaler */ - STM32_CAP_FILTER_MASK = (GTIM_CCMR1_IC1F_MASK), STM32_CAP_FILTER_NO = (0 << GTIM_CCMR1_IC1F_SHIFT), - - /* Internal clock with N time to confirm event */ - STM32_CAP_FILTER_INT_N2 = (1 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N4 = (2 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_INT_N8 = (3 << GTIM_CCMR1_IC1F_SHIFT), - - /* DTS clock div by D with N time to confirm event */ - STM32_CAP_FILTER_DTS_D2_N6 = (4 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D2_N8 = (5 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D4_N6 = (6 << GTIM_CCMR1_IC1F_SHIFT), @@ -118,9 +104,6 @@ typedef enum STM32_CAP_FILTER_DTS_D32_N5 = (13 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N6 = (14 << GTIM_CCMR1_IC1F_SHIFT), STM32_CAP_FILTER_DTS_D32_N8 = (15 << GTIM_CCMR1_IC1F_SHIFT), - - /* EDGE */ - STM32_CAP_EDGE_MASK = (3 << 8), STM32_CAP_EDGE_DISABLED = (0 << 8), STM32_CAP_EDGE_RISING = (1 << 8), @@ -128,12 +111,8 @@ typedef enum STM32_CAP_EDGE_BOTH = (3 << 8), } stm32_cap_ch_cfg_t; -/* Slave mode control configure */ - typedef enum { - /* Slave mode selection */ - STM32_CAP_SMS_MASK = (7 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_INT = (0 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_ENC1 = (1 << GTIM_SMCR_SMS_SHIFT), @@ -143,9 +122,6 @@ typedef enum STM32_CAP_SMS_GAT = (5 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_TRG = (6 << GTIM_SMCR_SMS_SHIFT), STM32_CAP_SMS_EXT = (7 << GTIM_SMCR_SMS_SHIFT), - - /* Trigger selection */ - STM32_CAP_TS_MASK = (7 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR0 = (0 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ITR1 = (1 << GTIM_SMCR_TS_SHIFT), @@ -155,25 +131,16 @@ typedef enum STM32_CAP_TS_TI1FP1 = (5 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_TI2FP2 = (6 << GTIM_SMCR_TS_SHIFT), STM32_CAP_TS_ETRF = (7 << GTIM_SMCR_TS_SHIFT), - - /* Master/Slave mode setting */ - STM32_CAP_MSM_MASK = (1 << 7) } stm32_cap_smc_cfg_t; -/* Capture flags */ - typedef enum { - /* One of the following */ - STM32_CAP_FLAG_IRQ_COUNTER = (GTIM_SR_UIF), - STM32_CAP_FLAG_IRQ_CH_1 = (GTIM_SR_CC1IF), STM32_CAP_FLAG_IRQ_CH_2 = (GTIM_SR_CC2IF), STM32_CAP_FLAG_IRQ_CH_3 = (GTIM_SR_CC3IF), STM32_CAP_FLAG_IRQ_CH_4 = (GTIM_SR_CC4IF), - STM32_CAP_FLAG_OF_CH_1 = (GTIM_SR_CC1OF), STM32_CAP_FLAG_OF_CH_2 = (GTIM_SR_CC2OF), STM32_CAP_FLAG_OF_CH_3 = (GTIM_SR_CC3OF), @@ -184,8 +151,6 @@ typedef enum #define STM32_CAP_FLAG_OF_CH(ch) (GTIM_SR_CC1OF<<((ch)-1)) #define STM32_CAP_CHANNEL_COUNTER 0 -/* Capture Operations */ - struct stm32_cap_ops_s { int (*setsmc)(struct stm32_cap_dev_s *dev, stm32_cap_smc_cfg_t cfg); @@ -202,38 +167,9 @@ struct stm32_cap_ops_s uint32_t (*rstcounter)(struct stm32_cap_dev_s *dev); }; -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Power-up timer and get its structure */ - struct stm32_cap_dev_s *stm32_cap_init(int timer); - -/* Power-down timer, mark it as unused */ - int stm32_cap_deinit(struct stm32_cap_dev_s *dev); - -/**************************************************************************** - * Name: stm32_cap_initialize - * - * Description: - * Initialize one timer for use with the upper_level capture driver. - * - * Input Parameters: - * timer - A number identifying the timer use. The number of valid timer - * IDs varies with the STM32 MCU and MCU family but is somewhere in - * the range of {1,..,5 8,...,14}. - * - * Returned Value: - * On success, a pointer to the STM32 lower half capture driver returned. - * NULL is returned on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_CAPTURE struct cap_lowerhalf_s *stm32_cap_initialize(int timer); -#endif #undef EXTERN #if defined(__cplusplus) @@ -241,4 +177,5 @@ struct cap_lowerhalf_s *stm32_cap_initialize(int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CAPTURE_H */ diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c index 966f41a0a43..48fcfe57c73 100644 --- a/arch/arm/src/stm32/stm32_capture.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_capture_lowerhalf.c b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_capture_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c index 0246f5e28f9..ea4e0b174fb 100644 --- a/arch/arm/src/stm32/stm32_capture_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_capture_lowerhalf.c + * arch/arm/src/common/stm32/stm32_capture_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.c b/arch/arm/src/common/stm32/stm32_ccm.h similarity index 76% rename from arch/arm/src/stm32f0l0g0/stm32_flash.c rename to arch/arm/src/common/stm32/stm32_ccm.h index 010d5059c0c..432d3bf5492 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.c +++ b/arch/arm/src/common/stm32/stm32_ccm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.c + * arch/arm/src/common/stm32/stm32_ccm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,18 +20,19 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H + /**************************************************************************** * Included Files ****************************************************************************/ #include -#if defined(CONFIG_STM32_STM32G0) || defined(CONFIG_STM32_STM32C0) -# include "stm32g0c0_flash.c" +#if defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) +# include "stm32_ccm_m3m4_v1.h" #else -# error "Flash driver unsupported on selected chip." +# error "Unsupported STM32 stm32_ccm" #endif -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CCM_H */ diff --git a/arch/arm/src/stm32/stm32_ccm.c b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c similarity index 95% rename from arch/arm/src/stm32/stm32_ccm.c rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c index 9c87b61d4af..fb4507e1d08 100644 --- a/arch/arm/src/stm32/stm32_ccm.c +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.c + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -26,7 +26,7 @@ #include -#include "stm32_ccm.h" +#include "stm32_ccm_m3m4_v1.h" #ifdef HAVE_CCM_HEAP diff --git a/arch/arm/src/stm32/stm32_ccm.h b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_ccm.h rename to arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h index f5a38d3d41b..705a58c0804 100644 --- a/arch/arm/src/stm32/stm32_ccm.h +++ b/arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ccm.h + * arch/arm/src/common/stm32/stm32_ccm_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CCM_H -#define __ARCH_ARM_SRC_STM32_STM32_CCM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H /**************************************************************************** * Included Files @@ -46,7 +46,7 @@ #if defined(CONFIG_STM32_STM32F30XX) # define CCM_START 0x10000000 # define CCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#elif defined(CONFIG_STM32_HAVE_IP_CCM_M3M4_V1) || \ defined(CONFIG_STM32_STM32F33XX) # define CCM_START 0x10000000 # define CCM_END 0x10010000 @@ -122,4 +122,4 @@ EXTERN struct mm_heap_s *g_ccm_heap; #endif /* __ASSEMBLY__ */ #endif /* HAVE_CCM_HEAP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_CCM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CCM_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.h b/arch/arm/src/common/stm32/stm32_comp.h similarity index 51% rename from arch/arm/src/stm32/stm32_comp_v1.h rename to arch/arm/src/common/stm32/stm32_comp.h index 5389e5ddca1..8178f55e6d4 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.h +++ b/arch/arm/src/common/stm32/stm32_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.h + * arch/arm/src/common/stm32/stm32_comp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,41 +20,55 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H /**************************************************************************** * Included Files ****************************************************************************/ -#ifdef CONFIG_STM32_COMP +#include + +#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +#include "chip.h" + +#include "hardware/stm32_comp.h" /**************************************************************************** * Pre-processor definitions ****************************************************************************/ -#define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS /* No blanking */ -#define COMP_POL_DEFAULT COMP_POL_NONINVERT /* Output is not inverted */ -#define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF /* 1/4 of Vrefint as INM */ -#define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL /* Output not selected */ -#define COMP_LOCK_DEFAULT COMP_LOCK_RW /* Do not lock CSR register */ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) +# define COMP_BLANKING_DEFAULT COMP_BLANKING_DIS +# define COMP_POL_DEFAULT COMP_POL_NONINVERT +# define COMP_INM_DEFAULT COMP_INMSEL_1P4VREF +# define COMP_OUTSEL_DEFAULT COMP_OUTSEL_NOSEL +# define COMP_LOCK_DEFAULT COMP_LOCK_RW -#ifndef CONFIG_STM32_STM32F33XX -#define COMP_MODE_DEFAULT -#define COMP_HYST_DEFAULT -#define COMP_WINMODE_DEFAULT +# ifndef CONFIG_STM32_STM32F33XX +# define COMP_MODE_DEFAULT +# define COMP_HYST_DEFAULT +# define COMP_WINMODE_DEFAULT +# endif +# endif #endif /**************************************************************************** * Public Types ****************************************************************************/ +#ifdef CONFIG_STM32_COMP +# if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) + /* Blanking source */ enum stm32_comp_blanking_e { COMP_BLANKING_DIS, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_BLANKING_T1OC5, COMP_BLANKING_T3OC4, COMP_BLANKING_T2OC3, @@ -62,7 +76,7 @@ enum stm32_comp_blanking_e COMP_BLANKING_T15OC1, COMP_BLANKING_T2OC4, COMP_BLANKING_T15OC2, -#endif +# endif }; /* Output polarisation */ @@ -91,7 +105,7 @@ enum stm32_comp_inm_e enum stm32_comp_outsel_e { COMP_OUTSEL_NOSEL, -#if defined(CONFIG_STM32_STM32F33XX) +# if defined(CONFIG_STM32_STM32F33XX) COMP_OUTSEL_BRKACTH, COMP_OUTSEL_BRK2, COMP_OUTSEL_T1OCC, /* COMP2 only */ @@ -106,7 +120,7 @@ enum stm32_comp_outsel_e COMP_OUTSEL_T15OCC, /* COMP4 only */ COMP_OUTSEL_T16CAP1, /* COMP6 only */ COMP_OUTSEL_T3OCC, /* COMP2 and COMP4 only */ -#endif +# endif }; /* CSR register lock state */ @@ -117,9 +131,9 @@ enum stm32_comp_lock_e COMP_LOCK_RO }; -#ifndef CONFIG_STM32_STM32F33XX +# ifndef CONFIG_STM32_STM32F33XX -/* Hysteresis */ +/* Hysteresis */ enum stm32_comp_hyst_e { @@ -147,7 +161,109 @@ enum stm32_comp_winmode_e COMP_WINMODE_EN }; +# endif +# elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) + +/* Inverting input. See Table 196 in RM0440 */ + +enum stm32_comp_inm_e +{ + COMP_INM_1_4_VREF, + COMP_INM_1_2_VREF, + COMP_INM_3_4_VREF, + COMP_INM_VREF, + COMP_INM_DAC_1, + COMP_INM_DAC_2, + COMP_INM_PIN_1, + COMP_INM_PIN_2, +}; + +/* Non-inverting input. See Table 195 in RM0440 */ + +enum stm32_comp_inp_e +{ + COMP_INP_PIN_1, + COMP_INP_PIN_2, +}; + +/* Output polarity */ + +enum stm32_comp_pol_e +{ + COMP_POL_NONINVERT, + COMP_POL_INVERTED +}; + +/* Hysteresis */ + +enum stm32_comp_hyst_e +{ + COMP_HYST_DIS, + COMP_HYST_10MV, + COMP_HYST_20MV, + COMP_HYST_30MV, + COMP_HYST_40MV, + COMP_HYST_50MV, + COMP_HYST_60MV, + COMP_HYST_70MV, +}; + +/* Blanking source */ + +enum stm32_comp_blanking_e +{ + COMP_BLANKING_DIS, + COMP_BLANKING_TIMX_OCY_1, + COMP_BLANKING_TIMX_OCY_2, + COMP_BLANKING_TIMX_OCY_3, + COMP_BLANKING_TIMX_OCY_4, + COMP_BLANKING_TIMX_OCY_5, + COMP_BLANKING_TIMX_OCY_6, + COMP_BLANKING_TIMX_OCY_7, +}; + +# endif +#endif /* CONFIG_STM32_COMP */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern #endif -#endif /* CONFIG_STM23_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V1_H */ +/**************************************************************************** + * Name: stm32_compinitialize + * + * Description: + * Initialize the COMP. + * + * Input Parameters: + * intf - The COMP interface number. + * + * Returned Value: + * Valid COMP device structure reference on success; a NULL on failure. + * + * Assumptions: + * 1. Clock to the COMP block has enabled, + * 2. Board-specific logic has already configured + * + ****************************************************************************/ + +struct comp_dev_s *stm32_compinitialize(int intf); + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_COMP_M3M4_V1 || CONFIG_STM32_HAVE_IP_COMP_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_COMP_H */ diff --git a/arch/arm/src/stm32/stm32_comp_v1.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v1.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c index 17e5ccefab2..5af2ab52177 100644 --- a/arch/arm/src/stm32/stm32_comp_v1.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v1.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_comp_v2.c b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_comp_v2.c rename to arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c index d6fbae9c202..8939e4a6ce9 100644 --- a/arch/arm/src/stm32/stm32_comp_v2.c +++ b/arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.c + * arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c * * SPDX-License-Identifier: Apache-2.0 * @@ -24,6 +24,23 @@ * Included Files ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_comp.h" +#include "stm32_gpio.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial.h b/arch/arm/src/common/stm32/stm32_cordic.h similarity index 75% rename from arch/arm/src/stm32f0l0g0/stm32_serial.h rename to arch/arm/src/common/stm32/stm32_cordic.h index 725db01e521..aa536a50f26 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial.h +++ b/arch/arm/src/common/stm32/stm32_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial.h + * arch/arm/src/common/stm32/stm32_cordic.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H /**************************************************************************** * Included Files @@ -29,8 +29,10 @@ #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_CORDIC_M3M4_V1) +# include "stm32_cordic_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_cordic" +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SERIAL_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_cordic.c b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_cordic.c rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c index a9ab089a7fb..e77afc841a1 100644 --- a/arch/arm/src/stm32/stm32_cordic.c +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.c + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -39,7 +39,7 @@ #include "hardware/stm32g4xxxx_cordic.h" -#include "stm32_cordic.h" +#include "stm32_cordic_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_cordic.h b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_cordic.h rename to arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h index be6da8d85ef..84328ab75c1 100644 --- a/arch/arm/src/stm32/stm32_cordic.h +++ b/arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_cordic.h + * arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_CORDIC_H -#define __ARCH_ARM_SRC_STM32_STM32_CORDIC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ struct cordic_lowerhalf_s *stm32_cordicinitialize(void); -#endif /* __ARCH_ARM_SRC_STM32_STM32_CORDIC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_CORDIC_H */ diff --git a/arch/arm/src/stm32/stm32_crypto.c b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_crypto.c rename to arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c index cf4646e04ee..8a88cff4803 100644 --- a/arch/arm/src/stm32/stm32_crypto.c +++ b/arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_crypto.c + * arch/arm/src/common/stm32/stm32_crypto_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac.h new file mode 100644 index 00000000000..192a666ec93 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dac.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dac.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) +# include "stm32_dac_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dac" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dac.c b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dac.c rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c index 873e3af5431..c9cb731658f 100644 --- a/arch/arm/src/stm32/stm32_dac.c +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.c + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -41,7 +41,7 @@ #include "arm_internal.h" #include "chip.h" #include "stm32.h" -#include "stm32_dac.h" +#include "stm32_dac_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_dma.h" #include "stm32_syscfg.h" @@ -145,7 +145,7 @@ # undef CONFIG_STM32_DAC1CH2_DMA # undef CONFIG_STM32_DAC2CH1_DMA # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # ifndef CONFIG_STM32_DMA1 # warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1" # undef CONFIG_STM32_DAC1CH1_DMA @@ -235,7 +235,7 @@ # if defined(CONFIG_STM32_DAC2CH1) && !defined(CONFIG_STM32_DAC2CH1_DMA_EXTERNAL) # define DAC2CH1_DMA_CHAN DMACHAN_DAC2_CH1 # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) # define HAVE_DMA 1 # define DAC_DMA 1 # if defined(CONFIG_STM32_DAC1CH1) && !defined(CONFIG_STM32_DAC1CH1_DMA_EXTERNAL) @@ -524,9 +524,12 @@ #warning "Missing Logic" -/* DMA stream/channel configuration */ +/* DMA stream/channel configuration. The register layout depends on the DMA + * IP version, not the DAC IP version: stream DMA (IPv2) uses the SCR + * register fields, while channel DMA (IPv1) uses the CCR register fields. + */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define DAC_DMA_CONTROL_WORD (DMA_SCR_MSIZE_16BITS | \ DMA_SCR_PSIZE_16BITS | \ DMA_SCR_MINC | \ @@ -603,7 +606,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, /* Interrupt handler */ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg); #endif @@ -971,7 +974,7 @@ static void tim_modifyreg(struct stm32_chan_s *chan, int offset, * ****************************************************************************/ -#if 0 /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#if 0 /* defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) */ static int dac_interrupt(int irq, void *context, void *arg) { #warning "Missing logic" diff --git a/arch/arm/src/stm32/stm32_dac.h b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_dac.h rename to arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h index b031fa463d8..9683dab6d88 100644 --- a/arch/arm/src/stm32/stm32_dac.h +++ b/arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dac.h + * arch/arm/src/common/stm32/stm32_dac_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DAC_H -#define __ARCH_ARM_SRC_STM32_STM32_DAC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H /**************************************************************************** * Included Files @@ -29,6 +29,9 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DAC_M3M4_V2) + #include "chip.h" #include "hardware/stm32_dac.h" @@ -136,4 +139,6 @@ struct dac_dev_s *stm32_dacinitialize(int intf); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DAC_H */ +#endif /* CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 || CONFIG_STM32_HAVE_IP_DAC_M3M4_V2 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DAC_H */ diff --git a/arch/arm/src/stm32/stm32_dbgmcu.h b/arch/arm/src/common/stm32/stm32_dbgmcu.h similarity index 82% rename from arch/arm/src/stm32/stm32_dbgmcu.h rename to arch/arm/src/common/stm32/stm32_dbgmcu.h index 1695141ff16..4b1b2f81ee3 100644 --- a/arch/arm/src/stm32/stm32_dbgmcu.h +++ b/arch/arm/src/common/stm32/stm32_dbgmcu.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dbgmcu.h + * arch/arm/src/common/stm32/stm32_dbgmcu.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H -#define __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H /**************************************************************************** * Included Files @@ -29,6 +29,10 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) + #include "chip.h" #include "hardware/stm32_dbgmcu.h" @@ -48,4 +52,6 @@ * Public Function Prototypes ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DBGMCU_H */ +#endif /* CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1 || ... */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DBGMCU_H */ diff --git a/arch/arm/src/common/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode.h new file mode 100644 index 00000000000..593c06fad90 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dfumode.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dfumode.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) +# include "stm32_dfumode_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dfumode" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DFUMODE_H */ diff --git a/arch/arm/src/stm32/stm32_dfumode.c b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_dfumode.c rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c index 45b8b0e9cd4..40bb4b28ad0 100644 --- a/arch/arm/src/stm32/stm32_dfumode.c +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.c + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include -#include "stm32_dfumode.h" +#include "stm32_dfumode_m3m4_v1.h" /**************************************************************************** * Public Functions @@ -56,7 +56,7 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) { #ifdef CONFIG_DEBUG_WARN @@ -77,4 +77,4 @@ void stm32_dfumode(void) __builtin_unreachable(); /* Tell compiler we will not return */ } -#endif /* CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1 */ diff --git a/arch/arm/src/stm32/stm32_dfumode.h b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h similarity index 87% rename from arch/arm/src/stm32/stm32_dfumode.h rename to arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h index 332ef05c097..5a3c639fc12 100644 --- a/arch/arm/src/stm32/stm32_dfumode.h +++ b/arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dfumode.h + * arch/arm/src/common/stm32/stm32_dfumode_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H -#define __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H /**************************************************************************** * Included Files @@ -44,8 +44,8 @@ * ****************************************************************************/ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_DFUMODE_M3M4_V1) void stm32_dfumode(void) noreturn_function; #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_DFUMODE_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DFUMODE_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma.h new file mode 100644 index 00000000000..16124d4a4b7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) || \ + defined(CONFIG_STM32_HAVE_IP_DMA_V2) +# include "stm32_dma_channel_stream.h" +#else +# error "Unsupported STM32 DMA" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_H */ diff --git a/arch/arm/src/common/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d.h new file mode 100644 index 00000000000..548dd220034 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_dma2d.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_dma2d.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_dma2d_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_dma2d" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma2d.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma2d.c rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index 83b98668454..e129ee671ce 100644 --- a/arch/arm/src/stm32/stm32_dma2d.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.c + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -48,8 +48,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ccm.h" -#include "stm32_dma2d.h" +#include "stm32_dma2d_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_dma2d.h b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_dma2d.h rename to arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h index f8627cfe105..5bc43e6da99 100644 --- a/arch/arm/src/stm32/stm32_dma2d.h +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma2d.h + * arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA2D_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA2D_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H /**************************************************************************** * Included Files @@ -189,4 +189,4 @@ int stm32_dma2dinitialize(void); void stm32_dma2duninitialize(void); #endif /* CONFIG_FB_OVERLAY */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA2D_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA2D_H */ diff --git a/arch/arm/src/stm32/stm32_dma.h b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h similarity index 97% rename from arch/arm/src/stm32/stm32_dma.h rename to arch/arm/src/common/stm32/stm32_dma_channel_stream.h index f7eb641ef86..aec408a5527 100644 --- a/arch/arm/src/stm32/stm32_dma.h +++ b/arch/arm/src/common/stm32/stm32_dma_channel_stream.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma.h + * arch/arm/src/common/stm32/stm32_dma_channel_stream.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32_STM32_DMA_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H /**************************************************************************** * Included Files @@ -349,4 +349,4 @@ uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_DMA_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_DMA_CHANNEL_STREAM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c index 3117fad02ec..06ae4eaf7ea 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index e622ab417d5..6fb57a23624 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v1.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c index ebd0f3d0af5..2d18d541a1a 100644 --- a/arch/arm/src/stm32/stm32_dma_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c * * SPDX-License-Identifier: Apache-2.0 * @@ -55,14 +55,14 @@ * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_STM32_HAVE_DMA1_CHAN8) +#if defined(CONFIG_STM32_DMA1_HAVE_CHAN8) # define DMA1_NCHANNELS 8 #else # define DMA1_NCHANNELS 7 #endif #if STM32_NDMA > 1 -# if defined(CONFIG_STM32_HAVE_DMA2_CHAN678) +# if defined(CONFIG_STM32_DMA2_HAVE_CHAN678) # define DMA2_NCHANNELS 8 # else # define DMA2_NCHANNELS 5 diff --git a/arch/arm/src/stm32/stm32_dma_v1mux.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v1mux.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c index d518dcf801c..dd8892f0f65 100644 --- a/arch/arm/src/stm32/stm32_dma_v1mux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v1mux.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch_dmamux.c * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #include -#include +#include #include "arm_internal.h" #include "sched/sched.h" diff --git a/arch/arm/src/stm32/stm32_dma_v2.c b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c similarity index 99% rename from arch/arm/src/stm32/stm32_dma_v2.c rename to arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c index ed3784d5388..0fadcf45a61 100644 --- a/arch/arm/src/stm32/stm32_dma_v2.c +++ b/arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dma_v2.c + * arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_dumpgpio.c b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_dumpgpio.c rename to arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c index 1f21684650b..429e3e70a16 100644 --- a/arch/arm/src/stm32/stm32_dumpgpio.c +++ b/arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_dumpgpio.c + * arch/arm/src/common/stm32/stm32_dumpgpio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -191,7 +191,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg) getreg32(base + STM32_GPIO_AFRL_OFFSET), getreg32(base + STM32_GPIO_BRR_OFFSET)); -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_EXTI_V1) DEBUGASSERT(port < STM32_NGPIO_PORTS); _info("GPIO%c pinset: %08" PRIx32 " base: %08" PRIx32 " -- %s\n", diff --git a/arch/arm/src/common/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth.h new file mode 100644 index 00000000000..6e772732396 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_eth.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_eth.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) +# include "stm32_eth_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_eth" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32ETH_H */ diff --git a/arch/arm/src/stm32/stm32_eth.c b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_eth.c rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c index 3f1fdf514a3..3fc669d3ff7 100644 --- a/arch/arm/src/stm32/stm32_eth.c +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.c + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,9 +57,11 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include "stm32_rcc.h" #include "stm32_syscfg.h" -#include "stm32_eth.h" +#include "stm32_gpio.h" +#include "stm32_eth_m3m4_v1.h" #include @@ -113,7 +115,7 @@ #endif #ifdef CONFIG_STM32_MII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_MII_MCO1) && !defined(CONFIG_STM32_MII_MCO2) && !defined(CONFIG_STM32_MII_EXTCLK) # warning "Neither CONFIG_STM32_MII_MCO1, CONFIG_STM32_MII_MCO2, nor CONFIG_STM32_MII_EXTCLK defined" # endif @@ -128,7 +130,7 @@ #endif #ifdef CONFIG_STM32_RMII -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) # if !defined(CONFIG_STM32_RMII_MCO1) && !defined(CONFIG_STM32_RMII_MCO2) && !defined(CONFIG_STM32_RMII_EXTCLK) # warning "Neither CONFIG_STM32_RMII_MCO1, CONFIG_STM32_RMII_MCO2, nor CONFIG_STM32_RMII_EXTCLK defined" # endif @@ -322,7 +324,7 @@ * ETH_MACCR_CSTF Bits 25: CRC stripping for Type frames (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define MACCR_CLEAR_BITS \ (ETH_MACCR_RE | ETH_MACCR_TE | ETH_MACCR_DC | ETH_MACCR_BL_MASK | \ ETH_MACCR_APCS | ETH_MACCR_RD | ETH_MACCR_IPCO | ETH_MACCR_DM | \ @@ -518,7 +520,7 @@ * ETH_DMABMR_MB Bit 26: Mixed burst (F2/F4 only) */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_ETHMAC_M3M4_V1) #define DMABMR_CLEAR_MASK \ (ETH_DMABMR_SR | ETH_DMABMR_DA | ETH_DMABMR_DSL_MASK | ETH_DMABMR_EDFE | \ ETH_DMABMR_PBL_MASK | ETH_DMABMR_RTPR_MASK | ETH_DMABMR_FB | ETH_DMABMR_RDP_MASK | \ diff --git a/arch/arm/src/stm32/stm32_eth.h b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h similarity index 94% rename from arch/arm/src/stm32/stm32_eth.h rename to arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h index 68515b80006..e2cfbdefe70 100644 --- a/arch/arm/src/stm32/stm32_eth.h +++ b/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_eth.h + * arch/arm/src/common/stm32/stm32_eth_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_ETH_H -#define __ARCH_ARM_SRC_STM32_STM32_ETH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H /**************************************************************************** * Included Files @@ -106,4 +106,4 @@ int stm32_phy_boardinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* STM32_NETHERNET > 0 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ETH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ETH_H */ diff --git a/arch/arm/src/stm32/stm32_exti.h b/arch/arm/src/common/stm32/stm32_exti.h similarity index 94% rename from arch/arm/src/stm32/stm32_exti.h rename to arch/arm/src/common/stm32/stm32_exti.h index ae9ac9dba4c..8e301cf9997 100644 --- a/arch/arm/src/stm32/stm32_exti.h +++ b/arch/arm/src/common/stm32/stm32_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti.h + * arch/arm/src/common/stm32/stm32_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32_STM32_EXTI_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H /**************************************************************************** * Included Files @@ -31,6 +31,9 @@ #include +#include +#include + #include "chip.h" #include "hardware/stm32_exti.h" @@ -127,4 +130,5 @@ int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_EXTI_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32/stm32_exti_alarm.c b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_alarm.c rename to arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c index e908fbae17f..e7b7d07cf81 100644 --- a/arch/arm/src/stm32/stm32_exti_alarm.c +++ b/arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_alarm.c + * arch/arm/src/common/stm32/stm32_exti_alarm_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c index 5e8beb51a12..00b9158085c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_exti_gpio.c b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_exti_gpio.c rename to arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c index abe6146c0be..db62fac13f6 100644 --- a/arch/arm/src/stm32/stm32_exti_gpio.c +++ b/arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_gpio.c + * arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr.h new file mode 100644 index 00000000000..f99225e5850 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_exti_pwr.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_exti_pwr.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_exti_pwr_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_exti_pwr" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32EXTIPWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_pwr.c b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32/stm32_exti_pwr.c rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c index 97b0060ac8c..0b83b171c19 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.c +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.c + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,8 +37,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" #include "stm32_exti.h" -#include "stm32_exti_pwr.h" +#include "stm32_gpio.h" +#include "stm32_exti_pwr_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_exti_pwr.h b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h similarity index 90% rename from arch/arm/src/stm32/stm32_exti_pwr.h rename to arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h index 9eb22090c60..41058ed24aa 100644 --- a/arch/arm/src/stm32/stm32_exti_pwr.h +++ b/arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_pwr.h + * arch/arm/src/common/stm32/stm32_exti_pwr_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef STM32_EXTI_PWR_H_ -#define STM32_EXTI_PWR_H_ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H /**************************************************************************** * Included Files @@ -55,4 +55,4 @@ int stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, xcpt_t func, void *arg); -#endif /* STM32_EXTI_PWR_H_ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32/stm32_exti_wakeup.c b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_exti_wakeup.c rename to arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c index dce70638d43..f3baba30545 100644 --- a/arch/arm/src/stm32/stm32_exti_wakeup.c +++ b/arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_exti_wakeup.c + * arch/arm/src/common/stm32/stm32_exti_wakeup_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_fdcan.h new file mode 100644 index 00000000000..8a2dc52c68a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fdcan.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fdcan.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/stm32_fdcan.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Port numbers for use with stm32_fdcan_initialize() */ + +#define FDCAN1 1 + +#if defined(CONFIG_STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1) +# define FDCAN2 2 +# define FDCAN3 3 +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +#ifdef CONFIG_STM32_FDCAN_CHARDRIVER +struct can_dev_s *stm32_fdcaninitialize(int port); +#endif + +#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_fdcansockinitialize(int port); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index d32259614db..e12f93b77fd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c index f17be5729df..d118271cf97 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m0_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c index 2e2574217eb..300545fefee 100644 --- a/arch/arm/src/stm32/stm32_fdcan.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fdcan_sock.c b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c similarity index 99% rename from arch/arm/src/stm32/stm32_fdcan_sock.c rename to arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c index b4f37e29c65..55d16f42349 100644 --- a/arch/arm/src/stm32/stm32_fdcan_sock.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan_sock.c + * arch/arm/src/common/stm32/stm32_fdcan_m3m4_v1_sock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_flash.h b/arch/arm/src/common/stm32/stm32_flash.h similarity index 70% rename from arch/arm/src/stm32f0l0g0/stm32_flash.h rename to arch/arm/src/common/stm32/stm32_flash.h index 1c670fa862c..9050b255d6b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_flash.h +++ b/arch/arm/src/common/stm32/stm32_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_flash.h + * arch/arm/src/common/stm32/stm32_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,48 +20,47 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include #include #include "chip.h" #include "hardware/stm32_flash.h" /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -# define EXTERN extern "C" -extern "C" -{ -#else -# define EXTERN extern -#endif +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M0_V1) void stm32_flash_getopt(uint32_t *opt); - int stm32_flash_optmodify(uint32_t clear, uint32_t set); - void stm32_flash_lock(void); - void stm32_flash_unlock(void); -#undef EXTERN -#if defined(__cplusplus) -} +#elif defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_V1) + +int stm32_flash_lock(void); +int stm32_flash_unlock(void); +uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); +size_t stm32_eeprom_size(void); +size_t stm32_eeprom_getaddress(void); +ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); +ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); + #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FLASH_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c index 1acb1b4a597..ec3a06037fb 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0c0_flash.c + * arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxf30xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c index a35d47482ba..5bdb27b1ddc 100644 --- a/arch/arm/src/stm32/stm32f10xxf30xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxf30xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c similarity index 97% rename from arch/arm/src/stm32/stm32f20xxf40xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c index f8125b7ceb9..afd7300dda0 100644 --- a/arch/arm/src/stm32/stm32f20xxf40xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxf40xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,7 +47,7 @@ /* Only for the STM32F[2|4]0xx family. */ -#if defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) +#if defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) #if defined(CONFIG_STM32_FLASH_CONFIG_DEFAULT) # warning "Default Flash Configuration Used - See Override Flash Size Designator" @@ -449,4 +449,4 @@ uint8_t up_progmem_erasestate(void) return FLASH_ERASEDVALUE; } -#endif /* defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) */ +#endif /* defined(CONFIG_STM32_HAVE_IP_FLASH_M3M4_F2F4) */ diff --git a/arch/arm/src/stm32/stm32g4xxx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c index c14dd875a9a..f2d722e4799 100644 --- a/arch/arm/src/stm32/stm32g4xxx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xx_flash.c b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xx_flash.c rename to arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c index 4051a7eafda..ec1379498f4 100644 --- a/arch/arm/src/stm32/stm32l15xx_flash.c +++ b/arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xx_flash.c + * arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc.h new file mode 100644 index 00000000000..c113a799541 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) +# include "stm32_fmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FMC_H */ diff --git a/arch/arm/src/stm32/stm32_fmc.c b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_fmc.c rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c index 4f0ac88e2a1..aa91d1824b2 100644 --- a/arch/arm/src/stm32/stm32_fmc.c +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.c + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_fmc.h b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_fmc.h rename to arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h index 9644068d0ee..a29da3062fe 100644 --- a/arch/arm/src/stm32/stm32_fmc.h +++ b/arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fmc.h + * arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H -#define __ARCH_ARM_STC_STM32_STM32_FMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fmc.h" @@ -133,4 +135,6 @@ void stm32_fmc_sdram_command(uint32_t cmd); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_FMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc.h new file mode 100644 index 00000000000..4f1b673f567 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_foc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_foc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_COMMON_FOC) +# include "stm32_foc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_foc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FOC_H */ diff --git a/arch/arm/src/stm32/stm32_foc.c b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_foc.c rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c index 4982a812b12..a50572a8bc5 100644 --- a/arch/arm/src/stm32/stm32_foc.c +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.c + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -38,13 +38,15 @@ #include "arm_internal.h" #include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "stm32_adc.h" #include "stm32_dma.h" #include #include -#include "stm32_foc.h" +#include "stm32_pwm.h" +#include "stm32_foc_m3m4_v1.h" #include "hardware/stm32_dbgmcu.h" @@ -141,10 +143,9 @@ /* Debug register for PWM timers */ -#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +#if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ) -#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +#elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC_PWM_FZ_REG (STM32_DBGMCU_CR) #endif @@ -154,10 +155,9 @@ # define FOC0_PWM (1) # define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS) # define FOC0_PWM_BASE (STM32_TIM1_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP) # endif # if CONFIG_STM32_TIM1_MODE != 2 @@ -171,10 +171,9 @@ # define FOC1_PWM (8) # define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS) # define FOC1_PWM_BASE (STM32_TIM8_BASE) -# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V2) || \ - defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V3) +# if defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_APB2_FZ) # define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP) -# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_M3M4_V1) +# elif defined(CONFIG_STM32_DBGMCU_HAVE_TIM_FZ_IN_CR) # define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP) # endif # if CONFIG_STM32_TIM8_MODE != 2 diff --git a/arch/arm/src/stm32/stm32_foc.h b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_foc.h rename to arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h index bfc145dbda8..58cddf08b2b 100644 --- a/arch/arm/src/stm32/stm32_foc.h +++ b/arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_foc.h + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FOC_H -#define __ARCH_ARM_SRC_STM32_STM32_FOC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H /**************************************************************************** * Included Files @@ -200,4 +200,4 @@ struct adc_dev_s *stm32_foc_adcget(struct foc_dev_s *dev); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FOC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FOC_H */ diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_freerun.h similarity index 54% rename from arch/arm/src/stm32/stm32_waste.h rename to arch/arm/src/common/stm32/stm32_freerun.h index 39a9b88893e..155917f7ea3 100644 --- a/arch/arm/src/stm32/stm32_waste.h +++ b/arch/arm/src/common/stm32/stm32_freerun.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.h + * arch/arm/src/common/stm32/stm32_freerun.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,16 +20,36 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H -#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H - -/* Waste CPU Time */ +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H /**************************************************************************** - * Pre-processor Definitions + * Included Files ****************************************************************************/ -#ifndef __ASSEMBLY__ +#include + +#include +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_FREERUN + +struct stm32_freerun_s +{ + uint8_t chan; + uint8_t width; + struct stm32_tim_dev_s *tch; + uint32_t frequency; +#ifndef CONFIG_CLOCK_TIMEKEEPING + uint32_t overflow; +#endif +#ifdef CONFIG_CLOCK_TIMEKEEPING + uint64_t counter_mask; +#endif +}; #undef EXTERN #if defined(__cplusplus) @@ -40,27 +60,22 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/* Waste CPU Time - * - * stm32_waste() is the logic that will be executed when portions of kernel - * or user-app is polling some register or similar, waiting for desired - * status. This time is wasted away. This function offers a measure of - * badly written piece of software or some undesired behavior. - * - * At the same time this function adds to some IDLE time which portion - * cannot be used for other purposes (yet). - */ - -void stm32_waste(void); +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution); +#ifndef CONFIG_CLOCK_TIMEKEEPING +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts); +#else +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + uint64_t *counter); +#endif +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WASTE_H */ +#endif /* CONFIG_STM32_FREERUN */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_freerun.c rename to arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c index af5599a9314..e8122d5ef41 100644 --- a/arch/arm/src/stm32/stm32_freerun.c +++ b/arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.c + * arch/arm/src/common/stm32/stm32_freerun_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc.h new file mode 100644 index 00000000000..15951027c41 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_fsmc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_fsmc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) +# include "stm32_fsmc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_fsmc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32FSMC_H */ diff --git a/arch/arm/src/stm32/stm32_fsmc.c b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c similarity index 93% rename from arch/arm/src/stm32/stm32_fsmc.c rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c index 5bfc967a961..c72cf09477f 100644 --- a/arch/arm/src/stm32/stm32_fsmc.c +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.c + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,7 @@ void stm32_fsmc_enable(void) modifyreg32(STM32_RCC_AHBENR, 0, RCC_AHBENR_FSMCEN); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_enable(void) { @@ -73,7 +73,7 @@ void stm32_fsmc_disable(void) modifyreg32(STM32_RCC_AHBENR, RCC_AHBENR_FSMCEN, 0); } -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) void stm32_fsmc_disable(void) { diff --git a/arch/arm/src/stm32/stm32_fsmc.h b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h similarity index 88% rename from arch/arm/src/stm32/stm32_fsmc.h rename to arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h index df340763016..215ce47c016 100644 --- a/arch/arm/src/stm32/stm32_fsmc.h +++ b/arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fsmc.h + * arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FSMC_H -#define __ARCH_ARM_SRC_STM32_STM32_FSMC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1) + #include "chip.h" #include "hardware/stm32_fsmc.h" @@ -73,4 +75,6 @@ void stm32_fsmc_disable(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FSMC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_FSMC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_FSMC_H */ diff --git a/arch/arm/src/common/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio.h new file mode 100644 index 00000000000..f4910cabef1 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_gpio.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) +# include "stm32_gpio_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1) +# include "stm32_gpio_m3m4_v1v2.h" +#else +# error "Unsupported STM32 GPIO" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_GPIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.c index 7917ca44a79..3313cba03cd 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include #include -#include +#include #include #include "arm_internal.h" diff --git a/arch/arm/src/stm32f0l0g0/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m0_v1.h index 0d6e7c881ac..43990a8514a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H /**************************************************************************** * Included Files @@ -35,7 +35,7 @@ #endif #include -#include +#include #include "chip.h" #include "hardware/stm32_gpio.h" @@ -364,4 +364,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V2_M0_H */ diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.c rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c index 947d75bf042..14fe1654baa 100644 --- a/arch/arm/src/stm32/stm32_gpio.c +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.c + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h similarity index 99% rename from arch/arm/src/stm32/stm32_gpio.h rename to arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h index 8fc0ef475eb..17689d672d9 100644 --- a/arch/arm/src/stm32/stm32_gpio.h +++ b/arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_gpio.h + * arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H -#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H /**************************************************************************** * Included Files @@ -559,4 +559,4 @@ void stm32_gpioinit(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_GPIO_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_GPIO_V1V2_H */ diff --git a/arch/arm/src/stm32/stm32_hall3ph.c b/arch/arm/src/common/stm32/stm32_hall3ph.c similarity index 98% rename from arch/arm/src/stm32/stm32_hall3ph.c rename to arch/arm/src/common/stm32/stm32_hall3ph.c index 4eff99aee76..d6f7d360f5c 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.c +++ b/arch/arm/src/common/stm32/stm32_hall3ph.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.c + * arch/arm/src/common/stm32/stm32_hall3ph.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,6 +37,7 @@ #include "chip.h" #include "arm_internal.h" +#include "stm32_gpio.h" #include "stm32_hall3ph.h" /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32_hall3ph.h b/arch/arm/src/common/stm32/stm32_hall3ph.h similarity index 85% rename from arch/arm/src/stm32/stm32_hall3ph.h rename to arch/arm/src/common/stm32/stm32_hall3ph.h index 97a7bde16bf..e8329f84b29 100644 --- a/arch/arm/src/stm32/stm32_hall3ph.h +++ b/arch/arm/src/common/stm32/stm32_hall3ph.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hall3ph.h + * arch/arm/src/common/stm32/stm32_hall3ph.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H -#define __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H /**************************************************************************** * Included Files @@ -47,10 +47,6 @@ struct stm32_hall3ph_cfg_s * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: stm32_hall3ph_initialize - ****************************************************************************/ - /**************************************************************************** * Name: stm32_hall3ph_initialize * @@ -62,4 +58,4 @@ struct stm32_hall3ph_cfg_s int stm32_hall3ph_initialize(const char *devpath, struct stm32_hall3ph_cfg_s *cfg); -#endif /* __ARCH_ARM_SRC_STM32_STM32_HALL3PH_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HALL3PH_H */ diff --git a/arch/arm/src/common/stm32/stm32_hciuart.h b/arch/arm/src/common/stm32/stm32_hciuart.h new file mode 100644 index 00000000000..f1ae1f79c81 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hciuart.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hciuart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +enum hciuart_devno_e +{ + HCIUART1 = 0, + HCIUART2 = 1, + HCIUART3 = 2, + HCIUART5 = 5, + HCIUART6 = 6, + HCIUART7 = 7 +}; + +const struct btuart_lowerhalf_s * +hciuart_instantiate(enum hciuart_devno_e uart); +void hciuart_initialize(void); + +#ifdef CONFIG_STM32_HCIUART_RXDMA +void stm32_serial_dma_poll(void); +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.c b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hciuart.c rename to arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c index cca04ded723..5f77bdc2899 100644 --- a/arch/arm/src/stm32/stm32_hciuart.c +++ b/arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.c + * arch/arm/src/common/stm32/stm32_hciuart_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -46,9 +46,10 @@ #include "arm_internal.h" #include "chip.h" #include "stm32_uart.h" +#include "stm32_hciuart.h" #include "stm32_dma.h" #include "stm32_rcc.h" -#include "stm32_hciuart.h" +#include "stm32_uart.h" #include @@ -66,7 +67,7 @@ #ifdef CONFIG_STM32_HCIUART_RXDMA -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) /* Verify that DMA has been enabled and the DMA channel has been defined. */ @@ -152,7 +153,7 @@ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ defined(CONFIG_STM32_STM32F37XX) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_HCIUART_RXDMAPRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -164,7 +165,7 @@ # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_HCIUART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_HCIUART_RXDMAPRIO" # endif @@ -174,7 +175,7 @@ /* DMA control word */ -# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# if defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SERIAL_DMA_CONTROL_WORD \ (DMA_SCR_DIR_P2M | \ DMA_SCR_CIRC | \ diff --git a/arch/arm/src/common/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim.h new file mode 100644 index 00000000000..0be3fcfe2f7 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hrtim.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hrtim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HRTIM_M3M4_V1) +# include "stm32_hrtim_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_hrtim" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HRTIM_H */ diff --git a/arch/arm/src/stm32/stm32_hrtim.c b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.c rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c index 86e0a074b26..73791c4c21f 100644 --- a/arch/arm/src/stm32/stm32_hrtim.c +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.c + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32.h" #include "stm32_gpio.h" -#include "stm32_hrtim.h" +#include "stm32_hrtim_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_hrtim_m3m4_v1.h" #if defined(CONFIG_STM32_HRTIM1) diff --git a/arch/arm/src/stm32/stm32_hrtim.h b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h similarity index 99% rename from arch/arm/src/stm32/stm32_hrtim.h rename to arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h index 7934ca14bff..026c6e2e7f3 100644 --- a/arch/arm/src/stm32/stm32_hrtim.h +++ b/arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_hrtim.h + * arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_HRTIM_H -#define __ARCH_ARM_SRC_STM32_STM32_HRTIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H /**************************************************************************** * Included Files @@ -1136,4 +1136,4 @@ int hrtim_register(const char *path, struct hrtim_dev_s *dev); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_HRTIM1 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_HRTIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HRTIM_H */ diff --git a/arch/arm/src/common/stm32/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48.h new file mode 100644 index 00000000000..6116df0117e --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_hsi48.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_hsi48.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_HSI48_M0_V1) +# include "stm32_hsi48_m0_v1.h" +#else +# error "Unsupported STM32 stm32_hsi48" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32HSI48_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.c rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c index 9902f196f26..ac6162fc82b 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.c +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.c + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include "hardware/stm32_rcc.h" #include "hardware/stm32_crs.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_hsi48.h rename to arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h index 216fce2501e..095c9e62cc6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_hsi48.h +++ b/arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_hsi48.h + * arch/arm/src/common/stm32/stm32_hsi48_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H /**************************************************************************** * Included Files @@ -93,4 +93,4 @@ void stm32_enable_hsi48(enum syncsrc_e syncsrc); void stm32_disable_hsi48(void); #endif /* CONFIG_STM32_HAVE_HSI48 */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_HSI48_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_HSI48_H */ diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/common/stm32/stm32_i2c.h similarity index 84% rename from arch/arm/src/stm32/stm32_i2c.h rename to arch/arm/src/common/stm32/stm32_i2c.h index 1ad4f2b7f1a..834372fd75c 100644 --- a/arch/arm/src/stm32/stm32_i2c.h +++ b/arch/arm/src/common/stm32/stm32_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.h + * arch/arm/src/common/stm32/stm32_i2c.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32_STM32_I2C_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H /**************************************************************************** * Included Files @@ -88,6 +88,7 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port); int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); +#if defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) || defined(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) /**************************************************************************** * Name: stm32_i2cbus_slaveinitialize * @@ -104,22 +105,6 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); ****************************************************************************/ struct i2c_slave_s *stm32_i2cbus_slaveinitialize(int port); +#endif -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2C_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m0_v1.c index b2f689f9798..b8cbdebce4c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2011 Uros Platise. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c index da30fd1342d..4cc9c4f8291 100644 --- a/arch/arm/src/stm32/stm32_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -1281,7 +1281,7 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) * from the F1 in that BTF is not set after data is received (only RXNE). */ -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) || \ +#if defined(CONFIG_STM32_HAVE_IP_DMA_V2) || \ defined(CONFIG_STM32_STM32L15XX) if (priv->dcnt <= 0 && (status & (I2C_SR1_BTF | I2C_SR1_RXNE)) != 0) #else @@ -1941,5 +1941,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_alt.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_alt.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c index 115a5a8d103..3f4055fd0bf 100644 --- a/arch/arm/src/stm32/stm32_i2c_alt.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_alt.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. @@ -112,7 +112,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -172,7 +172,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2448,5 +2448,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32f40xxx_i2c.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_i2c.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c index 58b769fc5d9..9ed73e228db 100644 --- a/arch/arm/src/stm32/stm32f40xxx_i2c.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_i2c.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_f40xxx.c * * SPDX-License-Identifier: Apache-2.0 * @@ -89,7 +89,7 @@ */ #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \ - defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) + defined(CONFIG_STM32_HAVE_IP_DMA_V2) /**************************************************************************** * Pre-processor Definitions @@ -149,7 +149,7 @@ #elif defined(CONFIG_STM32_STM32F10XX) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_OUTPUT_SET | GPIO_CNF_OUTOD | \ GPIO_MODE_50MHz) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define I2C_OUTPUT (GPIO_OUTPUT | GPIO_FLOAT | GPIO_OPENDRAIN |\ GPIO_SPEED_50MHz | GPIO_OUTPUT_SET) #endif @@ -2690,5 +2690,5 @@ int stm32_i2cbus_uninitialize(struct i2c_master_s *dev) return OK; } -#endif /* CONFIG_STM32_STM32F10XX || CONFIG_STM32_STM32F20XX || CONFIG_STM32_STM32F4XXX */ +#endif /* CONFIG_STM32_HAVE_IP_I2C_M3M4_V1 */ #endif /* CONFIG_STM32_I2C1 || CONFIG_STM32_I2C2 || CONFIG_STM32_I2C3 */ diff --git a/arch/arm/src/stm32/stm32_i2c_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2c_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c index 87d9a1700e0..8b0fd802c5e 100644 --- a/arch/arm/src/stm32/stm32_i2c_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2c_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_i2cslave_v2.c b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2cslave_v2.c rename to arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c index bbf86c2e49d..53ce3975f16 100644 --- a/arch/arm/src/stm32/stm32_i2cslave_v2.c +++ b/arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2cslave_v2.c + * arch/arm/src/common/stm32/stm32_i2c_m3m4_v2_slave.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/arm/src/stm32/stm32_i2s.h b/arch/arm/src/common/stm32/stm32_i2s.h similarity index 78% rename from arch/arm/src/stm32/stm32_i2s.h rename to arch/arm/src/common/stm32/stm32_i2s.h index 5ed34136591..376fa24efed 100644 --- a/arch/arm/src/stm32/stm32_i2s.h +++ b/arch/arm/src/common/stm32/stm32_i2s.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.h + * arch/arm/src/common/stm32/stm32_i2s.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,32 +20,35 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_I2S_H -#define __ARCH_ARM_SRC_STM32_STM32_I2S_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include -#include "chip.h" +#ifdef CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 -#ifndef __ASSEMBLY__ +# include + +# include "chip.h" + +# ifndef __ASSEMBLY__ /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" +# undef EXTERN +# if defined(__cplusplus) +# define EXTERN extern "C" extern "C" { -#else -#define EXTERN extern -#endif +# else +# define EXTERN extern +# endif /**************************************************************************** * Public Function Prototypes @@ -67,10 +70,13 @@ extern "C" struct i2s_dev_s *stm32_i2sbus_initialize(int port); -#undef EXTERN -#if defined(__cplusplus) +# undef EXTERN +# if defined(__cplusplus) } -#endif +# endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_I2S_H */ +# endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_STM32_HAVE_IP_I2S_M3M4_V1 */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_I2S_H */ diff --git a/arch/arm/src/stm32/stm32_i2s.c b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_i2s.c rename to arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c index af156dd8a7e..49be32aa826 100644 --- a/arch/arm/src/stm32/stm32_i2s.c +++ b/arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_i2s.c + * arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -72,6 +72,7 @@ #include "arm_internal.h" #include "stm32_dma.h" +#include "stm32_i2s.h" #include "stm32_spi.h" #include "stm32_rcc.h" @@ -144,7 +145,7 @@ # define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -154,7 +155,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -176,7 +177,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/stm32f0l0g0/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m0_v1.c index 1b971a961ca..a9d6ff68a08 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_idle.c b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_idle.c rename to arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c index 22f559f2767..19f57a3117e 100644 --- a/arch/arm/src/stm32/stm32_idle.c +++ b/arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_idle.c + * arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m0_v1.c index c46388c2641..fb71ce0917a 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_irq.c rename to arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c index 57ed8ba1a44..c79c0bddd8d 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_irq.c + * arch/arm/src/common/stm32/stm32_irq_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c index f2821942020..172534d89e8 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -43,6 +43,14 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_IWDG) + +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -69,6 +77,14 @@ /* Configuration ************************************************************/ +#ifndef CONFIG_STM32_IWDG_DEFTIMOUT +# define CONFIG_STM32_IWDG_DEFTIMOUT IWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_IWDG_REGDEBUG +#endif + /* REVISIT: It appears that you can only setup the prescaler and reload * registers once. After that, the SR register's PVU and RVU bits never go * to zero. So we defer setting up these registers until the watchdog @@ -116,17 +132,25 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg16(addr) +# define stm32_putreg(val,addr) putreg16(val,addr) +#endif + static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); /**************************************************************************** * Private Data @@ -153,6 +177,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 IWDG register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_IWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setprescaler * @@ -170,7 +278,7 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) { /* Enable write access to IWDG_PR and IWDG_RLR registers */ - putreg32(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR); /* Wait for the PVU and RVU bits to be reset be hardware. These bits * were set the last time that the PR register was written and may not @@ -181,20 +289,20 @@ static inline void stm32_setprescaler(struct stm32_lowerhalf_s *priv) */ #ifndef CONFIG_STM32_IWDG_ONETIMESETUP - while ((getreg32(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); + while ((stm32_getreg(STM32_IWDG_SR) & (IWDG_SR_PVU | IWDG_SR_RVU)) != 0); #endif /* Set the prescaler */ - putreg32((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); + stm32_putreg((uint16_t)priv->prescaler << IWDG_PR_SHIFT, STM32_IWDG_PR); /* Set the reload value */ - putreg32((uint16_t)priv->reload, STM32_IWDG_RLR); + stm32_putreg((uint16_t)priv->reload, STM32_IWDG_RLR); /* Reload the counter (and disable write access) */ - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); } /**************************************************************************** @@ -244,7 +352,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_START, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_START, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); priv->started = true; leave_critical_section(flags); @@ -303,7 +411,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) /* Reload the IWDG timer */ flags = enter_critical_section(); - putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); + stm32_putreg(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR); priv->lastreset = clock_systime_ticks(); leave_critical_section(flags); @@ -561,33 +669,41 @@ void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq) */ stm32_rcc_enablelsi(); -#ifdef STM32_RCC_CSR wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR)); -#else - wdinfo("RCC CSR: %08" PRIx32 "\n", getreg32(STM32_RCC_CSR1)); -#endif /* Select an arbitrary initial timeout value. But don't start the watchdog * yet. NOTE: If the "Hardware watchdog" feature is enabled through the * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, IWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_IWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ watchdog_register(devpath, (struct watchdog_lowerhalf_s *)priv); - /* When the microcontroller enters debug mode (core halted), + /* When the microcontroller enters debug mode (Cortex-M4F core halted), * the IWDG counter either continues to work normally or stops, depending * on DBG_IWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_IWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_IWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_IWDG */ diff --git a/arch/arm/src/stm32/stm32_iwdg.c b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_iwdg.c rename to arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c index 8996a9e845e..026b0edf053 100644 --- a/arch/arm/src/stm32/stm32_iwdg.c +++ b/arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_iwdg.c + * arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h b/arch/arm/src/common/stm32/stm32_lowputc.h similarity index 90% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc.h rename to arch/arm/src/common/stm32/stm32_lowputc.h index 8158c50f813..0c2ddb9156d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc.h +++ b/arch/arm/src/common/stm32/stm32_lowputc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc.h + * arch/arm/src/common/stm32/stm32_lowputc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H /**************************************************************************** * Included Files @@ -63,4 +63,4 @@ void stm32_lowsetup(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LOWPUTC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c index 2f3e87315b3..03acef0e8d0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v1.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c index db8065517c3..154051ca63c 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lowputc_v2.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lowputc.c b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_lowputc.c rename to arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c index ff9659c9710..aa83d21a3b3 100644 --- a/arch/arm/src/stm32/stm32_lowputc.c +++ b/arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.c + * arch/arm/src/common/stm32/stm32_lowputc_usart_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m0_v1.c index 9fb81ae318e..0e5bc4fbc3d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_lse.c rename to arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c index 7f4d215ddc1..25f33542e59 100644 --- a/arch/arm/src/stm32/stm32_lse.c +++ b/arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lse.c + * arch/arm/src/common/stm32/stm32_lse_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m0_v1.c index cfcc05e1902..19aa04dd4f0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,11 +33,11 @@ * Pre-processor Definitions ****************************************************************************/ -/* STM32C0 use the second CSR register for LSI */ +/* STM32C0 uses the second CSR register for LSI. */ #ifdef CONFIG_ARCH_CHIP_STM32C0 -# define STM32_RCC_CSR STM32_RCC_CSR2 -# define RCC_CSR_LSION RCC_CSR2_LSION +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION # define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY #endif diff --git a/arch/arm/src/stm32/stm32_lsi.c b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c similarity index 92% rename from arch/arm/src/stm32/stm32_lsi.c rename to arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c index 45d15c8fab1..97ae757a001 100644 --- a/arch/arm/src/stm32/stm32_lsi.c +++ b/arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lsi.c + * arch/arm/src/common/stm32/stm32_lsi_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,6 +33,14 @@ * Pre-processor Definitions ****************************************************************************/ +/* STM32C0 uses the second CSR register for LSI. */ + +#ifdef CONFIG_ARCH_CHIP_STM32C0 +# define STM32_RCC_CSR STM32_RCC_CSR2 +# define RCC_CSR_LSION RCC_CSR2_LSION +# define RCC_CSR_LSIRDY RCC_CSR2_LSIRDY +#endif + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/arch/arm/src/common/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc.h new file mode 100644 index 00000000000..d51c2b4ba3d --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_ltdc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_ltdc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) +# include "stm32_ltdc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_ltdc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_ltdc.c b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_ltdc.c rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c index 8e36b797a5e..59bc7fc4484 100644 --- a/arch/arm/src/stm32/stm32_ltdc.c +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.c + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,8 +49,8 @@ #include "stm32.h" #include "hardware/stm32_ltdc.h" #include "hardware/stm32_dma2d.h" -#include "stm32_ltdc.h" -#include "stm32_dma2d.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_dma2d_m3m4_v1.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/stm32_ltdc.h b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h similarity index 91% rename from arch/arm/src/stm32/stm32_ltdc.h rename to arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h index 50e089869e0..c0e4e3adb5f 100644 --- a/arch/arm/src/stm32/stm32_ltdc.h +++ b/arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_ltdc.h + * arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_LTDC_H -#define __ARCH_ARM_SRC_STM32_STM32_LTDC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H /**************************************************************************** * Included Files @@ -29,6 +29,8 @@ #include +#if defined(CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1) + #include #include @@ -99,4 +101,6 @@ struct fb_vtable_s *stm32_ltdcgetvplane(int vplane); #ifdef CONFIG_STM32_LCD_BACKLIGHT void stm32_backlight(bool blon); #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_LTDC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_LTDC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_LTDC_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.h b/arch/arm/src/common/stm32/stm32_mpuinit.h similarity index 91% rename from arch/arm/src/stm32/stm32_mpuinit.h rename to arch/arm/src/common/stm32/stm32_mpuinit.h index f4af906ef4e..606d589ef28 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.h +++ b/arch/arm/src/common/stm32/stm32_mpuinit.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.h + * arch/arm/src/common/stm32/stm32_mpuinit.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H -#define __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void stm32_mpu_uheap(uintptr_t start, size_t size); # define stm32_mpu_uheap(start,size) #endif -#endif /* __ARCH_ARM_SRC_STM32_STM32_MPUINIT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_MPUINIT_H */ diff --git a/arch/arm/src/stm32/stm32_mpuinit.c b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_mpuinit.c rename to arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c index 6cc545c825e..cc066077de6 100644 --- a/arch/arm/src/stm32/stm32_mpuinit.c +++ b/arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_mpuinit.c + * arch/arm/src/common/stm32/stm32_mpuinit_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_oneshot.h b/arch/arm/src/common/stm32/stm32_oneshot.h new file mode 100644 index 00000000000..7cb508f67d4 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_oneshot.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_oneshot.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_ONESHOT + +#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ + CONFIG_STM32_ONESHOT_MAXTIMERS < 1 +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 +#endif + +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 +# warning Additional logic required to handle more than 8 timers +# undef CONFIG_STM32_ONESHOT_MAXTIMERS +# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 +#endif + +typedef void (*oneshot_handler_t)(void *arg); + +struct stm32_oneshot_s +{ + uint8_t chan; +#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 + uint8_t cbndx; +#endif + volatile bool running; + struct stm32_tim_dev_s *tch; + volatile oneshot_handler_t handler; + volatile void *arg; + uint32_t frequency; + uint32_t period; +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution); +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_ONESHOT */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c index b80df41e762..e8ba155e9da 100644 --- a/arch/arm/src/stm32/stm32_oneshot.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_oneshot_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c index 8d5c5c79a28..729adb4078c 100644 --- a/arch/arm/src/stm32/stm32_oneshot_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot_lowerhalf.c + * arch/arm/src/common/stm32/stm32_oneshot_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp.h new file mode 100644 index 00000000000..f3c9827a959 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_opamp.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_opamp.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_OPAMP_M3M4_V1) +# include "stm32_opamp_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_opamp" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_opamp.c b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_opamp.c rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c index 05f685eab55..7c90dae4b8b 100644 --- a/arch/arm/src/stm32/stm32_opamp.c +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.c + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -37,7 +37,9 @@ #include "chip.h" #include "stm32_gpio.h" -#include "stm32_opamp.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_opamp_m3m4_v1.h" /* OPAMP "upper half" support must be enabled */ diff --git a/arch/arm/src/stm32/stm32_opamp.h b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h similarity index 96% rename from arch/arm/src/stm32/stm32_opamp.h rename to arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h index b85acb37bff..d45a7532236 100644 --- a/arch/arm/src/stm32/stm32_opamp.h +++ b/arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_opamp.h + * arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H -#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H /**************************************************************************** * Included Files @@ -216,4 +216,4 @@ struct opamp_dev_s *stm32_opampinitialize(int intf); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OPAMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OPAMP_H */ diff --git a/arch/arm/src/stm32/stm32_otgfs.h b/arch/arm/src/common/stm32/stm32_otgfs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otgfs.h rename to arch/arm/src/common/stm32/stm32_otgfs.h index 42287bc2120..b7cf5962ed0 100644 --- a/arch/arm/src/stm32/stm32_otgfs.h +++ b/arch/arm/src/common/stm32/stm32_otgfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfs.h + * arch/arm/src/common/stm32/stm32_otgfs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGFS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGFS_H */ diff --git a/arch/arm/src/stm32/stm32_otgfsdev.c b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfsdev.c rename to arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c index 2f3c1416e7e..af02d027c98 100644 --- a/arch/arm/src/stm32/stm32_otgfsdev.c +++ b/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfsdev.c + * arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otgfshost.c b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otgfshost.c rename to arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c index b8a44c90178..1197648cd1b 100644 --- a/arch/arm/src/stm32/stm32_otgfshost.c +++ b/arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otgfshost.c + * arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGFS) diff --git a/arch/arm/src/stm32/stm32_otghs.h b/arch/arm/src/common/stm32/stm32_otghs.h similarity index 95% rename from arch/arm/src/stm32/stm32_otghs.h rename to arch/arm/src/common/stm32/stm32_otghs.h index 68016e3793f..c6484304593 100644 --- a/arch/arm/src/stm32/stm32_otghs.h +++ b/arch/arm/src/common/stm32/stm32_otghs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghs.h + * arch/arm/src/common/stm32/stm32_otghs.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_OTGHS_H -#define __ARCH_ARM_SRC_STM32_STM32_OTGHS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_OTGHS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_OTGHS_H */ diff --git a/arch/arm/src/stm32/stm32_otghsdev.c b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghsdev.c rename to arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c index a4fae9cad4f..4a0e61a2132 100644 --- a/arch/arm/src/stm32/stm32_otghsdev.c +++ b/arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghsdev.c + * arch/arm/src/common/stm32/stm32_otghsdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_otghshost.c b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_otghshost.c rename to arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c index 4acc263c420..45faa0a4963 100644 --- a/arch/arm/src/stm32/stm32_otghshost.c +++ b/arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_otghshost.c + * arch/arm/src/common/stm32/stm32_otghshost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -56,7 +56,7 @@ #include "arm_internal.h" #include "stm32_gpio.h" -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #if defined(CONFIG_STM32_USBHOST) && defined(CONFIG_STM32_OTGHS) diff --git a/arch/arm/src/stm32/stm32_fdcan.h b/arch/arm/src/common/stm32/stm32_pm.h similarity index 58% rename from arch/arm/src/stm32/stm32_fdcan.h rename to arch/arm/src/common/stm32/stm32_pm.h index f157213828d..f9bdebd9f60 100644 --- a/arch/arm/src/stm32/stm32_fdcan.h +++ b/arch/arm/src/common/stm32/stm32_pm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_fdcan.h + * arch/arm/src/common/stm32/stm32_pm.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32_STM32_FDCAN_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H /**************************************************************************** * Included Files @@ -29,33 +29,25 @@ #include -#include "chip.h" -#include "hardware/stm32_fdcan.h" +#include -#include +#include "chip.h" +#include "arm_internal.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 -#define FDCAN2 2 -#define FDCAN3 3 - /**************************************************************************** * Public Types ****************************************************************************/ -#ifndef __ASSEMBLY__ - /**************************************************************************** * Public Data ****************************************************************************/ -#undef EXTERN -#if defined(__cplusplus) +#ifndef __ASSEMBLY__ +#ifdef __cplusplus #define EXTERN extern "C" extern "C" { @@ -67,48 +59,69 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - /**************************************************************************** - * Name: stm32_fdcaninitialize + * Name: stm32_pmstop * * Description: - * Initialize the selected FDCAN port + * Enter STOP mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * lpds - true: To further reduce power consumption in Stop mode, put the + * internal voltage regulator in low-power mode using the LPDS bit + * of the Power control register (PWR_CR). * * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure + * Zero means that the STOP was successfully entered and the system has + * been re-awakened. The internal voltage regulator is back to its + * original state. Otherwise, STOP mode did not occur and a negated + * errno value is returned to indicate the cause of the failure. * ****************************************************************************/ -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET +int stm32_pmstop(bool lpds); /**************************************************************************** - * Name: stm32_fdcansockinitialize + * Name: stm32_pmstandby * * Description: - * Initialize the selected FDCAN port as SocketCAN interface + * Enter STANDBY mode. * * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) + * None * * Returned Value: - * OK on success; Negated errno on failure. + * On success, this function will not return (STANDBY mode can only be + * terminated with a reset event). Otherwise, STANDBY mode did not occur + * and a negated errno value is returned to indicate the cause of the + * failure. * ****************************************************************************/ -int stm32_fdcansockinitialize(int port); -#endif +int stm32_pmstandby(void); + +/**************************************************************************** + * Name: stm32_pmsleep + * + * Description: + * Enter SLEEP mode. + * + * Input Parameters: + * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is + * executed, the MCU enters Sleep mode as soon as it + * exits the lowest priority ISR. + * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep + * mode as soon as WFI or WFE instruction is executed. + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_pmsleep(bool sleeponexit); #undef EXTERN -#if defined(__cplusplus) +#ifdef __cplusplus } #endif - #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FDCAN_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_pminitialize.c b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_pminitialize.c rename to arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c index 2f9883b2123..6120feeb7c4 100644 --- a/arch/arm/src/stm32/stm32_pminitialize.c +++ b/arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pminitialize.c + * arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmsleep.c b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmsleep.c rename to arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c index 5f78cc86268..24113447340 100644 --- a/arch/arm/src/stm32/stm32_pmsleep.c +++ b/arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmsleep.c + * arch/arm/src/common/stm32/stm32_pmsleep_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstandby.c b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstandby.c rename to arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c index d8b9825aed5..71195ed4bc5 100644 --- a/arch/arm/src/stm32/stm32_pmstandby.c +++ b/arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstandby.c + * arch/arm/src/common/stm32/stm32_pmstandby_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pmstop.c b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_pmstop.c rename to arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c index 9acf05990f9..82ce0a60bc0 100644 --- a/arch/arm/src/stm32/stm32_pmstop.c +++ b/arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pmstop.c + * arch/arm/src/common/stm32/stm32_pmstop_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.h b/arch/arm/src/common/stm32/stm32_pulsecount.h similarity index 87% rename from arch/arm/src/stm32/stm32_pulsecount.h rename to arch/arm/src/common/stm32/stm32_pulsecount.h index 20ccf3608fe..ec76dfe48e4 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.h +++ b/arch/arm/src/common/stm32/stm32_pulsecount.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.h + * arch/arm/src/common/stm32/stm32_pulsecount.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H /**************************************************************************** * Included Files @@ -36,4 +36,4 @@ struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); -#endif /* __ARCH_ARM_SRC_STM32_STM32_PULSECOUNT_H */ +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c index e644f31003f..e64d5be88fe 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pulsecount.c b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pulsecount.c rename to arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c index c8aea22c4e1..d73a83d0022 100644 --- a/arch/arm/src/stm32/stm32_pulsecount.c +++ b/arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pulsecount.c + * arch/arm/src/common/stm32/stm32_pulsecount_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm.h new file mode 100644 index 00000000000..c2a9a907897 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_pwm.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_pwm.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_pwm_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_pwm_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 PWM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_PWM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.c index 0710973de1b..cf7e6a3b238 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m0_v1.h index fc5beb4482c..eafff64985f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H /* The STM32F0L0G0 does not have dedicated PWM hardware. Rather, pulsed * output control is a capability of the STM32F0L0G0 timers. The logic in @@ -560,4 +560,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* CONFIG_STM32_TIMx_PWM */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.c rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c index 4b7d1378d82..17fff3b6e3e 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.c + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwm.h b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h similarity index 99% rename from arch/arm/src/stm32/stm32_pwm.h rename to arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h index f2f7191bcf0..032a0410d40 100644 --- a/arch/arm/src/stm32/stm32_pwm.h +++ b/arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwm.h + * arch/arm/src/common/stm32/stm32_pwm_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWM_H -#define __ARCH_ARM_SRC_STM32_STM32_PWM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H /* The STM32 does not have dedicated PWM hardware. Rather, pulsed output * control is a capability of the STM32 timers. The logic in this file @@ -1175,4 +1175,4 @@ struct pwm_lowerhalf_s *stm32_pwminitialize(int timer); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_PWM */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_pwr.h similarity index 94% rename from arch/arm/src/stm32/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_pwr.h index 141f81a3609..f7d0ec2b909 100644 --- a/arch/arm/src/stm32/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H /**************************************************************************** * Included Files @@ -30,29 +30,17 @@ #include #include +#include #include "chip.h" #include "hardware/stm32_pwr.h" /**************************************************************************** - * Pre-processor Definitions + * Public Types ****************************************************************************/ #ifndef __ASSEMBLY__ -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - /* Identify MCU-specific wakeup pin. * Different STM32 parts support differing numbers of wakeup pins. */ @@ -68,6 +56,15 @@ enum stm32_pwr_wupin_e * Public Function Prototypes ****************************************************************************/ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + /**************************************************************************** * Name: stm32_pwr_enablesdadc * @@ -112,7 +109,7 @@ void stm32_pwr_initbkp(bool writable); * * Description: * Enables access to the backup domain - * (RTC registers, RTC backup data registers and backup SRAM). + * (RTC registers, RTC backup data registers and backup SRAM). * * NOTE: * Reference counting is used in order to supported nested calls to this @@ -214,8 +211,9 @@ void stm32_pwr_enablebreg(bool region); * ****************************************************************************/ -#ifdef CONFIG_STM32_ENERGYLITE +#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) void stm32_pwr_setvos(uint16_t vos); +#endif /**************************************************************************** * Name: stm32_pwr_setpvd @@ -234,6 +232,7 @@ void stm32_pwr_setvos(uint16_t vos); * ****************************************************************************/ +#ifdef CONFIG_STM32_ENERGYLITE void stm32_pwr_setpvd(uint16_t pls); /**************************************************************************** @@ -264,4 +263,5 @@ void stm32_pwr_disablepvd(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32g0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_g0.c index 0e8b03e12ef..d1627f7fa5f 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_g0.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_g0.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m0_v1.c index 6516b14f98c..5ff40ed9e66 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0l0_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_pwr.c b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_pwr.c rename to arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c index b55c301cd36..0d2bed7a90f 100644 --- a/arch/arm/src/stm32/stm32_pwr.c +++ b/arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_pwr.c + * arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.h b/arch/arm/src/common/stm32/stm32_qencoder.h similarity index 84% rename from arch/arm/src/stm32/stm32_qencoder.h rename to arch/arm/src/common/stm32/stm32_qencoder.h index a8c9ff66e00..e82881b3032 100644 --- a/arch/arm/src/stm32/stm32_qencoder.h +++ b/arch/arm/src/common/stm32/stm32_qencoder.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.h + * arch/arm/src/common/stm32/stm32_qencoder.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32_STM32_QENCODER_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H /**************************************************************************** * Included Files @@ -34,13 +34,13 @@ #ifdef CONFIG_SENSORS_QENCODER /**************************************************************************** - * Included Files + * Pre-processor Definitions ****************************************************************************/ /* Timer devices may be used for different purposes. One special purpose is * as a quadrature encoder input device. If CONFIG_STM32_TIMn is defined - * then the CONFIG_STM32_TIMn_QE must also be defined to indicate that timer - * "n" is intended to be used for as a quadrature encoder. + * then CONFIG_STM32_TIMn_QE indicates that timer "n" is intended to be used + * as a quadrature encoder. */ #ifndef CONFIG_STM32_TIM1 @@ -62,9 +62,7 @@ # undef CONFIG_STM32_TIM8_QE #endif -/* Only timers 2-5, and 1 & 8 can be used as a quadrature encoder (at least - * for the STM32 F4) - */ +/* Basic and small general-purpose timers do not support encoder mode. */ #undef CONFIG_STM32_TIM6_QE #undef CONFIG_STM32_TIM7_QE @@ -74,9 +72,12 @@ #undef CONFIG_STM32_TIM12_QE #undef CONFIG_STM32_TIM13_QE #undef CONFIG_STM32_TIM14_QE +#undef CONFIG_STM32_TIM15_QE +#undef CONFIG_STM32_TIM16_QE +#undef CONFIG_STM32_TIM17_QE /**************************************************************************** - * Included Files + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** @@ -84,12 +85,11 @@ * * Description: * Initialize a quadrature encoder interface. This function must be called - * from board-specific logic.. + * from board-specific logic. * * Input Parameters: * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. 'tim' must be an element of - * {1,2,3,4,5,8} + * tim - The timer number to use. * * Returned Value: * Zero on success; A negated errno value is returned on failure. @@ -118,4 +118,5 @@ int stm32_qe_index_init(int tim, uint32_t gpio); #endif #endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_QENCODER_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c index 65cc9945546..e88ff33418d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_qencoder.c rename to arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c index 1c0a9921b4e..f5c4bea0d22 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_qencoder.c + * arch/arm/src/common/stm32/stm32_qencoder_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.h b/arch/arm/src/common/stm32/stm32_rcc.h similarity index 51% rename from arch/arm/src/stm32f0l0g0/stm32_pwr.h rename to arch/arm/src/common/stm32/stm32_rcc.h index 1562b607328..c2c57a6a0b6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.h +++ b/arch/arm/src/common/stm32/stm32_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.h + * arch/arm/src/common/stm32/stm32_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H /**************************************************************************** * Included Files @@ -29,12 +29,10 @@ #include -#include - +#include "arm_internal.h" #include "chip.h" -#include "hardware/stm32_pwr.h" -#ifdef CONFIG_STM32_PWR +#include "hardware/stm32_rcc.h" /**************************************************************************** * Pre-processor Definitions @@ -52,177 +50,178 @@ extern "C" #endif /**************************************************************************** - * Public Types + * Inline Functions ****************************************************************************/ -/* Identify MCU-specific wakeup pin. Different STM32 parts support differing - * numbers of wakeup pins. - */ +/**************************************************************************** + * Name: stm32_mco1config + * + * Description: + * Selects the clock source to output on MCO1 pin (PA8). PA8 should be + * configured in alternate function mode. + * + ****************************************************************************/ -enum stm32_pwr_wupin_e +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco1config(uint32_t source, uint32_t div) { - PWR_WUPIN_1 = 0, /* Wake-up pin 1 (all parts) */ - PWR_WUPIN_2, /* Wake-up pin 2 */ - PWR_WUPIN_3 /* Wake-up pin 3 */ -}; + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif /**************************************************************************** - * Public Functions Prototypes + * Name: stm32_mcoconfig + * + * Description: + * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. + * PA8 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_CONNECTIVITYLINE) +static inline void stm32_mcoconfig(uint32_t source) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO_MASK); + regval |= (source & RCC_CFGR_MCO_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mcodivconfig + * + * Description: + * Selects the clock source to output and clock divider on MC pin (PA4) for + * stm32l1xxx. PA4 should be configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCOSEL_MASK); + regval |= (source & RCC_CFGR_MCOSEL_MASK); + regval &= ~(RCC_CFGR_MCOPRE_MASK); + regval |= (divider & RCC_CFGR_MCOPRE_MASK); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Name: stm32_mco2config + * + * Description: + * Selects the clock source to output on MCO2 pin (PC9). PC9 should be + * configured in alternate function mode. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +static inline void stm32_mco2config(uint32_t source, uint32_t div) +{ + uint32_t regval; + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); + regval |= (source | div); + putreg32(regval, STM32_RCC_CFGR); +} +#endif + +/**************************************************************************** + * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: stm32_pwr_initbkp + * Name: stm32_clockconfig * * Description: - * Insures the referenced count access to the backup domain (RTC registers, - * RTC backup data registers and backup SRAM is consistent with the HW - * state without relying on a variable. + * Called to initialize the STM32F0XX. + * This does whatever setup is needed to put the MCU in a usable state. + * This includes the initialization of clocking using the settings + * in board.h. * - * NOTE: This function should only be called by SoC Start up code. + ****************************************************************************/ + +void stm32_clockconfig(void); + +/**************************************************************************** + * Name: stm32_board_clockconfig + * + * Description: + * Any STM32 board may replace the standard board clock configuration logic + * with its own custom clock configuration logic. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG +void stm32_board_clockconfig(void); +#endif + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings after low-power + * modes. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void); +#endif + +/**************************************************************************** + * Name: stm32_rcc_enablelse + * + * Description: + * Enable the External Low-Speed (LSE) Oscillator. * * Input Parameters: - * writable - set the initial state of the enable and the - * bkp_writable_counter + * None * * Returned Value: * None * ****************************************************************************/ -void stm32_pwr_initbkp(bool writable); +void stm32_rcc_enablelse(void); /**************************************************************************** - * Name: stm32_pwr_enablebkp + * Name: stm32_rcc_enablelsi * * Description: - * Enables access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). - * - * NOTE: - * Reference counting is used in order to supported nested calls to this - * function. As a consequence, every call to stm32_pwr_enablebkp(true) - * must be followed by a matching call to stm32_pwr_enablebkp(false). - * - * Input Parameters: - * writable - True: enable ability to write to backup domain registers - * - * Returned Value: - * None + * Enable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -void stm32_pwr_enablebkp(bool writable); +void stm32_rcc_enablelsi(void); /**************************************************************************** - * Name: stm32_pwr_enablewkup + * Name: stm32_rcc_disablelsi * * Description: - * Enables the WKUP pin. - * - * Input Parameters: - * wupin - Selects the WKUP pin to enable/disable - * wupon - state to set it to - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. The only cause of failure is if the selected MCU does not - * support the requested wakeup pin. + * Disable the Internal Low-Speed (LSI) RC Oscillator. * ****************************************************************************/ -int stm32_pwr_enablewkup(enum stm32_pwr_wupin_e wupin, bool wupon); - -/**************************************************************************** - * Name: stm32_pwr_getsbf - * - * Description: - * Return the standby flag. - * - ****************************************************************************/ - -bool stm32_pwr_getsbf(void); - -/**************************************************************************** - * Name: stm32_pwr_getwuf - * - * Description: - * Return the wakeup flag. - * - ****************************************************************************/ - -bool stm32_pwr_getwuf(void); - -/**************************************************************************** - * Name: stm32_pwr_setvos - * - * Description: - * Set voltage scaling for EnergyLite devices. - * - * Input Parameters: - * vos - Properly aligned voltage scaling select bits for the PWR_CR - * register. - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. If - * used for any other purpose that protection to assure that its operation - * is atomic will be required. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) || defined(CONFIG_STM32_STM32G0) -void stm32_pwr_setvos(uint16_t vos); -#endif /* CONFIG_STM32_ENERGYLITE || CONFIG_STM32_STM32G0 */ - -/**************************************************************************** - * Name: stm32_pwr_setpvd - * - * Description: - * Sets power voltage detector for EnergyLite devices. - * - * Input Parameters: - * pls - PVD level - * - * Returned Value: - * None - * - * Assumptions: - * At present, this function is called only from initialization logic. - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) -void stm32_pwr_setpvd(uint16_t pls); - -/**************************************************************************** - * Name: stm32_pwr_enablepvd - * - * Description: - * Enable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_enablepvd(void); - -/**************************************************************************** - * Name: stm32_pwr_disablepvd - * - * Description: - * Disable the Programmable Voltage Detector - * - ****************************************************************************/ - -void stm32_pwr_disablepvd(void); - -#endif /* CONFIG_STM32_ENERGYLITE */ +void stm32_rcc_disablelsi(void); #undef EXTERN #if defined(__cplusplus) } #endif - #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_STM32_PWR */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PWR_H */ + +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m0_v1.c index 9a4c46aaa0b..837ed6ce85e 100644 --- a/arch/arm/src/stm32/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_rng.c b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c similarity index 96% rename from arch/arm/src/stm32f0l0g0/stm32_rng.c rename to arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c index 2ccebb1060b..a40caf80bd5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rng.c +++ b/arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rng.c + * arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -158,7 +158,7 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) rngsr = getreg32(STM32_RNG_SR); if ((rngsr & (RNG_SR_SEIS | RNG_SR_CEIS)) /* Check for error bits */ - || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ + || !(rngsr & RNG_SR_DRDY)) /* Data ready must be set */ { /* This random value is not valid, we will try again. */ @@ -172,8 +172,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * RNGEN bit should not be used, but saved for comparison with the next * generated random number. Each subsequent generated random number has to * be compared with the previously generated number. The test fails if any - * two compared numbers are equal - * (continuous random number generator test). + * two compared numbers are equal (continuous random number generator + * test). */ if (g_rngdev.rd_first) @@ -223,8 +223,8 @@ static int stm32_rng_interrupt(int irq, void *context, void *arg) * Name: stm32_rng_read ****************************************************************************/ -static ssize_t stm32_rng_read(struct file *filep, - char *buffer, size_t buflen) +static ssize_t stm32_rng_read(struct file *filep, char *buffer, + size_t buflen) { int ret; @@ -234,7 +234,7 @@ static ssize_t stm32_rng_read(struct file *filep, return ret; } - /* We've got the semaphore. */ + /* We've got the mutex. */ /* Reset the operation semaphore with 0 for blocking until the * buffer is filled from interrupts. diff --git a/arch/arm/src/stm32/stm32_rtc.h b/arch/arm/src/common/stm32/stm32_rtc.h similarity index 96% rename from arch/arm/src/stm32/stm32_rtc.h rename to arch/arm/src/common/stm32/stm32_rtc.h index 3df1ac02a7b..96c8e4f5b8b 100644 --- a/arch/arm/src/stm32/stm32_rtc.h +++ b/arch/arm/src/common/stm32/stm32_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.h + * arch/arm/src/common/stm32/stm32_rtc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,11 +24,13 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_RTC_H -#define __ARCH_ARM_SRC_STM32_STM32_RTC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H #include +#ifdef CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 + #include "chip.h" /* The STM32 F1 has a simple battery-backed counter for its RTC and has a @@ -222,4 +224,6 @@ struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); } #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RTC_H */ + +#endif /* CONFIG_STM32_HAVE_IP_RTC_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_RTC_H */ diff --git a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtc_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c index 69c59d6f887..e8c1c75fc9d 100644 --- a/arch/arm/src/stm32/stm32_rtc_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtc_lowerhalf.c + * arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c index 6917d43fd34..9dff0b4bcca 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c index 3a37110089d..06d729c437b 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcc.c b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcc.c rename to arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c index cd0e55db467..fac37d3b563 100644 --- a/arch/arm/src/stm32/stm32_rtcc.c +++ b/arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcc.c + * arch/arm/src/common/stm32/stm32_rtcc_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_rtcounter.c b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_rtcounter.c rename to arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c index a93fcb4f890..6f5259e4498 100644 --- a/arch/arm/src/stm32/stm32_rtcounter.c +++ b/arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rtcounter.c + * arch/arm/src/common/stm32/stm32_rtcounter_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc.h new file mode 100644 index 00000000000..f69f80d1d56 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdadc.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdadc.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDADC_M3M4_V1) +# include "stm32_sdadc_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdadc" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDADC_H */ diff --git a/arch/arm/src/stm32/stm32_sdadc.c b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdadc.c rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c index 783dd03c6cc..23e5fc8a33f 100644 --- a/arch/arm/src/stm32/stm32_sdadc.c +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.c + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015-2017 Gregory Nutt. All rights reserved. @@ -64,8 +64,10 @@ #include "chip.h" #include "stm32.h" #include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #include "stm32_pwr.h" -#include "stm32_sdadc.h" +#include "stm32_dma.h" +#include "stm32_sdadc_m3m4_v1.h" #ifdef CONFIG_STM32_SDADC diff --git a/arch/arm/src/stm32/stm32_sdadc.h b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_sdadc.h rename to arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h index 75d474efa56..6906d43f07c 100644 --- a/arch/arm/src/stm32/stm32_sdadc.h +++ b/arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdadc.h + * arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Gregory Nutt. All rights reserved. @@ -37,8 +37,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDADC_H -#define __ARCH_ARM_SRC_STM32_STM32_SDADC_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H /**************************************************************************** * Included Files @@ -428,4 +428,4 @@ struct adc_dev_s *stm32_sdadcinitialize(int intf, #endif /* CONFIG_STM32_SDADC1 || CONFIG_STM32_SDADC2 || * CONFIG_STM32_SDADC3 */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDADC_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDADC_H */ diff --git a/arch/arm/src/common/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio.h new file mode 100644 index 00000000000..8dc71bb2709 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_sdio.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_sdio.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1) +# include "stm32_sdio_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_sdio" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32SDIO_H */ diff --git a/arch/arm/src/stm32/stm32_sdio.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_sdio.c rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c index 5d6e5cfc441..3387e111c4e 100644 --- a/arch/arm/src/stm32/stm32_sdio.c +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.c + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -49,7 +49,9 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_dma.h" -#include "stm32_sdio.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_dma.h" +#include "stm32_sdio_m3m4_v1.h" #ifdef CONFIG_STM32_SDIO @@ -107,7 +109,7 @@ # ifndef CONFIG_STM32_SDIO_DMAPRIO # if defined(CONFIG_STM32_STM32F10XX) # define CONFIG_STM32_SDIO_DMAPRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define CONFIG_STM32_SDIO_DMAPRIO DMA_SCR_PRIVERYHI # else # error "Unknown STM32 DMA" @@ -117,7 +119,7 @@ # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (CONFIG_STM32_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_STM32_SDIO_DMAPRIO" # endif @@ -199,7 +201,7 @@ /* STM32 F4 stream configuration register (SCR) settings. */ -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ CONFIG_STM32_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ @@ -219,7 +221,7 @@ #if defined(CONFIG_STM32_STM32F10XX) # define SDIO_DMACHAN DMACHAN_SDIO -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SDIO_DMACHAN DMAMAP_SDIO #else # error "Unknown STM32 DMA" diff --git a/arch/arm/src/stm32/stm32_sdio.h b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h similarity index 93% rename from arch/arm/src/stm32/stm32_sdio.h rename to arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h index d74b3fe3989..8ffd42b7eec 100644 --- a/arch/arm/src/stm32/stm32_sdio.h +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_sdio.h + * arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,17 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SDIO_H -#define __ARCH_ARM_SRC_STM32_STM32_SDIO_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H /**************************************************************************** * Included Files ****************************************************************************/ #include + +#ifdef CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 + #include #include @@ -133,4 +136,6 @@ void sdio_set_sdio_card_isr(struct sdio_dev_s *dev, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SDIO_H */ + +#endif /* CONFIG_STM32_HAVE_IP_SDIO_M3M4_V1 */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SDIO_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v1.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v3.c index 444e4888721..504e31b9c49 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v1.c + * arch/arm/src/common/stm32/stm32_serial_m0_v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_serial_v2.c rename to arch/arm/src/common/stm32/stm32_serial_m0_v4.c index 0d9d208c67f..feb3307bc6d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/common/stm32/stm32_serial_m0_v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_serial_v2.c + * arch/arm/src/common/stm32/stm32_serial_m0_v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_serial.c rename to arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c index 09cbe58c2fc..c5b3f861d10 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_serial.c + * arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.h b/arch/arm/src/common/stm32/stm32_spi.h similarity index 94% rename from arch/arm/src/stm32/stm32_spi.h rename to arch/arm/src/common/stm32/stm32_spi.h index 13a48fb92ce..9e861bcc690 100644 --- a/arch/arm/src/stm32/stm32_spi.h +++ b/arch/arm/src/common/stm32/stm32_spi.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.h + * arch/arm/src/common/stm32/stm32_spi.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32_STM32_SPI_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H /**************************************************************************** * Included Files @@ -29,6 +29,13 @@ #include +#if !(defined(CONFIG_STM32_HAVE_IP_SPI_V1) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V2) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V3) || \ + defined(CONFIG_STM32_HAVE_IP_SPI_V4)) +# error "Unsupported STM32 SPI" +#endif + #include #include "chip.h" @@ -206,4 +213,4 @@ int stm32_spi6register(struct spi_dev_s *dev, spi_mediachange_t callback, #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SPI_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SPI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m0_v1.c index ae149747b08..9b32cd490f5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_spi.c b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c similarity index 99% rename from arch/arm/src/stm32/stm32_spi.c rename to arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c index 62b019ce07e..567f79a95fe 100644 --- a/arch/arm/src/stm32/stm32_spi.c +++ b/arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_spi.c + * arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c * * SPDX-License-Identifier: Apache-2.0 * @@ -103,7 +103,7 @@ # elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32L15XX) || \ defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32G4XXX) # define SPI_DMA_PRIO DMA_CCR_PRIMED -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_DMA_PRIO DMA_SCR_PRIMED # else # error "Unknown STM32 DMA" @@ -114,7 +114,7 @@ # if (SPI_DMA_PRIO & ~DMA_CCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif -# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +# elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 # error "Illegal value for CONFIG_SPI_DMAPRIO" # endif @@ -135,7 +135,7 @@ # define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_MINC|DMA_CCR_DIR) # define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_16BITS |DMA_CCR_DIR) # define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_CCR_MSIZE_8BITS |DMA_CCR_PSIZE_8BITS |DMA_CCR_DIR) -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) +#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) # define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) # define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.h b/arch/arm/src/common/stm32/stm32_start.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/stm32_start.h rename to arch/arm/src/common/stm32/stm32_start.h index 34691d3ac80..ad9bbda5e31 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.h +++ b/arch/arm/src/common/stm32/stm32_start.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.h + * arch/arm/src/common/stm32/stm32_start.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H /**************************************************************************** * Included Files @@ -61,4 +61,4 @@ void stm32_boardinitialize(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_START_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_START_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m0_v1.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m0_v1.c index 9b1449d4fb7..b2585f49bc6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_start.c rename to arch/arm/src/common/stm32/stm32_start_m3m4_v1.c index e4abdb7d3e9..ad74f104e3c 100644 --- a/arch/arm/src/stm32/stm32_start.c +++ b/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_start.c + * arch/arm/src/common/stm32/stm32_start_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_syscfg.h b/arch/arm/src/common/stm32/stm32_syscfg.h similarity index 90% rename from arch/arm/src/stm32/stm32_syscfg.h rename to arch/arm/src/common/stm32/stm32_syscfg.h index 74d049711a6..1e95d770342 100644 --- a/arch/arm/src/stm32/stm32_syscfg.h +++ b/arch/arm/src/common/stm32/stm32_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_syscfg.h + * arch/arm/src/common/stm32/stm32_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H -#define __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32_STM32_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_SYSCFG_H */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_tickless.c rename to arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c index 3cd076bf1d7..1e49c2a3cb3 100644 --- a/arch/arm/src/stm32/stm32_tickless.c +++ b/arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tickless.c + * arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016-2017 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/common/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim.h new file mode 100644 index 00000000000..77d884e0672 --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_tim.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_tim.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_TIMERS_M0_V1) +# include "stm32_tim_m0_v1.h" +#elif defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2) || \ + defined(CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3) +# include "stm32_tim_m3m4_v1v2v3.h" +#else +# error "Unsupported STM32 TIM" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_TIM_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.c index 48a549aa415..9401a884a27 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m0_v1.h index ba9d7c7fbc4..07c0ef1f7e5 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m0_v1.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. @@ -34,8 +34,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H /**************************************************************************** * Included Files @@ -230,4 +230,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V3_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c index dbb558fa81b..356a3e9e6c7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c index 71774e2898b..65a9a062d05 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h similarity index 96% rename from arch/arm/src/stm32/stm32_tim.h rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h index 6e01e6693d7..9bd99fb862f 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim.h + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H -#define __ARCH_ARM_SRC_STM32_STM32_TIM_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H /**************************************************************************** * Included Files @@ -222,4 +222,4 @@ int stm32_timer_initialize(const char *devpath, int timer); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_TIM_V1V2V3_H */ diff --git a/arch/arm/src/stm32/stm32_tim_lowerhalf.c b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c similarity index 99% rename from arch/arm/src/stm32/stm32_tim_lowerhalf.c rename to arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c index 14407bdc4f7..25d5b631926 100644 --- a/arch/arm/src/stm32/stm32_tim_lowerhalf.c +++ b/arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_tim_lowerhalf.c + * arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Wail Khemir. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv6m.c index 9a92038c401..a3136b86579 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv6m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv6m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c similarity index 99% rename from arch/arm/src/stm32/stm32_timerisr.c rename to arch/arm/src/common/stm32/stm32_timerisr_armv7m.c index c4fa9c76fb6..b7f8e713252 100644 --- a/arch/arm/src/stm32/stm32_timerisr.c +++ b/arch/arm/src/common/stm32/stm32_timerisr_armv7m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_timerisr.c + * arch/arm/src/common/stm32/stm32_timerisr_armv7m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart.h new file mode 100644 index 00000000000..29de62701fe --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_uart.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_uart.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ARMV6M) +# if defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m0_v1.h" +# else +# error "Unsupported STM32 UART core for M0" +# endif +#elif defined(CONFIG_STM32_HAVE_IP_USART_V1) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V2) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V3) || \ + defined(CONFIG_STM32_HAVE_IP_USART_V4) +# include "stm32_uart_m3m4_v1v2.h" +#else +# error "Unsupported STM32 UART" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UART_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m0_v1.h index 9ebcefc8fc5..5844f46e084 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m0_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m0_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H /**************************************************************************** * Included Files @@ -449,4 +449,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_M0_H */ diff --git a/arch/arm/src/stm32/stm32_uart.h b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h similarity index 96% rename from arch/arm/src/stm32/stm32_uart.h rename to arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h index 3723edd4c1e..c4e20a1a781 100644 --- a/arch/arm/src/stm32/stm32_uart.h +++ b/arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uart.h + * arch/arm/src/common/stm32/stm32_uart_m3m4_v1v2.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_STC_STM32_STM32_UART_H -#define __ARCH_ARM_STC_STM32_STM32_UART_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H /**************************************************************************** * Included Files @@ -31,23 +31,7 @@ #include #include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \ - defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f30xxx_uart.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_uart.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_uart.h" -#else -# error "Unsupported STM32 UART" -#endif +#include "hardware/stm32_uart.h" /**************************************************************************** * Pre-processor Definitions @@ -665,4 +649,4 @@ void stm32_serial_dma_poll(void); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_UART_V1V2_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.h b/arch/arm/src/common/stm32/stm32_uid.h similarity index 79% rename from arch/arm/src/stm32f0l0g0/stm32_uid.h rename to arch/arm/src/common/stm32/stm32_uid.h index 34661df85de..e925374353e 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.h +++ b/arch/arm/src/common/stm32/stm32_uid.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.h + * arch/arm/src/common/stm32/stm32_uid.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,19 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H /**************************************************************************** * Included Files ****************************************************************************/ +#include + #include /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#if defined(CONFIG_STM32_HAVE_IP_UID_M0_V1) void stm32_get_uniqueid(uint32_t *uid); +#elif defined(CONFIG_STM32_HAVE_IP_UID_M3M4_V1) +void stm32_get_uniqueid(uint8_t uniqueid[12]); +#endif -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_UID_H */ \ No newline at end of file +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32_UID_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m0_v1.c index a57b048b8a7..9f9be6610a7 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_uid.c b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c similarity index 98% rename from arch/arm/src/stm32/stm32_uid.c rename to arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c index fa274e1d62a..9986db93d7c 100644 --- a/arch/arm/src/stm32/stm32_uid.c +++ b/arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_uid.c + * arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h b/arch/arm/src/common/stm32/stm32_usbdev.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.h rename to arch/arm/src/common/stm32/stm32_usbdev.h index afa99490451..1d1a989b0d0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.h +++ b/arch/arm/src/common/stm32/stm32_usbdev.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.h + * arch/arm/src/common/stm32/stm32_usbdev.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H /**************************************************************************** * Included Files @@ -34,6 +34,16 @@ #include "chip.h" #include "hardware/stm32_usbdev.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of endpoints */ + +#ifndef STM32_NENDPOINTS +# define STM32_NENDPOINTS (8) +#endif + /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ @@ -81,4 +91,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_USBDEV_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c index d98ef7274af..59632743a29 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_usbdev.c b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbdev.c rename to arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c index 09e73931312..f84789892b1 100644 --- a/arch/arm/src/stm32/stm32_usbdev.c +++ b/arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.c + * arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs.h new file mode 100644 index 00000000000..443a87bacfe --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbfs.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbfs.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_HAVE_IP_USBFS_M3M4_V1) +# include "stm32_usbfs_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbfs" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBFS_H */ diff --git a/arch/arm/src/stm32/stm32_usbfs.c b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbfs.c rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c index cb6cf7f4745..418dcf33211 100644 --- a/arch/arm/src/stm32/stm32_usbfs.c +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.c + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -47,8 +47,10 @@ #include "arm_internal.h" #include "stm32.h" #include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #include "stm32_gpio.h" -#include "stm32_usbfs.h" +#include "stm32_syscfg.h" +#include "stm32_usbfs_m3m4_v1.h" #if defined(CONFIG_STM32_USBFS) diff --git a/arch/arm/src/stm32/stm32_usbfs.h b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h similarity index 92% rename from arch/arm/src/stm32/stm32_usbfs.h rename to arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h index b9c7ed0405b..8a5b8adf762 100644 --- a/arch/arm/src/stm32/stm32_usbfs.h +++ b/arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbfs.h + * arch/arm/src/common/stm32/stm32_usbfs_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBFS_H -#define __ARCH_ARM_SRC_STM32_STM32_USBFS_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H /**************************************************************************** * Included Files @@ -76,4 +76,4 @@ void stm32_usbsuspend(struct usbdev_s *dev, bool resume); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBFS_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBFS_H */ diff --git a/arch/arm/src/common/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost.h new file mode 100644 index 00000000000..c659a23a25b --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_usbhost.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_usbhost.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H +#define __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_COMMON_LEGACY) +# include "stm32_usbhost_m3m4_v1.h" +#else +# error "Unsupported STM32 stm32_usbhost" +#endif + +#endif /* __ARCH_ARM_SRC_COMMON_COMPAT_STM32USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_usbhost.c b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_usbhost.c rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c index 1314be9c5e4..d6241c81881 100644 --- a/arch/arm/src/stm32/stm32_usbhost.c +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.c + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include -#include "stm32_usbhost.h" +#include "stm32_usbhost_m3m4_v1.h" #ifdef HAVE_USBHOST_TRACE diff --git a/arch/arm/src/stm32/stm32_usbhost.h b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h similarity index 98% rename from arch/arm/src/stm32/stm32_usbhost.h rename to arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h index b71a9e46a7c..867260f81c8 100644 --- a/arch/arm/src/stm32/stm32_usbhost.h +++ b/arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_usbhost.h + * arch/arm/src/common/stm32/stm32_usbhost_m3m4_v1.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBHOST_H -#define __ARCH_ARM_SRC_STM32_STM32_USBHOST_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H /**************************************************************************** * Included Files @@ -280,4 +280,4 @@ void stm32_usbhost_vbusdrive(int iface, bool enable); #endif /* __ASSEMBLY__ */ #endif /* CONFIG_STM32_OTGFS && CONFIG_STM32_USBHOST */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBHOST_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USBHOST_H */ diff --git a/arch/arm/src/stm32/stm32_comp.h b/arch/arm/src/common/stm32/stm32_userspace.h similarity index 66% rename from arch/arm/src/stm32/stm32_comp.h rename to arch/arm/src/common/stm32/stm32_userspace.h index 02e74e84972..36da6f4a783 100644 --- a/arch/arm/src/stm32/stm32_comp.h +++ b/arch/arm/src/common/stm32/stm32_userspace.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_comp.h + * arch/arm/src/common/stm32/stm32_userspace.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H /**************************************************************************** * Included Files @@ -29,61 +29,35 @@ #include -#include "chip.h" - -#include "hardware/stm32_comp.h" - -#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) -# include "stm32_comp_v1.h" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) -# include "stm32_comp_v2.h" -#endif - /**************************************************************************** - * Pre-processor definitions + * Pre-processor Definitions ****************************************************************************/ /**************************************************************************** * Public Types ****************************************************************************/ +/**************************************************************************** + * Public Data + ****************************************************************************/ + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - /**************************************************************************** - * Name: stm32_compinitialize + * Name: stm32_userspace * * Description: - * Initialize the COMP. - * - * Input Parameters: - * intf - The COMP interface number. - * - * Returned Value: - * Valid COMP device structure reference on success; a NULL on failure. - * - * Assumptions: - * 1. Clock to the COMP block has enabled, - * 2. Board-specific logic has already configured + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. * ****************************************************************************/ -struct comp_dev_s *stm32_compinitialize(int intf); - -#undef EXTERN -#ifdef __cplusplus -} +#ifdef CONFIG_BUILD_PROTECTED +void stm32_userspace(void); #endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.c b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c similarity index 98% rename from arch/arm/src/stm32/stm32_userspace.c rename to arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c index 92897821b35..31f567ecd02 100644 --- a/arch/arm/src/stm32/stm32_userspace.c +++ b/arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.c + * arch/arm/src/common/stm32/stm32_userspace_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/common/stm32/stm32_waste.h b/arch/arm/src/common/stm32/stm32_waste.h new file mode 100644 index 00000000000..702c166346a --- /dev/null +++ b/arch/arm/src/common/stm32/stm32_waste.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/common/stm32/stm32_waste.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +void stm32_waste(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WASTE_H */ diff --git a/arch/arm/src/stm32/stm32_waste.c b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c similarity index 97% rename from arch/arm/src/stm32/stm32_waste.c rename to arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c index ce40916f4f9..b689d1d91b0 100644 --- a/arch/arm/src/stm32/stm32_waste.c +++ b/arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_waste.c + * arch/arm/src/common/stm32/stm32_waste_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wdg.h b/arch/arm/src/common/stm32/stm32_wdg.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_wdg.h rename to arch/arm/src/common/stm32/stm32_wdg.h index 96ce766df55..c70b669ad87 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wdg.h +++ b/arch/arm/src/common/stm32/stm32_wdg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wdg.h + * arch/arm/src/common/stm32/stm32_wdg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H +#ifndef __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H +#define __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H /**************************************************************************** * Included Files @@ -101,4 +101,4 @@ void stm32_wwdginitialize(const char *devpath); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_WDG_H */ +#endif /* __ARCH_ARM_SRC_COMMON_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c similarity index 99% rename from arch/arm/src/stm32/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c index 26decaa9e5f..9ec66a9fa92 100644 --- a/arch/arm/src/stm32/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c similarity index 80% rename from arch/arm/src/stm32f0l0g0/stm32_wwdg.c rename to arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c index f8717ce0f2c..8d8ccdac2b0 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_wwdg.c +++ b/arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_wwdg.c + * arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -40,6 +40,8 @@ #include "hardware/stm32_dbgmcu.h" #include "stm32_wdg.h" +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_STM32_WWDG) + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -63,6 +65,16 @@ #define WWDG_FMIN (STM32_PCLK1_FREQUENCY / 4096 / 8) #define WWDG_MAXTIMEOUT (1000 * (WWDG_CR_T_MAX+1) / WWDG_FMIN) +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32_WWDG_DEFTIMOUT +# define CONFIG_STM32_WWDG_DEFTIMOUT WWDG_MAXTIMEOUT +#endif + +#ifndef CONFIG_DEBUG_WATCHDOG_INFO +# undef CONFIG_STM32_WWDG_REGDEBUG +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -89,25 +101,33 @@ struct stm32_lowerhalf_s /* Register operations ******************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window); +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint16_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window); /* Interrupt handling *******************************************************/ -static int stm32_interrupt(int irq, void *context, void *arg); +static int stm32_interrupt(int irq, void *context, void *arg); /* "Lower half" driver methods **********************************************/ -static int stm32_start(struct watchdog_lowerhalf_s *lower); -static int stm32_stop(struct watchdog_lowerhalf_s *lower); -static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); -static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); -static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg); +static int stm32_start(struct watchdog_lowerhalf_s *lower); +static int stm32_stop(struct watchdog_lowerhalf_s *lower); +static int stm32_keepalive(struct watchdog_lowerhalf_s *lower); +static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status); +static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout); +static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, + xcpt_t handler); +static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, + unsigned long arg); /**************************************************************************** * Private Data @@ -134,6 +154,90 @@ static struct stm32_lowerhalf_s g_wdgdev; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static uint16_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t count = 0; + static uint16_t preval = 0; + + /* Read the value from the register */ + + uint16_t val = getreg16(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + wdinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + wdinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + wdinfo("%08" PRIx32 "->%04x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_WWDG_REGDEBUG +static void stm32_putreg(uint16_t val, uint32_t addr) +{ + /* Show the register value being written */ + + wdinfo("%08" PRIx32 "<-%04x\n", addr, val); + + /* Write the value */ + + putreg16(val, addr); +} +#endif + /**************************************************************************** * Name: stm32_setwindow * @@ -145,16 +249,17 @@ static struct stm32_lowerhalf_s g_wdgdev; * ****************************************************************************/ -static void stm32_setwindow(struct stm32_lowerhalf_s *priv, uint8_t window) +static void stm32_setwindow(struct stm32_lowerhalf_s *priv, + uint8_t window) { uint16_t regval; /* Set W[6:0] bits according to selected window value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_W_MASK; regval |= window << WWDG_CFR_W_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Remember the window setting */ @@ -182,7 +287,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) /* Check if the EWI interrupt is really pending */ - regval = getreg32(STM32_WWDG_SR); + regval = stm32_getreg(STM32_WWDG_SR); if ((regval & WWDG_SR_EWIF) != 0) { /* Is there a registered handler? */ @@ -202,7 +307,7 @@ static int stm32_interrupt(int irq, void *context, void *arg) */ regval &= ~WWDG_SR_EWIF; - putreg32(regval, STM32_WWDG_SR); + stm32_putreg(regval, STM32_WWDG_SR); } return OK; @@ -235,7 +340,7 @@ static int stm32_start(struct watchdog_lowerhalf_s *lower) * except by a reset. */ - putreg32(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); + stm32_putreg(WWDG_CR_WDGA | WWDG_CR_T_RESET | priv->reload, STM32_WWDG_CR); priv->started = true; return OK; } @@ -300,7 +405,7 @@ static int stm32_keepalive(struct watchdog_lowerhalf_s *lower) * a read-modify-write; writing a 0 to WDGA bit does nothing. */ - putreg32((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); + stm32_putreg((WWDG_CR_T_RESET | priv->reload), STM32_WWDG_CR); return OK; } @@ -349,7 +454,7 @@ static int stm32_getstatus(struct watchdog_lowerhalf_s *lower, /* Get the time remaining until the watchdog expires (in milliseconds) */ - reload = (getreg32(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; + reload = (stm32_getreg(STM32_WWDG_CR) >> WWDG_CR_T_SHIFT) & 0x7f; elapsed = priv->reload - reload; status->timeleft = (priv->timeout * elapsed) / (priv->reload + 1); @@ -479,10 +584,10 @@ static int stm32_settimeout(struct watchdog_lowerhalf_s *lower, /* Set WDGTB[1:0] bits according to calculated value */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); regval &= ~WWDG_CFR_WDGTB_MASK; regval |= (uint16_t)wdgtb << WWDG_CFR_WDGTB_SHIFT; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); /* Reset the 7-bit window value to the maximum value.. essentially * disabling the lower limit of the watchdog reset time. @@ -536,13 +641,13 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Are we attaching or detaching the handler? */ - regval = getreg32(STM32_WWDG_CFR); + regval = stm32_getreg(STM32_WWDG_CFR); if (handler) { /* Attaching... Enable the EWI interrupt */ regval |= WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_enable_irq(STM32_IRQ_WWDG); } @@ -551,7 +656,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, /* Detaching... Disable the EWI interrupt */ regval &= ~WWDG_CFR_EWI; - putreg32(regval, STM32_WWDG_CFR); + stm32_putreg(regval, STM32_WWDG_CFR); up_disable_irq(STM32_IRQ_WWDG); } @@ -581,7 +686,7 @@ static xcpt_t stm32_capture(struct watchdog_lowerhalf_s *lower, ****************************************************************************/ static int stm32_ioctl(struct watchdog_lowerhalf_s *lower, int cmd, - unsigned long arg) + unsigned long arg) { struct stm32_lowerhalf_s *priv = (struct stm32_lowerhalf_s *)lower; int ret = -ENOTTY; @@ -663,7 +768,8 @@ void stm32_wwdginitialize(const char *devpath) * device option bits, the watchdog is automatically enabled at power-on. */ - stm32_settimeout((struct watchdog_lowerhalf_s *)priv, WWDG_MAXTIMEOUT); + stm32_settimeout((struct watchdog_lowerhalf_s *)priv, + CONFIG_STM32_WWDG_DEFTIMOUT); /* Register the watchdog driver as /dev/watchdog0 */ @@ -674,11 +780,22 @@ void stm32_wwdginitialize(const char *devpath) * on DBG_WWDG_STOP configuration bit in DBG module. */ -#ifdef CONFIG_DEBUG_FEATURES +#if defined(CONFIG_STM32_JTAG_FULL_ENABLE) || \ + defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE) || \ + defined(CONFIG_STM32_JTAG_SW_ENABLE) { +#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \ + defined(CONFIG_STM32_STM32F4XXX) || defined(CONFIG_STM32_STM32L15XX) uint32_t cr = getreg32(STM32_DBGMCU_APB1_FZ); cr |= DBGMCU_APB1_WWDGSTOP; putreg32(cr, STM32_DBGMCU_APB1_FZ); +#else /* if defined(CONFIG_STM32_STM32F10XX) */ + uint32_t cr = getreg32(STM32_DBGMCU_CR); + cr |= DBGMCU_CR_WWDGSTOP; + putreg32(cr, STM32_DBGMCU_CR); +#endif } #endif } + +#endif /* CONFIG_WATCHDOG && CONFIG_STM32_WWDG */ diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt index 6c370d70d10..f36e41d25df 100644 --- a/arch/arm/src/stm32/CMakeLists.txt +++ b/arch/arm/src/stm32/CMakeLists.txt @@ -30,32 +30,8 @@ list( stm32_rcc.c stm32_lse.c stm32_lsi.c - stm32_gpio.c - stm32_exti_gpio.c - stm32_flash.c stm32_irq.c - stm32_lowputc.c - stm32_spi.c - stm32_i2s.c - stm32_sdio.c - stm32_tim.c - stm32_waste.c - stm32_ccm.c - stm32_uid.c - stm32_capture.c - stm32_dfumode.c) - -if(CONFIG_STM32_USART) - list(APPEND SRCS stm32_serial.c) -endif() - -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - -if(CONFIG_TIMER) - list(APPEND SRCS stm32_tim_lowerhalf.c) -endif() + stm32_lowputc.c) if(CONFIG_STM32_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) @@ -63,64 +39,10 @@ else() list(APPEND SRCS stm32_timerisr.c) endif() -if(CONFIG_STM32_ONESHOT) - list(APPEND SRCS stm32_oneshot.c stm32_oneshot_lowerhalf.c) -endif() - -if(CONFIG_STM32_FREERUN) - list(APPEND SRCS stm32_freerun.c) -endif() - if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) endif() -if(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1) - if(CONFIG_STM32_I2C_ALT) - list(APPEND SRCS stm32_i2c_alt.c) - elseif(CONFIG_STM32_STM32F4XXX) - list(APPEND SRCS stm32f40xxx_i2c.c) - else() - list(APPEND SRCS stm32_i2c.c) - endif() -elseif(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2) - list(APPEND SRCS stm32_i2c_v2.c) - if(CONFIG_STM32_I2C_SLAVE) - list(APPEND SRCS stm32_i2cslave_v2.c) - endif() -endif() - -if(CONFIG_USBDEV) - if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) - endif() - if(CONFIG_STM32_USBFS) - list(APPEND SRCS stm32_usbfs.c) - endif() - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfsdev.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghsdev.c) - endif() -endif() - -if(CONFIG_STM32_USBHOST) - if(CONFIG_STM32_OTGFS) - list(APPEND SRCS stm32_otgfshost.c) - endif() - if(CONFIG_STM32_OTGHS) - list(APPEND SRCS stm32_otghshost.c) - endif() - if(CONFIG_USBHOST_TRACE) - list(APPEND SRCS stm32_usbhost.c) - else() - if(CONFIG_DEBUG_USB) - list(APPEND SRCS stm32_usbhost.c) - endif() - endif() -endif() - if(NOT CONFIG_ARCH_IDLE_CUSTOM) list(APPEND SRCS stm32_idle.c) endif() @@ -131,149 +53,5 @@ if(NOT CONFIG_ARCH_CUSTOM_PMINIT) list(APPEND SRCS stm32_pminitialize.c) endif() -if(CONFIG_STM32_ETHMAC) - list(APPEND SRCS stm32_eth.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c stm32_exti_pwr.c) -endif() - -if(CONFIG_STM32_RTC) - list(APPEND SRCS stm32_rtc.c) - if(CONFIG_RTC_ALARM) - list(APPEND SRCS stm32_exti_alarm.c) - endif() - if(CONFIG_RTC_PERIODIC) - list(APPEND SRCS stm32_exti_wakeup.c) - endif() - if(CONFIG_RTC_DRIVER) - list(APPEND SRCS stm32_rtc_lowerhalf.c) - endif() -endif() - -if(CONFIG_STM32_SDADC) - list(APPEND SRCS stm32_sdadc.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_DAC) - list(APPEND SRCS stm32_dac.c) -endif() - -if(CONFIG_STM32_COMP) - list(APPEND SRCS stm32_comp.c) -endif() - -if(CONFIG_STM32_OPAMP) - list(APPEND SRCS stm32_opamp.c) -endif() - -if(CONFIG_STM32_HRTIM) - list(APPEND SRCS stm32_hrtim.c) -endif() - -if(CONFIG_STM32_1WIREDRIVER) - list(APPEND SRCS stm32_1wire.c) -endif() - -if(CONFIG_STM32_HCIUART) - list(APPEND SRCS stm32_hciuart.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_LTDC) - list(APPEND SRCS stm32_ltdc.c) -endif() - -if(CONFIG_STM32_DMA2D) - list(APPEND SRCS stm32_dma2d.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_CAP) - list(APPEND SRCS stm32_capture_lowerhalf.c) -endif() - -if(CONFIG_SENSORS_QENCODER) - if(CONFIG_STM32_QE) - list(APPEND SRCS stm32_qencoder.c) - endif() -endif() - -if(CONFIG_SENSORS_HALL3PHASE) - list(APPEND SRCS stm32_hall3ph.c) -endif() - -if(CONFIG_STM32_CAN) - if(CONFIG_STM32_CAN_CHARDRIVER) - list(APPEND SRCS stm32_can.c) - endif() - if(CONFIG_STM32_CAN_SOCKET) - list(APPEND SRCS stm32_can_sock.c) - endif() -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_DEBUG_FEATURES) - list(APPEND SRCS stm32_dumpgpio.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - list(APPEND SRCS stm32_crypto.c) -endif() - -if(CONFIG_STM32_BBSRAM) - list(APPEND SRCS stm32_bbsram.c) -endif() - -if(CONFIG_STM32_FMC) - list(APPEND SRCS stm32_fmc.c) -endif() - -if(CONFIG_STM32_FSMC) - list(APPEND SRCS stm32_fsmc.c) -endif() - -if(CONFIG_STM32_FOC) - list(APPEND SRCS stm32_foc.c) -endif() - -if(CONFIG_STM32_CORDIC) - list(APPEND SRCS stm32_cordic.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 0f0b7e4cd0f..a7cf6decf4b 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -23,23 +23,7 @@ include armv7-m/Make.defs CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c -CHIP_CSRCS += stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_spi.c stm32_i2s.c stm32_sdio.c stm32_tim.c -CHIP_CSRCS += stm32_waste.c stm32_ccm.c stm32_uid.c stm32_capture.c -CHIP_CSRCS += stm32_dfumode.c - -ifeq ($(CONFIG_STM32_USART),y) -CHIP_CSRCS += stm32_serial.c -endif - -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += stm32_tim_lowerhalf.c -endif +CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c ifdef CONFIG_STM32_TICKLESS_TIMER CHIP_CSRCS += stm32_tickless.c @@ -47,64 +31,10 @@ else CHIP_CSRCS += stm32_timerisr.c endif -ifeq ($(CONFIG_STM32_ONESHOT),y) -CHIP_CSRCS += stm32_oneshot.c stm32_oneshot_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_FREERUN),y) -CHIP_CSRCS += stm32_freerun.c -endif - ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c endif -ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V1),y) -ifeq ($(CONFIG_STM32_I2C_ALT),y) -CHIP_CSRCS += stm32_i2c_alt.c -else ifeq ($(CONFIG_STM32_STM32F4XXX),y) -CHIP_CSRCS += stm32f40xxx_i2c.c -else -CHIP_CSRCS += stm32_i2c.c -endif -else ifeq ($(CONFIG_STM32_HAVE_IP_I2C_M3M4_V2),y) -CHIP_CSRCS += stm32_i2c_v2.c -ifeq ($(CONFIG_STM32_I2C_SLAVE),y) -CHIP_CSRCS += stm32_i2cslave_v2.c -endif -endif - -ifeq ($(CONFIG_USBDEV),y) -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif -ifeq ($(CONFIG_STM32_USBFS),y) -CHIP_CSRCS += stm32_usbfs.c -endif -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfsdev.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghsdev.c -endif -endif - -ifeq ($(CONFIG_STM32_USBHOST),y) -ifeq ($(CONFIG_STM32_OTGFS),y) -CHIP_CSRCS += stm32_otgfshost.c -endif -ifeq ($(CONFIG_STM32_OTGHS),y) -CHIP_CSRCS += stm32_otghshost.c -endif -ifeq ($(CONFIG_USBHOST_TRACE),y) -CHIP_CSRCS += stm32_usbhost.c -else -ifeq ($(CONFIG_DEBUG_USB),y) -CHIP_CSRCS += stm32_usbhost.c -endif -endif -endif - ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += stm32_idle.c endif @@ -115,147 +45,4 @@ ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CHIP_CSRCS += stm32_pminitialize.c endif -ifeq ($(CONFIG_STM32_ETHMAC),y) -CHIP_CSRCS += stm32_eth.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c -endif - -ifeq ($(CONFIG_STM32_RTC),y) -CHIP_CSRCS += stm32_rtc.c -ifeq ($(CONFIG_RTC_ALARM),y) -CHIP_CSRCS += stm32_exti_alarm.c -endif -ifeq ($(CONFIG_RTC_PERIODIC),y) -CHIP_CSRCS += stm32_exti_wakeup.c -endif -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += stm32_rtc_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_SDADC),y) -CHIP_CSRCS += stm32_sdadc.c -endif - -ifeq ($(CONFIG_STM32_DAC),y) -CHIP_CSRCS += stm32_dac.c -endif - -ifeq ($(CONFIG_STM32_COMP),y) -CHIP_CSRCS += stm32_comp.c -endif - -ifeq ($(CONFIG_STM32_OPAMP),y) -CHIP_CSRCS += stm32_opamp.c -endif - -ifeq ($(CONFIG_STM32_HRTIM),y) -CHIP_CSRCS += stm32_hrtim.c -endif - -ifeq ($(CONFIG_STM32_1WIREDRIVER),y) -CHIP_CSRCS += stm32_1wire.c -endif - -ifeq ($(CONFIG_STM32_HCIUART),y) -CHIP_CSRCS += stm32_hciuart.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_LTDC),y) -CHIP_CSRCS += stm32_ltdc.c -endif - -ifeq ($(CONFIG_STM32_DMA2D),y) -CHIP_CSRCS += stm32_dma2d.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_STM32_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif - -ifeq ($(CONFIG_STM32_CAP),y) -CHIP_CSRCS += stm32_capture_lowerhalf.c -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) - ifeq ($(CONFIG_STM32_QE),y) - CHIP_CSRCS += stm32_qencoder.c - endif -endif - -ifeq ($(CONFIG_SENSORS_HALL3PHASE),y) -CHIP_CSRCS += stm32_hall3ph.c -endif - -ifeq ($(CONFIG_STM32_CAN),y) -ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_can.c -endif -ifeq ($(CONFIG_STM32_CAN_SOCKET),y) -CHIP_CSRCS += stm32_can_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_DEBUG_FEATURES),y) -CHIP_CSRCS += stm32_dumpgpio.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) -CHIP_CSRCS += stm32_crypto.c -endif - -ifeq ($(CONFIG_STM32_BBSRAM),y) -CHIP_CSRCS += stm32_bbsram.c -endif - -ifeq ($(CONFIG_STM32_FMC),y) -CHIP_CSRCS += stm32_fmc.c -endif - -ifeq ($(CONFIG_STM32_FSMC),y) -CHIP_CSRCS += stm32_fsmc.c -endif - -ifeq ($(CONFIG_STM32_FOC),y) -CHIP_CSRCS += stm32_foc.c -endif - -ifeq ($(CONFIG_STM32_CORDIC),y) -CHIP_CSRCS += stm32_cordic.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/hardware/stm32_pinmap.h b/arch/arm/src/stm32/hardware/stm32_pinmap.h deleted file mode 100644 index 7e35c3b9b75..00000000000 --- a/arch/arm/src/stm32/hardware/stm32_pinmap.h +++ /dev/null @@ -1,136 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* STM32L EnergyLite Line ***************************************************/ - -#if defined(CONFIG_STM32_ENERGYLITE) - -/* STM32L15xx family */ - -# if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_pinmap.h" -# else -# error "Unsupported EnergyLite chip" -# endif - -/* STM32 F1 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F10XX) - -/* STM32F100 Value Line */ - -# if defined(CONFIG_STM32_VALUELINE) -# include "hardware/stm32f100_pinmap.h" - -/* STM32 F102 USB Access Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# include "hardware/stm32f102_pinmap.h" - -/* STM32 F103 Low / Medium Density Family */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ - defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ - defined(CONFIG_ARCH_CHIP_STM32F103CB) -# include "hardware/stm32f103c_pinmap.h" - -/* STM32 F103 High Density Family */ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RG) -# include "hardware/stm32f103r_pinmap.h" - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# include "hardware/stm32f103v_pinmap.h" - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ -# elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# include "hardware/stm32f103z_pinmap.h" - -/* STM32 F105/F107 Connectivity Line */ - -# elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# include "hardware/stm32f105v_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# include "hardware/stm32f105r_pinmap.h" - -# elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# include "hardware/stm32f107v_pinmap.h" -# else -# error "Unsupported STM32F10XXX chip" -# endif - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_pinmap.h" - -/* STM32 F3 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_pinmap.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_pinmap.h" - -/* STM32 F412 Family ********************************************************/ - -#elif defined(CONFIG_STM32_STM32F412) -# include "hardware/stm32f412xx_pinmap.h" - -/* STM32 F4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_pinmap.h" - -/* STM32 G4 Family **********************************************************/ - -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_pinmap.h" - -#else -# error "No pinmap file for this STM32 chip" -#endif - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/stm32_comp.c b/arch/arm/src/stm32/stm32_comp.c deleted file mode 100644 index b095de41efa..00000000000 --- a/arch/arm/src/stm32/stm32_comp.c +++ /dev/null @@ -1,60 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" -#include "stm32_comp.h" -#include "stm32_gpio.h" - -/* This file is only a thin shell that includes the correct COMP - * implementation. At this moment STM32 COMP IP versions 1 and 2 are - * supported. - * - STM32 COMP IP version 1: SMT32F33XX - * - STM32 COMP IP version 2: SMT32G4XXX - */ - -#if defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V1) -# include "stm32_comp_v1.c" -#elif defined(CONFIG_STM32_HAVE_IP_COMP_M3M4_V2) -# include "stm32_comp_v2.c" -#else -# error "STM32 COMP IP version not supported." -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ \ No newline at end of file diff --git a/arch/arm/src/stm32/stm32_comp_v2.h b/arch/arm/src/stm32/stm32_comp_v2.h deleted file mode 100644 index 3b748b01a9e..00000000000 --- a/arch/arm/src/stm32/stm32_comp_v2.h +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_comp_v2.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H -#define __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifdef CONFIG_STM32_COMP - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Inverting input. See Table 196 in RM0440 */ - -enum stm32_comp_inm_e -{ - COMP_INM_1_4_VREF, - COMP_INM_1_2_VREF, - COMP_INM_3_4_VREF, - COMP_INM_VREF, - COMP_INM_DAC_1, - COMP_INM_DAC_2, - COMP_INM_PIN_1, - COMP_INM_PIN_2, -}; - -/* Non-inverting input. See Table 195 in RM0440 */ - -enum stm32_comp_inp_e -{ - COMP_INP_PIN_1, - COMP_INP_PIN_2, -}; - -/* Output polarity */ - -enum stm32_comp_pol_e -{ - COMP_POL_NONINVERT, - COMP_POL_INVERTED -}; - -/* Hysteresis */ - -enum stm32_comp_hyst_e -{ - COMP_HYST_DIS, - COMP_HYST_10MV, - COMP_HYST_20MV, - COMP_HYST_30MV, - COMP_HYST_40MV, - COMP_HYST_50MV, - COMP_HYST_60MV, - COMP_HYST_70MV, -}; - -/* Blanking source */ - -enum stm32_comp_blanking_e -{ - COMP_BLANKING_DIS, - COMP_BLANKING_TIMX_OCY_1, - COMP_BLANKING_TIMX_OCY_2, - COMP_BLANKING_TIMX_OCY_3, - COMP_BLANKING_TIMX_OCY_4, - COMP_BLANKING_TIMX_OCY_5, - COMP_BLANKING_TIMX_OCY_6, - COMP_BLANKING_TIMX_OCY_7, -}; - -#endif /* CONFIG_STM32_COMP */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_COMP_V2_H */ diff --git a/arch/arm/src/stm32/stm32_dma.c b/arch/arm/src/stm32/stm32_dma.c deleted file mode 100644 index f5d1f1047a8..00000000000 --- a/arch/arm/src/stm32/stm32_dma.c +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_dma.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct DMA - * implementation for the selected STM32 IP core: - * - STM32 DMA IP version 1 - F0, F1, F3, G4, L0, L1, L4 - * - STM32 DMA IP version 2 - F2, F4, F7, H7 - * - * The STM32 DMA IPv2 differs from the STM32 DMA IPv1 primarily in that it - * adds the concept of "streams" that are used to associate DMA sources with - * DMA channels. - */ - -#if defined(CONFIG_STM32_HAVE_IP_DMA_V1) -# if defined(CONFIG_STM32_HAVE_DMAMUX) -# include "stm32_dma_v1mux.c" -# else -# include "stm32_dma_v1.c" -# endif -#elif defined(CONFIG_STM32_HAVE_IP_DMA_V2) -# include "stm32_dma_v2.c" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_flash.c b/arch/arm/src/stm32/stm32_flash.c deleted file mode 100644 index 0afd013d872..00000000000 --- a/arch/arm/src/stm32/stm32_flash.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provides standard flash access functions, to be used by the flash mtd - * driver. The interface is defined in the include/nuttx/progmem.h - */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/* Include the correct FLASH implementation for the selection STM32 part */ - -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xx_flash.c" -#elif defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) -# include "stm32f10xxf30xx_flash.c" -#elif defined(CONFIG_STM32_STM32F20XX) || defined (CONFIG_STM32_STM32F4XXX) -# include "stm32f20xxf40xx_flash.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxx_flash.c" -#else -# warning "No FLASH support for the selected part" -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_flash.h b/arch/arm/src/stm32/stm32_flash.h deleted file mode 100644 index 6a67d7b2ce6..00000000000 --- a/arch/arm/src/stm32/stm32_flash.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_flash.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H -#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_flash.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int stm32_flash_lock(void); -int stm32_flash_unlock(void); - -/**************************************************************************** - * Name: stm32_flash_user_optbytes - * - * Description: - * Modify the contents of the user option bytes (USR OPT) on the flash. - * This does not set OBL_LAUNCH so new options take effect only after - * next power reset. - * - * Input Parameters: - * clrbits - Bits in the option bytes to be cleared - * setbits - Bits in the option bytes to be set - * - * Returned Value: - * Option bytes after operation is completed - * - ****************************************************************************/ - -uint32_t stm32_flash_users_optbytes(uint32_t clrbits, uint32_t setbits); - -/**************************************************************************** - * Name: stm32_eeprom_size - * - * Description: - * Get EEPROM data memory size - * - * Returned Value: - * Length of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_size(void); - -/**************************************************************************** - * Name: stm32_eeprom_getaddress - * - * Description: - * Get EEPROM data memory address - * - * Returned Value: - * Address of EEPROM memory region - * - ****************************************************************************/ - -size_t stm32_eeprom_getaddress(void); - -/**************************************************************************** - * Name: stm32_eeprom_write - * - * Description: - * Write buffer to EEPROM data memory address - * - * Returned Value: - * Number of written bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_write(size_t addr, const void *buf, size_t buflen); - -/**************************************************************************** - * Name: stm32_eeprom_erase - * - * Description: - * Erase memory on EEPROM data memory address - * - * Returned Value: - * Number of erased bytes or error code. - * - ****************************************************************************/ - -ssize_t stm32_eeprom_erase(size_t addr, size_t eraselen); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_FLASH_H */ diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h deleted file mode 100644 index 4dbaadeee3c..00000000000 --- a/arch/arm/src/stm32/stm32_freerun.h +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_freerun.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_FREERUN_H -#define __ARCH_ARM_SRC_STM32_STM32_FREERUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_FREERUN - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The freerun client must allocate an instance of this structure and called - * stm32_freerun_initialize() before using the freerun facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_freerun_s -{ - uint8_t chan; /* The timer/counter in use */ - uint8_t width; /* Width of timer (16- or 32-bits) */ - struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ - uint32_t frequency; - -#ifndef CONFIG_CLOCK_TIMEKEEPING - uint32_t overflow; /* Timer counter overflow */ -#endif - -#ifdef CONFIG_CLOCK_TIMEKEEPING - uint64_t counter_mask; -#endif -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_freerun_initialize - * - * Description: - * Initialize the freerun timer wrapper - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_freerun_counter - * - * Description: - * Read the counter register of the free-running timer. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifndef CONFIG_CLOCK_TIMEKEEPING - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - struct timespec *ts); - -#else /* CONFIG_CLOCK_TIMEKEEPING */ - -int stm32_freerun_counter(struct stm32_freerun_s *freerun, - uint64_t *counter); - -#endif /* CONFIG_CLOCK_TIMEKEEPING */ - -/**************************************************************************** - * Name: stm32_freerun_uninitialize - * - * Description: - * Stop the free-running timer and release all resources that it uses. - * - * Input Parameters: - * freerun Caller allocated instance of the freerun state structure. This - * structure must have been previously initialized via a call to - * stm32_freerun_initialize(); - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_FREERUN */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_hciuart.h b/arch/arm/src/stm32/stm32_hciuart.h deleted file mode 100644 index ccbc7af5f4d..00000000000 --- a/arch/arm/src/stm32/stm32_hciuart.h +++ /dev/null @@ -1,96 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_hciuart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_HCIUART_H -#define __ARCH_ARM_SRC_STM32_STM32_HCIUART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum hciuart_devno_e -{ - HCIUART1 = 0, /* HCI UART on STM32 USART1 */ - HCIUART2 = 1, /* HCI UART on STM32 USART2 */ - HCIUART3 = 2, /* HCI UART on STM32 USART3 */ - /* UARTs 4-5 do not support RTS/CTS flow control */ - HCIUART5 = 5, /* HCI UART on STM32 USART6 */ - HCIUART6 = 6, /* HCI UART on STM32 UART7 */ - HCIUART7 = 7 /* HCI UART on STM32 UART8 */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: hciuart_instantiate - * - * Description: - * Obtain an instance of the HCI UART interface for the specified HCI UART - * This assumes that hciuart_initialize was called previously. - * - * Input Parameters: - * uart - Identifies the HCI UART to be configured - * - * Returned Value: - * On success, a reference to the HCI UART lower driver for the associated - * U[S]ART - * - ****************************************************************************/ - -const struct btuart_lowerhalf_s * -hciuart_instantiate(enum hciuart_devno_e uart); - -/**************************************************************************** - * Name: hciuart_initialize - * - * Description: - * Performs the low-level, one-time USART initialization. This must be - * called before hciuart_instantiate. - * - ****************************************************************************/ - -void hciuart_initialize(void); - -/**************************************************************************** - * Name: stm32_serial_dma_poll - * - * Description: - * Checks receive DMA buffers for received bytes that have not accumulated - * to the point where the DMA half/full interrupt has triggered. - * - * This function should be called from a timer or other periodic context. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_HCIUART_RXDMA -void stm32_serial_dma_poll(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_HCIUART_H */ diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h deleted file mode 100644 index 913321fa60e..00000000000 --- a/arch/arm/src/stm32/stm32_oneshot.h +++ /dev/null @@ -1,197 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_oneshot.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H -#define __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "stm32_tim.h" - -#ifdef CONFIG_STM32_ONESHOT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#if !defined(CONFIG_STM32_ONESHOT_MAXTIMERS) || \ - CONFIG_STM32_ONESHOT_MAXTIMERS < 1 -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 1 -#endif - -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 8 -# warning Additional logic required to handle more than 8 timers -# undef CONFIG_STM32_ONESHOT_MAXTIMERS -# define CONFIG_STM32_ONESHOT_MAXTIMERS 8 -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* This describes the callback function that will be invoked when the oneshot - * timer expires. The oneshot fires, the client will receive: - * - * arg - The opaque argument provided when the interrupt was registered - */ - -typedef void (*oneshot_handler_t)(void *arg); - -/* The oneshot client must allocate an instance of this structure and called - * stm32_oneshot_initialize() before using the oneshot facilities. The - * client should not access the contents of this structure directly since - * the contents are subject to change. - */ - -struct stm32_oneshot_s -{ - uint8_t chan; /* The timer/counter in use */ -#if CONFIG_STM32_ONESHOT_MAXTIMERS > 1 - uint8_t cbndx; /* Timer callback handler index */ -#endif - volatile bool running; /* True: the timer is running */ - struct stm32_tim_dev_s *tch; /* Pointer returned by - * stm32_tim_init() */ - volatile oneshot_handler_t handler; /* Oneshot expiration callback */ - volatile void *arg; /* The argument that will accompany - * the callback */ - uint32_t frequency; - uint32_t period; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_oneshot_initialize - * - * Description: - * Initialize the oneshot timer wrapper - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure - * chan Timer counter channel to be used. - * resolution The required resolution of the timer in units of - * microseconds. NOTE that the range is restricted to the - * range of uint16_t (excluding zero). - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, - uint16_t resolution); - -/**************************************************************************** - * Name: stm32_oneshot_max_delay - * - * Description: - * Determine the maximum delay of the one-shot timer (in microseconds) - * - ****************************************************************************/ - -int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); - -/**************************************************************************** - * Name: stm32_oneshot_start - * - * Description: - * Start the oneshot timer - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * handler The function to call when when the oneshot timer expires. - * arg An opaque argument that will accompany the callback. - * ts Provides the duration of the one shot timer. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, - oneshot_handler_t handler, void *arg, - const struct timespec *ts); - -/**************************************************************************** - * Name: stm32_oneshot_cancel - * - * Description: - * Cancel the oneshot timer and return the time remaining on the timer. - * - * NOTE: This function may execute at a high rate with no timer running (as - * when pre-emption is enabled and disabled). - * - * Input Parameters: - * oneshot Caller allocated instance of the oneshot state structure. This - * structure must have been previously initialized via a call to - * stm32_oneshot_initialize(); - * ts The location in which to return the time remaining on the - * oneshot timer. A time of zero is returned if the timer is - * not running. - * - * Returned Value: - * Zero (OK) is returned on success. A call to up_timer_cancel() when - * the timer is not active should also return success; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, - struct timespec *ts); - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_STM32_ONESHOT */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_rtc.c b/arch/arm/src/stm32/stm32_rtc.c deleted file mode 100644 index 7d191c98825..00000000000 --- a/arch/arm/src/stm32/stm32_rtc.c +++ /dev/null @@ -1,61 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rtc.c - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/* This file is only a thin shell that includes the correct RTC - * implementation for the selected STM32 family. The correct file cannot be - * selected by the make system because it needs the intelligence that only - * exists in chip.h that can associate an STM32 part number with an STM32 - * family. - */ - -/* The STM32 F1 has a simple battery-backed counter for its RTC and has a - * separate block for the BKP registers. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# include "stm32_rtcounter.c" - -/* The other families use a more traditional Realtime Clock/Calendar (RTCC) - * with broken-out data/time in BCD format. The backup registers are - * integrated into the RTCC in these families. - */ - -#elif defined(CONFIG_STM32_STM32F20XX) || \ - defined(CONFIG_STM32_STM32F30XX) -# include "stm32_rtcc.c" -#elif defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rtcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rtcc.c" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ diff --git a/arch/arm/src/stm32/stm32_uid.h b/arch/arm/src/stm32/stm32_uid.h deleted file mode 100644 index d820fcee8c6..00000000000 --- a/arch/arm/src/stm32/stm32_uid.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_uid.h - * - * SPDX-License-Identifier: BSD-3-Clause - * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. - * SPDX-FileContributor: Marawan Ragab - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_UID_H -#define __ARCH_ARM_SRC_STM32_STM32_UID_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -void stm32_get_uniqueid(uint8_t uniqueid[12]); - -#endif /* __ARCH_ARM_SRC_STM32_STM32_UID_H */ diff --git a/arch/arm/src/stm32/stm32_usbdev.h b/arch/arm/src/stm32/stm32_usbdev.h deleted file mode 100644 index 350bbb234d3..00000000000 --- a/arch/arm/src/stm32/stm32_usbdev.h +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_usbdev.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USBDEV_H -#define __ARCH_ARM_SRC_STM32_STM32_USBDEV_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" -#include "hardware/stm32_usbdev.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of endpoints */ - -#define STM32_NENDPOINTS (8) - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Name: stm32_usbpullup - * - * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB - * software connect and disconnect), then the board software must provide - * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description - * of this method. - * - ****************************************************************************/ - -int stm32_usbpullup(struct usbdev_s *dev, bool enable); - -/**************************************************************************** - * Name: stm32_usbsuspend - * - * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver - * is used. This function is called whenever the USB enters or leaves - * suspend mode. This is an opportunity for the board logic to shutdown - * clocks, power, etc. while the USB is suspended. - * - ****************************************************************************/ - -void stm32_usbsuspend(struct usbdev_s *dev, bool resume); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_USBDEV_H */ diff --git a/arch/arm/src/stm32/stm32_wdg.h b/arch/arm/src/stm32/stm32_wdg.h deleted file mode 100644 index 0ad2d4eb362..00000000000 --- a/arch/arm/src/stm32/stm32_wdg.h +++ /dev/null @@ -1,106 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_wdg.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_WDG_H -#define __ARCH_ARM_SRC_STM32_STM32_WDG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_wdg.h" - -#ifdef CONFIG_WATCHDOG - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_iwdginitialize - * - * Description: - * Initialize the IWDG watchdog time. The watchdog timer is initialized - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * lsifreq - The calibrated LSI clock frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_IWDG -void stm32_iwdginitialize(const char *devpath, uint32_t lsifreq); -#endif - -/**************************************************************************** - * Name: stm32_wwdginitialize - * - * Description: - * Initialize the WWDG watchdog time. The watchdog timer is initializeed - * and registers as 'devpath. The initial state of the watchdog time is - * disabled. - * - * Input Parameters: - * devpath - The full path to the watchdog. This should be of the form - * /dev/watchdog0 - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_WWDG -void stm32_wwdginitialize(const char *devpath); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* CONFIG_WATCHDOG */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_WDG_H */ diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt index 44b85031e93..7eca474eaf9 100644 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ b/arch/arm/src/stm32f0l0g0/CMakeLists.txt @@ -26,23 +26,15 @@ list( APPEND SRCS stm32_start.c - stm32_gpio.c - stm32_exti_gpio.c stm32_irq.c stm32_lowputc.c - stm32_serial.c stm32_lsi.c - stm32_rcc.c - stm32_uid.c) + stm32_rcc.c) if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) list(APPEND SRCS stm32_lse.c) endif() -if(CONFIG_STM32_DMA) - list(APPEND SRCS stm32_dma.c) -endif() - if(CONFIG_STM32_PWR) list(APPEND SRCS stm32_pwr.c) endif() @@ -59,77 +51,5 @@ if(CONFIG_BUILD_PROTECTED) list(APPEND SRCS stm32_userspace.c) endif() -if(CONFIG_STM32_PROGMEM) - list(APPEND SRCS stm32_flash.c) -endif() - -if(CONFIG_STM32_GPIOIRQ) - list(APPEND SRCS stm32_gpioint.c) -endif() - -if(CONFIG_ARCH_IRQPRIO) - list(APPEND SRCS stm32_irqprio.c) -endif() - -if(CONFIG_STM32_HAVE_HSI48) - list(APPEND SRCS stm32_hsi48.c) -endif() - -if(CONFIG_STM32_USB) - list(APPEND SRCS stm32_usbdev.c) -endif() - -if(CONFIG_STM32_I2C) - list(APPEND SRCS stm32_i2c.c) -endif() - -if(CONFIG_STM32_SPI) - list(APPEND SRCS stm32_spi.c) -endif() - -if(CONFIG_STM32_PWM) - list(APPEND SRCS stm32_pwm.c) -endif() - -if(CONFIG_PULSECOUNT AND CONFIG_STM32_TIM1_PULSECOUNT) - list(APPEND SRCS stm32_pulsecount.c) -endif() - -if(CONFIG_STM32_ADC) - list(APPEND SRCS stm32_adc.c) -endif() - -if(CONFIG_STM32_AES) - list(APPEND SRCS stm32_aes.c) -endif() - -if(CONFIG_STM32_RNG) - list(APPEND SRCS stm32_rng.c) -endif() - -if(CONFIG_STM32_TIM) - list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c) -endif() - -if(CONFIG_STM32_IWDG) - list(APPEND SRCS stm32_iwdg.c) -endif() - -if(CONFIG_STM32_WWDG) - list(APPEND SRCS stm32_wwdg.c) -endif() - -if(CONFIG_STM32_FDCAN) - if(CONFIG_STM32_FDCAN_CHARDRIVER) - list(APPEND SRCS stm32_fdcan.c) - endif() - if(CONFIG_STM32_FDCAN_SOCKET) - list(APPEND SRCS stm32_fdcan_sock.c) - endif() -endif() - -if(CONFIG_SENSORS_QENCODER) - list(APPEND SRCS stm32_qencoder.c) -endif() - target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32f0l0g0/Make.defs index 8ff7580bde2..9b02c489210 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32f0l0g0/Make.defs @@ -22,17 +22,13 @@ include armv6-m/Make.defs -CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c -CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c stm32_uid.c +CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c +CHIP_CSRCS += stm32_rcc.c stm32_lsi.c ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) CHIP_CSRCS += stm32_lse.c endif -ifeq ($(CONFIG_STM32_DMA),y) -CHIP_CSRCS += stm32_dma.c -endif - ifeq ($(CONFIG_STM32_PWR),y) CHIP_CSRCS += stm32_pwr.c endif @@ -49,73 +45,4 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c endif -ifeq ($(CONFIG_STM32_PROGMEM),y) -CHIP_CSRCS += stm32_flash.c -endif - -ifeq ($(CONFIG_STM32_GPIOIRQ),y) -CHIP_CSRCS += stm32_gpioint.c -endif - -ifeq ($(CONFIG_STM32_HAVE_HSI48),y) -CHIP_CSRCS += stm32_hsi48.c -endif - -ifeq ($(CONFIG_STM32_USB),y) -CHIP_CSRCS += stm32_usbdev.c -endif - -ifeq ($(CONFIG_STM32_I2C),y) -CHIP_CSRCS += stm32_i2c.c -endif - -ifeq ($(CONFIG_STM32_SPI),y) -CHIP_CSRCS += stm32_spi.c -endif - -ifeq ($(CONFIG_STM32_PWM),y) -CHIP_CSRCS += stm32_pwm.c -endif - -ifeq ($(CONFIG_PULSECOUNT),y) -ifeq ($(CONFIG_STM32_TIM1_PULSECOUNT),y) -CHIP_CSRCS += stm32_pulsecount.c -endif -endif - -ifeq ($(CONFIG_STM32_ADC),y) -CHIP_CSRCS += stm32_adc.c -endif - -ifeq ($(CONFIG_STM32_AES),y) -CHIP_CSRCS += stm32_aes.c -endif - -ifeq ($(CONFIG_STM32_RNG),y) -CHIP_CSRCS += stm32_rng.c -endif - -ifeq ($(CONFIG_STM32_TIM),y) -CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c -endif - -ifeq ($(CONFIG_STM32_IWDG),y) -CHIP_CSRCS += stm32_iwdg.c -endif - -ifeq ($(CONFIG_STM32_WWDG),y) -CHIP_CSRCS += stm32_wwdg.c -endif - -ifeq ($(CONFIG_STM32_FDCAN),y) -ifeq ($(CONFIG_STM32_FDCAN_CHARDRIVER),y) -CHIP_CSRCS += stm32_fdcan.c -endif -ifeq ($(CONFIG_STM32_FDCAN_SOCKET),y) -CHIP_CSRCS += stm32_fdcan_sock.c -endif -endif - -ifeq ($(CONFIG_SENSORS_QENCODER),y) -CHIP_CSRCS += stm32_qencoder.c -endif +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h deleted file mode 100644 index f6f07839c12..00000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_memorymap.h" -#elif defined(CONFIG_STM32_STM32F05X) || \ - defined(CONFIG_STM32_STM32F07X) || \ - defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f05xf07xf09x_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_memorymap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_memorymap.h" -#else -# error "Unsupported STM32 M0 memory map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h deleted file mode 100644 index 3f1e617b3cb..00000000000 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "chip.h" - -#if defined(CONFIG_STM32_STM32F03X) -# include "hardware/stm32f03x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F05X) -# include "hardware/stm32f05x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F07X) -# include "hardware/stm32f07x_pinmap.h" -#elif defined(CONFIG_STM32_STM32F09X) -# include "hardware/stm32f09x_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_pinmap.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_pinmap.h" -#else -# error "Unsupported STM32 M0 pin map" -#endif - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_aes.h b/arch/arm/src/stm32f0l0g0/stm32_aes.h deleted file mode 100644 index f499aa8b95d..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_aes.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_aes.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" - -#include "hardware/stm32_aes.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_AES_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_dma.h b/arch/arm/src/stm32f0l0g0/stm32_dma.h deleted file mode 100644 index ce5cb1a18af..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_dma.h +++ /dev/null @@ -1,327 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_dma.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "hardware/stm32_dma_v1.h" - -#ifdef CONFIG_STM32_HAVE_DMAMUX -# include "hardware/stm32_dmamux.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* These definitions provide the bit encoding of the 'status' parameter - * passed to the DMA callback function (see dma_callback_t). - */ - -#define DMA_STATUS_TEIF DMA_CHAN_TEIF_BIT /* Channel Transfer Error */ -#define DMA_STATUS_HTIF DMA_CHAN_HTIF_BIT /* Channel Half Transfer */ -#define DMA_STATUS_TCIF DMA_CHAN_TCIF_BIT /* Channel Transfer Complete */ - -#define DMA_STATUS_ERROR (DMA_STATUS_TEIF) -#define DMA_STATUS_SUCCESS (DMA_STATUS_TCIF | DMA_STATUS_HTIF) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* DMA_HANDLE provides an opaque reference that can be used to represent a - * DMA channel (F1) or a DMA stream (F4). - */ - -typedef void *DMA_HANDLE; - -/* Description: - * This is the type of the callback that is used to inform the user of the - * completion of the DMA. - * - * Input Parameters: - * handle - Refers to the DMA channel or stream - * status - A bit encoded value that provides the completion status. See - * the DMASTATUS_* definitions above. - * arg - A user-provided value that was provided when stm32_dmastart() - * was called. - */ - -typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg); - -#ifdef CONFIG_DEBUG_DMA_INFO -struct stm32_dmaregs_s -{ - uint32_t isr; - uint32_t ccr; - uint32_t cndtr; - uint32_t cpar; - uint32_t cmar; -}; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_dmachannel - * - * Description: - * Allocate a DMA channel. This function gives the caller mutually - * exclusive access to the DMA channel specified by the 'chan' argument. - * DMA channels are shared on the STM32: Devices sharing the same DMA - * channel cannot do DMA concurrently! See the DMACHAN_* definitions in - * stm32_dma.h. - * - * If the DMA channel is not available, then stm32_dmachannel() will wait - * until the holder of the channel relinquishes the channel by calling - * stm32_dmafree(). WARNING: If you have two devices sharing a DMA - * channel and the code never releases the channel, the stm32_dmachannel - * call for the other will hang forever in this function! Don't let your - * design do that! - * - * Hmm.. I suppose this interface could be extended to make a non-blocking - * version. Feel free to do that if that is what you need. - * - * Input Parameters: - * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h - * - * Returned Value: - * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, - * void* DMA channel handle. (If 'chan' is invalid, the function will - * assert if debug is enabled or do something ignorant otherwise). - * - * Assumptions: - * - The caller does not hold he DMA channel. - * - The caller can wait for the DMA channel to be freed if it is no - * available. - * - ****************************************************************************/ - -DMA_HANDLE stm32_dmachannel(unsigned int chan); - -/**************************************************************************** - * Name: stm32_dmafree - * - * Description: - * Release a DMA channel. If another thread is waiting for this DMA - * channel in a call to stm32_dmachannel, then this function will - * re-assign the DMA channel to that thread and wake it up. - * - * NOTE: The 'handle' used in this argument must NEVER be used again - * until stm32_dmachannel() is called again to re-gain access to - * the channel. - * - * Returned Value: - * None - * - * Assumptions: - * - The caller holds the DMA channel. - * - There is no DMA in progress - * - ****************************************************************************/ - -void stm32_dmafree(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmasetup - * - * Description: - * Configure DMA before using - * - ****************************************************************************/ - -void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, - size_t ntransfers, uint32_t ccr); - -/**************************************************************************** - * Name: stm32_dmastart - * - * Description: - * Start the DMA transfer - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - No DMA in progress - * - ****************************************************************************/ - -void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, - bool half); - -/**************************************************************************** - * Name: stm32_dmastop - * - * Description: - * Cancel the DMA. After stm32_dmastop() is called, the DMA channel is - * reset and stm32_dmasetup() must be called before stm32_dmastart() can - * be called again - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -void stm32_dmastop(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmaresidual - * - * Description: - * Returns the number of bytes remaining to be transferred - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -size_t stm32_dmaresidual(DMA_HANDLE handle); - -/**************************************************************************** - * Name: stm32_dmacapable - * - * Description: - * Check if the DMA controller can transfer data to/from given memory - * address with the given configuration. This depends on the internal - * connections in the ARM bus matrix of the processor. Note that this - * only applies to memory addresses, it will return false for any - * peripheral address. - * - * Returned Value: - * True, if transfer is possible. - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_DMACAPABLE -bool stm32_dmacapable(uintptr_t maddr, uint32_t count, uint32_t ccr); -#else -# define stm32_dmacapable(maddr, count, ccr) (true) -#endif - -/**************************************************************************** - * Name: stm32_dmasample - * - * Description: - * Sample DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs); -#else -# define stm32_dmasample(handle,regs) -#endif - -/**************************************************************************** - * Name: stm32_dmadump - * - * Description: - * Dump previously sampled DMA register contents - * - * Assumptions: - * - DMA handle allocated by stm32_dmachannel() - * - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_DMA_INFO -void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs, - const char *msg); -#else -# define stm32_dmadump(handle,regs,msg) -#endif - -/* High performance, zero latency DMA interrupts need some additional - * interfaces. - * - * TODO: For now the interface is different for STM32 DMAv1 and STM32 DMAv2. - * It should be unified somehow. - */ - -#ifdef CONFIG_ARCH_HIPRI_INTERRUPT - -/**************************************************************************** - * Name: stm32_dma_intack - * - * Description: - * Public visible interface to acknowledge interrupts on DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -void stm32_dma_intack(unsigned int chndx, uint32_t isr); -#elif defined(HAVE_IP_DMA_V2) -void stm32_dma_intack(unsigned int controller, uint8_t stream, uint32_t isr); -#endif - -/**************************************************************************** - * Name: stm32_dma_intget - * - * Description: - * Public visible interface to get pending interrupts from DMA channel - * - ****************************************************************************/ - -#if defined(HAVE_IP_DMA_V1) -uint32_t stm32_dma_intget(unsigned int chndx); -#elif defined(HAVE_IP_DMA_V2) -uint8_t stm32_dma_intget(unsigned int controller, uint8_t stream); -#endif - -#endif /* CONFIG_ARCH_HIPRI_INTERRUPT */ - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_DMA_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_exti.h b/arch/arm/src/stm32f0l0g0/stm32_exti.h deleted file mode 100644 index 33156f0dece..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_exti.h +++ /dev/null @@ -1,131 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_exti.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "hardware/stm32_exti.h" - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_gpiosetevent - * - * Description: - * Sets/clears GPIO based event and interrupt triggers. - * - * Input Parameters: - * - pinset: gpio pin configuration - * - rising/falling edge: enables - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -int stm32_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge, - bool event, xcpt_t func, void *arg); - -/**************************************************************************** - * Name: stm32_exti_alarm - * - * Description: - * Sets/clears EXTI alarm interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -int stm32_exti_alarm(bool risingedge, bool fallingedge, - bool event, xcpt_t func, - void *arg); -#endif - -/**************************************************************************** - * Name: stm32_exti_wakeup - * - * Description: - * Sets/clears EXTI wakeup interrupt. - * - * Input Parameters: - * - rising/falling edge: enables interrupt on rising/falling edges - * - event: generate event when set - * - func: when non-NULL, generate interrupt - * - arg: Argument passed to the interrupt callback - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure indicating the - * nature of the failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_PERIODIC -int stm32_exti_wakeup(bool risingedge, bool fallingedge, bool event, - xcpt_t func, void *arg); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h b/arch/arm/src/stm32f0l0g0/stm32_fdcan.h deleted file mode 100644 index 83893b284ef..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_fdcan.h +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_fdcan.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_fdcan.h" - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Port numbers for use with stm32_fdcan_initialize() */ - -#define FDCAN1 1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_STM32_FDCAN_CHARDRIVER - -/**************************************************************************** - * Name: stm32_fdcaninitialize - * - * Description: - * Initialize the selected FDCAN port - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * Valid FDCAN device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct can_dev_s *stm32_fdcaninitialize(int port); -#endif - -#ifdef CONFIG_STM32_FDCAN_SOCKET - -/**************************************************************************** - * Name: stm32_fdcansockinitialize - * - * Description: - * Initialize the selected FDCAN port as SocketCAN interface - * - * Input Parameters: - * Port number (for hardware that has multiple FDCAN interfaces) - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int stm32_fdcansockinitialize(int port); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_FDCAN_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_i2c.h b/arch/arm/src/stm32f0l0g0/stm32_i2c.h deleted file mode 100644 index 9d1d09b17a9..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_i2c.h +++ /dev/null @@ -1,91 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_i2c.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" -#include "hardware/stm32_i2c.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If a dynamic timeout is selected, then a non-negative, non-zero micro- - * seconds per byte value must be provided as well. - */ - -#ifdef CONFIG_STM32_I2C_DYNTIMEO -# if CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE < 1 -# warning "Ignoring CONFIG_STM32_I2C_DYNTIMEO because of CONFIG_STM32_I2C_DYNTIMEO_USECPERBYTE" -# undef CONFIG_STM32_I2C_DYNTIMEO -# endif -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a unique instance of struct - * struct i2c_master_s. This function may be called to obtain multiple - * instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * Port number (for hardware that has multiple I2C interfaces) - * - * Returned Value: - * Valid I2C device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct i2c_master_s *stm32_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: stm32_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port, and power down the device. - * - * Input Parameters: - * Device structure as returned by the stm32_i2cbus_initialize() - * - * Returned Value: - * OK on success, ERROR when internal reference count mismatch or dev - * points to invalid hardware device. - * - ****************************************************************************/ - -int stm32_i2cbus_uninitialize(struct i2c_master_s *dev); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_I2C_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h b/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h deleted file mode 100644 index 8c8aca535f1..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_pulsecount.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pulsecount.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct pulsecount_lowerhalf_s *stm32_pulsecountinitialize(int timer); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_PULSECOUNT_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h b/arch/arm/src/stm32f0l0g0/stm32_qencoder.h deleted file mode 100644 index c46fbdf9135..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_qencoder.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_qencoder.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -#ifdef CONFIG_SENSORS_QENCODER - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Timer devices may be used for different purposes. One special purpose is - * as a quadrature encoder input device. If CONFIG_STM32_TIMn is - * defined then the CONFIG_STM32_TIMn_QE must also be defined to - * indicate that timer "n" is intended to be used for as a quadrature - * encoder. - */ - -#ifndef CONFIG_STM32_TIM1 -# undef CONFIG_STM32_TIM1_QE -#endif -#ifndef CONFIG_STM32_TIM2 -# undef CONFIG_STM32_TIM2_QE -#endif -#ifndef CONFIG_STM32_TIM3 -# undef CONFIG_STM32_TIM3_QE -#endif -#ifndef CONFIG_STM32_TIM4 -# undef CONFIG_STM32_TIM4_QE -#endif - -/* Only timers 1-4 can be used as a quadrature encoder (timers with - * encoder mode support). - * TIM6, TIM7, TIM14-17 are basic/general purpose timers without encoder - * capability. - */ - -#undef CONFIG_STM32_TIM6_QE -#undef CONFIG_STM32_TIM7_QE -#undef CONFIG_STM32_TIM14_QE -#undef CONFIG_STM32_TIM15_QE -#undef CONFIG_STM32_TIM16_QE -#undef CONFIG_STM32_TIM17_QE - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_qeinitialize - * - * Description: - * Initialize a quadrature encoder interface. - * This function must be called from board-specific logic. - * - * Input Parameters: - * devpath - The full path to the driver to register. E.g., "/dev/qe0" - * tim - The timer number to used. - * 'tim' must be an element of {1,2,3,4} - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qeinitialize(const char *devpath, int tim); - -#ifdef CONFIG_STM32_QENCODER_INDEX_PIN -/**************************************************************************** - * Name: stm32_qe_index_init - * - * Description: - * Register the encoder index pin to a given Qencoder timer - * - * Input Parameters: - * tim - The qenco timer number - * gpio - gpio pin configuration - * - * Returned Value: - * Zero on success; A negated errno value is returned on failure. - * - ****************************************************************************/ - -int stm32_qe_index_init(int tim, uint32_t gpio); -#endif - -#endif /* CONFIG_SENSORS_QENCODER */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_QENCODER_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_spi.h b/arch/arm/src/stm32f0l0g0/stm32_spi.h deleted file mode 100644 index dd99c76575a..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_spi.h +++ /dev/null @@ -1,171 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_spi.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" -#include "hardware/stm32_spi.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -struct spi_dev_s; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_spibus_initialize - * - * Description: - * Initialize the selected SPI bus - * - * Input Parameters: - * bus number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *stm32_spibus_initialize(int bus); - -/**************************************************************************** - * Name: stm32_spi1/2/...select and stm32_spi1/2/...status - * - * Description: - * The external functions, stm32_spi1/2/...select, stm32_spi1/2/...status, - * and stm32_spi1/2/...cmddata must be provided by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s - * (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. - * To use this common SPI logic on your board: - * - * 1. Provide logic in stm32_board_initialize() to configure SPI chip - * select pins. - * 2. Provide stm32_spi1/2/...select() and stm32_spi1/2/...status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide stm32_spi1/2/...cmddata() functions in your - * board-specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a calls to stm32_spibus_initialize() in your low level - * application initialization logic - * 5. The handle returned by stm32_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver - * to the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -#ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid); -int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd); -#endif - -/**************************************************************************** - * Name: stm32_spi1/2/...register - * - * Description: - * If the board supports a card detect callback to inform the SPI-based - * MMC/SD driver when an SD card is inserted or removed, then - * CONFIG_SPI_CALLBACK should be defined and the following function(s) - * must be implemented. These functions implements the registercallback - * method of the SPI interface (see include/nuttx/spi/spi.h for details) - * - * Input Parameters: - * dev - Device-specific state data - * callback - The function to call on the media change - * arg - A caller provided value to return with the callback - * - * Returned Value: - * 0 on success; negated errno on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SPI_CALLBACK -#ifdef CONFIG_STM32_SPI1 -int stm32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI2 -int stm32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif - -#ifdef CONFIG_STM32_SPI3 -int stm32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback, - void *arg); -#endif -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_SPI_H */ From ccdc7a3a2882cc6763e38fea55242ee29201d959 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:43:32 +0200 Subject: [PATCH 151/268] !arch/stm32f0l0g0: move stm32f0 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f0 sources, headers and boards into arch/arm/src/stm32f0, arch/arm/include/stm32f0 and boards/arm/stm32f0. Signed-off-by: raiden00pl --- arch/arm/include/stm32f0/chip.h | 238 ++++++++ .../stm32f0_irq.h => stm32f0/irq.h} | 72 ++- arch/arm/src/stm32f0/CMakeLists.txt | 32 + arch/arm/src/stm32f0/Kconfig | 559 ++++++++++++++++++ arch/arm/src/stm32f0/Make.defs | 31 + .../hardware/stm32_rcc.h => stm32f0/chip.h} | 31 +- .../src/stm32f0/hardware/stm32_memorymap.h | 26 + arch/arm/src/stm32f0/hardware/stm32_pinmap.h | 29 + .../hardware/stm32f03x_memorymap.h | 8 +- .../hardware/stm32f03x_pinmap.h | 8 +- .../hardware/stm32f05x_pinmap.h | 8 +- .../hardware/stm32f05xf07xf09x_memorymap.h | 8 +- .../hardware/stm32f07x_pinmap.h | 8 +- .../hardware/stm32f09x_pinmap.h | 8 +- .../hardware/stm32f0_exti.h | 8 +- .../hardware/stm32f0_flash.h | 8 +- .../hardware/stm32f0_pwr.h | 8 +- .../hardware/stm32f0_rcc.h | 8 +- .../hardware/stm32f0_syscfg.h | 8 +- .../stm32_pwr.c => stm32f0/stm32.h} | 36 +- arch/arm/src/stm32f0/stm32_rcc.c | 220 +++++++ .../{stm32f0l0g0 => stm32f0}/stm32f0_rcc.c | 2 +- boards/arm/stm32f0/common/CMakeLists.txt | 25 + boards/arm/stm32f0/common/Kconfig | 6 + boards/arm/stm32f0/common/Makefile | 38 ++ .../nucleo-f072rb}/CMakeLists.txt | 2 +- .../nucleo-f072rb/Kconfig | 0 .../nucleo-f072rb/configs/nsh/defconfig | 2 +- .../nucleo-f072rb/include/board.h | 2 +- .../nucleo-f072rb/scripts/Make.defs | 2 +- .../nucleo-f072rb/scripts/flash.ld | 2 +- .../nucleo-f072rb/src/CMakeLists.txt | 2 +- .../nucleo-f072rb/src/Make.defs | 2 +- .../nucleo-f072rb/src/nucleo-f072rb.h | 2 +- .../nucleo-f072rb/src/stm32_autoleds.c | 2 +- .../nucleo-f072rb/src/stm32_boot.c | 2 +- .../nucleo-f072rb/src/stm32_bringup.c | 2 +- .../nucleo-f072rb/src/stm32_buttons.c | 2 +- .../nucleo-f072rb/src/stm32_userleds.c | 2 +- .../nucleo-f091rc/CMakeLists.txt | 2 +- .../nucleo-f091rc/Kconfig | 0 .../nucleo-f091rc/configs/nsh/defconfig | 2 +- .../nucleo-f091rc/configs/sx127x/defconfig | 2 +- .../nucleo-f091rc/include/board.h | 2 +- .../nucleo-f091rc/scripts/Make.defs | 2 +- .../nucleo-f091rc/scripts/flash.ld | 2 +- .../nucleo-f091rc/src/CMakeLists.txt | 2 +- .../nucleo-f091rc/src/Make.defs | 2 +- .../nucleo-f091rc/src/nucleo-f091rc.h | 2 +- .../nucleo-f091rc/src/stm32_autoleds.c | 2 +- .../nucleo-f091rc/src/stm32_boot.c | 2 +- .../nucleo-f091rc/src/stm32_bringup.c | 2 +- .../nucleo-f091rc/src/stm32_buttons.c | 2 +- .../nucleo-f091rc/src/stm32_spi.c | 2 +- .../nucleo-f091rc/src/stm32_sx127x.c | 2 +- .../nucleo-f091rc/src/stm32_userleds.c | 2 +- .../stm32f051-discovery}/CMakeLists.txt | 2 +- .../stm32f051-discovery/Kconfig | 0 .../stm32f051-discovery/configs/nsh/defconfig | 2 +- .../stm32f051-discovery/include/board.h | 2 +- .../stm32f051-discovery/scripts/Make.defs | 41 ++ .../stm32f051-discovery/scripts/flash.ld | 2 +- .../stm32f051-discovery/src/CMakeLists.txt | 2 +- .../stm32f051-discovery/src/Make.defs | 2 +- .../stm32f051-discovery/src/stm32_autoleds.c | 2 +- .../stm32f051-discovery/src/stm32_boot.c | 2 +- .../stm32f051-discovery/src/stm32_bringup.c | 2 +- .../stm32f051-discovery/src/stm32_buttons.c | 2 +- .../stm32f051-discovery/src/stm32_userleds.c | 2 +- .../src/stm32f051-discovery.h | 2 +- .../stm32f072-discovery/CMakeLists.txt | 23 + .../stm32f072-discovery/Kconfig | 0 .../stm32f072-discovery/configs/nsh/defconfig | 2 +- .../stm32f072-discovery/include/board.h | 2 +- .../stm32f072-discovery/scripts/Make.defs | 41 ++ .../stm32f072-discovery/scripts/flash.ld | 2 +- .../stm32f072-discovery/src/CMakeLists.txt | 2 +- .../stm32f072-discovery/src/Make.defs | 2 +- .../stm32f072-discovery/src/stm32_autoleds.c | 2 +- .../stm32f072-discovery/src/stm32_boot.c | 2 +- .../stm32f072-discovery/src/stm32_bringup.c | 2 +- .../stm32f072-discovery/src/stm32_buttons.c | 2 +- .../stm32f072-discovery/src/stm32_userleds.c | 2 +- .../src/stm32f072-discovery.h | 2 +- 84 files changed, 1478 insertions(+), 164 deletions(-) create mode 100644 arch/arm/include/stm32f0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32f0_irq.h => stm32f0/irq.h} (80%) create mode 100644 arch/arm/src/stm32f0/CMakeLists.txt create mode 100644 arch/arm/src/stm32f0/Kconfig create mode 100644 arch/arm/src/stm32f0/Make.defs rename arch/arm/src/{stm32f0l0g0/hardware/stm32_rcc.h => stm32f0/chip.h} (67%) create mode 100644 arch/arm/src/stm32f0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f03x_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f03x_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f05x_pinmap.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f05xf07xf09x_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f07x_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f09x_pinmap.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_exti.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_flash.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_pwr.h (94%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32f0}/hardware/stm32f0_syscfg.h (99%) rename arch/arm/src/{stm32f0l0g0/stm32_pwr.c => stm32f0/stm32.h} (70%) create mode 100644 arch/arm/src/stm32f0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => stm32f0}/stm32f0_rcc.c (99%) create mode 100644 boards/arm/stm32f0/common/CMakeLists.txt create mode 100644 boards/arm/stm32f0/common/Kconfig create mode 100644 boards/arm/stm32f0/common/Makefile rename boards/arm/{stm32f0l0g0/nucleo-c071rb => stm32f0/nucleo-f072rb}/CMakeLists.txt (94%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/configs/nsh/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/nucleo-f072rb.h (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/stm32_bringup.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f072rb/src/stm32_userleds.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/CMakeLists.txt (94%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/configs/nsh/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/configs/sx127x/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/nucleo-f091rc.h (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_bringup.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_sx127x.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/nucleo-f091rc/src/stm32_userleds.c (98%) rename boards/arm/{stm32f0l0g0/b-l072z-lrwan1 => stm32f0/stm32f051-discovery}/CMakeLists.txt (94%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/include/board.h (99%) create mode 100644 boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32_autoleds.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32_boot.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32_bringup.c (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32_userleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f051-discovery/src/stm32f051-discovery.h (98%) create mode 100644 boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/include/board.h (99%) create mode 100644 boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32_autoleds.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32_boot.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32_bringup.c (96%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32_userleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32f0}/stm32f072-discovery/src/stm32f072-discovery.h (98%) diff --git a/arch/arm/include/stm32f0/chip.h b/arch/arm/include/stm32f0/chip.h new file mode 100644 index 00000000000..c045084d62e --- /dev/null +++ b/arch/arm/include/stm32f0/chip.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/arm/include/stm32f0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) + +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 0 /* No I2S modules */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* One DAC channel */ +# define STM32_NCOMP 0 /* Two Analog Comparators */ +# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) + +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ + +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* Two USARTs modules */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 1 /* One DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072C8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072R8 +# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) + +# ifdef CONFIG_ARCH_CHIP_STM32F072V8 +# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ +# else +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# endif +# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USARTs module */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) + +# ifdef CONFIG_ARCH_CHIP_STM32F091CB +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 6 /* Six USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCAP 17 /* Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) + +# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# else +# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ +# endif +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ +# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ +# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C modules */ +# define STM32_NDMA 2 /* DMA1, DMA2 */ +# define STM32_NUSART 8 /* Eight USARTs modules */ +# define STM32_NCAN 1 /* One CAN controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channel */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) +# define STM32_NCAP 24 /* Capacitive sensing channels */ +# else +# define STM32_NCAP 18 /* Capacitive sensing channels */ +# endif +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h b/arch/arm/include/stm32f0/irq.h similarity index 80% rename from arch/arm/include/stm32f0l0g0/stm32f0_irq.h rename to arch/arm/include/stm32f0/irq.h index 1d214b1569c..c142f9068be 100644 --- a/arch/arm/include/stm32f0l0g0/stm32f0_irq.h +++ b/arch/arm/include/stm32f0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32f0_irq.h + * arch/arm/include/stm32f0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */ #define STM32_IRQ_PVD_VDDIO2 (STM32_IRQ_EXTINT + 1) /* 1: PVD_VDDIO2 */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ @@ -97,35 +118,8 @@ #define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */ #define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */ -#define STM32_IRQ_NEXTINTS (32) /* 32 external interrupts */ +#define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32F0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F0_IRQ_H */ diff --git a/arch/arm/src/stm32f0/CMakeLists.txt b/arch/arm/src/stm32f0/CMakeLists.txt new file mode 100644 index 00000000000..1d1fbc82d05 --- /dev/null +++ b/arch/arm/src/stm32f0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32f0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0/Kconfig b/arch/arm/src/stm32f0/Kconfig new file mode 100644 index 00000000000..f25a1017f3f --- /dev/null +++ b/arch/arm/src/stm32f0/Kconfig @@ -0,0 +1,559 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F0 configuration" + +if ARCH_CHIP_STM32F0 + +choice + prompt "ST STM32F0 Chip Selection" + default ARCH_CHIP_STM32F051R8 + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C6 + bool "STM32F030C6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030C8 + bool "STM32F030C8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030CC + bool "STM32F030CC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030F4 + bool "STM32F030F4" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030K6 + bool "STM32F030K6" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030R8 + bool "STM32F030R8" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F030RC + bool "STM32F030RC" + select STM32_STM32F03X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C4 + bool "STM32F031C4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031C6 + bool "STM32F031C6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031E6 + bool "STM32F031E6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F4 + bool "STM32F031F4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031F6 + bool "STM32F031F6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G4 + bool "STM32F031G4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031G6 + bool "STM32F031G6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K4 + bool "STM32F031K4" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F031K6 + bool "STM32F031K6" + select STM32_STM32F03X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038C6 + bool "STM32F038C6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038E6 + bool "STM32F038E6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038F6 + bool "STM32F038F6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038G6 + bool "STM32F038G6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F038K6 + bool "STM32F038K6" + select STM32_STM32F03X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C4 + bool "STM32F042C4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042C6 + bool "STM32F042C6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F4 + bool "STM32F042F4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042F6 + bool "STM32F042F6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G4 + bool "STM32F042G4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042G6 + bool "STM32F042G6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K4 + bool "STM32F042K4" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042K6 + bool "STM32F042K6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F042T6 + bool "STM32F042T6" + select STM32_STM32F04X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048C6 + bool "STM32F048C6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048G6 + bool "STM32F048G6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F048T6 + bool "STM32F048T6" + select STM32_STM32F04X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C4 + bool "STM32F051C4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C6 + bool "STM32F051C6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051C8 + bool "STM32F051C8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K4 + bool "STM32F051K4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K6 + bool "STM32F051K6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051K8 + bool "STM32F051K8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R4 + bool "STM32F051R4" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R6 + bool "STM32F051R6" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051R8 + bool "STM32F051R8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F051T8 + bool "STM32F051T8" + select STM32_STM32F05X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058C8 + bool "STM32F058C8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058R8 + bool "STM32F058R8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F058T8 + bool "STM32F058T8" + select STM32_STM32F05X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070C6 + bool "STM32F070C6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070CB + bool "STM32F070CB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070F6 + bool "STM32F070F6" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F070RB + bool "STM32F070RB" + select STM32_STM32F07X + select STM32F0_VALUELINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071C8 + bool "STM32F071C8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071CB + bool "STM32F071CB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071RB + bool "STM32F071RB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071V8 + bool "STM32F071V8" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F071VB + bool "STM32F071VB" + select STM32_STM32F07X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072C8 + bool "STM32F072C8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072CB + bool "STM32F072CB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072R8 + bool "STM32F072R8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072RB + bool "STM32F072RB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072V8 + bool "STM32F072V8" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F072VB + bool "STM32F072VB" + select STM32_STM32F07X + select STM32F0_USBLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078CB + bool "STM32F078CB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078RB + bool "STM32F078RB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F078VB + bool "STM32F078VB" + select STM32_STM32F07X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CB + bool "STM32F091CB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091CC + bool "STM32F091CC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RB + bool "STM32F091RB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091RC + bool "STM32F091RC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VB + bool "STM32F091VB" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F091VC + bool "STM32F091VC" + select STM32_STM32F09X + select STM32F0_ACCESSLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098CC + bool "STM32F098CC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098RC + bool "STM32F098RC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +config ARCH_CHIP_STM32F098VC + bool "STM32F098VC" + select STM32_STM32F09X + select STM32F0_LOWVOLTLINE + depends on ARCH_CHIP_STM32F0 + +endchoice + +endif + +config STM32_STM32F0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKP + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_CAN_BXCAN_M0_V1 + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config STM32_STM32F03X + bool + default n + select STM32_STM32F0 + +config STM32_STM32F04X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + +config STM32_STM32F05X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_DMA2 + +config STM32_STM32F07X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32_STM32F09X + bool + default n + select STM32_STM32F0 + select STM32_HAVE_HSI48 + select STM32_HAVE_DMA2 + +config STM32F0_VALUELINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + +config STM32F0_ACCESSLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_LOWVOLTLINE + bool + default n + select STM32_HAVE_USART5 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + +config STM32F0_USBLINE + bool + default n + select STM32_HAVE_HSI48 + select STM32_HAVE_CAN1 + select STM32_HAVE_SPI2 + select STM32_HAVE_USBDEV diff --git a/arch/arm/src/stm32f0/Make.defs b/arch/arm/src/stm32f0/Make.defs new file mode 100644 index 00000000000..54436033fa2 --- /dev/null +++ b/arch/arm/src/stm32f0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32f0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h b/arch/arm/src/stm32f0/chip.h similarity index 67% rename from arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h rename to arch/arm/src/stm32f0/chip.h index 9242ac00ff6..3e5f5a1103c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h +++ b/arch/arm/src/stm32f0/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h + * arch/arm/src/stm32f0/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,26 +20,25 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_CHIP_H +#define __ARCH_ARM_SRC_STM32F0_CHIP_H /**************************************************************************** * Included Files ****************************************************************************/ #include -#include "chip.h" +#include "nvic.h" -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "hardware/stm32f0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "hardware/stm32l0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "hardware/stm32g0_rcc.h" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "hardware/stm32c0_rcc.h" -#else -# error "Unsupported STM32 M0 RCC" -#endif +/* Include the chip capabilities file */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_RCC_H */ +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F0_CHIP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..b11687cda1f --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_memorymap.h @@ -0,0 +1,26 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_memorymap.h" +#elif defined(CONFIG_STM32_STM32F05X) || defined(CONFIG_STM32_STM32F07X) || \ + defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f05xf07xf09x_memorymap.h" +#else +# error "Unsupported STM32F0 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0/hardware/stm32_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..847044b52b3 --- /dev/null +++ b/arch/arm/src/stm32f0/hardware/stm32_pinmap.h @@ -0,0 +1,29 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F03X) +# include "hardware/stm32f03x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F05X) +# include "hardware/stm32f05x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F07X) +# include "hardware/stm32f07x_pinmap.h" +#elif defined(CONFIG_STM32_STM32F09X) +# include "hardware/stm32f09x_pinmap.h" +#else +# error "Unsupported STM32F0 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h index b88eb339fe7..c993ab03591 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -141,4 +141,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h index 1c9bbb9622c..6a8d81bf82d 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f03x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f03x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ #define GPIO_USART4_TX_1 (GPIO_ALT | GPIO_AF0 | GPIO_PORTC | GPIO_PIN10) #define GPIO_USART4_TX_2 (GPIO_ALT | GPIO_AF4 | GPIO_PORTA | GPIO_PIN0) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F03X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F03X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h index 81964a46b93..436a483058a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f05x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H /**************************************************************************** * Included Files @@ -119,4 +119,4 @@ #define GPIO_I2C2_SCL_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN10) #define GPIO_I2C2_SDA_0 (GPIO_ALT | GPIO_AF1 | GPIO_OPENDRAIN | GPIO_PORTB | GPIO_PIN11) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h rename to arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h index 384e67bdeea..b8fa02c00a1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f05xf07xf09x_memorymap.h + * arch/arm/src/stm32f0/hardware/stm32f05xf07xf09x_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -145,4 +145,4 @@ #define STM32_SYSMEM_UID 0x1ffff7ac /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F05XF07XF09X_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h index 2210e67af11..24255d24048 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f07x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f07x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H /**************************************************************************** * Included Files @@ -385,4 +385,4 @@ #define GPIO_USB_NOE_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN13) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F07X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F07X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h rename to arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h index b2b2b44cd9b..bfeb238a732 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h +++ b/arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f09x_pinmap.h + * arch/arm/src/stm32f0/hardware/stm32f09x_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H /**************************************************************************** * Included Files @@ -414,4 +414,4 @@ #define GPIO_USART8_RX_3 (GPIO_ALT | GPIO_AF0 | GPIO_PORTD | GPIO_PIN13) #define GPIO_USART8_CK_RST_0 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN14) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F09X_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F09X_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h rename to arch/arm/src/stm32f0/hardware/stm32f0_exti.h index ec2f58f8a18..d006ddb3ff1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_exti.h + * arch/arm/src/stm32f0/hardware/stm32f0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H /**************************************************************************** * Included Files @@ -114,4 +114,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h rename to arch/arm/src/stm32f0/hardware/stm32f0_flash.h index fde24890c4f..46c87416a0a 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_flash.h + * arch/arm/src/stm32f0/hardware/stm32f0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H /**************************************************************************** * Included Files @@ -94,4 +94,4 @@ #define FLASH_OBR_ /* To be provided */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h similarity index 94% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h rename to arch/arm/src/stm32f0/hardware/stm32f0_pwr.h index 64a693f7522..9b981257bc5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h + * arch/arm/src/stm32f0/hardware/stm32f0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H /**************************************************************************** * Included Files @@ -85,4 +85,4 @@ #define PWR_CSR_EWUP7 (1 << 14) /* Bit 14: Enable WKUP7 pin */ #define PWR_CSR_EWUP8 (1 << 15) /* Bit 15: Enable WKUP8 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h rename to arch/arm/src/stm32f0/hardware/stm32f0_rcc.h index 63c213b1531..3bd0a3dab17 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_rcc.h + * arch/arm/src/stm32f0/hardware/stm32f0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -391,4 +391,4 @@ #define RCC_CR2_HSI48CAL_SHIFT (24) /* Bits 24-31: HSI48 factory clock calibration */ #define RCC_CR2_HSI48CAL_MASK (0xff << RCC_CR2_HSI48CAL_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h rename to arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h index 63f38bf07ca..f7822582a67 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h +++ b/arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32f0_syscfg.h + * arch/arm/src/stm32f0/hardware/stm32f0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H /**************************************************************************** * Included Files @@ -378,4 +378,4 @@ #define SYSCFG_ITLINE30_CEC (1 << 0) /* Bit 0: CEC interrupt request pending, combined with EXTI line 27 */ #define SYSCFG_ITLINE30_CAN (1 << 1) /* Bit 1: CAN interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32F0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32F0_HARDWARE_STM32F0_SYSCFG_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_pwr.c b/arch/arm/src/stm32f0/stm32.h similarity index 70% rename from arch/arm/src/stm32f0l0g0/stm32_pwr.c rename to arch/arm/src/stm32f0/stm32.h index 70c8df356ab..fabdd48a625 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_pwr.c +++ b/arch/arm/src/stm32f0/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_pwr.c + * arch/arm/src/stm32f0/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,23 +20,35 @@ * ****************************************************************************/ +#ifndef __ARCH_ARM_SRC_STM32F0_STM32_H +#define __ARCH_ARM_SRC_STM32F0_STM32_H + /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + #include "chip.h" - -/* This file is only a thin shell that includes the proper PWR implementation - * according to the selected MCU family. - */ - -#if defined(CONFIG_STM32_STM32G0) -# include "stm32g0_pwr.c" -#elif defined(CONFIG_STM32_STM32F0) || defined(CONFIG_STM32_STM32L0) -# include "stm32f0l0_pwr.c" -#endif +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" /**************************************************************************** - * Public Functions + * Pre-processor Definitions ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32F0_STM32_H */ diff --git a/arch/arm/src/stm32f0/stm32_rcc.c b/arch/arm/src/stm32f0/stm32_rcc.c new file mode 100644 index 00000000000..d343b49ad17 --- /dev/null +++ b/arch/arm/src/stm32f0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32f0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c b/arch/arm/src/stm32f0/stm32f0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32f0_rcc.c rename to arch/arm/src/stm32f0/stm32f0_rcc.c index 018b81897df..b5106208ca9 100644 --- a/arch/arm/src/stm32f0l0g0/stm32f0_rcc.c +++ b/arch/arm/src/stm32f0/stm32f0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32f0_rcc.c + * arch/arm/src/stm32f0/stm32f0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/common/CMakeLists.txt b/boards/arm/stm32f0/common/CMakeLists.txt new file mode 100644 index 00000000000..d2fe9a8016b --- /dev/null +++ b/boards/arm/stm32f0/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32f0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32f0/common/Kconfig b/boards/arm/stm32f0/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32f0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f0/common/Makefile b/boards/arm/stm32f0/common/Makefile new file mode 100644 index 00000000000..f71484ae823 --- /dev/null +++ b/boards/arm/stm32f0/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32f0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt index 93b039d1da7..f4c468079f8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f072rb/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig b/boards/arm/stm32f0/nucleo-f072rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig rename to boards/arm/stm32f0/nucleo-f072rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig rename to boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig index e65551b343e..4a266b9184f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/configs/nsh/defconfig +++ b/boards/arm/stm32f0/nucleo-f072rb/configs/nsh/defconfig @@ -24,7 +24,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f072rb" CONFIG_ARCH_BOARD_NUCLEO_F072RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h b/boards/arm/stm32f0/nucleo-f072rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h rename to boards/arm/stm32f0/nucleo-f072rb/include/board.h index c8098bc38de..ecbb09cd8db 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h +++ b/boards/arm/stm32f0/nucleo-f072rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/include/board.h + * boards/arm/stm32f0/nucleo-f072rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs rename to boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs index cb4dd043232..8565d214ef4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/Make.defs +# boards/arm/stm32f0/nucleo-f072rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld rename to boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld index 5e638ee2498..ae6006b5cdb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld +++ b/boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/scripts/flash.ld + * boards/arm/stm32f0/nucleo-f072rb/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt index 16d4ed14c12..26e316b2b24 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f072rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs rename to boards/arm/stm32f0/nucleo-f072rb/src/Make.defs index 27aae3fb3b1..8d74dbfdb4c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs +++ b/boards/arm/stm32f0/nucleo-f072rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f072rb/src/Make.defs +# boards/arm/stm32f0/nucleo-f072rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h rename to boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h index 36016f917cc..d4bf7700d10 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h +++ b/boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/nucleo-f072rb.h + * boards/arm/stm32f0/nucleo-f072rb/src/nucleo-f072rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c index 2738e92b21d..dbd5f76182e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_autoleds.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c index fb79ff4c3a4..e1c37566fda 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_boot.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c index dbb0d70b4b8..ccf38aeb624 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_bringup.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c index 246f6a7a98e..8bca5ed46ca 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_buttons.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c rename to boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c index a64c333c331..9715fe31a22 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c +++ b/boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f072rb/src/stm32_userleds.c + * boards/arm/stm32f0/nucleo-f072rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt index a9ce71ece55..7b9d3c1af75 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f091rc/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig b/boards/arm/stm32f0/nucleo-f091rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig rename to boards/arm/stm32f0/nucleo-f091rc/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig rename to boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig index 23fbeaa2d4d..1cd0f3abf39 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/nsh/defconfig +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/nsh/defconfig @@ -24,7 +24,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig rename to boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig index f38d694fe4b..0298afca179 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/configs/sx127x/defconfig +++ b/boards/arm/stm32f0/nucleo-f091rc/configs/sx127x/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f091rc" CONFIG_ARCH_BOARD_NUCLEO_F091RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F091RC=y CONFIG_ARCH_CHIP_STM32F0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h b/boards/arm/stm32f0/nucleo-f091rc/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h rename to boards/arm/stm32f0/nucleo-f091rc/include/board.h index dd2355bc204..745d8a66443 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h +++ b/boards/arm/stm32f0/nucleo-f091rc/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/include/board.h + * boards/arm/stm32f0/nucleo-f091rc/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs rename to boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs index 0ee77f57b23..712d91084b7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/Make.defs +# boards/arm/stm32f0/nucleo-f091rc/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld rename to boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld index 4965225b112..7d017d64323 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld +++ b/boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/scripts/flash.ld + * boards/arm/stm32f0/nucleo-f091rc/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt rename to boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt index afd6342087a..3ca74165ebc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +++ b/boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/CMakeLists.txt +# boards/arm/stm32f0/nucleo-f091rc/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs rename to boards/arm/stm32f0/nucleo-f091rc/src/Make.defs index 82b838efb81..a79b2d81893 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +++ b/boards/arm/stm32f0/nucleo-f091rc/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-f091rc/src/Make.defs +# boards/arm/stm32f0/nucleo-f091rc/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h rename to boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h index fadc808cd38..e1f962c5270 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h +++ b/boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/nucleo-f091rc.h + * boards/arm/stm32f0/nucleo-f091rc/src/nucleo-f091rc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c index 6462ab5c813..c6905fbe01e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_autoleds.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c index 57014d141df..2d58bdb01f2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_boot.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c index 02697f3f888..0a1f1e5eba1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_bringup.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c index 6bcff91cece..060097e42e6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_buttons.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c index 0fc2cab2ae5..253eae21e0d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_spi.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c index 2c674d8aa64..2f96bee9948 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_sx127x.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c rename to boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c index cf8e3cccc45..92b0a4bcdd3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c +++ b/boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-f091rc/src/stm32_userleds.c + * boards/arm/stm32f0/nucleo-f091rc/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt rename to boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt index be95ff78863..82f56ec121e 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/CMakeLists.txt +# boards/arm/stm32f0/stm32f051-discovery/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig b/boards/arm/stm32f0/stm32f051-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig rename to boards/arm/stm32f0/stm32f051-discovery/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig rename to boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig index cfea4a1858a..2e21e6e8d07 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0/stm32f051-discovery/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f051-discovery" CONFIG_ARCH_BOARD_STM32F051_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F051R8=y CONFIG_ARCH_CHIP_STM32F0=y diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h b/boards/arm/stm32f0/stm32f051-discovery/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h rename to boards/arm/stm32f0/stm32f051-discovery/include/board.h index 0975e695619..64aa156add7 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f051-discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/include/board.h + * boards/arm/stm32f0/stm32f051-discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs new file mode 100644 index 00000000000..101580bd303 --- /dev/null +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f051-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld rename to boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld index bd4efbb4503..7be00e78d98 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld +++ b/boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/flash.ld + * boards/arm/stm32f0/stm32f051-discovery/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt rename to boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt index 091c56d51df..ea0e96675cc 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/CMakeLists.txt +# boards/arm/stm32f0/stm32f051-discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs rename to boards/arm/stm32f0/stm32f051-discovery/src/Make.defs index b991bc06e47..df3653b25ac 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +++ b/boards/arm/stm32f0/stm32f051-discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/Make.defs +# boards/arm/stm32f0/stm32f051-discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c index 1528e56afd6..db37ca075aa 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_autoleds.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c index bd53babb84a..94dafa4afee 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_boot.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c index 5ad5089520c..c3adb7ee280 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_bringup.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c index 9fd07f705f5..fefd449f40a 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_buttons.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c index d0bda657d64..973ab746680 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32_userleds.c + * boards/arm/stm32f0/stm32f051-discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h rename to boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h index 5c74903ff1f..46edd74b739 100644 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h +++ b/boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f051-discovery/src/stm32f051-discovery.h + * boards/arm/stm32f0/stm32f051-discovery/src/stm32f051-discovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt new file mode 100644 index 00000000000..2e72ceab91a --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f0/stm32f072-discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig b/boards/arm/stm32f0/stm32f072-discovery/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig rename to boards/arm/stm32f0/stm32f072-discovery/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig rename to boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig index 9a218ef1cc1..8496c183dd9 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f0/stm32f072-discovery/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f072-discovery" CONFIG_ARCH_BOARD_STM32F072_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32f0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F072RB=y CONFIG_ARCH_CHIP_STM32F0=y diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h b/boards/arm/stm32f0/stm32f072-discovery/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h rename to boards/arm/stm32f0/stm32f072-discovery/include/board.h index 06932bb64ee..52a339aee2a 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h +++ b/boards/arm/stm32f0/stm32f072-discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/include/board.h + * boards/arm/stm32f0/stm32f072-discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs new file mode 100644 index 00000000000..9796d338da4 --- /dev/null +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f0/stm32f072-discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld rename to boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld index 5ae8a09a00d..fc42f97036a 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld +++ b/boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/flash.ld + * boards/arm/stm32f0/stm32f072-discovery/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt rename to boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt index ac55fa30c74..4a75392b78b 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/CMakeLists.txt +# boards/arm/stm32f0/stm32f072-discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs rename to boards/arm/stm32f0/stm32f072-discovery/src/Make.defs index b71427a7627..e5b94f00634 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +++ b/boards/arm/stm32f0/stm32f072-discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/src/Make.defs +# boards/arm/stm32f0/stm32f072-discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c index c6860f90f7a..dc5246da655 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_autoleds.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c index 623f491e91a..5992d7a77ca 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_boot.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c similarity index 96% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c index 4302171b881..48c86e9507b 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_bringup.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c index 6c894a4a375..a4c7fa265fd 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_buttons.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c index 55510283936..30c60093484 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32_userleds.c + * boards/arm/stm32f0/stm32f072-discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h rename to boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h index db6fe74ca29..48251792969 100644 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h +++ b/boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32f072-discovery/src/stm32f072-discovery.h + * boards/arm/stm32f0/stm32f072-discovery/src/stm32f072-discovery.h * * SPDX-License-Identifier: Apache-2.0 * From ebdd79abd25eacc336a10b6a0c518293875bef7c Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:43:32 +0200 Subject: [PATCH 152/268] !arch/stm32f0l0g0: move stm32l0 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32l0 sources, headers and boards into arch/arm/src/stm32l0, arch/arm/include/stm32l0 and boards/arm/stm32l0. Signed-off-by: raiden00pl --- arch/arm/include/stm32l0/chip.h | 371 ++++++++++++++++++ .../stm32l0_irq.h => stm32l0/irq.h} | 79 ++-- arch/arm/src/stm32l0/CMakeLists.txt | 32 ++ arch/arm/src/stm32l0/Kconfig | 273 +++++++++++++ arch/arm/src/stm32l0/Make.defs | 31 ++ arch/arm/src/stm32l0/chip.h | 44 +++ .../src/stm32l0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32l0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32l0_exti.h | 8 +- .../hardware/stm32l0_flash.h | 8 +- .../hardware/stm32l0_memorymap.h | 8 +- .../hardware/stm32l0_pinmap.h | 8 +- .../hardware/stm32l0_pwr.h | 8 +- .../hardware/stm32l0_rcc.h | 8 +- .../hardware/stm32l0_syscfg.h | 8 +- arch/arm/src/stm32l0/stm32.h | 54 +++ arch/arm/src/stm32l0/stm32_rcc.c | 220 +++++++++++ .../{stm32f0l0g0 => stm32l0}/stm32l0_rcc.c | 2 +- .../arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt | 23 ++ .../b-l072z-lrwan1/Kconfig | 0 .../b-l072z-lrwan1/configs/adc/defconfig | 2 +- .../b-l072z-lrwan1/configs/nsh/defconfig | 2 +- .../configs/nxlines_oled/defconfig | 2 +- .../b-l072z-lrwan1/configs/sx127x/defconfig | 2 +- .../b-l072z-lrwan1/include/board.h | 2 +- .../stm32l0/b-l072z-lrwan1/scripts/Make.defs | 41 ++ .../b-l072z-lrwan1/scripts/ld.script | 2 +- .../b-l072z-lrwan1/src/CMakeLists.txt | 2 +- .../b-l072z-lrwan1/src/Make.defs | 2 +- .../b-l072z-lrwan1/src/b-l072z-lrwan1.h | 2 +- .../b-l072z-lrwan1/src/stm32_adc.c | 2 +- .../b-l072z-lrwan1/src/stm32_autoleds.c | 2 +- .../b-l072z-lrwan1/src/stm32_boot.c | 2 +- .../b-l072z-lrwan1/src/stm32_bringup.c | 2 +- .../b-l072z-lrwan1/src/stm32_lcd_ssd1306.c | 2 +- .../b-l072z-lrwan1/src/stm32_spi.c | 2 +- .../b-l072z-lrwan1/src/stm32_sx127x.c | 2 +- boards/arm/stm32l0/common/CMakeLists.txt | 25 ++ boards/arm/stm32l0/common/Kconfig | 6 + boards/arm/stm32l0/common/Makefile | 38 ++ .../arm/stm32l0/nucleo-l073rz/CMakeLists.txt | 23 ++ .../nucleo-l073rz/Kconfig | 0 .../nucleo-l073rz/configs/nsh/defconfig | 2 +- .../nucleo-l073rz/configs/sx127x/defconfig | 2 +- .../nucleo-l073rz/include/board.h | 2 +- .../stm32l0/nucleo-l073rz/scripts/Make.defs | 41 ++ .../nucleo-l073rz/scripts/ld.script | 2 +- .../nucleo-l073rz/src/CMakeLists.txt | 2 +- .../nucleo-l073rz/src/Make.defs | 2 +- .../nucleo-l073rz/src/nucleo-l073rz.h | 2 +- .../nucleo-l073rz/src/stm32_autoleds.c | 2 +- .../nucleo-l073rz/src/stm32_boot.c | 2 +- .../nucleo-l073rz/src/stm32_bringup.c | 2 +- .../nucleo-l073rz/src/stm32_buttons.c | 2 +- .../nucleo-l073rz/src/stm32_mfrc522.c | 2 +- .../nucleo-l073rz/src/stm32_nrf24l01.c | 2 +- .../nucleo-l073rz/src/stm32_spi.c | 2 +- .../nucleo-l073rz/src/stm32_sx127x.c | 2 +- .../stm32l0/stm32l0538-disco/CMakeLists.txt | 23 ++ .../stm32l0538-disco/Kconfig | 0 .../stm32l0538-disco/configs/nsh/defconfig | 2 +- .../stm32l0538-disco/include/board.h | 2 +- .../stm32l0538-disco/scripts/Make.defs | 2 +- .../stm32l0538-disco/scripts/ld.script | 2 +- .../stm32l0538-disco/src/CMakeLists.txt | 2 +- .../stm32l0538-disco/src/Make.defs | 2 +- .../stm32l0538-disco/src/stm32_autoleds.c | 2 +- .../stm32l0538-disco/src/stm32_boot.c | 2 +- .../stm32l0538-disco/src/stm32_bringup.c | 2 +- .../stm32l0538-disco/src/stm32_buttons.c | 2 +- .../stm32l0538-disco/src/stm32l0538-disco.h | 2 +- 71 files changed, 1387 insertions(+), 113 deletions(-) create mode 100644 arch/arm/include/stm32l0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32l0_irq.h => stm32l0/irq.h} (76%) create mode 100644 arch/arm/src/stm32l0/CMakeLists.txt create mode 100644 arch/arm/src/stm32l0/Kconfig create mode 100644 arch/arm/src/stm32l0/Make.defs create mode 100644 arch/arm/src/stm32l0/chip.h create mode 100644 arch/arm/src/stm32l0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32l0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_exti.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_flash.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_pwr.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32l0}/hardware/stm32l0_syscfg.h (97%) create mode 100644 arch/arm/src/stm32l0/stm32.h create mode 100644 arch/arm/src/stm32l0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => stm32l0}/stm32l0_rcc.c (99%) create mode 100644 boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/adc/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/nxlines_oled/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/configs/sx127x/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/include/board.h (99%) create mode 100644 boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/b-l072z-lrwan1.h (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_adc.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/b-l072z-lrwan1/src/stm32_sx127x.c (99%) create mode 100644 boards/arm/stm32l0/common/CMakeLists.txt create mode 100644 boards/arm/stm32l0/common/Kconfig create mode 100644 boards/arm/stm32l0/common/Makefile create mode 100644 boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/configs/sx127x/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/include/board.h (99%) create mode 100644 boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/nucleo-l073rz.h (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_mfrc522.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_nrf24l01.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/nucleo-l073rz/src/stm32_sx127x.c (98%) create mode 100644 boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_boot.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_bringup.c (97%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32l0}/stm32l0538-disco/src/stm32l0538-disco.h (98%) diff --git a/arch/arm/include/stm32l0/chip.h b/arch/arm/include/stm32l0/chip.h new file mode 100644 index 00000000000..dcd81994546 --- /dev/null +++ b/arch/arm/include/stm32l0/chip.h @@ -0,0 +1,371 @@ +/**************************************************************************** + * arch/arm/include/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32L071K8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 2 /* 2 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 1 /* 1 LCD */ +# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ + defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* 1 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) +# define STM32_NATIM 0 /* 0 advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ + /* 1 LPTIMER */ +# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ +# define STM32_NI2S 0 /* 0 I2S module */ +# define STM32_NI2C 3 /* 3 I2C */ +# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ +# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ + /* 1 LPUART */ +# define STM32_NCAN 0 /* 0 CAN controllers */ +# define STM32_NLCD 0 /* 0 LCD */ +# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* 0 DAC channel */ +# define STM32_NCOMP 2 /* 2 Analog Comparators */ +# define STM32_NCRC 0 /* 0 CRC module */ +# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ +# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L072VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ + defined(CONFIG_ARCH_CHIP_STM32L073VZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module */ +# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 1 /* One LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h b/arch/arm/include/stm32l0/irq.h similarity index 76% rename from arch/arm/include/stm32f0l0g0/stm32l0_irq.h rename to arch/arm/include/stm32l0/irq.h index 166815ea7fa..93fe2b0e049 100644 --- a/arch/arm/include/stm32f0l0g0/stm32l0_irq.h +++ b/arch/arm/include/stm32l0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32l0_irq.h + * arch/arm/include/stm32l0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,34 +20,54 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. - * The IRQ number corresponds vector number and hence map directly to - * bits in the NVIC. This does, however, waste several words of memory in - * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions - * can be found in nuttx/arch/arm/include/stm32f0l0g0/irq.h +/* IRQ numbers. The IRQ number corresponds vector number and hence map + * directly to bits in the NVIC. This does, however, waste several words of + * memory in the IRQ to handle mapping tables. */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_EXTINT + 1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC global interrupt */ @@ -92,31 +112,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32L0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L0_IRQ_H */ diff --git a/arch/arm/src/stm32l0/CMakeLists.txt b/arch/arm/src/stm32l0/CMakeLists.txt new file mode 100644 index 00000000000..0b2c640ff2d --- /dev/null +++ b/arch/arm/src/stm32l0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32l0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l0/Kconfig b/arch/arm/src/stm32l0/Kconfig new file mode 100644 index 00000000000..6d71aebe758 --- /dev/null +++ b/arch/arm/src/stm32l0/Kconfig @@ -0,0 +1,273 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L0 configuration" + +if ARCH_CHIP_STM32L0 + +choice + prompt "ST STM32L0 Chip Selection" + default ARCH_CHIP_STM32L073RZ + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053C8 + bool "STM32L053C8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L053R8 + bool "STM32L053R8" + select ARCH_CHIP_STM32L053XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071K8 + bool "STM32L071K8" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KB + bool "STM32L071KB" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071KZ + bool "STM32L071KZ" + select ARCH_CHIP_STM32L071XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071C8 + bool "STM32L071C8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CB + bool "STM32L071CB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071CZ + bool "STM32L071CZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071V8 + bool "STM32L071V8" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VB + bool "STM32L071VB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071VZ + bool "STM32L071VZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RB + bool "STM32L071RB" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L071RZ + bool "STM32L071RZ" + select ARCH_CHIP_STM32L071XX + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072V8 + bool "STM32L072V8" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VB + bool "STM32L072VB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072VZ + bool "STM32L072VZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KB + bool "STM32L072KB" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072KZ + bool "STM32L072KZ" + select ARCH_CHIP_STM32L072XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CB + bool "STM32L072CB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072CZ + bool "STM32L072CZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RB + bool "STM32L072RB" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L072RZ + bool "STM32L072RZ" + select ARCH_CHIP_STM32L072XX + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C3 + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073V8 + bool "STM32L073V8" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VB + bool "STM32L073VB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073VZ + bool "STM32L073VZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CB + bool "STM32L073CB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073CZ + bool "STM32L073CZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RB + bool "STM32L073RB" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +config ARCH_CHIP_STM32L073RZ + bool "STM32L073RZ" + select ARCH_CHIP_STM32L073XX + depends on ARCH_CHIP_STM32L0 + +endchoice + +endif + +config STM32_STM32L0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_ENERGYLITE + select STM32_HAVE_LCD + select STM32_HAVE_VREFINT + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKP + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_M0_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_HSI48_M0_V1 if STM32_HAVE_HSI48 + +config ARCH_CHIP_STM32L053XX + bool + select STM32_STM32L0 + +config ARCH_CHIP_STM32L071XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + +config ARCH_CHIP_STM32L072XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_I2C2 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32L073XX + bool + select STM32_STM32L0 + select STM32_HAVE_RNG + select STM32_HAVE_HSI48 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_USBDEV + +config STM32_FLASH_OVERRIDE + bool "Override Flash Designator" + default n diff --git a/arch/arm/src/stm32l0/Make.defs b/arch/arm/src/stm32l0/Make.defs new file mode 100644 index 00000000000..41ee69999f4 --- /dev/null +++ b/arch/arm/src/stm32l0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32l0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32l0/chip.h b/arch/arm/src/stm32l0/chip.h new file mode 100644 index 00000000000..f5e1ecde93e --- /dev/null +++ b/arch/arm/src/stm32l0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_CHIP_H +#define __ARCH_ARM_SRC_STM32L0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_CHIP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..44f335487ab --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l0/hardware/stm32_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..680c386947b --- /dev/null +++ b/arch/arm/src/stm32l0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h rename to arch/arm/src/stm32l0/hardware/stm32l0_exti.h index 4f246ccd8f7..dea6972eae5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_exti.h + * arch/arm/src/stm32l0/hardware/stm32l0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H /**************************************************************************** * Included Files @@ -116,4 +116,4 @@ #define EXTI_PR_SHIFT (0) /* Bits 0-X: Pending bit for all lines */ #define EXTI_PR_MASK STM32_EXTI_MASK -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h rename to arch/arm/src/stm32l0/hardware/stm32l0_flash.h index 489d8588f18..2f22a50f7f8 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_flash.h + * arch/arm/src/stm32l0/hardware/stm32l0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H /**************************************************************************** * Included Files @@ -102,4 +102,4 @@ #define FLASH_SR_OPTVERRUSR (1 << 12) /* Bit 12: Option UserValidity Error */ #define FLASH_SR_RDERR (1 << 13) /* Bit 13: Read protected error */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h index 30da782402d..dfdb2b3c4bc 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_memorymap.h + * arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -118,4 +118,4 @@ #define STM32_SYSMEM_UID 0x1ff80050 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h index a47d0df7245..9e18b9be9ab 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pinmap.h + * arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H /**************************************************************************** * Included Files @@ -326,4 +326,4 @@ /* TODO: LPUART */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h rename to arch/arm/src/stm32l0/hardware/stm32l0_pwr.h index b5c00fa05e0..9f98c41d294 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h + * arch/arm/src/stm32l0/hardware/stm32l0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H /**************************************************************************** * Included Files @@ -91,4 +91,4 @@ #define PWR_CSR_EWUP2 (1 << 9) /* Bit 9: Enable WKUP2 pin */ #define PWR_CSR_EWUP3 (1 << 10) /* Bit 10: Enable WKUP3 pin */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h rename to arch/arm/src/stm32l0/hardware/stm32l0_rcc.h index 42a19e50100..1b924ce6870 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_rcc.h + * arch/arm/src/stm32l0/hardware/stm32l0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -538,4 +538,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h rename to arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h index 85d28dc0ce9..e3dd1bf7159 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h +++ b/arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32l0_syscfg.h + * arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H /**************************************************************************** * Included Files @@ -132,4 +132,4 @@ #define SYSCFG_EXTICR4_EXTI15_SHIFT (12) /* Bits 12-15: EXTI 15 configuration */ #define SYSCFG_EXTICR4_EXTI15_MASK (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32L0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32L0_HARDWARE_STM32L0_SYSCFG_H */ diff --git a/arch/arm/src/stm32l0/stm32.h b/arch/arm/src/stm32l0/stm32.h new file mode 100644 index 00000000000..cdcdb2d4aa7 --- /dev/null +++ b/arch/arm/src/stm32l0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L0_STM32_H +#define __ARCH_ARM_SRC_STM32L0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32L0_STM32_H */ diff --git a/arch/arm/src/stm32l0/stm32_rcc.c b/arch/arm/src/stm32l0/stm32_rcc.c new file mode 100644 index 00000000000..a41366fdfeb --- /dev/null +++ b/arch/arm/src/stm32l0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32l0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c b/arch/arm/src/stm32l0/stm32l0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32l0_rcc.c rename to arch/arm/src/stm32l0/stm32l0_rcc.c index 6e7b9a92f9d..79359bb30bf 100644 --- a/arch/arm/src/stm32f0l0g0/stm32l0_rcc.c +++ b/arch/arm/src/stm32l0/stm32l0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32l0_rcc.c + * arch/arm/src/stm32l0/stm32l0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt new file mode 100644 index 00000000000..f474a7db2a1 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/b-l072z-lrwan1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig b/boards/arm/stm32l0/b-l072z-lrwan1/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/Kconfig diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig index faac0bde227..016388d1db9 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/adc/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig @@ -11,7 +11,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig index b51bbbb4f4a..f8dc57d2784 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nsh/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig index 6be6bf998c4..b2c85a1eebb 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/nxlines_oled/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig rename to boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig index cfe38151ba5..1f5723aba0a 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/configs/sx127x/defconfig +++ b/boards/arm/stm32l0/b-l072z-lrwan1/configs/sx127x/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-l072z-lrwan1" CONFIG_ARCH_BOARD_B_L072Z_LRWAN1=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L072CZ=y CONFIG_ARCH_CHIP_STM32L072XX=y diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h rename to boards/arm/stm32l0/b-l072z-lrwan1/include/board.h index 95e19a5a6c2..2029f595402 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/include/board.h + * boards/arm/stm32l0/b-l072z-lrwan1/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs new file mode 100644 index 00000000000..74fc513e986 --- /dev/null +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/b-l072z-lrwan1/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script rename to boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script index c95d535e86d..1c6f4b40e82 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script +++ b/boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/ld.script + * boards/arm/stm32l0/b-l072z-lrwan1/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt rename to boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt index 4770af26d5f..3c1bf3c65f3 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/CMakeLists.txt +# boards/arm/stm32l0/b-l072z-lrwan1/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs rename to boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs index 55c1d27f870..0ef4cef9f33 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/Make.defs +# boards/arm/stm32l0/b-l072z-lrwan1/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h rename to boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h index 81c81c06f1d..dfbc614c322 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/b-l072z-lrwan1.h + * boards/arm/stm32l0/b-l072z-lrwan1/src/b-l072z-lrwan1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c index 36d2d48f60e..593a484fd83 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_adc.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c index c71e5764e6e..1b0b8cd55b3 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_autoleds.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c index ce025e3b964..aad79dbb41f 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_boot.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c index 152c4cc463c..c3935c1ff16 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_bringup.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c index dcdae68aef2..9644213f066 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c index 7b42fb7e3ce..368df13bf05 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_spi.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c similarity index 99% rename from boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c rename to boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c index 32e9e675406..e6ffc468139 100644 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c +++ b/boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/b-l072z-lrwan1/src/stm32_sx127x.c + * boards/arm/stm32l0/b-l072z-lrwan1/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/common/CMakeLists.txt b/boards/arm/stm32l0/common/CMakeLists.txt new file mode 100644 index 00000000000..8ee0b83c1a4 --- /dev/null +++ b/boards/arm/stm32l0/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32l0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32l0/common/Kconfig b/boards/arm/stm32l0/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32l0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32l0/common/Makefile b/boards/arm/stm32l0/common/Makefile new file mode 100644 index 00000000000..56d7a1f9086 --- /dev/null +++ b/boards/arm/stm32l0/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32l0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt new file mode 100644 index 00000000000..d660ec8525f --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/nucleo-l073rz/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig b/boards/arm/stm32l0/nucleo-l073rz/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig rename to boards/arm/stm32l0/nucleo-l073rz/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig rename to boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig index 9633c3b48c0..d4ddb1d55dd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/nsh/defconfig +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig rename to boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig index 38cc3a0d14e..32220b19127 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/configs/sx127x/defconfig +++ b/boards/arm/stm32l0/nucleo-l073rz/configs/sx127x/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l073rz" CONFIG_ARCH_BOARD_NUCLEO_L073RZ=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L073RZ=y CONFIG_ARCH_CHIP_STM32L073XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h b/boards/arm/stm32l0/nucleo-l073rz/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h rename to boards/arm/stm32l0/nucleo-l073rz/include/board.h index d24c64eaaf4..af284ca168e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h +++ b/boards/arm/stm32l0/nucleo-l073rz/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/include/board.h + * boards/arm/stm32l0/nucleo-l073rz/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs new file mode 100644 index 00000000000..596e9665da7 --- /dev/null +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32l0/nucleo-l073rz/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script rename to boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script index e0da80b38d5..2156f68042f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script +++ b/boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/ld.script + * boards/arm/stm32l0/nucleo-l073rz/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt rename to boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt index ac95ed5c073..b70c2615c82 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +++ b/boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/CMakeLists.txt +# boards/arm/stm32l0/nucleo-l073rz/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs rename to boards/arm/stm32l0/nucleo-l073rz/src/Make.defs index ff5d2d230eb..f2967390346 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +++ b/boards/arm/stm32l0/nucleo-l073rz/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/src/Make.defs +# boards/arm/stm32l0/nucleo-l073rz/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h rename to boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h index 90410fded75..f72a20312f5 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h +++ b/boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/nucleo-l073rz.h + * boards/arm/stm32l0/nucleo-l073rz/src/nucleo-l073rz.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c index 2f06c37702f..ffe74f73f87 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_autoleds.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c index a08ebff3930..8ee936849c3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_boot.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c index 35e5ae85e28..3a573ba1c8d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_bringup.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c index 6fee37bc6e0..5f59392762a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_buttons.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c index 2481cdfb428..4cbc3ee003c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_mfrc522.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_mfrc522.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c index b8bb669ff79..4b3e1311e58 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_nrf24l01.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_nrf24l01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c index a9495e3544c..3daa7531191 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_spi.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c rename to boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c index a5786872108..1893e179735 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c +++ b/boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-l073rz/src/stm32_sx127x.c + * boards/arm/stm32l0/nucleo-l073rz/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt new file mode 100644 index 00000000000..32e681f9f1b --- /dev/null +++ b/boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32l0/stm32l0538-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig b/boards/arm/stm32l0/stm32l0538-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig rename to boards/arm/stm32l0/stm32l0538-disco/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig rename to boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig index ce9e752caa6..7a823b72968 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32l0538-disco" CONFIG_ARCH_BOARD_STM32L0538_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32l0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L053C8=y CONFIG_ARCH_CHIP_STM32L053XX=y diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h b/boards/arm/stm32l0/stm32l0538-disco/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h rename to boards/arm/stm32l0/stm32l0538-disco/include/board.h index 5cc344752dc..f1ba04878c6 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h +++ b/boards/arm/stm32l0/stm32l0538-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/include/board.h + * boards/arm/stm32l0/stm32l0538-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs rename to boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs index 5417678c0ce..5a209945f33 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/Make.defs +# boards/arm/stm32l0/stm32l0538-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script rename to boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script index 3ab8df515ea..9eb309a0097 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script +++ b/boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/scripts/ld.script + * boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt rename to boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt index 2d3a59a01db..7819e8f7226 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt +++ b/boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/CMakeLists.txt +# boards/arm/stm32l0/stm32l0538-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs rename to boards/arm/stm32l0/stm32l0538-disco/src/Make.defs index 502d059a105..6d6fb20db57 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs +++ b/boards/arm/stm32l0/stm32l0538-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32l0538-disco/src/Make.defs +# boards/arm/stm32l0/stm32l0538-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c index b7564b91312..9e28a2427ef 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_autoleds.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c index b760b793943..b3a0d820c48 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_boot.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c index c4907ef7ac8..1bc7e9a74e6 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_bringup.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c index f6cff70cb19..73295823d91 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32_buttons.c + * boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h similarity index 98% rename from boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h rename to boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h index 34b45f2a994..38e14d22f82 100644 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h +++ b/boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32l0538-disco/src/stm32l0538-disco.h + * boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h * * SPDX-License-Identifier: Apache-2.0 * From 6d6bcbfcbaa3c0073551ddc9b90fed2aaf78c178 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:43:32 +0200 Subject: [PATCH 153/268] !arch/stm32f0l0g0: move stm32g0 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32g0 sources, headers and boards into arch/arm/src/stm32g0, arch/arm/include/stm32g0 and boards/arm/stm32g0. Signed-off-by: raiden00pl --- arch/arm/include/stm32g0/chip.h | 166 +++++++ .../stm32g0_irq.h => stm32g0/irq.h} | 76 ++- arch/arm/src/stm32g0/CMakeLists.txt | 32 ++ arch/arm/src/stm32g0/Kconfig | 434 ++++++++++++++++++ arch/arm/src/stm32g0/Make.defs | 31 ++ arch/arm/src/stm32g0/chip.h | 44 ++ .../src/stm32g0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32g0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32g0_dmamux.h | 8 +- .../hardware/stm32g0_exti.h | 8 +- .../hardware/stm32g0_flash.h | 8 +- .../hardware/stm32g0_memorymap.h | 8 +- .../hardware/stm32g0_pinmap.h | 8 +- .../hardware/stm32g0_pwr.h | 8 +- .../hardware/stm32g0_rcc.h | 8 +- .../hardware/stm32g0_syscfg.h | 8 +- arch/arm/src/stm32g0/stm32.h | 54 +++ arch/arm/src/stm32g0/stm32_rcc.c | 220 +++++++++ .../{stm32f0l0g0 => stm32g0}/stm32g0_rcc.c | 2 +- boards/arm/stm32g0/common/CMakeLists.txt | 25 + boards/arm/stm32g0/common/Kconfig | 6 + boards/arm/stm32g0/common/Makefile | 38 ++ .../arm/stm32g0/nucleo-g070rb/CMakeLists.txt | 23 + .../nucleo-g070rb/Kconfig | 0 .../nucleo-g070rb/configs/nsh/defconfig | 2 +- .../nucleo-g070rb/include/board.h | 2 +- .../nucleo-g070rb}/scripts/Make.defs | 2 +- .../nucleo-g070rb/scripts/ld.script | 2 +- .../nucleo-g070rb/src/CMakeLists.txt | 2 +- .../nucleo-g070rb/src/Make.defs | 2 +- .../nucleo-g070rb/src/nucleo-g070rb.h | 2 +- .../nucleo-g070rb/src/stm32_autoleds.c | 2 +- .../nucleo-g070rb/src/stm32_boot.c | 2 +- .../nucleo-g070rb/src/stm32_bringup.c | 2 +- .../nucleo-g070rb/src/stm32_buttons.c | 2 +- .../nucleo-g070rb/src/stm32_gpio.c | 2 +- .../nucleo-g070rb/src/stm32_pwm.c | 2 +- .../nucleo-g070rb/src/stm32_timer.c | 2 +- .../arm/stm32g0/nucleo-g071rb/CMakeLists.txt | 23 + .../nucleo-g071rb/Kconfig | 0 .../nucleo-g071rb/configs/nsh/defconfig | 2 +- .../nucleo-g071rb/include/board.h | 2 +- .../nucleo-g071rb/scripts/Make.defs | 2 +- .../nucleo-g071rb/scripts/ld.script | 2 +- .../nucleo-g071rb/src/CMakeLists.txt | 2 +- .../nucleo-g071rb/src/Make.defs | 2 +- .../nucleo-g071rb/src/nucleo-g071rb.h | 2 +- .../nucleo-g071rb/src/stm32_autoleds.c | 2 +- .../nucleo-g071rb/src/stm32_boot.c | 2 +- .../nucleo-g071rb/src/stm32_bringup.c | 2 +- .../nucleo-g071rb/src/stm32_buttons.c | 2 +- .../arm/stm32g0/nucleo-g0b1re/CMakeLists.txt | 23 + .../nucleo-g0b1re/Kconfig | 0 .../nucleo-g0b1re/configs/adc/defconfig | 2 +- .../nucleo-g0b1re/configs/adc_dma/defconfig | 2 +- .../nucleo-g0b1re/configs/nsh/defconfig | 2 +- .../nucleo-g0b1re/include/board.h | 2 +- .../nucleo-g0b1re/scripts/Make.defs | 2 +- .../nucleo-g0b1re/scripts/ld.script | 2 +- .../nucleo-g0b1re/src/CMakeLists.txt | 2 +- .../nucleo-g0b1re/src/Make.defs | 2 +- .../nucleo-g0b1re/src/nucleo-g0b1re.h | 2 +- .../nucleo-g0b1re/src/stm32_adc.c | 2 +- .../nucleo-g0b1re/src/stm32_autoleds.c | 2 +- .../nucleo-g0b1re/src/stm32_boot.c | 2 +- .../nucleo-g0b1re/src/stm32_bringup.c | 2 +- .../nucleo-g0b1re/src/stm32_buttons.c | 2 +- .../stm32g0/stm32g071b-disco/CMakeLists.txt | 23 + .../stm32g071b-disco/Kconfig | 0 .../stm32g071b-disco/configs/nsh/defconfig | 2 +- .../stm32g071b-disco/configs/oled/defconfig | 2 +- .../stm32g071b-disco/include/board.h | 2 +- .../stm32g071b-disco}/scripts/Make.defs | 2 +- .../stm32g071b-disco/scripts/ld.script | 2 +- .../stm32g071b-disco/src/CMakeLists.txt | 2 +- .../stm32g071b-disco/src/Make.defs | 2 +- .../stm32g071b-disco/src/stm32_boot.c | 2 +- .../stm32g071b-disco/src/stm32_bringup.c | 2 +- .../stm32g071b-disco/src/stm32_djoystick.c | 2 +- .../stm32g071b-disco/src/stm32_gpio.c | 2 +- .../stm32g071b-disco/src/stm32_ina226.c | 2 +- .../stm32g071b-disco/src/stm32_lcd_ssd1306.c | 2 +- .../stm32g071b-disco/src/stm32_spi.c | 2 +- .../stm32g071b-disco/src/stm32_userleds.c | 2 +- .../stm32g071b-disco/src/stm32g071b-disco.h | 2 +- 85 files changed, 1296 insertions(+), 132 deletions(-) create mode 100644 arch/arm/include/stm32g0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32g0_irq.h => stm32g0/irq.h} (85%) create mode 100644 arch/arm/src/stm32g0/CMakeLists.txt create mode 100644 arch/arm/src/stm32g0/Kconfig create mode 100644 arch/arm/src/stm32g0/Make.defs create mode 100644 arch/arm/src/stm32g0/chip.h create mode 100644 arch/arm/src/stm32g0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32g0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_dmamux.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_exti.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_flash.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_pwr.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32g0}/hardware/stm32g0_syscfg.h (98%) create mode 100644 arch/arm/src/stm32g0/stm32.h create mode 100644 arch/arm/src/stm32g0/stm32_rcc.c rename arch/arm/src/{stm32f0l0g0 => stm32g0}/stm32g0_rcc.c (99%) create mode 100644 boards/arm/stm32g0/common/CMakeLists.txt create mode 100644 boards/arm/stm32g0/common/Kconfig create mode 100644 boards/arm/stm32g0/common/Makefile create mode 100644 boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/configs/nsh/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/include/board.h (99%) rename boards/arm/{stm32f0l0g0/nucleo-l073rz => stm32g0/nucleo-g070rb}/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/nucleo-g070rb.h (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_gpio.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_pwm.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g070rb/src/stm32_timer.c (98%) create mode 100644 boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/nucleo-g071rb.h (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g071rb/src/stm32_buttons.c (98%) create mode 100644 boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/configs/adc/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/configs/adc_dma/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/include/board.h (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/nucleo-g0b1re.h (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/stm32_adc.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/nucleo-g0b1re/src/stm32_buttons.c (98%) create mode 100644 boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/configs/nsh/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/configs/oled/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/include/board.h (99%) rename boards/arm/{stm32f0l0g0/nucleo-g070rb => stm32g0/stm32g071b-disco}/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/scripts/ld.script (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_djoystick.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_gpio.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_ina226.c (98%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_lcd_ssd1306.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_spi.c (99%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32_userleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32g0}/stm32g071b-disco/src/stm32g071b-disco.h (99%) diff --git a/arch/arm/include/stm32g0/chip.h b/arch/arm/include/stm32g0/chip.h new file mode 100644 index 00000000000..4c92e149ced --- /dev/null +++ b/arch/arm/include/stm32g0/chip.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/include/stm32g0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G070RB) + +# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ +# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, + * TIM14-17 */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ +# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 0 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 16-channels */ + +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ + defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ + defined(CONFIG_ARCH_CHIP_STM32G071RB) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 + * (with DMA) and TIM21-22 without DMA */ +# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* Two LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 1 /* One DMA1, 7-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ + /* One LPUART */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 2 /* Two Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ + defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) + +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ +# define STM32_NGTIM32 1 /* TIM2 */ +# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ + /* One LPTIMER */ +# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ +# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ +# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ +# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ + /* Two LPUART */ +# define STM32_NCAN 1 /* One FDCAN controller */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBDEV 1 /* One USB full-speed controller */ +# define STM32_NUSBOTG 0 /* No USB OTG */ +# define STM32_NCEC 1 /* One HDMI-CEC controller */ +# define STM32_NADC 1 /* (1) ADC1, 12-channels */ + +# define STM32_NDAC 2 /* Two DAC channels */ +# define STM32_NCOMP 3 /* Three Analog Comparators */ +# define STM32_NCRC 0 /* No CRC module */ +# define STM32_NRNG 1 /* One Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L073XX - With LCD + * STM32L072XX - No LCD + * STM32L071XX - Access line, no LCD + * + * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM + * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM + * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM + * + * STM32L0XXCX - 48-pins + * STM32L0XXRX - 64-pins + * STM32L0XXVX - 100-pins + */ + +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h b/arch/arm/include/stm32g0/irq.h similarity index 85% rename from arch/arm/include/stm32f0l0g0/stm32g0_irq.h rename to arch/arm/include/stm32g0/irq.h index ae5e5a29194..1edbcd2b850 100644 --- a/arch/arm/include/stm32f0l0g0/stm32g0_irq.h +++ b/arch/arm/include/stm32g0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32g0_irq.h + * arch/arm/include/stm32g0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32G0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ @@ -94,8 +115,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_COMP */ - #else # define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */ #endif @@ -115,10 +134,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_DAC */ - -/* No STM32_IRQ_LPTIM1 */ - #else # define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */ # define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */ @@ -128,8 +143,6 @@ #if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ defined(CONFIG_ARCH_CHIP_STM32G070RB) -/* No STM32_IRQ_LPTIM2 */ - #else # define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */ #endif @@ -165,31 +178,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32G0_IRQ_H */ diff --git a/arch/arm/src/stm32g0/CMakeLists.txt b/arch/arm/src/stm32g0/CMakeLists.txt new file mode 100644 index 00000000000..d2d126dda46 --- /dev/null +++ b/arch/arm/src/stm32g0/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# arch/arm/src/stm32g0/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g0/Kconfig b/arch/arm/src/stm32g0/Kconfig new file mode 100644 index 00000000000..de97aaf4f30 --- /dev/null +++ b/arch/arm/src/stm32g0/Kconfig @@ -0,0 +1,434 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G0 configuration" + +if ARCH_CHIP_STM32G0 + +choice + prompt "ST STM32G0 Chip Selection" + default ARCH_CHIP_STM32G071RB + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070CB + bool "STM32G070CB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070KB + bool "STM32G070KB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G070RB + bool "STM32G070RB" + select STM32_STM32G070 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071EB + bool "STM32G071EB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8 + bool "STM32G071G8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GB + bool "STM32G071GB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071G8XN + bool "STM32G071G8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071GBXN + bool "STM32G071GBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8 + bool "STM32G071K8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KB + bool "STM32G071KB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071K8XN + bool "STM32G071K8XN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071KBXN + bool "STM32G071KBXN" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071C8 + bool "STM32G071C8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071CB + bool "STM32G071CB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071R8 + bool "STM32G071R8" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_8 + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G071RB + bool "STM32G071RB" + select STM32_STM32G071 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KB + bool "STM32G0B1KB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CB + bool "STM32G0B1CB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RB + bool "STM32G0B1RB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MB + bool "STM32G0B1MB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VB + bool "STM32G0B1VB" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_B + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KC + bool "STM32G0B1KC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CC + bool "STM32G0B1CC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RC + bool "STM32G0B1RC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1MC + bool "STM32G0B1MC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VC + bool "STM32G0B1VC" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_C + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1KE + bool "STM32G0B1KE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1CE + bool "STM32G0B1CE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1RE + bool "STM32G0B1RE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1NE + bool "STM32G0B1NE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1ME + bool "STM32G0B1ME" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +config ARCH_CHIP_STM32G0B1VE + bool "STM32G0B1VE" + select STM32_STM32G0B1 + select STM32_FLASH_CONFIG_E + depends on ARCH_CHIP_STM32G0 + +endchoice + +endif + +config STM32_STM32G0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKP + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_I2C2 + select ARCH_HAVE_PROGMEM + +config STM32_STM32G030 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + +config STM32_STM32G031 + bool + default n + select STM32_STM32G0 + select STM32_STM32G03X + select STM32_HAVE_LPUART1 + +config STM32_STM32G03X + bool + default n + +config STM32_STM32G041 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_LPUART1 + +config STM32_STM32G050 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + +config STM32_STM32G051 + bool + default n + select STM32_STM32G0 + select STM32_STM32G05X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G05X + bool + default n + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + +config STM32_STM32G061 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_LPUART1 + +config STM32_STM32G070 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + +config STM32_STM32G071 + bool + default n + select STM32_STM32G0 + select STM32_STM32G07X + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G07X + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + +config STM32_STM32G081 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_CEC + select STM32_HAVE_LPUART1 + +config STM32_STM32G0B0 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + +config STM32_STM32G0B1 + bool + default n + select STM32_STM32G0 + select STM32_STM32G0BX + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + +config STM32_STM32G0BX + bool + default n + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_LPUART1 + select STM32_HAVE_LPUART2 + select STM32_HAVE_CRS + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_HSI48 + +config STM32_STM32G0C1 + bool + default n + select STM32_STM32G0 + select STM32_HAVE_DMA2 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_USART5 + select STM32_HAVE_USART6 + select STM32_HAVE_CRS + select STM32_HAVE_RNG + select STM32_HAVE_AES + select STM32_HAVE_DAC1 + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S2 + select STM32_HAVE_LPUART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_UCPD1 + select STM32_HAVE_UCPD2 + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_CEC + select STM32_HAVE_HSI48 diff --git a/arch/arm/src/stm32g0/Make.defs b/arch/arm/src/stm32g0/Make.defs new file mode 100644 index 00000000000..75f1a3a88a8 --- /dev/null +++ b/arch/arm/src/stm32g0/Make.defs @@ -0,0 +1,31 @@ +############################################################################ +# arch/arm/src/stm32g0/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv6-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += stm32_userspace.c +endif + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32g0/chip.h b/arch/arm/src/stm32g0/chip.h new file mode 100644 index 00000000000..1569d0603c7 --- /dev/null +++ b/arch/arm/src/stm32g0/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_CHIP_H +#define __ARCH_ARM_SRC_STM32G0_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "nvic.h" + +/* Include the chip capabilities file */ + +#include + +/* Include the memory map file. + * Other chip hardware files should then include this file for the proper + * setup. + */ + +#include "hardware/stm32_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_CHIP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..cd95640e9a6 --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g0/hardware/stm32_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..56faffa2e66 --- /dev/null +++ b/arch/arm/src/stm32g0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h rename to arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h index 2f1161c7d37..d8ac7f51795 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_dmamux.h + * arch/arm/src/stm32g0/hardware/stm32g0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H /**************************************************************************** * Included Files @@ -322,4 +322,4 @@ #define DMAMUX_SYNC_LPTIM2_OUT 21 #define DMAMUX_SYNC_TIM14_OC 22 -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h rename to arch/arm/src/stm32g0/hardware/stm32g0_exti.h index bfbd8802918..695a57836a5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_exti.h + * arch/arm/src/stm32g0/hardware/stm32g0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h rename to arch/arm/src/stm32g0/hardware/stm32g0_flash.h index 5d5780116bf..779011abd83 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_flash.h + * arch/arm/src/stm32g0/hardware/stm32g0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H /**************************************************************************** * Included Files @@ -279,4 +279,4 @@ #define FLASH_SECR_SEC_SIZE2_MASK (0xff << FLASH_SECR_SEC_SIZE2_SHIFT) /* Bits 28-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h index 595e1886b4c..c5455b4df97 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_memorymap.h + * arch/arm/src/stm32g0/hardware/stm32g0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -131,4 +131,4 @@ #define STM32_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h index efbb5415b74..3cc3b5b0850 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h + * arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Gregory Nutt. All rights reserved. @@ -36,8 +36,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H /**************************************************************************** * Included Files @@ -283,4 +283,4 @@ /* TODO: CEC */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h rename to arch/arm/src/stm32g0/hardware/stm32g0_pwr.h index ae226f9fca6..2df357db170 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h + * arch/arm/src/stm32g0/hardware/stm32g0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H /**************************************************************************** * Included Files @@ -175,4 +175,4 @@ #define PWR_SCR_CWUF5 (1 << 4) /* Bit 4: Clear wakeup flag 5 */ #define PWR_SCR_CSBF (1 << 8) /* Bit 8: Clear standby flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h rename to arch/arm/src/stm32g0/hardware/stm32g0_rcc.h index 940cb9e6ba2..3c5f8ca4521 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_rcc.h + * arch/arm/src/stm32g0/hardware/stm32g0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -363,4 +363,4 @@ #define RCC_CSR_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h rename to arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h index cb4f9bb9c39..7ca1ecbbce1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h +++ b/arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32g0_syscfg.h + * arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H +#ifndef __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H +#define __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H /**************************************************************************** * Included Files @@ -300,4 +300,4 @@ #define SYSCFG_ITLINE30_RNG (1 << 0) /* Bit 0: RNG interrupt request pending */ #define SYSCFG_ITLINE30_AES (1 << 1) /* Bit 1: AES interrupt request pending */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32G0_SYSCFG_H */ +#endif /* __ARCH_ARM_SRC_STM32G0_HARDWARE_STM32G0_SYSCFG_H */ diff --git a/arch/arm/src/stm32g0/stm32.h b/arch/arm/src/stm32g0/stm32.h new file mode 100644 index 00000000000..9e70f1bf95f --- /dev/null +++ b/arch/arm/src/stm32g0/stm32.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G0_STM32_H +#define __ARCH_ARM_SRC_STM32G0_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_spi.h" +#include "stm32_uart.h" +#include "stm32_lowputc.h" +#include "stm32_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_STM32G0_STM32_H */ diff --git a/arch/arm/src/stm32g0/stm32_rcc.c b/arch/arm/src/stm32g0/stm32_rcc.c new file mode 100644 index 00000000000..f2f084012f8 --- /dev/null +++ b/arch/arm/src/stm32g0/stm32_rcc.c @@ -0,0 +1,220 @@ +/**************************************************************************** + * arch/arm/src/stm32g0/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "hardware/stm32_flash.h" +#include "stm32_rcc.h" +#include "stm32_hsi48_m0_v1.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_STM32_RNG +# ifndef STM32_USE_CLK48 +# error RNG requires CLK48 enabled +# endif +#endif + +#ifdef CONFIG_STM32_USB +# ifndef STM32_USE_CLK48 +# error USB requires CLK48 enabled +# endif +#endif + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g0_rcc.c" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already configured + * LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings in + * board.h. This function is only available to support low-power modes of + * operation: When re-awakening from deep-sleep modes, it is necessary to + * re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then + * clocking will be enabled by an externally provided, board-specific + * function called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c b/arch/arm/src/stm32g0/stm32g0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32g0_rcc.c rename to arch/arm/src/stm32g0/stm32g0_rcc.c index 8933230be5f..b79a0224392 100644 --- a/arch/arm/src/stm32f0l0g0/stm32g0_rcc.c +++ b/arch/arm/src/stm32g0/stm32g0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32g0_rcc.c + * arch/arm/src/stm32g0/stm32g0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/common/CMakeLists.txt b/boards/arm/stm32g0/common/CMakeLists.txt new file mode 100644 index 00000000000..929a4d5fd28 --- /dev/null +++ b/boards/arm/stm32g0/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32g0/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32g0/common/Kconfig b/boards/arm/stm32g0/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32g0/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g0/common/Makefile b/boards/arm/stm32g0/common/Makefile new file mode 100644 index 00000000000..c0ed3475cba --- /dev/null +++ b/boards/arm/stm32g0/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32g0/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt new file mode 100644 index 00000000000..f505090d81c --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g070rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig b/boards/arm/stm32g0/nucleo-g070rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig rename to boards/arm/stm32g0/nucleo-g070rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig index 5381c3dce05..f78e5a4b951 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g070rb/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g070rb" CONFIG_ARCH_BOARD_NUCLEO_G070RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G070RB=y CONFIG_ARCH_CHIP_STM32G0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h b/boards/arm/stm32g0/nucleo-g070rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h rename to boards/arm/stm32g0/nucleo-g070rb/include/board.h index 5e09c65d50a..2a65558b105 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h +++ b/boards/arm/stm32g0/nucleo-g070rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/include/board.h + * boards/arm/stm32g0/nucleo-g070rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs index 0f50dc2d96b..2e92c773e09 100644 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-l073rz/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g070rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script index 3eddc960eb9..96714a97dd6 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/ld.script + * boards/arm/stm32g0/nucleo-g070rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt index 08d07dd22c1..cea0f3cd6a3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g070rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs rename to boards/arm/stm32g0/nucleo-g070rb/src/Make.defs index 3fcfafcf17f..e7b3454bb32 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g070rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/src/Make.defs +# boards/arm/stm32g0/nucleo-g070rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h rename to boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h index c48523c4184..7db19ce4ced 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h +++ b/boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/nucleo-g070rb.h + * boards/arm/stm32g0/nucleo-g070rb/src/nucleo-g070rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c index b96b3795bd0..185304a6903 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c index 5fc389ad066..c5fbfbc3047 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c index 975cd5aeb1c..8ca8dd171b8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c index 9bd12c84dfa..4b711729ba8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c index ecd0da7f944..d414c7c3e05 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c index b81ff3aa9b6..cfcbef9088a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c rename to boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c index 9442536d35f..886e6f72ca0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +++ b/boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c + * boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: Fundação CERTI. All rights reserved. diff --git a/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt new file mode 100644 index 00000000000..4d11fab0a18 --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g071rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig b/boards/arm/stm32g0/nucleo-g071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig rename to boards/arm/stm32g0/nucleo-g071rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig index 8960d71e898..fd83983a8e0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g071rb/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g071rb" CONFIG_ARCH_BOARD_NUCLEO_G071RB=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h b/boards/arm/stm32g0/nucleo-g071rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h rename to boards/arm/stm32g0/nucleo-g071rb/include/board.h index a6bba4ae7d9..bf18ab683b9 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h +++ b/boards/arm/stm32g0/nucleo-g071rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/include/board.h + * boards/arm/stm32g0/nucleo-g071rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs index e7c7c7f21af..dfc69a1d5bf 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g071rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script index b545dc383e7..9ea7803e49a 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/scripts/ld.script + * boards/arm/stm32g0/nucleo-g071rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt index b0e6eae77fb..4a054473a96 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g071rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs rename to boards/arm/stm32g0/nucleo-g071rb/src/Make.defs index 75e78e8bc72..3fa2cd2f85f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g071rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g071rb/src/Make.defs +# boards/arm/stm32g0/nucleo-g071rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h rename to boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h index 32e9d86e5fb..cda374f9f43 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h +++ b/boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/nucleo-g071rb.h + * boards/arm/stm32g0/nucleo-g071rb/src/nucleo-g071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c index e0c9af572f4..38287bbc4a1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c index 14706cd0ce5..5f891341e72 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c index cea5f3eab4e..d36512d8e58 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c index a8f45768364..881950a0dbc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g071rb/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g071rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt new file mode 100644 index 00000000000..7acee0b7fed --- /dev/null +++ b/boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/nucleo-g0b1re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig b/boards/arm/stm32g0/nucleo-g0b1re/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig rename to boards/arm/stm32g0/nucleo-g0b1re/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig index afc8179b09e..c72cc65d0a7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc/defconfig @@ -11,7 +11,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig index 2cffd2d94c1..6b0f6cd7c32 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/adc_dma/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/adc_dma/defconfig @@ -12,7 +12,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig rename to boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig index e093b5b2a67..05e08970e6c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/configs/nsh/defconfig +++ b/boards/arm/stm32g0/nucleo-g0b1re/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g0b1re" CONFIG_ARCH_BOARD_NUCLEO_G0B1RE=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G0=y CONFIG_ARCH_CHIP_STM32G0B1RE=y diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h rename to boards/arm/stm32g0/nucleo-g0b1re/include/board.h index 03888c49925..6120aad294e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h +++ b/boards/arm/stm32g0/nucleo-g0b1re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/include/board.h + * boards/arm/stm32g0/nucleo-g0b1re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs rename to boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs index 4f7c125818c..5090b0ed960 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/Make.defs +# boards/arm/stm32g0/nucleo-g0b1re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script rename to boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script index efe5f8f915e..0010b524154 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script +++ b/boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/scripts/ld.script + * boards/arm/stm32g0/nucleo-g0b1re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt rename to boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt index 031e1fc9f43..e7835f86dd8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/CMakeLists.txt +# boards/arm/stm32g0/nucleo-g0b1re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs rename to boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs index b3019b82f54..63f203ffda0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g0b1re/src/Make.defs +# boards/arm/stm32g0/nucleo-g0b1re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h rename to boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h index 66318689a0f..30f9bd80a2c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/nucleo-g0b1re.h + * boards/arm/stm32g0/nucleo-g0b1re/src/nucleo-g0b1re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c index b1f9be4fd72..21ab51079be 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_adc.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c index 2ee5c55f2ad..248a297f617 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_autoleds.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c index e882e5d1617..231a9256892 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_boot.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c index e9ca45a84d7..d852c55b2a2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_bringup.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c rename to boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c index 688327750b6..8a389b06aef 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c +++ b/boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-g0b1re/src/stm32_buttons.c + * boards/arm/stm32g0/nucleo-g0b1re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt new file mode 100644 index 00000000000..2b50926e867 --- /dev/null +++ b/boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g0/stm32g071b-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig b/boards/arm/stm32g0/stm32g071b-disco/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/Kconfig rename to boards/arm/stm32g0/stm32g071b-disco/Kconfig diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig rename to boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig index 2c85c18f603..0fc28153e81 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/nsh/defconfig +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig rename to boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig index a0e1eef8c5b..37dc8896e41 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/configs/oled/defconfig +++ b/boards/arm/stm32g0/stm32g071b-disco/configs/oled/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32g071b-disco" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32G071B_DISCO=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32g0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G071RB=y CONFIG_ARCH_CHIP_STM32G0=y diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h b/boards/arm/stm32g0/stm32g071b-disco/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h rename to boards/arm/stm32g0/stm32g071b-disco/include/board.h index c3e14a3fe1d..86274e4365e 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h +++ b/boards/arm/stm32g0/stm32g071b-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/include/board.h + * boards/arm/stm32g0/stm32g071b-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs rename to boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs index df8a4c75ba1..86966d95270 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-g070rb/scripts/Make.defs +# boards/arm/stm32g0/stm32g071b-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script rename to boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script index 83336a8c174..b39bb951fed 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script +++ b/boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/ld.script + * boards/arm/stm32g0/stm32g071b-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt rename to boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt index 88d162b1679..2757b87d9fd 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt +++ b/boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/CMakeLists.txt +# boards/arm/stm32g0/stm32g071b-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs rename to boards/arm/stm32g0/stm32g071b-disco/src/Make.defs index 1f012b2515c..0adb2e6de3e 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs +++ b/boards/arm/stm32g0/stm32g071b-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/src/Make.defs +# boards/arm/stm32g0/stm32g071b-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c index 9fd6f2becdc..9ceb6f99b05 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_boot.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c index c41a38d31a1..09ca37d7392 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_bringup.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c index bd9171ece4a..0eae75d75e2 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_djoystick.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_djoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c index 310ba0bc75c..edc72b34f92 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_gpio.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c similarity index 98% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c index 1dce5040dd3..5655d41731c 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_ina226.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c index ee25ef5734f..db74b668500 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c index 07037ab3d6b..f75d17e3bd1 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_spi.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c index d8845d205d5..c1341209dff 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32_userleds.c + * boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h similarity index 99% rename from boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h rename to boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h index f8c27839f17..69585d3f7b1 100644 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h +++ b/boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/stm32g071b-disco/src/stm32g071b-disco.h + * boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h * * SPDX-License-Identifier: Apache-2.0 * From 79e3c2e59faadb9519781dced41fd94697e67025 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:43:32 +0200 Subject: [PATCH 154/268] !arch/stm32f0l0g0: move stm32c0 and finalize the directory split Move the stm32c0 sources, headers and boards into arch/arm/src/stm32c0, arch/arm/include/stm32c0 and boards/arm/stm32c0, then finalize the split: source each split family directly in arch/arm/Kconfig and boards/Kconfig and remove the now-empty combined arch/arm/src/stm32f0l0g0 and boards/arm/stm32f0l0g0 trees. BREAKING CHANGE: The combined STM32F0/L0/G0/C0 architecture and board paths were split into stm32f0, stm32l0, stm32g0, and stm32c0 directories. Out-of-tree boards, include paths, source paths, and defconfigs must move from stm32f0l0g0 to the matching split family. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 559 +++---- LICENSE | 20 +- arch/arm/include/phy62xx/phy62xx_irq.h | 2 +- arch/arm/include/stm32c0/chip.h | 157 ++ .../stm32c0_irq.h => stm32c0/irq.h} | 68 +- arch/arm/include/stm32f0l0g0/chip.h | 776 --------- arch/arm/include/stm32f0l0g0/irq.h | 114 -- arch/arm/src/common/stm32/CMakeLists.txt | 6 + arch/arm/src/common/stm32/Make.defs | 4 + .../stm32/stm32_crypto_m0_v1.c} | 6 +- .../arm/src/stm32c0}/CMakeLists.txt | 13 +- arch/arm/src/stm32c0/Kconfig | 286 ++++ .../src/{stm32f0l0g0 => stm32c0}/Make.defs | 21 +- arch/arm/src/{stm32f0l0g0 => stm32c0}/chip.h | 12 +- .../src/stm32c0/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32c0/hardware/stm32_pinmap.h | 17 + .../hardware/stm32c0_dmamux.h | 8 +- .../hardware/stm32c0_exti.h | 8 +- .../hardware/stm32c0_flash.h | 8 +- .../hardware/stm32c0_memorymap.h | 8 +- .../hardware/stm32c0_pinmap.h | 8 +- .../hardware/stm32c0_pwr.h | 8 +- .../hardware/stm32c0_rcc.h | 8 +- arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32.h | 8 +- .../src/{stm32f0l0g0 => stm32c0}/stm32_rcc.c | 16 +- .../{stm32f0l0g0 => stm32c0}/stm32c0_rcc.c | 2 +- arch/arm/src/stm32f0l0g0/CMakeLists.txt | 55 - arch/arm/src/stm32f0l0g0/Kconfig | 1418 ----------------- arch/arm/src/stm32f0l0g0/stm32_rcc.h | 90 -- boards/Kconfig | 5 +- .../common/CMakeLists.txt | 2 +- .../{stm32f0l0g0 => stm32c0}/common/Kconfig | 0 .../{stm32f0l0g0 => stm32c0}/common/Makefile | 2 +- .../nucleo-c071rb}/CMakeLists.txt | 2 +- .../nucleo-c071rb/Kconfig | 0 .../nucleo-c071rb/configs/adcscope/defconfig | 2 +- .../nucleo-c071rb/configs/jumbo/defconfig | 2 +- .../nucleo-c071rb/configs/nsh/defconfig | 2 +- .../nucleo-c071rb/include/board.h | 2 +- .../nucleo-c071rb}/scripts/Make.defs | 2 +- .../nucleo-c071rb/scripts/flash.ld | 2 +- .../nucleo-c071rb/src/CMakeLists.txt | 2 +- .../nucleo-c071rb/src/Make.defs | 2 +- .../nucleo-c071rb/src/nucleo-c071rb.h | 2 +- .../nucleo-c071rb/src/stm32_adc.c | 2 +- .../nucleo-c071rb/src/stm32_autoleds.c | 2 +- .../nucleo-c071rb/src/stm32_boot.c | 2 +- .../nucleo-c071rb/src/stm32_bringup.c | 2 +- .../nucleo-c071rb/src/stm32_buttons.c | 2 +- .../nucleo-c071rb/src/stm32_userleds.c | 2 +- .../nucleo-c092rc}/CMakeLists.txt | 2 +- .../nucleo-c092rc/Kconfig | 0 .../nucleo-c092rc/configs/can/defconfig | 2 +- .../nucleo-c092rc/configs/cansock/defconfig | 2 +- .../nucleo-c092rc/configs/jumbo/defconfig | 2 +- .../nucleo-c092rc/configs/nsh/defconfig | 2 +- .../nucleo-c092rc/include/board.h | 2 +- .../nucleo-c092rc}/scripts/Make.defs | 2 +- .../nucleo-c092rc/scripts/flash.ld | 2 +- .../nucleo-c092rc/src/CMakeLists.txt | 2 +- .../nucleo-c092rc/src/Make.defs | 2 +- .../nucleo-c092rc/src/nucleo-c092rc.h | 2 +- .../nucleo-c092rc/src/stm32_adc.c | 2 +- .../nucleo-c092rc/src/stm32_autoleds.c | 2 +- .../nucleo-c092rc/src/stm32_boot.c | 2 +- .../nucleo-c092rc/src/stm32_bringup.c | 2 +- .../nucleo-c092rc/src/stm32_buttons.c | 2 +- .../nucleo-c092rc/src/stm32_can.c | 2 +- .../nucleo-c092rc/src/stm32_cansock.c | 2 +- .../nucleo-c092rc/src/stm32_userleds.c | 2 +- .../b-l072z-lrwan1/scripts/Make.defs | 41 - .../stm32f0l0g0/nucleo-f072rb/CMakeLists.txt | 23 - .../stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt | 23 - .../stm32f0l0g0/nucleo-l073rz/CMakeLists.txt | 23 - .../stm32f051-discovery/CMakeLists.txt | 23 - .../stm32f051-discovery/scripts/Make.defs | 41 - .../stm32f072-discovery/CMakeLists.txt | 23 - .../stm32f072-discovery/scripts/Make.defs | 41 - .../stm32g071b-disco/CMakeLists.txt | 23 - .../stm32g071b-disco/scripts/Make.defs | 41 - .../stm32l0538-disco/CMakeLists.txt | 23 - 81 files changed, 865 insertions(+), 3262 deletions(-) create mode 100644 arch/arm/include/stm32c0/chip.h rename arch/arm/include/{stm32f0l0g0/stm32c0_irq.h => stm32c0/irq.h} (78%) delete mode 100644 arch/arm/include/stm32f0l0g0/chip.h delete mode 100644 arch/arm/include/stm32f0l0g0/irq.h rename arch/arm/src/{stm32f0l0g0/stm32_crypto.c => common/stm32/stm32_crypto_m0_v1.c} (97%) rename {boards/arm/stm32f0l0g0/nucleo-g070rb => arch/arm/src/stm32c0}/CMakeLists.txt (79%) create mode 100644 arch/arm/src/stm32c0/Kconfig rename arch/arm/src/{stm32f0l0g0 => stm32c0}/Make.defs (71%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/chip.h (85%) create mode 100644 arch/arm/src/stm32c0/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32c0/hardware/stm32_pinmap.h rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_dmamux.h (89%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_exti.h (95%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_flash.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_memorymap.h (96%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_pinmap.h (98%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_pwr.h (97%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/hardware/stm32c0_rcc.h (99%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32.h (91%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32_rcc.c (94%) rename arch/arm/src/{stm32f0l0g0 => stm32c0}/stm32c0_rcc.c (99%) delete mode 100644 arch/arm/src/stm32f0l0g0/CMakeLists.txt delete mode 100644 arch/arm/src/stm32f0l0g0/Kconfig delete mode 100644 arch/arm/src/stm32f0l0g0/stm32_rcc.h rename boards/arm/{stm32f0l0g0 => stm32c0}/common/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32c0}/common/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32c0}/common/Makefile (97%) rename boards/arm/{stm32f0l0g0/nucleo-c092rc => stm32c0/nucleo-c071rb}/CMakeLists.txt (94%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/configs/adcscope/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/configs/jumbo/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/include/board.h (99%) rename boards/arm/{stm32f0l0g0/nucleo-c092rc => stm32c0/nucleo-c071rb}/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/CMakeLists.txt (95%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/nucleo-c071rb.h (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_adc.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c071rb/src/stm32_userleds.c (98%) rename boards/arm/{stm32f0l0g0/nucleo-g071rb => stm32c0/nucleo-c092rc}/CMakeLists.txt (94%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/Kconfig (100%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/configs/can/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/configs/cansock/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/configs/jumbo/defconfig (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/configs/nsh/defconfig (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/include/board.h (99%) rename boards/arm/{stm32f0l0g0/nucleo-c071rb => stm32c0/nucleo-c092rc}/scripts/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/scripts/flash.ld (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/CMakeLists.txt (96%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/Make.defs (96%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/nucleo-c092rc.h (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_adc.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_autoleds.c (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_boot.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_bringup.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_buttons.c (98%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_can.c (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_cansock.c (97%) rename boards/arm/{stm32f0l0g0 => stm32c0}/nucleo-c092rc/src/stm32_userleds.c (98%) delete mode 100644 boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs delete mode 100644 boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs delete mode 100644 boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs delete mode 100644 boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt delete mode 100644 boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs delete mode 100644 boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index af9aa333479..d6832ccd151 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -905,9 +905,7 @@ arch/arm/include/mps/irq.h anjiahao@xiaomi.com alin.jerpelea@sony.com arch/arm/include/mx8mp/chip.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/irq.h philippe.leduc@wandercraft.eu alin.jerpelea@sony.com arch/arm/include/mx8mp/mx8mp_irq.h philippe.leduc@wandercraft.eu devel@sumpfralle.de alin.jerpelea@sony.com - arch/arm/include/nrf* raiden00@railab.me alin.jerpelea@sony.com - arch/arm/include/nuc1xx/chip.h alin.jerpelea@sony.com loketep@yahoo.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com arch/arm/include/nuc1xx/nuc120_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com @@ -974,17 +972,17 @@ arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.gi arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32f0l0g0/chip.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com tbennett@2g-eng.com -arch/arm/include/stm32f0l0g0/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me gustavo.nihei@espressif.com -arch/arm/include/stm32f0l0g0/stm32c0_irq.h raiden00@railab.me -arch/arm/include/stm32f0l0g0/stm32f0_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com -arch/arm/include/stm32f0l0g0/stm32g0_irq.h dpo@certi.org.br 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com kwilson@2g-eng.com -arch/arm/include/stm32f0l0g0/stm32l0_irq.h alin.jerpelea@sony.com raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com xiaoxiang@xiaomi.com +arch/arm/include/stm32c0/chip.h raiden00@railab.me +arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com +arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com titus@elbe-informatik.de arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32g0/chip.h raiden00@railab.me +arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +992,8 @@ arch/arm/include/stm32h7/stm32h7x3xx_irq.h simon@leitwert.ch David.Sidrane@NscDg arch/arm/include/stm32h7/stm32h7x5xx_cpu2_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony.com arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com +arch/arm/include/stm32l0/chip.h raiden00@railab.me +arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br @@ -3431,7 +3431,6 @@ arch/arm/src/rp2040/rp2040_ws2812.h 58759586+curuvar@users.noreply.github.com xi arch/arm/src/rp2040/rp2040_ws2812.pio 58759586+curuvar@users.noreply.github.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de arch/arm/src/rp2040/rp2040_xosc.c y.512.nakamura@gmail.com ian@iandouglasscott.com xiaoxiang@xiaomi.com yinshengkai@xiaomi.com arch/arm/src/rp2040/rp2040_xosc.h y.512.nakamura@gmail.com alin.jerpelea@sony.com - arch/arm/src/rp23xx/* marco.casaroli@gmail.com alin.jerpelea@sony.com bijunda@dreame.tech arch/arm/src/rtl8720c/* jerry_tang@realsil.com.cn petro.karashchenko@gmail.com alin.jerpelea@sony.com arch/arm/src/s32k1xx/* jari.vanewijk@nxp.com peter.vanderperk@nxp.com David.Sidrane@NscDg.com alin.jerpelea@sony.com gustavo.nihei@espressif.com @@ -3440,7 +3439,6 @@ arch/arm/src/sama5/* alin.jerpelea@sony.com adam@adamfeuer.com 56726697+TimJTi@u arch/arm/src/samd2l2/* alin.jerpelea@sony.com arch/arm/src/samd5e5/* alin.jerpelea@sony.com xiaoxiang@xiaomi.com leomar@falker.com.br arch/arm/src/samv7/* michallenc@seznam.cz petro.karashchenko@gmail.com pressste@fel.cvut.cz alin.jerpelea@sony.com xiaoxiang@xiaomi.com - arch/arm/src/stm32/Kconfig raiden00pl@gmail.com raiden00@railab.me danieloak@gmail.com arch/arm/src/stm32/chip.h raiden00pl@gmail.com alin.jerpelea@sony.com paul-a.patience@polymtl.ca arch/arm/src/stm32/hardware/stm32_adc.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com @@ -3746,142 +3744,38 @@ arch/arm/src/stm32/stm32l15xx_flash.c alin.jerpelea@sony.com abdelatif.guettouch arch/arm/src/stm32/stm32l15xxx_alarm.h juha.niskanen@haltian.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com arch/arm/src/stm32/stm32l15xxx_rcc.c 59230071+hartmannathan@users.noreply.github.com juha.niskanen@haltian.com alin.jerpelea@sony.com raiden00pl@gmail.com arch/arm/src/stm32/stm32l15xxx_rtcc.c juha.niskanen@haltian.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/Kconfig dpo@certi.org.br raiden00@railab.me kwilson@2g-eng.com tbennett@2g-eng.com -arch/arm/src/stm32f0l0g0/chip.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h tbennett@2g-eng.com alin.jerpelea@sony.com raiden00@railab.me kwilson@2g-eng.com -arch/arm/src/stm32f0l0g0/hardware/stm32_aes.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_can.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_comp.h raiden00@railab.me alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_crc.h alin.jerpelea@sony.com devel@sumpfralle.de -arch/arm/src/stm32f0l0g0/hardware/stm32_crs.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de -arch/arm/src/stm32f0l0g0/hardware/stm32_dac.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_dma_v1.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_dmamux.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_exti.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_fdcan.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_flash.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_gpio.h alin.jerpelea@sony.com raiden00@railab.me hartman.nathan@gmail.com -arch/arm/src/stm32f0l0g0/hardware/stm32_i2c.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_memorymap.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_pinmap.h alin.jerpelea@sony.com David.Sidrane@NscDg.com acassis@gmail.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_pwr.h alin.jerpelea@sony.com raiden00@railab.me xiaoxiang@xiaomi.com -arch/arm/src/stm32f0l0g0/hardware/stm32_rcc.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_rng.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_rtcc.h alin.jerpelea@sony.com gustavo.nihei@espressif.com -arch/arm/src/stm32f0l0g0/hardware/stm32_spi.h alin.jerpelea@sony.com raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_syscfg.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h dpo@certi.org.br alin.jerpelea@sony.com raiden00@railab.me gvr@certi.org.br -arch/arm/src/stm32f0l0g0/hardware/stm32_uart.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v1.h alin.jerpelea@sony.com petro.karashchenko@gmail.com -arch/arm/src/stm32f0l0g0/hardware/stm32_uart_v2.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com -arch/arm/src/stm32f0l0g0/hardware/stm32_usbdev.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32_wdt.h alin.jerpelea@sony.com -arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h raiden00@railab.me -arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h raiden00@railab.me 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alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com +arch/arm/src/stm32f0/stm32f0_rcc.c raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com xiaoxiang@xiaomi.com piyushpatle228@gmail.com arch/arm/src/stm32f7/Kconfig david_s5@nscdg.com raiden00@railab.me david_s5@usa.net titus@elbe-informatik.de arch/arm/src/stm32f7/chip.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com Lok Tep 1 file changed, 1 insertion(+) arch/arm/src/stm32f7/hardware/stm32_adc.h alin.jerpelea@sony.com @@ -4046,6 +3940,21 @@ arch/arm/src/stm32f7/stm32_waste.h ville.juven@unikie.com 101105604+simbit18@use arch/arm/src/stm32f7/stm32f72xx73xx_rcc.c bob.feretich@rafresearch.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de ramtin@lambdaconcept.com arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c david_s5@nscdg.com jussi.kivilinna@haltian.com alin.jerpelea@sony.com b.brandt@messwerk-gmbh.de arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c 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+arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me David.Sidrane@NscDg.com gvr@certi.org.br +arch/arm/src/stm32g0/hardware/stm32g0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32g0/hardware/stm32g0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com kwilson@2g-eng.com tbennett@2g-eng.com +arch/arm/src/stm32g0/hardware/stm32g0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32g0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com +arch/arm/src/stm32g0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com +arch/arm/src/stm32g0/stm32g0_rcc.c raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me dpo@certi.org.br juha.niskanen@haltian.com arch/arm/src/stm32h5/Kconfig kwilson@2g-eng.com tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com raiden00@railab.me jlange@2g-eng.com arch/arm/src/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/src/stm32h5/hardware/stm32_adc.h tbennett@2g-eng.com 101105604+simbit18@users.noreply.github.com @@ -4276,6 +4185,20 @@ arch/arm/src/stm32h7/stm32h743xx_flash.c javiercasas@geotab.com petro.karashchen arch/arm/src/stm32h7/stm32h7b3xx_flash.c javiercasas@geotab.com petro.karashchenko@gmail.com alin.jerpelea@sony.com lipengfei28@xiaomi.com arch/arm/src/stm32h7/stm32h7x3xx_rcc.c simon@leitwert.ch raiden00pl@gmail.com david.sidrane@nscdg.com raiden00@railab.me anthony@vergeaero.com arch/arm/src/stm32h7/stm32h7x7xx_rcc.c lwazeh@gmail.com anthony@vergeaero.com raiden00@railab.me alin.jerpelea@sony.com jfbblue0922@gmail.com +arch/arm/src/stm32l0/Kconfig raiden00@railab.me +arch/arm/src/stm32l0/chip.h alin.jerpelea@sony.com acassis@gmail.com raiden00@railab.me raiden00pl@gmail.com +arch/arm/src/stm32l0/hardware/stm32_memorymap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32_pinmap.h raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_exti.h alin.jerpelea@sony.com raiden00pl@gmail.com raiden00@railab.me david_s5@usa.net bob.feretich@rafresearch.com +arch/arm/src/stm32l0/hardware/stm32l0_flash.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_memorymap.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com juha.niskanen@haltian.com +arch/arm/src/stm32l0/hardware/stm32l0_pinmap.h David.Sidrane@NscDg.com raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32l0/hardware/stm32l0_pwr.h raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/src/stm32l0/hardware/stm32l0_rcc.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com +arch/arm/src/stm32l0/hardware/stm32l0_syscfg.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com acassis@gmail.com +arch/arm/src/stm32l0/stm32.h alin.jerpelea@sony.com raiden00pl@gmail.com pettitkd@gmail.com raiden00@railab.me acassis@gmail.com +arch/arm/src/stm32l0/stm32_rcc.c raiden00@railab.me alin.jerpelea@sony.com raiden00pl@gmail.com 85544393+oreh-a@users.noreply.github.com alexander.oryshchenko@ge.com +arch/arm/src/stm32l0/stm32l0_rcc.c raiden00pl@gmail.com raiden00@railab.me juha.niskanen@haltian.com matteo.golin@gmail.com xiaoxiang@xiaomi.com arch/arm/src/stm32l4/Kconfig dev@ziggurat29.com danieloak@gmail.com juha.niskanen@haltian.com sebastien@lorquet.fr arch/arm/src/stm32l4/chip.h sebastien@lorquet.fr alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/src/stm32l4/hardware/stm32l4_adc.h danieloak@gmail.com alin.jerpelea@sony.com anchao@xiaomi.com acassis@gmail.com @@ -4698,12 +4621,10 @@ arch/arm/src/stm32wl5/stm32wl5_userspace.c michal.lyszczek@bofc.pl alin.jerpelea arch/arm/src/stm32wl5/stm32wl5_userspace.h michal.lyszczek@bofc.pl alin.jerpelea@sony.com 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+boards/arm/stm32g0/stm32g071b-disco/src/stm32_ina226.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_lcd_ssd1306.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_spi.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32_userleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32g0/stm32g071b-disco/src/stm32g071b-disco.h raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/Kconfig raiden00@railab.me +boards/arm/stm32l0/stm32l0538-disco/configs/nsh/defconfig raiden00@railab.me xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32l0/stm32l0538-disco/include/board.h raiden00@railab.me devel@sumpfralle.de alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/scripts/ld.script raiden00@railab.me cuiziwei@xiaomi.com alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_appinit.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_autoleds.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_boot.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_bringup.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32_buttons.c raiden00@railab.me alin.jerpelea@sony.com +boards/arm/stm32l0/stm32l0538-disco/src/stm32l0538-disco.h raiden00@railab.me alin.jerpelea@sony.com boards/arm/stm32f7/common/Kconfig raiden00@railab.me acassis@gmail.com boards/arm/stm32f7/common/Makefile acassis@gmail.com alin.jerpelea@sony.com boards/arm/stm32f7/common/include/stm32_bh1750.h acassis@gmail.com alin.jerpelea@sony.com diff --git a/LICENSE b/LICENSE index f78dcd33b6e..a76c658ae4e 100644 --- a/LICENSE +++ b/LICENSE @@ -3386,9 +3386,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_gpio.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_pwm.c -boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_timer.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_gpio.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_pwm.c +boards/arm/stm32g0/nucleo-g070rb/src/stm32_timer.c ===================================================== Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4243,7 +4243,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h +arch/arm/src/stm32g0/hardware/stm32g0_pinmap.h ===================================================== Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -4276,7 +4276,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_i2c.c +arch/arm/src/common/stm32/stm32_i2c_m0_v1.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4309,7 +4309,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.c +arch/arm/src/common/stm32/stm32_pwm_m0_v1.c ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4341,9 +4341,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_pwm.h -arch/arm/src/stm32f0l0g0/stm32_tim.c -arch/arm/src/stm32f0l0g0/stm32_tim.h +arch/arm/src/common/stm32/stm32_pwm_m0_v1.h +arch/arm/src/common/stm32/stm32_tim_m0_v1.c +arch/arm/src/common/stm32/stm32_tim_m0_v1.h ======================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. @@ -4375,7 +4375,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m0_v1_lowerhalf.c ================================================= Copyright (C) 2019 Fundação CERTI. All rights reserved. diff --git a/arch/arm/include/phy62xx/phy62xx_irq.h b/arch/arm/include/phy62xx/phy62xx_irq.h index b8bf21ed912..c6d55217f62 100644 --- a/arch/arm/include/phy62xx/phy62xx_irq.h +++ b/arch/arm/include/phy62xx/phy62xx_irq.h @@ -44,7 +44,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h + * found in nuttx/arch/arm/include/phy62xx/irq.h */ #define PHY62XX_IRQ_BB_IRQn (PHY62XX_IRQ_EXTINT + 4) /* 4: RCC and CRS */ diff --git a/arch/arm/include/stm32c0/chip.h b/arch/arm/include/stm32c0/chip.h new file mode 100644 index 00000000000..64eb965d03f --- /dev/null +++ b/arch/arm/include/stm32c0/chip.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/arm/include/stm32c0/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32C0_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32C0_CHIP_H + +#define ARMV6M_PERIPHERAL_INTERRUPTS 32 + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip */ + +#if defined(CONFIG_ARCH_CHIP_STM32C051XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, + * TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 0 /* No FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, + * TIM15, TIM16 and TIM17 */ +# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ +# define STM32_NBTIM 0 /* No basic timers */ + /* One LPTIMER */ +# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ +# define STM32_NI2S 0 /* No I2S module */ +# define STM32_NI2C 2 /* Two I2C */ +# define STM32_NDMA 1 /* One DMA1, 5-channels */ +# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ +# define STM32_NCAN 0 /* No CAN controllers */ +# define STM32_FDCAN 1 /* One FD CAN */ +# define STM32_NLCD 0 /* No LCD controller */ +# define STM32_NUSBDEV 1 /* USB full-speed device controller */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NCEC 0 /* No HDMI-CEC controller */ +# define STM32_NADC 1 /* One 12-bit module */ +# define STM32_NDAC 0 /* No DAC channels */ +# define STM32_NCOMP 0 /* No Analog Comparators */ +# define STM32_NCRC 1 /* One CRC module */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NCAP 0 /* No Capacitive sensing channels */ +# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ +#else +# error "Unsupported STM32 Cortex M0 chip" +#endif + +/* NVIC priority levels *****************************************************/ + +/* Each priority field holds a priority value, 0-31. The lower the value, + * the greater the priority of the corresponding interrupt. The processor + * implements only bits[7:6] of each field, bits[5:0] read as zero and + * ignore writes. + */ + +#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32C0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h b/arch/arm/include/stm32c0/irq.h similarity index 78% rename from arch/arm/include/stm32f0l0g0/stm32c0_irq.h rename to arch/arm/include/stm32c0/irq.h index fe52e407a7d..aba16028025 100644 --- a/arch/arm/include/stm32f0l0g0/stm32c0_irq.h +++ b/arch/arm/include/stm32c0/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32f0l0g0/stm32c0_irq.h + * arch/arm/include/stm32c0/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,16 +24,17 @@ * through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32C0_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32C0_IRQ_H /**************************************************************************** * Included Files ****************************************************************************/ -#include -#include -#include +#ifndef __ASSEMBLY__ +# include +#endif +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,11 +43,31 @@ /* IRQ numbers. The IRQ number corresponds vector number and hence map * directly to bits in the NVIC. This does, however, waste several words of * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32f0l0g0/irq.h */ +/* Common Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ + /* Vectors 4-10: Reserved */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ + /* Vector 12-13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16) */ + +#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* External interrupt vectors */ + #define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVM (STM32_IRQ_EXTINT + 1) /* 1: VDDIO2 monitor interrupt */ #define STM32_IRQ_RTC (STM32_IRQ_EXTINT + 2) /* 2: RTC */ @@ -87,31 +108,6 @@ #define STM32_IRQ_NEXTINTS (32) -/**************************************************************************** - * Public Types - ****************************************************************************/ +#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32C0_IRQ_H */ diff --git a/arch/arm/include/stm32f0l0g0/chip.h b/arch/arm/include/stm32f0l0g0/chip.h deleted file mode 100644 index 11626cd2e83..00000000000 --- a/arch/arm/include/stm32f0l0g0/chip.h +++ /dev/null @@ -1,776 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Get customizations for each supported chip */ - -#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC) - -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 0 /* No I2S modules */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 0 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* One DAC channel */ -# define STM32_NCOMP 0 /* Two Analog Comparators */ -# define STM32_NCAP 0 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F051R8) - -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */ - -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* Two USARTs modules */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 1 /* One DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 13 /* Capacitive sensing channels (14 on UFQFPN32)) */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072C8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072R8) || defined(CONFIG_ARCH_CHIP_STM32F072RB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072R8 -# define STM32_FLASH_SIZE (64*1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128*1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16*1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB) - -# ifdef CONFIG_ARCH_CHIP_STM32F072V8 -# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */ -# else -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# endif -# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USARTs module */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 1 /* One USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC) - -# ifdef CONFIG_ARCH_CHIP_STM32F091CB -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 6 /* Six USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCAP 17 /* Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091RC) || \ - defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) - -# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB) -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# else -# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */ -# endif -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */ -# define STM32_NGTIM32 1 /* 32-bit general up/down timers TIM2 */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */ -# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C modules */ -# define STM32_NDMA 2 /* DMA1, DMA2 */ -# define STM32_NUSART 8 /* Eight USARTs modules */ -# define STM32_NCAN 1 /* One CAN controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channel */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# if defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC) -# define STM32_NCAP 24 /* Capacitive sensing channels */ -# else -# define STM32_NCAP 18 /* Capacitive sensing channels */ -# endif -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G070RB) - -# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */ -# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */ - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, - * TIM14-17 */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module (SPI or I2S) */ -# define STM32_NI2C 2 /* Two I2C (1 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 0 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 16-channels */ - -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G071EB) || defined(CONFIG_ARCH_CHIP_STM32G071G8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GB) || defined(CONFIG_ARCH_CHIP_STM32G071G8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071GBXN) || defined(CONFIG_ARCH_CHIP_STM32G071K8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KB) || defined(CONFIG_ARCH_CHIP_STM32G071K8XN) || \ - defined(CONFIG_ARCH_CHIP_STM32G071KBXN) || defined(CONFIG_ARCH_CHIP_STM32G071C8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071CB) || defined(CONFIG_ARCH_CHIP_STM32G071R8) || \ - defined(CONFIG_ARCH_CHIP_STM32G071RB) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* Two LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 2 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -#elif defined(CONFIG_ARCH_CHIP_STM32G0B1KB) || defined(CONFIG_ARCH_CHIP_STM32G0B1CB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RB) || defined(CONFIG_ARCH_CHIP_STM32G0B1MB) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1VB) || defined(CONFIG_ARCH_CHIP_STM32G0B1KC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1CC) || defined(CONFIG_ARCH_CHIP_STM32G0B1RC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1MC) || defined(CONFIG_ARCH_CHIP_STM32G0B1VC) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1KE) || defined(CONFIG_ARCH_CHIP_STM32G0B1CE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1RE) || defined(CONFIG_ARCH_CHIP_STM32G0B1NE) || \ - defined(CONFIG_ARCH_CHIP_STM32G0B1ME) || defined(CONFIG_ARCH_CHIP_STM32G0B1VE) - -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM16 6 /* 16-bit general purpose timers */ -# define STM32_NGTIM32 1 /* TIM2 */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 3 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Two I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 2 /* DMA1 7-channels, DMA2 5-channels DMA1 */ -# define STM32_NUSART 6 /* Six USART modules, USART1-6 */ - /* Two LPUART */ -# define STM32_NCAN 1 /* One FDCAN controller */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 1 /* One USB full-speed controller */ -# define STM32_NUSBOTG 0 /* No USB OTG */ -# define STM32_NCEC 1 /* One HDMI-CEC controller */ -# define STM32_NADC 1 /* (1) ADC1, 12-channels */ - -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 3 /* Three Analog Comparators */ -# define STM32_NCRC 0 /* No CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-F */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L073XX - With LCD - * STM32L072XX - No LCD - * STM32L071XX - Access line, no LCD - * - * STM32L0XXX8 - 64KB FLASH, 20KB SRAM, 3KB EEPROM - * STM32L0XXXB - 128KB FLASH, 20KB SRAM, 6KB EEPROM - * STM32L0XXXZ - 192KB FLASH, 20KB SRAM, 3KB EEPROM - * - * STM32L0XXCX - 48-pins - * STM32L0XXRX - 64-pins - * STM32L0XXVX - 100-pins - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071K8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 3 /* 3 USART modules, USART1-3 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053C8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L053R8) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 3 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 1 /* 1 basic timers: TIM6 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 2 /* 2 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 2 /* 2 USART modules, USART1-1 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 1 /* 1 LCD */ -# define STM32_NUSBDEV 1 /* 1 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 24 /* 24 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071C8) || defined(CONFIG_ARCH_CHIP_STM32L071V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L071CB) || defined(CONFIG_ARCH_CHIP_STM32L071VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L071RB) || defined(CONFIG_ARCH_CHIP_STM32L071CZ) || \ - defined(CONFIG_ARCH_CHIP_STM32L071VZ) || defined(CONFIG_ARCH_CHIP_STM32L071RZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 2 /* 2 SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* 1 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L071KB) || defined(CONFIG_ARCH_CHIP_STM32L071KZ) -# define STM32_NATIM 0 /* 0 advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* 0 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ - /* 1 LPTIMER */ -# define STM32_NSPI 1 /* 1 SPI modules SPI1 */ -# define STM32_NI2S 0 /* 0 I2S module */ -# define STM32_NI2C 3 /* 3 I2C */ -# define STM32_NDMA 1 /* 1 DMA1, 7-channels */ -# define STM32_NUSART 4 /* 4 USART modules, USART1-4 */ - /* 1 LPUART */ -# define STM32_NCAN 0 /* 0 CAN controllers */ -# define STM32_NLCD 0 /* 0 LCD */ -# define STM32_NUSBDEV 0 /* 0 USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* 0 USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* 0 HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* 0 DAC channel */ -# define STM32_NCOMP 2 /* 2 Analog Comparators */ -# define STM32_NCRC 0 /* 0 CRC module */ -# define STM32_NRNG 0 /* 0 Random number generator (RNG) */ -# define STM32_NCAP 0 /* 0 Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072V8) || defined(CONFIG_ARCH_CHIP_STM32L072VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L072VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072KB) || defined(CONFIG_ARCH_CHIP_STM32L072KZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 13 /* Thirteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072CB) || defined(CONFIG_ARCH_CHIP_STM32L072CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 18 /* Nineteen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L072RB) || defined(CONFIG_ARCH_CHIP_STM32L072RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073V8) || defined(CONFIG_ARCH_CHIP_STM32L073VB) || \ - defined(CONFIG_ARCH_CHIP_STM32L073VZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073CB) || defined(CONFIG_ARCH_CHIP_STM32L073CZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L073RB) || defined(CONFIG_ARCH_CHIP_STM32L073RZ) -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM2-3 - * (with DMA) and TIM21-22 without DMA */ -# define STM32_NGTIM32 0 /* No 32-bit general up/down timers */ -# define STM32_NBTIM 2 /* Two basic timers: TIM6, TIM7 with DMA */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 1 /* One I2S module */ -# define STM32_NI2C 3 /* Three I2C (2 with SMBus/PMBus) */ -# define STM32_NDMA 1 /* One DMA1, 7-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ - /* One LPUART */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_NLCD 1 /* One LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 1 /* One USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 2 /* Two DAC channels */ -# define STM32_NCOMP 2 /* Two Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 1 /* One Random number generator (RNG) */ -# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */ -# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */ -#elif defined(CONFIG_ARCH_CHIP_STM32C051XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* Four 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 0 /* No USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C071XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 4 /* 16-bit general up/down timers TIM3, TIM14, - * TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 2 /* Two USART modules, USART1-2 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C091XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 0 /* No FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#elif defined(CONFIG_ARCH_CHIP_STM32C092XX) -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14, - * TIM15, TIM16 and TIM17 */ -# define STM32_NGTIM32 1 /* One 32-bit general up/down timer TIM2 */ -# define STM32_NBTIM 0 /* No basic timers */ - /* One LPTIMER */ -# define STM32_NSPI 2 /* Two SPI modules SPI1-2 */ -# define STM32_NI2S 0 /* No I2S module */ -# define STM32_NI2C 2 /* Two I2C */ -# define STM32_NDMA 1 /* One DMA1, 5-channels */ -# define STM32_NUSART 4 /* Four USART modules, USART1-4 */ -# define STM32_NCAN 0 /* No CAN controllers */ -# define STM32_FDCAN 1 /* One FD CAN */ -# define STM32_NLCD 0 /* No LCD controller */ -# define STM32_NUSBDEV 1 /* USB full-speed device controller */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NCEC 0 /* No HDMI-CEC controller */ -# define STM32_NADC 1 /* One 12-bit module */ -# define STM32_NDAC 0 /* No DAC channels */ -# define STM32_NCOMP 0 /* No Analog Comparators */ -# define STM32_NCRC 1 /* One CRC module */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NCAP 0 /* No Capacitive sensing channels */ -# define STM32_NPORTS 5 /* Five GPIO ports, GPIOA-D, F */ -#else -# error "Unsupported STM32 Cortex M0 chip" -#endif - -/* NVIC priority levels *****************************************************/ - -/* Each priority field holds a priority value, 0-31. The lower the value, - * the greater the priority of the corresponding interrupt. The processor - * implements only bits[7:6] of each field, bits[5:0] read as zero and - * ignore writes. - */ - -#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */ diff --git a/arch/arm/include/stm32f0l0g0/irq.h b/arch/arm/include/stm32f0l0g0/irq.h deleted file mode 100644 index 450d793e120..00000000000 --- a/arch/arm/include/stm32f0l0g0/irq.h +++ /dev/null @@ -1,114 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32f0l0g0/irq.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h - */ - -#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - */ - -/* Common Processor Exceptions (vectors 0-15) */ - -#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ - /* Vector 0: Reset stack pointer value */ - /* Vector 1: Reset (not handler as an IRQ) */ -#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ -#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ - /* Vectors 4-10: Reserved */ -#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ - /* Vector 12-13: Reserved */ -#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ -#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ - -/* External interrupts (vectors >= 16) */ - -#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Include MCU-specific external interrupt definitions */ - -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include -#else -# error Unrecognized STM32 Cortex M0 family -#endif - -#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -typedef void (*vic_vector_t)(uint32_t *regs); - -/**************************************************************************** - * Inline functions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -extern "C" -{ -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_IRQ_H */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index f7b24554c0f..c235abddbee 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -467,6 +467,12 @@ if(CONFIG_ARCH_CORTEXM0) list(APPEND SRCS stm32_aes_m0_v1.c) endif() + if(CONFIG_CRYPTO_CRYPTODEV_HARDWARE + AND CONFIG_STM32_AES + AND CONFIG_STM32_HAVE_IP_AES_M0_V1) + list(APPEND SRCS stm32_crypto_m0_v1.c) + endif() + if(CONFIG_STM32_RNG AND CONFIG_STM32_HAVE_IP_RNG_M0_V1) list(APPEND SRCS stm32_rng_m0_v1.c) endif() diff --git a/arch/arm/src/common/stm32/Make.defs b/arch/arm/src/common/stm32/Make.defs index 1e51e181755..729ce0b5983 100644 --- a/arch/arm/src/common/stm32/Make.defs +++ b/arch/arm/src/common/stm32/Make.defs @@ -511,6 +511,10 @@ ifeq ($(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yy) CHIP_CSRCS += stm32_aes_m0_v1.c endif +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE)$(CONFIG_STM32_AES)$(CONFIG_STM32_HAVE_IP_AES_M0_V1),yyy) +CHIP_CSRCS += stm32_crypto_m0_v1.c +endif + ifeq ($(CONFIG_STM32_RNG)$(CONFIG_STM32_HAVE_IP_RNG_M0_V1),yy) CHIP_CSRCS += stm32_rng_m0_v1.c endif diff --git a/arch/arm/src/stm32f0l0g0/stm32_crypto.c b/arch/arm/src/common/stm32/stm32_crypto_m0_v1.c similarity index 97% rename from arch/arm/src/stm32f0l0g0/stm32_crypto.c rename to arch/arm/src/common/stm32/stm32_crypto_m0_v1.c index 64b4b99c4f8..46e63d157e6 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_crypto.c +++ b/arch/arm/src/common/stm32/stm32_crypto_m0_v1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_crypto.c + * arch/arm/src/common/stm32/stm32_crypto_m0_v1.c * * SPDX-License-Identifier: Apache-2.0 * @@ -26,6 +26,8 @@ #include #include +#include +#include #include #include @@ -134,6 +136,8 @@ static int stm32_process(struct cryptop *crp) return -EINVAL; } } + + return 0; } /**************************************************************************** diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt b/arch/arm/src/stm32c0/CMakeLists.txt similarity index 79% rename from boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt rename to arch/arm/src/stm32c0/CMakeLists.txt index 4427973ea26..c795baf9c04 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt +++ b/arch/arm/src/stm32c0/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g070rb/CMakeLists.txt +# arch/arm/src/stm32c0/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,13 @@ # # ############################################################################## -add_subdirectory(src) +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS stm32_userspace.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32c0/Kconfig b/arch/arm/src/stm32c0/Kconfig new file mode 100644 index 00000000000..a2c0962ad1c --- /dev/null +++ b/arch/arm/src/stm32c0/Kconfig @@ -0,0 +1,286 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 C0 configuration" + +if ARCH_CHIP_STM32C0 + +choice + prompt "ST STM32C0 Chip Selection" + default ARCH_CHIP_STM32C071RB + depends on ARCH_CHIP_STM32C0 + +config ARCH_CHIP_STM32C051D8 + bool "STM32C051D8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051F6 + bool "STM32C051F6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051F8 + bool "STM32C051F8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051G6 + bool "STM32C051G6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051G8 + bool "STM32C051G8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051K6 + bool "STM32C051K6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051K8 + bool "STM32C051K8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C051C6 + bool "STM32C051C6" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_6 + +config ARCH_CHIP_STM32C051C8 + bool "STM32C051C8" + select ARCH_CHIP_STM32C051XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071F8 + bool "STM32C071F8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071FB + bool "STM32C071FB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071G8 + bool "STM32C071G8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071GB + bool "STM32C071GB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071K8 + bool "STM32C071K8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071KB + bool "STM32C071KB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071C8 + bool "STM32C071C8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071CB + bool "STM32C071CB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C071R8 + bool "STM32C071R8" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_8 + +config ARCH_CHIP_STM32C071RB + bool "STM32C071RB" + select ARCH_CHIP_STM32C071XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FB + bool "STM32C091FB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091FC + bool "STM32C091FC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091EC + bool "STM32C091EC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091GB + bool "STM32C091GB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091GC + bool "STM32C091GC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091KB + bool "STM32C091KB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091KC + bool "STM32C091KC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091CB + bool "STM32C091CB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091CC + bool "STM32C091CC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C091RB + bool "STM32C091RB" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C091RC + bool "STM32C091RC" + select ARCH_CHIP_STM32C091XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092FB + bool "STM32C092FB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092FC + bool "STM32C092FC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092EC + bool "STM32C092EC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092GB + bool "STM32C092GB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092GC + bool "STM32C092GC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092KB + bool "STM32C092KB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092KC + bool "STM32C092KC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092CB + bool "STM32C092CB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092CC + bool "STM32C092CC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +config ARCH_CHIP_STM32C092RB + bool "STM32C092RB" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_B + +config ARCH_CHIP_STM32C092RC + bool "STM32C092RC" + select ARCH_CHIP_STM32C092XX + select STM32_FLASH_CONFIG_C + +endchoice + +endif + +config STM32_STM32C0 + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_ADC_M0_V1 + select STM32_HAVE_CRC + select STM32_HAVE_BKP + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_AES_M0_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_COMP_M0_V1 if STM32_HAVE_COMP + select STM32_HAVE_IP_DAC_M0_V1 if STM32_HAVE_DAC1 + select STM32_HAVE_IP_DBGMCU_M0_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_FDCAN_MCAN_M0_V1 + select STM32_HAVE_IP_DMA_V1_7CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_FLASH_M0_V1 + select STM32_HAVE_IP_FLASH_M0_G0C0 + select STM32_HAVE_IP_GPIO_M0_V1 + select STM32_HAVE_IP_I2C_M0_V1 + select STM32_HAVE_IP_PWR_G0 + select STM32_HAVE_IP_RNG_M0_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTCC_M0_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_TIMERS_M0_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_WDG_M0_V1 + select STM32_HAVE_IP_UID_M0_V1 + select STM32_HAVE_IP_USBDEV_M0_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select ARCH_HAVE_PROGMEM + +config ARCH_CHIP_STM32C051XX + bool + select STM32_STM32C0 + +config ARCH_CHIP_STM32C071XX + bool + select STM32_STM32C0 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32C091XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_TIM15 + +config ARCH_CHIP_STM32C092XX + bool + select STM32_STM32C0 + select STM32_HAVE_USART3 + select STM32_HAVE_USART4 + select STM32_HAVE_FDCAN1 diff --git a/arch/arm/src/stm32f0l0g0/Make.defs b/arch/arm/src/stm32c0/Make.defs similarity index 71% rename from arch/arm/src/stm32f0l0g0/Make.defs rename to arch/arm/src/stm32c0/Make.defs index 9b02c489210..f7f9d727e67 100644 --- a/arch/arm/src/stm32f0l0g0/Make.defs +++ b/arch/arm/src/stm32c0/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32f0l0g0/Make.defs +# arch/arm/src/stm32c0/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,24 +22,7 @@ include armv6-m/Make.defs -CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_lowputc.c -CHIP_CSRCS += stm32_rcc.c stm32_lsi.c - -ifneq ($(CONFIG_STM32_RTC_LSECLOCK)$(CONFIG_STM32_LCD_LSECLOCK),) -CHIP_CSRCS += stm32_lse.c -endif - -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_pwr.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += stm32_timerisr.c -endif +CHIP_CSRCS = stm32_rcc.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += stm32_userspace.c diff --git a/arch/arm/src/stm32f0l0g0/chip.h b/arch/arm/src/stm32c0/chip.h similarity index 85% rename from arch/arm/src/stm32f0l0g0/chip.h rename to arch/arm/src/stm32c0/chip.h index b496c6b2020..e65e4fc23f6 100644 --- a/arch/arm/src/stm32f0l0g0/chip.h +++ b/arch/arm/src/stm32c0/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/chip.h + * arch/arm/src/stm32c0/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H +#ifndef __ARCH_ARM_SRC_STM32C0_CHIP_H +#define __ARCH_ARM_SRC_STM32C0_CHIP_H /**************************************************************************** * Included Files @@ -32,9 +32,7 @@ /* Include the chip capabilities file */ -#include - -#define ARMV6M_PERIPHERAL_INTERRUPTS 32 +#include /* Include the memory map file. * Other chip hardware files should then include this file for the proper @@ -43,4 +41,4 @@ #include "hardware/stm32_memorymap.h" -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_CHIP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_CHIP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..455026d8941 --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32c0/hardware/stm32_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..4d31e5c8a3e --- /dev/null +++ b/arch/arm/src/stm32c0/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32c0/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32c0_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h similarity index 89% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h rename to arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h index 1d91dc308bc..1e03567fdd5 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_dmamux.h + * arch/arm/src/stm32c0/hardware/stm32c0_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H /**************************************************************************** * Included Files @@ -54,4 +54,4 @@ #define DMAMAP_DMA1_REQGEN3 DMAMAP_MAP(DMA1, DMAMUX1_REQ_GEN3) #define DMAMAP_DMA1_ADC1 DMAMAP_MAP(DMA1, DMAMUX1_ADC1) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_DMAMUX_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h similarity index 95% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h rename to arch/arm/src/stm32c0/hardware/stm32c0_exti.h index 800a7a4faff..666034a22cd 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_exti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_exti.h + * arch/arm/src/stm32c0/hardware/stm32c0_exti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ /* TODO */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_EXTI_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_EXTI_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h rename to arch/arm/src/stm32c0/hardware/stm32c0_flash.h index dfcdb1e5e13..0fb3d2d0844 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_flash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_flash.h + * arch/arm/src/stm32c0/hardware/stm32c0_flash.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H /**************************************************************************** * Included Files @@ -202,4 +202,4 @@ #define FLASH_SECR_BOOT_LOCK (1 << 16) /* Bit 16: Used to force boot from user area */ /* Bits 20-31: Reserved */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_FLASH_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_FLASH_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h similarity index 96% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h index c847f7ca050..212d3f4a95c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_memorymap.h + * arch/arm/src/stm32c0/hardware/stm32c0_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H /**************************************************************************** * Pre-processor Definitions @@ -115,4 +115,4 @@ #define STM32_SYSMEM_UID 0x1fff7550 /* The 96-bit unique device identifier */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_MEMORYMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h similarity index 98% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h index 4e10209f8a6..5d8805236ed 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pinmap.h + * arch/arm/src/stm32c0/hardware/stm32c0_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,8 +32,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H /**************************************************************************** * Included Files @@ -351,4 +351,4 @@ #define GPIO_TIM17_CH1NOUT_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN4) #define GPIO_TIM17_CH1NOUT_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN7) -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PINMAP_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PINMAP_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h similarity index 97% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h rename to arch/arm/src/stm32c0/hardware/stm32c0_pwr.h index 7c16d410baf..0b6db18987c 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h + * arch/arm/src/stm32c0/hardware/stm32c0_pwr.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H /**************************************************************************** * Included Files @@ -150,4 +150,4 @@ #define PWR_BKPR_MASK (0xffff) /* Bits 0-16: Backup bitfield */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_PWR_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_PWR_H */ diff --git a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h similarity index 99% rename from arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h rename to arch/arm/src/stm32c0/hardware/stm32c0_rcc.h index 10119b6e62d..9784111a9b1 100644 --- a/arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h +++ b/arch/arm/src/stm32c0/hardware/stm32c0_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/hardware/stm32c0_rcc.h + * arch/arm/src/stm32c0/hardware/stm32c0_rcc.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H +#ifndef __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H +#define __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H /**************************************************************************** * Pre-processor Definitions @@ -394,4 +394,4 @@ #define RCC_CSR2_WWDGRSTF (1 << 30) /* Bit 30: WWDG reset flag */ #define RCC_CSR2_LPWRRSTF (1 << 31) /* Bit 31: Low-power reset flag */ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32C0_RCC_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_HARDWARE_STM32C0_RCC_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32.h b/arch/arm/src/stm32c0/stm32.h similarity index 91% rename from arch/arm/src/stm32f0l0g0/stm32.h rename to arch/arm/src/stm32c0/stm32.h index c43d655c8b9..7d1c5ae3476 100644 --- a/arch/arm/src/stm32f0l0g0/stm32.h +++ b/arch/arm/src/stm32c0/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32.h + * arch/arm/src/stm32c0/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_H +#ifndef __ARCH_ARM_SRC_STM32C0_STM32_H +#define __ARCH_ARM_SRC_STM32C0_STM32_H /**************************************************************************** * Included Files @@ -51,4 +51,4 @@ * Pre-processor Definitions ****************************************************************************/ -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_H */ +#endif /* __ARCH_ARM_SRC_STM32C0_STM32_H */ diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.c b/arch/arm/src/stm32c0/stm32_rcc.c similarity index 94% rename from arch/arm/src/stm32f0l0g0/stm32_rcc.c rename to arch/arm/src/stm32c0/stm32_rcc.c index b227f714756..4c847902807 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.c +++ b/arch/arm/src/stm32c0/stm32_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.c + * arch/arm/src/stm32c0/stm32_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -36,7 +36,7 @@ #include "arm_internal.h" #include "hardware/stm32_flash.h" #include "stm32_rcc.h" -#include "stm32_hsi48.h" +#include "stm32_hsi48_m0_v1.h" /**************************************************************************** * Pre-processor Definitions @@ -70,17 +70,7 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_ARCH_CHIP_STM32F0) -# include "stm32f0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32L0) -# include "stm32l0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32G0) -# include "stm32g0_rcc.c" -#elif defined(CONFIG_ARCH_CHIP_STM32C0) -# include "stm32c0_rcc.c" -#else -# error "Unsupported STM32F0/L0 RCC" -#endif +#include "stm32c0_rcc.c" /**************************************************************************** * Public Functions diff --git a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c b/arch/arm/src/stm32c0/stm32c0_rcc.c similarity index 99% rename from arch/arm/src/stm32f0l0g0/stm32c0_rcc.c rename to arch/arm/src/stm32c0/stm32c0_rcc.c index ec620d49538..ffa41fc0c6d 100644 --- a/arch/arm/src/stm32f0l0g0/stm32c0_rcc.c +++ b/arch/arm/src/stm32c0/stm32c0_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32c0_rcc.c + * arch/arm/src/stm32c0/stm32c0_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f0l0g0/CMakeLists.txt b/arch/arm/src/stm32f0l0g0/CMakeLists.txt deleted file mode 100644 index 7eca474eaf9..00000000000 --- a/arch/arm/src/stm32f0l0g0/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32f0l0g0/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_start.c - stm32_irq.c - stm32_lowputc.c - stm32_lsi.c - stm32_rcc.c) - -if(CONFIG_STM32_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK) - list(APPEND SRCS stm32_lse.c) -endif() - -if(CONFIG_STM32_PWR) - list(APPEND SRCS stm32_pwr.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -if(NOT CONFIG_SCHED_TICKLESS) - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f0l0g0/Kconfig b/arch/arm/src/stm32f0l0g0/Kconfig deleted file mode 100644 index 7ba32284fb0..00000000000 --- a/arch/arm/src/stm32f0l0g0/Kconfig +++ /dev/null @@ -1,1418 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32F0/L0/G0 Configuration Options" - -config STM32_F0L0G0_PERIPHERALS - bool - default y - depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 - select STM32_HAVE_COMP - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - -choice - prompt "ST STM32F0/L0/G0 Chip Selection" - default ARCH_CHIP_STM32F051R8 if ARCH_CHIP_STM32F0 - default ARCH_CHIP_STM32L073RZ if ARCH_CHIP_STM32L0 - default ARCH_CHIP_STM32G071RB if ARCH_CHIP_STM32G0 - default ARCH_CHIP_STM32C071RB if ARCH_CHIP_STM32C0 - depends on ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 - -config ARCH_CHIP_STM32F030C6 - bool "STM32F030C6" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030C8 - bool "STM32F030C8" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030CC - bool "STM32F030CC" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030F4 - bool "STM32F030F4" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030K6 - bool "STM32F030K6" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030R8 - bool "STM32F030R8" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F030RC - bool "STM32F030RC" - select STM32_STM32F03X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C4 - bool "STM32F031C4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031C6 - bool "STM32F031C6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031E6 - bool "STM32F031E6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F4 - bool "STM32F031F4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031F6 - bool "STM32F031F6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G4 - bool "STM32F031G4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031G6 - bool "STM32F031G6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K4 - bool "STM32F031K4" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F031K6 - bool "STM32F031K6" - select STM32_STM32F03X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038C6 - bool "STM32F038C6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038E6 - bool "STM32F038E6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038F6 - bool "STM32F038F6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038G6 - bool "STM32F038G6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F038K6 - bool "STM32F038K6" - select STM32_STM32F03X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C4 - bool "STM32F042C4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042C6 - bool "STM32F042C6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F4 - bool "STM32F042F4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042F6 - bool "STM32F042F6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G4 - bool "STM32F042G4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042G6 - bool "STM32F042G6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K4 - bool "STM32F042K4" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042K6 - bool "STM32F042K6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F042T6 - bool "STM32F042T6" - select STM32_STM32F04X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048C6 - bool "STM32F048C6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048G6 - bool "STM32F048G6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F048T6 - bool "STM32F048T6" - select STM32_STM32F04X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C4 - bool "STM32F051C4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C6 - bool "STM32F051C6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051C8 - bool "STM32F051C8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K4 - bool "STM32F051K4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K6 - bool "STM32F051K6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051K8 - bool "STM32F051K8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R4 - bool "STM32F051R4" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R6 - bool "STM32F051R6" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051R8 - bool "STM32F051R8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F051T8 - bool "STM32F051T8" - select STM32_STM32F05X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058C8 - bool "STM32F058C8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058R8 - bool "STM32F058R8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F058T8 - bool "STM32F058T8" - select STM32_STM32F05X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070C6 - bool "STM32F070C6" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070CB - bool "STM32F070CB" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070F6 - bool "STM32F070F6" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F070RB - bool "STM32F070RB" - select STM32_STM32F07X - select STM32_VALUELINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071C8 - bool "STM32F071C8" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071CB - bool "STM32F071CB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071RB - bool "STM32F071RB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071V8 - bool "STM32F071V8" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F071VB - bool "STM32F071VB" - select STM32_STM32F07X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072C8 - bool "STM32F072C8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072CB - bool "STM32F072CB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072R8 - bool "STM32F072R8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072RB - bool "STM32F072RB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072V8 - bool "STM32F072V8" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F072VB - bool "STM32F072VB" - select STM32_STM32F07X - select STM32_USBLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078CB - bool "STM32F078CB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078RB - bool "STM32F078RB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F078VB - bool "STM32F078VB" - select STM32_STM32F07X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CB - bool "STM32F091CB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091CC - bool "STM32F091CC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RB - bool "STM32F091RB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091RC - bool "STM32F091RC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VB - bool "STM32F091VB" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F091VC - bool "STM32F091VC" - select STM32_STM32F09X - select STM32_ACCESSLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098CC - bool "STM32F098CC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098RC - bool "STM32F098RC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32F098VC - bool "STM32F098VC" - select STM32_STM32F09X - select STM32_LOWVOLTLINE - depends on ARCH_CHIP_STM32F0 - -config ARCH_CHIP_STM32G070CB - bool "STM32G070CB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070KB - bool "STM32G070KB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G070RB - bool "STM32G070RB" - select STM32_STM32G070 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071EB - bool "STM32G071EB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8 - bool "STM32G071G8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GB - bool "STM32G071GB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071G8XN - bool "STM32G071G8XN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071GBXN - bool "STM32G071GBXN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8 - bool "STM32G071K8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KB - bool "STM32G071KB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071K8XN - bool "STM32G071K8XN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071KBXN - bool "STM32G071KBXN" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071C8 - bool "STM32G071C8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071CB - bool "STM32G071CB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071R8 - bool "STM32G071R8" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_8 - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G071RB - bool "STM32G071RB" - select STM32_STM32G071 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KB - bool "STM32G0B1KB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CB - bool "STM32G0B1CB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RB - bool "STM32G0B1RB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MB - bool "STM32G0B1MB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VB - bool "STM32G0B1VB" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_B - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KC - bool "STM32G0B1KC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CC - bool "STM32G0B1CC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RC - bool "STM32G0B1RC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1MC - bool "STM32G0B1MC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VC - bool "STM32G0B1VC" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_C - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1KE - bool "STM32G0B1KE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1CE - bool "STM32G0B1CE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1RE - bool "STM32G0B1RE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1NE - bool "STM32G0B1NE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1ME - bool "STM32G0B1ME" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32G0B1VE - bool "STM32G0B1VE" - select STM32_STM32G0B1 - select STM32_FLASH_CONFIG_E - depends on ARCH_CHIP_STM32G0 - -config ARCH_CHIP_STM32L053C8 - bool "STM32L053C8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L053R8 - bool "STM32L053R8" - select ARCH_CHIP_STM32L053XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071K8 - bool "STM32L071K8" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KB - bool "STM32L071KB" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071KZ - bool "STM32L071KZ" - select ARCH_CHIP_STM32L071XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071C8 - bool "STM32L071C8" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CB - bool "STM32L071CB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071CZ - bool "STM32L071CZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071V8 - bool "STM32L071V8" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VB - bool "STM32L071VB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071VZ - bool "STM32L071VZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RB - bool "STM32L071RB" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L071RZ - bool "STM32L071RZ" - select ARCH_CHIP_STM32L071XX - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072V8 - bool "STM32L072V8" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VB - bool "STM32L072VB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072VZ - bool "STM32L072VZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KB - bool "STM32L072KB" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072KZ - bool "STM32L072KZ" - select ARCH_CHIP_STM32L072XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CB - bool "STM32L072CB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072CZ - bool "STM32L072CZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RB - bool "STM32L072RB" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L072RZ - bool "STM32L072RZ" - select ARCH_CHIP_STM32L072XX - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C3 - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073V8 - bool "STM32L073V8" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VB - bool "STM32L073VB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073VZ - bool "STM32L073VZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CB - bool "STM32L073CB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073CZ - bool "STM32L073CZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RB - bool "STM32L073RB" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32L073RZ - bool "STM32L073RZ" - select ARCH_CHIP_STM32L073XX - depends on ARCH_CHIP_STM32L0 - -config ARCH_CHIP_STM32C051D8 - bool "STM32C051D8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051F6 - bool "STM32C051F6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051F8 - bool "STM32C051F8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051G6 - bool "STM32C051G6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051G8 - bool "STM32C051G8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051K6 - bool "STM32C051K6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051K8 - bool "STM32C051K8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C051C6 - bool "STM32C051C6" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_6 - -config ARCH_CHIP_STM32C051C8 - bool "STM32C051C8" - select ARCH_CHIP_STM32C051XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071F8 - bool "STM32C071F8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071FB - bool "STM32C071FB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071G8 - bool "STM32C071G8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071GB - bool "STM32C071GB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071K8 - bool "STM32C071K8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071KB - bool "STM32C071KB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071C8 - bool "STM32C071C8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071CB - bool "STM32C071CB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C071R8 - bool "STM32C071R8" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_8 - -config ARCH_CHIP_STM32C071RB - bool "STM32C071RB" - select ARCH_CHIP_STM32C071XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FB - bool "STM32C091FB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091FC - bool "STM32C091FC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091EC - bool "STM32C091EC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091GB - bool "STM32C091GB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091GC - bool "STM32C091GC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091KB - bool "STM32C091KB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091KC - bool "STM32C091KC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091CB - bool "STM32C091CB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091CC - bool "STM32C091CC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C091RB - bool "STM32C091RB" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C091RC - bool "STM32C091RC" - select ARCH_CHIP_STM32C091XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092FB - bool "STM32C092FB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092FC - bool "STM32C092FC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092EC - bool "STM32C092EC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092GB - bool "STM32C092GB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092GC - bool "STM32C092GC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092KB - bool "STM32C092KB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092KC - bool "STM32C092KC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092CB - bool "STM32C092CB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092CC - bool "STM32C092CC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -config ARCH_CHIP_STM32C092RB - bool "STM32C092RB" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_B - -config ARCH_CHIP_STM32C092RC - bool "STM32C092RC" - select ARCH_CHIP_STM32C092XX - select STM32_FLASH_CONFIG_C - -endchoice # ST STM32F0/L0/G0/C0 Chip Selection - -# Flash configurations - -config STM32_FLASH_OVERRIDE - bool "Override Flash Designator" - default n - -config STM32_STM32F0 - bool - default n - select STM32_HAVE_PWR - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_EXTI_V1 - -config STM32_STM32G0 - bool - default n - select STM32_HAVE_PWR - select STM32_HAVE_DMA1 - select STM32_HAVE_ADC1 - select STM32_HAVE_USART_RXFIFO_THRESHOLD - select STM32_HAVE_IP_ADC_M0_V1 - select STM32_HAVE_IP_TIMERS_M0_V1 - select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_I2C2 - select ARCH_HAVE_PROGMEM - -config STM32_STM32L0 - bool - default n - select STM32_HAVE_PWR - select STM32_HAVE_ADC1 - select STM32_HAVE_IP_ADC_M0_V1 - select STM32_HAVE_DMA1 - select STM32_ENERGYLITE - select STM32_HAVE_LCD - select STM32_HAVE_VREFINT - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_EXTI_V1 - -config STM32_STM32C0 - bool - default n - select STM32_HAVE_PWR - select STM32_HAVE_USART_RXFIFO_THRESHOLD - select STM32_HAVE_DMA1 - select STM32_HAVE_IP_WDG_M0_V1 - select STM32_HAVE_ADC1 - select STM32_HAVE_IP_ADC_M0_V1 - select STM32_HAVE_IP_TIMERS_M0_V1 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select ARCH_HAVE_PROGMEM - -config STM32_STM32F03X - bool - default n - select STM32_STM32F0 - -config STM32_STM32F04X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - -config STM32_STM32F05X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_DMA2 - -config STM32_STM32F07X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - select STM32_HAVE_DMA2 - -config STM32_STM32F09X - bool - default n - select STM32_STM32F0 - select STM32_HAVE_HSI48 - select STM32_HAVE_DMA2 - -config STM32_STM32G030 - bool - default n - select STM32_STM32G0 - select STM32_STM32G03X - -config STM32_STM32G031 - bool - default n - select STM32_STM32G0 - select STM32_STM32G03X - select STM32_HAVE_LPUART1 - -config STM32_STM32G03X - bool - default n - -config STM32_STM32G041 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_LPUART1 - -config STM32_STM32G050 - bool - default n - select STM32_STM32G0 - select STM32_STM32G05X - -config STM32_STM32G051 - bool - default n - select STM32_STM32G0 - select STM32_STM32G05X - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM15 - select STM32_HAVE_LPUART1 - -config STM32_STM32G05X - bool - default n - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - -config STM32_STM32G061 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_LPUART1 - -config STM32_STM32G070 - bool - default n - select STM32_STM32G0 - select STM32_STM32G07X - -config STM32_STM32G071 - bool - default n - select STM32_STM32G0 - select STM32_STM32G07X - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_CEC - select STM32_HAVE_LPUART1 - -config STM32_STM32G07X - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - -config STM32_STM32G081 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_CEC - select STM32_HAVE_LPUART1 - -config STM32_STM32G0B0 - bool - default n - select STM32_STM32G0 - select STM32_STM32G0BX - -config STM32_STM32G0B1 - bool - default n - select STM32_STM32G0 - select STM32_STM32G0BX - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_CEC - -config STM32_STM32G0BX - bool - default n - select STM32_HAVE_DMA2 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_USART6 - select STM32_HAVE_LPUART1 - select STM32_HAVE_LPUART2 - select STM32_HAVE_CRS - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S2 - select STM32_HAVE_USBDEV - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_HSI48 - -config STM32_STM32G0C1 - bool - default n - select STM32_STM32G0 - select STM32_HAVE_DMA2 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_USART6 - select STM32_HAVE_CRS - select STM32_HAVE_RNG - select STM32_HAVE_AES - select STM32_HAVE_DAC1 - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S2 - select STM32_HAVE_LPUART2 - select STM32_HAVE_USBDEV - select STM32_HAVE_UCPD1 - select STM32_HAVE_UCPD2 - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_CEC - select STM32_HAVE_HSI48 - -config STM32_ACCESSLINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - -config STM32_LOWVOLTLINE - bool - default n - select STM32_HAVE_USART5 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - -config STM32_USBLINE - bool - default n - select STM32_HAVE_HSI48 - select STM32_HAVE_CAN1 - select STM32_HAVE_SPI2 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32L053XX - bool - select STM32_STM32L0 - -config ARCH_CHIP_STM32L071XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - -config ARCH_CHIP_STM32L072XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_I2C2 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32L073XX - bool - select STM32_STM32L0 - select STM32_HAVE_RNG - select STM32_HAVE_HSI48 - select STM32_HAVE_USART4 - select STM32_HAVE_USART5 - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32C051XX - bool - select STM32_STM32C0 - -config ARCH_CHIP_STM32C071XX - bool - select STM32_STM32C0 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32C091XX - bool - select STM32_STM32C0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_TIM15 - -config ARCH_CHIP_STM32C092XX - bool - select STM32_STM32C0 - select STM32_HAVE_USART3 - select STM32_HAVE_USART4 - select STM32_HAVE_FDCAN1 diff --git a/arch/arm/src/stm32f0l0g0/stm32_rcc.h b/arch/arm/src/stm32f0l0g0/stm32_rcc.h deleted file mode 100644 index 3a45a94a0cd..00000000000 --- a/arch/arm/src/stm32f0l0g0/stm32_rcc.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32f0l0g0/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#include "hardware/stm32_rcc.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to initialize the STM32F0XX. - * This does whatever setup is needed to put the MCU in a usable state. - * This includes the initialization of clocking using the settings - * in board.h. - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#endif /* __ARCH_ARM_SRC_STM32F0L0G0_STM32_RCC_H */ diff --git a/boards/Kconfig b/boards/Kconfig index e2d689a9e0e..354c57d92b0 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -5207,13 +5207,10 @@ endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" endif -if ARCH_CHIP_STM32 -source "boards/arm/common/stm32/Kconfig" -endif if ARCH_CHIP_STM32F7 source "boards/arm/stm32f7/common/Kconfig" endif -if ARCH_CHIP_STM32F0L0G0 +if ARCH_CHIP_STM32C0 || ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32L1 source "boards/arm/common/stm32/Kconfig" endif if ARCH_CHIP_RP2040 diff --git a/boards/arm/stm32f0l0g0/common/CMakeLists.txt b/boards/arm/stm32c0/common/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/common/CMakeLists.txt rename to boards/arm/stm32c0/common/CMakeLists.txt index 3168617cea3..a792a3d2dc6 100644 --- a/boards/arm/stm32f0l0g0/common/CMakeLists.txt +++ b/boards/arm/stm32c0/common/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/common/CMakeLists.txt +# boards/arm/stm32c0/common/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/common/Kconfig b/boards/arm/stm32c0/common/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/common/Kconfig rename to boards/arm/stm32c0/common/Kconfig diff --git a/boards/arm/stm32f0l0g0/common/Makefile b/boards/arm/stm32c0/common/Makefile similarity index 97% rename from boards/arm/stm32f0l0g0/common/Makefile rename to boards/arm/stm32c0/common/Makefile index 43855190fc6..667cd9d3c44 100644 --- a/boards/arm/stm32f0l0g0/common/Makefile +++ b/boards/arm/stm32c0/common/Makefile @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32f0l0g0/common/Makefile +# boards/arm/stm32c0/common/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt index 1eaec21dd1a..84bb8fe3c7b 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c071rb/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig b/boards/arm/stm32c0/nucleo-c071rb/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig rename to boards/arm/stm32c0/nucleo-c071rb/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig index 3803bc20d69..c203fd3be4d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/adcscope/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/adcscope/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig index 06f620204ed..6851bb112d3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/jumbo/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/jumbo/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig rename to boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig index 105e69b35bd..5849d3ab45d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/configs/nsh/defconfig +++ b/boards/arm/stm32c0/nucleo-c071rb/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c071rb" CONFIG_ARCH_BOARD_NUCLEO_C071RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C071RB=y CONFIG_ARCH_CHIP_STM32C071XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h b/boards/arm/stm32c0/nucleo-c071rb/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h rename to boards/arm/stm32c0/nucleo-c071rb/include/board.h index 5ca9fdd6cfa..500badf7dcb 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h +++ b/boards/arm/stm32c0/nucleo-c071rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/include/board.h + * boards/arm/stm32c0/nucleo-c071rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs rename to boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs index 58cbdee0271..50ef07255e8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/Make.defs +# boards/arm/stm32c0/nucleo-c071rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld rename to boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld index a522204b0c1..d8da09abcd0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld +++ b/boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/flash.ld + * boards/arm/stm32c0/nucleo-c071rb/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt index 2d327d8c106..0639871c1d3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c071rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs rename to boards/arm/stm32c0/nucleo-c071rb/src/Make.defs index a89ade51216..335741d9e20 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs +++ b/boards/arm/stm32c0/nucleo-c071rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/src/Make.defs +# boards/arm/stm32c0/nucleo-c071rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h rename to boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h index 62e686e1c56..58b351b36a3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h +++ b/boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/nucleo-c071rb.h + * boards/arm/stm32c0/nucleo-c071rb/src/nucleo-c071rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c index 25a62741c1c..8b0e2ebc7b1 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_adc.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c index 86ed1091a04..aa077728f35 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_autoleds.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c index 67acc29262f..8750e264317 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_boot.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c index 139d760fc25..d85f3e4d8d9 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_bringup.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c index bc9ffb41367..82d2a8e704f 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_buttons.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c rename to boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c index 2ee610d173f..525b1264992 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c +++ b/boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c071rb/src/stm32_userleds.c + * boards/arm/stm32c0/nucleo-c071rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt similarity index 94% rename from boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt index b94721d67af..a30b26ee4f4 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g071rb/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c092rc/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig b/boards/arm/stm32c0/nucleo-c092rc/Kconfig similarity index 100% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig rename to boards/arm/stm32c0/nucleo-c092rc/Kconfig diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig index d9a948b94c4..1a2ebdb4185 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/can/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/can/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig index 6a9589eea45..57d858f02bd 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/cansock/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/cansock/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig index c135e688fcc..bd38abc3918 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/jumbo/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/jumbo/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig rename to boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig index 665917285bf..718871956d3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/configs/nsh/defconfig +++ b/boards/arm/stm32c0/nucleo-c092rc/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-c092rc" CONFIG_ARCH_BOARD_NUCLEO_C092RC=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32f0l0g0" +CONFIG_ARCH_CHIP="stm32c0" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32C092RC=y CONFIG_ARCH_CHIP_STM32C092XX=y diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h b/boards/arm/stm32c0/nucleo-c092rc/include/board.h similarity index 99% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h rename to boards/arm/stm32c0/nucleo-c092rc/include/board.h index f85f0b12044..0422106dda3 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h +++ b/boards/arm/stm32c0/nucleo-c092rc/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/include/board.h + * boards/arm/stm32c0/nucleo-c092rc/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs rename to boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs index 1e325f2a9bf..dad81a59c24 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c071rb/scripts/Make.defs +# boards/arm/stm32c0/nucleo-c092rc/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld rename to boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld index 675eb647b5b..83f188550d8 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld +++ b/boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/scripts/flash.ld + * boards/arm/stm32c0/nucleo-c092rc/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt rename to boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt index eacf44fab25..0ab1b18faa2 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +++ b/boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/CMakeLists.txt +# boards/arm/stm32c0/nucleo-c092rc/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs similarity index 96% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs rename to boards/arm/stm32c0/nucleo-c092rc/src/Make.defs index b6701ee29bf..74c27aa25f7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +++ b/boards/arm/stm32c0/nucleo-c092rc/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/nucleo-c092rc/src/Make.defs +# boards/arm/stm32c0/nucleo-c092rc/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h rename to boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h index f7ab2300b19..85f594562c7 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h +++ b/boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/nucleo-c092rc.h + * boards/arm/stm32c0/nucleo-c092rc/src/nucleo-c092rc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c index 51a76e9d591..777e65c018e 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_adc.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c index 016eca350de..e43d5cf6749 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_autoleds.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c index 29e95219a8e..d60d9f20b37 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_boot.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c index eb5bb09a60f..8f631a46a2c 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_bringup.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c index 06501f3b4ff..c5659c8f6cc 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_buttons.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c index b51e5ba4d4d..d2ba35278e0 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_can.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c index a1a4bcb89b2..8a24931b13d 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_cansock.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c rename to boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c index 77b08b2f3a8..5740dc20b90 100644 --- a/boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c +++ b/boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32f0l0g0/nucleo-c092rc/src/stm32_userleds.c + * boards/arm/stm32c0/nucleo-c092rc/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs b/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs deleted file mode 100644 index cede66c2c89..00000000000 --- a/boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/b-l072z-lrwan1/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt deleted file mode 100644 index 03f3ea5a665..00000000000 --- a/boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-f072rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt deleted file mode 100644 index f161ea4448a..00000000000 --- a/boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-g0b1re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt b/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt deleted file mode 100644 index 79eec2b120d..00000000000 --- a/boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/nucleo-l073rz/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt deleted file mode 100644 index 3097fc40425..00000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f051-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs deleted file mode 100644 index 5d941d50d5a..00000000000 --- a/boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt deleted file mode 100644 index 46b3a6cd11d..00000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32f072-discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs deleted file mode 100644 index 5d8a0c14523..00000000000 --- a/boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32f072-discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = flash.ld -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt deleted file mode 100644 index 9dcefda96ea..00000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32g071b-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs b/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs deleted file mode 100644 index 8679bdc9fcd..00000000000 --- a/boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32f0l0g0/stm32g071b-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt b/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt deleted file mode 100644 index 367387d199b..00000000000 --- a/boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32f0l0g0/stm32l0538-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) From e21a15eb4e684999b868ac53b67af79ebf9ceb38 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 155/268] !arch/stm32: move stm32f1 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f1 sources, headers and boards into arch/arm/src/stm32f1, arch/arm/include/stm32f1 and boards/arm/stm32f1. Signed-off-by: raiden00pl --- arch/arm/include/stm32f1/chip.h | 495 ++++++++++++++++++ .../stm32f10xxx_irq.h => stm32f1/irq.h} | 80 ++- arch/arm/src/stm32f1/CMakeLists.txt | 28 + arch/arm/src/stm32f1/Kconfig | 486 +++++++++++++++++ arch/arm/src/stm32f1/Kconfig.pinmap | 182 +++++++ arch/arm/src/stm32f1/Make.defs | 27 + arch/arm/src/{stm32 => stm32f1}/chip.h | 12 +- .../src/stm32f1/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32f1/hardware/stm32_pinmap.h | 46 ++ .../hardware/stm32f100_pinmap.h | 2 +- .../hardware/stm32f102_pinmap.h | 2 +- .../hardware/stm32f103c_pinmap.h | 2 +- .../hardware/stm32f103r_pinmap.h | 2 +- .../hardware/stm32f103v_pinmap.h | 2 +- .../hardware/stm32f103z_pinmap.h | 2 +- .../hardware/stm32f105r_pinmap.h | 2 +- .../hardware/stm32f105v_pinmap.h | 2 +- .../hardware/stm32f107v_pinmap.h | 2 +- .../hardware/stm32f10xxx_gpio.h | 2 +- .../hardware/stm32f10xxx_memorymap.h | 2 +- .../hardware/stm32f10xxx_rcc.h | 2 +- arch/arm/src/{stm32 => stm32f1}/stm32.h | 16 +- arch/arm/src/stm32f1/stm32_rcc.c | 234 +++++++++ .../src/{stm32 => stm32f1}/stm32f10xxx_rcc.c | 2 +- .../cloudctrl}/CMakeLists.txt | 2 +- .../arm/{stm32 => stm32f1}/cloudctrl/Kconfig | 0 .../cloudctrl/configs/nsh/defconfig | 2 +- .../cloudctrl/include/board.h | 2 +- .../cloudctrl/scripts/Make.defs | 2 +- .../cloudctrl/scripts/cloudctrl-dfu.ld | 2 +- .../cloudctrl/scripts/cloudctrl.ld | 2 +- .../cloudctrl/src/CMakeLists.txt | 2 +- .../cloudctrl/src/Make.defs | 2 +- .../cloudctrl/src/cloudctrl.h | 2 +- .../cloudctrl/src/stm32_adc.c | 2 +- .../cloudctrl/src/stm32_autoleds.c | 2 +- .../cloudctrl/src/stm32_boot.c | 2 +- .../cloudctrl/src/stm32_buttons.c | 2 +- .../cloudctrl/src/stm32_chipid.c | 2 +- .../cloudctrl/src/stm32_phyinit.c | 2 +- .../cloudctrl/src/stm32_relays.c | 2 +- .../cloudctrl/src/stm32_spi.c | 2 +- .../cloudctrl/src/stm32_usb.c | 2 +- .../cloudctrl/src/stm32_usbmsc.c | 2 +- .../cloudctrl/src/stm32_userleds.c | 2 +- .../cloudctrl/src/stm32_w25.c | 2 +- .../cloudctrl/tools/olimex-arm-usb-ocd.cfg | 0 .../cloudctrl/tools/oocd.sh | 0 .../cloudctrl/tools/stm32.cfg | 0 .../cloudctrl/tools/usb-driver.txt | 0 .../{stm32 => stm32f1}/common/CMakeLists.txt | 2 +- boards/arm/{stm32 => stm32f1}/common/Kconfig | 0 boards/arm/{stm32 => stm32f1}/common/Makefile | 2 +- .../arm/stm32f1/et-stm32-stamp/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/et-stm32-stamp/Kconfig | 0 .../et-stm32-stamp/configs/nsh/defconfig | 2 +- .../et-stm32-stamp/include/board.h | 2 +- .../stm32f1/et-stm32-stamp/scripts/Make.defs | 41 ++ .../et-stm32-stamp/scripts/ld.script | 2 +- .../et-stm32-stamp/src/CMakeLists.txt | 2 +- .../et-stm32-stamp/src/Make.defs | 2 +- .../et-stm32-stamp/src/et-stm32-stamp.h | 4 +- .../et-stm32-stamp/src/stm32_boot.c | 2 +- .../fire-stm32v2}/CMakeLists.txt | 2 +- .../{stm32 => stm32f1}/fire-stm32v2/Kconfig | 0 .../fire-stm32v2/configs/nsh/defconfig | 2 +- .../fire-stm32v2/include/board.h | 2 +- .../fire-stm32v2/scripts/Make.defs | 2 +- .../fire-stm32v2/scripts/fire-stm32v2-dfu.ld | 2 +- .../fire-stm32v2/scripts/fire-stm32v2.ld | 2 +- .../fire-stm32v2/src/CMakeLists.txt | 2 +- .../fire-stm32v2/src/Make.defs | 2 +- .../fire-stm32v2/src/fire-stm32v2.h | 2 +- .../fire-stm32v2/src/stm32_autoleds.c | 2 +- .../fire-stm32v2/src/stm32_boot.c | 2 +- .../fire-stm32v2/src/stm32_buttons.c | 2 +- .../fire-stm32v2/src/stm32_enc28j60.c | 2 +- .../fire-stm32v2/src/stm32_mmcsd.c | 2 +- .../fire-stm32v2/src/stm32_selectlcd.c | 2 +- .../fire-stm32v2/src/stm32_spi.c | 2 +- .../fire-stm32v2/src/stm32_usbdev.c | 2 +- .../fire-stm32v2/src/stm32_usbmsc.c | 2 +- .../fire-stm32v2/src/stm32_userleds.c | 2 +- .../fire-stm32v2/src/stm32_w25.c | 2 +- .../arm/stm32f1/hymini-stm32v/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/hymini-stm32v/Kconfig | 0 .../hymini-stm32v/configs/nsh/defconfig | 2 +- .../hymini-stm32v/configs/nsh2/defconfig | 2 +- .../hymini-stm32v/configs/usbmsc/defconfig | 2 +- .../hymini-stm32v/configs/usbnsh/defconfig | 2 +- .../hymini-stm32v/configs/usbserial/defconfig | 2 +- .../hymini-stm32v/include/board.h | 2 +- .../hymini-stm32v/scripts/Make.defs | 2 +- .../hymini-stm32v/scripts/ld.script | 2 +- .../hymini-stm32v/src/CMakeLists.txt | 2 +- .../hymini-stm32v/src/Make.defs | 2 +- .../hymini-stm32v/src/hymini-stm32v.h | 4 +- .../hymini-stm32v/src/stm32_boot.c | 2 +- .../hymini-stm32v/src/stm32_buttons.c | 2 +- .../hymini-stm32v/src/stm32_leds.c | 2 +- .../hymini-stm32v/src/stm32_r61505u.c | 2 +- .../hymini-stm32v/src/stm32_spi.c | 2 +- .../hymini-stm32v/src/stm32_ssd1289.c | 2 +- .../hymini-stm32v/src/stm32_ts.c | 2 +- .../hymini-stm32v/src/stm32_usbdev.c | 2 +- .../hymini-stm32v/src/stm32_usbmsc.c | 2 +- .../axoloti => stm32f1/maple}/CMakeLists.txt | 2 +- boards/arm/{stm32 => stm32f1}/maple/Kconfig | 0 .../maple/configs/nsh/defconfig | 2 +- .../maple/configs/nx/defconfig | 2 +- .../maple/configs/usbnsh/defconfig | 2 +- .../{stm32 => stm32f1}/maple/include/board.h | 2 +- .../maple/scripts/Make.defs | 2 +- .../maple/scripts/ld.script | 2 +- .../maple/scripts/ld.script.dfu | 2 +- .../maple/src/CMakeLists.txt | 2 +- .../{stm32 => stm32f1}/maple/src/Make.defs | 2 +- .../arm/{stm32 => stm32f1}/maple/src/maple.h | 4 +- .../{stm32 => stm32f1}/maple/src/stm32_boot.c | 2 +- .../{stm32 => stm32f1}/maple/src/stm32_lcd.c | 2 +- .../{stm32 => stm32f1}/maple/src/stm32_leds.c | 2 +- .../{stm32 => stm32f1}/maple/src/stm32_spi.c | 2 +- .../maple/src/stm32_usbdev.c | 2 +- .../arm/{stm32 => stm32f1}/maple/tools/dfu.sh | 0 .../arm/{stm32 => stm32f1}/maple/tools/env.sh | 0 .../arm/stm32f1/nucleo-f103rb/CMakeLists.txt | 23 + .../{stm32 => stm32f1}/nucleo-f103rb/Kconfig | 0 .../nucleo-f103rb/configs/adc/defconfig | 2 +- .../configs/ihm07m1_b16/defconfig | 2 +- .../nucleo-f103rb/configs/nsh/defconfig | 2 +- .../nucleo-f103rb/configs/pwm/defconfig | 2 +- .../nucleo-f103rb/configs/qenco/defconfig | 2 +- .../nucleo-f103rb/include/board.h | 2 +- .../nucleo-f103rb}/scripts/Make.defs | 2 +- .../nucleo-f103rb/scripts/ld.script | 2 +- .../nucleo-f103rb/src/CMakeLists.txt | 2 +- .../nucleo-f103rb/src/Make.defs | 2 +- .../nucleo-f103rb/src/nucleo-f103rb.h | 2 +- .../nucleo-f103rb/src/stm32_adc.c | 2 +- .../nucleo-f103rb/src/stm32_autoleds.c | 2 +- .../nucleo-f103rb/src/stm32_boot.c | 2 +- .../nucleo-f103rb/src/stm32_bringup.c | 2 +- .../nucleo-f103rb/src/stm32_buttons.c | 2 +- .../nucleo-f103rb/src/stm32_foc_ihm07m1.c | 2 +- .../nucleo-f103rb/src/stm32_pwm.c | 2 +- .../nucleo-f103rb/src/stm32_userleds.c | 2 +- .../stm32f1/olimex-stm32-p107/CMakeLists.txt | 23 + .../olimex-stm32-p107/Kconfig | 0 .../olimex-stm32-p107/configs/nsh/defconfig | 2 +- .../olimex-stm32-p107/include/board.h | 2 +- .../olimex-stm32-p107/scripts/Make.defs | 2 +- .../olimex-stm32-p107/scripts/ld.script | 2 +- .../olimex-stm32-p107/scripts/ld.script.dfu | 2 +- .../olimex-stm32-p107/src/CMakeLists.txt | 2 +- .../olimex-stm32-p107/src/Make.defs | 2 +- .../olimex-stm32-p107/src/olimex-stm32-p107.h | 2 +- .../olimex-stm32-p107/src/stm32_boot.c | 2 +- .../olimex-stm32-p107/src/stm32_can.c | 2 +- .../olimex-stm32-p107/src/stm32_encx24j600.c | 2 +- .../olimex-stm32-p107/src/stm32_spi.c | 2 +- .../stm32f1/olimexino-stm32/CMakeLists.txt | 23 + .../olimexino-stm32/Kconfig | 0 .../olimexino-stm32/configs/can/defconfig | 2 +- .../configs/composite/defconfig | 2 +- .../olimexino-stm32/configs/nsh/defconfig | 2 +- .../configs/smallnsh/defconfig | 2 +- .../olimexino-stm32/configs/tiny/defconfig | 2 +- .../olimexino-stm32/include/board.h | 2 +- .../olimexino-stm32/scripts/Make.defs | 2 +- .../olimexino-stm32/scripts/ld.script | 2 +- .../olimexino-stm32/scripts/ld.script.dfu | 2 +- .../olimexino-stm32/src/CMakeLists.txt | 2 +- .../olimexino-stm32/src/Make.defs | 2 +- .../olimexino-stm32/src/olimexino-stm32.h | 2 +- .../olimexino-stm32/src/stm32_boot.c | 2 +- .../olimexino-stm32/src/stm32_buttons.c | 2 +- .../olimexino-stm32/src/stm32_can.c | 2 +- .../olimexino-stm32/src/stm32_composite.c | 2 +- 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.../stm3210e-eval/src/stm32_pm.c | 2 +- .../stm3210e-eval/src/stm32_pmbuttons.c | 2 +- .../stm3210e-eval/src/stm32_selectlcd.c | 2 +- .../stm3210e-eval/src/stm32_selectnor.c | 2 +- .../stm3210e-eval/src/stm32_selectsram.c | 2 +- .../stm3210e-eval/src/stm32_spi.c | 2 +- .../stm3210e-eval/src/stm32_usbdev.c | 2 +- .../stm3210e-eval/src/stm32_usbmsc.c | 2 +- .../tools/olimex-arm-usb-ocd.cfg | 0 .../stm3210e-eval/tools/oocd.sh | 2 +- .../stm3210e-eval/tools/stm32.cfg | 0 .../stm3210e-eval/tools/usb-driver.txt | 0 boards/arm/stm32f1/stm32_tiny/CMakeLists.txt | 23 + .../arm/{stm32 => stm32f1}/stm32_tiny/Kconfig | 0 .../stm32_tiny/configs/nsh/defconfig | 2 +- .../stm32_tiny/configs/usbnsh/defconfig | 2 +- .../stm32_tiny/include/board.h | 2 +- .../stm32_tiny}/scripts/Make.defs | 2 +- .../stm32_tiny/scripts/ld.script | 2 +- .../stm32_tiny/src/CMakeLists.txt | 2 +- .../stm32_tiny/src/Make.defs | 2 +- .../stm32_tiny/src/stm32_boot.c | 2 +- .../stm32_tiny/src/stm32_leds.c | 2 +- .../stm32_tiny/src/stm32_pwm.c | 2 +- .../stm32_tiny/src/stm32_spi.c | 2 +- .../stm32_tiny/src/stm32_tiny.h | 2 +- .../stm32_tiny/src/stm32_usbdev.c | 2 +- .../stm32f1/stm32butterfly2/CMakeLists.txt | 23 + .../stm32butterfly2/Kconfig | 0 .../stm32butterfly2/configs/nsh/defconfig | 2 +- .../stm32butterfly2/configs/nshnet/defconfig | 2 +- .../configs/nshusbdev/defconfig | 2 +- .../configs/nshusbhost/defconfig | 2 +- .../stm32butterfly2/include/board.h | 2 +- .../stm32butterfly2/scripts/Make.defs | 2 +- .../stm32butterfly2/scripts/dfu.ld | 2 +- .../stm32butterfly2/scripts/flash.ld | 2 +- .../stm32butterfly2/src/CMakeLists.txt | 2 +- .../stm32butterfly2/src/Make.defs | 2 +- .../stm32butterfly2/src/stm32_adc.c | 2 +- .../stm32butterfly2/src/stm32_boot.c | 2 +- .../stm32butterfly2/src/stm32_butterfly2.h | 2 +- .../stm32butterfly2/src/stm32_buttons.c | 2 +- .../stm32butterfly2/src/stm32_leds.c | 2 +- .../stm32butterfly2/src/stm32_mmcsd.c | 2 +- .../stm32butterfly2/src/stm32_spi.c | 2 +- .../stm32butterfly2/src/stm32_usb.c | 2 +- .../stm32butterfly2/src/stm32_usbdev.c | 2 +- .../stm32butterfly2/src/stm32_usbhost.c | 2 +- .../stm32f1/stm32f103-minimum/CMakeLists.txt | 23 + .../stm32f103-minimum/Kconfig | 0 .../stm32f103-minimum/configs/adb/defconfig | 2 +- .../configs/apds9960/defconfig | 2 +- .../configs/audio_tone/defconfig | 2 +- .../configs/buttons/defconfig | 2 +- .../stm32f103-minimum/configs/can/defconfig | 2 +- .../stm32f103-minimum/configs/hello/defconfig | 2 +- .../configs/jlx12864g/defconfig | 2 +- .../configs/lcd1602/defconfig | 2 +- .../configs/mcp2515/defconfig | 2 +- .../stm32f103-minimum/configs/nrf24/defconfig | 2 +- .../stm32f103-minimum/configs/nsh/defconfig | 2 +- .../stm32f103-minimum/configs/pwm/defconfig | 2 +- .../configs/rfid-rc522/defconfig | 2 +- .../configs/rgbled/defconfig | 2 +- .../configs/sensors/defconfig | 2 +- .../configs/ssd1306/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../configs/userled/defconfig | 2 +- .../configs/veml6070/defconfig | 2 +- .../stm32f103-minimum/include/board.h | 2 +- .../stm32f103-minimum/scripts/Make.defs | 2 +- .../stm32f103-minimum/scripts/ld.script | 2 +- .../stm32f103-minimum/scripts/ld.script.dfu | 2 +- .../stm32f103-minimum/src/CMakeLists.txt | 2 +- .../stm32f103-minimum/src/Make.defs | 2 +- .../stm32f103-minimum/src/stm32_adc.c | 2 +- .../stm32f103-minimum/src/stm32_at24.c | 2 +- .../stm32f103-minimum/src/stm32_autoleds.c | 2 +- .../stm32f103-minimum/src/stm32_boot.c | 2 +- .../stm32f103-minimum/src/stm32_bringup.c | 2 +- .../stm32f103-minimum/src/stm32_buttons.c | 2 +- .../stm32f103-minimum/src/stm32_can.c | 2 +- .../stm32f103-minimum/src/stm32_cansock.c | 2 +- .../stm32f103-minimum/src/stm32_ds18b20.c | 2 +- .../stm32f103-minimum/src/stm32_gpio.c | 2 +- .../stm32f103-minimum/src/stm32_hyt271.c | 2 +- .../stm32f103-minimum/src/stm32_lcd_ssd1306.c | 2 +- .../stm32f103-minimum/src/stm32_lcd_st7567.c | 2 +- .../stm32f103-minimum/src/stm32_max7219.c | 2 +- .../stm32f103-minimum/src/stm32_mcp2515.c | 2 +- .../stm32f103-minimum/src/stm32_mmcsd.c | 2 +- .../stm32f103-minimum/src/stm32_pcd8544.c | 2 +- .../stm32f103-minimum/src/stm32_pwm.c | 2 +- .../stm32f103-minimum/src/stm32_reset.c | 3 +- .../stm32f103-minimum/src/stm32_rgbled.c | 2 +- .../stm32f103-minimum/src/stm32_spi.c | 2 +- .../stm32f103-minimum/src/stm32_usbdev.c | 2 +- .../stm32f103-minimum/src/stm32_usbmsc.c | 2 +- .../stm32f103-minimum/src/stm32_userleds.c | 2 +- .../stm32f103-minimum/src/stm32_w25.c | 2 +- .../stm32f103-minimum/src/stm32f103_minimum.h | 2 +- .../stm32f1/stm32vldiscovery/CMakeLists.txt | 23 + .../stm32vldiscovery/Kconfig | 0 .../stm32vldiscovery/configs/nsh/defconfig | 2 +- .../stm32vldiscovery/include/board.h | 2 +- .../stm32vldiscovery/scripts/Make.defs | 2 +- .../scripts/stm32vldiscovery.ld | 2 +- .../stm32vldiscovery/src/CMakeLists.txt | 2 +- .../stm32vldiscovery/src/Make.defs | 2 +- .../stm32vldiscovery/src/stm32_boot.c | 2 +- .../stm32vldiscovery/src/stm32_bringup.c | 2 +- .../stm32vldiscovery/src/stm32_buttons.c | 2 +- .../stm32vldiscovery/src/stm32_leds.c | 2 +- .../stm32vldiscovery/src/stm32vldiscovery.h | 2 +- .../stm32f1/viewtool-stm32f107/CMakeLists.txt | 23 + .../viewtool-stm32f107/Kconfig | 0 .../configs/ft80x/defconfig | 2 +- .../configs/highpri/defconfig | 2 +- .../configs/netnsh/defconfig | 2 +- .../viewtool-stm32f107/configs/nsh/defconfig | 2 +- .../configs/tcpblaster/defconfig | 2 +- .../include/board-stm32f103vct6.h | 2 +- .../include/board-stm32f107vct6.h | 2 +- .../viewtool-stm32f107/include/board.h | 2 +- .../viewtool-stm32f107/scripts/Make.defs | 2 +- .../viewtool-stm32f107/scripts/dfu.ld | 2 +- .../viewtool-stm32f107/scripts/flash.ld | 2 +- .../viewtool-stm32f107/src/CMakeLists.txt | 2 +- .../viewtool-stm32f107/src/Make.defs | 2 +- .../viewtool-stm32f107/src/stm32_ads7843e.c | 2 +- .../viewtool-stm32f107/src/stm32_boot.c | 2 +- .../viewtool-stm32f107/src/stm32_bringup.c | 2 +- .../viewtool-stm32f107/src/stm32_buttons.c | 2 +- .../viewtool-stm32f107/src/stm32_can.c | 2 +- .../viewtool-stm32f107/src/stm32_ft80x.c | 2 +- .../viewtool-stm32f107/src/stm32_highpri.c | 2 +- .../viewtool-stm32f107/src/stm32_leds.c | 2 +- .../viewtool-stm32f107/src/stm32_max3421e.c | 2 +- .../viewtool-stm32f107/src/stm32_mmcsd.c | 2 +- .../viewtool-stm32f107/src/stm32_spi.c | 2 +- .../viewtool-stm32f107/src/stm32_ssd1289.c | 2 +- .../viewtool-stm32f107/src/stm32_usbdev.c | 2 +- .../viewtool-stm32f107/src/stm32_usbmsc.c | 2 +- .../src/viewtool_stm32f107.h | 2 +- 391 files changed, 2201 insertions(+), 405 deletions(-) create mode 100644 arch/arm/include/stm32f1/chip.h rename arch/arm/include/{stm32/stm32f10xxx_irq.h => stm32f1/irq.h} (91%) create mode 100644 arch/arm/src/stm32f1/CMakeLists.txt create mode 100644 arch/arm/src/stm32f1/Kconfig create mode 100644 arch/arm/src/stm32f1/Kconfig.pinmap create mode 100644 arch/arm/src/stm32f1/Make.defs rename arch/arm/src/{stm32 => stm32f1}/chip.h (90%) create mode 100644 arch/arm/src/stm32f1/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f1/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f100_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f102_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103c_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103r_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103v_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f103z_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f105r_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f105v_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f107v_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f10xxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f10xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f1}/hardware/stm32f10xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f1}/stm32.h (88%) create mode 100644 arch/arm/src/stm32f1/stm32_rcc.c rename arch/arm/src/{stm32 => stm32f1}/stm32f10xxx_rcc.c (99%) rename boards/arm/{stm32/b-g431b-esc1 => stm32f1/cloudctrl}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/Kconfig (100%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/include/board.h (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/scripts/cloudctrl-dfu.ld (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/scripts/cloudctrl.ld (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/cloudctrl.h (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_adc.c (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_autoleds.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_buttons.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_chipid.c (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_phyinit.c (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_relays.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_usbmsc.c (97%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_userleds.c (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/src/stm32_w25.c (98%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/tools/olimex-arm-usb-ocd.cfg (100%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/tools/oocd.sh (100%) rename boards/arm/{stm32 => stm32f1}/cloudctrl/tools/stm32.cfg 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stm32f1}/stm32butterfly2/src/stm32_butterfly2.h (98%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_leds.c (99%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_mmcsd.c (99%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_spi.c (98%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_usb.c (97%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_usbdev.c (97%) rename boards/arm/{stm32 => stm32f1}/stm32butterfly2/src/stm32_usbhost.c (98%) create mode 100644 boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt rename boards/arm/{stm32 => stm32f1}/stm32f103-minimum/Kconfig (100%) rename boards/arm/{stm32 => stm32f1}/stm32f103-minimum/configs/adb/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/stm32f103-minimum/configs/apds9960/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/stm32f103-minimum/configs/audio_tone/defconfig (98%) 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stm32f1}/stm32f103-minimum/src/stm32f103_minimum.h (99%) create mode 100644 boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/Kconfig (100%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/include/board.h (98%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/scripts/Make.defs (96%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/scripts/stm32vldiscovery.ld (98%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/Make.defs (95%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/stm32_bringup.c (97%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/stm32_leds.c (97%) rename boards/arm/{stm32 => stm32f1}/stm32vldiscovery/src/stm32vldiscovery.h (97%) create mode 100644 boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/Kconfig (100%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/configs/ft80x/defconfig (97%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/configs/highpri/defconfig (97%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/configs/netnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/configs/tcpblaster/defconfig (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/include/board-stm32f103vct6.h (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/include/board-stm32f107vct6.h (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/include/board.h (99%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/scripts/Make.defs (96%) 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stm32f1}/viewtool-stm32f107/src/stm32_max3421e.c (99%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/stm32_mmcsd.c (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/stm32_ssd1289.c (99%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/stm32_usbdev.c (98%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/stm32_usbmsc.c (97%) rename boards/arm/{stm32 => stm32f1}/viewtool-stm32f107/src/viewtool_stm32f107.h (99%) diff --git a/arch/arm/include/stm32f1/chip.h b/arch/arm/include/stm32f1/chip.h new file mode 100644 index 00000000000..a216966d478 --- /dev/null +++ b/arch/arm/include/stm32f1/chip.h @@ -0,0 +1,495 @@ +/**************************************************************************** + * arch/arm/include/stm32f1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ + || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 3 additional timers (15-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 High-density value Line ***************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100RE) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 64 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ + || defined(CONFIG_ARCH_CHIP_STM32F100VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ + +/* TODO: there are also 6 additional timers (12-17) + * that don't fit any existing category + */ + +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timer TIM1 */ +# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-D */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC1 */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Low Density Family ********************************************/ + +/* STM32F103C4 & STM32F103C6 */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 2 /* General timers TIM2,3 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timer */ +# define STM32_NDMA 1 /* DMA1 */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 Medium Density Performance Line *******************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 1 /* SPI1 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 26 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-C */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 3 /* General timers TIM2-4 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 1 /* DMA1, 7 channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F103 High Density Family *******************************************/ + +/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-D */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* General timers TIM2-5 */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* bxCAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 3 /* ADC1-3 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin + * packages and differ only in the available FLASH and SRAM. + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timer TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 0 /* No I2S (?) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 1 /* CAN1 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 112 /* GPIOA-G */ +# define STM32_NADC 1 /* ADC1 */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F105/F107 Connectivity Line ****************************************/ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2 */ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ +# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* I2C1 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 80 /* GPIOA-E */ +# define STM32_NADC 2 /* ADC1-2*/ +# define STM32_NDAC 2 /* DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F2 Family **********************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F1_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32f1/irq.h similarity index 91% rename from arch/arm/include/stm32/stm32f10xxx_irq.h rename to arch/arm/include/stm32f1/irq.h index 52d1b038f78..50020cb6d58 100644 --- a/arch/arm/include/stm32/stm32f10xxx_irq.h +++ b/arch/arm/include/stm32f1/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f10xxx_irq.h + * arch/arm/include/stm32f1/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,8 +24,8 @@ * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F1_IRQ_H /**************************************************************************** * Included Files @@ -33,22 +33,43 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. */ -/* Value line devices */ +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ #if defined(CONFIG_STM32_VALUELINE) # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ @@ -118,8 +139,6 @@ # define STM32_IRQ_NEXTINTS (61) -/* Connectivity Line Devices */ - #elif defined(CONFIG_STM32_CONNECTIVITYLINE) # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ @@ -192,8 +211,6 @@ # define STM32_IRQ_NEXTINTS (68) -/* Medium and High Density Devices */ - #else # define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */ @@ -258,8 +275,6 @@ # define STM32_IRQ_NEXTINTS (60) -/* Convenience definitions for interrupts with multiple functions */ - # define STM32_IRQ_USBHP STM32_IRQ_USBHPCANTX # define STM32_IRQ_CAN1TX STM32_IRQ_USBHPCANTX # define STM32_IRQ_USBLP STM32_IRQ_USBLPCANRX0 @@ -268,31 +283,4 @@ # define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F10XXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F1_IRQ_H */ diff --git a/arch/arm/src/stm32f1/CMakeLists.txt b/arch/arm/src/stm32f1/CMakeLists.txt new file mode 100644 index 00000000000..2126b9b6e33 --- /dev/null +++ b/arch/arm/src/stm32f1/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f1/Kconfig b/arch/arm/src/stm32f1/Kconfig new file mode 100644 index 00000000000..a14872ed7c7 --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig @@ -0,0 +1,486 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F1 configuration" + +if ARCH_CHIP_STM32F1 + +choice + prompt "STM32F1 Chip Selection" + default ARCH_CHIP_STM32F103ZE + depends on ARCH_CHIP_STM32F1 + +config ARCH_CHIP_STM32F100C8 + bool "STM32F100C8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100CB + bool "STM32F100CB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100R8 + bool "STM32F100R8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RB + bool "STM32F100RB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RC + bool "STM32F100RC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RD + bool "STM32F100RD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100RE + bool "STM32F100RE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100V8 + bool "STM32F100V8" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VB + bool "STM32F100VB" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VC + bool "STM32F100VC" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VD + bool "STM32F100VD" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F100VE + bool "STM32F100VE" + select STM32_STM32F10XX + select STM32F1_VALUELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F102CB + bool "STM32F102CB" + select STM32_STM32F10XX + select STM32F1_USBACCESSLINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103T8 + bool "STM32F103T8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103TB + bool "STM32F103TB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103C4 + bool "STM32F103C4" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_LOWDENSITY + +config ARCH_CHIP_STM32F103C8 + bool "STM32F103C8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103CB + bool "STM32F103CB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103R8 + bool "STM32F103R8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RB + bool "STM32F103RB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RC + bool "STM32F103RC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RD + bool "STM32F103RD" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RE + bool "STM32F103RE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103RG + bool "STM32F103RG" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103V8 + bool "STM32F103V8" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VB + bool "STM32F103VB" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_MEDIUMDENSITY + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VC + bool "STM32F103VC" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103VE + bool "STM32F103VE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F103ZE + bool "STM32F103ZE" + select STM32_STM32F10XX + select STM32F1_PERFORMANCELINE + select STM32F1_HIGHDENSITY + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105VB + bool "STM32F105VBT7" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F105RB + bool "STM32F105RB" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_TIM4 + +config ARCH_CHIP_STM32F107VC + bool "STM32F107VC" + select STM32_STM32F10XX + select STM32F1_CONNECTIVITYLINE + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM4 + +endchoice + +endif + +config STM32_STM32F10XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY + select ARCH_CORTEXM3 + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY || STM32F1_MEDIUMDENSITY + select STM32_HAVE_RTC_COUNTER + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKP + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V1 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32F1_VALUELINE + bool + default n + select STM32_VALUELINE + select STM32_HAVE_CEC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_SPI2 if STM32F1_HIGHDENSITY + select STM32_HAVE_SPI3 if STM32F1_HIGHDENSITY + +config STM32F1_CONNECTIVITYLINE + bool + default n + select STM32_CONNECTIVITYLINE + select STM32_HAVE_OTGFS + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + +config STM32F1_PERFORMANCELINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + +config STM32F1_USBACCESSLINE + bool + default n + select STM32_HAVE_USBDEV + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_SPI2 + +config STM32F1_MEDIUMPLUSDENSITY + bool + default n + +config STM32F1_HIGHDENSITY + bool + default n + select STM32_HIGHDENSITY + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_MEDIUMDENSITY + bool + default n + select STM32_MEDIUMDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32F1_LOWDENSITY + bool + default n + select STM32_LOWDENSITY + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 if !STM32F1_VALUELINE + +# Compatibility symbols kept private to STM32F1 selection. Existing driver +# code still keys off these historical names. + +config STM32_VALUELINE + bool + +config STM32_CONNECTIVITYLINE + bool + +config STM32_HIGHDENSITY + bool + +config STM32_MEDIUMDENSITY + bool + +config STM32_LOWDENSITY + bool + +source "arch/arm/src/stm32f1/Kconfig.pinmap" diff --git a/arch/arm/src/stm32f1/Kconfig.pinmap b/arch/arm/src/stm32f1/Kconfig.pinmap new file mode 100644 index 00000000000..f04d44944be --- /dev/null +++ b/arch/arm/src/stm32f1/Kconfig.pinmap @@ -0,0 +1,182 @@ +menu "Alternate Pin Mapping" + depends on STM32_STM32F10XX + +choice + prompt "CAN1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_CAN1 + default STM32_CAN1_NO_REMAP + +config STM32_CAN1_NO_REMAP + bool "No pin remapping" + +config STM32_CAN1_REMAP1 + bool "CAN1 alternate pin remapping #1" + +config STM32_CAN1_REMAP2 + bool "CAN1 alternate pin remapping #2" + +endchoice + +config STM32_CAN2_REMAP + bool "CAN2 Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_CAN2 + +config STM32_CEC_REMAP + bool "CEC Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_CEC + +config STM32_ETH_REMAP + bool "Ethernet Alternate Pin Mapping" + default n + depends on STM32F1_CONNECTIVITYLINE && STM32_ETHMAC + +config STM32_I2C1_REMAP + bool "I2C1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2C1 + +config STM32_SPI1_REMAP + bool "SPI1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI1 + +config STM32_SPI3_REMAP + bool "SPI3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_SPI3 && !STM32F1_VALUELINE + +config STM32_I2S3_REMAP + bool "I2S3 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_I2S3 && !STM32F1_VALUELINE + +choice + prompt "TIM1 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM1 + default STM32_TIM1_NO_REMAP + +config STM32_TIM1_NO_REMAP + bool "No pin remapping" + +config STM32_TIM1_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM1_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +choice + prompt "TIM2 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM2 + default STM32_TIM2_NO_REMAP + +config STM32_TIM2_NO_REMAP + bool "No pin remapping" + +config STM32_TIM2_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM2_PARTIAL_REMAP_1 + bool "Partial pin remapping #1" + +config STM32_TIM2_PARTIAL_REMAP_2 + bool "Partial pin remapping #2" + +endchoice + +choice + prompt "TIM3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_TIM3 + default STM32_TIM3_NO_REMAP + +config STM32_TIM3_NO_REMAP + bool "No pin remapping" + +config STM32_TIM3_FULL_REMAP + bool "Full pin remapping" + +config STM32_TIM3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +config STM32_TIM4_REMAP + bool "TIM4 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM4 + +config STM32_TIM9_REMAP + bool "TIM9 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM9 + +config STM32_TIM10_REMAP + bool "TIM10 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM10 + +config STM32_TIM11_REMAP + bool "TIM11 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM11 + +config STM32_TIM12_REMAP + bool "TIM12 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM12 + +config STM32_TIM13_REMAP + bool "TIM13 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM13 + +config STM32_TIM14_REMAP + bool "TIM14 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM14 + +config STM32_TIM15_REMAP + bool "TIM15 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM15 + +config STM32_TIM16_REMAP + bool "TIM16 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM16 + +config STM32_TIM17_REMAP + bool "TIM17 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_TIM17 + +config STM32_USART1_REMAP + bool "USART1 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART1 + +config STM32_USART2_REMAP + bool "USART2 Alternate Pin Mapping" + default n + depends on STM32_STM32F10XX && STM32_USART2 + +choice + prompt "USART3 Alternate Pin Mappings" + depends on STM32_STM32F10XX && STM32_USART3 + default STM32_USART3_NO_REMAP + +config STM32_USART3_NO_REMAP + bool "No pin remapping" + +config STM32_USART3_FULL_REMAP + bool "Full pin remapping" + +config STM32_USART3_PARTIAL_REMAP + bool "Partial pin remapping" + +endchoice + +endmenu diff --git a/arch/arm/src/stm32f1/Make.defs b/arch/arm/src/stm32f1/Make.defs new file mode 100644 index 00000000000..0f8a65ef5a8 --- /dev/null +++ b/arch/arm/src/stm32f1/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f1/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32f1/chip.h similarity index 90% rename from arch/arm/src/stm32/chip.h rename to arch/arm/src/stm32f1/chip.h index 295751fca51..9f3e121b8db 100644 --- a/arch/arm/src/stm32/chip.h +++ b/arch/arm/src/stm32f1/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/chip.h + * arch/arm/src/stm32f1/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_CHIP_H -#define __ARCH_ARM_SRC_STM32_CHIP_H +#ifndef __ARCH_ARM_SRC_STM32F1_CHIP_H +#define __ARCH_ARM_SRC_STM32F1_CHIP_H /**************************************************************************** * Included Files @@ -31,11 +31,11 @@ /* Include the chip capabilities file */ -#include +#include /* Include the chip interrupt definition file */ -#include +#include /* Include the chip memory map */ @@ -56,4 +56,4 @@ #define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS -#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */ +#endif /* __ARCH_ARM_SRC_STM32F1_CHIP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..027e14eaf9b --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f10xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f1/hardware/stm32_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..ed4b8e68f0f --- /dev/null +++ b/arch/arm/src/stm32f1/hardware/stm32_pinmap.h @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_VALUELINE) +# include "hardware/stm32f100_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) +# include "hardware/stm32f102_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) || \ + defined(CONFIG_ARCH_CHIP_STM32F103C8) || \ + defined(CONFIG_ARCH_CHIP_STM32F103CB) +# include "hardware/stm32f103c_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RE) || \ + defined(CONFIG_ARCH_CHIP_STM32F103RG) +# include "hardware/stm32f103r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || \ + defined(CONFIG_ARCH_CHIP_STM32F103VE) +# include "hardware/stm32f103v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) +# include "hardware/stm32f103z_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) +# include "hardware/stm32f105v_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) +# include "hardware/stm32f105r_pinmap.h" +#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) +# include "hardware/stm32f107v_pinmap.h" +#else +# error "Unsupported STM32F1 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f100_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h index e50de324c47..56174b63221 100644 --- a/arch/arm/src/stm32/hardware/stm32f100_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f100_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2009 Gregory Nutt. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f102_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h index a54ff133eab..8d85291705b 100644 --- a/arch/arm/src/stm32/hardware/stm32f102_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f102_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f102_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103c_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h index fa8052df026..b11796ad7bd 100644 --- a/arch/arm/src/stm32/hardware/stm32f103c_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103c_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103c_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h index 0f5596cd8b0..7ad6aa3e63b 100644 --- a/arch/arm/src/stm32/hardware/stm32f103r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h index 8d15dd04fd4..3074b6fec43 100644 --- a/arch/arm/src/stm32/hardware/stm32f103v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f103z_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h index 95a21a58da3..1af5f6ef0d1 100644 --- a/arch/arm/src/stm32/hardware/stm32f103z_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f103z_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f103z_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105r_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h index 5701c4af503..5956145aa28 100644 --- a/arch/arm/src/stm32/hardware/stm32f105r_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105r_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105r_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f105v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h index a0f07baaa03..b4ce3444d97 100644 --- a/arch/arm/src/stm32/hardware/stm32f105v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f105v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f105v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f107v_pinmap.h rename to arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h index e034bf01647..7433722c087 100644 --- a/arch/arm/src/stm32/hardware/stm32f107v_pinmap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f107v_pinmap.h + * arch/arm/src/stm32f1/hardware/stm32f107v_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h index 9dd7264b6f1..4ba272eebf5 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_gpio.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h index c11e00c13b6..ec755efb47b 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_memorymap.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h rename to arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h index 457fea592df..54828425c3c 100644 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h +++ b/arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_rcc.h + * arch/arm/src/stm32f1/hardware/stm32f10xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32.h b/arch/arm/src/stm32f1/stm32.h similarity index 88% rename from arch/arm/src/stm32/stm32.h rename to arch/arm/src/stm32f1/stm32.h index 66b91b72e86..5707089d7b8 100644 --- a/arch/arm/src/stm32/stm32.h +++ b/arch/arm/src/stm32f1/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32.h + * arch/arm/src/stm32f1/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -42,19 +42,19 @@ #include "stm32_comp.h" #include "stm32_dbgmcu.h" #include "stm32_dma.h" -#include "stm32_dac.h" +#include "stm32_dac_m3m4_v1.h" #include "stm32_exti.h" #include "stm32_flash.h" -#include "stm32_fmc.h" -#include "stm32_fsmc.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" #include "stm32_gpio.h" #include "stm32_i2c.h" -#include "stm32_ltdc.h" -#include "stm32_opamp.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" #include "stm32_pwr.h" #include "stm32_rcc.h" #include "stm32_rtc.h" -#include "stm32_sdio.h" +#include "stm32_sdio_m3m4_v1.h" #include "stm32_spi.h" #include "stm32_i2s.h" #include "stm32_tim.h" @@ -64,6 +64,6 @@ #endif #include "stm32_wdg.h" #include "stm32_lowputc.h" -#include "stm32_eth.h" +#include "stm32_eth_m3m4_v1.h" #endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f1/stm32_rcc.c b/arch/arm/src/stm32f1/stm32_rcc.c new file mode 100644 index 00000000000..f78d3e0a189 --- /dev/null +++ b/arch/arm/src/stm32f1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f10xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f10xxx_rcc.c rename to arch/arm/src/stm32f1/stm32f10xxx_rcc.c index fa8c0debe69..8b2604a55a2 100644 --- a/arch/arm/src/stm32/stm32f10xxx_rcc.c +++ b/arch/arm/src/stm32f1/stm32f10xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f10xxx_rcc.c + * arch/arm/src/stm32f1/stm32f10xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/b-g431b-esc1/CMakeLists.txt rename to boards/arm/stm32f1/cloudctrl/CMakeLists.txt index 8651bd85622..63062e3011b 100644 --- a/boards/arm/stm32/b-g431b-esc1/CMakeLists.txt +++ b/boards/arm/stm32f1/cloudctrl/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/b-g431b-esc1/CMakeLists.txt +# boards/arm/stm32f1/cloudctrl/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/cloudctrl/Kconfig b/boards/arm/stm32f1/cloudctrl/Kconfig similarity index 100% rename from boards/arm/stm32/cloudctrl/Kconfig rename to boards/arm/stm32f1/cloudctrl/Kconfig diff --git a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/cloudctrl/configs/nsh/defconfig rename to boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig index d27766792b5..35a72832e26 100644 --- a/boards/arm/stm32/cloudctrl/configs/nsh/defconfig +++ b/boards/arm/stm32f1/cloudctrl/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="cloudctrl" CONFIG_ARCH_BOARD_CLOUDCTRL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/cloudctrl/include/board.h b/boards/arm/stm32f1/cloudctrl/include/board.h similarity index 99% rename from boards/arm/stm32/cloudctrl/include/board.h rename to boards/arm/stm32f1/cloudctrl/include/board.h index 93955bad8b7..df0ae697667 100644 --- a/boards/arm/stm32/cloudctrl/include/board.h +++ b/boards/arm/stm32f1/cloudctrl/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/include/board.h + * boards/arm/stm32f1/cloudctrl/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/scripts/Make.defs b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/cloudctrl/scripts/Make.defs rename to boards/arm/stm32f1/cloudctrl/scripts/Make.defs index ef5f8e0d7da..806f4f368af 100644 --- a/boards/arm/stm32/cloudctrl/scripts/Make.defs +++ b/boards/arm/stm32f1/cloudctrl/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/cloudctrl/scripts/Make.defs +# boards/arm/stm32f1/cloudctrl/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld index f65e582ac70..962101f6050 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl-dfu.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld similarity index 98% rename from boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld rename to boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld index 1d6e63c1ec9..edbb31f7bf7 100644 --- a/boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld +++ b/boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/scripts/cloudctrl.ld + * boards/arm/stm32f1/cloudctrl/scripts/cloudctrl.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/cloudctrl/src/CMakeLists.txt rename to boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt index 2c62ad02c35..323760288c2 100644 --- a/boards/arm/stm32/cloudctrl/src/CMakeLists.txt +++ b/boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/cloudctrl/src/CMakeLists.txt +# boards/arm/stm32f1/cloudctrl/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/cloudctrl/src/Make.defs b/boards/arm/stm32f1/cloudctrl/src/Make.defs similarity index 97% rename from boards/arm/stm32/cloudctrl/src/Make.defs rename to boards/arm/stm32f1/cloudctrl/src/Make.defs index 746c1618cf6..acb393d7f7e 100644 --- a/boards/arm/stm32/cloudctrl/src/Make.defs +++ b/boards/arm/stm32f1/cloudctrl/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/cloudctrl/src/Make.defs +# boards/arm/stm32f1/cloudctrl/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/cloudctrl/src/cloudctrl.h b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h similarity index 99% rename from boards/arm/stm32/cloudctrl/src/cloudctrl.h rename to boards/arm/stm32f1/cloudctrl/src/cloudctrl.h index 58d98fabb4c..00d0411160c 100644 --- a/boards/arm/stm32/cloudctrl/src/cloudctrl.h +++ b/boards/arm/stm32f1/cloudctrl/src/cloudctrl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/cloudctrl.h + * boards/arm/stm32f1/cloudctrl/src/cloudctrl.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_adc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/cloudctrl/src/stm32_adc.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_adc.c index 075adeb257a..dff3cb52e98 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_adc.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_adc.c + * boards/arm/stm32f1/cloudctrl/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_autoleds.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c index f4ecba575e8..ba9fe2732c0 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_autoleds.c + * boards/arm/stm32f1/cloudctrl/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_boot.c b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_boot.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_boot.c index cd489c2ae3d..20d17470a6d 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_boot.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_boot.c + * boards/arm/stm32f1/cloudctrl/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_buttons.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c index cc0e9ea8ea2..06b2467a8b2 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_buttons.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_buttons.c + * boards/arm/stm32f1/cloudctrl/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c similarity index 97% rename from boards/arm/stm32/cloudctrl/src/stm32_chipid.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c index c2f6f75cf00..8abfb93176d 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_chipid.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_chipid.c + * boards/arm/stm32f1/cloudctrl/src/stm32_chipid.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c similarity index 97% rename from boards/arm/stm32/cloudctrl/src/stm32_phyinit.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c index 26b01ab9810..95382ef1a22 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_phyinit.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_phyinit.c + * boards/arm/stm32f1/cloudctrl/src/stm32_phyinit.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_relays.c b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_relays.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_relays.c index 0007901ff80..e86a2345942 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_relays.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_relays.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_relays.c + * boards/arm/stm32f1/cloudctrl/src/stm32_relays.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_spi.c b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_spi.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_spi.c index 9e5e2a3d88c..d1aa4127a14 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_spi.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_spi.c + * boards/arm/stm32f1/cloudctrl/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usb.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/cloudctrl/src/stm32_usb.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_usb.c index ae70668bb50..92b57904640 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_usb.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usb.c + * boards/arm/stm32f1/cloudctrl/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c index ab372b7c355..bde12464514 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c + * boards/arm/stm32f1/cloudctrl/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/cloudctrl/src/stm32_userleds.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c index d9f75c9aa28..3fbcf5b60fb 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_userleds.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_userleds.c + * boards/arm/stm32f1/cloudctrl/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/src/stm32_w25.c b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c similarity index 98% rename from boards/arm/stm32/cloudctrl/src/stm32_w25.c rename to boards/arm/stm32f1/cloudctrl/src/stm32_w25.c index bcd7be927bc..16de2838d3a 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_w25.c +++ b/boards/arm/stm32f1/cloudctrl/src/stm32_w25.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/cloudctrl/src/stm32_w25.c + * boards/arm/stm32f1/cloudctrl/src/stm32_w25.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/cloudctrl/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/oocd.sh b/boards/arm/stm32f1/cloudctrl/tools/oocd.sh similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/oocd.sh rename to boards/arm/stm32f1/cloudctrl/tools/oocd.sh diff --git a/boards/arm/stm32/cloudctrl/tools/stm32.cfg b/boards/arm/stm32f1/cloudctrl/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/stm32.cfg rename to boards/arm/stm32f1/cloudctrl/tools/stm32.cfg diff --git a/boards/arm/stm32/cloudctrl/tools/usb-driver.txt b/boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/cloudctrl/tools/usb-driver.txt rename to boards/arm/stm32f1/cloudctrl/tools/usb-driver.txt diff --git a/boards/arm/stm32/common/CMakeLists.txt b/boards/arm/stm32f1/common/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/common/CMakeLists.txt rename to boards/arm/stm32f1/common/CMakeLists.txt index 2d59a76459e..1d43b25fbc9 100644 --- a/boards/arm/stm32/common/CMakeLists.txt +++ b/boards/arm/stm32f1/common/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/common/CMakeLists.txt +# boards/arm/stm32f1/common/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/common/Kconfig b/boards/arm/stm32f1/common/Kconfig similarity index 100% rename from boards/arm/stm32/common/Kconfig rename to boards/arm/stm32f1/common/Kconfig diff --git a/boards/arm/stm32/common/Makefile b/boards/arm/stm32f1/common/Makefile similarity index 97% rename from boards/arm/stm32/common/Makefile rename to boards/arm/stm32f1/common/Makefile index 801cf99b184..1ec563c38c8 100644 --- a/boards/arm/stm32/common/Makefile +++ b/boards/arm/stm32f1/common/Makefile @@ -1,5 +1,5 @@ ############################################################################# -# boards/arm/stm32/common/Makefile +# boards/arm/stm32f1/common/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt new file mode 100644 index 00000000000..eb55f812bda --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/et-stm32-stamp/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/Kconfig b/boards/arm/stm32f1/et-stm32-stamp/Kconfig similarity index 100% rename from boards/arm/stm32/et-stm32-stamp/Kconfig rename to boards/arm/stm32f1/et-stm32-stamp/Kconfig diff --git a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig rename to boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig index e1777e13148..33ca6384081 100644 --- a/boards/arm/stm32/et-stm32-stamp/configs/nsh/defconfig +++ b/boards/arm/stm32f1/et-stm32-stamp/configs/nsh/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="et-stm32-stamp" CONFIG_ARCH_BOARD_ET_STM32_STAMP=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/et-stm32-stamp/include/board.h b/boards/arm/stm32f1/et-stm32-stamp/include/board.h similarity index 99% rename from boards/arm/stm32/et-stm32-stamp/include/board.h rename to boards/arm/stm32f1/et-stm32-stamp/include/board.h index c2d3dd4b1a9..7cb521fadc8 100644 --- a/boards/arm/stm32/et-stm32-stamp/include/board.h +++ b/boards/arm/stm32f1/et-stm32-stamp/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/include/board.h + * boards/arm/stm32f1/et-stm32-stamp/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs new file mode 100644 index 00000000000..3470a34f64a --- /dev/null +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f1/et-stm32-stamp/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script similarity index 98% rename from boards/arm/stm32/et-stm32-stamp/scripts/ld.script rename to boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script index ddf645d3c6c..6c11e86fc69 100644 --- a/boards/arm/stm32/et-stm32-stamp/scripts/ld.script +++ b/boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/scripts/ld.script + * boards/arm/stm32f1/et-stm32-stamp/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt rename to boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt index 3aa3d6093c6..b7aae37dd01 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt +++ b/boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/et-stm32-stamp/src/CMakeLists.txt +# boards/arm/stm32f1/et-stm32-stamp/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/et-stm32-stamp/src/Make.defs b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs similarity index 95% rename from boards/arm/stm32/et-stm32-stamp/src/Make.defs rename to boards/arm/stm32f1/et-stm32-stamp/src/Make.defs index 009c8104955..d022a6aad98 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/Make.defs +++ b/boards/arm/stm32f1/et-stm32-stamp/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/et-stm32-stamp/src/Make.defs +# boards/arm/stm32f1/et-stm32-stamp/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h similarity index 96% rename from boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h rename to boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h index 4daca3f0bfb..81ca060fcab 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h +++ b/boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/et-stm32-stamp.h + * boards/arm/stm32f1/et-stm32-stamp/src/et-stm32-stamp.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c rename to boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c index b56fe99ba71..498eae42453 100644 --- a/boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c +++ b/boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/et-stm32-stamp/src/stm32_boot.c + * boards/arm/stm32f1/et-stm32-stamp/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/clicker2-stm32/CMakeLists.txt rename to boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt index 40b17adb6cb..aaab83b6d0d 100644 --- a/boards/arm/stm32/clicker2-stm32/CMakeLists.txt +++ b/boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/clicker2-stm32/CMakeLists.txt +# boards/arm/stm32f1/fire-stm32v2/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/fire-stm32v2/Kconfig b/boards/arm/stm32f1/fire-stm32v2/Kconfig similarity index 100% rename from boards/arm/stm32/fire-stm32v2/Kconfig rename to boards/arm/stm32f1/fire-stm32v2/Kconfig diff --git a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig rename to boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig index bdd40431cd1..a310a440555 100644 --- a/boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig +++ b/boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="fire-stm32v2" CONFIG_ARCH_BOARD_FIRE_STM32=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/fire-stm32v2/include/board.h b/boards/arm/stm32f1/fire-stm32v2/include/board.h similarity index 99% rename from boards/arm/stm32/fire-stm32v2/include/board.h rename to boards/arm/stm32f1/fire-stm32v2/include/board.h index 573773b7da3..27e228b9257 100644 --- a/boards/arm/stm32/fire-stm32v2/include/board.h +++ b/boards/arm/stm32f1/fire-stm32v2/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/include/board.h + * boards/arm/stm32f1/fire-stm32v2/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/fire-stm32v2/scripts/Make.defs rename to boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs index f51a205edbf..82ac28f1b37 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/Make.defs +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/fire-stm32v2/scripts/Make.defs +# boards/arm/stm32f1/fire-stm32v2/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld index 98e7d8a77d3..32ac24c4ef2 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2-dfu.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2-dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld similarity index 98% rename from boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld rename to boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld index d9e527a239c..64ee682f7b6 100644 --- a/boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld +++ b/boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/scripts/fire-stm32v2.ld + * boards/arm/stm32f1/fire-stm32v2/scripts/fire-stm32v2.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt rename to boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt index 8d9a77eabc3..a589de40419 100644 --- a/boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt +++ b/boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/fire-stm32v2/src/CMakeLists.txt +# boards/arm/stm32f1/fire-stm32v2/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/fire-stm32v2/src/Make.defs b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs similarity index 97% rename from boards/arm/stm32/fire-stm32v2/src/Make.defs rename to boards/arm/stm32f1/fire-stm32v2/src/Make.defs index fdfe1aaa4b3..741b5125d19 100644 --- a/boards/arm/stm32/fire-stm32v2/src/Make.defs +++ b/boards/arm/stm32f1/fire-stm32v2/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/fire-stm32v2/src/Make.defs +# boards/arm/stm32f1/fire-stm32v2/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h rename to boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h index 7bfd672d81e..8b6606826ee 100644 --- a/boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h +++ b/boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/fire-stm32v2.h + * boards/arm/stm32f1/fire-stm32v2/src/fire-stm32v2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c index 882946b820a..74380388b50 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_autoleds.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/stm32_boot.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c index 9ee669b3fbc..0ab15a7fc13 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_boot.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_boot.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c index 735bda0f2fd..24e083f6f65 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_buttons.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c index de824d6ad02..f75a83fa181 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_enc28j60.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_enc28j60.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c index 5b800a06600..7b24f9062cf 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_mmcsd.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c index a1654527d23..153572749c5 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_selectlcd.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_selectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/fire-stm32v2/src/stm32_spi.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c index 309d8d175de..42f31b0005e 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_spi.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_spi.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c index 4d592165ae8..51fb1b1ab51 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbdev.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c index dd87c605e78..c34d41e6896 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_usbmsc.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c index 15f5e2506f7..f94020021af 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_userleds.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c similarity index 98% rename from boards/arm/stm32/fire-stm32v2/src/stm32_w25.c rename to boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c index 3dd694251ba..56ed032c057 100644 --- a/boards/arm/stm32/fire-stm32v2/src/stm32_w25.c +++ b/boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/fire-stm32v2/src/stm32_w25.c + * boards/arm/stm32f1/fire-stm32v2/src/stm32_w25.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt new file mode 100644 index 00000000000..4af2981effa --- /dev/null +++ b/boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/hymini-stm32v/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/hymini-stm32v/Kconfig b/boards/arm/stm32f1/hymini-stm32v/Kconfig similarity index 100% rename from boards/arm/stm32/hymini-stm32v/Kconfig rename to boards/arm/stm32f1/hymini-stm32v/Kconfig diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig rename to boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig index b904fc0c04c..2b1d0d38fe1 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh/defconfig +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig similarity index 98% rename from boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig rename to boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig index af5c99a60ef..fda1334b588 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/nsh2/defconfig +++ b/boards/arm/stm32f1/hymini-stm32v/configs/nsh2/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig rename to boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig index 93e1fda2fb6..3686bd67351 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbmsc/defconfig +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbmsc/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig similarity index 97% rename from boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig rename to boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig index d4abd686cc2..1d4d8194119 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbnsh/defconfig +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig similarity index 97% rename from boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig rename to boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig index e83a76ba4d6..488745ba2fb 100644 --- a/boards/arm/stm32/hymini-stm32v/configs/usbserial/defconfig +++ b/boards/arm/stm32f1/hymini-stm32v/configs/usbserial/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="hymini-stm32v" CONFIG_ARCH_BOARD_HYMINI_STM32V=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/hymini-stm32v/include/board.h b/boards/arm/stm32f1/hymini-stm32v/include/board.h similarity index 99% rename from boards/arm/stm32/hymini-stm32v/include/board.h rename to boards/arm/stm32f1/hymini-stm32v/include/board.h index 9fae5bdda94..820d03a162b 100644 --- a/boards/arm/stm32/hymini-stm32v/include/board.h +++ b/boards/arm/stm32f1/hymini-stm32v/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/include/board.h + * boards/arm/stm32f1/hymini-stm32v/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/hymini-stm32v/scripts/Make.defs rename to boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs index 40a135bea3b..cc9f4fdc84e 100644 --- a/boards/arm/stm32/hymini-stm32v/scripts/Make.defs +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/hymini-stm32v/scripts/Make.defs +# boards/arm/stm32f1/hymini-stm32v/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/hymini-stm32v/scripts/ld.script b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script similarity index 98% rename from boards/arm/stm32/hymini-stm32v/scripts/ld.script rename to boards/arm/stm32f1/hymini-stm32v/scripts/ld.script index 0f1cc348f8a..faa108e1d4b 100644 --- a/boards/arm/stm32/hymini-stm32v/scripts/ld.script +++ b/boards/arm/stm32f1/hymini-stm32v/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/scripts/ld.script + * boards/arm/stm32f1/hymini-stm32v/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt rename to boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt index e31d5a0ca4c..aa571e0ce09 100644 --- a/boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt +++ b/boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/hymini-stm32v/src/CMakeLists.txt +# boards/arm/stm32f1/hymini-stm32v/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/hymini-stm32v/src/Make.defs b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs similarity index 96% rename from boards/arm/stm32/hymini-stm32v/src/Make.defs rename to boards/arm/stm32f1/hymini-stm32v/src/Make.defs index d96eeceb4ad..7285c60b44a 100644 --- a/boards/arm/stm32/hymini-stm32v/src/Make.defs +++ b/boards/arm/stm32f1/hymini-stm32v/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/hymini-stm32v/src/Make.defs +# boards/arm/stm32f1/hymini-stm32v/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h rename to boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h index e8966e76f01..ba053fc552f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h +++ b/boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/hymini-stm32v.h + * boards/arm/stm32f1/hymini-stm32v/src/hymini-stm32v.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_boot.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c index 755f41cf039..934454ae8b8 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_boot.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_boot.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c index dccdff634d9..14082bc395a 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_buttons.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_leds.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c index f54f78f99ed..166971c8b24 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_leds.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_leds.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c index 531e96e91b5..a43d7b85e27 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_r61505u.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_spi.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c index 75eb1cbfd17..6e88b17755f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_spi.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_spi.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c similarity index 99% rename from boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c index 6da455a5bd4..679d23535de 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ssd1289.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_ts.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c index e7e7a8720c3..86b9a9137e8 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_ts.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_ts.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_ts.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c index c5bbfba802a..108df51135f 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbdev.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c similarity index 98% rename from boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c rename to boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c index 5072bc4531f..ed78a1b8665 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/hymini-stm32v/src/stm32_usbmsc.c + * boards/arm/stm32f1/hymini-stm32v/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/CMakeLists.txt b/boards/arm/stm32f1/maple/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/axoloti/CMakeLists.txt rename to boards/arm/stm32f1/maple/CMakeLists.txt index 47501793832..c22e019a545 100644 --- a/boards/arm/stm32/axoloti/CMakeLists.txt +++ b/boards/arm/stm32f1/maple/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/axoloti/CMakeLists.txt +# boards/arm/stm32f1/maple/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/maple/Kconfig b/boards/arm/stm32f1/maple/Kconfig similarity index 100% rename from boards/arm/stm32/maple/Kconfig rename to boards/arm/stm32f1/maple/Kconfig diff --git a/boards/arm/stm32/maple/configs/nsh/defconfig b/boards/arm/stm32f1/maple/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/maple/configs/nsh/defconfig rename to boards/arm/stm32f1/maple/configs/nsh/defconfig index 8560b225c2a..619ff1f1dbf 100644 --- a/boards/arm/stm32/maple/configs/nsh/defconfig +++ b/boards/arm/stm32f1/maple/configs/nsh/defconfig @@ -23,7 +23,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/maple/configs/nx/defconfig b/boards/arm/stm32f1/maple/configs/nx/defconfig similarity index 98% rename from boards/arm/stm32/maple/configs/nx/defconfig rename to boards/arm/stm32f1/maple/configs/nx/defconfig index b0fe6deb135..5d98c00a330 100644 --- a/boards/arm/stm32/maple/configs/nx/defconfig +++ b/boards/arm/stm32f1/maple/configs/nx/defconfig @@ -25,7 +25,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/maple/configs/usbnsh/defconfig b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/maple/configs/usbnsh/defconfig rename to boards/arm/stm32f1/maple/configs/usbnsh/defconfig index e25aa718adb..128d504fd3f 100644 --- a/boards/arm/stm32/maple/configs/usbnsh/defconfig +++ b/boards/arm/stm32f1/maple/configs/usbnsh/defconfig @@ -24,7 +24,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="maple" CONFIG_ARCH_BOARD_MAPLE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103CB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/maple/include/board.h b/boards/arm/stm32f1/maple/include/board.h similarity index 99% rename from boards/arm/stm32/maple/include/board.h rename to boards/arm/stm32f1/maple/include/board.h index dd3a2053a28..af797c5453d 100644 --- a/boards/arm/stm32/maple/include/board.h +++ b/boards/arm/stm32f1/maple/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/include/board.h + * boards/arm/stm32f1/maple/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/scripts/Make.defs b/boards/arm/stm32f1/maple/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/maple/scripts/Make.defs rename to boards/arm/stm32f1/maple/scripts/Make.defs index 29529db249b..659d183e627 100644 --- a/boards/arm/stm32/maple/scripts/Make.defs +++ b/boards/arm/stm32f1/maple/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/maple/scripts/Make.defs +# boards/arm/stm32f1/maple/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/maple/scripts/ld.script b/boards/arm/stm32f1/maple/scripts/ld.script similarity index 98% rename from boards/arm/stm32/maple/scripts/ld.script rename to boards/arm/stm32f1/maple/scripts/ld.script index afe284a8b80..0a473342b75 100644 --- a/boards/arm/stm32/maple/scripts/ld.script +++ b/boards/arm/stm32f1/maple/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script + * boards/arm/stm32f1/maple/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/scripts/ld.script.dfu b/boards/arm/stm32f1/maple/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/maple/scripts/ld.script.dfu rename to boards/arm/stm32f1/maple/scripts/ld.script.dfu index f36caa9525e..c1b90e6d7af 100644 --- a/boards/arm/stm32/maple/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/maple/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/scripts/ld.script.dfu + * boards/arm/stm32f1/maple/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/src/CMakeLists.txt b/boards/arm/stm32f1/maple/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/maple/src/CMakeLists.txt rename to boards/arm/stm32f1/maple/src/CMakeLists.txt index 9eec7a7387b..97ee99bae62 100644 --- a/boards/arm/stm32/maple/src/CMakeLists.txt +++ b/boards/arm/stm32f1/maple/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/maple/src/CMakeLists.txt +# boards/arm/stm32f1/maple/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/maple/src/Make.defs b/boards/arm/stm32f1/maple/src/Make.defs similarity index 97% rename from boards/arm/stm32/maple/src/Make.defs rename to boards/arm/stm32f1/maple/src/Make.defs index 90ae23399e3..1a04a2a8db6 100644 --- a/boards/arm/stm32/maple/src/Make.defs +++ b/boards/arm/stm32f1/maple/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/maple/src/Make.defs +# boards/arm/stm32f1/maple/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/maple/src/maple.h b/boards/arm/stm32f1/maple/src/maple.h similarity index 98% rename from boards/arm/stm32/maple/src/maple.h rename to boards/arm/stm32f1/maple/src/maple.h index 01bb5e5758f..26626776fb6 100644 --- a/boards/arm/stm32/maple/src/maple.h +++ b/boards/arm/stm32f1/maple/src/maple.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/maple.h + * boards/arm/stm32f1/maple/src/maple.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/maple/src/stm32_boot.c b/boards/arm/stm32f1/maple/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/maple/src/stm32_boot.c rename to boards/arm/stm32f1/maple/src/stm32_boot.c index 56d8a61eb6d..cbf666746d3 100644 --- a/boards/arm/stm32/maple/src/stm32_boot.c +++ b/boards/arm/stm32f1/maple/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/stm32_boot.c + * boards/arm/stm32f1/maple/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/src/stm32_lcd.c b/boards/arm/stm32f1/maple/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/maple/src/stm32_lcd.c rename to boards/arm/stm32f1/maple/src/stm32_lcd.c index b81dc0df3e7..58f5831a33f 100644 --- a/boards/arm/stm32/maple/src/stm32_lcd.c +++ b/boards/arm/stm32f1/maple/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/stm32_lcd.c + * boards/arm/stm32f1/maple/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/src/stm32_leds.c b/boards/arm/stm32f1/maple/src/stm32_leds.c similarity index 98% rename from boards/arm/stm32/maple/src/stm32_leds.c rename to boards/arm/stm32f1/maple/src/stm32_leds.c index b0ae4807205..61d8957f2e4 100644 --- a/boards/arm/stm32/maple/src/stm32_leds.c +++ b/boards/arm/stm32f1/maple/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/stm32_leds.c + * boards/arm/stm32f1/maple/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/src/stm32_spi.c b/boards/arm/stm32f1/maple/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/maple/src/stm32_spi.c rename to boards/arm/stm32f1/maple/src/stm32_spi.c index 22d6bb192e2..1b644a2eb7b 100644 --- a/boards/arm/stm32/maple/src/stm32_spi.c +++ b/boards/arm/stm32f1/maple/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/stm32_spi.c + * boards/arm/stm32f1/maple/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/src/stm32_usbdev.c b/boards/arm/stm32f1/maple/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/maple/src/stm32_usbdev.c rename to boards/arm/stm32f1/maple/src/stm32_usbdev.c index 648bfe8a929..301485eb42c 100644 --- a/boards/arm/stm32/maple/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/maple/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/maple/src/stm32_usbdev.c + * boards/arm/stm32f1/maple/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/tools/dfu.sh b/boards/arm/stm32f1/maple/tools/dfu.sh similarity index 100% rename from boards/arm/stm32/maple/tools/dfu.sh rename to boards/arm/stm32f1/maple/tools/dfu.sh diff --git a/boards/arm/stm32/maple/tools/env.sh b/boards/arm/stm32f1/maple/tools/env.sh similarity index 100% rename from boards/arm/stm32/maple/tools/env.sh rename to boards/arm/stm32f1/maple/tools/env.sh diff --git a/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt new file mode 100644 index 00000000000..2b4f584cf31 --- /dev/null +++ b/boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/nucleo-f103rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f103rb/Kconfig b/boards/arm/stm32f1/nucleo-f103rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f103rb/Kconfig rename to boards/arm/stm32f1/nucleo-f103rb/Kconfig diff --git a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig rename to boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig index c42749dde06..03b0dc7c459 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/adc/defconfig +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/adc/defconfig @@ -11,7 +11,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig rename to boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig index c9db38b3727..603393f3806 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/ihm07m1_b16/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F103RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig rename to boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig index 3e2df5a41ac..c3f979d2d13 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/nsh/defconfig +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/nsh/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig rename to boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig index 5be68b08744..f581b347f76 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/pwm/defconfig +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/pwm/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig rename to boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig index dfcbc2403c6..3e080577801 100644 --- a/boards/arm/stm32/nucleo-f103rb/configs/qenco/defconfig +++ b/boards/arm/stm32f1/nucleo-f103rb/configs/qenco/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f103rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F103RB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/nucleo-f103rb/include/board.h b/boards/arm/stm32f1/nucleo-f103rb/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f103rb/include/board.h rename to boards/arm/stm32f1/nucleo-f103rb/include/board.h index 6eb712c909c..508c91177a3 100644 --- a/boards/arm/stm32/nucleo-f103rb/include/board.h +++ b/boards/arm/stm32f1/nucleo-f103rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/include/board.h + * boards/arm/stm32f1/nucleo-f103rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/et-stm32-stamp/scripts/Make.defs rename to boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs index 702ac50cba5..cec74ca3dda 100644 --- a/boards/arm/stm32/et-stm32-stamp/scripts/Make.defs +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/et-stm32-stamp/scripts/Make.defs +# boards/arm/stm32f1/nucleo-f103rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/scripts/ld.script rename to boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script index 26fb217a12a..2d8d8c9c134 100644 --- a/boards/arm/stm32/nucleo-f103rb/scripts/ld.script +++ b/boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/scripts/ld.script + * boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt rename to boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt index 513418e9419..f8e649461b7 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt +++ b/boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f103rb/src/CMakeLists.txt +# boards/arm/stm32f1/nucleo-f103rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f103rb/src/Make.defs b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-f103rb/src/Make.defs rename to boards/arm/stm32f1/nucleo-f103rb/src/Make.defs index fa7a6e98720..f3c2bb75822 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/Make.defs +++ b/boards/arm/stm32f1/nucleo-f103rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f103rb/src/Make.defs +# boards/arm/stm32f1/nucleo-f103rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h rename to boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h index d4cb2b2383a..09dd3b1dd54 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h +++ b/boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/nucleo-f103rb.h + * boards/arm/stm32f1/nucleo-f103rb/src/nucleo-f103rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c index e3f6006eabc..5b5ff6d6bc8 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_adc.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c index 891d76833e2..9185329bab1 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_autoleds.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c index b2362627a32..0084bba60a8 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_boot.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c index 8ea6ec5e144..d4583edc58e 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_bringup.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c index 5631fb1246a..ce1e2da780e 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_buttons.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c index f22035b78c4..632f8770ef3 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_foc_ihm07m1.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_foc_ihm07m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c index e17931280d1..e4942fddead 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_pwm.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c rename to boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c index cb23d594b11..3e9985bd998 100644 --- a/boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c +++ b/boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f103rb/src/stm32_userleds.c + * boards/arm/stm32f1/nucleo-f103rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt new file mode 100644 index 00000000000..0a2eaea0a5f --- /dev/null +++ b/boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimex-stm32-p107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p107/Kconfig b/boards/arm/stm32f1/olimex-stm32-p107/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p107/Kconfig rename to boards/arm/stm32f1/olimex-stm32-p107/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig rename to boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig index 3c3be28514f..8b360b49552 100644 --- a/boards/arm/stm32/olimex-stm32-p107/configs/nsh/defconfig +++ b/boards/arm/stm32f1/olimex-stm32-p107/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p107" CONFIG_ARCH_BOARD_OLIMEX_STM32P107=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimex-stm32-p107/include/board.h b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p107/include/board.h rename to boards/arm/stm32f1/olimex-stm32-p107/include/board.h index 2af99acd922..612ecb223fd 100644 --- a/boards/arm/stm32/olimex-stm32-p107/include/board.h +++ b/boards/arm/stm32f1/olimex-stm32-p107/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/include/board.h + * boards/arm/stm32f1/olimex-stm32-p107/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs rename to boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs index 340d9862478..dda83d88983 100644 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p107/scripts/Make.defs +# boards/arm/stm32f1/olimex-stm32-p107/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/scripts/ld.script rename to boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script index a0144f22e74..7a37a617e07 100644 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu rename to boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu index 9a2251caf1a..410230772b1 100644 --- a/boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/scripts/ld.script.dfu + * boards/arm/stm32f1/olimex-stm32-p107/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt rename to boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt index 0e5286c799d..36500b34205 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/src/CMakeLists.txt +# boards/arm/stm32f1/olimex-stm32-p107/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p107/src/Make.defs rename to boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs index d7aa1806f73..c50f59af776 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/Make.defs +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p107/src/Make.defs +# boards/arm/stm32f1/olimex-stm32-p107/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h rename to boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h index 4ce6a7ce0f9..97366814f1f 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/olimex-stm32-p107.h + * boards/arm/stm32f1/olimex-stm32-p107/src/olimex-stm32-p107.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c index 729ccbe7e16..63c23905de9 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_boot.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c index 1836835c4bc..e6381bb949c 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_can.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c index c689ee90823..a3b484f5a16 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_encx24j600.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_encx24j600.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c rename to boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c index 62ae40b65ed..19f74116c0c 100644 --- a/boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c +++ b/boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p107/src/stm32_spi.c + * boards/arm/stm32f1/olimex-stm32-p107/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt new file mode 100644 index 00000000000..79a8aa20d74 --- /dev/null +++ b/boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/olimexino-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/Kconfig b/boards/arm/stm32f1/olimexino-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/olimexino-stm32/Kconfig rename to boards/arm/stm32f1/olimexino-stm32/Kconfig diff --git a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig similarity index 99% rename from boards/arm/stm32/olimexino-stm32/configs/can/defconfig rename to boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig index 5cda9c9dfaf..250c12385ea 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/can/defconfig +++ b/boards/arm/stm32f1/olimexino-stm32/configs/can/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig similarity index 99% rename from boards/arm/stm32/olimexino-stm32/configs/composite/defconfig rename to boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig index 17a4b63f45e..15da06b5596 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/composite/defconfig +++ b/boards/arm/stm32f1/olimexino-stm32/configs/composite/defconfig @@ -32,7 +32,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig similarity index 99% rename from boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig rename to boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig index 14b1c6b45e4..d5366a2e5fc 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32f1/olimexino-stm32/configs/nsh/defconfig @@ -32,7 +32,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig similarity index 98% rename from boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig rename to boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig index 1a32249955a..d21cfa15a19 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/smallnsh/defconfig +++ b/boards/arm/stm32f1/olimexino-stm32/configs/smallnsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig similarity index 98% rename from boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig rename to boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig index 6c7249cf180..14bbaffe7b9 100644 --- a/boards/arm/stm32/olimexino-stm32/configs/tiny/defconfig +++ b/boards/arm/stm32f1/olimexino-stm32/configs/tiny/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimexino-stm32" CONFIG_ARCH_BOARD_OLIMEXINO_STM32=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/olimexino-stm32/include/board.h b/boards/arm/stm32f1/olimexino-stm32/include/board.h similarity index 99% rename from boards/arm/stm32/olimexino-stm32/include/board.h rename to boards/arm/stm32f1/olimexino-stm32/include/board.h index 219e6256517..43d1b956c90 100644 --- a/boards/arm/stm32/olimexino-stm32/include/board.h +++ b/boards/arm/stm32f1/olimexino-stm32/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/include/board.h + * boards/arm/stm32f1/olimexino-stm32/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/scripts/Make.defs b/boards/arm/stm32f1/olimexino-stm32/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/olimexino-stm32/scripts/Make.defs rename to boards/arm/stm32f1/olimexino-stm32/scripts/Make.defs index 93225ddac82..a66f5147472 100644 --- a/boards/arm/stm32/olimexino-stm32/scripts/Make.defs +++ b/boards/arm/stm32f1/olimexino-stm32/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimexino-stm32/scripts/Make.defs +# boards/arm/stm32f1/olimexino-stm32/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimexino-stm32/scripts/ld.script b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script similarity index 98% rename from boards/arm/stm32/olimexino-stm32/scripts/ld.script rename to boards/arm/stm32f1/olimexino-stm32/scripts/ld.script index a3b5bfd0ce7..75f933f503c 100644 --- a/boards/arm/stm32/olimexino-stm32/scripts/ld.script +++ b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/scripts/ld.script + * boards/arm/stm32f1/olimexino-stm32/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu rename to boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu index 5cb7d690bfa..5e711e9bf44 100644 --- a/boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/scripts/ld.script.dfu + * boards/arm/stm32f1/olimexino-stm32/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt rename to boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt index 9457b7258b7..92c20f5852f 100644 --- a/boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt +++ b/boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimexino-stm32/src/CMakeLists.txt +# boards/arm/stm32f1/olimexino-stm32/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimexino-stm32/src/Make.defs b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs similarity index 96% rename from boards/arm/stm32/olimexino-stm32/src/Make.defs rename to boards/arm/stm32f1/olimexino-stm32/src/Make.defs index 65205d71528..3e70dc2362c 100644 --- a/boards/arm/stm32/olimexino-stm32/src/Make.defs +++ b/boards/arm/stm32f1/olimexino-stm32/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimexino-stm32/src/Make.defs +# boards/arm/stm32f1/olimexino-stm32/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h similarity index 99% rename from boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h rename to boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h index 09d5de74303..e0f4f7c67c1 100644 --- a/boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h +++ b/boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/olimexino-stm32.h + * boards/arm/stm32f1/olimexino-stm32/src/olimexino-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_boot.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c index b4d93ced9dc..3e0ea392f3a 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_boot.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_boot.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c index 026ef07e68e..341e220517e 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_buttons.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_can.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c index 64164af8b23..06c03bd103f 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_can.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_can.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c similarity index 99% rename from boards/arm/stm32/olimexino-stm32/src/stm32_composite.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c index dbc418009f5..79a7efdc01e 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_composite.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_composite.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_composite.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_leds.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c index f0a2df6beff..49fc941fc45 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_leds.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_leds.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/olimexino-stm32/src/stm32_spi.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c index 43053e5ccbe..50e199d75dc 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_spi.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_spi.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c index da1a423330f..fbbca672512 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbdev.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c similarity index 98% rename from boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c rename to boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c index 8af999fdb60..9a9a44a028f 100644 --- a/boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimexino-stm32/src/stm32_usbmsc.c + * boards/arm/stm32f1/olimexino-stm32/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/photon/CMakeLists.txt rename to boards/arm/stm32f1/shenzhou/CMakeLists.txt index 2bb4205c977..23fa95383dd 100644 --- a/boards/arm/stm32/photon/CMakeLists.txt +++ b/boards/arm/stm32f1/shenzhou/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/photon/CMakeLists.txt +# boards/arm/stm32f1/shenzhou/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/shenzhou/Kconfig b/boards/arm/stm32f1/shenzhou/Kconfig similarity index 100% rename from boards/arm/stm32/shenzhou/Kconfig rename to boards/arm/stm32f1/shenzhou/Kconfig diff --git a/boards/arm/stm32/shenzhou/configs/nsh/defconfig b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/shenzhou/configs/nsh/defconfig rename to boards/arm/stm32f1/shenzhou/configs/nsh/defconfig index b2165bef2b2..cc6a676e941 100644 --- a/boards/arm/stm32/shenzhou/configs/nsh/defconfig +++ b/boards/arm/stm32f1/shenzhou/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig similarity index 99% rename from boards/arm/stm32/shenzhou/configs/nxwm/defconfig rename to boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig index 66414f65561..39fd4cf05d0 100644 --- a/boards/arm/stm32/shenzhou/configs/nxwm/defconfig +++ b/boards/arm/stm32f1/shenzhou/configs/nxwm/defconfig @@ -19,7 +19,7 @@ CONFIG_ADS7843E_THRESHY=51 CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig similarity index 98% rename from boards/arm/stm32/shenzhou/configs/thttpd/defconfig rename to boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig index 4316fa865f2..9d4170bfa9e 100644 --- a/boards/arm/stm32/shenzhou/configs/thttpd/defconfig +++ b/boards/arm/stm32f1/shenzhou/configs/thttpd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="shenzhou" CONFIG_ARCH_BOARD_SHENZHOU=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/shenzhou/include/board.h b/boards/arm/stm32f1/shenzhou/include/board.h similarity index 99% rename from boards/arm/stm32/shenzhou/include/board.h rename to boards/arm/stm32f1/shenzhou/include/board.h index 394f305ee98..858074f77df 100644 --- a/boards/arm/stm32/shenzhou/include/board.h +++ b/boards/arm/stm32f1/shenzhou/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/include/board.h + * boards/arm/stm32f1/shenzhou/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/scripts/Make.defs b/boards/arm/stm32f1/shenzhou/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/shenzhou/scripts/Make.defs rename to boards/arm/stm32f1/shenzhou/scripts/Make.defs index 920c3f3fc25..d43905ce219 100644 --- a/boards/arm/stm32/shenzhou/scripts/Make.defs +++ b/boards/arm/stm32f1/shenzhou/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/shenzhou/scripts/Make.defs +# boards/arm/stm32f1/shenzhou/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script b/boards/arm/stm32f1/shenzhou/scripts/ld.script similarity index 98% rename from boards/arm/stm32/shenzhou/scripts/ld.script rename to boards/arm/stm32f1/shenzhou/scripts/ld.script index 92929e25eb2..8487eb9e182 100644 --- a/boards/arm/stm32/shenzhou/scripts/ld.script +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script + * boards/arm/stm32f1/shenzhou/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/shenzhou/scripts/ld.script.dfu rename to boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu index 63eb3ea0491..02c796db472 100644 --- a/boards/arm/stm32/shenzhou/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/scripts/ld.script.dfu + * boards/arm/stm32f1/shenzhou/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/CMakeLists.txt b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/shenzhou/src/CMakeLists.txt rename to boards/arm/stm32f1/shenzhou/src/CMakeLists.txt index fe1037ab0f8..162ec56a04e 100644 --- a/boards/arm/stm32/shenzhou/src/CMakeLists.txt +++ b/boards/arm/stm32f1/shenzhou/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/shenzhou/src/CMakeLists.txt +# boards/arm/stm32f1/shenzhou/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/shenzhou/src/Make.defs b/boards/arm/stm32f1/shenzhou/src/Make.defs similarity index 97% rename from boards/arm/stm32/shenzhou/src/Make.defs rename to boards/arm/stm32f1/shenzhou/src/Make.defs index 86db238f76e..262f7424103 100644 --- a/boards/arm/stm32/shenzhou/src/Make.defs +++ b/boards/arm/stm32f1/shenzhou/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/shenzhou/src/Make.defs +# boards/arm/stm32f1/shenzhou/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/shenzhou/src/shenzhou.h b/boards/arm/stm32f1/shenzhou/src/shenzhou.h similarity index 99% rename from boards/arm/stm32/shenzhou/src/shenzhou.h rename to boards/arm/stm32f1/shenzhou/src/shenzhou.h index 9bf3f825b80..089c07fd6f1 100644 --- a/boards/arm/stm32/shenzhou/src/shenzhou.h +++ b/boards/arm/stm32f1/shenzhou/src/shenzhou.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/shenzhou.h + * boards/arm/stm32f1/shenzhou/src/shenzhou.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_adc.c b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_adc.c rename to boards/arm/stm32f1/shenzhou/src/stm32_adc.c index 95cd3ac7acc..922698d8e74 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_adc.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_adc.c + * boards/arm/stm32f1/shenzhou/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_autoleds.c rename to boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c index cae0688a9f3..4ea472253b4 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_autoleds.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_autoleds.c + * boards/arm/stm32f1/shenzhou/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_boot.c b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_boot.c rename to boards/arm/stm32f1/shenzhou/src/stm32_boot.c index b4aa743dcb0..c2e3492aaa3 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_boot.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_boot.c + * boards/arm/stm32f1/shenzhou/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_buttons.c b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_buttons.c rename to boards/arm/stm32f1/shenzhou/src/stm32_buttons.c index 0081e708c36..15dcb93fae3 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_buttons.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_buttons.c + * boards/arm/stm32f1/shenzhou/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_can.c b/boards/arm/stm32f1/shenzhou/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_can.c rename to boards/arm/stm32f1/shenzhou/src/stm32_can.c index 8a32d419a42..5a8f603b946 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_can.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_can.c + * boards/arm/stm32f1/shenzhou/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_chipid.c b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c similarity index 97% rename from boards/arm/stm32/shenzhou/src/stm32_chipid.c rename to boards/arm/stm32f1/shenzhou/src/stm32_chipid.c index 8ad2d692034..8ae5a0fd181 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_chipid.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_chipid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_chipid.c + * boards/arm/stm32f1/shenzhou/src/stm32_chipid.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_ili93xx.c rename to boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c index eb190ae7884..5610e1946a1 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ili93xx.c + * boards/arm/stm32f1/shenzhou/src/stm32_ili93xx.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_mmcsd.c rename to boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c index 283527e5d11..d9e7cbfa97d 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_mmcsd.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_mmcsd.c + * boards/arm/stm32f1/shenzhou/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_relays.c b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_relays.c rename to boards/arm/stm32f1/shenzhou/src/stm32_relays.c index fab22788936..6c7fd95eeaa 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_relays.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_relays.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_relays.c + * boards/arm/stm32f1/shenzhou/src/stm32_relays.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_spi.c b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_spi.c rename to boards/arm/stm32f1/shenzhou/src/stm32_spi.c index 43629080b14..d77612c7eb6 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_spi.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_spi.c + * boards/arm/stm32f1/shenzhou/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_ssd1289.c rename to boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c index c8b22220d74..d4bbe679b1b 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_ssd1289.c + * boards/arm/stm32f1/shenzhou/src/stm32_ssd1289.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_touchscreen.c rename to boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c index 537e004b629..c7733ba51f9 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_touchscreen.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_touchscreen.c + * boards/arm/stm32f1/shenzhou/src/stm32_touchscreen.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_usb.c b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/shenzhou/src/stm32_usb.c rename to boards/arm/stm32f1/shenzhou/src/stm32_usb.c index 6660fca6bf8..bbc47272d23 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_usb.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usb.c + * boards/arm/stm32f1/shenzhou/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_usbmsc.c rename to boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c index 4e9f496f132..bce9cfc30f6 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_usbmsc.c + * boards/arm/stm32f1/shenzhou/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_userleds.c b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_userleds.c rename to boards/arm/stm32f1/shenzhou/src/stm32_userleds.c index 52d3107e2fa..9b18917f728 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_userleds.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_userleds.c + * boards/arm/stm32f1/shenzhou/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/src/stm32_w25.c b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c similarity index 98% rename from boards/arm/stm32/shenzhou/src/stm32_w25.c rename to boards/arm/stm32f1/shenzhou/src/stm32_w25.c index 861d79a8550..1658b957ca3 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_w25.c +++ b/boards/arm/stm32f1/shenzhou/src/stm32_w25.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/shenzhou/src/stm32_w25.c + * boards/arm/stm32f1/shenzhou/src/stm32_w25.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/shenzhou/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/shenzhou/tools/oocd.sh b/boards/arm/stm32f1/shenzhou/tools/oocd.sh similarity index 96% rename from boards/arm/stm32/shenzhou/tools/oocd.sh rename to boards/arm/stm32f1/shenzhou/tools/oocd.sh index 136a792c6f9..e965ac36e90 100755 --- a/boards/arm/stm32/shenzhou/tools/oocd.sh +++ b/boards/arm/stm32f1/shenzhou/tools/oocd.sh @@ -47,7 +47,7 @@ fi # Local search directory and configurations -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/shenzhou/tools" +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/shenzhou/tools" OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" diff --git a/boards/arm/stm32/shenzhou/tools/stm32.cfg b/boards/arm/stm32f1/shenzhou/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/shenzhou/tools/stm32.cfg rename to boards/arm/stm32f1/shenzhou/tools/stm32.cfg diff --git a/boards/arm/stm32/shenzhou/tools/usb-driver.txt b/boards/arm/stm32f1/shenzhou/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/shenzhou/tools/usb-driver.txt rename to boards/arm/stm32f1/shenzhou/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt new file mode 100644 index 00000000000..c8d5f73a498 --- /dev/null +++ b/boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm3210e-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/Kconfig b/boards/arm/stm32f1/stm3210e-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3210e-eval/Kconfig rename to boards/arm/stm32f1/stm3210e-eval/Kconfig diff --git a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig similarity index 98% rename from boards/arm/stm32/stm3210e-eval/configs/composite/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig index 4d34cbf1d2f..ceb671630ba 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/composite/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/composite/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig index 47fd55dd162..7b6a0aa1410 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig similarity index 99% rename from boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig index e4725eae5e5..9fab1ef45c7 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nsh2/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig similarity index 98% rename from boards/arm/stm32/stm3210e-eval/configs/nx/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig index 6b36c1764c1..280f178d64d 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nx/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nx/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig similarity index 98% rename from boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig index b0bb9f6722e..aeaf6de160c 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/nxterm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig similarity index 99% rename from boards/arm/stm32/stm3210e-eval/configs/pm/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig index b463e9b6cb4..bf5f62f52cc 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/pm/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/pm/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig index cf8067e033f..862ffdecb9e 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbmsc/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbmsc/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig similarity index 97% rename from boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig rename to boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig index 2e238975a91..0fda54afcae 100644 --- a/boards/arm/stm32/stm3210e-eval/configs/usbserial/defconfig +++ b/boards/arm/stm32f1/stm3210e-eval/configs/usbserial/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3210e-eval" CONFIG_ARCH_BOARD_STM3210E_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103ZE=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm3210e-eval/include/board.h b/boards/arm/stm32f1/stm3210e-eval/include/board.h similarity index 99% rename from boards/arm/stm32/stm3210e-eval/include/board.h rename to boards/arm/stm32f1/stm3210e-eval/include/board.h index 6f3c4414492..ad0c8628d22 100644 --- a/boards/arm/stm32/stm3210e-eval/include/board.h +++ b/boards/arm/stm32f1/stm3210e-eval/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/include/board.h + * boards/arm/stm32f1/stm3210e-eval/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm3210e-eval/scripts/Make.defs rename to boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs index 7087042362d..42002bd0d29 100644 --- a/boards/arm/stm32/stm3210e-eval/scripts/Make.defs +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3210e-eval/scripts/Make.defs +# boards/arm/stm32f1/stm3210e-eval/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm3210e-eval/scripts/ld.script rename to boards/arm/stm32f1/stm3210e-eval/scripts/ld.script index afebfee8ace..0f14faebace 100644 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu rename to boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu index 24bf37b6b6b..1a8c3f20a86 100644 --- a/boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/scripts/ld.script.dfu + * boards/arm/stm32f1/stm3210e-eval/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt rename to boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt index b870c533c1c..34dd5c8b285 100644 --- a/boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm3210e-eval/src/CMakeLists.txt +# boards/arm/stm32f1/stm3210e-eval/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3210e-eval/src/Make.defs b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/Make.defs rename to boards/arm/stm32f1/stm3210e-eval/src/Make.defs index 9815a6acb2d..06d9de85d5a 100644 --- a/boards/arm/stm32/stm3210e-eval/src/Make.defs +++ b/boards/arm/stm32f1/stm3210e-eval/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3210e-eval/src/Make.defs +# boards/arm/stm32f1/stm3210e-eval/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h rename to boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h index 0f56d7a9328..f97c09d7bf2 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm3210e-eval.h + * boards/arm/stm32f1/stm3210e-eval/src/stm3210e-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -32,7 +32,7 @@ #include -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_adc.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c index fc374d2a837..dca12d9b1b8 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_adc.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_adc.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_boot.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c index e4a1125248a..cb9730521db 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_boot.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c index 3a6d49c8f43..45beb076a26 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_bringup.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c index c60b60a4d50..9833133076a 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_buttons.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_can.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c index 9ef1ed80279..4bd62db364e 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_can.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_can.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_composite.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c index b955808ef1b..7eaeac51120 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_composite.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_composite.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_composite.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c index 4b10bfee096..e36b381ba7c 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectlcd.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c index 64260e98038..1798b2b4c94 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c similarity index 97% rename from boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c index 42bed7c9f85..2a23173f2a4 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_deselectsram.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_deselectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c index acd4aa605df..4b3b7868e33 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_djoystick.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_djoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c index c6b2b4afc38..64f822a232f 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extcontext.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extcontext.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c index e40b69a0985..3b2779e4ffb 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_extmem.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_idle.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c index 6420bf627a4..1c4cb71b0df 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_idle.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_idle.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c index 9195f4a7c88..f0b29a830d7 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_lcd.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c similarity index 99% rename from boards/arm/stm32/stm3210e-eval/src/stm32_leds.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c index 56d005a627c..d2b6e2f5f57 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_leds.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_leds.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_pm.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c index 867ea413b5c..0f4aa4ac80b 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pm.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pm.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c index 20fd76a4af2..bc9823007cd 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_pmbuttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c index d128d108edd..f506a43e459 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectlcd.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c index ce5039b0501..f5823c781e2 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectnor.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectnor.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c index 3569e423e7c..6d46f6c872e 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_selectsram.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_selectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_spi.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c index 61a21c6674a..69641713aa0 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_spi.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_spi.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c index ba8518ef085..ac892b7e8af 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbdev.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c similarity index 98% rename from boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c rename to boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c index 6abb8c388fe..ecb66a7f25d 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3210e-eval/src/stm32_usbmsc.c + * boards/arm/stm32f1/stm3210e-eval/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh similarity index 96% rename from boards/arm/stm32/stm3210e-eval/tools/oocd.sh rename to boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh index 66a7cca63d0..04c7a7606c2 100755 --- a/boards/arm/stm32/stm3210e-eval/tools/oocd.sh +++ b/boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh @@ -44,7 +44,7 @@ fi # Local search directory and configurations -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f1/stm3210e-eval/tools" OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" diff --git a/boards/arm/stm32/stm3210e-eval/tools/stm32.cfg b/boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/stm32.cfg rename to boards/arm/stm32f1/stm3210e-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt b/boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3210e-eval/tools/usb-driver.txt rename to boards/arm/stm32f1/stm3210e-eval/tools/usb-driver.txt diff --git a/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt new file mode 100644 index 00000000000..a22235736fc --- /dev/null +++ b/boards/arm/stm32f1/stm32_tiny/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32_tiny/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32_tiny/Kconfig b/boards/arm/stm32f1/stm32_tiny/Kconfig similarity index 100% rename from boards/arm/stm32/stm32_tiny/Kconfig rename to boards/arm/stm32f1/stm32_tiny/Kconfig diff --git a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32_tiny/configs/nsh/defconfig rename to boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig index d8ef1dff900..b6dfc1579c2 100644 --- a/boards/arm/stm32/stm32_tiny/configs/nsh/defconfig +++ b/boards/arm/stm32f1/stm32_tiny/configs/nsh/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32_tiny" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig rename to boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig index 3ff9fd0c32e..0b88bf69134 100644 --- a/boards/arm/stm32/stm32_tiny/configs/usbnsh/defconfig +++ b/boards/arm/stm32f1/stm32_tiny/configs/usbnsh/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32_tiny" CONFIG_ARCH_BOARD_STM32_TINY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32_tiny/include/board.h b/boards/arm/stm32f1/stm32_tiny/include/board.h similarity index 99% rename from boards/arm/stm32/stm32_tiny/include/board.h rename to boards/arm/stm32f1/stm32_tiny/include/board.h index 26354257da2..2a9a1ac8c92 100644 --- a/boards/arm/stm32/stm32_tiny/include/board.h +++ b/boards/arm/stm32f1/stm32_tiny/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/include/board.h + * boards/arm/stm32f1/stm32_tiny/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/scripts/Make.defs b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/axoloti/scripts/Make.defs rename to boards/arm/stm32f1/stm32_tiny/scripts/Make.defs index e284200c3ba..fd9ee583e07 100644 --- a/boards/arm/stm32/axoloti/scripts/Make.defs +++ b/boards/arm/stm32f1/stm32_tiny/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/axoloti/scripts/Make.defs +# boards/arm/stm32f1/stm32_tiny/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32_tiny/scripts/ld.script b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32_tiny/scripts/ld.script rename to boards/arm/stm32f1/stm32_tiny/scripts/ld.script index 4ce9e558389..d8c2424728f 100644 --- a/boards/arm/stm32/stm32_tiny/scripts/ld.script +++ b/boards/arm/stm32f1/stm32_tiny/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/scripts/ld.script + * boards/arm/stm32f1/stm32_tiny/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32_tiny/src/CMakeLists.txt rename to boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt index c73b5cfb5bd..b09d5da50b7 100644 --- a/boards/arm/stm32/stm32_tiny/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32_tiny/src/CMakeLists.txt +# boards/arm/stm32f1/stm32_tiny/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32_tiny/src/Make.defs b/boards/arm/stm32f1/stm32_tiny/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32_tiny/src/Make.defs rename to boards/arm/stm32f1/stm32_tiny/src/Make.defs index a8268fc3401..3e58ff4b7fe 100644 --- a/boards/arm/stm32/stm32_tiny/src/Make.defs +++ b/boards/arm/stm32f1/stm32_tiny/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32_tiny/src/Make.defs +# boards/arm/stm32f1/stm32_tiny/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_boot.c rename to boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c index 978fee88af4..b392a99ddf8 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_boot.c + * boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_leds.c rename to boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c index 96ed9bf54df..79b15918460 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_leds.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_leds.c + * boards/arm/stm32f1/stm32_tiny/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_pwm.c rename to boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c index 3a4f9982399..332755c7b21 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_pwm.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_pwm.c + * boards/arm/stm32f1/stm32_tiny/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_spi.c rename to boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c index ff9d37e515a..0b27f331ef7 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_spi.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_spi.c + * boards/arm/stm32f1/stm32_tiny/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_tiny.h rename to boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h index 1d113843ecf..300fdd01bb1 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_tiny.h +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_tiny.h + * boards/arm/stm32f1/stm32_tiny/src/stm32_tiny.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c rename to boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c index 34a13f0c6fc..b183b6827ef 100644 --- a/boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32_tiny/src/stm32_usbdev.c + * boards/arm/stm32f1/stm32_tiny/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt new file mode 100644 index 00000000000..7c8a40cb663 --- /dev/null +++ b/boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32butterfly2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/Kconfig b/boards/arm/stm32f1/stm32butterfly2/Kconfig similarity index 100% rename from boards/arm/stm32/stm32butterfly2/Kconfig rename to boards/arm/stm32f1/stm32butterfly2/Kconfig diff --git a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig rename to boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig index 893268b7731..151be594518 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nsh/defconfig +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig similarity index 98% rename from boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig rename to boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig index 346a366f30e..4ffa586a44c 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshnet/defconfig +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshnet/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig similarity index 98% rename from boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig rename to boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig index 31c7bc88829..a2793fec932 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbdev/defconfig +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbdev/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig similarity index 98% rename from boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig rename to boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig index 893268b7731..151be594518 100644 --- a/boards/arm/stm32/stm32butterfly2/configs/nshusbhost/defconfig +++ b/boards/arm/stm32f1/stm32butterfly2/configs/nshusbhost/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32butterfly2" CONFIG_ARCH_BOARD_STM32_BUTTERFLY2=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32butterfly2/include/board.h b/boards/arm/stm32f1/stm32butterfly2/include/board.h similarity index 99% rename from boards/arm/stm32/stm32butterfly2/include/board.h rename to boards/arm/stm32f1/stm32butterfly2/include/board.h index 47811ad89f0..cef38c97de0 100644 --- a/boards/arm/stm32/stm32butterfly2/include/board.h +++ b/boards/arm/stm32f1/stm32butterfly2/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/include/board.h + * boards/arm/stm32f1/stm32butterfly2/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32butterfly2/scripts/Make.defs rename to boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs index 8fe66cdd72f..42d7ff815b5 100644 --- a/boards/arm/stm32/stm32butterfly2/scripts/Make.defs +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32butterfly2/scripts/Make.defs +# boards/arm/stm32f1/stm32butterfly2/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld similarity index 98% rename from boards/arm/stm32/stm32butterfly2/scripts/dfu.ld rename to boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld index 5901e67a909..dcdeb43f940 100644 --- a/boards/arm/stm32/stm32butterfly2/scripts/dfu.ld +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/dfu.ld + * boards/arm/stm32f1/stm32butterfly2/scripts/dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/stm32butterfly2/scripts/flash.ld rename to boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld index 57edf7919bc..3fc5750bbfc 100644 --- a/boards/arm/stm32/stm32butterfly2/scripts/flash.ld +++ b/boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/scripts/flash.ld + * boards/arm/stm32f1/stm32butterfly2/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt rename to boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt index 6e3faeea1a2..6005e74d05f 100644 --- a/boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32butterfly2/src/CMakeLists.txt +# boards/arm/stm32f1/stm32butterfly2/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32butterfly2/src/Make.defs b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32butterfly2/src/Make.defs rename to boards/arm/stm32f1/stm32butterfly2/src/Make.defs index 04fda674517..f6e1bc4b4f5 100644 --- a/boards/arm/stm32/stm32butterfly2/src/Make.defs +++ b/boards/arm/stm32f1/stm32butterfly2/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32butterfly2/src/Make.defs +# boards/arm/stm32f1/stm32butterfly2/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c similarity index 97% rename from boards/arm/stm32/stm32butterfly2/src/stm32_adc.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c index 1c15f9556a9..e38387e607b 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_adc.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_adc.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_boot.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c index de6bf256cf4..b3391b7eb56 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_boot.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h index f034a407985..1f7def66799 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_butterfly2.h + * boards/arm/stm32f1/stm32butterfly2/src/stm32_butterfly2.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c index 9de138b47b0..8f5f81e84e8 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_buttons.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c similarity index 99% rename from boards/arm/stm32/stm32butterfly2/src/stm32_leds.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c index c2d1d4b4f26..08723b68358 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_leds.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_leds.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c similarity index 99% rename from boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c index 50b5bc9ea60..b471480af34 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_mmcsd.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_spi.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c index 9044b910a78..0d6e77b58db 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_spi.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_spi.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c similarity index 97% rename from boards/arm/stm32/stm32butterfly2/src/stm32_usb.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c index 56ebf480d74..53cdb720cf8 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usb.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usb.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c similarity index 97% rename from boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c index 8bdb6fce116..b7414d0669f 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbdev.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c similarity index 98% rename from boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c rename to boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c index 7d5c6a160e4..6510e703c9b 100644 --- a/boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c +++ b/boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32butterfly2/src/stm32_usbhost.c + * boards/arm/stm32f1/stm32butterfly2/src/stm32_usbhost.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt new file mode 100644 index 00000000000..617cc91dd88 --- /dev/null +++ b/boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32f103-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/Kconfig b/boards/arm/stm32f1/stm32f103-minimum/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f103-minimum/Kconfig rename to boards/arm/stm32f1/stm32f103-minimum/Kconfig diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig index d907586a307..36fb231b5a9 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/adb/defconfig @@ -32,7 +32,7 @@ CONFIG_ADBD_USB_SERVER=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig index 6104e46be6d..cbb116b3a53 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/apds9960/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/apds9960/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig index b8535b6a90f..002da5d5dbb 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/audio_tone/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/audio_tone/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig index cd55e62de45..1909d11c9d4 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/buttons/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/buttons/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/can/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig index 10d91ed5c67..1ef7b1dec1d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/can/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/can/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig index ac563e19f7b..175e2d56fbc 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/hello/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/hello/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig index 03814d1bd53..abeabb55778 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/jlx12864g/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/jlx12864g/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig index 29472d4f0ac..d9b48e9bb91 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/lcd1602/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/lcd1602/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig index 3a16a7bc3ed..f86c33c470a 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/mcp2515/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/mcp2515/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig index fe3f09845e6..9c543b8150d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nrf24/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nrf24/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig index 93f668740d1..17c41e7e904 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/nsh/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig index d8c11ad84e0..36708cff594 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/pwm/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig index dfff987949b..8a19f920589 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rfid-rc522/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rfid-rc522/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig index 047341ed0b4..f13a1496852 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/rgbled/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig index 3fd2d3dbf38..ded90e2212a 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/sensors/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/sensors/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig index 66f457ffcf6..88c42001647 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/ssd1306/defconfig @@ -33,7 +33,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig index c88a05558e1..0f71cd16246 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/usbnsh/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/usbnsh/defconfig @@ -21,7 +21,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig index 3977f0bef72..a1bd26f706d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/userled/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/userled/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig rename to boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig index 9fa8c828abe..79db5a7a98f 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/veml6070/defconfig +++ b/boards/arm/stm32f1/stm32f103-minimum/configs/veml6070/defconfig @@ -20,7 +20,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f103-minimum" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F103_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103C8=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32f103-minimum/include/board.h b/boards/arm/stm32f1/stm32f103-minimum/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/include/board.h rename to boards/arm/stm32f1/stm32f103-minimum/include/board.h index 36ed8ae7f69..52c125f7cc8 100644 --- a/boards/arm/stm32/stm32f103-minimum/include/board.h +++ b/boards/arm/stm32f1/stm32f103-minimum/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/include/board.h + * boards/arm/stm32f1/stm32f103-minimum/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/scripts/Make.defs rename to boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs index 6d4f1b4b8c9..2fc72d54d7f 100644 --- a/boards/arm/stm32/stm32f103-minimum/scripts/Make.defs +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f103-minimum/scripts/Make.defs +# boards/arm/stm32f1/stm32f103-minimum/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/scripts/ld.script rename to boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script index 38b17fb8915..2b4373a3956 100644 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu rename to boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu index e9a9a6b75d2..28a18a1d04a 100644 --- a/boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu +++ b/boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/scripts/ld.script.dfu + * boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script.dfu * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt rename to boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt index 06607962aed..20cf6395910 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f103-minimum/src/CMakeLists.txt +# boards/arm/stm32f1/stm32f103-minimum/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f103-minimum/src/Make.defs b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/Make.defs rename to boards/arm/stm32f1/stm32f103-minimum/src/Make.defs index a0fc84fc4ee..c704b2c3564 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/Make.defs +++ b/boards/arm/stm32f1/stm32f103-minimum/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f103-minimum/src/Make.defs +# boards/arm/stm32f1/stm32f103-minimum/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c index 2da9c070aff..ab527d7429e 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_adc.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c index 0204fcfa0de..f4ac9eccdcc 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_at24.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_at24.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c index 5a352af6e54..341981c8dd2 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_autoleds.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c index 0f4f0c9e0a5..029f62453ed 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_boot.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c index 518bffcec4a..90273d10732 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c index 44fa04b7ace..55775a26fd9 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_buttons.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_can.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c index 4d0d37d09c6..3b80bc794fd 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_can.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_can.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c index 47da3f32fb9..db15840d4b8 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_cansock.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c index 91b7c4e8da0..3749f5d14c0 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_ds18b20.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_ds18b20.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c index 5806b9579bd..aa0cf6dc13b 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_gpio.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c index e054a450031..7ebd76dd08a 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_hyt271.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_hyt271.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c index adff376b279..206ed62e678 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_ssd1306.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c index 97381277ed0..e0337214ebf 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_lcd_st7567.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_lcd_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c index 79dc5aa1120..d4205a9f0e5 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_max7219.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_max7219.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c index 71ba958c155..ed9b317847f 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mcp2515.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mcp2515.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c index 96c77106410..a8aa3c85489 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_mmcsd.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c index 1bff3d3426a..da8ff4b7a22 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pcd8544.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pcd8544.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c index fb7dc02e793..8cdb0e0fe6e 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_pwm.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c index 40e3e2659b8..886ca544518 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_reset.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * @@ -63,4 +63,3 @@ int board_reset(int status) up_systemreset(); return 0; } - diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c index 3ba2dc47d78..5363f128f71 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_rgbled.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_rgbled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c index 4cb79126a6d..46f22b8038b 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_spi.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c index 9cf25efa67c..812481439f9 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbdev.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c index 3ab090b7c65..d7e83b0581e 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_usbmsc.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c index 7ae565c5719..96c7b060568 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_userleds.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c index 3303c6eabbf..96b95da27ca 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32_w25.c + * boards/arm/stm32f1/stm32f103-minimum/src/stm32_w25.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h similarity index 99% rename from boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h rename to boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h index a3cac399ded..5270b996e1c 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h +++ b/boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f103-minimum/src/stm32f103_minimum.h + * boards/arm/stm32f1/stm32f103-minimum/src/stm32f103_minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt new file mode 100644 index 00000000000..82b0be5e77c --- /dev/null +++ b/boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/stm32vldiscovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/Kconfig b/boards/arm/stm32f1/stm32vldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32vldiscovery/Kconfig rename to boards/arm/stm32f1/stm32vldiscovery/Kconfig diff --git a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig rename to boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig index 388c171d65c..dc5b5c596e9 100644 --- a/boards/arm/stm32/stm32vldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32vldiscovery" CONFIG_ARCH_BOARD_STM32VL_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F100RB=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/stm32vldiscovery/include/board.h b/boards/arm/stm32f1/stm32vldiscovery/include/board.h similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/include/board.h rename to boards/arm/stm32f1/stm32vldiscovery/include/board.h index 2d6b6419de4..cde0a062e8e 100644 --- a/boards/arm/stm32/stm32vldiscovery/include/board.h +++ b/boards/arm/stm32f1/stm32vldiscovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/include/board.h + * boards/arm/stm32f1/stm32vldiscovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/stm32vldiscovery/scripts/Make.defs rename to boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs index aba039baff4..ae0bf8f97a4 100644 --- a/boards/arm/stm32/stm32vldiscovery/scripts/Make.defs +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32vldiscovery/scripts/Make.defs +# boards/arm/stm32f1/stm32vldiscovery/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld rename to boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld index d0ce202ebf6..0decb5ac94d 100644 --- a/boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld +++ b/boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/scripts/stm32vldiscovery.ld + * boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt rename to boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt index ee0a0879fca..d28696c4196 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt +++ b/boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32vldiscovery/src/CMakeLists.txt +# boards/arm/stm32f1/stm32vldiscovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32vldiscovery/src/Make.defs b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs similarity index 95% rename from boards/arm/stm32/stm32vldiscovery/src/Make.defs rename to boards/arm/stm32f1/stm32vldiscovery/src/Make.defs index 9eef1f9e16d..2cac864f9dc 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/Make.defs +++ b/boards/arm/stm32f1/stm32vldiscovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32vldiscovery/src/Make.defs +# boards/arm/stm32f1/stm32vldiscovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c index cbdbe7788a8..dcf8e4960a1 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c index bf078df319d..fa7c252e326 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_bringup.c + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c index e5e62a4fa34..fe0a79c1754 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_buttons.c + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c similarity index 97% rename from boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c index 0bb0c88732a..084e3832633 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c + * boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h similarity index 97% rename from boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h rename to boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h index 23898505690..d3b31910712 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h +++ b/boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h + * boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt new file mode 100644 index 00000000000..23add80a6ac --- /dev/null +++ b/boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f1/viewtool-stm32f107/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/Kconfig b/boards/arm/stm32f1/viewtool-stm32f107/Kconfig similarity index 100% rename from boards/arm/stm32/viewtool-stm32f107/Kconfig rename to boards/arm/stm32f1/viewtool-stm32f107/Kconfig diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig rename to boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig index a12fed7ddbf..5cfee10bef7 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig rename to boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig index 1c9bac124dc..40363260dd6 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/highpri/defconfig +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F103VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig rename to boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig index 186f2553905..ff5671048b6 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/netnsh/defconfig +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig rename to boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig index 6a9adabea7b..04627a445fc 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/nsh/defconfig +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig rename to boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig index 30468070067..0feae7117d3 100644 --- a/boards/arm/stm32/viewtool-stm32f107/configs/tcpblaster/defconfig +++ b/boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="viewtool-stm32f107" CONFIG_ARCH_BOARD_VIEWTOOL_STM32F107=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F107VC=y CONFIG_ARCH_CHIP_STM32F1=y diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h index 3fa04fc7240..75e96c76459 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f103vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h index 4f88851d81d..ac40282bdcc 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board-stm32f107vct6.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/include/board.h b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/include/board.h rename to boards/arm/stm32f1/viewtool-stm32f107/include/board.h index 28494c647cc..dc37787be0c 100644 --- a/boards/arm/stm32/viewtool-stm32f107/include/board.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/include/board.h + * boards/arm/stm32f1/viewtool-stm32f107/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs rename to boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs index 1aa5da98b3f..6789123bb8c 100644 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/viewtool-stm32f107/scripts/Make.defs +# boards/arm/stm32f1/viewtool-stm32f107/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld rename to boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld index 8dda6388063..a83768dd096 100644 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/dfu.ld + * boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld rename to boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld index 5cd741cedc8..904f9b611a6 100644 --- a/boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld +++ b/boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/scripts/flash.ld + * boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt rename to boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt index c994fa4536c..c801fe9de87 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/src/CMakeLists.txt +# boards/arm/stm32f1/viewtool-stm32f107/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/src/Make.defs rename to boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs index 260a9270b30..00ba8c4b620 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/Make.defs +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/viewtool-stm32f107/src/Make.defs +# boards/arm/stm32f1/viewtool-stm32f107/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c index 99c2c0315eb..9982aca8aa2 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ads7843e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c index c7eada92098..a5b6fbb767c 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_boot.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c index c9cfd7c6591..a8ea0f11135 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_bringup.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c index 38d6fbedecf..427e07f6c76 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_buttons.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c index ae2e41e792c..672a1294a2b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_can.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c index 59620fcab0f..cba254d5570 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ft80x.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c index b9d97434c77..d7a113d035b 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c index fb495d7e018..51573cbff75 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_leds.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c index b7b6d1053be..f397f092523 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_max3421e.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c index 7720b136bfd..318d2badb54 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_mmcsd.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c index 317acedc809..04ec48f81d2 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_spi.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c index 527956b6f1d..4d80b05f9d8 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c similarity index 98% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c index c0d3001b339..c94e99e18cd 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbdev.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c rename to boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c index 015af8a323d..2a2d8f29847 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/stm32_usbmsc.c + * boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h similarity index 99% rename from boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h rename to boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h index be6c8199aff..35c858e0a75 100644 --- a/boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h +++ b/boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/viewtool-stm32f107/src/viewtool_stm32f107.h + * boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h * * SPDX-License-Identifier: Apache-2.0 * From c94805fe7438d67625e03885cd4249b102b12c55 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 156/268] !arch/stm32: move stm32f2 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f2 sources, headers and boards into arch/arm/src/stm32f2, arch/arm/include/stm32f2 and boards/arm/stm32f2. Signed-off-by: raiden00pl --- arch/arm/include/stm32f2/chip.h | 189 ++++++++++++++ .../stm32f20xxx_irq.h => stm32f2/irq.h} | 78 +++--- arch/arm/src/stm32f2/CMakeLists.txt | 28 +++ arch/arm/src/stm32f2/Kconfig | 184 ++++++++++++++ arch/arm/src/stm32f2/Make.defs | 27 ++ arch/arm/src/stm32f2/chip.h | 59 +++++ .../src/stm32f2/hardware/stm32_memorymap.h | 17 ++ arch/arm/src/stm32f2/hardware/stm32_pinmap.h | 17 ++ .../hardware/stm32f20xxx_gpio.h | 2 +- .../hardware/stm32f20xxx_memorymap.h | 2 +- .../hardware/stm32f20xxx_pinmap.h | 2 +- .../hardware/stm32f20xxx_rcc.h | 2 +- .../hardware/stm32f20xxx_syscfg.h | 2 +- arch/arm/src/stm32f2/stm32.h | 69 ++++++ arch/arm/src/stm32f2/stm32_rcc.c | 234 ++++++++++++++++++ .../src/{stm32 => stm32f2}/stm32f20xxx_rcc.c | 2 +- boards/arm/stm32f2/common/CMakeLists.txt | 25 ++ boards/arm/stm32f2/common/Kconfig | 6 + boards/arm/stm32f2/common/Makefile | 38 +++ .../emw3162}/CMakeLists.txt | 2 +- boards/arm/{stm32 => stm32f2}/emw3162/Kconfig | 0 .../emw3162/configs/nsh/defconfig | 2 +- .../emw3162/configs/wlan/defconfig | 2 +- .../emw3162/include/board.h | 2 +- .../emw3162/scripts/Make.defs | 2 +- .../emw3162/scripts/ld.script | 2 +- .../emw3162/src/CMakeLists.txt | 2 +- .../{stm32 => stm32f2}/emw3162/src/Make.defs | 2 +- .../{stm32 => stm32f2}/emw3162/src/emw3162.h | 4 +- .../emw3162/src/stm32_autoleds.c | 2 +- .../emw3162/src/stm32_boot.c | 2 +- .../emw3162/src/stm32_bringup.c | 2 +- .../emw3162/src/stm32_userleds.c | 2 +- .../emw3162/src/stm32_wlan.c | 2 +- .../emw3162/src/stm32_wlan_firmware.c | 0 .../arm/stm32f2/nucleo-f207zg/CMakeLists.txt | 23 ++ .../{stm32 => stm32f2}/nucleo-f207zg/Kconfig | 0 .../nucleo-f207zg/configs/adc/defconfig | 2 +- .../nucleo-f207zg/configs/nsh/defconfig | 2 +- .../nucleo-f207zg/configs/pwm/defconfig | 2 +- .../nucleo-f207zg/include/board.h | 2 +- .../nucleo-f207zg}/scripts/Make.defs | 2 +- .../nucleo-f207zg/scripts/ld.script | 2 +- .../nucleo-f207zg/src/CMakeLists.txt | 2 +- .../nucleo-f207zg/src/Make.defs | 2 +- .../nucleo-f207zg/src/nucleo-f207zg.h | 2 +- .../nucleo-f207zg/src/stm32_adc.c | 2 +- .../nucleo-f207zg/src/stm32_autoleds.c | 2 +- .../nucleo-f207zg/src/stm32_boot.c | 2 +- .../nucleo-f207zg/src/stm32_bringup.c | 2 +- .../nucleo-f207zg/src/stm32_buttons.c | 2 +- .../nucleo-f207zg/src/stm32_pwm.c | 2 +- .../nucleo-f207zg/src/stm32_usb.c | 2 +- .../nucleo-f207zg/src/stm32_userleds.c | 2 +- .../stm32f2/olimex-stm32-p207/CMakeLists.txt | 23 ++ .../olimex-stm32-p207/Kconfig | 0 .../olimex-stm32-p207/configs/nsh/defconfig | 2 +- .../olimex-stm32-p207/include/board.h | 2 +- .../olimex-stm32-p207}/scripts/Make.defs | 2 +- .../olimex-stm32-p207/scripts/ld.script | 2 +- .../olimex-stm32-p207}/src/CMakeLists.txt | 2 +- .../olimex-stm32-p207/src/Make.defs | 2 +- .../olimex-stm32-p207/src/olimex-stm32-p207.h | 2 +- .../olimex-stm32-p207/src/stm32_adc.c | 2 +- .../olimex-stm32-p207/src/stm32_autoleds.c | 2 +- .../olimex-stm32-p207/src/stm32_boot.c | 2 +- .../olimex-stm32-p207/src/stm32_buttons.c | 2 +- .../olimex-stm32-p207/src/stm32_can.c | 2 +- .../olimex-stm32-p207/src/stm32_usb.c | 2 +- .../olimex-stm32-p207/src/stm32_userleds.c | 2 +- .../photon}/CMakeLists.txt | 2 +- boards/arm/{stm32 => stm32f2}/photon/Kconfig | 0 .../photon/configs/adb/defconfig | 2 +- .../photon/configs/nsh/defconfig | 2 +- .../photon/configs/rgbled/defconfig | 2 +- .../photon/configs/usbnsh/defconfig | 2 +- .../photon/configs/wlan-perf/defconfig | 2 +- .../photon/configs/wlan/defconfig | 2 +- .../{stm32 => stm32f2}/photon/include/board.h | 2 +- .../photon/scripts/Make.defs | 2 +- .../photon/scripts/photon_dfu.ld | 2 +- .../photon/scripts/photon_jtag.ld | 2 +- .../photon/src/CMakeLists.txt | 2 +- .../{stm32 => stm32f2}/photon/src/Make.defs | 2 +- .../photon/src/dfu_signature.c | 2 +- .../{stm32 => stm32f2}/photon/src/photon.h | 4 +- .../photon/src/stm32_autoleds.c | 2 +- .../photon/src/stm32_boot.c | 2 +- .../photon/src/stm32_bringup.c | 2 +- .../photon/src/stm32_buttons.c | 2 +- .../photon/src/stm32_composite.c | 2 +- .../photon/src/stm32_rgbled.c | 2 +- .../{stm32 => stm32f2}/photon/src/stm32_spi.c | 2 +- .../{stm32 => stm32f2}/photon/src/stm32_usb.c | 2 +- .../photon/src/stm32_userleds.c | 2 +- .../{stm32 => stm32f2}/photon/src/stm32_wdt.c | 2 +- .../photon/src/stm32_wlan.c | 2 +- .../photon/src/stm32_wlan_firmware.c | 2 +- .../arm/stm32f2/stm3220g-eval/CMakeLists.txt | 23 ++ .../{stm32 => stm32f2}/stm3220g-eval/Kconfig | 0 .../stm3220g-eval/configs/dhcpd/defconfig | 2 +- .../stm3220g-eval/configs/nettest/defconfig | 2 +- .../stm3220g-eval/configs/nsh/defconfig | 2 +- .../stm3220g-eval/configs/nsh2/defconfig | 2 +- .../stm3220g-eval/configs/nxwm/defconfig | 2 +- .../stm3220g-eval/configs/telnetd/defconfig | 2 +- .../stm3220g-eval/include/board.h | 2 +- .../stm3220g-eval}/scripts/Make.defs | 2 +- .../stm3220g-eval/scripts/ld.script | 2 +- .../stm3220g-eval/src/CMakeLists.txt | 2 +- .../stm3220g-eval/src/Make.defs | 2 +- .../stm3220g-eval/src/stm3220g-eval.h | 2 +- .../stm3220g-eval/src/stm32_adc.c | 2 +- .../stm3220g-eval/src/stm32_autoleds.c | 2 +- .../stm3220g-eval/src/stm32_boot.c | 2 +- .../stm3220g-eval/src/stm32_buttons.c | 2 +- .../stm3220g-eval/src/stm32_can.c | 2 +- .../stm3220g-eval/src/stm32_deselectlcd.c | 2 +- .../stm3220g-eval/src/stm32_deselectsram.c | 2 +- .../stm3220g-eval/src/stm32_extmem.c | 2 +- .../stm3220g-eval/src/stm32_lcd.c | 2 +- .../stm3220g-eval/src/stm32_pwm.c | 2 +- .../stm3220g-eval/src/stm32_selectlcd.c | 2 +- .../stm3220g-eval/src/stm32_selectsram.c | 2 +- .../stm3220g-eval/src/stm32_spi.c | 2 +- .../stm3220g-eval/src/stm32_stmpe811.c | 2 +- .../stm3220g-eval/src/stm32_usb.c | 2 +- .../stm3220g-eval/src/stm32_userleds.c | 2 +- .../tools/olimex-arm-usb-ocd.cfg | 0 .../stm3220g-eval/tools/oocd.sh | 2 +- .../stm3220g-eval/tools/stm32.cfg | 0 .../stm3220g-eval/tools/usb-driver.txt | 0 132 files changed, 1108 insertions(+), 150 deletions(-) create mode 100644 arch/arm/include/stm32f2/chip.h rename arch/arm/include/{stm32/stm32f20xxx_irq.h => stm32f2/irq.h} (85%) create mode 100644 arch/arm/src/stm32f2/CMakeLists.txt create mode 100644 arch/arm/src/stm32f2/Kconfig create mode 100644 arch/arm/src/stm32f2/Make.defs create mode 100644 arch/arm/src/stm32f2/chip.h create mode 100644 arch/arm/src/stm32f2/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f2/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32f2}/hardware/stm32f20xxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32f2}/hardware/stm32f20xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f2}/hardware/stm32f20xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f2}/hardware/stm32f20xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f2}/hardware/stm32f20xxx_syscfg.h (99%) create mode 100644 arch/arm/src/stm32f2/stm32.h create mode 100644 arch/arm/src/stm32f2/stm32_rcc.c rename arch/arm/src/{stm32 => stm32f2}/stm32f20xxx_rcc.c (99%) create mode 100644 boards/arm/stm32f2/common/CMakeLists.txt create mode 100644 boards/arm/stm32f2/common/Kconfig create mode 100644 boards/arm/stm32f2/common/Makefile rename boards/arm/{stm32/cloudctrl => stm32f2/emw3162}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f2}/emw3162/Kconfig (100%) rename boards/arm/{stm32 => stm32f2}/emw3162/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f2}/emw3162/configs/wlan/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/include/board.h (99%) rename boards/arm/{stm32 => stm32f2}/emw3162/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f2}/emw3162/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/emw3162.h (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_userleds.c (97%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_wlan.c (99%) rename boards/arm/{stm32 => stm32f2}/emw3162/src/stm32_wlan_firmware.c (100%) create mode 100644 boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/Kconfig (100%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/configs/adc/defconfig (97%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/configs/pwm/defconfig (97%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/include/board.h (99%) rename boards/arm/{stm32/mikroe-stm32f4 => stm32f2/nucleo-f207zg}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/nucleo-f207zg.h (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_bringup.c (97%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f2}/nucleo-f207zg/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/Kconfig (100%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/include/board.h (99%) rename boards/arm/{stm32/olimex-stm32-h405 => stm32f2/olimex-stm32-p207}/scripts/Make.defs (96%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/scripts/ld.script (98%) rename boards/arm/{stm32/olimex-stm32-h405 => stm32f2/olimex-stm32-p207}/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/olimex-stm32-p207.h (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_adc.c (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_can.c (98%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f2}/olimex-stm32-p207/src/stm32_userleds.c (98%) rename boards/arm/{stm32/odrive36 => stm32f2/photon}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f2}/photon/Kconfig (100%) rename boards/arm/{stm32 => stm32f2}/photon/configs/adb/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/photon/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f2}/photon/configs/rgbled/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/photon/configs/usbnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/photon/configs/wlan-perf/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/photon/configs/wlan/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/photon/include/board.h (99%) rename boards/arm/{stm32 => stm32f2}/photon/scripts/Make.defs (98%) rename boards/arm/{stm32 => stm32f2}/photon/scripts/photon_dfu.ld (98%) rename boards/arm/{stm32 => stm32f2}/photon/scripts/photon_jtag.ld (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f2}/photon/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f2}/photon/src/dfu_signature.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/photon.h (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_composite.c (99%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_rgbled.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_usb.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_userleds.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_wdt.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_wlan.c (98%) rename boards/arm/{stm32 => stm32f2}/photon/src/stm32_wlan_firmware.c (99%) create mode 100644 boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/Kconfig (100%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/dhcpd/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/nettest/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/nsh2/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/nxwm/defconfig (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/configs/telnetd/defconfig (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/include/board.h (99%) rename boards/arm/{stm32/nucleo-f103rb => stm32f2/stm3220g-eval}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm3220g-eval.h (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_adc.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_autoleds.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_can.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_deselectlcd.c (97%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_deselectsram.c (97%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_extmem.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_lcd.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_selectlcd.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_selectsram.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_spi.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_stmpe811.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/src/stm32_userleds.c (98%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg (100%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/tools/oocd.sh (96%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/tools/stm32.cfg (100%) rename boards/arm/{stm32 => stm32f2}/stm3220g-eval/tools/usb-driver.txt (100%) diff --git a/arch/arm/include/stm32f2/chip.h b/arch/arm/include/stm32f2/chip.h new file mode 100644 index 00000000000..6252fc7ad06 --- /dev/null +++ b/arch/arm/include/stm32f2/chip.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/arm/include/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F2_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 82 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 140 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ + defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +/* STM23 F3 Family **********************************************************/ + +/* Part Numbering: STM32Fssscfxxx + * + * Where + * sss = 302/303, 334 or 372/373 + * c = C (48pins) R (68 pins) V (100 pins) + * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) + * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) + * xxx = Package, temperature range, options (ignored here) + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F2_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32f20xxx_irq.h b/arch/arm/include/stm32f2/irq.h similarity index 85% rename from arch/arm/include/stm32/stm32f20xxx_irq.h rename to arch/arm/include/stm32f2/irq.h index fddc9841359..b91d6952fa9 100644 --- a/arch/arm/include/stm32/stm32f20xxx_irq.h +++ b/arch/arm/include/stm32f2/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f20xxx_irq.h + * arch/arm/include/stm32f2/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F2_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F2_IRQ_H /**************************************************************************** * Included Files @@ -33,21 +33,44 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. */ +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + #define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */ @@ -142,31 +165,4 @@ #define STM32_IRQ_NEXTINTS (81) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F20XXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F2_IRQ_H */ diff --git a/arch/arm/src/stm32f2/CMakeLists.txt b/arch/arm/src/stm32f2/CMakeLists.txt new file mode 100644 index 00000000000..79b7a470297 --- /dev/null +++ b/arch/arm/src/stm32f2/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f2/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f2/Kconfig b/arch/arm/src/stm32f2/Kconfig new file mode 100644 index 00000000000..a93ae1f0118 --- /dev/null +++ b/arch/arm/src/stm32f2/Kconfig @@ -0,0 +1,184 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F2 configuration" + +if ARCH_CHIP_STM32F2 + +choice + prompt "STM32F2 Chip Selection" + depends on ARCH_CHIP_STM32F2 + +config ARCH_CHIP_STM32F205RG + bool "STM32F205RG" + select STM32_STM32F20XX + select STM32_STM32F205 + +config ARCH_CHIP_STM32F207VC + bool "STM32F207VC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VE + bool "STM32F207VE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VF + bool "STM32F207VF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207VG + bool "STM32F207VG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IC + bool "STM32F207IC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IE + bool "STM32F207IE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IF + bool "STM32F207IF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207IG + bool "STM32F207IG" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZC + bool "STM32F207ZC" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZE + bool "STM32F207ZE" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZF + bool "STM32F207ZF" + select STM32_STM32F20XX + select STM32_STM32F207 + +config ARCH_CHIP_STM32F207ZG + bool "STM32F207ZG" + select STM32_STM32F20XX + select STM32_STM32F207 + +endchoice + +endif + +config STM32_STM32F20XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_HAVE_DCMI + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_OTGFS + select STM32_HAVE_OTGHS + select STM32_HAVE_SPI1 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_SYSCFG + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F205 + bool + default n + +config STM32_STM32F207 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_ETHMAC diff --git a/arch/arm/src/stm32f2/Make.defs b/arch/arm/src/stm32f2/Make.defs new file mode 100644 index 00000000000..b98256025f3 --- /dev/null +++ b/arch/arm/src/stm32f2/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f2/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f2/chip.h b/arch/arm/src/stm32f2/chip.h new file mode 100644 index 00000000000..4b555d13fb7 --- /dev/null +++ b/arch/arm/src/stm32f2/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_CHIP_H +#define __ARCH_ARM_SRC_STM32F2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F2_CHIP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..4037ce463e1 --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f2/hardware/stm32_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..e9a0e492b35 --- /dev/null +++ b/arch/arm/src/stm32f2/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f20xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32F2_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h index ebb05948282..32ab85cc3df 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_gpio.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h index 189e5a7a081..d55645a1ac5 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_memorymap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h index aa7f4da6bfb..544806fd181 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_pinmap.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h index c447c70bf6a..31af35f07a1 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_rcc.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h rename to arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h index 954c0466331..c4ad192e1ee 100644 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h +++ b/arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_syscfg.h + * arch/arm/src/stm32f2/hardware/stm32f20xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f2/stm32.h b/arch/arm/src/stm32f2/stm32.h new file mode 100644 index 00000000000..9069ebcbca6 --- /dev/null +++ b/arch/arm/src/stm32f2/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f2/stm32_rcc.c b/arch/arm/src/stm32f2/stm32_rcc.c new file mode 100644 index 00000000000..7452375136a --- /dev/null +++ b/arch/arm/src/stm32f2/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f2/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f20xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f20xxx_rcc.c b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f20xxx_rcc.c rename to arch/arm/src/stm32f2/stm32f20xxx_rcc.c index eb9e97e0ed8..30c8f34740d 100644 --- a/arch/arm/src/stm32/stm32f20xxx_rcc.c +++ b/arch/arm/src/stm32f2/stm32f20xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f20xxx_rcc.c + * arch/arm/src/stm32f2/stm32f20xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/common/CMakeLists.txt b/boards/arm/stm32f2/common/CMakeLists.txt new file mode 100644 index 00000000000..05c541018bc --- /dev/null +++ b/boards/arm/stm32f2/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32f2/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32f2/common/Kconfig b/boards/arm/stm32f2/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32f2/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f2/common/Makefile b/boards/arm/stm32f2/common/Makefile new file mode 100644 index 00000000000..e87bad2ffe0 --- /dev/null +++ b/boards/arm/stm32f2/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32f2/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32/cloudctrl/CMakeLists.txt b/boards/arm/stm32f2/emw3162/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/cloudctrl/CMakeLists.txt rename to boards/arm/stm32f2/emw3162/CMakeLists.txt index 17ccd5a4c78..3ae13f51fc4 100644 --- a/boards/arm/stm32/cloudctrl/CMakeLists.txt +++ b/boards/arm/stm32f2/emw3162/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/cloudctrl/CMakeLists.txt +# boards/arm/stm32f2/emw3162/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/emw3162/Kconfig b/boards/arm/stm32f2/emw3162/Kconfig similarity index 100% rename from boards/arm/stm32/emw3162/Kconfig rename to boards/arm/stm32f2/emw3162/Kconfig diff --git a/boards/arm/stm32/emw3162/configs/nsh/defconfig b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/emw3162/configs/nsh/defconfig rename to boards/arm/stm32f2/emw3162/configs/nsh/defconfig index fc40697134b..ba23a8e0b0e 100644 --- a/boards/arm/stm32/emw3162/configs/nsh/defconfig +++ b/boards/arm/stm32f2/emw3162/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="emw3162" CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/emw3162/configs/wlan/defconfig b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig similarity index 98% rename from boards/arm/stm32/emw3162/configs/wlan/defconfig rename to boards/arm/stm32f2/emw3162/configs/wlan/defconfig index ccfcd0a4584..a623c00de35 100644 --- a/boards/arm/stm32/emw3162/configs/wlan/defconfig +++ b/boards/arm/stm32f2/emw3162/configs/wlan/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="emw3162" CONFIG_ARCH_BOARD_EMW3162=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/emw3162/include/board.h b/boards/arm/stm32f2/emw3162/include/board.h similarity index 99% rename from boards/arm/stm32/emw3162/include/board.h rename to boards/arm/stm32f2/emw3162/include/board.h index 96825cff434..04fe380ce64 100644 --- a/boards/arm/stm32/emw3162/include/board.h +++ b/boards/arm/stm32f2/emw3162/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/include/board.h + * boards/arm/stm32f2/emw3162/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/scripts/Make.defs b/boards/arm/stm32f2/emw3162/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/emw3162/scripts/Make.defs rename to boards/arm/stm32f2/emw3162/scripts/Make.defs index bc77620c6b4..0f1c1fb18dd 100644 --- a/boards/arm/stm32/emw3162/scripts/Make.defs +++ b/boards/arm/stm32f2/emw3162/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/emw3162/scripts/Make.defs +# boards/arm/stm32f2/emw3162/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/emw3162/scripts/ld.script b/boards/arm/stm32f2/emw3162/scripts/ld.script similarity index 98% rename from boards/arm/stm32/emw3162/scripts/ld.script rename to boards/arm/stm32f2/emw3162/scripts/ld.script index 469fdbf5198..6728bf250c6 100644 --- a/boards/arm/stm32/emw3162/scripts/ld.script +++ b/boards/arm/stm32f2/emw3162/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/scripts/ld.script + * boards/arm/stm32f2/emw3162/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/CMakeLists.txt b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/emw3162/src/CMakeLists.txt rename to boards/arm/stm32f2/emw3162/src/CMakeLists.txt index 8c94250123d..74410fcc34e 100644 --- a/boards/arm/stm32/emw3162/src/CMakeLists.txt +++ b/boards/arm/stm32f2/emw3162/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/emw3162/src/CMakeLists.txt +# boards/arm/stm32f2/emw3162/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/emw3162/src/Make.defs b/boards/arm/stm32f2/emw3162/src/Make.defs similarity index 96% rename from boards/arm/stm32/emw3162/src/Make.defs rename to boards/arm/stm32f2/emw3162/src/Make.defs index f397baef02b..1cd6ec0b13d 100644 --- a/boards/arm/stm32/emw3162/src/Make.defs +++ b/boards/arm/stm32f2/emw3162/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/emw3162/src/Make.defs +# boards/arm/stm32f2/emw3162/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/emw3162/src/emw3162.h b/boards/arm/stm32f2/emw3162/src/emw3162.h similarity index 98% rename from boards/arm/stm32/emw3162/src/emw3162.h rename to boards/arm/stm32f2/emw3162/src/emw3162.h index 6142ab2310e..2930b329265 100644 --- a/boards/arm/stm32/emw3162/src/emw3162.h +++ b/boards/arm/stm32f2/emw3162/src/emw3162.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/emw3162.h + * boards/arm/stm32f2/emw3162/src/emw3162.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/emw3162/src/stm32_autoleds.c b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/emw3162/src/stm32_autoleds.c rename to boards/arm/stm32f2/emw3162/src/stm32_autoleds.c index cb2dd8f580b..e385fbbbd86 100644 --- a/boards/arm/stm32/emw3162/src/stm32_autoleds.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_autoleds.c + * boards/arm/stm32f2/emw3162/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/stm32_boot.c b/boards/arm/stm32f2/emw3162/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/emw3162/src/stm32_boot.c rename to boards/arm/stm32f2/emw3162/src/stm32_boot.c index fc3647ca0cf..afed8722823 100644 --- a/boards/arm/stm32/emw3162/src/stm32_boot.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_boot.c + * boards/arm/stm32f2/emw3162/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/stm32_bringup.c b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/emw3162/src/stm32_bringup.c rename to boards/arm/stm32f2/emw3162/src/stm32_bringup.c index 0ffd40553fc..f78b630f138 100644 --- a/boards/arm/stm32/emw3162/src/stm32_bringup.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_bringup.c + * boards/arm/stm32f2/emw3162/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/stm32_userleds.c b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/emw3162/src/stm32_userleds.c rename to boards/arm/stm32f2/emw3162/src/stm32_userleds.c index 61d304b6cf6..51cadf4321b 100644 --- a/boards/arm/stm32/emw3162/src/stm32_userleds.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_userleds.c + * boards/arm/stm32f2/emw3162/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c similarity index 99% rename from boards/arm/stm32/emw3162/src/stm32_wlan.c rename to boards/arm/stm32f2/emw3162/src/stm32_wlan.c index d8a110dc14f..ff0e8ccaf1d 100644 --- a/boards/arm/stm32/emw3162/src/stm32_wlan.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/emw3162/src/stm32_wlan.c + * boards/arm/stm32f2/emw3162/src/stm32_wlan.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c similarity index 100% rename from boards/arm/stm32/emw3162/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/emw3162/src/stm32_wlan_firmware.c diff --git a/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt new file mode 100644 index 00000000000..4f4af60fbff --- /dev/null +++ b/boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/nucleo-f207zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/Kconfig b/boards/arm/stm32f2/nucleo-f207zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f207zg/Kconfig rename to boards/arm/stm32f2/nucleo-f207zg/Kconfig diff --git a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig rename to boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig index 019a6cec7cb..53b10cb1c26 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/adc/defconfig +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/adc/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig rename to boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig index 0bba482d3d2..2679b5c5e8b 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/nsh/defconfig +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig rename to boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig index 785cc7e2c1b..04c5b15c502 100644 --- a/boards/arm/stm32/nucleo-f207zg/configs/pwm/defconfig +++ b/boards/arm/stm32f2/nucleo-f207zg/configs/pwm/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f207zg" CONFIG_ARCH_BOARD_NUCLEO_F207ZG=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/nucleo-f207zg/include/board.h b/boards/arm/stm32f2/nucleo-f207zg/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f207zg/include/board.h rename to boards/arm/stm32f2/nucleo-f207zg/include/board.h index bf2ce642c59..62f9ed1e30e 100644 --- a/boards/arm/stm32/nucleo-f207zg/include/board.h +++ b/boards/arm/stm32f2/nucleo-f207zg/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/include/board.h + * boards/arm/stm32f2/nucleo-f207zg/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs rename to boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs index 36864251081..63f3a3eb5ce 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/mikroe-stm32f4/scripts/Make.defs +# boards/arm/stm32f2/nucleo-f207zg/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/scripts/ld.script rename to boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script index 0f8ef1906b0..5ea1a69efb1 100644 --- a/boards/arm/stm32/nucleo-f207zg/scripts/ld.script +++ b/boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/scripts/ld.script + * boards/arm/stm32f2/nucleo-f207zg/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt rename to boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt index 5ca78ff3da4..06e696f9570 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt +++ b/boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f207zg/src/CMakeLists.txt +# boards/arm/stm32f2/nucleo-f207zg/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f207zg/src/Make.defs b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-f207zg/src/Make.defs rename to boards/arm/stm32f2/nucleo-f207zg/src/Make.defs index 3962a5368fd..71bb086e057 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/Make.defs +++ b/boards/arm/stm32f2/nucleo-f207zg/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f207zg/src/Make.defs +# boards/arm/stm32f2/nucleo-f207zg/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h rename to boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h index c6d2497a864..26ec0f5cb09 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h +++ b/boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/nucleo-f207zg.h + * boards/arm/stm32f2/nucleo-f207zg/src/nucleo-f207zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c index 6a7e27ca6b7..3e2a2c19e32 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_adc.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c index 9a1986701ba..10db82a159e 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_autoleds.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c index 3f7ae0c33c1..5828a05c690 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_boot.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c index 149f1cc0930..1927f3bca09 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_bringup.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c index 861f569c31f..8638a37a4b6 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_buttons.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c index 298ae7ce617..a43f95dc57e 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_pwm.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c index d9840309112..6d3390be492 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_usb.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c rename to boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c index d0ce94829ee..7ee325e6000 100644 --- a/boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c +++ b/boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f207zg/src/stm32_userleds.c + * boards/arm/stm32f2/nucleo-f207zg/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt new file mode 100644 index 00000000000..f2381912c11 --- /dev/null +++ b/boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/olimex-stm32-p207/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/Kconfig b/boards/arm/stm32f2/olimex-stm32-p207/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p207/Kconfig rename to boards/arm/stm32f2/olimex-stm32-p207/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig rename to boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig index d8e2974ccfc..d74bd22eb86 100644 --- a/boards/arm/stm32/olimex-stm32-p207/configs/nsh/defconfig +++ b/boards/arm/stm32f2/olimex-stm32-p207/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p207" CONFIG_ARCH_BOARD_OLIMEX_STM32P207=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207ZE=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/olimex-stm32-p207/include/board.h b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p207/include/board.h rename to boards/arm/stm32f2/olimex-stm32-p207/include/board.h index 6a632373c9b..7ad51256922 100644 --- a/boards/arm/stm32/olimex-stm32-p207/include/board.h +++ b/boards/arm/stm32f2/olimex-stm32-p207/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/include/board.h + * boards/arm/stm32f2/olimex-stm32-p207/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs rename to boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs index ecd20a669ce..d8143a48fee 100644 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-h405/scripts/Make.defs +# boards/arm/stm32f2/olimex-stm32-p207/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/scripts/ld.script rename to boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script index d8e4a95fc73..b658404f87c 100644 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/ld.script +++ b/boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/scripts/ld.script + * boards/arm/stm32f2/olimex-stm32-p207/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt rename to boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt index 0fb338eadb5..1f6060c53a7 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/src/CMakeLists.txt +# boards/arm/stm32f2/olimex-stm32-p207/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p207/src/Make.defs rename to boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs index 42ceed74368..f506294680b 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/Make.defs +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p207/src/Make.defs +# boards/arm/stm32f2/olimex-stm32-p207/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h rename to boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h index 5f69d7f4934..30f8489f633 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/olimex-stm32-p207.h + * boards/arm/stm32f2/olimex-stm32-p207/src/olimex-stm32-p207.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c index 82241854400..4c75b624f49 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_adc.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c index 7455e3582f3..a748ff57c4c 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_autoleds.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c index 3ce6df06ea4..1fee37320cf 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_boot.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c index fbf2d1236ba..20089fe607e 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_buttons.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c index b2bf59dacf7..f64cb2f25b3 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_can.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c index 0217d0bdfd1..3931c992d82 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_usb.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c rename to boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c index 044ff84794d..b552c74f237 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c +++ b/boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p207/src/stm32_userleds.c + * boards/arm/stm32f2/olimex-stm32-p207/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/CMakeLists.txt b/boards/arm/stm32f2/photon/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/odrive36/CMakeLists.txt rename to boards/arm/stm32f2/photon/CMakeLists.txt index 430752bb2ce..425a22bcb9f 100644 --- a/boards/arm/stm32/odrive36/CMakeLists.txt +++ b/boards/arm/stm32f2/photon/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/odrive36/CMakeLists.txt +# boards/arm/stm32f2/photon/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/photon/Kconfig b/boards/arm/stm32f2/photon/Kconfig similarity index 100% rename from boards/arm/stm32/photon/Kconfig rename to boards/arm/stm32f2/photon/Kconfig diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32f2/photon/configs/adb/defconfig similarity index 98% rename from boards/arm/stm32/photon/configs/adb/defconfig rename to boards/arm/stm32f2/photon/configs/adb/defconfig index 51b74bca0df..08ea7b35969 100644 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ b/boards/arm/stm32f2/photon/configs/adb/defconfig @@ -18,7 +18,7 @@ CONFIG_ADBD_USB_SERVER=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/configs/nsh/defconfig b/boards/arm/stm32f2/photon/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/photon/configs/nsh/defconfig rename to boards/arm/stm32f2/photon/configs/nsh/defconfig index 4401baf4dfd..e5d1d5b3b9c 100644 --- a/boards/arm/stm32/photon/configs/nsh/defconfig +++ b/boards/arm/stm32f2/photon/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/configs/rgbled/defconfig b/boards/arm/stm32f2/photon/configs/rgbled/defconfig similarity index 98% rename from boards/arm/stm32/photon/configs/rgbled/defconfig rename to boards/arm/stm32f2/photon/configs/rgbled/defconfig index c8935b1083d..dc5e7d9718c 100644 --- a/boards/arm/stm32/photon/configs/rgbled/defconfig +++ b/boards/arm/stm32f2/photon/configs/rgbled/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/configs/usbnsh/defconfig b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/photon/configs/usbnsh/defconfig rename to boards/arm/stm32f2/photon/configs/usbnsh/defconfig index 80a40d20e62..d364c6b0c33 100644 --- a/boards/arm/stm32/photon/configs/usbnsh/defconfig +++ b/boards/arm/stm32f2/photon/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/configs/wlan-perf/defconfig b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig similarity index 98% rename from boards/arm/stm32/photon/configs/wlan-perf/defconfig rename to boards/arm/stm32f2/photon/configs/wlan-perf/defconfig index ccd836bce23..d763e1d77aa 100644 --- a/boards/arm/stm32/photon/configs/wlan-perf/defconfig +++ b/boards/arm/stm32f2/photon/configs/wlan-perf/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/configs/wlan/defconfig b/boards/arm/stm32f2/photon/configs/wlan/defconfig similarity index 98% rename from boards/arm/stm32/photon/configs/wlan/defconfig rename to boards/arm/stm32f2/photon/configs/wlan/defconfig index 97ef2d948dd..98f29fac9ed 100644 --- a/boards/arm/stm32/photon/configs/wlan/defconfig +++ b/boards/arm/stm32f2/photon/configs/wlan/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="photon" CONFIG_ARCH_BOARD_PHOTON=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F205RG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/photon/include/board.h b/boards/arm/stm32f2/photon/include/board.h similarity index 99% rename from boards/arm/stm32/photon/include/board.h rename to boards/arm/stm32f2/photon/include/board.h index 6c5ac34d01c..a26b8826bff 100644 --- a/boards/arm/stm32/photon/include/board.h +++ b/boards/arm/stm32f2/photon/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/include/board.h + * boards/arm/stm32f2/photon/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/scripts/Make.defs b/boards/arm/stm32f2/photon/scripts/Make.defs similarity index 98% rename from boards/arm/stm32/photon/scripts/Make.defs rename to boards/arm/stm32f2/photon/scripts/Make.defs index 12f4622680f..930772652d6 100644 --- a/boards/arm/stm32/photon/scripts/Make.defs +++ b/boards/arm/stm32f2/photon/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/photon/scripts/Make.defs +# boards/arm/stm32f2/photon/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/photon/scripts/photon_dfu.ld b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_dfu.ld rename to boards/arm/stm32f2/photon/scripts/photon_dfu.ld index 0272b8a7157..d5fdad6367d 100644 --- a/boards/arm/stm32/photon/scripts/photon_dfu.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_dfu.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_dfu.ld + * boards/arm/stm32f2/photon/scripts/photon_dfu.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/scripts/photon_jtag.ld b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld similarity index 98% rename from boards/arm/stm32/photon/scripts/photon_jtag.ld rename to boards/arm/stm32f2/photon/scripts/photon_jtag.ld index ca944b41a41..ad1ecad2b09 100644 --- a/boards/arm/stm32/photon/scripts/photon_jtag.ld +++ b/boards/arm/stm32f2/photon/scripts/photon_jtag.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/scripts/photon_jtag.ld + * boards/arm/stm32f2/photon/scripts/photon_jtag.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/CMakeLists.txt b/boards/arm/stm32f2/photon/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/photon/src/CMakeLists.txt rename to boards/arm/stm32f2/photon/src/CMakeLists.txt index e6e55c00a00..e9248b8107f 100644 --- a/boards/arm/stm32/photon/src/CMakeLists.txt +++ b/boards/arm/stm32f2/photon/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/photon/src/CMakeLists.txt +# boards/arm/stm32f2/photon/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/photon/src/Make.defs b/boards/arm/stm32f2/photon/src/Make.defs similarity index 97% rename from boards/arm/stm32/photon/src/Make.defs rename to boards/arm/stm32f2/photon/src/Make.defs index 6edf5dce2d9..36c65e38e42 100644 --- a/boards/arm/stm32/photon/src/Make.defs +++ b/boards/arm/stm32f2/photon/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/photon/src/Make.defs +# boards/arm/stm32f2/photon/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/photon/src/dfu_signature.c b/boards/arm/stm32f2/photon/src/dfu_signature.c similarity index 98% rename from boards/arm/stm32/photon/src/dfu_signature.c rename to boards/arm/stm32f2/photon/src/dfu_signature.c index 0ac237a3852..3738ed93a42 100644 --- a/boards/arm/stm32/photon/src/dfu_signature.c +++ b/boards/arm/stm32f2/photon/src/dfu_signature.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/dfu_signature.c + * boards/arm/stm32f2/photon/src/dfu_signature.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/photon.h b/boards/arm/stm32f2/photon/src/photon.h similarity index 98% rename from boards/arm/stm32/photon/src/photon.h rename to boards/arm/stm32f2/photon/src/photon.h index 299fe0294ec..30f904847d1 100644 --- a/boards/arm/stm32/photon/src/photon.h +++ b/boards/arm/stm32f2/photon/src/photon.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/photon.h + * boards/arm/stm32f2/photon/src/photon.h * * SPDX-License-Identifier: Apache-2.0 * @@ -29,7 +29,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/photon/src/stm32_autoleds.c b/boards/arm/stm32f2/photon/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_autoleds.c rename to boards/arm/stm32f2/photon/src/stm32_autoleds.c index f78cd9a89a0..fe1a324f455 100644 --- a/boards/arm/stm32/photon/src/stm32_autoleds.c +++ b/boards/arm/stm32f2/photon/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_autoleds.c + * boards/arm/stm32f2/photon/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_boot.c b/boards/arm/stm32f2/photon/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_boot.c rename to boards/arm/stm32f2/photon/src/stm32_boot.c index 631df3142d6..8acf417ab0f 100644 --- a/boards/arm/stm32/photon/src/stm32_boot.c +++ b/boards/arm/stm32f2/photon/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_boot.c + * boards/arm/stm32f2/photon/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_bringup.c b/boards/arm/stm32f2/photon/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_bringup.c rename to boards/arm/stm32f2/photon/src/stm32_bringup.c index 5096dad8d0b..7bcb3c0afa0 100644 --- a/boards/arm/stm32/photon/src/stm32_bringup.c +++ b/boards/arm/stm32f2/photon/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_bringup.c + * boards/arm/stm32f2/photon/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_buttons.c b/boards/arm/stm32f2/photon/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_buttons.c rename to boards/arm/stm32f2/photon/src/stm32_buttons.c index 9288ec789f6..c4f6bd29b3a 100644 --- a/boards/arm/stm32/photon/src/stm32_buttons.c +++ b/boards/arm/stm32f2/photon/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_buttons.c + * boards/arm/stm32f2/photon/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_composite.c b/boards/arm/stm32f2/photon/src/stm32_composite.c similarity index 99% rename from boards/arm/stm32/photon/src/stm32_composite.c rename to boards/arm/stm32f2/photon/src/stm32_composite.c index f0eec287904..49f82ed1d23 100644 --- a/boards/arm/stm32/photon/src/stm32_composite.c +++ b/boards/arm/stm32f2/photon/src/stm32_composite.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_composite.c + * boards/arm/stm32f2/photon/src/stm32_composite.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_rgbled.c b/boards/arm/stm32f2/photon/src/stm32_rgbled.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_rgbled.c rename to boards/arm/stm32f2/photon/src/stm32_rgbled.c index c43f21b604b..3b56149af24 100644 --- a/boards/arm/stm32/photon/src/stm32_rgbled.c +++ b/boards/arm/stm32f2/photon/src/stm32_rgbled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_rgbled.c + * boards/arm/stm32f2/photon/src/stm32_rgbled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_spi.c b/boards/arm/stm32f2/photon/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/photon/src/stm32_spi.c rename to boards/arm/stm32f2/photon/src/stm32_spi.c index 618331bb43d..775b45ed32d 100644 --- a/boards/arm/stm32/photon/src/stm32_spi.c +++ b/boards/arm/stm32f2/photon/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_spi.c + * boards/arm/stm32f2/photon/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_usb.c b/boards/arm/stm32f2/photon/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_usb.c rename to boards/arm/stm32f2/photon/src/stm32_usb.c index d8f58624854..3bb76c85e31 100644 --- a/boards/arm/stm32/photon/src/stm32_usb.c +++ b/boards/arm/stm32f2/photon/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_usb.c + * boards/arm/stm32f2/photon/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_userleds.c b/boards/arm/stm32f2/photon/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_userleds.c rename to boards/arm/stm32f2/photon/src/stm32_userleds.c index 1d78b7ecd2a..30b2933307b 100644 --- a/boards/arm/stm32/photon/src/stm32_userleds.c +++ b/boards/arm/stm32f2/photon/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_userleds.c + * boards/arm/stm32f2/photon/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_wdt.c b/boards/arm/stm32f2/photon/src/stm32_wdt.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_wdt.c rename to boards/arm/stm32f2/photon/src/stm32_wdt.c index 738312db16e..09db859e1df 100644 --- a/boards/arm/stm32/photon/src/stm32_wdt.c +++ b/boards/arm/stm32f2/photon/src/stm32_wdt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wdt.c + * boards/arm/stm32f2/photon/src/stm32_wdt.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_wlan.c b/boards/arm/stm32f2/photon/src/stm32_wlan.c similarity index 98% rename from boards/arm/stm32/photon/src/stm32_wlan.c rename to boards/arm/stm32f2/photon/src/stm32_wlan.c index 2c0edcbca37..88bfa4561e9 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan.c + * boards/arm/stm32f2/photon/src/stm32_wlan.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c similarity index 99% rename from boards/arm/stm32/photon/src/stm32_wlan_firmware.c rename to boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c index 2374ae038c9..ace87343d4e 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/photon/src/stm32_wlan_firmware.c + * boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt new file mode 100644 index 00000000000..9107f3bbd27 --- /dev/null +++ b/boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f2/stm3220g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/Kconfig b/boards/arm/stm32f2/stm3220g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3220g-eval/Kconfig rename to boards/arm/stm32f2/stm3220g-eval/Kconfig diff --git a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig similarity index 98% rename from boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig index 99c464911f8..4e83650fdf4 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/dhcpd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig similarity index 98% rename from boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig index 1d654ac87eb..431b3151a62 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nettest/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig index fc5b0a1d607..26a63e10c07 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig similarity index 98% rename from boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig index 5c70dff6840..5dff42667f2 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nsh2/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig similarity index 99% rename from boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig index 560ebc95176..8a2c4444608 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/nxwm/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig similarity index 98% rename from boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig rename to boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig index 6ff3b7d474f..5d80ddff92c 100644 --- a/boards/arm/stm32/stm3220g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32f2/stm3220g-eval/configs/telnetd/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3220g-eval" CONFIG_ARCH_BOARD_STM3220G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f2" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F207IG=y CONFIG_ARCH_CHIP_STM32F2=y diff --git a/boards/arm/stm32/stm3220g-eval/include/board.h b/boards/arm/stm32f2/stm3220g-eval/include/board.h similarity index 99% rename from boards/arm/stm32/stm3220g-eval/include/board.h rename to boards/arm/stm32f2/stm3220g-eval/include/board.h index 86ebef53bb0..fb3043eada2 100644 --- a/boards/arm/stm32/stm3220g-eval/include/board.h +++ b/boards/arm/stm32f2/stm3220g-eval/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/include/board.h + * boards/arm/stm32f2/stm3220g-eval/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f103rb/scripts/Make.defs rename to boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs index a9ad56f5283..3b902ef1830 100644 --- a/boards/arm/stm32/nucleo-f103rb/scripts/Make.defs +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f103rb/scripts/Make.defs +# boards/arm/stm32f2/stm3220g-eval/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3220g-eval/scripts/ld.script b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm3220g-eval/scripts/ld.script rename to boards/arm/stm32f2/stm3220g-eval/scripts/ld.script index 0133f9415af..bb2f5e12f4c 100644 --- a/boards/arm/stm32/stm3220g-eval/scripts/ld.script +++ b/boards/arm/stm32f2/stm3220g-eval/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/scripts/ld.script + * boards/arm/stm32f2/stm3220g-eval/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt rename to boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt index 7f0321dd1b8..c198e622bed 100644 --- a/boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt +++ b/boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm3220g-eval/src/CMakeLists.txt +# boards/arm/stm32f2/stm3220g-eval/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3220g-eval/src/Make.defs b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm3220g-eval/src/Make.defs rename to boards/arm/stm32f2/stm3220g-eval/src/Make.defs index e77785ac6fa..3c938b32998 100644 --- a/boards/arm/stm32/stm3220g-eval/src/Make.defs +++ b/boards/arm/stm32f2/stm3220g-eval/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3220g-eval/src/Make.defs +# boards/arm/stm32f2/stm3220g-eval/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h rename to boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h index 7908e0a422c..775b69a377d 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm3220g-eval.h + * boards/arm/stm32f2/stm3220g-eval/src/stm3220g-eval.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_adc.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c index d3bfcd0a171..347835c5d36 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_adc.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_adc.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c index 2cd09b07a13..58d3ebc7653 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_autoleds.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_boot.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c index a3693105506..f73fd6ed35a 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_boot.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_boot.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c index 8c177aa3ed4..f054a70494d 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_buttons.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_can.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c index 0145c3b0a51..5a2826f4674 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_can.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_can.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c similarity index 97% rename from boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c index a6239db7ecf..3ef672f986d 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectlcd.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c similarity index 97% rename from boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c index 9c0696c9849..e1fe12d86a5 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_deselectsram.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_deselectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c index 1b61bc8e502..7a0344fcc7e 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_extmem.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c index 2828d7eb768..d8c10b46395 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c index 546c8335f2d..55325a9f41d 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_pwm.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c index 45603a50da5..99317669252 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c index 5c1553a1aa4..3a0016a1a49 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_selectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_spi.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c index 5d99e643455..c766ed8ca44 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_spi.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_spi.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c index 190e897501d..4b37d489a8e 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_stmpe811.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_stmpe811.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm3220g-eval/src/stm32_usb.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c index 3252daf95d9..18abe851b16 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_usb.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_usb.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c rename to boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c index 9a69e756ae0..c7c5a9f1c70 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c +++ b/boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3220g-eval/src/stm32_userleds.c + * boards/arm/stm32f2/stm3220g-eval/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/olimex-arm-usb-ocd.cfg diff --git a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh similarity index 96% rename from boards/arm/stm32/stm3220g-eval/tools/oocd.sh rename to boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh index 66a7cca63d0..9d01a7c8756 100755 --- a/boards/arm/stm32/stm3220g-eval/tools/oocd.sh +++ b/boards/arm/stm32f2/stm3220g-eval/tools/oocd.sh @@ -44,7 +44,7 @@ fi # Local search directory and configurations -OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32/stm3210e-eval/tools" +OPENOCD_SEARCHDIR="${TOPDIR}/boards/arm/stm32f2/stm3220g-eval/tools" OPENOCD_WSEARCHDIR="`cygpath -w ${OPENOCD_SEARCHDIR}`" OPENOCD_PATH="/cygdrive/c/Program Files (x86)/OpenOCD/0.4.0/bin" diff --git a/boards/arm/stm32/stm3220g-eval/tools/stm32.cfg b/boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/stm32.cfg rename to boards/arm/stm32f2/stm3220g-eval/tools/stm32.cfg diff --git a/boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt b/boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt similarity index 100% rename from boards/arm/stm32/stm3220g-eval/tools/usb-driver.txt rename to boards/arm/stm32f2/stm3220g-eval/tools/usb-driver.txt From b37e3e7c466aacb607b8c5c6863c3ddcef3bed36 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 157/268] !arch/stm32: move stm32f3 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f3 sources, headers and boards into arch/arm/src/stm32f3, arch/arm/include/stm32f3 and boards/arm/stm32f3. Signed-off-by: raiden00pl --- arch/arm/include/stm32f3/chip.h | 627 ++++++++++++++++++ arch/arm/include/{stm32 => stm32f3}/irq.h | 57 +- .../{stm32 => stm32f3}/stm32f30xxx_irq.h | 31 +- .../{stm32 => stm32f3}/stm32f33xxx_irq.h | 31 +- .../{stm32 => stm32f3}/stm32f37xxx_irq.h | 31 +- arch/arm/src/stm32f3/CMakeLists.txt | 28 + arch/arm/src/stm32f3/Kconfig | 626 +++++++++++++++++ arch/arm/src/stm32f3/Make.defs | 27 + arch/arm/src/stm32f3/chip.h | 59 ++ .../src/stm32f3/hardware/stm32_memorymap.h | 27 + arch/arm/src/stm32f3/hardware/stm32_pinmap.h | 27 + .../hardware/stm32f30xxx_gpio.h | 2 +- .../hardware/stm32f30xxx_memorymap.h | 2 +- .../hardware/stm32f30xxx_pinmap.h | 2 +- .../hardware/stm32f30xxx_rcc.h | 2 +- .../hardware/stm32f30xxx_syscfg.h | 2 +- .../hardware/stm32f33xxx_comp.h | 2 +- .../hardware/stm32f33xxx_hrtim.h | 2 +- .../hardware/stm32f33xxx_memorymap.h | 2 +- .../hardware/stm32f33xxx_opamp.h | 2 +- .../hardware/stm32f33xxx_pinmap.h | 2 +- .../hardware/stm32f33xxx_rcc.h | 2 +- .../hardware/stm32f33xxx_syscfg.h | 2 +- .../hardware/stm32f37xxx_memorymap.h | 2 +- .../hardware/stm32f37xxx_pinmap.h | 2 +- .../hardware/stm32f37xxx_rcc.h | 2 +- .../hardware/stm32f37xxx_sdadc.h | 2 +- .../hardware/stm32f37xxx_syscfg.h | 2 +- arch/arm/src/stm32f3/stm32.h | 69 ++ arch/arm/src/{stm32 => stm32f3}/stm32_rcc.c | 16 +- .../src/{stm32 => stm32f3}/stm32f30xxx_rcc.c | 2 +- .../src/{stm32 => stm32f3}/stm32f33xxx_rcc.c | 2 +- .../src/{stm32 => stm32f3}/stm32f37xxx_rcc.c | 2 +- boards/arm/stm32f3/common/CMakeLists.txt | 25 + boards/arm/stm32f3/common/Kconfig | 6 + boards/arm/stm32f3/common/Makefile | 38 ++ .../arm/stm32f3/nucleo-f302r8/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f302r8/Kconfig | 0 .../nucleo-f302r8/configs/can/defconfig | 2 +- .../nucleo-f302r8/configs/cansock/defconfig | 2 +- .../nucleo-f302r8/configs/highpri/defconfig | 2 +- .../configs/ihm07m1_b16/defconfig | 2 +- .../configs/ihm07m1_f32/defconfig | 2 +- .../nucleo-f302r8/configs/nsh/defconfig | 2 +- .../nucleo-f302r8/configs/qenco/defconfig | 2 +- .../nucleo-f302r8/include/board.h | 2 +- .../stm32f3/nucleo-f302r8/scripts/Make.defs | 41 ++ .../nucleo-f302r8/scripts/ld.script | 2 +- .../nucleo-f302r8/src/CMakeLists.txt | 2 +- .../nucleo-f302r8/src/Make.defs | 2 +- .../nucleo-f302r8/src/nucleo-f302r8.h | 2 +- .../nucleo-f302r8/src/stm32_adc.c | 2 +- .../nucleo-f302r8/src/stm32_autoleds.c | 2 +- .../nucleo-f302r8/src/stm32_boot.c | 2 +- .../nucleo-f302r8/src/stm32_bringup.c | 2 +- .../nucleo-f302r8/src/stm32_buttons.c | 2 +- .../nucleo-f302r8/src/stm32_can.c | 2 +- .../nucleo-f302r8/src/stm32_cansock.c | 2 +- .../nucleo-f302r8/src/stm32_foc_ihm07m1.c | 2 +- .../nucleo-f302r8/src/stm32_highpri.c | 2 +- .../nucleo-f302r8/src/stm32_pwm.c | 2 +- .../nucleo-f302r8/src/stm32_userleds.c | 2 +- .../arm/stm32f3/nucleo-f303re/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f303re/Kconfig | 0 .../nucleo-f303re/configs/adc/defconfig | 2 +- .../nucleo-f303re/configs/can/defconfig | 2 +- .../nucleo-f303re/configs/hello/defconfig | 2 +- .../nucleo-f303re/configs/nsh/defconfig | 2 +- .../nucleo-f303re/configs/nxlines/defconfig | 2 +- .../nucleo-f303re/configs/pwm/defconfig | 2 +- .../nucleo-f303re/configs/serialrx/defconfig | 2 +- .../nucleo-f303re/include/board.h | 2 +- .../stm32f3/nucleo-f303re/scripts/Make.defs | 41 ++ .../nucleo-f303re/scripts/ld.script | 2 +- .../nucleo-f303re/src/CMakeLists.txt | 2 +- .../nucleo-f303re/src/Make.defs | 2 +- .../nucleo-f303re/src/nucleo-f303re.h | 2 +- .../nucleo-f303re/src/stm32_adc.c | 2 +- .../nucleo-f303re/src/stm32_autoleds.c | 2 +- .../nucleo-f303re/src/stm32_boot.c | 2 +- .../nucleo-f303re/src/stm32_buttons.c | 2 +- .../nucleo-f303re/src/stm32_can.c | 2 +- .../nucleo-f303re/src/stm32_pwm.c | 2 +- .../nucleo-f303re/src/stm32_spi.c | 2 +- .../nucleo-f303re/src/stm32_ssd1351.c | 2 +- .../nucleo-f303re/src/stm32_timer.c | 2 +- .../nucleo-f303re/src/stm32_uid.c | 2 +- .../nucleo-f303re/src/stm32_userleds.c | 2 +- .../arm/stm32f3/nucleo-f303ze/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f303ze/Kconfig | 0 .../nucleo-f303ze/configs/adc/defconfig | 2 +- .../nucleo-f303ze/configs/nsh/defconfig | 2 +- .../configs/nxlines_oled/defconfig | 2 +- .../nucleo-f303ze/include/board.h | 2 +- .../stm32f3/nucleo-f303ze/scripts/Make.defs | 41 ++ .../nucleo-f303ze/scripts/ld.script | 2 +- .../nucleo-f303ze/src/CMakeLists.txt | 2 +- .../nucleo-f303ze/src/Make.defs | 2 +- .../nucleo-f303ze/src/nucleo-f303ze.h | 2 +- .../nucleo-f303ze/src/stm32_adc.c | 2 +- .../nucleo-f303ze/src/stm32_autoleds.c | 2 +- .../nucleo-f303ze/src/stm32_boot.c | 2 +- .../nucleo-f303ze/src/stm32_bringup.c | 2 +- .../nucleo-f303ze/src/stm32_buttons.c | 2 +- .../nucleo-f303ze/src/stm32_lcd.c | 2 +- .../nucleo-f303ze/src/stm32_userleds.c | 2 +- .../arm/stm32f3/nucleo-f334r8/CMakeLists.txt | 23 + .../{stm32 => stm32f3}/nucleo-f334r8/Kconfig | 0 .../nucleo-f334r8/configs/adc/defconfig | 2 +- .../nucleo-f334r8/configs/highpri/defconfig | 2 +- .../nucleo-f334r8/configs/nsh/defconfig | 2 +- .../nucleo-f334r8/configs/spwm1/defconfig | 2 +- .../nucleo-f334r8/configs/spwm2/defconfig | 2 +- .../nucleo-f334r8/include/board.h | 2 +- .../stm32f3/nucleo-f334r8/scripts/Make.defs | 41 ++ .../nucleo-f334r8/scripts/ld.script | 2 +- .../nucleo-f334r8/src/CMakeLists.txt | 2 +- .../nucleo-f334r8/src/Make.defs | 2 +- .../nucleo-f334r8/src/nucleo-f334r8.h | 2 +- .../nucleo-f334r8/src/stm32_adc.c | 2 +- .../nucleo-f334r8/src/stm32_autoleds.c | 2 +- .../nucleo-f334r8/src/stm32_boot.c | 2 +- .../nucleo-f334r8/src/stm32_comp.c | 2 +- .../nucleo-f334r8/src/stm32_highpri.c | 2 +- .../nucleo-f334r8/src/stm32_hrtim.c | 2 +- .../nucleo-f334r8/src/stm32_opamp.c | 2 +- .../nucleo-f334r8/src/stm32_spwm.c | 2 +- .../stm32f3/stm32f334-disco/CMakeLists.txt | 23 + .../stm32f334-disco/Kconfig | 0 .../configs/buckboost/defconfig | 2 +- .../stm32f334-disco/configs/nsh/defconfig | 2 +- .../configs/powerled/defconfig | 2 +- .../stm32f334-disco/include/board.h | 2 +- .../stm32f3/stm32f334-disco/scripts/Make.defs | 41 ++ .../stm32f334-disco/scripts/ld.script | 2 +- .../stm32f334-disco/src/CMakeLists.txt | 2 +- .../stm32f334-disco/src/Make.defs | 2 +- .../stm32f334-disco/src/stm32_adc.c | 2 +- .../stm32f334-disco/src/stm32_autoleds.c | 2 +- .../stm32f334-disco/src/stm32_boot.c | 2 +- .../stm32f334-disco/src/stm32_comp.c | 2 +- .../stm32f334-disco/src/stm32_hrtim.c | 2 +- .../stm32f334-disco/src/stm32_opamp.c | 2 +- .../stm32f334-disco/src/stm32_powerled.c | 2 +- .../stm32f334-disco/src/stm32_smps.c | 2 +- .../stm32f334-disco/src/stm32f334-disco.h | 2 +- .../stm32f3/stm32f3discovery/CMakeLists.txt | 23 + .../stm32f3discovery/Kconfig | 0 .../stm32f3discovery/configs/nsh/defconfig | 2 +- .../stm32f3discovery/configs/usbnsh/defconfig | 2 +- .../stm32f3discovery/include/board.h | 2 +- .../stm32f3discovery/scripts/Make.defs | 41 ++ .../stm32f3discovery/scripts/ld.script | 2 +- .../stm32f3discovery/src/CMakeLists.txt | 2 +- .../stm32f3discovery/src/Make.defs | 2 +- .../stm32f3discovery/src/stm32_autoleds.c | 2 +- .../stm32f3discovery/src/stm32_boot.c | 2 +- .../stm32f3discovery/src/stm32_bringup.c | 2 +- .../stm32f3discovery/src/stm32_buttons.c | 2 +- .../stm32f3discovery/src/stm32_pwm.c | 2 +- .../stm32f3discovery/src/stm32_spi.c | 2 +- .../stm32f3discovery/src/stm32_usb.c | 2 +- .../stm32f3discovery/src/stm32_userleds.c | 2 +- .../stm32f3discovery/src/stm32f3discovery.h | 4 +- 164 files changed, 2093 insertions(+), 278 deletions(-) create mode 100644 arch/arm/include/stm32f3/chip.h rename arch/arm/include/{stm32 => stm32f3}/irq.h (68%) rename arch/arm/include/{stm32 => stm32f3}/stm32f30xxx_irq.h (93%) rename arch/arm/include/{stm32 => stm32f3}/stm32f33xxx_irq.h (92%) rename arch/arm/include/{stm32 => stm32f3}/stm32f37xxx_irq.h (92%) create mode 100644 arch/arm/src/stm32f3/CMakeLists.txt create mode 100644 arch/arm/src/stm32f3/Kconfig create mode 100644 arch/arm/src/stm32f3/Make.defs create mode 100644 arch/arm/src/stm32f3/chip.h create mode 100644 arch/arm/src/stm32f3/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f3/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f30xxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f30xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f30xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f30xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f30xxx_syscfg.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_comp.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_hrtim.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_opamp.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f33xxx_syscfg.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f37xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f37xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f37xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f37xxx_sdadc.h (99%) rename arch/arm/src/{stm32 => stm32f3}/hardware/stm32f37xxx_syscfg.h (99%) create mode 100644 arch/arm/src/stm32f3/stm32.h rename arch/arm/src/{stm32 => stm32f3}/stm32_rcc.c (93%) rename arch/arm/src/{stm32 => stm32f3}/stm32f30xxx_rcc.c (99%) rename arch/arm/src/{stm32 => stm32f3}/stm32f33xxx_rcc.c (99%) rename arch/arm/src/{stm32 => stm32f3}/stm32f37xxx_rcc.c (99%) create mode 100644 boards/arm/stm32f3/common/CMakeLists.txt create mode 100644 boards/arm/stm32f3/common/Kconfig create mode 100644 boards/arm/stm32f3/common/Makefile create mode 100644 boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/can/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/cansock/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/highpri/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/ihm07m1_b16/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/ihm07m1_f32/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/configs/qenco/defconfig (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/include/board.h (99%) create mode 100644 boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/nucleo-f302r8.h (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_adc.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_can.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_cansock.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_foc_ihm07m1.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_highpri.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f302r8/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/adc/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/can/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/hello/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/nxlines/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/pwm/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/configs/serialrx/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/include/board.h (99%) create mode 100644 boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/nucleo-f303re.h (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_can.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_ssd1351.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_timer.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_uid.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303re/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/configs/adc/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/configs/nxlines_oled/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/include/board.h (99%) create mode 100644 boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/nucleo-f303ze.h (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_bringup.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_lcd.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f303ze/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/configs/adc/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/configs/highpri/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/configs/spwm1/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/configs/spwm2/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/include/board.h (99%) create mode 100644 boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/nucleo-f334r8.h (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_comp.c (98%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_highpri.c (99%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_hrtim.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_opamp.c (97%) rename boards/arm/{stm32 => stm32f3}/nucleo-f334r8/src/stm32_spwm.c (99%) create mode 100644 boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/configs/buckboost/defconfig (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/configs/powerled/defconfig (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/include/board.h (99%) create mode 100644 boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_comp.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_hrtim.c (97%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_opamp.c (97%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_powerled.c (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32_smps.c (99%) rename boards/arm/{stm32 => stm32f3}/stm32f334-disco/src/stm32f334-disco.h (99%) create mode 100644 boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/Kconfig (100%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/configs/usbnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/include/board.h (99%) create mode 100644 boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_usb.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32_userleds.c (98%) rename boards/arm/{stm32 => stm32f3}/stm32f3discovery/src/stm32f3discovery.h (98%) diff --git a/arch/arm/include/stm32f3/chip.h b/arch/arm/include/stm32f3/chip.h new file mode 100644 index 00000000000..f97f301c8f0 --- /dev/null +++ b/arch/arm/include/stm32f3/chip.h @@ -0,0 +1,627 @@ +/**************************************************************************** + * arch/arm/include/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F3_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 24 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 2 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ + +# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S */ +# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 52 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (2) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ +# define STM32_NGTIM 6 /* (5) 16-bit general timers + * (1) 32-bit general timers */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 4 /* (4) SPI1-4 */ +# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* (3) I2C1-3 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 115 /* GPIOA-F */ +# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ +# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 2 /* (2) USART1-2 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 25 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 37 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ +# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ +# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 + * (1) 32-bit general timers with DMA: TIM2 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* All timers have DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ +# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ +# define STM32_NSPI 1 /* (1) SPI1 */ +# define STM32_NI2S 0 /* (0) No I2S1 */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 1 /* (1) I2C1 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* (0) No USB */ +# define STM32_NGPIO 51 /* GPIOA-F */ +# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ +# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ +# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ +# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 + * (2) 32-bit general timers with DMA: TIM2 and TIM5 + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ +# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ +# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ +# define STM32_NSPI 3 /* (3) SPI1-3 */ +# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ +# define STM32_NUSART 3 /* (3) USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* (2) I2C1-2 */ +# define STM32_NCAN 1 /* (1) CAN1 */ +# define STM32_NSDIO 0 /* (0) No SDIO */ +# define STM32_NLCD 0 /* (0) No LCD */ +# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ +# define STM32_NGPIO 87 /* GPIOA-F */ +# define STM32_NADC 1 /* (1) 12-bit ADC1 */ +# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ +# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ +# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ +# define STM32_NCRC 1 /* (1) CRC calculation unit */ +# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ +# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ +# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ + +/* STM23 F4 Family **********************************************************/ + +/* STM32F01xB/C Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 + * STM32F401RB LQFP64 128Kb Yes 16 + * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 + * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 + * STM32F401RC LQFP64 256Kb Yes 16 + * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 + */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#if defined(CONFIG_STM32_STM32F30XX) +# define STM32_HAVE_IP_SPI_V3 + +#elif defined(CONFIG_STM32_STM32F33XX) +# define STM32_HAVE_IP_SPI_V1 + +#elif defined(CONFIG_STM32_STM32F37XX) +# define STM32_HAVE_IP_SPI_V3 + +#else +# error "Did not resolve peripheral IP versions!" +#endif + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F3_CHIP_H */ diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32f3/irq.h similarity index 68% rename from arch/arm/include/stm32/irq.h rename to arch/arm/include/stm32f3/irq.h index 6e55b57a3fc..91c056320ef 100644 --- a/arch/arm/include/stm32/irq.h +++ b/arch/arm/include/stm32f3/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/irq.h + * arch/arm/include/stm32f3/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,8 +24,8 @@ * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F3_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F3_IRQ_H /**************************************************************************** * Included Files @@ -33,7 +33,7 @@ #include #include -#include +#include /**************************************************************************** * Pre-processor Prototypes @@ -71,51 +71,14 @@ * Included Files ****************************************************************************/ -#if defined(CONFIG_STM32_STM32L15XX) -# include -#elif defined(CONFIG_STM32_STM32F10XX) -# include -#elif defined(CONFIG_STM32_STM32F20XX) -# include -#elif defined(CONFIG_STM32_STM32F30XX) -# include +#if defined(CONFIG_STM32_STM32F30XX) +# include #elif defined(CONFIG_STM32_STM32F33XX) -# include +# include #elif defined(CONFIG_STM32_STM32F37XX) -# include -#elif defined(CONFIG_STM32_STM32F4XXX) -# include -#elif defined(CONFIG_STM32_STM32G4XXX) -# include +# include #else -# error "Unsupported STM32 chip" +# error "Unsupported STM32F3 chip" #endif -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F3_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f30xxx_irq.h b/arch/arm/include/stm32f3/stm32f30xxx_irq.h similarity index 93% rename from arch/arm/include/stm32/stm32f30xxx_irq.h rename to arch/arm/include/stm32f3/stm32f30xxx_irq.h index 32c5dc0d557..b5a5612cfa2 100644 --- a/arch/arm/include/stm32/stm32f30xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f30xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f30xxx_irq.h + * arch/arm/include/stm32f3/stm32f30xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -153,31 +153,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f33xxx_irq.h b/arch/arm/include/stm32f3/stm32f33xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f33xxx_irq.h rename to arch/arm/include/stm32f3/stm32f33xxx_irq.h index bb6e9f84cc9..4dde150c30d 100644 --- a/arch/arm/include/stm32/stm32f33xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f33xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f33xxx_irq.h + * arch/arm/include/stm32f3/stm32f33xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -143,31 +143,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32f3/stm32f37xxx_irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f37xxx_irq.h rename to arch/arm/include/stm32f3/stm32f37xxx_irq.h index cf052a8493a..445fa0c657b 100644 --- a/arch/arm/include/stm32/stm32f37xxx_irq.h +++ b/arch/arm/include/stm32f3/stm32f37xxx_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f37xxx_irq.h + * arch/arm/include/stm32f3/stm32f37xxx_irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -43,7 +43,7 @@ * memory in the IRQ to handle mapping tables. * * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h + * found in nuttx/arch/arm/include/stm32f3/irq.h * * External interrupts (vectors >= 16) */ @@ -138,31 +138,4 @@ #define STM32_IRQ_NEXTINTS (82) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - #endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */ diff --git a/arch/arm/src/stm32f3/CMakeLists.txt b/arch/arm/src/stm32f3/CMakeLists.txt new file mode 100644 index 00000000000..36707fa80f1 --- /dev/null +++ b/arch/arm/src/stm32f3/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f3/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f3/Kconfig b/arch/arm/src/stm32f3/Kconfig new file mode 100644 index 00000000000..428efe6c9c5 --- /dev/null +++ b/arch/arm/src/stm32f3/Kconfig @@ -0,0 +1,626 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F3 configuration" + +if ARCH_CHIP_STM32F3 + +choice + prompt "STM32F3 Chip Selection" + depends on ARCH_CHIP_STM32F3 + +config ARCH_CHIP_STM32F302K6 + bool "STM32F302K6" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302K8 + bool "STM32F302K8" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_I2C3 + +config ARCH_CHIP_STM32F302C6 + bool "STM32F302C6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302C8 + bool "STM32F302C8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R6 + bool "STM32F302R6" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302R8 + bool "STM32F302R8" + select STM32_STM32F30XX + select STM32_STM32F302 + +config ARCH_CHIP_STM32F302CB + bool "STM32F302CB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302CC + bool "STM32F302CC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F302RB + bool "STM32F302RB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302RC + bool "STM32F302RC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VB + bool "STM32F302VB" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F302VC + bool "STM32F302VC" + select STM32_STM32F30XX + select STM32_STM32F302 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config ARCH_CHIP_STM32F303K6 + bool "STM32F303K6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303K8 + bool "STM32F303K8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + +config ARCH_CHIP_STM32F303C6 + bool "STM32F303C6" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303C8 + bool "STM32F303C8" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_DAC2 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303CB + bool "STM32F303CB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303CC + bool "STM32F303CC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RB + bool "STM32F303RB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RC + bool "STM32F303RC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RD + bool "STM32F303RD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303RE + bool "STM32F303RE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VB + bool "STM32F303VB" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VC + bool "STM32F303VC" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USBDEV + +config ARCH_CHIP_STM32F303VD + bool "STM32F303VD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303VE + bool "STM32F303VE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZD + bool "STM32F303ZD" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F303ZE + bool "STM32F303ZE" + select STM32_STM32F30XX + select STM32_STM32F303 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_USART3 + +config ARCH_CHIP_STM32F334K4 + bool "STM32F334K4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K6 + bool "STM32F334K6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334K8 + bool "STM32F334K8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C4 + bool "STM32F334C4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C6 + bool "STM32F334C6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334C8 + bool "STM32F334C8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R4 + bool "STM32F334R4" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R6 + bool "STM32F334R6" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F334R8 + bool "STM32F334R8" + select STM32_STM32F33XX + +config ARCH_CHIP_STM32F372C8 + bool "STM32F372C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372R8 + bool "STM32F372R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372V8 + bool "STM32F372V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CB + bool "STM32F372CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RB + bool "STM32F372RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VB + bool "STM32F372VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372CC + bool "STM32F372CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372RC + bool "STM32F372RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F372VC + bool "STM32F372VC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373C8 + bool "STM32F373C8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373R8 + bool "STM32F373R8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373V8 + bool "STM32F373V8" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CB + bool "STM32F373CB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RB + bool "STM32F373RB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VB + bool "STM32F373VB" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373CC + bool "STM32F373CC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373RC + bool "STM32F373RC" + select STM32_STM32F37XX + +config ARCH_CHIP_STM32F373VC + bool "STM32F373VC" + select STM32_STM32F37XX + +endchoice + +endif + +config STM32_STM32F30XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F302 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM4 + select STM32_HAVE_USBDEV + +config STM32_STM32F303 + bool + default n + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM7 + +config STM32_STM32F33XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP6 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_CCM + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART2 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_HAVE_IP_COMP_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V2 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F37XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USBDEV + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TSC + select STM32_HAVE_SDADC1 + select STM32_HAVE_SDADC2 + select STM32_HAVE_SDADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_USART3 + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_ADC_M3M4_V1_BASIC + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F1F3 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SDADC_M3M4_V1 + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V3 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 diff --git a/arch/arm/src/stm32f3/Make.defs b/arch/arm/src/stm32f3/Make.defs new file mode 100644 index 00000000000..e847b60c007 --- /dev/null +++ b/arch/arm/src/stm32f3/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f3/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f3/chip.h b/arch/arm/src/stm32f3/chip.h new file mode 100644 index 00000000000..c3961139c12 --- /dev/null +++ b/arch/arm/src/stm32f3/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_CHIP_H +#define __ARCH_ARM_SRC_STM32F3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F3_CHIP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..475cd8800a3 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_memorymap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_memorymap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_memorymap.h" +#else +# error "Unsupported STM32F3 memory map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f3/hardware/stm32_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..35a22b56009 --- /dev/null +++ b/arch/arm/src/stm32f3/hardware/stm32_pinmap.h @@ -0,0 +1,27 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F30XX) +# include "hardware/stm32f30xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F33XX) +# include "hardware/stm32f33xxx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F37XX) +# include "hardware/stm32f37xxx_pinmap.h" +#else +# error "Unsupported STM32F3 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F3_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h index 47087489a38..247900fd222 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_gpio.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h index 23667f3b7c9..9471911d8c4 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h index d92b45de89a..02c86632c64 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h index 9d86d13a704..10d8c30c617 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h index 74900826244..e9fa174e4e7 100644 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f30xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_comp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h index d12e43317d5..0cc9a568c7b 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_comp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_comp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h index 7c6ff331f9a..94480b13875 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_hrtim.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h index eb59aba7e21..ce0e3889d20 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h index 3235866bcee..a2a1a269b96 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_opamp.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h index 629efe26b24..d26376e3af5 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h index 1e26281fb43..05348c760ec 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h index 5c3764b2d4d..a3270a48b35 100644 --- a/arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f33xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f33xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h index fd05c2477b9..26baaf49cd4 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_memorymap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h index f830d6868dc..f26a6c33f29 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_pinmap.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h index a0f658aa6d7..ef555856d7c 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_rcc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h index f7514129502..908ccda789f 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2016 Studelec SA. All rights reserved. diff --git a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h rename to arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h index 6849a95cbb6..d6a72647148 100644 --- a/arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h +++ b/arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f37xxx_syscfg.h + * arch/arm/src/stm32f3/hardware/stm32f37xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f3/stm32.h b/arch/arm/src/stm32f3/stm32.h new file mode 100644 index 00000000000..f7eb0f45c81 --- /dev/null +++ b/arch/arm/src/stm32f3/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f3/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.c b/arch/arm/src/stm32f3/stm32_rcc.c similarity index 93% rename from arch/arm/src/stm32/stm32_rcc.c rename to arch/arm/src/stm32f3/stm32_rcc.c index 5d1c3715b6a..32d4bbca0f3 100644 --- a/arch/arm/src/stm32/stm32_rcc.c +++ b/arch/arm/src/stm32f3/stm32_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.c + * arch/arm/src/stm32f3/stm32_rcc.c * * SPDX-License-Identifier: Apache-2.0 * @@ -62,24 +62,14 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32_STM32L15XX) -# include "stm32l15xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "stm32f10xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "stm32f20xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F30XX) +#if defined(CONFIG_STM32_STM32F30XX) # include "stm32f30xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F33XX) # include "stm32f33xxx_rcc.c" #elif defined(CONFIG_STM32_STM32F37XX) # include "stm32f37xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "stm32f40xxx_rcc.c" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "stm32g4xxxx_rcc.c" #else -# error "Unsupported STM32 chip" +# error "Unsupported STM32F3 chip" #endif /**************************************************************************** diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f30xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f30xxx_rcc.c index 8c0f606c765..79eeff67e83 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f30xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f30xxx_rcc.c + * arch/arm/src/stm32f3/stm32f30xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f33xxx_rcc.c b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f33xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f33xxx_rcc.c index bf3edc07275..d55f756b53b 100644 --- a/arch/arm/src/stm32/stm32f33xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f33xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f33xxx_rcc.c + * arch/arm/src/stm32f3/stm32f33xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f37xxx_rcc.c b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f37xxx_rcc.c rename to arch/arm/src/stm32f3/stm32f37xxx_rcc.c index 6c8a157a48e..c640835f696 100644 --- a/arch/arm/src/stm32/stm32f37xxx_rcc.c +++ b/arch/arm/src/stm32f3/stm32f37xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f37xxx_rcc.c + * arch/arm/src/stm32f3/stm32f37xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/common/CMakeLists.txt b/boards/arm/stm32f3/common/CMakeLists.txt new file mode 100644 index 00000000000..793d06cc009 --- /dev/null +++ b/boards/arm/stm32f3/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32f3/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32f3/common/Kconfig b/boards/arm/stm32f3/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32f3/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f3/common/Makefile b/boards/arm/stm32f3/common/Makefile new file mode 100644 index 00000000000..c4aa92e0a7f --- /dev/null +++ b/boards/arm/stm32f3/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32f3/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt new file mode 100644 index 00000000000..d777a964b18 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f302r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/Kconfig b/boards/arm/stm32f3/nucleo-f302r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f302r8/Kconfig rename to boards/arm/stm32f3/nucleo-f302r8/Kconfig diff --git a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/can/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig index d9e63f0503d..5e2a50cea1a 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/can/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/can/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig index a7d8a70986e..de7101c186d 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/cansock/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/cansock/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig index 591de57c991..f415d6e0fc5 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/highpri/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/highpri/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig index 3c84735698b..b0a78520cab 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_b16/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_b16/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig index e51931b5d9e..4f71addaafc 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/ihm07m1_f32/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/ihm07m1_f32/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig index 0e3692e647d..7363a11f42d 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/nsh/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig rename to boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig index a63d93c717a..f8824d58450 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ b/boards/arm/stm32f3/nucleo-f302r8/configs/qenco/defconfig @@ -62,7 +62,7 @@ CONFIG_ARCH_BOARD="nucleo-f302r8" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F302R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F302R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f302r8/include/board.h b/boards/arm/stm32f3/nucleo-f302r8/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/include/board.h rename to boards/arm/stm32f3/nucleo-f302r8/include/board.h index 21d24f4b50e..14529925ce3 100644 --- a/boards/arm/stm32/nucleo-f302r8/include/board.h +++ b/boards/arm/stm32f3/nucleo-f302r8/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/include/board.h + * boards/arm/stm32f3/nucleo-f302r8/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs new file mode 100644 index 00000000000..32cfbf27178 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f302r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/scripts/ld.script rename to boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script index cde87e144cb..a5bad8b6dac 100644 --- a/boards/arm/stm32/nucleo-f302r8/scripts/ld.script +++ b/boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/scripts/ld.script + * boards/arm/stm32f3/nucleo-f302r8/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt rename to boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt index e5e905b763f..d2e1166c77e 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt +++ b/boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f302r8/src/CMakeLists.txt +# boards/arm/stm32f3/nucleo-f302r8/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f302r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/Make.defs rename to boards/arm/stm32f3/nucleo-f302r8/src/Make.defs index 7c9ce0e0b1f..4b4fc883e98 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/Make.defs +++ b/boards/arm/stm32f3/nucleo-f302r8/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f302r8/src/Make.defs +# boards/arm/stm32f3/nucleo-f302r8/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h rename to boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h index 6c3c83d04a0..f38dbe2ed28 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h +++ b/boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/nucleo-f302r8.h + * boards/arm/stm32f3/nucleo-f302r8/src/nucleo-f302r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c index f4ec3e6b317..b4aed937ec9 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_adc.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c index 0175408b561..16b52f1961f 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_autoleds.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c index 36c4aa9905c..58c14e31836 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_boot.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c index 4a878d66e05..ddf259cacf7 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_bringup.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c index 581c45bda8e..718b549d346 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_buttons.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_can.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c index 3fae10a1a6a..c75d14627c2 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_can.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_can.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c index 7ccf0ad686b..6a7ed672f30 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_cansock.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c index 3d061622c90..b06c6378f9d 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_foc_ihm07m1.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_foc_ihm07m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c similarity index 99% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c index a7775f2b0ec..2882d646db1 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_highpri.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_highpri.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c index 49997999a1c..3270dce669b 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_pwm.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c rename to boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c index 1895649936c..5b5c35cf20d 100644 --- a/boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c +++ b/boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f302r8/src/stm32_userleds.c + * boards/arm/stm32f3/nucleo-f302r8/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt new file mode 100644 index 00000000000..98d4d6771d7 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303re/Kconfig b/boards/arm/stm32f3/nucleo-f303re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303re/Kconfig rename to boards/arm/stm32f3/nucleo-f303re/Kconfig diff --git a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/adc/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig index 40f25f3adf6..800369214a2 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/adc/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/adc/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/can/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig index 7132acae45a..464b73deff7 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/can/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/can/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/hello/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig index ca034f8f9bd..e8470d5fdbd 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/hello/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/hello/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig index 2c491319b47..4b5ead9b89f 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nsh/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig index 75d56847146..6c5fbbe4e1c 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/nxlines/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/nxlines/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig index 2b12f647fd7..e6ef3644349 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/pwm/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/pwm/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig rename to boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig index 1f48a0590ec..cdfbb2e02b0 100644 --- a/boards/arm/stm32/nucleo-f303re/configs/serialrx/defconfig +++ b/boards/arm/stm32f3/nucleo-f303re/configs/serialrx/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303re" CONFIG_ARCH_BOARD_NUCLEO_F303RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303RE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303re/include/board.h b/boards/arm/stm32f3/nucleo-f303re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f303re/include/board.h rename to boards/arm/stm32f3/nucleo-f303re/include/board.h index d5cb48ca3b4..a27906b0a72 100644 --- a/boards/arm/stm32/nucleo-f303re/include/board.h +++ b/boards/arm/stm32f3/nucleo-f303re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/include/board.h + * boards/arm/stm32f3/nucleo-f303re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs new file mode 100644 index 00000000000..8d2299c83d6 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303re/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f303re/scripts/ld.script rename to boards/arm/stm32f3/nucleo-f303re/scripts/ld.script index 509bf141fad..49e73ee56d1 100644 --- a/boards/arm/stm32/nucleo-f303re/scripts/ld.script +++ b/boards/arm/stm32f3/nucleo-f303re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/scripts/ld.script + * boards/arm/stm32f3/nucleo-f303re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt rename to boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt index bcc8d69e66c..1388c1f7d1e 100644 --- a/boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt +++ b/boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f303re/src/CMakeLists.txt +# boards/arm/stm32f3/nucleo-f303re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f303re/src/Make.defs b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/Make.defs rename to boards/arm/stm32f3/nucleo-f303re/src/Make.defs index 08749d74cd0..d65a5d39ac5 100644 --- a/boards/arm/stm32/nucleo-f303re/src/Make.defs +++ b/boards/arm/stm32f3/nucleo-f303re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f303re/src/Make.defs +# boards/arm/stm32f3/nucleo-f303re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h similarity index 99% rename from boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h rename to boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h index bcd7bb84176..01ce746a805 100644 --- a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h +++ b/boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h + * boards/arm/stm32f3/nucleo-f303re/src/nucleo-f303re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-f303re/src/stm32_adc.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c index 7f9f78d1d8e..8031cccfaee 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_adc.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c index 55c7df56a71..b8bd4ec3c7f 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_autoleds.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f303re/src/stm32_boot.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c index 6231f8b5f59..8ff26cda3c5 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_boot.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_boot.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c index f93ac3a5f9b..0dbfc2add9f 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_buttons.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/stm32_can.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c index e7b25cf16ae..5aad2992848 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_can.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_can.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c index 5d4544d1e8c..c9910bee3d0 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_pwm.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-f303re/src/stm32_spi.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c index 559b5020f03..70e8e235c6e 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_spi.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c similarity index 98% rename from boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c index b0f3a56d028..35e09d621e5 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_ssd1351.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_ssd1351.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/stm32_timer.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c index 221f721b5af..61e2ff9d063 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_timer.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_timer.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_timer.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c similarity index 98% rename from boards/arm/stm32/nucleo-f303re/src/stm32_uid.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c index af1a488fa10..54e03ff99d1 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_uid.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_uid.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c rename to boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c index 121230d908e..fdcf1734640 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c +++ b/boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303re/src/stm32_userleds.c + * boards/arm/stm32f3/nucleo-f303re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt new file mode 100644 index 00000000000..236a1e371d1 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f303ze/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/Kconfig b/boards/arm/stm32f3/nucleo-f303ze/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f303ze/Kconfig rename to boards/arm/stm32f3/nucleo-f303ze/Kconfig diff --git a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig rename to boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig index 2d1aa57d9d7..f9450ed1b9f 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/adc/defconfig +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/adc/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303ze" CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig rename to boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig index 876b7df5a5e..c6f9fe743d0 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nsh/defconfig +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f303ze" CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig rename to boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig index 8e5491d82fe..028b18ca152 100644 --- a/boards/arm/stm32/nucleo-f303ze/configs/nxlines_oled/defconfig +++ b/boards/arm/stm32f3/nucleo-f303ze/configs/nxlines_oled/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="nucleo-f303ze" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F303ZE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303ZE=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f303ze/include/board.h b/boards/arm/stm32f3/nucleo-f303ze/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f303ze/include/board.h rename to boards/arm/stm32f3/nucleo-f303ze/include/board.h index b604725820c..2f7b5950dd0 100644 --- a/boards/arm/stm32/nucleo-f303ze/include/board.h +++ b/boards/arm/stm32f3/nucleo-f303ze/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/include/board.h + * boards/arm/stm32f3/nucleo-f303ze/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs new file mode 100644 index 00000000000..1a1821fb246 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f303ze/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/scripts/ld.script rename to boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script index c43ec67e0d9..055c0bbe01f 100644 --- a/boards/arm/stm32/nucleo-f303ze/scripts/ld.script +++ b/boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/scripts/ld.script + * boards/arm/stm32f3/nucleo-f303ze/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt rename to boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt index 5c6e0c74cb3..1ad333906e1 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt +++ b/boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f303ze/src/CMakeLists.txt +# boards/arm/stm32f3/nucleo-f303ze/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f303ze/src/Make.defs b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-f303ze/src/Make.defs rename to boards/arm/stm32f3/nucleo-f303ze/src/Make.defs index 099d67193b3..57baf0dc88a 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/Make.defs +++ b/boards/arm/stm32f3/nucleo-f303ze/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f303ze/src/Make.defs +# boards/arm/stm32f3/nucleo-f303ze/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h rename to boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h index 7f302796b5f..35d4d81fa9a 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h +++ b/boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/nucleo-f303ze.h + * boards/arm/stm32f3/nucleo-f303ze/src/nucleo-f303ze.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c index a5f559fb432..e137704a98a 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_adc.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c index b990cdd6219..1861cae6b24 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_autoleds.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c index f2c54d36d4e..8984995d203 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_boot.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c index 697969eec66..3daad9db6c2 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_bringup.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c index 9e82309922d..ff143d50418 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_buttons.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c index cb6b3ffe895..2499bfdbb64 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_lcd.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c rename to boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c index f2f7522ee69..770c74720d1 100644 --- a/boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c +++ b/boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f303ze/src/stm32_userleds.c + * boards/arm/stm32f3/nucleo-f303ze/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt new file mode 100644 index 00000000000..6822d936f95 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/nucleo-f334r8/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/Kconfig b/boards/arm/stm32f3/nucleo-f334r8/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f334r8/Kconfig rename to boards/arm/stm32f3/nucleo-f334r8/Kconfig diff --git a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig rename to boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig index 8408fa611bf..c5b882ea444 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/adc/defconfig +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/adc/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig rename to boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig index fd85cdf0d5d..1c1da0ff5ee 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/highpri/defconfig +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/highpri/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig rename to boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig index 38e98f8d2c5..7a8a8baf3f1 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/nsh/defconfig +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig rename to boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig index eabb1afa344..351e8d90ad4 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm1/defconfig +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm1/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig rename to boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig index abe476df3aa..2427abbae0b 100644 --- a/boards/arm/stm32/nucleo-f334r8/configs/spwm2/defconfig +++ b/boards/arm/stm32f3/nucleo-f334r8/configs/spwm2/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f334r8" CONFIG_ARCH_BOARD_NUCLEO_F334R8=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334R8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/nucleo-f334r8/include/board.h b/boards/arm/stm32f3/nucleo-f334r8/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/include/board.h rename to boards/arm/stm32f3/nucleo-f334r8/include/board.h index e437be709a1..52d5fbd8889 100644 --- a/boards/arm/stm32/nucleo-f334r8/include/board.h +++ b/boards/arm/stm32f3/nucleo-f334r8/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/include/board.h + * boards/arm/stm32f3/nucleo-f334r8/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs new file mode 100644 index 00000000000..26228f81667 --- /dev/null +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/nucleo-f334r8/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/scripts/ld.script rename to boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script index 5f4e9d8ae71..83850802f01 100644 --- a/boards/arm/stm32/nucleo-f334r8/scripts/ld.script +++ b/boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/scripts/ld.script + * boards/arm/stm32f3/nucleo-f334r8/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt rename to boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt index 30f5bccef47..e56987f9cba 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt +++ b/boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f334r8/src/CMakeLists.txt +# boards/arm/stm32f3/nucleo-f334r8/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f334r8/src/Make.defs b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f334r8/src/Make.defs rename to boards/arm/stm32f3/nucleo-f334r8/src/Make.defs index 97dbc7a0f51..a3a09d9253c 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/Make.defs +++ b/boards/arm/stm32f3/nucleo-f334r8/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f334r8/src/Make.defs +# boards/arm/stm32f3/nucleo-f334r8/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h rename to boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h index ddcab273b09..b2a0f7c72f4 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h +++ b/boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/nucleo-f334r8.h + * boards/arm/stm32f3/nucleo-f334r8/src/nucleo-f334r8.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c index a369fe2f4fa..d6530730994 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_adc.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c index e2088b7ea6f..a108db4e5e3 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_autoleds.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c index 6387f93c8a3..69051c8f1b3 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_boot.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c similarity index 98% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c index 1175e6b17ba..cc95203cb1e 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_comp.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_comp.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c index 7be598a7747..961fcdd3a3f 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_highpri.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_highpri.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c similarity index 97% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c index 6b493ee1cbd..6e333274414 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_hrtim.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_hrtim.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c similarity index 97% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c index cdc526cb427..33a3febc2ab 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_opamp.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_opamp.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c similarity index 99% rename from boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c rename to boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c index 1bb93258e20..3fd7576b012 100644 --- a/boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c +++ b/boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f334r8/src/stm32_spwm.c + * boards/arm/stm32f3/nucleo-f334r8/src/stm32_spwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt new file mode 100644 index 00000000000..25937ad493c --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f334-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/Kconfig b/boards/arm/stm32f3/stm32f334-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f334-disco/Kconfig rename to boards/arm/stm32f3/stm32f334-disco/Kconfig diff --git a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig similarity index 99% rename from boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig rename to boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig index 2f7c28b1b2a..2736b34ef80 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/buckboost/defconfig +++ b/boards/arm/stm32f3/stm32f334-disco/configs/buckboost/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig rename to boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig index e7c49036087..7bdc5a61d0f 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f3/stm32f334-disco/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig similarity index 99% rename from boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig rename to boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig index b08e14d40ba..a6bccf5b397 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ b/boards/arm/stm32f3/stm32f334-disco/configs/powerled/defconfig @@ -27,7 +27,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f334-disco" CONFIG_ARCH_BOARD_STM32F334_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F334C8=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/stm32f334-disco/include/board.h b/boards/arm/stm32f3/stm32f334-disco/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f334-disco/include/board.h rename to boards/arm/stm32f3/stm32f334-disco/include/board.h index b1b39e94d8f..b4c5ffeca08 100644 --- a/boards/arm/stm32/stm32f334-disco/include/board.h +++ b/boards/arm/stm32f3/stm32f334-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/include/board.h + * boards/arm/stm32f3/stm32f334-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs new file mode 100644 index 00000000000..808988ed8e2 --- /dev/null +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f334-disco/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f334-disco/scripts/ld.script b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f334-disco/scripts/ld.script rename to boards/arm/stm32f3/stm32f334-disco/scripts/ld.script index 4a28638fbc2..f5f4236470b 100644 --- a/boards/arm/stm32/stm32f334-disco/scripts/ld.script +++ b/boards/arm/stm32f3/stm32f334-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/scripts/ld.script + * boards/arm/stm32f3/stm32f334-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt rename to boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt index b3e02b012c8..0f8f031ecba 100644 --- a/boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f334-disco/src/CMakeLists.txt +# boards/arm/stm32f3/stm32f334-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f334-disco/src/Make.defs b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f334-disco/src/Make.defs rename to boards/arm/stm32f3/stm32f334-disco/src/Make.defs index df8d1b44b37..fc16406ada6 100644 --- a/boards/arm/stm32/stm32f334-disco/src/Make.defs +++ b/boards/arm/stm32f3/stm32f334-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f334-disco/src/Make.defs +# boards/arm/stm32f3/stm32f334-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_adc.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c index 9d40e86bd6c..82267bb3d83 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_adc.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_adc.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c index 3cc43c8ee0a..2adf161687a 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_autoleds.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_boot.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c index 5aacb0f9f11..0dce4b87b7d 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_boot.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_boot.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c similarity index 98% rename from boards/arm/stm32/stm32f334-disco/src/stm32_comp.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c index d1f45f0ab7a..9f0c52f925b 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_comp.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_comp.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_comp.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c similarity index 97% rename from boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c index 381aa7549c3..38885ff50b9 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_hrtim.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_hrtim.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c similarity index 97% rename from boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c index 67ba3ad9f67..03f9557d1e1 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_opamp.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_opamp.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c index 0f7890bd25f..81430e490d8 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_powerled.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_powerled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32_smps.c rename to boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c index 8c42a9c23cb..9253f274ce9 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32_smps.c +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32_smps.c + * boards/arm/stm32f3/stm32f334-disco/src/stm32_smps.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h similarity index 99% rename from boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h rename to boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h index 213f549b427..0aac0ea8e6c 100644 --- a/boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h +++ b/boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f334-disco/src/stm32f334-disco.h + * boards/arm/stm32f3/stm32f334-disco/src/stm32f334-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt new file mode 100644 index 00000000000..898b9836865 --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f3/stm32f3discovery/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/Kconfig b/boards/arm/stm32f3/stm32f3discovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f3discovery/Kconfig rename to boards/arm/stm32f3/stm32f3discovery/Kconfig diff --git a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig rename to boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig index b05c264572a..e05647d329b 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f3/stm32f3discovery/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f3discovery" CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303VC=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig rename to boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig index 11e8b675785..ca4b9b58240 100644 --- a/boards/arm/stm32/stm32f3discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32f3/stm32f3discovery/configs/usbnsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f3discovery" CONFIG_ARCH_BOARD_STM32F3_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f3" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F303VC=y CONFIG_ARCH_CHIP_STM32F3=y diff --git a/boards/arm/stm32/stm32f3discovery/include/board.h b/boards/arm/stm32f3/stm32f3discovery/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f3discovery/include/board.h rename to boards/arm/stm32f3/stm32f3discovery/include/board.h index 2761c0cfb05..0e989224f45 100644 --- a/boards/arm/stm32/stm32f3discovery/include/board.h +++ b/boards/arm/stm32f3/stm32f3discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/include/board.h + * boards/arm/stm32f3/stm32f3discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs new file mode 100644 index 00000000000..be421233cda --- /dev/null +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f3/stm32f3discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f3discovery/scripts/ld.script b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f3discovery/scripts/ld.script rename to boards/arm/stm32f3/stm32f3discovery/scripts/ld.script index eef42690810..a54ec9fcb66 100644 --- a/boards/arm/stm32/stm32f3discovery/scripts/ld.script +++ b/boards/arm/stm32f3/stm32f3discovery/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/scripts/ld.script + * boards/arm/stm32f3/stm32f3discovery/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt rename to boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt index a5f1196b826..b630617db14 100644 --- a/boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f3discovery/src/CMakeLists.txt +# boards/arm/stm32f3/stm32f3discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f3discovery/src/Make.defs b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f3discovery/src/Make.defs rename to boards/arm/stm32f3/stm32f3discovery/src/Make.defs index 5ab0f6b49b4..726b069c0ef 100644 --- a/boards/arm/stm32/stm32f3discovery/src/Make.defs +++ b/boards/arm/stm32f3/stm32f3discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f3discovery/src/Make.defs +# boards/arm/stm32f3/stm32f3discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c index fd2d12653cb..a88f93396fb 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_autoleds.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_boot.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c index fe335712274..88ceb8fb861 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_boot.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_boot.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c index b0fc88f9be7..4b4f5a63b73 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_bringup.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c index ba6a7507847..b95f1899118 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_buttons.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c index d929dcfd8ce..132b6bbdf56 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_pwm.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f3discovery/src/stm32_spi.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c index b5a17433a87..9b9e324250d 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_spi.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_spi.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_usb.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c index 375d66d3408..7084ab7babd 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_usb.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_usb.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c rename to boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c index 38ff516b8cb..f38041a78a1 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32_userleds.c + * boards/arm/stm32f3/stm32f3discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h similarity index 98% rename from boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h rename to boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h index 44464bcf3a8..79b10628034 100644 --- a/boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h +++ b/boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f3discovery/src/stm32f3discovery.h + * boards/arm/stm32f3/stm32f3discovery/src/stm32f3discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -33,7 +33,7 @@ #include -#include +#include #include "stm32.h" From 6cda2fcc96bb227adf000193908c5323dcb39138 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 158/268] !arch/stm32: move stm32f4 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32f4 sources, headers and boards into arch/arm/src/stm32f4, arch/arm/include/stm32f4 and boards/arm/stm32f4. Signed-off-by: raiden00pl --- arch/arm/include/stm32f4/chip.h | 864 ++++++++++++++++++ .../stm32f40xxx_irq.h => stm32f4/irq.h} | 63 +- arch/arm/src/stm32f4/CMakeLists.txt | 28 + arch/arm/src/stm32f4/Kconfig | 625 +++++++++++++ arch/arm/src/stm32f4/Make.defs | 27 + arch/arm/src/stm32f4/chip.h | 59 ++ .../src/stm32f4/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32f4/hardware/stm32_pinmap.h | 25 + .../hardware/stm32f40xxx_gpio.h | 2 +- .../hardware/stm32f40xxx_memorymap.h | 2 +- .../hardware/stm32f40xxx_pinmap.h | 2 +- .../hardware/stm32f40xxx_rcc.h | 2 +- .../hardware/stm32f40xxx_syscfg.h | 2 +- .../hardware/stm32f412xx_pinmap.h | 2 +- arch/arm/src/stm32f4/stm32.h | 69 ++ arch/arm/src/stm32f4/stm32_rcc.c | 234 +++++ .../{stm32 => stm32f4}/stm32f40xxx_alarm.h | 2 +- .../src/{stm32 => stm32f4}/stm32f40xxx_rcc.c | 2 +- .../maple => stm32f4/axoloti}/CMakeLists.txt | 2 +- boards/arm/{stm32 => stm32f4}/axoloti/Kconfig | 0 .../axoloti/configs/nsh/defconfig | 2 +- .../axoloti/include/board.h | 2 +- .../axoloti}/scripts/Make.defs | 3 +- .../axoloti/scripts/kernel-space.ld | 2 +- .../axoloti/scripts/ld.script | 2 +- .../axoloti/scripts/memory.ld | 4 +- .../axoloti/scripts/user-space.ld | 2 +- .../axoloti/src/CMakeLists.txt | 2 +- .../{stm32 => stm32f4}/axoloti/src/Make.defs | 2 +- .../{stm32 => stm32f4}/axoloti/src/axoloti.h | 4 +- .../axoloti/src/stm32_adau1961.c | 2 +- .../axoloti/src/stm32_boot.c | 2 +- .../axoloti/src/stm32_bringup.c | 2 +- .../axoloti/src/stm32_buttons.c | 2 +- .../axoloti/src/stm32_extmem.c | 2 +- .../axoloti/src/stm32_sdio.c | 2 +- .../axoloti/src/stm32_usbhost.c | 2 +- .../axoloti/src/stm32_userleds.c | 2 +- .../arm/stm32f4/clicker2-stm32/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/clicker2-stm32/Kconfig | 0 .../clicker2-stm32/configs/knsh/defconfig | 4 +- .../configs/mrf24j40-6lowpan/defconfig | 2 +- .../configs/mrf24j40-mac/defconfig | 2 +- .../configs/mrf24j40-starhub/defconfig | 2 +- .../configs/mrf24j40-starpoint/defconfig | 2 +- .../clicker2-stm32/configs/nsh/defconfig | 2 +- .../clicker2-stm32/configs/usbnsh/defconfig | 2 +- .../configs/xbee-6lowpan/defconfig | 2 +- .../clicker2-stm32/include/board.h | 2 +- .../clicker2-stm32/kernel/Makefile | 2 +- .../clicker2-stm32/kernel/stm32_userspace.c | 2 +- .../clicker2-stm32/scripts/Make.defs | 2 +- .../clicker2-stm32/scripts/flash.ld | 2 +- .../clicker2-stm32/scripts/kernel-space.ld | 2 +- .../clicker2-stm32/scripts/memory.ld | 4 +- .../clicker2-stm32/scripts/user-space.ld | 2 +- .../clicker2-stm32/src/CMakeLists.txt | 2 +- .../clicker2-stm32/src/Make.defs | 2 +- .../clicker2-stm32/src/clicker2-stm32.h | 2 +- .../clicker2-stm32/src/stm32_adc.c | 2 +- .../clicker2-stm32/src/stm32_autoleds.c | 2 +- .../clicker2-stm32/src/stm32_automount.c | 2 +- .../clicker2-stm32/src/stm32_boot.c | 2 +- .../clicker2-stm32/src/stm32_bringup.c | 2 +- .../clicker2-stm32/src/stm32_buttons.c | 2 +- .../clicker2-stm32/src/stm32_can.c | 2 +- .../clicker2-stm32/src/stm32_mmcsd.c | 2 +- .../clicker2-stm32/src/stm32_mrf24j40.c | 2 +- .../clicker2-stm32/src/stm32_spi.c | 2 +- .../clicker2-stm32/src/stm32_usb.c | 2 +- .../clicker2-stm32/src/stm32_userleds.c | 2 +- .../clicker2-stm32/src/stm32_xbee.c | 2 +- boards/arm/stm32f4/common/CMakeLists.txt | 25 + boards/arm/stm32f4/common/Kconfig | 6 + boards/arm/stm32f4/common/Makefile | 38 + .../arm/stm32f4/mikroe-stm32f4/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/mikroe-stm32f4/Kconfig | 0 .../mikroe-stm32f4/configs/fulldemo/defconfig | 2 +- .../mikroe-stm32f4/configs/kostest/defconfig | 4 +- .../mikroe-stm32f4/configs/nsh/defconfig | 2 +- .../mikroe-stm32f4/configs/nx/defconfig | 2 +- .../mikroe-stm32f4/configs/nxlines/defconfig | 2 +- .../mikroe-stm32f4/configs/nxtext/defconfig | 2 +- .../mikroe-stm32f4/configs/usbnsh/defconfig | 2 +- .../mikroe-stm32f4/include/board.h | 2 +- .../mikroe-stm32f4/kernel/Makefile | 2 +- .../mikroe-stm32f4/kernel/stm32_userspace.c | 2 +- .../stm32f4/mikroe-stm32f4/scripts/Make.defs | 41 + .../mikroe-stm32f4/scripts/kernel-space.ld | 2 +- .../mikroe-stm32f4/scripts/ld.script | 2 +- .../mikroe-stm32f4/scripts/memory.ld | 2 +- .../mikroe-stm32f4/scripts/user-space.ld | 2 +- .../mikroe-stm32f4/src/CMakeLists.txt | 2 +- .../mikroe-stm32f4/src/Make.defs | 2 +- .../mikroe-stm32f4/src/etc_romfs.c | 2 +- .../mikroe-stm32f4/src/mikroe-stm32f4.h | 2 +- .../mikroe-stm32f4/src/stm32_boot.c | 2 +- .../mikroe-stm32f4/src/stm32_clockconfig.c | 2 +- .../mikroe-stm32f4/src/stm32_extmem.c | 2 +- .../mikroe-stm32f4/src/stm32_idle.c | 2 +- .../mikroe-stm32f4/src/stm32_mio283qt2.c | 2 +- .../mikroe-stm32f4/src/stm32_mio283qt9a.c | 2 +- .../mikroe-stm32f4/src/stm32_pm.c | 2 +- .../mikroe-stm32f4/src/stm32_pwm.c | 2 +- .../mikroe-stm32f4/src/stm32_spi.c | 2 +- .../mikroe-stm32f4/src/stm32_touchscreen.c | 2 +- .../mikroe-stm32f4/src/stm32_usb.c | 2 +- .../mikroe-stm32f4/src/stm32_vs1053.c | 2 +- .../arm/stm32f4/nucleo-f401re/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f401re/Kconfig | 0 .../nucleo-f401re/configs/fb/defconfig | 2 +- .../nucleo-f401re/configs/nsh/defconfig | 2 +- .../nucleo-f401re/include/board.h | 2 +- .../nucleo-f401re/scripts/Make.defs | 2 +- .../nucleo-f401re/scripts/flash.ld | 2 +- .../nucleo-f401re/src/CMakeLists.txt | 2 +- .../nucleo-f401re/src/Make.defs | 2 +- .../nucleo-f401re/src/nucleo-f401re.h | 2 +- .../nucleo-f401re/src/stm32_adc.c | 2 +- .../nucleo-f401re/src/stm32_ajoystick.c | 2 +- .../nucleo-f401re/src/stm32_autoleds.c | 2 +- .../nucleo-f401re/src/stm32_boot.c | 2 +- .../nucleo-f401re/src/stm32_bringup.c | 3 +- .../nucleo-f401re/src/stm32_buttons.c | 2 +- .../nucleo-f401re/src/stm32_lcd_ssd1306.c | 2 +- .../nucleo-f401re/src/stm32_mcp2515.c | 2 +- .../nucleo-f401re/src/stm32_spi.c | 2 +- .../nucleo-f401re/src/stm32_userleds.c | 2 +- .../arm/stm32f4/nucleo-f410rb/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f410rb/Kconfig | 0 .../nucleo-f410rb/configs/nsh/defconfig | 2 +- .../nucleo-f410rb/include/board.h | 2 +- .../nucleo-f410rb/scripts/Make.defs | 2 +- .../nucleo-f410rb/scripts/f410rb.ld | 2 +- .../nucleo-f410rb/src/CMakeLists.txt | 2 +- .../nucleo-f410rb/src/Make.defs | 2 +- .../nucleo-f410rb/src/nucleo-f410rb.h | 2 +- .../nucleo-f410rb/src/stm32_adc.c | 2 +- .../nucleo-f410rb/src/stm32_autoleds.c | 2 +- .../nucleo-f410rb/src/stm32_boot.c | 2 +- .../nucleo-f410rb/src/stm32_bringup.c | 2 +- .../nucleo-f410rb/src/stm32_buttons.c | 2 +- .../nucleo-f410rb/src/stm32_userleds.c | 2 +- .../arm/stm32f4/nucleo-f411re/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f411re/Kconfig | 0 .../configs/mcp2515-extid/defconfig | 2 +- .../nucleo-f411re/configs/nsh/defconfig | 2 +- .../nucleo-f411re/include/board.h | 2 +- .../nucleo-f411re/scripts/Make.defs | 2 +- .../nucleo-f411re/scripts/flash.ld | 2 +- .../nucleo-f411re/src/CMakeLists.txt | 2 +- .../nucleo-f411re/src/Make.defs | 2 +- .../nucleo-f411re/src/nucleo-f411re.h | 2 +- .../nucleo-f411re/src/stm32_adc.c | 2 +- .../nucleo-f411re/src/stm32_ajoystick.c | 2 +- .../nucleo-f411re/src/stm32_autoleds.c | 2 +- .../nucleo-f411re/src/stm32_boot.c | 2 +- .../nucleo-f411re/src/stm32_bringup.c | 3 +- .../nucleo-f411re/src/stm32_buttons.c | 2 +- .../nucleo-f411re/src/stm32_lcd_ssd1306.c | 2 +- .../nucleo-f411re/src/stm32_mcp2515.c | 2 +- .../nucleo-f411re/src/stm32_spi.c | 2 +- .../nucleo-f411re/src/stm32_userleds.c | 2 +- .../arm/stm32f4/nucleo-f412zg/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f412zg/Kconfig | 0 .../nucleo-f412zg/configs/coremark/defconfig | 2 +- .../nucleo-f412zg/configs/nsh/defconfig | 2 +- .../nucleo-f412zg/configs/ostest/defconfig | 2 +- .../nucleo-f412zg/include/board.h | 2 +- .../nucleo-f412zg/scripts/Make.defs | 2 +- .../nucleo-f412zg/scripts/f412zg.ld | 2 +- .../nucleo-f412zg/src/CMakeLists.txt | 2 +- .../nucleo-f412zg/src/Make.defs | 2 +- .../nucleo-f412zg/src/nucleo-f412zg.h | 2 +- .../nucleo-f412zg/src/stm32_autoleds.c | 2 +- .../nucleo-f412zg/src/stm32_boot.c | 2 +- .../nucleo-f412zg/src/stm32_bringup.c | 2 +- .../nucleo-f412zg/src/stm32_usb.c | 2 +- .../arm/stm32f4/nucleo-f429zi/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f429zi/Kconfig | 0 .../nucleo-f429zi/configs/netnsh/defconfig | 2 +- .../nucleo-f429zi/configs/nsh/defconfig | 2 +- .../nucleo-f429zi/configs/trace/defconfig | 2 +- .../nucleo-f429zi/include/board.h | 2 +- .../nucleo-f429zi/scripts/Make.defs | 2 +- .../nucleo-f429zi}/scripts/kernel-space.ld | 2 +- .../nucleo-f429zi/scripts/ld.script | 2 +- .../nucleo-f429zi}/scripts/memory.ld | 4 +- .../nucleo-f429zi/scripts/user-space.ld | 2 +- .../nucleo-f429zi/src/CMakeLists.txt | 2 +- .../nucleo-f429zi/src/Make.defs | 2 +- .../nucleo-f429zi/src/nucleo-144.h | 2 +- .../nucleo-f429zi/src/stm32_adc.c | 2 +- .../nucleo-f429zi/src/stm32_autoleds.c | 2 +- .../nucleo-f429zi/src/stm32_bbsram.c | 2 +- .../nucleo-f429zi/src/stm32_boot.c | 2 +- .../nucleo-f429zi/src/stm32_buttons.c | 2 +- .../nucleo-f429zi/src/stm32_dma_alloc.c | 2 +- .../nucleo-f429zi/src/stm32_gpio.c | 2 +- .../nucleo-f429zi/src/stm32_pwm.c | 2 +- .../nucleo-f429zi/src/stm32_reset.c | 2 +- .../nucleo-f429zi/src/stm32_romfs.h | 2 +- .../src/stm32_romfs_initialize.c | 2 +- .../nucleo-f429zi/src/stm32_sdio.c | 2 +- .../nucleo-f429zi/src/stm32_spi.c | 2 +- .../nucleo-f429zi/src/stm32_usb.c | 2 +- .../nucleo-f429zi/src/stm32_userleds.c | 2 +- .../arm/stm32f4/nucleo-f446re/CMakeLists.txt | 23 + .../{stm32 => stm32f4}/nucleo-f446re/Kconfig | 0 .../nucleo-f446re/configs/adc/defconfig | 2 +- .../nucleo-f446re/configs/can/defconfig | 2 +- .../nucleo-f446re/configs/cansock/defconfig | 2 +- .../nucleo-f446re/configs/dac/defconfig | 2 +- .../nucleo-f446re/configs/gpio/defconfig | 2 +- .../configs/ihm08m1_b16/defconfig | 2 +- .../configs/ihm08m1_f32/defconfig | 2 +- .../nucleo-f446re/configs/jumbo/defconfig | 2 +- .../nucleo-f446re/configs/lcd/defconfig | 2 +- .../nucleo-f446re/configs/nsh/defconfig | 2 +- .../nucleo-f446re/configs/pwm/defconfig | 2 +- .../nucleo-f446re/configs/qenco/defconfig | 2 +- .../configs/systemview/defconfig | 2 +- .../nucleo-f446re/include/board.h | 2 +- .../nucleo-f446re/scripts/Make.defs | 2 +- .../nucleo-f446re/scripts/f446re.ld | 2 +- .../nucleo-f446re/src/CMakeLists.txt | 2 +- .../nucleo-f446re/src/Make.defs | 2 +- .../nucleo-f446re/src/nucleo-f446re.h | 2 +- .../nucleo-f446re/src/stm32_adc.c | 2 +- .../nucleo-f446re/src/stm32_ajoystick.c | 2 +- .../nucleo-f446re/src/stm32_autoleds.c | 2 +- .../nucleo-f446re/src/stm32_boot.c | 2 +- .../nucleo-f446re/src/stm32_bringup.c | 2 +- .../nucleo-f446re/src/stm32_buttons.c | 2 +- .../nucleo-f446re/src/stm32_can.c | 2 +- .../nucleo-f446re/src/stm32_cansock.c | 2 +- .../nucleo-f446re/src/stm32_dac.c | 2 +- .../nucleo-f446re/src/stm32_foc_ihm08m1.c | 2 +- .../nucleo-f446re/src/stm32_gpio.c | 2 +- .../nucleo-f446re/src/stm32_ili9225.c | 2 +- .../nucleo-f446re/src/stm32_pwm.c | 2 +- .../nucleo-f446re/src/stm32_romfs.h | 2 +- .../src/stm32_romfs_initialize.c | 2 +- .../nucleo-f446re/src/stm32_spi.c | 2 +- .../nucleo-f446re/src/stm32_userleds.c | 2 +- .../odrive36}/CMakeLists.txt | 2 +- .../arm/{stm32 => stm32f4}/odrive36/Kconfig | 0 .../odrive36/configs/nsh/defconfig | 2 +- .../odrive36/configs/usbnsh/defconfig | 2 +- .../odrive36/include/board.h | 2 +- .../odrive36}/scripts/Make.defs | 3 +- .../odrive36/scripts/ld.script | 2 +- .../odrive36/src/CMakeLists.txt | 2 +- .../{stm32 => stm32f4}/odrive36/src/Make.defs | 2 +- .../{stm32 => stm32f4}/odrive36/src/odrive.h | 2 +- .../odrive36/src/stm32_boot.c | 2 +- .../odrive36/src/stm32_bringup.c | 2 +- .../odrive36/src/stm32_foc.c | 2 +- .../odrive36/src/stm32_spi.c | 2 +- .../odrive36/src/stm32_usb.c | 2 +- .../stm32f4/olimex-stm32-e407/CMakeLists.txt | 23 + .../olimex-stm32-e407/Kconfig | 0 .../configs/bmp180/defconfig | 2 +- .../olimex-stm32-e407/configs/dac/defconfig | 2 +- .../configs/discover/defconfig | 2 +- .../configs/ina219/defconfig | 2 +- .../configs/mrf24j40-6lowpan/defconfig | 2 +- .../configs/mrf24j40-mac/defconfig | 2 +- .../configs/netnsh/defconfig | 2 +- .../olimex-stm32-e407/configs/nsh/defconfig | 2 +- .../configs/telnetd/defconfig | 2 +- .../olimex-stm32-e407/configs/timer/defconfig | 2 +- .../configs/usbnsh/defconfig | 2 +- .../configs/webserver/defconfig | 2 +- .../olimex-stm32-e407/include/board.h | 2 +- .../olimex-stm32-e407/scripts/Make.defs | 2 +- .../olimex-stm32-e407/scripts/f407ze.ld | 2 +- .../olimex-stm32-e407/scripts/f407zg.ld | 2 +- .../olimex-stm32-e407/src/CMakeLists.txt | 2 +- .../olimex-stm32-e407/src/Make.defs | 2 +- .../olimex-stm32-e407/src/olimex-stm32-e407.h | 4 +- .../olimex-stm32-e407/src/stm32_adc.c | 2 +- .../olimex-stm32-e407/src/stm32_autoleds.c | 2 +- .../olimex-stm32-e407/src/stm32_boot.c | 2 +- .../olimex-stm32-e407/src/stm32_bringup.c | 2 +- .../olimex-stm32-e407/src/stm32_buttons.c | 2 +- .../olimex-stm32-e407/src/stm32_can.c | 2 +- .../olimex-stm32-e407/src/stm32_dac.c | 2 +- .../olimex-stm32-e407/src/stm32_mrf24j40.c | 2 +- .../olimex-stm32-e407/src/stm32_spi.c | 2 +- .../olimex-stm32-e407/src/stm32_timer.c | 2 +- .../olimex-stm32-e407/src/stm32_usb.c | 2 +- .../olimex-stm32-e407/src/stm32_userleds.c | 2 +- .../stm32f4/olimex-stm32-h405/CMakeLists.txt | 23 + .../olimex-stm32-h405/Kconfig | 0 .../configs/usbnsh/defconfig | 2 +- .../olimex-stm32-h405/include/board.h | 2 +- .../olimex-stm32-h405}/scripts/Make.defs | 2 +- .../olimex-stm32-h405/scripts/ld.script | 2 +- .../olimex-stm32-h405}/src/CMakeLists.txt | 2 +- .../olimex-stm32-h405/src/Make.defs | 2 +- .../olimex-stm32-h405/src/olimex-stm32-h405.h | 2 +- .../olimex-stm32-h405/src/stm32_adc.c | 2 +- .../olimex-stm32-h405/src/stm32_autoleds.c | 2 +- .../olimex-stm32-h405/src/stm32_boot.c | 2 +- .../olimex-stm32-h405/src/stm32_buttons.c | 2 +- .../olimex-stm32-h405/src/stm32_can.c | 2 +- .../olimex-stm32-h405/src/stm32_usb.c | 2 +- .../olimex-stm32-h405/src/stm32_userleds.c | 2 +- .../stm32f4/olimex-stm32-h407/CMakeLists.txt | 23 + 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.../stm32f4discovery/configs/usbnsh/defconfig | 2 +- .../stm32f4discovery/configs/wifi/defconfig | 2 +- .../configs/xen1210/defconfig | 2 +- .../stm32f4discovery/include/board.h | 2 +- .../stm32f4discovery/kernel/CMakeLists.txt | 2 +- .../stm32f4discovery/kernel/Makefile | 2 +- .../stm32f4discovery/kernel/stm32_userspace.c | 2 +- .../stm32f4discovery/scripts/Make.defs | 41 + .../stm32f4discovery/scripts/kernel-space.ld | 2 +- .../stm32f4discovery/scripts/ld.script | 2 +- .../stm32f4discovery/scripts/memory.ld | 4 +- .../stm32f4discovery/scripts/user-space.ld | 2 +- .../stm32f4discovery/src/CMakeLists.txt | 2 +- .../stm32f4discovery/src/Make.defs | 2 +- .../stm32f4discovery/src/stm32_apa102.c | 3 +- .../stm32f4discovery/src/stm32_autoleds.c | 2 +- .../stm32f4discovery/src/stm32_boot.c | 2 +- .../stm32f4discovery/src/stm32_bringup.c | 3 +- .../stm32f4discovery/src/stm32_buttons.c | 2 +- .../stm32f4discovery/src/stm32_can.c | 2 +- .../stm32f4discovery/src/stm32_capture.c | 2 +- .../stm32f4discovery/src/stm32_composite.c | 2 +- .../stm32f4discovery/src/stm32_cs43l22.c | 2 +- .../stm32f4discovery/src/stm32_djoystick.c | 2 +- .../stm32f4discovery/src/stm32_enc28j60.c | 2 +- .../stm32f4discovery/src/stm32_ethernet.c | 2 +- .../stm32f4discovery/src/stm32_extmem.c | 2 +- .../stm32f4discovery/src/stm32_gs2200m.c | 2 +- .../stm32f4discovery/src/stm32_hciuart.c | 2 +- .../stm32f4discovery/src/stm32_hx711.c | 4 +- .../stm32f4discovery/src/stm32_idle.c | 2 +- .../stm32f4discovery/src/stm32_max7219.c | 2 +- .../stm32f4discovery/src/stm32_max7219_leds.c | 2 +- .../stm32f4discovery/src/stm32_mmcsd.c | 2 +- .../stm32f4discovery/src/stm32_netinit.c | 2 +- .../stm32f4discovery/src/stm32_pca9635.c | 2 +- .../stm32f4discovery/src/stm32_pm.c | 2 +- .../stm32f4discovery/src/stm32_pmbuttons.c | 2 +- .../stm32f4discovery/src/stm32_pwm.c | 2 +- .../stm32f4discovery}/src/stm32_reset.c | 2 +- .../stm32f4discovery/src/stm32_rgbled.c | 2 +- .../stm32f4discovery/src/stm32_romfs.h | 2 +- .../src/stm32_romfs_initialize.c | 2 +- .../stm32f4discovery/src/stm32_sdio.c | 2 +- .../stm32f4discovery/src/stm32_spi.c | 2 +- .../stm32f4discovery/src/stm32_ssd1289.c | 2 +- .../stm32f4discovery/src/stm32_ssd1351.c | 2 +- .../stm32f4discovery/src/stm32_st7032.c | 2 +- .../stm32f4discovery/src/stm32_st7567.c | 2 +- .../stm32f4discovery/src/stm32_st7789.c | 2 +- .../stm32f4discovery/src/stm32_sx127x.c | 2 +- .../stm32f4discovery/src/stm32_timer.c | 2 +- .../src/stm32_ug2864ambag01.c | 2 +- .../src/stm32_ug2864hsweg01.c | 2 +- .../stm32f4discovery/src/stm32_uid.c | 2 +- .../stm32f4discovery/src/stm32_usb.c | 2 +- .../stm32f4discovery/src/stm32_usbmsc.c | 2 +- .../stm32f4discovery/src/stm32_userleds.c | 2 +- .../stm32f4discovery/src/stm32_w5500.c | 2 +- .../stm32f4discovery/src/stm32f4discovery.h | 4 +- 675 files changed, 3378 insertions(+), 682 deletions(-) create mode 100644 arch/arm/include/stm32f4/chip.h rename arch/arm/include/{stm32/stm32f40xxx_irq.h => stm32f4/irq.h} (92%) create mode 100644 arch/arm/src/stm32f4/CMakeLists.txt create mode 100644 arch/arm/src/stm32f4/Kconfig create mode 100644 arch/arm/src/stm32f4/Make.defs create mode 100644 arch/arm/src/stm32f4/chip.h create mode 100644 arch/arm/src/stm32f4/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32f4/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f40xxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f40xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f40xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f40xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f40xxx_syscfg.h (99%) rename arch/arm/src/{stm32 => stm32f4}/hardware/stm32f412xx_pinmap.h (99%) create mode 100644 arch/arm/src/stm32f4/stm32.h create mode 100644 arch/arm/src/stm32f4/stm32_rcc.c rename arch/arm/src/{stm32 => stm32f4}/stm32f40xxx_alarm.h (98%) rename arch/arm/src/{stm32 => stm32f4}/stm32f40xxx_rcc.c (99%) rename boards/arm/{stm32/maple => stm32f4/axoloti}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f4}/axoloti/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/axoloti/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f4}/axoloti/include/board.h (99%) rename boards/arm/{stm32/odrive36 => stm32f4/axoloti}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/axoloti/scripts/kernel-space.ld (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/scripts/memory.ld (97%) rename boards/arm/{stm32 => stm32f4}/axoloti/scripts/user-space.ld (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/axoloti.h (99%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_adau1961.c (99%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_extmem.c (99%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_sdio.c (98%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_usbhost.c (99%) rename boards/arm/{stm32 => stm32f4}/axoloti/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/configs/knsh/defconfig (94%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/configs/mrf24j40-mac/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/configs/mrf24j40-starhub/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/configs/mrf24j40-starpoint/defconfig (99%) rename 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stm32f4}/clicker2-stm32/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/clicker2-stm32.h (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_adc.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_automount.c (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_can.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_mmcsd.c (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_mrf24j40.c (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_usb.c (98%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_userleds.c (97%) rename boards/arm/{stm32 => stm32f4}/clicker2-stm32/src/stm32_xbee.c (99%) create mode 100644 boards/arm/stm32f4/common/CMakeLists.txt create mode 100644 boards/arm/stm32f4/common/Kconfig create mode 100644 boards/arm/stm32f4/common/Makefile create mode 100644 boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/fulldemo/defconfig (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/kostest/defconfig (95%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/nx/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/nxlines/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/nxtext/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/configs/usbnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/include/board.h (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/kernel/Makefile (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/kernel/stm32_userspace.c (98%) create mode 100644 boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/scripts/kernel-space.ld (97%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/scripts/memory.ld (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/scripts/user-space.ld (97%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/etc_romfs.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/mikroe-stm32f4.h (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_clockconfig.c (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_extmem.c (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_idle.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_mio283qt2.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_mio283qt9a.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_pm.c (97%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_touchscreen.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f4}/mikroe-stm32f4/src/stm32_vs1053.c (99%) create mode 100644 boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/nucleo-f401re/Kconfig (100%) rename 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boards/arm/{stm32 => stm32f4}/nucleo-f401re/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f401re/src/stm32_lcd_ssd1306.c (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f401re/src/stm32_mcp2515.c (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f401re/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f401re/src/stm32_userleds.c (99%) create mode 100644 boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/include/board.h (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/scripts/f410rb.ld (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f4}/nucleo-f410rb/src/Make.defs (96%) rename boards/arm/{stm32 => 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stm32f4}/nucleo-f411re/src/stm32_userleds.c (99%) create mode 100644 boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/configs/coremark/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/configs/ostest/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/include/board.h (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/scripts/f412zg.ld (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/nucleo-f412zg.h (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/stm32_bringup.c (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f412zg/src/stm32_usb.c (99%) create mode 100644 boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/configs/netnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/configs/trace/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/include/board.h (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/scripts/Make.defs (97%) rename boards/arm/{stm32/stm3240g-eval => stm32f4/nucleo-f429zi}/scripts/kernel-space.ld (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/scripts/ld.script (98%) rename boards/arm/{stm32/stm32f429i-disco => stm32f4/nucleo-f429zi}/scripts/memory.ld (96%) rename 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stm32f4}/nucleo-f429zi/src/stm32_romfs.h (97%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/src/stm32_romfs_initialize.c (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/src/stm32_sdio.c (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f4}/nucleo-f429zi/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/configs/adc/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/configs/can/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/configs/cansock/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/configs/dac/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/nucleo-f446re/configs/gpio/defconfig (98%) rename boards/arm/{stm32 => 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stm32f4}/olimex-stm32-e407/src/stm32_timer.c (97%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-e407/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-e407/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/configs/usbnsh/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/include/board.h (99%) rename boards/arm/{stm32/olimex-stm32-p207 => stm32f4/olimex-stm32-h405}/scripts/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/scripts/ld.script (98%) rename boards/arm/{stm32/olimex-stm32-p207 => stm32f4/olimex-stm32-h405}/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/src/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-h405/src/olimex-stm32-h405.h (98%) rename boards/arm/{stm32 => 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stm32f4}/olimex-stm32-h407/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/audio/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/dhtxx/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/hidkbd/defconfig (98%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/kelf/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/kelf/defconfig (94%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/kmodule/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/kmodule/defconfig (93%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/knsh/Make.defs (96%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/configs/knsh/defconfig (93%) rename boards/arm/{stm32 => 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(99%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/src/stm32_st7735.c (98%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/src/stm32_usb.c (99%) rename boards/arm/{stm32 => stm32f4}/olimex-stm32-p407/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32f4/omnibusf4/CMakeLists.txt rename boards/arm/{stm32 => stm32f4}/omnibusf4/Kconfig (100%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/configs/nsh/defconfig (99%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/include/board.h (99%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/kernel/Makefile (98%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/kernel/stm32_userspace.c (98%) rename boards/arm/{stm32/stm32_tiny => stm32f4/omnibusf4}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/scripts/kernel-space.ld (98%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32f4}/omnibusf4/scripts/memory.ld (96%) rename boards/arm/{stm32 => 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stm32f4}/stm32f4discovery/src/stm32_userleds.c (99%) rename boards/arm/{stm32 => stm32f4}/stm32f4discovery/src/stm32_w5500.c (99%) rename boards/arm/{stm32 => stm32f4}/stm32f4discovery/src/stm32f4discovery.h (99%) diff --git a/arch/arm/include/stm32f4/chip.h b/arch/arm/include/stm32f4/chip.h new file mode 100644 index 00000000000..796e1590ab4 --- /dev/null +++ b/arch/arm/include/stm32f4/chip.h @@ -0,0 +1,864 @@ +/**************************************************************************** + * arch/arm/include/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32F4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32F01xD/E Family Differences: + * + * PART PACKAGE FLASH SDIO ADC Channels + * ----------- ---------------- ----- ---- ------------ + * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 + * STM32F401RD LQFP64 384Kb Yes 16 + * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 + * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 + * STM32F401RE LQFP64 512Kb Yes 16 + * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 + */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ + defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ + defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) +# define STM32_NSDIO 0 /* No SDIO interface */ +# else +# define STM32_NSDIO 1 /* One SDIO interface */ +# endif +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 3 /* SPI1-4 */ +# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 50 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 1 /* One advanced timers TIM1 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 0 /* No basic timers */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 81 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 0 /* No Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ +# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ +# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ +# define STM32_NSPI 5 /* SPI1-5 */ +# define STM32_NI2S 3 /* I2S1-3 */ +# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* 2 CAN */ +# define STM32_NSDIO 1 /* One SDIO interface */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ +# define STM32_NGPIO 113 /* GPIOA-H */ +# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ +# define STM32_NDAC 0 /* No DAC */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 139 /* GPIOA-I */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 114 /* GPIOA-I */ +# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 0 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# define STM32_NGPIO 168 /* GPIOA-K */ +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ + defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA + * 32-bit general timers TIM2 and 5 with DMA */ +# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 6 /* SPI1-6 */ +# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ +# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 2 /* CAN1-2 */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NGPIO 114 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) +# define STM32_NGPIO 131 /* GPIOA-I */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NGPIO 161 /* GPIOA-K */ +# endif +# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ +# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# if defined(CONFIG_ARCH_CHIP_STM32F469A) +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ + defined(CONFIG_ARCH_CHIP_STM32F469B) || \ + defined(CONFIG_ARCH_CHIP_STM32F469N) +# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ +# endif +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V2 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32F4_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32f4/irq.h similarity index 92% rename from arch/arm/include/stm32/stm32f40xxx_irq.h rename to arch/arm/include/stm32f4/irq.h index 268bcc2323b..eb9eb5e3438 100644 --- a/arch/arm/include/stm32/stm32f40xxx_irq.h +++ b/arch/arm/include/stm32f4/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32f40xxx_irq.h + * arch/arm/include/stm32f4/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -24,8 +24,8 @@ * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32F4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32F4_IRQ_H /**************************************************************************** * Included Files @@ -33,6 +33,7 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes @@ -42,13 +43,34 @@ * The IRQ number corresponds vector number and hence map directly to * bits in the NVIC. This does, however, waste several words of memory in * the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can - * be found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) */ +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + #define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */ @@ -321,27 +343,4 @@ # define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32F40XXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32F4_IRQ_H */ diff --git a/arch/arm/src/stm32f4/CMakeLists.txt b/arch/arm/src/stm32f4/CMakeLists.txt new file mode 100644 index 00000000000..7b5008db371 --- /dev/null +++ b/arch/arm/src/stm32f4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32f4/Kconfig b/arch/arm/src/stm32f4/Kconfig new file mode 100644 index 00000000000..ec97a0a6139 --- /dev/null +++ b/arch/arm/src/stm32f4/Kconfig @@ -0,0 +1,625 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 F4 configuration" + +if ARCH_CHIP_STM32F4 + +choice + prompt "STM32F4 Chip Selection" + depends on ARCH_CHIP_STM32F4 + +config ARCH_CHIP_STM32F401CB + bool "STM32F401CB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RB + bool "STM32F401RB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VB + bool "STM32F401VB" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CC + bool "STM32F401CC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401RC + bool "STM32F401RC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401VC + bool "STM32F401VC" + select STM32_STM32F401xBC + +config ARCH_CHIP_STM32F401CD + bool "STM32F401CD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RD + bool "STM32F401RD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VD + bool "STM32F401VD" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401CE + bool "STM32F401CE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401RE + bool "STM32F401RE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F401VE + bool "STM32F401VE" + select STM32_STM32F401xDE + +config ARCH_CHIP_STM32F410RB + bool "STM32F410RB" + select STM32_STM32F4XXX + select STM32_STM32F410 + +config ARCH_CHIP_STM32F411CE + bool "STM32F411CE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411RE + bool "STM32F411RE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F411VE + bool "STM32F411VE" + select STM32_STM32F4XXX + select STM32_STM32F411 + +config ARCH_CHIP_STM32F412CE + bool "STM32F412CE" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F412ZG + bool "STM32F412ZG" + select STM32_STM32F4XXX + select STM32_STM32F412 + +config ARCH_CHIP_STM32F405RG + bool "STM32F405RG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405VG + bool "STM32F405VG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F405ZG + bool "STM32F405ZG" + select STM32_STM32F4XXX + select STM32_STM32F405 + +config ARCH_CHIP_STM32F407VE + bool "STM32F407VE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407VG + bool "STM32F407VG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZE + bool "STM32F407ZE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407ZG + bool "STM32F407ZG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IE + bool "STM32F407IE" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F407IG + bool "STM32F407IG" + select STM32_STM32F4XXX + select STM32_STM32F407 + +config ARCH_CHIP_STM32F427V + bool "STM32F427V" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427Z + bool "STM32F427Z" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F427I + bool "STM32F427I" + select STM32_STM32F4XXX + select STM32_STM32F427 + +config ARCH_CHIP_STM32F429V + bool "STM32F429V" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429Z + bool "STM32F429Z" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429I + bool "STM32F429I" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429B + bool "STM32F429B" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F429N + bool "STM32F429N" + select STM32_STM32F4XXX + select STM32_STM32F429 + +config ARCH_CHIP_STM32F446M + bool "STM32F446M" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446R + bool "STM32F446R" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446V + bool "STM32F446V" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F446Z + bool "STM32F446Z" + select STM32_STM32F4XXX + select STM32_STM32F446 + +config ARCH_CHIP_STM32F469A + bool "STM32F469A" + select STM32_STM32F4XXX + select STM32_STM32F469 + +config ARCH_CHIP_STM32F469I + bool "STM32F469I" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469B + bool "STM32F469B" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +config ARCH_CHIP_STM32F469N + bool "STM32F469N" + select STM32_STM32F4XXX + select STM32_STM32F469 + select STM32_HAVE_ETHMAC + +endchoice + +endif + +config STM32_STM32F4XXX + bool + default n + select STM32_HAVE_OTGHS + select STM32_HAVE_DMA1 + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_DCMI + select STM32_HAVE_HASH + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_FLASH_ICACHE + select STM32_HAVE_FLASH_DCACHE + select STM32_HAVE_CRYP + select STM32_HAVE_SPI2 + select STM32_HAVE_I2C2 + select STM32_HAVE_IOCOMPENSATION + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V2 + select STM32_HAVE_IP_DMA_V2_STREAM + select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_F2F4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OTGHS_M3M4_V1 + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_F4 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_BKPSRAM + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V2 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32F401xBC + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401xDE + bool + default n + select STM32_STM32F401 + +config STM32_STM32F401 + bool + default n + select ARCH_CORTEXM4 + select STM32_STM32F4XXX + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F410 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI5 + select STM32_HAVE_DAC1 + +config STM32_STM32F411 + bool + default n + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F412 + bool + default n + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_USART3 + select STM32_HAVE_USART2 + select STM32_HAVE_USART6 + select STM32_HAVE_I2C1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_SPI1 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_OTGFS + select STM32_HAVE_I2SPLL + +config STM32_STM32F405 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_OTGFS + +config STM32_STM32F407 + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_OTGFS + +# This is really 427/437, but we treat the two the same. + +config STM32_STM32F427 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SPI6 + select STM32_HAVE_I2SPLL + +# This is really 429/439, but we treat the two the same. + +config STM32_STM32F429 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_ETHMAC + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_I2S3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + +config STM32_STM32F446 + bool + default n + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + +# This is really 469/479, but we treat the two the same. + +config STM32_STM32F469 + bool + default n + select STM32_HAVE_DMA2D + select STM32_HAVE_IP_DMA2D_M3M4_V1 + select STM32_HAVE_OVERDRIVE + select STM32_HAVE_FMC + select STM32_HAVE_LTDC + select STM32_HAVE_CCM + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_USART6 + select STM32_HAVE_UART7 + select STM32_HAVE_UART8 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_TIM12 + select STM32_HAVE_TIM13 + select STM32_HAVE_TIM14 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + select STM32_HAVE_CAN2 + select STM32_HAVE_DAC1 + select STM32_HAVE_RNG + select STM32_HAVE_SPI3 + select STM32_HAVE_SPI4 + select STM32_HAVE_SPI5 + select STM32_HAVE_SPI6 + select STM32_HAVE_OTGFS + select STM32_HAVE_SAIPLL + select STM32_HAVE_I2SPLL + select STM32_HAVE_I2S3 + select STM32_HAVE_I2C3 diff --git a/arch/arm/src/stm32f4/Make.defs b/arch/arm/src/stm32f4/Make.defs new file mode 100644 index 00000000000..061c1711624 --- /dev/null +++ b/arch/arm/src/stm32f4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32f4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32f4/chip.h b/arch/arm/src/stm32f4/chip.h new file mode 100644 index 00000000000..647bbd778c8 --- /dev/null +++ b/arch/arm/src/stm32f4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_CHIP_H +#define __ARCH_ARM_SRC_STM32F4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32F4_CHIP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..c2b208c9c27 --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32f40xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32f4/hardware/stm32_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..35b04147293 --- /dev/null +++ b/arch/arm/src/stm32f4/hardware/stm32_pinmap.h @@ -0,0 +1,25 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_STM32_STM32F412) +# include "hardware/stm32f412xx_pinmap.h" +#elif defined(CONFIG_STM32_STM32F4XXX) +# include "hardware/stm32f40xxx_pinmap.h" +#else +# error "Unsupported STM32F4 pin map" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h index 95ce98d3d93..167dedbd484 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_gpio.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h index 72fe218a444..c1549f7b994 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_memorymap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h index 0b40bdd8422..4f97953d160 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h index 08bd4e7328e..d4e56f3f296 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_rcc.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h rename to arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h index 19da1a40b39..9beeef94ebb 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h +++ b/arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_syscfg.h + * arch/arm/src/stm32f4/hardware/stm32f40xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h rename to arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h index 0ecba4ca903..305547e1888 100644 --- a/arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h +++ b/arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f412xx_pinmap.h + * arch/arm/src/stm32f4/hardware/stm32f412xx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32f4/stm32.h b/arch/arm/src/stm32f4/stm32.h new file mode 100644 index 00000000000..56a9dbc8151 --- /dev/null +++ b/arch/arm/src/stm32f4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32f4/stm32_rcc.c b/arch/arm/src/stm32f4/stm32_rcc.c new file mode 100644 index 00000000000..0c03fece5cd --- /dev/null +++ b/arch/arm/src/stm32f4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32f4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32f40xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32f40xxx_alarm.h b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h similarity index 98% rename from arch/arm/src/stm32/stm32f40xxx_alarm.h rename to arch/arm/src/stm32f4/stm32f40xxx_alarm.h index 98daa796e7b..04e096a63cb 100644 --- a/arch/arm/src/stm32/stm32f40xxx_alarm.h +++ b/arch/arm/src/stm32f4/stm32f40xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_alarm.h + * arch/arm/src/stm32f4/stm32f40xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32f40xxx_rcc.c rename to arch/arm/src/stm32f4/stm32f40xxx_rcc.c index 453ced82d2b..f5f8dc84a6f 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32f4/stm32f40xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32f40xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/maple/CMakeLists.txt b/boards/arm/stm32f4/axoloti/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/maple/CMakeLists.txt rename to boards/arm/stm32f4/axoloti/CMakeLists.txt index ebbac811ea8..83d2d132d5d 100644 --- a/boards/arm/stm32/maple/CMakeLists.txt +++ b/boards/arm/stm32f4/axoloti/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/maple/CMakeLists.txt +# boards/arm/stm32f4/axoloti/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/axoloti/Kconfig b/boards/arm/stm32f4/axoloti/Kconfig similarity index 100% rename from boards/arm/stm32/axoloti/Kconfig rename to boards/arm/stm32f4/axoloti/Kconfig diff --git a/boards/arm/stm32/axoloti/configs/nsh/defconfig b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/axoloti/configs/nsh/defconfig rename to boards/arm/stm32f4/axoloti/configs/nsh/defconfig index 13126e94b97..00ea1126c41 100644 --- a/boards/arm/stm32/axoloti/configs/nsh/defconfig +++ b/boards/arm/stm32f4/axoloti/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="axoloti" CONFIG_ARCH_BOARD_AXOLOTI=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F427I=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/axoloti/include/board.h b/boards/arm/stm32f4/axoloti/include/board.h similarity index 99% rename from boards/arm/stm32/axoloti/include/board.h rename to boards/arm/stm32f4/axoloti/include/board.h index 41d122815b3..07a076bda5a 100644 --- a/boards/arm/stm32/axoloti/include/board.h +++ b/boards/arm/stm32f4/axoloti/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/include/board.h + * boards/arm/stm32f4/axoloti/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/scripts/Make.defs b/boards/arm/stm32f4/axoloti/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/odrive36/scripts/Make.defs rename to boards/arm/stm32f4/axoloti/scripts/Make.defs index fc9a05f91d2..9f486f1452d 100644 --- a/boards/arm/stm32/odrive36/scripts/Make.defs +++ b/boards/arm/stm32f4/axoloti/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/odrive36/scripts/Make.defs +# boards/arm/stm32f4/axoloti/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -25,7 +25,6 @@ include $(TOPDIR)/tools/Config.mk include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs LDSCRIPT = ld.script - ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 diff --git a/boards/arm/stm32/axoloti/scripts/kernel-space.ld b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld similarity index 98% rename from boards/arm/stm32/axoloti/scripts/kernel-space.ld rename to boards/arm/stm32f4/axoloti/scripts/kernel-space.ld index 64edc323381..f87d33f4f44 100644 --- a/boards/arm/stm32/axoloti/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/axoloti/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/scripts/kernel-space.ld + * boards/arm/stm32f4/axoloti/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/scripts/ld.script b/boards/arm/stm32f4/axoloti/scripts/ld.script similarity index 98% rename from boards/arm/stm32/axoloti/scripts/ld.script rename to boards/arm/stm32f4/axoloti/scripts/ld.script index c7bb602cb21..72142ae7d5a 100644 --- a/boards/arm/stm32/axoloti/scripts/ld.script +++ b/boards/arm/stm32f4/axoloti/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/scripts/ld.script + * boards/arm/stm32f4/axoloti/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/scripts/memory.ld b/boards/arm/stm32f4/axoloti/scripts/memory.ld similarity index 97% rename from boards/arm/stm32/axoloti/scripts/memory.ld rename to boards/arm/stm32f4/axoloti/scripts/memory.ld index 2815db533fb..a168b907bc8 100644 --- a/boards/arm/stm32/axoloti/scripts/memory.ld +++ b/boards/arm/stm32f4/axoloti/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/scripts/memory.ld + * boards/arm/stm32f4/axoloti/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/axoloti/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/axoloti/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/axoloti/scripts/user-space.ld b/boards/arm/stm32f4/axoloti/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/axoloti/scripts/user-space.ld rename to boards/arm/stm32f4/axoloti/scripts/user-space.ld index 0a24aa25f6c..c5b08c5f847 100644 --- a/boards/arm/stm32/axoloti/scripts/user-space.ld +++ b/boards/arm/stm32f4/axoloti/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/scripts/user-space.ld + * boards/arm/stm32f4/axoloti/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/CMakeLists.txt b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/axoloti/src/CMakeLists.txt rename to boards/arm/stm32f4/axoloti/src/CMakeLists.txt index c232216905b..e1eb12177d5 100644 --- a/boards/arm/stm32/axoloti/src/CMakeLists.txt +++ b/boards/arm/stm32f4/axoloti/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/axoloti/src/CMakeLists.txt +# boards/arm/stm32f4/axoloti/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/axoloti/src/Make.defs b/boards/arm/stm32f4/axoloti/src/Make.defs similarity index 97% rename from boards/arm/stm32/axoloti/src/Make.defs rename to boards/arm/stm32f4/axoloti/src/Make.defs index e13a8e82802..69fd26fb33d 100644 --- a/boards/arm/stm32/axoloti/src/Make.defs +++ b/boards/arm/stm32f4/axoloti/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/axoloti/src/Make.defs +# boards/arm/stm32f4/axoloti/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/axoloti/src/axoloti.h b/boards/arm/stm32f4/axoloti/src/axoloti.h similarity index 99% rename from boards/arm/stm32/axoloti/src/axoloti.h rename to boards/arm/stm32f4/axoloti/src/axoloti.h index d6a2c7ac577..2554ef11df1 100644 --- a/boards/arm/stm32/axoloti/src/axoloti.h +++ b/boards/arm/stm32f4/axoloti/src/axoloti.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/axoloti.h + * boards/arm/stm32f4/axoloti/src/axoloti.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/axoloti/src/stm32_adau1961.c b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c similarity index 99% rename from boards/arm/stm32/axoloti/src/stm32_adau1961.c rename to boards/arm/stm32f4/axoloti/src/stm32_adau1961.c index 1d3851ba296..30fbef9abdd 100644 --- a/boards/arm/stm32/axoloti/src/stm32_adau1961.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_adau1961.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_adau1961.c + * boards/arm/stm32f4/axoloti/src/stm32_adau1961.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_boot.c b/boards/arm/stm32f4/axoloti/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/axoloti/src/stm32_boot.c rename to boards/arm/stm32f4/axoloti/src/stm32_boot.c index eda2b87a774..2eb3a1596fb 100644 --- a/boards/arm/stm32/axoloti/src/stm32_boot.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_boot.c + * boards/arm/stm32f4/axoloti/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_bringup.c b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/axoloti/src/stm32_bringup.c rename to boards/arm/stm32f4/axoloti/src/stm32_bringup.c index 0232a265bf9..f110e090558 100644 --- a/boards/arm/stm32/axoloti/src/stm32_bringup.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_bringup.c + * boards/arm/stm32f4/axoloti/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_buttons.c b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/axoloti/src/stm32_buttons.c rename to boards/arm/stm32f4/axoloti/src/stm32_buttons.c index 2fc688a660c..5ec7863e74c 100644 --- a/boards/arm/stm32/axoloti/src/stm32_buttons.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_buttons.c + * boards/arm/stm32f4/axoloti/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_extmem.c b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c similarity index 99% rename from boards/arm/stm32/axoloti/src/stm32_extmem.c rename to boards/arm/stm32f4/axoloti/src/stm32_extmem.c index a1558ff885c..496b14c757d 100644 --- a/boards/arm/stm32/axoloti/src/stm32_extmem.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_extmem.c + * boards/arm/stm32f4/axoloti/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_sdio.c b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c similarity index 98% rename from boards/arm/stm32/axoloti/src/stm32_sdio.c rename to boards/arm/stm32f4/axoloti/src/stm32_sdio.c index 58b957bc57a..35236a2039c 100644 --- a/boards/arm/stm32/axoloti/src/stm32_sdio.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_sdio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_sdio.c + * boards/arm/stm32f4/axoloti/src/stm32_sdio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_usbhost.c b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c similarity index 99% rename from boards/arm/stm32/axoloti/src/stm32_usbhost.c rename to boards/arm/stm32f4/axoloti/src/stm32_usbhost.c index c4b42ffc54a..94aed1ef76b 100644 --- a/boards/arm/stm32/axoloti/src/stm32_usbhost.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_usbhost.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_usbhost.c + * boards/arm/stm32f4/axoloti/src/stm32_usbhost.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/axoloti/src/stm32_userleds.c b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/axoloti/src/stm32_userleds.c rename to boards/arm/stm32f4/axoloti/src/stm32_userleds.c index c1aae206904..b6825a8b06b 100644 --- a/boards/arm/stm32/axoloti/src/stm32_userleds.c +++ b/boards/arm/stm32f4/axoloti/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/axoloti/src/stm32_userleds.c + * boards/arm/stm32f4/axoloti/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt new file mode 100644 index 00000000000..c6fa956e228 --- /dev/null +++ b/boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/clicker2-stm32/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/clicker2-stm32/Kconfig b/boards/arm/stm32f4/clicker2-stm32/Kconfig similarity index 100% rename from boards/arm/stm32/clicker2-stm32/Kconfig rename to boards/arm/stm32f4/clicker2-stm32/Kconfig diff --git a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig similarity index 94% rename from boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig index 8bc472bb1a3..3f73f847e27 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/knsh/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/knsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -34,7 +34,7 @@ CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/clicker2-stm32/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/clicker2-stm32/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=131072 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig similarity index 99% rename from boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig index 7a9d38c2dc5..d468e8c135b 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-6lowpan/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig similarity index 98% rename from boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig index 045007e9967..37c9d51ec17 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-mac/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig similarity index 98% rename from boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig index c468cfa3458..9906db1241a 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starhub/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig similarity index 99% rename from boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig index 18104f2c327..6f66c0144f9 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/mrf24j40-starpoint/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/mrf24j40-starpoint/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig index fe869ff395f..50e12a7f9e4 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/nsh/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig index 1b1542c9e7d..33748ef3eca 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/usbnsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig similarity index 99% rename from boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig rename to boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig index a453402fc63..853fec364b7 100644 --- a/boards/arm/stm32/clicker2-stm32/configs/xbee-6lowpan/defconfig +++ b/boards/arm/stm32f4/clicker2-stm32/configs/xbee-6lowpan/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="clicker2-stm32" CONFIG_ARCH_BOARD_CLICKER2_STM32=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/clicker2-stm32/include/board.h b/boards/arm/stm32f4/clicker2-stm32/include/board.h similarity index 99% rename from boards/arm/stm32/clicker2-stm32/include/board.h rename to boards/arm/stm32f4/clicker2-stm32/include/board.h index e13c619319b..5234be7f4f8 100644 --- a/boards/arm/stm32/clicker2-stm32/include/board.h +++ b/boards/arm/stm32f4/clicker2-stm32/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/include/board.h + * boards/arm/stm32f4/clicker2-stm32/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/kernel/Makefile b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile similarity index 98% rename from boards/arm/stm32/clicker2-stm32/kernel/Makefile rename to boards/arm/stm32f4/clicker2-stm32/kernel/Makefile index 5807644db2b..2f5b6553e72 100644 --- a/boards/arm/stm32/clicker2-stm32/kernel/Makefile +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/clicker2-stm32/kernel/Makefile +# boards/arm/stm32f4/clicker2-stm32/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c rename to boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c index 0274e2ab465..fcaa153b670 100644 --- a/boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/kernel/stm32_userspace.c + * boards/arm/stm32f4/clicker2-stm32/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/clicker2-stm32/scripts/Make.defs rename to boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs index c20f435cec4..a90d88a34ec 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/Make.defs +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/clicker2-stm32/scripts/Make.defs +# boards/arm/stm32f4/clicker2-stm32/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/clicker2-stm32/scripts/flash.ld rename to boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld index 31444fc0659..4615162c950 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/flash.ld +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/flash.ld + * boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld rename to boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld index d67c215eb7e..4ab5390cf82 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld + * boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/clicker2-stm32/scripts/memory.ld rename to boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld index 75ae8743baf..c19be9593b5 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/memory.ld +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/memory.ld + * boards/arm/stm32f4/clicker2-stm32/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -34,7 +34,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/clicker2-stm32/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/clicker2-stm32/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/clicker2-stm32/scripts/user-space.ld rename to boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld index 1e89ef45fd0..a7fa7ca7f56 100644 --- a/boards/arm/stm32/clicker2-stm32/scripts/user-space.ld +++ b/boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/scripts/user-space.ld + * boards/arm/stm32f4/clicker2-stm32/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt rename to boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt index cb3d46c6c34..ae754f915ab 100644 --- a/boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt +++ b/boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/clicker2-stm32/src/CMakeLists.txt +# boards/arm/stm32f4/clicker2-stm32/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/clicker2-stm32/src/Make.defs b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs similarity index 97% rename from boards/arm/stm32/clicker2-stm32/src/Make.defs rename to boards/arm/stm32f4/clicker2-stm32/src/Make.defs index 6079d7268ea..8aa9073a43a 100644 --- a/boards/arm/stm32/clicker2-stm32/src/Make.defs +++ b/boards/arm/stm32f4/clicker2-stm32/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/clicker2-stm32/src/Make.defs +# boards/arm/stm32f4/clicker2-stm32/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h rename to boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h index 206efc3a8ba..021d8c0ceac 100644 --- a/boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h +++ b/boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/clicker2-stm32.h + * boards/arm/stm32f4/clicker2-stm32/src/clicker2-stm32.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_adc.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c index 0f3fa6dd712..2da98b9f340 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_adc.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_adc.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c index ea8eaced940..c05d2d69f3a 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_autoleds.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_automount.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c index 6b2927ae6b5..7b3b777ceeb 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_automount.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_automount.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_boot.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c index 7c6c0bd27c7..89ef2589b8e 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_boot.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_boot.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c index 3dd96d97b7e..385e36e540a 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_bringup.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c index ccae882484f..357926885bd 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_buttons.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_can.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c index ac1db032f95..c5487024a47 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_can.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_can.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c index a9988f5017f..6d34e4bb215 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mmcsd.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c index 35b83249479..ecd813fb9a5 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_mrf24j40.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_mrf24j40.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_spi.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c index 26df2d0e6d3..3e631a3b6a3 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_spi.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_spi.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/clicker2-stm32/src/stm32_usb.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c index 5739adee983..6c32c09880b 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_usb.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_usb.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c index 0ad9207c751..4d9f9190137 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_userleds.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c similarity index 99% rename from boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c rename to boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c index c5bd9cafb82..8aef55384ca 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c +++ b/boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/clicker2-stm32/src/stm32_xbee.c + * boards/arm/stm32f4/clicker2-stm32/src/stm32_xbee.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/common/CMakeLists.txt b/boards/arm/stm32f4/common/CMakeLists.txt new file mode 100644 index 00000000000..5881e8c3972 --- /dev/null +++ b/boards/arm/stm32f4/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32f4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32f4/common/Kconfig b/boards/arm/stm32f4/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32f4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32f4/common/Makefile b/boards/arm/stm32f4/common/Makefile new file mode 100644 index 00000000000..817d2270613 --- /dev/null +++ b/boards/arm/stm32f4/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32f4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt new file mode 100644 index 00000000000..ea2ce2c8f04 --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/mikroe-stm32f4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/mikroe-stm32f4/Kconfig b/boards/arm/stm32f4/mikroe-stm32f4/Kconfig similarity index 100% rename from boards/arm/stm32/mikroe-stm32f4/Kconfig rename to boards/arm/stm32f4/mikroe-stm32f4/Kconfig diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig index 4608142f8d4..b72204cedca 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/fulldemo/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig similarity index 95% rename from boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig index e8099c11539..1c3eb8c59df 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/kostest/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/kostest/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -53,7 +53,7 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NSH_STRERROR=y CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/mikroe-stm32f4/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/mikroe-stm32f4/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMMTD=y CONFIG_RAM_SIZE=114688 diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig index c8abdaa5642..b1dfc76caa8 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nsh/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig index f8e4317f850..000e9a61f29 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nx/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nx/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig index 7ebdd06692a..c67e2e80f97 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxlines/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxlines/defconfig @@ -19,7 +19,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig index cff66efd83a..30d89a2cdff 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/nxtext/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/nxtext/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig rename to boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig index 3d2e73deec4..598b9908013 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/mikroe-stm32f4/configs/usbnsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="mikroe-stm32f4" CONFIG_ARCH_BOARD_MIKROE_STM32F4=y CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/mikroe-stm32f4/include/board.h b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/include/board.h rename to boards/arm/stm32f4/mikroe-stm32f4/include/board.h index 7c5d365a96b..8c6d5b2833e 100644 --- a/boards/arm/stm32/mikroe-stm32f4/include/board.h +++ b/boards/arm/stm32f4/mikroe-stm32f4/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/include/board.h + * boards/arm/stm32f4/mikroe-stm32f4/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/kernel/Makefile rename to boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile index 6983f10eff1..085f09c0d79 100644 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/Makefile +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/mikroe-stm32f4/kernel/Makefile +# boards/arm/stm32f4/mikroe-stm32f4/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c rename to boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c index 81c267d2fd5..75c04f0ea07 100644 --- a/boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/kernel/stm32_userspace.c + * boards/arm/stm32f4/mikroe-stm32f4/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs new file mode 100644 index 00000000000..c97f06d478e --- /dev/null +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/mikroe-stm32f4/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld rename to boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld index 1555c66cdde..153de5546bd 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/kernel-space.ld + * boards/arm/stm32f4/mikroe-stm32f4/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/scripts/ld.script rename to boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script index c576581edc4..b0a85f1be26 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/ld.script +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/ld.script + * boards/arm/stm32f4/mikroe-stm32f4/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld rename to boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld index a8f5498242e..9d0a6f39cf6 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/memory.ld + * boards/arm/stm32f4/mikroe-stm32f4/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld rename to boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld index e7e09d43613..56cf83bb0fa 100644 --- a/boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld +++ b/boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/scripts/user-space.ld + * boards/arm/stm32f4/mikroe-stm32f4/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt rename to boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt index ccadb52a739..1f0c3d19eed 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/src/CMakeLists.txt +# boards/arm/stm32f4/mikroe-stm32f4/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/src/Make.defs rename to boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs index 4d1e116adb8..aea83e0fe05 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/Make.defs +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/mikroe-stm32f4/src/Make.defs +# boards/arm/stm32f4/mikroe-stm32f4/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c index 158b6f53256..8e4bde5a9f6 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/etc_romfs.c + * boards/arm/stm32f4/mikroe-stm32f4/src/etc_romfs.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h rename to boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h index beeb62fda1f..ab13436ea21 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/mikroe-stm32f4.h + * boards/arm/stm32f4/mikroe-stm32f4/src/mikroe-stm32f4.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c index aa2a1c87b09..548e44dd179 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_boot.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c index 75b6870101a..2bf857538d2 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_clockconfig.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c index bcc1ef406e2..3f04746a7ec 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_extmem.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c index f03d247d4ad..f9cef25fff2 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_idle.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c index c56b43eed1a..259eaf710b7 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt2.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c index b40aff992d5..aab48c5e5e5 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_mio283qt9a.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c similarity index 97% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c index d7ce01fddfd..1905d67954d 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pm.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c index 28cb28a6653..0e96a7fd9a2 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_pwm.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c index 2877044cc8a..35f55d130af 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c index d95270676d7..c1ca2713954 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_touchscreen.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_touchscreen.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c index bba5752941b..fc2c9b7af8f 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_usb.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c similarity index 99% rename from boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c rename to boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c index 00f3c919e2e..938fa176441 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c +++ b/boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c + * boards/arm/stm32f4/mikroe-stm32f4/src/stm32_vs1053.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt new file mode 100644 index 00000000000..a8b1f68f8e1 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f401re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f401re/Kconfig b/boards/arm/stm32f4/nucleo-f401re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f401re/Kconfig rename to boards/arm/stm32f4/nucleo-f401re/Kconfig diff --git a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f401re/configs/fb/defconfig rename to boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig index 9ac5b0e47cc..7e41a425008 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/fb/defconfig +++ b/boards/arm/stm32f4/nucleo-f401re/configs/fb/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="nucleo-f401re" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F401RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig index 9ad92364dd4..691067a8b3a 100644 --- a/boards/arm/stm32/nucleo-f401re/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f401re/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f401re" CONFIG_ARCH_BOARD_NUCLEO_F401RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f401re/include/board.h b/boards/arm/stm32f4/nucleo-f401re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f401re/include/board.h rename to boards/arm/stm32f4/nucleo-f401re/include/board.h index 48a13db82da..f8cff6a2383 100644 --- a/boards/arm/stm32/nucleo-f401re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f401re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/include/board.h + * boards/arm/stm32f4/nucleo-f401re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f401re/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs index a106e21e6af..35c3c0c4e27 100644 --- a/boards/arm/stm32/nucleo-f401re/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f401re/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f401re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/nucleo-f401re/scripts/flash.ld rename to boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld index 4ad627c8819..66d8d456dc6 100644 --- a/boards/arm/stm32/nucleo-f401re/scripts/flash.ld +++ b/boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/scripts/flash.ld + * boards/arm/stm32f4/nucleo-f401re/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt index d1e694f4405..b0ff5784c01 100644 --- a/boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f401re/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f401re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f401re/src/Make.defs b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f401re/src/Make.defs rename to boards/arm/stm32f4/nucleo-f401re/src/Make.defs index 45725b5052e..369d8455de3 100644 --- a/boards/arm/stm32/nucleo-f401re/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f401re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f401re/src/Make.defs +# boards/arm/stm32f4/nucleo-f401re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h rename to boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h index 09a0d7af69a..3e3010ad53b 100644 --- a/boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h +++ b/boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/nucleo-f401re.h + * boards/arm/stm32f4/nucleo-f401re/src/nucleo-f401re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f401re/src/stm32_adc.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c index 2ad4c4e22e8..71b9e0974ec 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_adc.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_adc.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c index 7752b7a61da..7aa58581772 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_ajoystick.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_ajoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c index 6dffbce983e..7ccc0909188 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f401re/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c index 66eb41c6066..c37cf6b9feb 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c index d768f5dc584..224f1ead6d9 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_bringup.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c index b0a02f7a879..da3e2fb0ee6 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_buttons.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c index 144f5b50c58..4865b4d69b0 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_lcd_ssd1306.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c index 5ed40a07fde..3a87e3e7af2 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_mcp2515.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_mcp2515.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/stm32_spi.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c index 2b7cf5fac79..721b001a014 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_spi.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_spi.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c rename to boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c index 0415373cc07..c7737d5e3e0 100644 --- a/boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c +++ b/boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f401re/src/stm32_userleds.c + * boards/arm/stm32f4/nucleo-f401re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt new file mode 100644 index 00000000000..bbf909582a5 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f410rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/Kconfig b/boards/arm/stm32f4/nucleo-f410rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f410rb/Kconfig rename to boards/arm/stm32f4/nucleo-f410rb/Kconfig diff --git a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig index d34fcf48937..2f7c904678d 100644 --- a/boards/arm/stm32/nucleo-f410rb/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f410rb/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f410rb" CONFIG_ARCH_BOARD_NUCLEO_F410RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F410RB=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f410rb/include/board.h b/boards/arm/stm32f4/nucleo-f410rb/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f410rb/include/board.h rename to boards/arm/stm32f4/nucleo-f410rb/include/board.h index 0da6ad80797..4a264975b6f 100644 --- a/boards/arm/stm32/nucleo-f410rb/include/board.h +++ b/boards/arm/stm32f4/nucleo-f410rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/include/board.h + * boards/arm/stm32f4/nucleo-f410rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f410rb/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs index af0a457b263..02cb165c1f3 100644 --- a/boards/arm/stm32/nucleo-f410rb/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f410rb/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f410rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld rename to boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld index ec48fa2500b..3cabdd87366 100644 --- a/boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld +++ b/boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/scripts/f410rb.ld + * boards/arm/stm32f4/nucleo-f410rb/scripts/f410rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt index df15551bccb..99f2c446b20 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f410rb/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f410rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f410rb/src/Make.defs b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-f410rb/src/Make.defs rename to boards/arm/stm32f4/nucleo-f410rb/src/Make.defs index abd7559d831..dce7ead7aff 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f410rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f410rb/src/Make.defs +# boards/arm/stm32f4/nucleo-f410rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h rename to boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h index 1ff343716d0..a6f43ec0118 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h +++ b/boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/nucleo-f410rb.h + * boards/arm/stm32f4/nucleo-f410rb/src/nucleo-f410rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c index cf679ab14d2..db055495438 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_adc.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c index 4eaaaf20686..f182bd93aed 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c index d85baaa2d49..41ead6f349c 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c index 043d8c543a8..53c3ee92501 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_bringup.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c index 0797e9f5139..a400a0692c9 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_buttons.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c rename to boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c index b007a34d323..80c619214d6 100644 --- a/boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c +++ b/boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f410rb/src/stm32_userleds.c + * boards/arm/stm32f4/nucleo-f410rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt new file mode 100644 index 00000000000..cbf8d25eb2d --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f411re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/Kconfig b/boards/arm/stm32f4/nucleo-f411re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f411re/Kconfig rename to boards/arm/stm32f4/nucleo-f411re/Kconfig diff --git a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig rename to boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig index 94fb4e9344c..a15efeda085 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/mcp2515-extid/defconfig +++ b/boards/arm/stm32f4/nucleo-f411re/configs/mcp2515-extid/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f411re" CONFIG_ARCH_BOARD_NUCLEO_F411RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411RE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig index 4711d3f0d23..97a77721430 100644 --- a/boards/arm/stm32/nucleo-f411re/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f411re/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f411re" CONFIG_ARCH_BOARD_NUCLEO_F411RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411RE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f411re/include/board.h b/boards/arm/stm32f4/nucleo-f411re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f411re/include/board.h rename to boards/arm/stm32f4/nucleo-f411re/include/board.h index 9b16ece4154..6613554b8c4 100644 --- a/boards/arm/stm32/nucleo-f411re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f411re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/include/board.h + * boards/arm/stm32f4/nucleo-f411re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f411re/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs index 88f77e2be62..15d0e61e1e9 100644 --- a/boards/arm/stm32/nucleo-f411re/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f411re/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f411re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/nucleo-f411re/scripts/flash.ld rename to boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld index 09718dfc8e3..2a160e7bbfc 100644 --- a/boards/arm/stm32/nucleo-f411re/scripts/flash.ld +++ b/boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/scripts/flash.ld + * boards/arm/stm32f4/nucleo-f411re/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt index 9339106e5de..951b203a531 100644 --- a/boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f411re/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f411re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f411re/src/Make.defs b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f411re/src/Make.defs rename to boards/arm/stm32f4/nucleo-f411re/src/Make.defs index 0bab56576f5..9f0e1dfa8db 100644 --- a/boards/arm/stm32/nucleo-f411re/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f411re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f411re/src/Make.defs +# boards/arm/stm32f4/nucleo-f411re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h rename to boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h index 036d7b73c37..2f052ef44dc 100644 --- a/boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h +++ b/boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/nucleo-f411re.h + * boards/arm/stm32f4/nucleo-f411re/src/nucleo-f411re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f411re/src/stm32_adc.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c index cde6cfc40ae..d07d2edbc6a 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_adc.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_adc.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c index 69dcfc850d0..9ba5d9f69aa 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_ajoystick.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c index 24b8a3db27e..16655c5a13e 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f411re/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c index 88b543398ba..aabbaf87e94 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c index 04836ee845a..5d0025fdac2 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_bringup.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -33,6 +33,7 @@ #include #include #include +#include #include #include diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c index 7d064a6b2d5..25f46f07154 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_buttons.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c similarity index 97% rename from boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c index 558b20fa145..1fda9fe85e2 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_lcd_ssd1306.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c index 2de6483c236..3b5cf927c8d 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_mcp2515.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_mcp2515.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/stm32_spi.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c index 9a7d4878355..69a16d88c7f 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_spi.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_spi.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c rename to boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c index 63434897ac3..0cb15012e4e 100644 --- a/boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c +++ b/boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f411re/src/stm32_userleds.c + * boards/arm/stm32f4/nucleo-f411re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt new file mode 100644 index 00000000000..78c8c99ff25 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f412zg/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/Kconfig b/boards/arm/stm32f4/nucleo-f412zg/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f412zg/Kconfig rename to boards/arm/stm32f4/nucleo-f412zg/Kconfig diff --git a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig rename to boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig index bc43703857b..4f4f921618c 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/coremark/defconfig +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/coremark/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig index 1f346ea02df..ece24fb0b1a 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/nsh/defconfig @@ -17,7 +17,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig rename to boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig index 223b220ecac..e6c03ecfce8 100644 --- a/boards/arm/stm32/nucleo-f412zg/configs/ostest/defconfig +++ b/boards/arm/stm32f4/nucleo-f412zg/configs/ostest/defconfig @@ -17,7 +17,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f412zg" CONFIG_ARCH_BOARD_NUCLEO_F412ZG=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F412ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f412zg/include/board.h b/boards/arm/stm32f4/nucleo-f412zg/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f412zg/include/board.h rename to boards/arm/stm32f4/nucleo-f412zg/include/board.h index 9414bde3d63..35a7fa13dd5 100644 --- a/boards/arm/stm32/nucleo-f412zg/include/board.h +++ b/boards/arm/stm32f4/nucleo-f412zg/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/include/board.h + * boards/arm/stm32f4/nucleo-f412zg/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f412zg/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs index 9cc6754a294..7bd8f7113fd 100644 --- a/boards/arm/stm32/nucleo-f412zg/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f412zg/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f412zg/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld rename to boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld index 0c66b0979e5..d89c0190925 100644 --- a/boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld +++ b/boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/scripts/f412zg.ld + * boards/arm/stm32f4/nucleo-f412zg/scripts/f412zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt index b3cae915b25..48cd9e87536 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f412zg/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f412zg/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f412zg/src/Make.defs b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-f412zg/src/Make.defs rename to boards/arm/stm32f4/nucleo-f412zg/src/Make.defs index d437533fd24..9c28d010d93 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f412zg/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f412zg/src/Make.defs +# boards/arm/stm32f4/nucleo-f412zg/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h rename to boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h index e0a4726994c..203f5ce9273 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h +++ b/boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/nucleo-f412zg.h + * boards/arm/stm32f4/nucleo-f412zg/src/nucleo-f412zg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c index 554db9c523b..c9e7efe0a24 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c index f55d0686040..407e508cc35 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c similarity index 97% rename from boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c rename to boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c index 5b14c9c8f27..695de2977b5 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_bringup.c + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c rename to boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c index d3eef5fcdc6..5359021bc95 100644 --- a/boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c +++ b/boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c + * boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. diff --git a/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt new file mode 100644 index 00000000000..cefebbf5e50 --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f429zi/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/Kconfig b/boards/arm/stm32f4/nucleo-f429zi/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f429zi/Kconfig rename to boards/arm/stm32f4/nucleo-f429zi/Kconfig diff --git a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig rename to boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig index 13de7189e38..d6a052fbd2a 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/netnsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/netnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig index 6b6330f2792..262b4becc71 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig rename to boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig index 691ca8e05ed..a03f1d5e458 100644 --- a/boards/arm/stm32/nucleo-f429zi/configs/trace/defconfig +++ b/boards/arm/stm32f4/nucleo-f429zi/configs/trace/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f429zi" CONFIG_ARCH_BOARD_NUCLEO_F429ZI=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f429zi/include/board.h b/boards/arm/stm32f4/nucleo-f429zi/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/include/board.h rename to boards/arm/stm32f4/nucleo-f429zi/include/board.h index 04829a544e8..4e259c13a92 100644 --- a/boards/arm/stm32/nucleo-f429zi/include/board.h +++ b/boards/arm/stm32f4/nucleo-f429zi/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/include/board.h + * boards/arm/stm32f4/nucleo-f429zi/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs index 70114e47e21..b60be2ea221 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f429zi/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f429zi/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld rename to boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld index 92d718a435c..c1decce24f5 100644 --- a/boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld + * boards/arm/stm32f4/nucleo-f429zi/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/scripts/ld.script rename to boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script index 7c53a588434..9a1d4001a99 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/ld.script +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/ld.script + * boards/arm/stm32f4/nucleo-f429zi/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/stm32f429i-disco/scripts/memory.ld rename to boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld index 95ece2dbfe8..ec8a5798e4a 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/memory.ld +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/memory.ld + * boards/arm/stm32f4/nucleo-f429zi/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld rename to boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld index 03cd4598f1b..2a9866a6758 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld +++ b/boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/user-space.ld + * boards/arm/stm32f4/nucleo-f429zi/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt index cfcef00556c..1f6f30ca92b 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f429zi/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f429zi/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f429zi/src/Make.defs b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/src/Make.defs rename to boards/arm/stm32f4/nucleo-f429zi/src/Make.defs index 2824447d2d6..22ef4de2cdd 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f429zi/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f429zi/src/Make.defs +# boards/arm/stm32f4/nucleo-f429zi/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h rename to boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h index c66f463faa4..60e0078b43c 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h +++ b/boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/nucleo-144.h + * boards/arm/stm32f4/nucleo-f429zi/src/nucleo-144.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c index 25efe68db8b..1c8b4361bdf 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_adc.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c index 9dedddc80a9..54359c2a174 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c index a9c35cc5cc4..3d90e5cb5a2 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_bbsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c index f6131a8308b..656da24f967 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c index 656f3e42fc7..26101a63eb9 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_buttons.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c index c11a26e3adb..0cc0979f578 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_dma_alloc.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_dma_alloc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c index b1de5bf8c16..b58bf7c7a5c 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_gpio.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c index 53f1ec4ebd7..a7186ebdb7c 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_pwm.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c index 80a5399c8cd..c17caaa874e 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_reset.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h index bd2b62c9854..2e8f7f643cb 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs.h + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c index ac86209be36..8eaaf58c73d 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_romfs_initialize.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_romfs_initialize.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c index 48a4f794420..fd8a1dca33e 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_sdio.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_sdio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c index 70e933f51ca..fa7a2cc7519 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_spi.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c index 7ad104a61f0..47d002de4cc 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_usb.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c rename to boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c index 80d0f0247fc..7677d7ba65c 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c +++ b/boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/src/stm32_userleds.c + * boards/arm/stm32f4/nucleo-f429zi/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt new file mode 100644 index 00000000000..4371e311a7b --- /dev/null +++ b/boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/nucleo-f446re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/Kconfig b/boards/arm/stm32f4/nucleo-f446re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-f446re/Kconfig rename to boards/arm/stm32f4/nucleo-f446re/Kconfig diff --git a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/adc/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig index fef22a76f57..5b5f4de0bc0 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/adc/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/adc/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/can/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig index eb95a0857ea..bf16478bf0f 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/can/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/can/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig index 93cd1a3a7a6..e549ee92ce9 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/cansock/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/cansock/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/dac/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig index 94e7c7aa642..12275ba08bf 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/dac/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/dac/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig index bc1d3de1e86..9367b5a74c2 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/gpio/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/gpio/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig index a4f0be9b9bc..243dbde9820 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_b16/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_b16/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig index cfba3f468ea..ce02324a89a 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/ihm08m1_f32/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/ihm08m1_f32/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig index 37087dd5ce9..aa93ca052f8 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/jumbo/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/jumbo/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig index 113b92fc963..db27a7127b8 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/lcd/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/lcd/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig index f37e6a0b9a4..a4266c978ab 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/nsh/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig index 49a67a4fa1c..d56c5382c30 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/pwm/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/pwm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig index e2a2f748c60..9227f770c55 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/qenco/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/qenco/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig rename to boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig index 1fdaa7ce509..891ed15e150 100644 --- a/boards/arm/stm32/nucleo-f446re/configs/systemview/defconfig +++ b/boards/arm/stm32f4/nucleo-f446re/configs/systemview/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-f446re" CONFIG_ARCH_BOARD_NUCLEO_F446RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F446R=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/nucleo-f446re/include/board.h b/boards/arm/stm32f4/nucleo-f446re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-f446re/include/board.h rename to boards/arm/stm32f4/nucleo-f446re/include/board.h index 3e4b1ed1757..dc46e111057 100644 --- a/boards/arm/stm32/nucleo-f446re/include/board.h +++ b/boards/arm/stm32f4/nucleo-f446re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/include/board.h + * boards/arm/stm32f4/nucleo-f446re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f446re/scripts/Make.defs rename to boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs index 3ce0409127a..e2c1dea47e0 100644 --- a/boards/arm/stm32/nucleo-f446re/scripts/Make.defs +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f446re/scripts/Make.defs +# boards/arm/stm32f4/nucleo-f446re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld similarity index 98% rename from boards/arm/stm32/nucleo-f446re/scripts/f446re.ld rename to boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld index bdb91d982c9..cc81e91e33f 100644 --- a/boards/arm/stm32/nucleo-f446re/scripts/f446re.ld +++ b/boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/scripts/f446re.ld + * boards/arm/stm32f4/nucleo-f446re/scripts/f446re.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt rename to boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt index f9d569a51e9..25458b16ff5 100644 --- a/boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt +++ b/boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-f446re/src/CMakeLists.txt +# boards/arm/stm32f4/nucleo-f446re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f446re/src/Make.defs b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f446re/src/Make.defs rename to boards/arm/stm32f4/nucleo-f446re/src/Make.defs index 968930b9767..f861a66574e 100644 --- a/boards/arm/stm32/nucleo-f446re/src/Make.defs +++ b/boards/arm/stm32f4/nucleo-f446re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f446re/src/Make.defs +# boards/arm/stm32f4/nucleo-f446re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h rename to boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h index 9510bade876..d3e51ce12cc 100644 --- a/boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h +++ b/boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/nucleo-f446re.h + * boards/arm/stm32f4/nucleo-f446re/src/nucleo-f446re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_adc.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c index 5ae9b9dc8ef..a39c53c93c5 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_adc.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_adc.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c index 8e78f8d1adb..4027f6b9258 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ajoystick.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ajoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c index 5ef67f5e802..ab223ac8a52 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_autoleds.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_boot.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c index a3af05f0527..9ac3db6e971 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_boot.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_boot.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c index 893fe825102..94dd44f5839 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_bringup.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c index c7e976e49ba..9b267ab7ae7 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_buttons.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_can.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c index dd2c75c98b0..bb052a7c124 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_can.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_can.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c index e0ea15be89f..a41b61f2307 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_cansock.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_dac.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c index 1cb743db573..bb835a90f04 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_dac.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_dac.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_dac.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c index 99857b6aa01..047dca4ffa0 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_foc_ihm08m1.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_foc_ihm08m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c index 43ceabb8ca3..46fba657f50 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_gpio.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c index 435ba03a612..59668522820 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_ili9225.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_ili9225.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c index 9279bbe6630..e091f026a71 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_pwm.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h similarity index 97% rename from boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h index edb106e917d..fa4e75ddadd 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs.h + * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c index 97b4fd238c9..f1fe6d08062 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_romfs_initialize.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_romfs_initialize.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-f446re/src/stm32_spi.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c index e713d51ed0c..65b9768161f 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_spi.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_spi.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c rename to boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c index 4a75e98c496..8a2c4d80797 100644 --- a/boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c +++ b/boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f446re/src/stm32_userleds.c + * boards/arm/stm32f4/nucleo-f446re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/emw3162/CMakeLists.txt b/boards/arm/stm32f4/odrive36/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/emw3162/CMakeLists.txt rename to boards/arm/stm32f4/odrive36/CMakeLists.txt index f31385e8a77..61c57407acd 100644 --- a/boards/arm/stm32/emw3162/CMakeLists.txt +++ b/boards/arm/stm32f4/odrive36/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/emw3162/CMakeLists.txt +# boards/arm/stm32f4/odrive36/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/odrive36/Kconfig b/boards/arm/stm32f4/odrive36/Kconfig similarity index 100% rename from boards/arm/stm32/odrive36/Kconfig rename to boards/arm/stm32f4/odrive36/Kconfig diff --git a/boards/arm/stm32/odrive36/configs/nsh/defconfig b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/odrive36/configs/nsh/defconfig rename to boards/arm/stm32f4/odrive36/configs/nsh/defconfig index bd3b6e49f09..fd7a87f012f 100644 --- a/boards/arm/stm32/odrive36/configs/nsh/defconfig +++ b/boards/arm/stm32f4/odrive36/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="odrive36" CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/odrive36/configs/usbnsh/defconfig rename to boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig index d216eecfd45..0ce1ca15d65 100644 --- a/boards/arm/stm32/odrive36/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/odrive36/configs/usbnsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="odrive36" CONFIG_ARCH_BOARD_ODRIVE36=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/odrive36/include/board.h b/boards/arm/stm32f4/odrive36/include/board.h similarity index 99% rename from boards/arm/stm32/odrive36/include/board.h rename to boards/arm/stm32f4/odrive36/include/board.h index 87d431fa5c4..88d42164eaf 100644 --- a/boards/arm/stm32/odrive36/include/board.h +++ b/boards/arm/stm32f4/odrive36/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/include/board.h + * boards/arm/stm32f4/odrive36/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/scripts/Make.defs b/boards/arm/stm32f4/odrive36/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/omnibusf4/scripts/Make.defs rename to boards/arm/stm32f4/odrive36/scripts/Make.defs index fb493131e67..afe58161611 100644 --- a/boards/arm/stm32/omnibusf4/scripts/Make.defs +++ b/boards/arm/stm32f4/odrive36/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/omnibusf4/scripts/Make.defs +# boards/arm/stm32f4/odrive36/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -25,6 +25,7 @@ include $(TOPDIR)/tools/Config.mk include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs LDSCRIPT = ld.script + ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 diff --git a/boards/arm/stm32/odrive36/scripts/ld.script b/boards/arm/stm32f4/odrive36/scripts/ld.script similarity index 98% rename from boards/arm/stm32/odrive36/scripts/ld.script rename to boards/arm/stm32f4/odrive36/scripts/ld.script index 7e28d654434..e96bd2dde2a 100644 --- a/boards/arm/stm32/odrive36/scripts/ld.script +++ b/boards/arm/stm32f4/odrive36/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/scripts/ld.script + * boards/arm/stm32f4/odrive36/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/CMakeLists.txt b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/odrive36/src/CMakeLists.txt rename to boards/arm/stm32f4/odrive36/src/CMakeLists.txt index fb8dbb343df..3cb279a2f72 100644 --- a/boards/arm/stm32/odrive36/src/CMakeLists.txt +++ b/boards/arm/stm32f4/odrive36/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/odrive36/src/CMakeLists.txt +# boards/arm/stm32f4/odrive36/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/odrive36/src/Make.defs b/boards/arm/stm32f4/odrive36/src/Make.defs similarity index 96% rename from boards/arm/stm32/odrive36/src/Make.defs rename to boards/arm/stm32f4/odrive36/src/Make.defs index 4074cab81c5..1b8f5678a46 100644 --- a/boards/arm/stm32/odrive36/src/Make.defs +++ b/boards/arm/stm32f4/odrive36/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/odrive36/src/Make.defs +# boards/arm/stm32f4/odrive36/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/odrive36/src/odrive.h b/boards/arm/stm32f4/odrive36/src/odrive.h similarity index 99% rename from boards/arm/stm32/odrive36/src/odrive.h rename to boards/arm/stm32f4/odrive36/src/odrive.h index c8de89d3b2a..22d37671a3d 100644 --- a/boards/arm/stm32/odrive36/src/odrive.h +++ b/boards/arm/stm32f4/odrive36/src/odrive.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/odrive.h + * boards/arm/stm32f4/odrive36/src/odrive.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/stm32_boot.c b/boards/arm/stm32f4/odrive36/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/odrive36/src/stm32_boot.c rename to boards/arm/stm32f4/odrive36/src/stm32_boot.c index bb3bb54f71f..8d0b0145672 100644 --- a/boards/arm/stm32/odrive36/src/stm32_boot.c +++ b/boards/arm/stm32f4/odrive36/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_boot.c + * boards/arm/stm32f4/odrive36/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/stm32_bringup.c b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/odrive36/src/stm32_bringup.c rename to boards/arm/stm32f4/odrive36/src/stm32_bringup.c index ab2bb6f29b8..23a07ac524b 100644 --- a/boards/arm/stm32/odrive36/src/stm32_bringup.c +++ b/boards/arm/stm32f4/odrive36/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_bringup.c + * boards/arm/stm32f4/odrive36/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/stm32_foc.c b/boards/arm/stm32f4/odrive36/src/stm32_foc.c similarity index 99% rename from boards/arm/stm32/odrive36/src/stm32_foc.c rename to boards/arm/stm32f4/odrive36/src/stm32_foc.c index 7107a31b61a..8e3ee200013 100644 --- a/boards/arm/stm32/odrive36/src/stm32_foc.c +++ b/boards/arm/stm32f4/odrive36/src/stm32_foc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_foc.c + * boards/arm/stm32f4/odrive36/src/stm32_foc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/stm32_spi.c b/boards/arm/stm32f4/odrive36/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/odrive36/src/stm32_spi.c rename to boards/arm/stm32f4/odrive36/src/stm32_spi.c index dd3c358b070..1e462af7a33 100644 --- a/boards/arm/stm32/odrive36/src/stm32_spi.c +++ b/boards/arm/stm32f4/odrive36/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_spi.c + * boards/arm/stm32f4/odrive36/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/odrive36/src/stm32_usb.c b/boards/arm/stm32f4/odrive36/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/odrive36/src/stm32_usb.c rename to boards/arm/stm32f4/odrive36/src/stm32_usb.c index 6b622e0768b..d3f53924d0c 100644 --- a/boards/arm/stm32/odrive36/src/stm32_usb.c +++ b/boards/arm/stm32f4/odrive36/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/odrive36/src/stm32_usb.c + * boards/arm/stm32f4/odrive36/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt new file mode 100644 index 00000000000..389002b8fac --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-e407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-e407/Kconfig b/boards/arm/stm32f4/olimex-stm32-e407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-e407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-e407/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig index 1aa6e086128..0234ae05eba 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/bmp180/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/bmp180/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig index a4ec3de1aec..7c870afe0d1 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/dac/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/dac/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig index ecab558ba8a..67d4415b193 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/discover/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/discover/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig index 524514c10a5..c945c4e776b 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/ina219/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/ina219/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig index 82866611578..44eab998857 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-6lowpan/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig index ce4bcf2897c..1f65505de8f 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/mrf24j40-mac/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/mrf24j40-mac/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig index afcfaffe6bf..40f0c41a88e 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/netnsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/netnsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig index 221b5529d60..0dd7bf92b27 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/nsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig index 3c53e107b14..bd9d1caa9a8 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/telnetd/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/telnetd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig index f8bfe6f3aba..578b077e1ba 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/timer/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/timer/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig index 219c9d105fa..9cfbc790575 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig rename to boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig index ef871f1e02f..05748b1f5ee 100644 --- a/boards/arm/stm32/olimex-stm32-e407/configs/webserver/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-e407/configs/webserver/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-e407" CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-e407/include/board.h b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/include/board.h rename to boards/arm/stm32f4/olimex-stm32-e407/include/board.h index 2ea3adb4e42..a12b129b4dd 100644 --- a/boards/arm/stm32/olimex-stm32-e407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-e407/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/include/board.h + * boards/arm/stm32f4/olimex-stm32-e407/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs index 4d7247871dc..884d70b6944 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-e407/scripts/Make.defs +# boards/arm/stm32f4/olimex-stm32-e407/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld index 654c8e73ab5..283be36be0f 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407ze.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407ze.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld rename to boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld index 3760d7df201..f0bd2b22774 100644 --- a/boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld +++ b/boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/scripts/f407zg.ld + * boards/arm/stm32f4/olimex-stm32-e407/scripts/f407zg.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt rename to boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt index 152d38216dd..c3ee8a36e66 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/src/CMakeLists.txt +# boards/arm/stm32f4/olimex-stm32-e407/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/src/Make.defs rename to boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs index e5b1f17edc3..84b3dce9a78 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-e407/src/Make.defs +# boards/arm/stm32f4/olimex-stm32-e407/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h rename to boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h index 7d1d5064417..ee640dbc99d 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/olimex-stm32-e407.h + * boards/arm/stm32f4/olimex-stm32-e407/src/olimex-stm32-e407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include "stm32.h" diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c index f97001b1243..7796617d96b 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_adc.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c index 89766c7191e..d58f96ed9e9 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_autoleds.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c index 9c52967acfc..b9bc201270e 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_boot.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c index 5636dad2618..6dab2b65954 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_bringup.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c index 8964bd3c7b4..09c257fd407 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_buttons.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c index 468129ff98d..2550c1b3f14 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_can.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c index b98658b4eb0..f553f6d94b4 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2019 Acutronics Robotics All rights reserved. diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c index 7659f5432a7..3baadf6977c 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_mrf24j40.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c index 8f81e1556a2..c188a6abe7e 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c index 5bc17c864d0..8d696f1f725 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_timer.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_timer.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c index 4df415385ef..29725ddce93 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_usb.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c rename to boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c index d9e198ee199..b4509067921 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c +++ b/boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-e407/src/stm32_userleds.c + * boards/arm/stm32f4/olimex-stm32-e407/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt new file mode 100644 index 00000000000..8f277b475ed --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h405/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/Kconfig b/boards/arm/stm32f4/olimex-stm32-h405/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h405/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h405/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig index 56300440f6b..04484f5b989 100644 --- a/boards/arm/stm32/olimex-stm32-h405/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-h405/configs/usbnsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-h405" CONFIG_ARCH_BOARD_OLIMEX_STM32H405=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-h405/include/board.h b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-h405/include/board.h rename to boards/arm/stm32f4/olimex-stm32-h405/include/board.h index 81bdf242002..139fac64fa5 100644 --- a/boards/arm/stm32/olimex-stm32-h405/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-h405/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/include/board.h + * boards/arm/stm32f4/olimex-stm32-h405/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs rename to boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs index 9aaebcbad7a..f9d445c42f7 100644 --- a/boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p207/scripts/Make.defs +# boards/arm/stm32f4/olimex-stm32-h405/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/scripts/ld.script rename to boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script index 37a944a3efb..3bf301337f5 100644 --- a/boards/arm/stm32/olimex-stm32-h405/scripts/ld.script +++ b/boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/scripts/ld.script + * boards/arm/stm32f4/olimex-stm32-h405/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt rename to boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt index 98fcae67692..5c6283a1d12 100644 --- a/boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/src/CMakeLists.txt +# boards/arm/stm32f4/olimex-stm32-h405/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-h405/src/Make.defs rename to boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs index 82df67a1c2d..edf6087d9fd 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-h405/src/Make.defs +# boards/arm/stm32f4/olimex-stm32-h405/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h rename to boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h index 06359cc80bd..610c2384d5c 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/olimex-stm32-h405.h + * boards/arm/stm32f4/olimex-stm32-h405/src/olimex-stm32-h405.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c index f741f3255f9..6415a54736b 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_adc.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c index 7dc946d460e..2c131bdac98 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_autoleds.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c index f7b9a5410e3..c030d22076a 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_boot.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c index 5a2e348ea2e..8f180773eb7 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_buttons.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c index 64bbe3f5b0c..44529b9f1ef 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_can.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c index ce10acef664..c6418591044 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_usb.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c rename to boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c index 8b805929542..1662368f1a3 100644 --- a/boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c +++ b/boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h405/src/stm32_userleds.c + * boards/arm/stm32f4/olimex-stm32-h405/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt new file mode 100644 index 00000000000..8bbac202e6f --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-h407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/Kconfig b/boards/arm/stm32f4/olimex-stm32-h407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-h407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-h407/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig index 37c7caa077f..d1ceb8ccdc7 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-h407" CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig similarity index 97% rename from boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig rename to boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig index ffecc92a539..1c67edfa136 100644 --- a/boards/arm/stm32/olimex-stm32-h407/configs/nsh_uext/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-h407/configs/nsh_uext/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-h407" CONFIG_ARCH_BOARD_OLIMEX_STM32H407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-h407/include/board.h b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-h407/include/board.h rename to boards/arm/stm32f4/olimex-stm32-h407/include/board.h index e585d6a451d..231db8e1865 100644 --- a/boards/arm/stm32/olimex-stm32-h407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-h407/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/include/board.h + * boards/arm/stm32f4/olimex-stm32-h407/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs new file mode 100644 index 00000000000..e158e90e0f3 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/olimex-stm32-h407/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/scripts/ld.script rename to boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script index 2d0c8e0704f..5fc191cd18c 100644 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/ld.script +++ b/boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/scripts/ld.script + * boards/arm/stm32f4/olimex-stm32-h407/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt rename to boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt index 4f687f840f7..51a4ddbada4 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/src/CMakeLists.txt +# boards/arm/stm32f4/olimex-stm32-h407/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs similarity index 97% rename from boards/arm/stm32/olimex-stm32-h407/src/Make.defs rename to boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs index 9e3959c58c9..7fd882bf3aa 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-h407/src/Make.defs +# boards/arm/stm32f4/olimex-stm32-h407/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h rename to boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h index 5fe28b34fab..bb73d19691f 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/olimex-stm32-h407.h + * boards/arm/stm32f4/olimex-stm32-h407/src/olimex-stm32-h407.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c index 6ec856172e3..1e6c8c43807 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_adc.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c index 8b8236d5ea9..6c9fa1b273f 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_autoleds.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c index a2f2c02ed66..63eb2232eb3 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_boot.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c index 7a4e99655bd..83932835b4b 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_bringup.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c index f8eefa4d76f..2c8c1b3b490 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_buttons.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c index c9cc0fc2678..3953ecafb56 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_can.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c index 7752b2a054d..e8c8fda4baa 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_sdio.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_sdio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c index 2da446dbe07..fefb1776b45 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_usb.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c rename to boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c index 7f7b3162044..807ad57522d 100644 --- a/boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c +++ b/boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-h407/src/stm32_userleds.c + * boards/arm/stm32f4/olimex-stm32-h407/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt new file mode 100644 index 00000000000..03081b159c4 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/olimex-stm32-p407/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/Kconfig b/boards/arm/stm32f4/olimex-stm32-p407/Kconfig similarity index 100% rename from boards/arm/stm32/olimex-stm32-p407/Kconfig rename to boards/arm/stm32f4/olimex-stm32-p407/Kconfig diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig index 01fefc9cf1e..c4aa5630fee 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/audio/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/audio/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig index 47c8e24b497..c2568a49d5a 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/dhtxx/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/dhtxx/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig index f835cb6764b..1474e1bd565 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/hidkbd/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/hidkbd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs rename to boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs index b8256a14399..9c06da91d4e 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kelf/Make.defs +# boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig similarity index 94% rename from boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig index e70543e3326..15ba73092b0 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kelf/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kelf/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -37,7 +37,7 @@ CONFIG_LIBC_ENVPATH=y CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_MM_REGIONS=2 CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" CONFIG_PATH_INITIAL="/mnt/vfat" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs rename to boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs index 03291ccbb78..22979d8184d 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/kmodule/Make.defs +# boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig similarity index 93% rename from boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig index 39ae6fde6a8..1026bb269dd 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/kmodule/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/kmodule/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -34,7 +34,7 @@ CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_MM_REGIONS=2 CONFIG_MODULE=y CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs rename to boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs index e933d297972..f9a6444eca0 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/configs/knsh/Make.defs +# boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig similarity index 93% rename from boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig index 1d27f2abdbf..40beb1054dc 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/knsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/knsh/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -35,7 +35,7 @@ CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/olimex-stm32-p407/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/olimex-stm32-p407/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=131072 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig similarity index 97% rename from boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig index fbcc984f58e..a9a50a224ef 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/module/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/module/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig index 15d2916f721..6dc5ccbb18b 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/mqttc/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/mqttc/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig index 120b8f3bb36..20dfd48105d 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/nsh/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig rename to boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig index 4843b097e6a..d14e46b5dd7 100644 --- a/boards/arm/stm32/olimex-stm32-p407/configs/zmodem/defconfig +++ b/boards/arm/stm32f4/olimex-stm32-p407/configs/zmodem/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="olimex-stm32-p407" CONFIG_ARCH_BOARD_OLIMEX_STM32P407=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407ZG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/olimex-stm32-p407/include/board.h b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/include/board.h rename to boards/arm/stm32f4/olimex-stm32-p407/include/board.h index 92a26895aad..e1d157fa0dd 100644 --- a/boards/arm/stm32/olimex-stm32-p407/include/board.h +++ b/boards/arm/stm32f4/olimex-stm32-p407/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/include/board.h + * boards/arm/stm32f4/olimex-stm32-p407/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/kernel/Makefile rename to boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile index 4590512f134..e056219e025 100644 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/Makefile +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/kernel/Makefile +# boards/arm/stm32f4/olimex-stm32-p407/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c rename to boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c index 9741858be58..db4079eff62 100644 --- a/boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/kernel/stm32_userspace.c + * boards/arm/stm32f4/olimex-stm32-p407/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs rename to boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs index c617c730ec8..086726dad0f 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/scripts/Make.defs +# boards/arm/stm32f4/olimex-stm32-p407/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld rename to boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld index 75ab5f6cdf4..577a9d8f2df 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/flash.ld + * boards/arm/stm32f4/olimex-stm32-p407/scripts/flash.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld new file mode 100644 index 00000000000..8eab527b056 --- /dev/null +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld @@ -0,0 +1,101 @@ +/**************************************************************************** + * boards/arm/stm32f4/olimex-stm32-p407/scripts/kernel-space.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld rename to boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld index f877525caa1..a636ac8e99f 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/memory.ld + * boards/arm/stm32f4/olimex-stm32-p407/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld rename to boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld index c0c286e10c9..97ddb090ed1 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld +++ b/boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/user-space.ld + * boards/arm/stm32f4/olimex-stm32-p407/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt rename to boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt index f10df30fa1f..1ba829e0eee 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/src/CMakeLists.txt +# boards/arm/stm32f4/olimex-stm32-p407/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs similarity index 97% rename from boards/arm/stm32/olimex-stm32-p407/src/Make.defs rename to boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs index 8d0d261b5fb..490a6059847 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/Make.defs +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/olimex-stm32-p407/src/Make.defs +# boards/arm/stm32f4/olimex-stm32-p407/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h rename to boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h index 8847489d520..a158aaf9af6 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/olimex-stm32-p407.h + * boards/arm/stm32f4/olimex-stm32-p407/src/olimex-stm32-p407.h * * SPDX-License-Identifier: Apache-2.0 * @@ -31,7 +31,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c index 37fddf81d0e..0278cefdd26 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_adc.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c index a77daaf0ea9..8ac94043160 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_autoleds.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c index 77a521816a5..96f423fd65d 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_boot.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c index af02950de45..23aef9764d5 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_bringup.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c index a17716582e1..7e53c997dee 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_buttons.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c index 71bc50e3bc6..abb3d539c72 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_can.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c index fdef20aabf0..caebdff338f 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_cs4344.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_cs4344.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c index 4f96e0bff41..191399950d2 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_djoystick.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_djoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c index 75b6ec8f972..d7777549c85 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_spi.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c index d2d7a1c2608..0e3a7159be3 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_sram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c index 9e74c73f278..3ee27f56b0a 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_st7735.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c index a21739968a7..63700d43db5 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_usb.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c rename to boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c index 2a7ceec92a3..01b7c08cead 100644 --- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c +++ b/boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/src/stm32_userleds.c + * boards/arm/stm32f4/olimex-stm32-p407/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/omnibusf4/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt new file mode 100644 index 00000000000..b1118af49bb --- /dev/null +++ b/boards/arm/stm32f4/omnibusf4/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/omnibusf4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/Kconfig b/boards/arm/stm32f4/omnibusf4/Kconfig similarity index 100% rename from boards/arm/stm32/omnibusf4/Kconfig rename to boards/arm/stm32f4/omnibusf4/Kconfig diff --git a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig similarity index 99% rename from boards/arm/stm32/omnibusf4/configs/nsh/defconfig rename to boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig index a092cd5ce1e..848febabe21 100644 --- a/boards/arm/stm32/omnibusf4/configs/nsh/defconfig +++ b/boards/arm/stm32f4/omnibusf4/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="omnibusf4" CONFIG_ARCH_BOARD_OMNIBUSF4=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F405RG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/omnibusf4/include/board.h b/boards/arm/stm32f4/omnibusf4/include/board.h similarity index 99% rename from boards/arm/stm32/omnibusf4/include/board.h rename to boards/arm/stm32f4/omnibusf4/include/board.h index 89ac84283a1..3fd9a21b8f2 100644 --- a/boards/arm/stm32/omnibusf4/include/board.h +++ b/boards/arm/stm32f4/omnibusf4/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/include/board.h + * boards/arm/stm32f4/omnibusf4/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/kernel/Makefile b/boards/arm/stm32f4/omnibusf4/kernel/Makefile similarity index 98% rename from boards/arm/stm32/omnibusf4/kernel/Makefile rename to boards/arm/stm32f4/omnibusf4/kernel/Makefile index 75b08bc56a6..9ccee530286 100644 --- a/boards/arm/stm32/omnibusf4/kernel/Makefile +++ b/boards/arm/stm32f4/omnibusf4/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/omnibusf4/kernel/Makefile +# boards/arm/stm32f4/omnibusf4/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c rename to boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c index 4f26f3b6fa7..77bf45552f2 100644 --- a/boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/kernel/stm32_userspace.c + * boards/arm/stm32f4/omnibusf4/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32_tiny/scripts/Make.defs b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32_tiny/scripts/Make.defs rename to boards/arm/stm32f4/omnibusf4/scripts/Make.defs index 3093bfc93ee..f5c23b2b86c 100644 --- a/boards/arm/stm32/stm32_tiny/scripts/Make.defs +++ b/boards/arm/stm32f4/omnibusf4/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32_tiny/scripts/Make.defs +# boards/arm/stm32f4/omnibusf4/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld similarity index 98% rename from boards/arm/stm32/omnibusf4/scripts/kernel-space.ld rename to boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld index 05813d38015..6c45eaa4e84 100644 --- a/boards/arm/stm32/omnibusf4/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/kernel-space.ld + * boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/scripts/ld.script b/boards/arm/stm32f4/omnibusf4/scripts/ld.script similarity index 98% rename from boards/arm/stm32/omnibusf4/scripts/ld.script rename to boards/arm/stm32f4/omnibusf4/scripts/ld.script index a4e200f91e9..947c33103d2 100644 --- a/boards/arm/stm32/omnibusf4/scripts/ld.script +++ b/boards/arm/stm32f4/omnibusf4/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/ld.script + * boards/arm/stm32f4/omnibusf4/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/scripts/memory.ld b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/omnibusf4/scripts/memory.ld rename to boards/arm/stm32f4/omnibusf4/scripts/memory.ld index ff462c1e469..196d3591fff 100644 --- a/boards/arm/stm32/omnibusf4/scripts/memory.ld +++ b/boards/arm/stm32f4/omnibusf4/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/memory.ld + * boards/arm/stm32f4/omnibusf4/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -34,7 +34,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/omnibusf4/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/omnibusf4/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/omnibusf4/scripts/user-space.ld b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/omnibusf4/scripts/user-space.ld rename to boards/arm/stm32f4/omnibusf4/scripts/user-space.ld index 83c52fe4f9f..b50708ae317 100644 --- a/boards/arm/stm32/omnibusf4/scripts/user-space.ld +++ b/boards/arm/stm32f4/omnibusf4/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/scripts/user-space.ld + * boards/arm/stm32f4/omnibusf4/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/omnibusf4/src/CMakeLists.txt rename to boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt index 9be173575b5..531c7feb5d6 100644 --- a/boards/arm/stm32/omnibusf4/src/CMakeLists.txt +++ b/boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/omnibusf4/src/CMakeLists.txt +# boards/arm/stm32f4/omnibusf4/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/omnibusf4/src/Make.defs b/boards/arm/stm32f4/omnibusf4/src/Make.defs similarity index 97% rename from boards/arm/stm32/omnibusf4/src/Make.defs rename to boards/arm/stm32f4/omnibusf4/src/Make.defs index 6fa1d9b08b8..b0c74f55cde 100644 --- a/boards/arm/stm32/omnibusf4/src/Make.defs +++ b/boards/arm/stm32f4/omnibusf4/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/omnibusf4/src/Make.defs +# boards/arm/stm32f4/omnibusf4/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/omnibusf4/src/omnibusf4.h b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h similarity index 98% rename from boards/arm/stm32/omnibusf4/src/omnibusf4.h rename to boards/arm/stm32f4/omnibusf4/src/omnibusf4.h index d401a52253d..1eb7d9667cb 100644 --- a/boards/arm/stm32/omnibusf4/src/omnibusf4.h +++ b/boards/arm/stm32f4/omnibusf4/src/omnibusf4.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/omnibusf4.h + * boards/arm/stm32f4/omnibusf4/src/omnibusf4.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/omnibusf4/src/stm32_boot.c b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_boot.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_boot.c index 651df187d81..1eb7e82d4ba 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_boot.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_boot.c + * boards/arm/stm32f4/omnibusf4/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/omnibusf4/src/stm32_bringup.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c index bbda6f831f8..59aa712f47f 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_bringup.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_bringup.c + * boards/arm/stm32f4/omnibusf4/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_idle.c b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c similarity index 99% rename from boards/arm/stm32/omnibusf4/src/stm32_idle.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_idle.c index a21bc28cff6..ae1ed824146 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_idle.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_idle.c + * boards/arm/stm32f4/omnibusf4/src/stm32_idle.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_ioctl.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c index c7d7674e3bf..c744806de82 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_ioctl.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_ioctl.c + * boards/arm/stm32f4/omnibusf4/src/stm32_ioctl.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_max7456.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c index 58413d89ee7..05c90434478 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_max7456.c + * boards/arm/stm32f4/omnibusf4/src/stm32_max7456.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c index 2d6e436022a..2459813e68b 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mmcsd.c + * boards/arm/stm32f4/omnibusf4/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c index 9d79cf9790e..c2957c2a7e1 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c + * boards/arm/stm32f4/omnibusf4/src/stm32_mpu6000.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c similarity index 96% rename from boards/arm/stm32/omnibusf4/src/stm32_netinit.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c index 459c12b540f..3360c835506 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_netinit.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_netinit.c + * boards/arm/stm32f4/omnibusf4/src/stm32_netinit.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_pm.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_pm.c index 1192f27edcc..dfe132e9f78 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_pm.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pm.c + * boards/arm/stm32f4/omnibusf4/src/stm32_pm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_pwm.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c index 110d82016bb..41770c035b6 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_pwm.c + * boards/arm/stm32f4/omnibusf4/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_reset.c b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c similarity index 97% rename from boards/arm/stm32/omnibusf4/src/stm32_reset.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_reset.c index 9ce6cdc4963..4d6ec55831d 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_reset.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_reset.c + * boards/arm/stm32f4/omnibusf4/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_romfs.h rename to boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h index a626fd2ac27..b1376c031e7 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs.h +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs.h + * boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. diff --git a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c index 3111816d8ef..8c5d8069a95 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c + * boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. diff --git a/boards/arm/stm32/omnibusf4/src/stm32_spi.c b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/omnibusf4/src/stm32_spi.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_spi.c index 525a8781df7..91a4916ca6f 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_spi.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_spi.c + * boards/arm/stm32f4/omnibusf4/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_timer.c b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c similarity index 97% rename from boards/arm/stm32/omnibusf4/src/stm32_timer.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_timer.c index 0d6e5b1b5d3..c0b13b8a0a2 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_timer.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_timer.c + * boards/arm/stm32f4/omnibusf4/src/stm32_timer.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_uid.c b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c similarity index 98% rename from boards/arm/stm32/omnibusf4/src/stm32_uid.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_uid.c index 892821fa453..5ea001248f0 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_uid.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_uid.c + * boards/arm/stm32f4/omnibusf4/src/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usb.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/omnibusf4/src/stm32_usb.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_usb.c index 94f60081162..d229c176ce9 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_usb.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usb.c + * boards/arm/stm32f4/omnibusf4/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c index b3c093ab6a1..5fb5e112497 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_usbmsc.c + * boards/arm/stm32f4/omnibusf4/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/omnibusf4/src/stm32_userleds.c rename to boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c index 2d624f27610..ecfafda5b1f 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_userleds.c +++ b/boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/omnibusf4/src/stm32_userleds.c + * boards/arm/stm32f4/omnibusf4/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt new file mode 100644 index 00000000000..efa9246cf95 --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm3240g-eval/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/Kconfig b/boards/arm/stm32f4/stm3240g-eval/Kconfig similarity index 100% rename from boards/arm/stm32/stm3240g-eval/Kconfig rename to boards/arm/stm32f4/stm3240g-eval/Kconfig diff --git a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig index 34b5600ff35..f6c6f566907 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/dhcpd/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/dhcpd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/discover/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig index c44d9a0e2bd..616c7e441cb 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/discover/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/discover/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/fb/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig index 5dc598e063b..7658129cd2b 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/fb/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/fb/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs similarity index 96% rename from boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs rename to boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs index c8ecd22e21e..bdadecf8603 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3240g-eval/configs/knxwm/Make.defs +# boards/arm/stm32f4/stm3240g-eval/configs/knxwm/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig similarity index 96% rename from boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig index 203da50b7bb..8e782525897 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/knxwm/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/knxwm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -70,7 +70,7 @@ CONFIG_NXWM_TASKBAR_VSPACING=4 CONFIG_NX_BLOCKING=y CONFIG_NX_KBD=y CONFIG_NX_XYINPUT_TOUCHSCREEN=y -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm3240g-eval/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm3240g-eval/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=196608 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig index 01e8df44d21..1f3385947f2 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nettest/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nettest/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig index b10f9d1ad78..80a98d96abb 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig index 1020cc7ac97..005e9e04a08 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nsh2/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nsh2/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig similarity index 99% rename from boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig index d1fbb36a5eb..25740c07a6c 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxterm/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxterm/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig similarity index 99% rename from boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig index 50139a990d9..9104b7cd84a 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/nxwm/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/nxwm/defconfig @@ -17,7 +17,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig index f97d570a56f..fbe59922f17 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/telnetd/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/telnetd/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig index ac283d015d3..28c7c0ac956 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/webserver/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/webserver/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig similarity index 98% rename from boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig rename to boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig index 23c950db80b..530c00545a4 100644 --- a/boards/arm/stm32/stm3240g-eval/configs/xmlrpc/defconfig +++ b/boards/arm/stm32f4/stm3240g-eval/configs/xmlrpc/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm3240g-eval" CONFIG_ARCH_BOARD_STM3240G_EVAL=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407IG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm3240g-eval/include/board.h b/boards/arm/stm32f4/stm3240g-eval/include/board.h similarity index 99% rename from boards/arm/stm32/stm3240g-eval/include/board.h rename to boards/arm/stm32f4/stm3240g-eval/include/board.h index 895059dfce0..702e2d93d90 100644 --- a/boards/arm/stm32/stm3240g-eval/include/board.h +++ b/boards/arm/stm32f4/stm3240g-eval/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/include/board.h + * boards/arm/stm32f4/stm3240g-eval/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/kernel/Makefile b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile similarity index 98% rename from boards/arm/stm32/stm3240g-eval/kernel/Makefile rename to boards/arm/stm32f4/stm3240g-eval/kernel/Makefile index 3aba5389f39..f89e2210f73 100644 --- a/boards/arm/stm32/stm3240g-eval/kernel/Makefile +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3240g-eval/kernel/Makefile +# boards/arm/stm32f4/stm3240g-eval/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c rename to boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c index f50a59be452..ca655d1ada4 100644 --- a/boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/kernel/stm32_userspace.c + * boards/arm/stm32f4/stm3240g-eval/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs new file mode 100644 index 00000000000..9f8df9bce9c --- /dev/null +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm3240g-eval/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld rename to boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld index 43a2313798f..7712a4771a1 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/kernel-space.ld + * boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/scripts/ld.script b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm3240g-eval/scripts/ld.script rename to boards/arm/stm32f4/stm3240g-eval/scripts/ld.script index 250db269b1f..a4987bf37e0 100644 --- a/boards/arm/stm32/stm3240g-eval/scripts/ld.script +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/ld.script + * boards/arm/stm32f4/stm3240g-eval/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/stm3240g-eval/scripts/memory.ld rename to boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld index 7eeff47560d..4f997fbe4f9 100644 --- a/boards/arm/stm32/stm3240g-eval/scripts/memory.ld +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/memory.ld + * boards/arm/stm32f4/stm3240g-eval/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -34,7 +34,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 256Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm3240g-eval/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/stm3240g-eval/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/stm3240g-eval/scripts/user-space.ld rename to boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld index 80a6572aa64..fd7922b7737 100644 --- a/boards/arm/stm32/stm3240g-eval/scripts/user-space.ld +++ b/boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/scripts/user-space.ld + * boards/arm/stm32f4/stm3240g-eval/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt rename to boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt index c8c5aa4f724..1969d7755e5 100644 --- a/boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm3240g-eval/src/CMakeLists.txt +# boards/arm/stm32f4/stm3240g-eval/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3240g-eval/src/Make.defs b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm3240g-eval/src/Make.defs rename to boards/arm/stm32f4/stm3240g-eval/src/Make.defs index 04d1ecfdd0b..529bccfba93 100644 --- a/boards/arm/stm32/stm3240g-eval/src/Make.defs +++ b/boards/arm/stm32f4/stm3240g-eval/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm3240g-eval/src/Make.defs +# boards/arm/stm32f4/stm3240g-eval/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h rename to boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h index b607dc33408..da73e0674a9 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm3240g-eval.h + * boards/arm/stm32f4/stm3240g-eval/src/stm3240g-eval.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_adc.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c index bfeaca3cf33..ec49c4f1225 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_adc.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_adc.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c index fc90a9ad319..d09719923af 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_autoleds.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_boot.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c index 4f59c13c407..f77dac198d8 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_boot.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c index 016041c9190..80e06aa4a9a 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_bringup.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c index 66f45af6837..6f53a11fb24 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_buttons.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_can.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c index 53e357df19c..ec742a605d5 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_can.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_can.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c similarity index 97% rename from boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c index dc9cee810b6..ff9e69d2c0d 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectlcd.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c similarity index 97% rename from boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c index 6f8840bedfb..2ced0277d8f 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_deselectsram.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_deselectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c index dd6d6b4163f..46afe66b928 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_extmem.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c index 8ab6c22e6ad..0bd00dd976b 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c index 2d4e6393779..4182be207e5 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_pwm.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c index c3c854d0320..e8ec7732462 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectlcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c index 7ffe0a673f7..2fd43e8b2fb 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_selectsram.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_spi.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c index c2ca8d2be6b..b14ec2bd659 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_spi.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_spi.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c index 87334017a2f..ec55412bec3 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_stmpe811.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_stmpe811.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm3240g-eval/src/stm32_usb.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c index e09730cee8f..9f7e3c0c97c 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_usb.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c rename to boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c index 61299ea969e..48f0eb96950 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm3240g-eval/src/stm32_userleds.c + * boards/arm/stm32f4/stm3240g-eval/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt new file mode 100644 index 00000000000..ef6c336e422 --- /dev/null +++ b/boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f401rc-rs485/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f401rc-rs485/Kconfig b/boards/arm/stm32f4/stm32f401rc-rs485/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f401rc-rs485/Kconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/Kconfig diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig index 6e22dc02126..18ba4c33634 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/adc/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig index 178a756ab5d..702fd4ebb5f 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/bmp280/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/bmp280/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig index 9c1468d40d2..dfa0032c87b 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/dac/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig index df1e41dab3d..20321b364cd 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig index dcb15b1eb51..9e5dd06e38d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lcd1602/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lcd1602/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig index 9fa82205b31..ab31f55aabe 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/lm75/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig index e911ed96554..71205dd3469 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/max7219/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/max7219/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig index 2359bdf62c1..bd6c560ffa6 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/mfrc522/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/mfrc522/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig index 311c24b5ce4..09aa15441b0 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -22,7 +22,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig index 62e05716167..54650ba01e5 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig index 934fe5937d5..6579a60a223 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig index 0b08c8a1637..6e145c65d59 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/qencoder/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig index 60be3f8d8ef..be5813d65a6 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/rndis/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig index 17e9bcd416a..cd419b48e96 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/sdcard/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig index 3e49da0d35e..d9828a3ad37 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig index 17abb4b5997..303875d809f 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/telnetd/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/telnetd/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig index f1b9b35d2cd..95f8b90b02a 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig index 4604117e6a1..594ab62510e 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig rename to boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig index 0b46c33727a..260bbbe3bf9 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/ws2812/defconfig +++ b/boards/arm/stm32f4/stm32f401rc-rs485/configs/ws2812/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="stm32f401rc-rs485" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F401RC_RS485=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F401RC=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/include/board.h b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/include/board.h rename to boards/arm/stm32f4/stm32f401rc-rs485/include/board.h index 537c0650e1f..4225ee4db74 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/include/board.h +++ b/boards/arm/stm32f4/stm32f401rc-rs485/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/include/board.h + * boards/arm/stm32f4/stm32f401rc-rs485/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs rename to boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs index ac4d6335198..51422c125e6 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/scripts/Make.defs +# boards/arm/stm32f4/stm32f401rc-rs485/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script rename to boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script index 855e00562ce..fc6386990b8 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script +++ b/boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/scripts/ld.script + * boards/arm/stm32f4/stm32f401rc-rs485/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt rename to boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt index bf67263f692..64b46b4813d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt +# boards/arm/stm32f4/stm32f401rc-rs485/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/Make.defs rename to boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs index 122740343ad..04f89e99e4f 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f401rc-rs485/src/Make.defs +# boards/arm/stm32f4/stm32f401rc-rs485/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c index a31a7a7174a..f9140a1421b 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c index 4d37aa0c64f..8cad42b70a2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_at24.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_at24.c * * SPDX-License-Identifier: Apache-2.0 * @@ -94,4 +94,3 @@ int stm32_at24_init(char *path) return OK; } - diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c index dd989cc1f14..1d02e1f7d13 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_autoleds.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c index e4a5038168b..eb622ee8ac4 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c index eaf5642cb8a..61d5448a187 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -31,6 +31,7 @@ #include #include +#include #include #include diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c index f8ac4d7ec25..9ab473a5267 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c index fddefc25ae8..0cfe7d24a67 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_gpio.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c index 929558c3b1c..772a358f7d5 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_hx711.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_hx711.c * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c index f4fe30a4acc..2bb64bfa1a2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c index 876e5b82346..bffad71e473 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_st7735.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_lcd_st7735.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c index 885152e7b33..2579135afcf 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_reset.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c index 9edc36b2a30..5e243092980 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_reset.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_reset.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c index e7e4de29421..959cc8637db 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_sdio.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_sdio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c index ead5b4fcfca..eef9dbcd070 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c similarity index 98% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c index 317d1358bc6..c9ad90a9976 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c index d5d633d8996..506a30b7e79 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c index b0b46ca4075..7b97b71c8ec 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_userleds.c + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h similarity index 99% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h rename to boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h index b8fbec7e25a..f6065bbdb8c 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h +++ b/boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h + * boards/arm/stm32f4/stm32f401rc-rs485/src/stm32f401rc-rs485.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt new file mode 100644 index 00000000000..f4b26f4eddd --- /dev/null +++ b/boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411-minimum/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig b/boards/arm/stm32f4/stm32f411-minimum/Kconfig similarity index 96% rename from boards/arm/stm32/stm32f411-minimum/Kconfig rename to boards/arm/stm32f4/stm32f411-minimum/Kconfig index 43f2f0018b8..44ee6a90407 100644 --- a/boards/arm/stm32/stm32f411-minimum/Kconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/Kconfig @@ -80,7 +80,7 @@ menuconfig STM32F411MINIMUM_GPIO bool "enable gpio subsystem" if STM32F411MINIMUM_GPIO -source "boards/arm/stm32/stm32f411-minimum/Kconfig.gpio" +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio" endif endif diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio b/boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio similarity index 100% rename from boards/arm/stm32/stm32f411-minimum/Kconfig.gpio rename to boards/arm/stm32f4/stm32f411-minimum/Kconfig.gpio diff --git a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig index fd0ea5aa335..f7e74ef5eb1 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/composite/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/composite/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig index d9e14188dee..6d7961ef2fa 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/nsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig index eea54a81ee2..6d7545748b8 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/pwm/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/pwm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig index df31e577207..cadadfaea58 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/rgbled/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/rgbled/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig index 6534f827cf1..d9edd314500 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/spifsnsh/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/spifsnsh/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig rename to boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig index a4b9ef9cb77..825535f8217 100644 --- a/boards/arm/stm32/stm32f411-minimum/configs/usbmsc/defconfig +++ b/boards/arm/stm32f4/stm32f411-minimum/configs/usbmsc/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411-minimum" CONFIG_ARCH_BOARD_STM32F411_MINIMUM=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411CE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411-minimum/include/board.h b/boards/arm/stm32f4/stm32f411-minimum/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/include/board.h rename to boards/arm/stm32f4/stm32f411-minimum/include/board.h index 5d353b961ca..c90a3ade986 100644 --- a/boards/arm/stm32/stm32f411-minimum/include/board.h +++ b/boards/arm/stm32f4/stm32f411-minimum/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/include/board.h + * boards/arm/stm32f4/stm32f411-minimum/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f411-minimum/scripts/Make.defs rename to boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs index 3a41209051d..15e53eadfbd 100644 --- a/boards/arm/stm32/stm32f411-minimum/scripts/Make.defs +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f411-minimum/scripts/Make.defs +# boards/arm/stm32f4/stm32f411-minimum/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld rename to boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld index b5b77c8a49b..58afcc51985 100644 --- a/boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld +++ b/boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/scripts/stm32f411ce.ld + * boards/arm/stm32f4/stm32f411-minimum/scripts/stm32f411ce.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt rename to boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt index 67ae6a038bb..0b5473d5b55 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt +# boards/arm/stm32f4/stm32f411-minimum/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411-minimum/src/Make.defs b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f411-minimum/src/Make.defs rename to boards/arm/stm32f4/stm32f411-minimum/src/Make.defs index a221a572f16..dcda7c66430 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/Make.defs +++ b/boards/arm/stm32f4/stm32f411-minimum/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f411-minimum/src/Make.defs +# boards/arm/stm32f4/stm32f411-minimum/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c index 9846714e8d8..5287975f236 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_autoleds.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c index c37c11bf046..4bc171dc6a8 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_boot.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c index e81aad31989..9264b917c7d 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c index ff186728327..4ccae3e1a4d 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_buttons.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c index 78bd6f5a5b8..88e53ea4840 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_composite.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_composite.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c index 754e624d61a..d7b499aaa79 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_gpio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c similarity index 97% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c index ce88a74bcbf..65db25d28fe 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_hx711.c * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c index 6f7354477ca..284affc8fbb 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_pwm.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c index faaa9e4871b..e142de19b15 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_rgbled.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_rgbled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c index 890f8cc3db2..43347015546 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_spi.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c index 08afc617c0c..ff842eb11b4 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usb.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c index 19084231667..14890201cac 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_usbmsc.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c index 3abebf3e77c..660ef135af9 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_userleds.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c similarity index 98% rename from boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c index 17427b4e926..e2c0ce64a47 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32_w25.c + * boards/arm/stm32f4/stm32f411-minimum/src/stm32_w25.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h index 1942732d682..54b682fa67c 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum-gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h similarity index 99% rename from boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h rename to boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h index 38d62a738ac..fac30d9a1f9 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h +++ b/boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h + * boards/arm/stm32f4/stm32f411-minimum/src/stm32f411-minimum.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt new file mode 100644 index 00000000000..7147e4505e5 --- /dev/null +++ b/boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f411e-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/Kconfig b/boards/arm/stm32f4/stm32f411e-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f411e-disco/Kconfig rename to boards/arm/stm32f4/stm32f411e-disco/Kconfig diff --git a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig rename to boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig index dae6672714d..0a887cdf2dd 100644 --- a/boards/arm/stm32/stm32f411e-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm32f411e-disco/configs/nsh/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f411e-disco" CONFIG_ARCH_BOARD_STM32F411E_DISCO=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F411VE=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f411e-disco/include/board.h b/boards/arm/stm32f4/stm32f411e-disco/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f411e-disco/include/board.h rename to boards/arm/stm32f4/stm32f411e-disco/include/board.h index 903bf73d317..ce8aadff512 100644 --- a/boards/arm/stm32/stm32f411e-disco/include/board.h +++ b/boards/arm/stm32f4/stm32f411e-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/include/board.h + * boards/arm/stm32f4/stm32f411e-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f411e-disco/scripts/Make.defs rename to boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs index 606d070f68d..6442599a8f6 100644 --- a/boards/arm/stm32/stm32f411e-disco/scripts/Make.defs +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f411e-disco/scripts/Make.defs +# boards/arm/stm32f4/stm32f411e-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld rename to boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld index 4f0e398e085..a7ae15bdd1a 100644 --- a/boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld +++ b/boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/scripts/f411ve.ld + * boards/arm/stm32f4/stm32f411e-disco/scripts/f411ve.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt rename to boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt index 9f3433d0cc8..d92b2d6fbc1 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f411e-disco/src/CMakeLists.txt +# boards/arm/stm32f4/stm32f411e-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411e-disco/src/Make.defs b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f411e-disco/src/Make.defs rename to boards/arm/stm32f4/stm32f411e-disco/src/Make.defs index cff6ead802f..d979394c3dd 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/Make.defs +++ b/boards/arm/stm32f4/stm32f411e-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f411e-disco/src/Make.defs +# boards/arm/stm32f4/stm32f411e-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c index 07237023ba4..532620b9c14 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_autoleds.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c index 9aecad9bdee..ba49ba9262d 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c index fe85d312f3e..8d104e05902 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_bringup.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c index ef990dc549b..458b4443786 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_buttons.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c index 83372a115e9..3434d64f9eb 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Gregory Nutt. All rights reserved. diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c index a4b0a2bf774..7a080b42983 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32_userleds.c + * boards/arm/stm32f4/stm32f411e-disco/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h similarity index 99% rename from boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h rename to boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h index 993efb33dd7..625a7d463f3 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h +++ b/boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f411e-disco/src/stm32f411e-disco.h + * boards/arm/stm32f4/stm32f411e-disco/src/stm32f411e-disco.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt new file mode 100644 index 00000000000..581e2ba994a --- /dev/null +++ b/boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32f4/stm32f429i-disco/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/Kconfig b/boards/arm/stm32f4/stm32f429i-disco/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f429i-disco/Kconfig rename to boards/arm/stm32f4/stm32f429i-disco/Kconfig diff --git a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig index 40e510989cc..7a06ad371b5 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/adc/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/adc/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig index 82c861c4e6d..5610e2c3f06 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/bootlogo/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/bootlogo/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig index 2e3dce2e53e..f35ce2450e6 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/extflash/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/extflash/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig index ff349a213b4..e61f766cb1f 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/fb/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/fb/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig index 4982ec9e495..f44bd74c69d 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/gdbstub/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/gdbstub/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig index 207032d4861..24deb19b351 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/highpri/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/highpri/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig index cc548e45b17..dd6fdbb3aab 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lcd/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lcd/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig index 34f00994c65..91927fed122 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/lvgl/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig index 1ab0fba0f4f..fec735c9fa5 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig index 89ff4b37859..de8144a4494 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxhello/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxhello/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig index c3300bb7d34..571440c8d67 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/nxwm/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/nxwm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig index 15ff2c9db50..962af638709 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/ofloader/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/ofloader/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig index c3dc124c4a5..00451cde08c 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/stack/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/stack/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig index 10a6be5de4a..03aff6f4318 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/systemview/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/systemview/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig index 9e9a7617949..7e6ab150d4a 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbmsc/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbmsc/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig rename to boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig index 53447258b17..0a13ff51539 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/stm32f429i-disco/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f429i-disco" CONFIG_ARCH_BOARD_STM32F429I_DISCO=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F429Z=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f429i-disco/include/board.h b/boards/arm/stm32f4/stm32f429i-disco/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/include/board.h rename to boards/arm/stm32f4/stm32f429i-disco/include/board.h index 2bb3b57f0cf..8d06febb0a6 100644 --- a/boards/arm/stm32/stm32f429i-disco/include/board.h +++ b/boards/arm/stm32f4/stm32f429i-disco/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/include/board.h + * boards/arm/stm32f4/stm32f429i-disco/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f429i-disco/scripts/Make.defs rename to boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs index a88280f56b3..5ecd6c7d194 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/Make.defs +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f429i-disco/scripts/Make.defs +# boards/arm/stm32f4/stm32f429i-disco/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld index 38a91fff986..b03d51ac65f 100644 --- a/boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/olimex-stm32-p407/scripts/kernel-space.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -27,7 +27,6 @@ OUTPUT_ARCH(arm) EXTERN(_vectors) ENTRY(_stext) - SECTIONS { .text : { diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/scripts/ld.script rename to boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script index f6fde30fd1e..349f486d473 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ld.script +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ld.script + * boards/arm/stm32f4/stm32f429i-disco/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/nucleo-f429zi/scripts/memory.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld index b1be6243402..75cf8f18e6e 100644 --- a/boards/arm/stm32/nucleo-f429zi/scripts/memory.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-f429zi/scripts/memory.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/stm32f429i-disco/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld index ab7554dc716..10857b3f77c 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/ofloader.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/ofloader.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld rename to boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld index 3ee80c42f46..9830e408057 100644 --- a/boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld +++ b/boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/user-space.ld + * boards/arm/stm32f4/stm32f429i-disco/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt rename to boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt index fa9314f019b..c4b340d84d8 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt +# boards/arm/stm32f4/stm32f429i-disco/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f429i-disco/src/Make.defs b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs similarity index 97% rename from boards/arm/stm32/stm32f429i-disco/src/Make.defs rename to boards/arm/stm32f4/stm32f429i-disco/src/Make.defs index 5b7dd1fcbd2..a5df5de7384 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/Make.defs +++ b/boards/arm/stm32f4/stm32f429i-disco/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f429i-disco/src/Make.defs +# boards/arm/stm32f4/stm32f429i-disco/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c index 45b62589d27..d7a1d4b33be 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_adc.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c index cdc48319a02..be4ca27083e 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_autoleds.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c index deabbc588b5..60fa8e9a75d 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_boot.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c index a00da867c59..5b59f2dcf00 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c index 314d14da7c9..80439363c1a 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_buttons.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_can.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c index 68464531cc5..565420489dc 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_can.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c index c74f2bb1ce9..d0f2faf088d 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c index 1a40a0bb803..66ec057d07c 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_highpri.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_highpri.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c index 2daac96d2b7..16b818e188a 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_idle.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c index 2171493eb4b..84c83f2113f 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_ili93414ws.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_ili93414ws.c * * SPDX-License-Identifier: Apache-2.0 * @@ -57,7 +57,7 @@ #define ILI93414WS_SPI_DEVICE 5 -/* spi frequency based on arch/arm/src/stm32/stm32_spi.c */ +/* spi frequency based on arch/arm/src/common/stm32/stm32_spi.h */ #ifndef CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY # define CONFIG_STM32F429I_DISCO_ILI9341_SPIFREQUENCY 20000000 @@ -209,7 +209,7 @@ struct ili93414ws_lcd_s g_lcddev; * * Description: * Clear and set bits in the CR register (based on - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). * * Input Parameters: * reg - register to set @@ -951,14 +951,14 @@ static void stm32_ili93414ws_deselect(struct ili9341_lcd_s *lcd) /* Restore cr1 and cr2 register to be sure they will be usable * by default spi interface structure. (This is an important workaround as * long as half duplex mode is not supported by the spi interface in - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ putreg16(priv->cr2, ILI93414WS_SPI_CR2); putreg16(priv->cr1, ILI93414WS_SPI_CR1); /* Enable spi device is default for initialized spi ports (see - * arch/arm/src/stm32/stm32_spi.c). + * arch/arm/src/common/stm32/stm32_spi.h). */ stm32_ili93414ws_spienable(); diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c index 07dd27571eb..28e8c772a62 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c index 9ce1aab6c42..318fe6a8521 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_pwm.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c index 940f4af472a..b45295dbf24 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c index 9179d51fc3f..e6733b6f569 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_stmpe811.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_stmpe811.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c index 3178d70af9e..64d1ec5758e 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_usb.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c index b3d122eb039..9ba0c74b5a5 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32_userleds.c + * boards/arm/stm32f4/stm32f429i-disco/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h similarity index 99% rename from boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h rename to boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h index 121f0380a73..a9f7d7a5d6a 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h +++ b/boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h + * boards/arm/stm32f4/stm32f429i-disco/src/stm32f429i-disco.h * * SPDX-License-Identifier: Apache-2.0 * @@ -35,7 +35,7 @@ #include #endif -#include +#include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh similarity index 98% rename from boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh rename to boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh index d871b35a27d..b2df4b4f3b0 100755 --- a/boards/arm/stm32/stm32f429i-disco/tools/fbcalc.sh +++ b/boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash ############################################################################# - # boards/arm/stm32/stm32f429-disco/tools/fbcalc.sh + # boards/arm/stm32f4/stm32f429i-disco/tools/fbcalc.sh # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/stm32f4discovery/CMakeLists.txt rename to boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt index 290b7c62f75..3aee03875c3 100644 --- a/boards/arm/stm32/stm32f4discovery/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f4discovery/CMakeLists.txt +# boards/arm/stm32f4/stm32f4discovery/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/Kconfig b/boards/arm/stm32f4/stm32f4discovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32f4discovery/Kconfig rename to boards/arm/stm32f4/stm32f4discovery/Kconfig diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/adb/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig index 3b05080d90f..493408723d3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/adb/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/audio/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig index 623d3a1e1bb..aec03f8df55 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/audio/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/audio/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig index ecd9f77382d..0580be8f51b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/brickmatch/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/brickmatch/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/canard/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig index 869c48008b0..6b7b18cc1b1 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/canard/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/canard/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/composite/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig index dbe02211a04..51f162f19cf 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/composite/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/composite/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig similarity index 97% rename from boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig index d6797cbdc44..c76721660ac 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxx-oot-build/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxx-oot-build/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig similarity index 97% rename from boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig index 225ef545f47..e08ad78e23d 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/cxxtest/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/cxxtest/defconfig @@ -10,7 +10,7 @@ CONFIG_ALLOW_GPL_COMPONENTS=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig similarity index 97% rename from boards/arm/stm32/stm32f4discovery/configs/elf/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig index e56e68e8342..5d723c21b0b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/elf/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/elf/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig index a4a5c25d0e0..34aeeb9e313 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ether_w5500/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ether_w5500/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig index 6858d9793fa..0a856c6e165 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/ipv6/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/ipv6/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs similarity index 96% rename from boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs rename to boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs index 8905673c979..8c981466a32 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f4discovery/configs/kostest/Make.defs +# boards/arm/stm32f4/stm32f4discovery/configs/kostest/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig similarity index 93% rename from boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig index 2a280821536..f24a077cc43 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y @@ -28,7 +28,7 @@ CONFIG_INTELHEX_BINARY=y CONFIG_MM_KERNEL_HEAPSIZE=16384 CONFIG_MM_REGIONS=2 CONFIG_NUTTX_USERSPACE=0x08020000 -CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel" +CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel" CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig index a77136217c5..90156f132df 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lcd1602/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lcd1602/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig similarity index 97% rename from boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig index 9e891cdedc8..5f14cb57fe7 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/lwl/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/lwl/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig index 9781ef94b88..09872937415 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max31855/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max31855/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig similarity index 99% rename from boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig index 9535be0eca2..bee74446f04 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/max7219/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/max7219/defconfig @@ -44,7 +44,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig index 954b7b3a225..905b47c6c4e 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mmcsdspi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mmcsdspi/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig index 43ba01f9c0e..9ca17e59aa3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/modbus_slave/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/modbus_slave/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/module/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig index df1afdd0b43..187cc954564 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/module/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/module/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig index 21b36c9bdd4..ed7c5122192 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mpr121_keypad/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mpr121_keypad/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig index 0245779431b..54d22a0a69b 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/mt6816/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/mt6816/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig index ec06dd1c797..e18237614b4 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/netnsh/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/netnsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig index 88ce0cf4f4c..f81f20eeb80 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nsh/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nsh/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig index 3802741e950..b52478393f0 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxlines/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxlines/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig index 97640d9aed1..44b45995116 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/nxscope_cdcacm/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/nxscope_cdcacm/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/pm/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig index 2213a49a0f5..baab23750c3 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pm/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pm/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig index 7300c051e05..71f4c346848 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/posix_spawn/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/posix_spawn/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig index 86c0b568849..2571bb23113 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/pseudoterm/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/pseudoterm/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig index 54b58a3d240..37c135b2c6f 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rgbled/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rgbled/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig index 78c093599ac..dafce58d612 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/rndis/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/rndis/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig index f97fa10aa37..569b7f230ce 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sbutton/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sbutton/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig index 9162788372a..5c8b151be4f 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/sporadic/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/sporadic/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig index 5da6dfcacc8..c76f9ac1a12 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7567/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7567/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig index d1a66e7735a..2e36dbdc267 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/st7789/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/st7789/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig index 98bd5b03d4a..938dcea494f 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/testlibcxx/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/testlibcxx/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig index b5881e0ef33..65c89a22460 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbmsc/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbmsc/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig index 76611a126a3..167fbd097ef 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/usbnsh/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/usbnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig similarity index 99% rename from boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig index dec3fc4699e..673265e3c77 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/wifi/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/wifi/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig similarity index 98% rename from boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig rename to boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig index 13fc63197cb..c7a5839e069 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/xen1210/defconfig +++ b/boards/arm/stm32f4/stm32f4discovery/configs/xen1210/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH_BOARD="stm32f4discovery" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_STM32F4_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32f4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32F407VG=y CONFIG_ARCH_CHIP_STM32F4=y diff --git a/boards/arm/stm32/stm32f4discovery/include/board.h b/boards/arm/stm32f4/stm32f4discovery/include/board.h similarity index 99% rename from boards/arm/stm32/stm32f4discovery/include/board.h rename to boards/arm/stm32f4/stm32f4discovery/include/board.h index 0287bd8a0fd..d8bebb7ef98 100644 --- a/boards/arm/stm32/stm32f4discovery/include/board.h +++ b/boards/arm/stm32f4/stm32f4discovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/include/board.h + * boards/arm/stm32f4/stm32f4discovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt similarity index 94% rename from boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt rename to boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt index 9691ef02692..7edffd00c7c 100644 --- a/boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f4discovery/kernel/CMakeLists.txt +# boards/arm/stm32f4/stm32f4discovery/kernel/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/kernel/Makefile b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile similarity index 98% rename from boards/arm/stm32/stm32f4discovery/kernel/Makefile rename to boards/arm/stm32f4/stm32f4discovery/kernel/Makefile index 1edb33f89ba..94250906043 100644 --- a/boards/arm/stm32/stm32f4discovery/kernel/Makefile +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f4discovery/kernel/Makefile +# boards/arm/stm32f4/stm32f4discovery/kernel/Makefile # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c rename to boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c index ee6b7fab075..6bcb1ee9edf 100644 --- a/boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c +++ b/boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/kernel/stm32_userspace.c + * boards/arm/stm32f4/stm32f4discovery/kernel/stm32_userspace.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs new file mode 100644 index 00000000000..9b89de7ed1c --- /dev/null +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/stm32f4/stm32f4discovery/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld similarity index 97% rename from boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld rename to boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld index b9bf5bf4bbb..b6fff76f8b9 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld + * boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/scripts/ld.script b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script similarity index 98% rename from boards/arm/stm32/stm32f4discovery/scripts/ld.script rename to boards/arm/stm32f4/stm32f4discovery/scripts/ld.script index 25abe6a0150..d51d0c7f6b2 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/ld.script +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/ld.script + * boards/arm/stm32f4/stm32f4discovery/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld similarity index 96% rename from boards/arm/stm32/stm32f4discovery/scripts/memory.ld rename to boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld index d82501ffb65..0d1eadb712d 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/memory.ld +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/memory.ld + * boards/arm/stm32f4/stm32f4discovery/scripts/memory.ld * * SPDX-License-Identifier: Apache-2.0 * @@ -34,7 +34,7 @@ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which * should fit into 64KB and, of course, can be optimized as needed (See - * also boards/arm/stm32/stm32f4discovery/scripts/kernel-space.ld). Allowing the + * also boards/arm/stm32f4/stm32f4discovery/scripts/kernel-space.ld). Allowing the * additional does permit addition debug instrumentation to be added to the * kernel space without overflowing the partition. * diff --git a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld similarity index 98% rename from boards/arm/stm32/stm32f4discovery/scripts/user-space.ld rename to boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld index 5e246bc2833..24c62636c46 100644 --- a/boards/arm/stm32/stm32f4discovery/scripts/user-space.ld +++ b/boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/scripts/user-space.ld + * boards/arm/stm32f4/stm32f4discovery/scripts/user-space.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt rename to boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt index e56c3f35a7d..f65fa366811 100644 --- a/boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt +++ b/boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32f4discovery/src/CMakeLists.txt +# boards/arm/stm32f4/stm32f4discovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/src/Make.defs b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/Make.defs rename to boards/arm/stm32f4/stm32f4discovery/src/Make.defs index d4a14a5c9f1..bb7e1b04123 100644 --- a/boards/arm/stm32/stm32f4discovery/src/Make.defs +++ b/boards/arm/stm32f4/stm32f4discovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32f4discovery/src/Make.defs +# boards/arm/stm32f4/stm32f4discovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c index 340db0bae33..ee6b826ed96 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_apa102.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_apa102.c * * SPDX-License-Identifier: Apache-2.0 * @@ -108,4 +108,3 @@ void board_lcd_uninitialize(void) { /* TO-FIX */ } - diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c index 2f886258095..ef69cc6c3ab 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_autoleds.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_boot.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c index b99a443e08d..1ea43384fbf 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_boot.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c index a5dae40aba6..a9ea083a706 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * @@ -32,6 +32,7 @@ #include #include +#include #ifdef CONFIG_USBMONITOR # include diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c index 8e2150389e1..db8e7e3f5e0 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_buttons.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_can.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c index b919bdc52ee..18a72d54f8a 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_can.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_can.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_capture.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c index df94bdee2a6..f3e15b471d0 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_capture.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_capture.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_capture.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_composite.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c index 12531a29de3..55103ee912e 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_composite.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_composite.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_composite.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c index 32949202cf4..a50ef41c344 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_cs43l22.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_cs43l22.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c index dbbd33c9a47..aa9fe97748a 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_djoystick.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_djoystick.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c index 5e7994ce3d0..1f81619aed8 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_enc28j60.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c index 88cf550586e..7907bedf1a2 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ethernet.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ethernet.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c index 49bb57a9d95..53427696131 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_extmem.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_extmem.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c index e53aba34f5b..44a5d77c1d8 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_gs2200m.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_gs2200m.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c index 899face28a1..12ac1ef084b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hciuart.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hciuart.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c index 30ab88b32e4..17a22bd6125 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_hx711.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_hx711.c * * SPDX-License-Identifier: Apache-2.0 * @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include #include "stm32_gpio.h" diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_idle.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c index f4b5bf5bbb8..b32240a9bdc 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_idle.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_idle.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c index 6c4905055d7..b3cd7b43f6c 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c index de429e9f91a..4062a4006ba 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_max7219_leds.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_max7219_leds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c index 980b52d497b..1118bb880c6 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_mmcsd.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_mmcsd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c similarity index 96% rename from boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c index f6a8f0af711..12e0b8aa0d9 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_netinit.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_netinit.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c index b5f8c9935ab..fabe0a26b57 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pca9635.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pca9635.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pm.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c index d9ac5804f38..1a490e03595 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pm.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pm.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c index 2d67dc8dd9c..bde3abd4658 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pmbuttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c index 089b3a8c74d..29fe4fe38db 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_pwm.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c similarity index 97% rename from boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c index 7f140d6ee42..8381b158e68 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f401rc-rs485/src/stm32_reset.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_reset.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c index 983d11293bc..dc245cd3738 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_rgbled.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_rgbled.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h index 8e47a501f46..7cfb268ae3d 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h + * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2017 Tomasz Wozniak. All rights reserved. diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c index 7f56897a821..2814a9eb8e1 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c * This file provides contents of an optional ROMFS volume, mounted at boot. * * SPDX-License-Identifier: BSD-3-Clause diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c index 9a604e0817c..a65801e5b34 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sdio.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sdio.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_spi.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c index a1026359b94..dac42a7b178 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_spi.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_spi.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c index 9f51dc3545f..f01e75e1494 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1289.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c index 6fc6f5a3b9c..d11616999a4 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ssd1351.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c index 6334b89e2ff..24f3975ba30 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7032.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c index ec7a72af4bd..8ce4280fa70 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7567.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c index 79d9586028d..43820a435bc 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_st7789.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c index 95dfed45d00..162d349a3fc 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_sx127x.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_timer.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c index e9f274bfbca..4b89cf2f844 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_timer.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c index 76be6cf99e1..17badadd6d0 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864ambag01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c similarity index 98% rename from boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c index e9d2fb8771e..4b4d62620c9 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ug2864hsweg01.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_uid.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c index 32f51da6faa..65bbd762409 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_uid.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c * * SPDX-License-Identifier: BSD-3-Clause * SPDX-FileCopyrightText: 2015 Marawan Ragab. All rights reserved. diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_usb.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c index b8f70554c48..34f38634343 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usb.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usb.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c similarity index 97% rename from boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c index d4afdc4e95e..327275dd7fe 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_usbmsc.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c index c2fc1756428..28992310825 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_userleds.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c rename to boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c index 210b7cb9e60..1524ec0f16b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_w5500.c + * boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h similarity index 99% rename from boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h rename to boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h index ef99b4a2fa7..2989dc8bc33 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h +++ b/boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h + * boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h * * SPDX-License-Identifier: Apache-2.0 * @@ -30,7 +30,7 @@ #include #include #include -#include +#include /**************************************************************************** * Pre-processor Definitions From 52922288ef159c0d1d03811e39144add5f3498de Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 159/268] !arch/stm32: move stm32g4 to its own directory BREAKING CHANGE: Part of splitting the legacy stm32 super-directory; relocates the stm32g4 sources, headers and boards into arch/arm/src/stm32g4, arch/arm/include/stm32g4 and boards/arm/stm32g4. Signed-off-by: raiden00pl --- arch/arm/include/stm32g4/chip.h | 350 ++++++++++++++++++ .../stm32g4xxxx_irq.h => stm32g4/irq.h} | 75 ++-- arch/arm/src/stm32g4/CMakeLists.txt | 28 ++ arch/arm/src/stm32g4/Kconfig | 340 +++++++++++++++++ arch/arm/src/stm32g4/Make.defs | 27 ++ arch/arm/src/stm32g4/chip.h | 59 +++ .../src/stm32g4/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32g4/hardware/stm32_pinmap.h | 17 + .../hardware/stm32g47xxx_hrtim.h | 2 +- .../hardware/stm32g4xxc_pinmap.h | 2 +- .../hardware/stm32g4xxk_pinmap.h | 2 +- .../hardware/stm32g4xxm_pinmap.h | 2 +- .../hardware/stm32g4xxp_pinmap.h | 2 +- .../hardware/stm32g4xxq_pinmap.h | 2 +- .../hardware/stm32g4xxr_pinmap.h | 2 +- .../hardware/stm32g4xxv_pinmap.h | 2 +- .../hardware/stm32g4xxxx_comp.h | 2 +- .../hardware/stm32g4xxxx_cordic.h | 2 +- .../hardware/stm32g4xxxx_dmamux.h | 2 +- .../hardware/stm32g4xxxx_gpio.h | 2 +- .../hardware/stm32g4xxxx_memorymap.h | 2 +- .../hardware/stm32g4xxxx_opamp.h | 2 +- .../hardware/stm32g4xxxx_pinmap.h | 2 +- .../hardware/stm32g4xxxx_pwr.h | 2 +- .../hardware/stm32g4xxxx_rcc.h | 2 +- .../hardware/stm32g4xxxx_syscfg.h | 2 +- .../hardware/stm32g4xxxx_vrefbuf.h | 2 +- arch/arm/src/stm32g4/stm32.h | 69 ++++ arch/arm/src/stm32g4/stm32_rcc.c | 234 ++++++++++++ .../src/{stm32 => stm32g4}/stm32g4xxxx_rcc.c | 2 +- .../b-g431b-esc1}/CMakeLists.txt | 2 +- .../{stm32 => stm32g4}/b-g431b-esc1/Kconfig | 0 .../b-g431b-esc1/configs/can/defconfig | 2 +- .../b-g431b-esc1/configs/cansock/defconfig | 2 +- .../b-g431b-esc1/configs/foc_b16/defconfig | 2 +- .../b-g431b-esc1/configs/foc_f32/defconfig | 2 +- .../b-g431b-esc1/configs/nsh/defconfig | 2 +- .../b-g431b-esc1/include/board.h | 2 +- .../b-g431b-esc1}/scripts/Make.defs | 2 +- .../b-g431b-esc1/scripts/ld.script | 2 +- .../b-g431b-esc1/src/.gitignore | 0 .../b-g431b-esc1/src/CMakeLists.txt | 2 +- .../b-g431b-esc1/src/Make.defs | 2 +- .../b-g431b-esc1/src/b-g431b-esc1.h | 2 +- .../b-g431b-esc1/src/stm32_autoleds.c | 2 +- .../b-g431b-esc1/src/stm32_boot.c | 2 +- .../b-g431b-esc1/src/stm32_bringup.c | 2 +- .../b-g431b-esc1/src/stm32_buttons.c | 2 +- .../b-g431b-esc1/src/stm32_can.c | 2 +- .../b-g431b-esc1/src/stm32_cansock.c | 2 +- .../b-g431b-esc1/src/stm32_foc.c | 2 +- .../b-g431b-esc1/src/stm32_userleds.c | 2 +- .../arm/stm32g4/b-g474e-dpow1/CMakeLists.txt | 23 ++ .../{stm32 => stm32g4}/b-g474e-dpow1/Kconfig | 0 .../b-g474e-dpow1/configs/buckboost/defconfig | 2 +- .../b-g474e-dpow1/configs/nsh/defconfig | 2 +- .../b-g474e-dpow1/configs/ostest/defconfig | 2 +- .../b-g474e-dpow1/include/board.h | 2 +- .../b-g474e-dpow1}/scripts/Make.defs | 2 +- .../b-g474e-dpow1/scripts/ld.script | 2 +- .../b-g474e-dpow1/scripts/ld.script.dfu | 2 +- .../b-g474e-dpow1/src/.gitignore | 0 .../b-g474e-dpow1/src/CMakeLists.txt | 2 +- .../b-g474e-dpow1/src/Make.defs | 2 +- .../b-g474e-dpow1/src/b-g474e-dpow1.h | 2 +- .../b-g474e-dpow1/src/stm32_autoleds.c | 2 +- .../b-g474e-dpow1/src/stm32_boot.c | 2 +- .../b-g474e-dpow1/src/stm32_smps.c | 2 +- .../b-g474e-dpow1/src/stm32_userleds.c | 2 +- boards/arm/stm32g4/common/CMakeLists.txt | 25 ++ boards/arm/stm32g4/common/Kconfig | 6 + boards/arm/stm32g4/common/Makefile | 38 ++ .../arm/stm32g4/nucleo-g431kb/CMakeLists.txt | 23 ++ .../{stm32 => stm32g4}/nucleo-g431kb/Kconfig | 0 .../nucleo-g431kb/configs/comp/defconfig | 2 +- .../nucleo-g431kb/configs/nsh/defconfig | 2 +- .../nucleo-g431kb/configs/pwm/defconfig | 2 +- .../nucleo-g431kb/include/board.h | 2 +- .../nucleo-g431kb}/scripts/Make.defs | 2 +- .../nucleo-g431kb/scripts/ld.script | 2 +- .../nucleo-g431kb/src/.gitignore | 0 .../nucleo-g431kb/src/CMakeLists.txt | 2 +- .../nucleo-g431kb/src/Make.defs | 2 +- .../nucleo-g431kb/src/nucleo-g431kb.h | 2 +- .../nucleo-g431kb/src/stm32_autoleds.c | 2 +- .../nucleo-g431kb/src/stm32_boot.c | 2 +- .../nucleo-g431kb/src/stm32_bringup.c | 2 +- .../nucleo-g431kb/src/stm32_comp.c | 2 +- .../nucleo-g431kb/src/stm32_dac.c | 2 +- .../nucleo-g431kb/src/stm32_pwm.c | 2 +- .../nucleo-g431kb/src/stm32_userleds.c | 2 +- .../arm/stm32g4/nucleo-g431rb/CMakeLists.txt | 23 ++ .../{stm32 => stm32g4}/nucleo-g431rb/Kconfig | 0 .../nucleo-g431rb/configs/adc/defconfig | 2 +- .../nucleo-g431rb/configs/can/defconfig | 2 +- .../nucleo-g431rb/configs/cansock/defconfig | 2 +- .../nucleo-g431rb/configs/cordic/defconfig | 2 +- .../configs/ihm16m1_b16/defconfig | 2 +- .../configs/ihm16m1_f32/defconfig | 2 +- .../nucleo-g431rb/configs/nsh/defconfig | 2 +- .../nucleo-g431rb/configs/pwm/defconfig | 2 +- .../nucleo-g431rb/configs/qenco/defconfig | 2 +- .../nucleo-g431rb/include/board.h | 2 +- .../nucleo-g431rb}/scripts/Make.defs | 2 +- .../nucleo-g431rb/scripts/ld.script | 2 +- .../nucleo-g431rb/src/.gitignore | 0 .../nucleo-g431rb/src/CMakeLists.txt | 2 +- .../nucleo-g431rb/src/Make.defs | 2 +- .../nucleo-g431rb/src/nucleo-g431rb.h | 2 +- .../nucleo-g431rb/src/stm32_adc.c | 2 +- .../nucleo-g431rb/src/stm32_autoleds.c | 2 +- .../nucleo-g431rb/src/stm32_boot.c | 2 +- .../nucleo-g431rb/src/stm32_bringup.c | 2 +- .../nucleo-g431rb/src/stm32_buttons.c | 2 +- .../nucleo-g431rb/src/stm32_can.c | 2 +- .../nucleo-g431rb/src/stm32_cansock.c | 2 +- .../nucleo-g431rb/src/stm32_cordic.c | 2 +- .../nucleo-g431rb/src/stm32_foc_ihm16m1.c | 2 +- .../nucleo-g431rb/src/stm32_pwm.c | 2 +- .../nucleo-g431rb/src/stm32_userleds.c | 2 +- .../arm/stm32g4/nucleo-g474re/CMakeLists.txt | 23 ++ .../{stm32 => stm32g4}/nucleo-g474re/Kconfig | 0 .../nucleo-g474re/configs/lpuartnsh/defconfig | 2 +- .../nucleo-g474re/configs/nsh/defconfig | 2 +- .../nucleo-g474re/configs/usbserial/defconfig | 2 +- .../nucleo-g474re/include/board.h | 2 +- .../stm32g4/nucleo-g474re/scripts/Make.defs | 51 +++ .../nucleo-g474re/scripts/ld.script | 2 +- .../nucleo-g474re/scripts/ld.script.dfu | 2 +- .../nucleo-g474re/src/.gitignore | 0 .../nucleo-g474re/src/CMakeLists.txt | 2 +- .../nucleo-g474re/src/Make.defs | 2 +- .../nucleo-g474re/src/nucleo-g474re.h | 2 +- .../nucleo-g474re/src/stm32_autoleds.c | 2 +- .../nucleo-g474re/src/stm32_boot.c | 2 +- .../nucleo-g474re/src/stm32_bringup.c | 2 +- .../nucleo-g474re/src/stm32_usbdev.c | 2 +- .../nucleo-g474re/src/stm32_userleds.c | 2 +- 138 files changed, 1512 insertions(+), 136 deletions(-) create mode 100644 arch/arm/include/stm32g4/chip.h rename arch/arm/include/{stm32/stm32g4xxxx_irq.h => stm32g4/irq.h} (82%) create mode 100644 arch/arm/src/stm32g4/CMakeLists.txt create mode 100644 arch/arm/src/stm32g4/Kconfig create mode 100644 arch/arm/src/stm32g4/Make.defs create mode 100644 arch/arm/src/stm32g4/chip.h create mode 100644 arch/arm/src/stm32g4/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32g4/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g47xxx_hrtim.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxc_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxk_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxm_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxp_pinmap.h (96%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxq_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxr_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxv_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_comp.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_cordic.h (98%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_dmamux.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_opamp.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_pinmap.h (97%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_pwr.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_syscfg.h (99%) rename arch/arm/src/{stm32 => stm32g4}/hardware/stm32g4xxxx_vrefbuf.h (98%) create mode 100644 arch/arm/src/stm32g4/stm32.h create mode 100644 arch/arm/src/stm32g4/stm32_rcc.c rename arch/arm/src/{stm32 => stm32g4}/stm32g4xxxx_rcc.c (99%) rename boards/arm/{stm32/b-g474e-dpow1 => stm32g4/b-g431b-esc1}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/Kconfig (100%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/configs/can/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/configs/cansock/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/configs/foc_b16/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/configs/foc_f32/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/include/board.h (99%) rename boards/arm/{stm32/nucleo-g431kb => stm32g4/b-g431b-esc1}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/.gitignore (100%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/b-g431b-esc1.h (99%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_can.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_cansock.c (97%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_foc.c (99%) rename boards/arm/{stm32 => stm32g4}/b-g431b-esc1/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/Kconfig (100%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/configs/buckboost/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/configs/ostest/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/include/board.h (99%) rename boards/arm/{stm32/nucleo-g431rb => stm32g4/b-g474e-dpow1}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/scripts/ld.script.dfu (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/.gitignore (100%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/Make.defs (96%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/b-g474e-dpow1.h (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/stm32_smps.c (99%) rename boards/arm/{stm32 => stm32g4}/b-g474e-dpow1/src/stm32_userleds.c (98%) create mode 100644 boards/arm/stm32g4/common/CMakeLists.txt create mode 100644 boards/arm/stm32g4/common/Kconfig create mode 100644 boards/arm/stm32g4/common/Makefile create mode 100644 boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/Kconfig (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/configs/comp/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/configs/pwm/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/include/board.h (99%) rename boards/arm/{stm32/b-g474e-dpow1 => stm32g4/nucleo-g431kb}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/.gitignore (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/Make.defs (96%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/nucleo-g431kb.h (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_comp.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_dac.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431kb/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/Kconfig (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/adc/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/can/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/cansock/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/cordic/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/ihm16m1_b16/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/ihm16m1_f32/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/pwm/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/configs/qenco/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/include/board.h (99%) rename boards/arm/{stm32/b-g431b-esc1 => stm32g4/nucleo-g431rb}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/.gitignore (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/CMakeLists.txt (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/Make.defs (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/nucleo-g431rb.h (99%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_adc.c (99%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_can.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_cansock.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_cordic.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_foc_ihm16m1.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g431rb/src/stm32_userleds.c (97%) create mode 100644 boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/Kconfig (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/configs/lpuartnsh/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/configs/nsh/defconfig (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/configs/usbserial/defconfig (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/include/board.h (99%) create mode 100644 boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/scripts/ld.script.dfu (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/.gitignore (100%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/Make.defs (96%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/nucleo-g474re.h (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/stm32_usbdev.c (97%) rename boards/arm/{stm32 => stm32g4}/nucleo-g474re/src/stm32_userleds.c (98%) diff --git a/arch/arm/include/stm32g4/chip.h b/arch/arm/include/stm32g4/chip.h new file mode 100644 index 00000000000..f552caac654 --- /dev/null +++ b/arch/arm/include/stm32g4/chip.h @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/arm/include/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32G4_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +#if defined (CONFIG_ARCH_CHIP_STM32G431K) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 2 /* USART1-2 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 26 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 66 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G431V) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ +# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (1) 32-bit general timers TIM2 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 4 /* USART1-3 and UART4*/ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 3 /* I2C1-3 */ +# define STM32_NCAN 1 /* FDCAN1 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 2 /* 12-bit ADC1-2 */ +# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474C) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 42 /* GPIOA-C, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474M) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 67 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474R) +# define STM32_NFSMC 0 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 52 /* GPIOA-D, F-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 107 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined (CONFIG_ARCH_CHIP_STM32G474V) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ +# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA + * (2) 32-bit general timers TIM2 and 5 with DMA + * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ +# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ +# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ +# define STM32_NDMA 2 /* DMA1-2 */ +# define STM32_NSPI 4 /* SPI1-4 */ +# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ +# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ +# define STM32_NLPUART 1 /* LPUART1 */ +# define STM32_NI2C 4 /* I2C1-4 */ +# define STM32_NCAN 3 /* FDCAN1-3 */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed + * with LPM and BCD support) */ +# define STM32_NGPIO 86 /* GPIOA-G */ +# define STM32_NADC 5 /* 12-bit ADC1-5 */ +# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ +# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No Ethernet MAC */ +# define STM32_NRNG 1 /* Random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V4 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32G4_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32g4xxxx_irq.h b/arch/arm/include/stm32g4/irq.h similarity index 82% rename from arch/arm/include/stm32/stm32g4xxxx_irq.h rename to arch/arm/include/stm32g4/irq.h index 1d0418be96a..ef6c1fd7fa6 100644 --- a/arch/arm/include/stm32/stm32g4xxxx_irq.h +++ b/arch/arm/include/stm32g4/irq.h @@ -1,31 +1,31 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32g4xxxx_irq.h + * arch/arm/include/stm32g4/irq.h * * SPDX-License-Identifier: Apache-2.0 * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at * - * http://www.apache.org/licenses/LICENSE-2.0 + * http://www.apache.org/licenses/LICENSE-2.0 * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. * ****************************************************************************/ -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32G4_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32G4_IRQ_H /**************************************************************************** * Included Files @@ -33,21 +33,44 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. The IRQ numbers correspond to the vector numbers and hence - * map directly to bits in the NVIC. This does, however, waste several words - * of memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15) are common to all STM32 parts and are - * found in nuttx/arch/arm/include/stm32/irq.h. They are not repeated here. - * - * Other interrupts (vectors >= 16) are defined below. +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. */ +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + #define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ #define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ #define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper interrupt, or Time Stamp (shared with STM32_IRQ_TIMESTAMP) */ @@ -199,4 +222,4 @@ extern "C" #endif #endif -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32G4XXXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32G4_IRQ_H */ diff --git a/arch/arm/src/stm32g4/CMakeLists.txt b/arch/arm/src/stm32g4/CMakeLists.txt new file mode 100644 index 00000000000..24e6c94b342 --- /dev/null +++ b/arch/arm/src/stm32g4/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm/src/stm32g4/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32g4/Kconfig b/arch/arm/src/stm32g4/Kconfig new file mode 100644 index 00000000000..a151b4a4877 --- /dev/null +++ b/arch/arm/src/stm32g4/Kconfig @@ -0,0 +1,340 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 G4 configuration" + +if ARCH_CHIP_STM32G4 + +choice + prompt "STM32G4 Chip Selection" + depends on ARCH_CHIP_STM32G4 + +config ARCH_CHIP_STM32G431K + bool "STM32G431K" + select STM32_STM32G43XX + select STM32_STM32G4XXK + select STM32_STM32G431K + +config ARCH_CHIP_STM32G431C + bool "STM32G431C" + select STM32_STM32G43XX + select STM32_STM32G4XXC + select STM32_STM32G431C + +config ARCH_CHIP_STM32G431R + bool "STM32G431R" + select STM32_STM32G43XX + select STM32_STM32G4XXR + select STM32_STM32G431R + +config ARCH_CHIP_STM32G431M + bool "STM32G431M" + select STM32_STM32G43XX + select STM32_STM32G4XXM + select STM32_STM32G431M + +config ARCH_CHIP_STM32G431V + bool "STM32G431V" + select STM32_STM32G43XX + select STM32_STM32G4XXV + select STM32_STM32G431V + +config ARCH_CHIP_STM32G474C + bool "STM32G474C" + select STM32_STM32G47XX + select STM32_STM32G4XXC + select STM32_STM32G474C + +config ARCH_CHIP_STM32G474M + bool "STM32G474M" + select STM32_STM32G47XX + select STM32_STM32G4XXM + select STM32_STM32G474M + +config ARCH_CHIP_STM32G474R + bool "STM32G474R" + select STM32_STM32G47XX + select STM32_STM32G4XXR + select STM32_STM32G474R + select STM32_HAVE_USBFS + +config ARCH_CHIP_STM32G474Q + bool "STM32G474Q" + select STM32_STM32G47XX + select STM32_STM32G4XXQ + select STM32_STM32G474Q + +config ARCH_CHIP_STM32G474V + bool "STM32G474V" + select STM32_STM32G47XX + select STM32_STM32G4XXV + select STM32_STM32G474V + +endchoice + +endif + +config STM32_STM32G4XXX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM4 + select ARCH_HAVE_FPU + select STM32_HAVE_I2C1 + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_DMAMUX + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V3 + select STM32_HAVE_IP_ADC_M3M4_V2 + select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_COMP_M3M4_V2 + select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC + select STM32_HAVE_IP_DAC_M3M4_V2 + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX + select STM32_HAVE_IP_EXTI_V2 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_G4 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V2 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_V1 + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_SPI_V3 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V3 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V4 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32_STM32G4_CAT2 + bool + default n + +config STM32_STM32G4_CAT3 + bool + default n + +config STM32_STM32G4_CAT4 + bool + default n + +config STM32_STM32G4XXK + bool + default n + +config STM32_STM32G4XXC + bool + default n + +config STM32_STM32G4XXR + bool + default n + +config STM32_STM32G4XXM + bool + default n + +config STM32_STM32G4XXV + bool + default n + +config STM32_STM32G4XXP + bool + default n + +config STM32_STM32G4XXQ + bool + default n + +config STM32_STM32G43XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT2 + select STM32_HAVE_ADC2 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC3 + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM8 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G431K + bool + default n + +config STM32_STM32G431C + bool + default n + select STM32_HAVE_USART3 + +config STM32_STM32G431R + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431M + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G431V + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + +config STM32_STM32G47XX + bool + default n + select STM32_STM32G4XXX + select STM32_STM32G4_CAT3 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_ADC4 + select STM32_HAVE_ADC5 + select STM32_HAVE_CCM + select STM32_HAVE_COMP1 + select STM32_HAVE_COMP2 + select STM32_HAVE_COMP3 + select STM32_HAVE_COMP4 + select STM32_HAVE_COMP5 + select STM32_HAVE_COMP6 + select STM32_HAVE_COMP7 + select STM32_HAVE_CORDIC + select STM32_HAVE_CRS + select STM32_HAVE_DAC1 + select STM32_HAVE_DAC2 + select STM32_HAVE_DAC3 + select STM32_HAVE_DAC4 + select STM32_HAVE_FSMC + select STM32_HAVE_FMAC + select STM32_HAVE_FDCAN1 + select STM32_HAVE_FDCAN2 + select STM32_HAVE_HRTIM1 + select STM32_HAVE_I2C2 + select STM32_HAVE_I2C3 + select STM32_HAVE_I2C4 + select STM32_HAVE_I2S3 + select STM32_HAVE_LPTIM1 + select STM32_HAVE_LPUART1 + select STM32_HAVE_OPAMP1 + select STM32_HAVE_OPAMP2 + select STM32_HAVE_OPAMP3 + select STM32_HAVE_OPAMP4 + select STM32_HAVE_OPAMP5 + select STM32_HAVE_OPAMP6 + select STM32_HAVE_QSPI + select STM32_HAVE_RNG + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM15 + select STM32_HAVE_TIM16 + select STM32_HAVE_TIM17 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM20 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM8 + select STM32_HAVE_USART3 + select STM32_HAVE_UCPD + select STM32_HAVE_USBDEV + +config STM32_STM32G474C + bool + default n + select STM32_HAVE_FDCAN3 + +config STM32_STM32G474M + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474R + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474Q + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + +config STM32_STM32G474V + bool + default n + select STM32_HAVE_FDCAN3 + select STM32_HAVE_FMC + select STM32_HAVE_SPI4 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 diff --git a/arch/arm/src/stm32g4/Make.defs b/arch/arm/src/stm32g4/Make.defs new file mode 100644 index 00000000000..e8ec4e1184e --- /dev/null +++ b/arch/arm/src/stm32g4/Make.defs @@ -0,0 +1,27 @@ +############################################################################ +# arch/arm/src/stm32g4/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv7-m/Make.defs + +CHIP_CSRCS = stm32_rcc.c + +include common/stm32/Make.defs diff --git a/arch/arm/src/stm32g4/chip.h b/arch/arm/src/stm32g4/chip.h new file mode 100644 index 00000000000..2be83d370f5 --- /dev/null +++ b/arch/arm/src/stm32g4/chip.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_CHIP_H +#define __ARCH_ARM_SRC_STM32G4_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ + +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32G4_CHIP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..5c737c84db3 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32g4/hardware/stm32_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..24148a45828 --- /dev/null +++ b/arch/arm/src/stm32g4/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32g4xxxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32G4_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h rename to arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h index 4e2a6445bfa..21a1dc772c5 100644 --- a/arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h +++ b/arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g47xxx_hrtim.h + * arch/arm/src/stm32g4/hardware/stm32g47xxx_hrtim.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h index ce520496590..6712ccc160f 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxc_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxc_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h index 44701877d52..0061b3e7fd4 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxk_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxk_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h index 1f28684b136..c8ef978d5cc 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxm_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxm_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h similarity index 96% rename from arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h index 860e449abac..2d3ad178534 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxp_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxp_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h index 82d1c4b8642..92b1d059c20 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxq_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxq_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h index 53806263bc7..009b98fe1f5 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxr_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxr_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h index a6cd76129e0..78197031a2c 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxv_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxv_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h index 4a9ec781e07..aff65335c07 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_comp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_comp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h index c0e5c6669cb..d664710669c 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_cordic.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_cordic.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h index a5d58546c6c..7e7c994dc30 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_dmamux.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_dmamux.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h index 661060cb876..7136812cdf6 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_gpio.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h index e0d72cf4cf1..fe1b4330269 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_memorymap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h index 89cddf6e59b..d607bd4d2b5 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_opamp.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_opamp.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h similarity index 97% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h index b8a5dc9546c..04f177f6ce8 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pinmap.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h index c5af4b8e157..20bf5247308 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_pwr.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_pwr.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h index 543d369f3eb..6070eeea00f 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_rcc.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h index a7fdf99c74b..4de4a00d94e 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_syscfg.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h similarity index 98% rename from arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h rename to arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h index 5591bfe744a..4b3d532c27f 100644 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h +++ b/arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_vrefbuf.h + * arch/arm/src/stm32g4/hardware/stm32g4xxxx_vrefbuf.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32g4/stm32.h b/arch/arm/src/stm32g4/stm32.h new file mode 100644 index 00000000000..07776d68275 --- /dev/null +++ b/arch/arm/src/stm32g4/stm32.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ + +#include "chip.h" +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" +#endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" + +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32g4/stm32_rcc.c b/arch/arm/src/stm32g4/stm32_rcc.c new file mode 100644 index 00000000000..49cfab73fb9 --- /dev/null +++ b/arch/arm/src/stm32g4/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32g4/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32g4xxxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32g4xxxx_rcc.c b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32g4xxxx_rcc.c rename to arch/arm/src/stm32g4/stm32g4xxxx_rcc.c index 8f937465778..f92d785d742 100644 --- a/arch/arm/src/stm32/stm32g4xxxx_rcc.c +++ b/arch/arm/src/stm32g4/stm32g4xxxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32g4xxxx_rcc.c + * arch/arm/src/stm32g4/stm32g4xxxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt rename to boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt index f0b7d812e44..c06c5331c11 100644 --- a/boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt +++ b/boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/CMakeLists.txt +# boards/arm/stm32g4/b-g431b-esc1/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g431b-esc1/Kconfig b/boards/arm/stm32g4/b-g431b-esc1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/Kconfig rename to boards/arm/stm32g4/b-g431b-esc1/Kconfig diff --git a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/configs/can/defconfig rename to boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig index 17b32fcb9bb..87e330cdcf3 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/can/defconfig +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/can/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig rename to boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig index 373cdc11f37..320b24936f0 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/cansock/defconfig +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/cansock/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig rename to boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig index a539b4674fc..d24c0ae4314 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_b16/defconfig +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_b16/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig rename to boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig index 83afe8d9abe..b8a719cfc1c 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/foc_f32/defconfig +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/foc_f32/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig rename to boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig index e90af74b545..89e273fb439 100644 --- a/boards/arm/stm32/b-g431b-esc1/configs/nsh/defconfig +++ b/boards/arm/stm32g4/b-g431b-esc1/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g431b-esc1" CONFIG_ARCH_BOARD_B_G431B_ESC1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431C=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g431b-esc1/include/board.h b/boards/arm/stm32g4/b-g431b-esc1/include/board.h similarity index 99% rename from boards/arm/stm32/b-g431b-esc1/include/board.h rename to boards/arm/stm32g4/b-g431b-esc1/include/board.h index f5568827ce8..006e80f98f3 100644 --- a/boards/arm/stm32/b-g431b-esc1/include/board.h +++ b/boards/arm/stm32g4/b-g431b-esc1/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/include/board.h + * boards/arm/stm32g4/b-g431b-esc1/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/scripts/Make.defs rename to boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs index 569fe825159..79f59cc5dc2 100644 --- a/boards/arm/stm32/nucleo-g431kb/scripts/Make.defs +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-g431kb/scripts/Make.defs +# boards/arm/stm32g4/b-g431b-esc1/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/scripts/ld.script rename to boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script index aae24391abf..6eecf3272e4 100644 --- a/boards/arm/stm32/b-g431b-esc1/scripts/ld.script +++ b/boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/scripts/ld.script + * boards/arm/stm32g4/b-g431b-esc1/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/.gitignore b/boards/arm/stm32g4/b-g431b-esc1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g431b-esc1/src/.gitignore rename to boards/arm/stm32g4/b-g431b-esc1/src/.gitignore diff --git a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt rename to boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt index 76a72b59c7a..3c5362a634c 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt +++ b/boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/b-g431b-esc1/src/CMakeLists.txt +# boards/arm/stm32g4/b-g431b-esc1/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g431b-esc1/src/Make.defs b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs similarity index 97% rename from boards/arm/stm32/b-g431b-esc1/src/Make.defs rename to boards/arm/stm32g4/b-g431b-esc1/src/Make.defs index 2d49b9a66c9..04209293fc8 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/Make.defs +++ b/boards/arm/stm32g4/b-g431b-esc1/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/b-g431b-esc1/src/Make.defs +# boards/arm/stm32g4/b-g431b-esc1/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h similarity index 99% rename from boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h rename to boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h index 40e7863bd06..708c07fdbd2 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h +++ b/boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/b-g431b-esc1.h + * boards/arm/stm32g4/b-g431b-esc1/src/b-g431b-esc1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c index ec5bbf09cf5..23784ea51aa 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_autoleds.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c index 12e9e93bf6e..09acc6b61f6 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_boot.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c index 3b5cf90e926..8a4aed406f0 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_bringup.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c index 3e7c93b00f7..ac13875fa0c 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_buttons.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_can.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c index 5a8c005e9ba..7061003ba90 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_can.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_can.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c index 1841bc9e6cd..eb0d3acfdf2 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_cansock.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c similarity index 99% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c index 6b22e655b38..c20d43a435e 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_foc.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_foc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c rename to boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c index 2606087a8fa..debdfde7e98 100644 --- a/boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c +++ b/boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g431b-esc1/src/stm32_userleds.c + * boards/arm/stm32g4/b-g431b-esc1/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt new file mode 100644 index 00000000000..d5b7816aff5 --- /dev/null +++ b/boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/b-g474e-dpow1/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/b-g474e-dpow1/Kconfig b/boards/arm/stm32g4/b-g474e-dpow1/Kconfig similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/Kconfig rename to boards/arm/stm32g4/b-g474e-dpow1/Kconfig diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig rename to boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig index fbccc190546..9bc515466ce 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/buckboost/defconfig +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/buckboost/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig rename to boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig index 4a06eef534f..f2c942f86db 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/nsh/defconfig +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig similarity index 97% rename from boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig rename to boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig index f0062bba6a8..de16a9a8cab 100644 --- a/boards/arm/stm32/b-g474e-dpow1/configs/ostest/defconfig +++ b/boards/arm/stm32g4/b-g474e-dpow1/configs/ostest/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="b-g474e-dpow1" CONFIG_ARCH_BOARD_B_G474E_DPOW1=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/b-g474e-dpow1/include/board.h b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h similarity index 99% rename from boards/arm/stm32/b-g474e-dpow1/include/board.h rename to boards/arm/stm32g4/b-g474e-dpow1/include/board.h index 03a0e8edd1a..d06e0188bf6 100644 --- a/boards/arm/stm32/b-g474e-dpow1/include/board.h +++ b/boards/arm/stm32g4/b-g474e-dpow1/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/include/board.h + * boards/arm/stm32g4/b-g474e-dpow1/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/scripts/Make.defs rename to boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs index 43067ac1b19..a70ca28ceb5 100644 --- a/boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-g431rb/scripts/Make.defs +# boards/arm/stm32g4/b-g474e-dpow1/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/scripts/ld.script rename to boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script index 64c1953f7fc..94b8086bd49 100644 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu rename to boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu index d27ca98a144..bef0887a3a8 100644 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/ld.script.dfu +++ b/boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/scripts/ld.script + * boards/arm/stm32g4/b-g474e-dpow1/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/src/.gitignore b/boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore similarity index 100% rename from boards/arm/stm32/b-g474e-dpow1/src/.gitignore rename to boards/arm/stm32g4/b-g474e-dpow1/src/.gitignore diff --git a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt rename to boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt index 87e3c2b6ee9..5a6c304b0f2 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/b-g474e-dpow1/src/CMakeLists.txt +# boards/arm/stm32g4/b-g474e-dpow1/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs similarity index 96% rename from boards/arm/stm32/b-g474e-dpow1/src/Make.defs rename to boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs index e91f93fd7a5..172dcb8b099 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/Make.defs +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/b-g474e-dpow1/src/Make.defs +# boards/arm/stm32g4/b-g474e-dpow1/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h rename to boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h index f7c09937e7f..f981e5ed105 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/b-g474e-dpow1.h + * boards/arm/stm32g4/b-g474e-dpow1/src/b-g474e-dpow1.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c rename to boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c index 1591f068d43..41f87f2130b 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_autoleds.c + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c rename to boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c index f901b448b02..a7bbb7138b0 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_boot.c + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c similarity index 99% rename from boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c rename to boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c index b2496a63d85..9a51ba29084 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_smps.c + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_smps.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c rename to boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c index badccd03daa..c96b7278570 100644 --- a/boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c +++ b/boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/b-g474e-dpow1/src/stm32_userleds.c + * boards/arm/stm32g4/b-g474e-dpow1/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/common/CMakeLists.txt b/boards/arm/stm32g4/common/CMakeLists.txt new file mode 100644 index 00000000000..b3ddb9ace0f --- /dev/null +++ b/boards/arm/stm32g4/common/CMakeLists.txt @@ -0,0 +1,25 @@ +# ############################################################################## +# boards/arm/stm32g4/common/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32g4/common/Kconfig b/boards/arm/stm32g4/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32g4/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32g4/common/Makefile b/boards/arm/stm32g4/common/Makefile new file mode 100644 index 00000000000..d66ce54147b --- /dev/null +++ b/boards/arm/stm32g4/common/Makefile @@ -0,0 +1,38 @@ +############################################################################# +# boards/arm/stm32g4/common/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 + +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs + +DEPPATH += --dep-path board + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt new file mode 100644 index 00000000000..2b117337231 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431kb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/Kconfig b/boards/arm/stm32g4/nucleo-g431kb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/Kconfig rename to boards/arm/stm32g4/nucleo-g431kb/Kconfig diff --git a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig rename to boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig index 19ef6fb3b3a..d47e5c3e774 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/comp/defconfig +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/comp/defconfig @@ -9,7 +9,7 @@ CONFIG_ANALOG=y CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig rename to boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig index 71d86817a14..e848946ed7e 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/nsh/defconfig +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/nsh/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig rename to boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig index 03c3f4463e2..8fbb0dc6b87 100644 --- a/boards/arm/stm32/nucleo-g431kb/configs/pwm/defconfig +++ b/boards/arm/stm32g4/nucleo-g431kb/configs/pwm/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431kb" CONFIG_ARCH_BOARD_NUCLEO_G431KB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431K=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431kb/include/board.h b/boards/arm/stm32g4/nucleo-g431kb/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-g431kb/include/board.h rename to boards/arm/stm32g4/nucleo-g431kb/include/board.h index c5e339abd03..c3a80f1c312 100644 --- a/boards/arm/stm32/nucleo-g431kb/include/board.h +++ b/boards/arm/stm32g4/nucleo-g431kb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/include/board.h + * boards/arm/stm32g4/nucleo-g431kb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs rename to boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs index 57c27ead5ec..0018145617a 100644 --- a/boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/b-g474e-dpow1/scripts/Make.defs +# boards/arm/stm32g4/nucleo-g431kb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/scripts/ld.script rename to boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script index b7f4d0667e9..4c8eebff5b1 100644 --- a/boards/arm/stm32/nucleo-g431kb/scripts/ld.script +++ b/boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/scripts/ld.script + * boards/arm/stm32g4/nucleo-g431kb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431kb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431kb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431kb/src/.gitignore diff --git a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt rename to boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt index e45962dfe20..eb079f99567 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt +++ b/boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-g431kb/src/CMakeLists.txt +# boards/arm/stm32g4/nucleo-g431kb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431kb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-g431kb/src/Make.defs rename to boards/arm/stm32g4/nucleo-g431kb/src/Make.defs index 7aa1045c6a8..d0b9afc1629 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/Make.defs +++ b/boards/arm/stm32g4/nucleo-g431kb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-g431kb/src/Make.defs +# boards/arm/stm32g4/nucleo-g431kb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h rename to boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h index 147f4c3479d..79f0f56b472 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h +++ b/boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/nucleo-g431kb.h + * boards/arm/stm32g4/nucleo-g431kb/src/nucleo-g431kb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c index fbb97ddcaeb..918b2ad9fbf 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_autoleds.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c index 4a75293c2de..3b9024b9b1f 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_boot.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c index 7def155d655..c20ef2f5cdd 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_bringup.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c index 077454afccd..17cb1960b99 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_comp.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_comp.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c index 97790997116..c67d3d78edf 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_dac.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_dac.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c index 01ae0c92765..b20b3c2dcad 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_pwm.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c rename to boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c index 072ae0166ae..2d20146d07e 100644 --- a/boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c +++ b/boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431kb/src/stm32_userleds.c + * boards/arm/stm32g4/nucleo-g431kb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt new file mode 100644 index 00000000000..bc497249c83 --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g431rb/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/Kconfig b/boards/arm/stm32g4/nucleo-g431rb/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/Kconfig rename to boards/arm/stm32g4/nucleo-g431rb/Kconfig diff --git a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig index c275012af8b..2154e927ac4 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/adc/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/adc/defconfig @@ -13,7 +13,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/can/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig index 164ca565954..2aa1ede955e 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/can/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/can/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig index 6986192ece8..c139bf6d9b5 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cansock/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cansock/defconfig @@ -12,7 +12,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig index a70cdc98d43..1490159995b 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/cordic/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/cordic/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig index de716f64e0e..ded5f303e7c 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_b16/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_b16/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig index 0565f5b91df..d70d9724fe0 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/ihm16m1_f32/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/ihm16m1_f32/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig index d86c4e134ce..2741f79a4ff 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/nsh/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig index 63712349344..7bb17b75b5b 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/pwm/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/pwm/defconfig @@ -8,7 +8,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_NUCLEO_G431RB=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig rename to boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig index 8c11d4f8a59..f593ed1dac3 100644 --- a/boards/arm/stm32/nucleo-g431rb/configs/qenco/defconfig +++ b/boards/arm/stm32g4/nucleo-g431rb/configs/qenco/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD="nucleo-g431rb" CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_NUCLEO_G431RB=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G431R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g431rb/include/board.h b/boards/arm/stm32g4/nucleo-g431rb/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-g431rb/include/board.h rename to boards/arm/stm32g4/nucleo-g431rb/include/board.h index d0276b130af..75cc137c574 100644 --- a/boards/arm/stm32/nucleo-g431rb/include/board.h +++ b/boards/arm/stm32g4/nucleo-g431rb/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/include/board.h + * boards/arm/stm32g4/nucleo-g431rb/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/b-g431b-esc1/scripts/Make.defs rename to boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs index 0a510303baa..2eb0f2b8463 100644 --- a/boards/arm/stm32/b-g431b-esc1/scripts/Make.defs +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/b-g431b-esc1/scripts/Make.defs +# boards/arm/stm32g4/nucleo-g431rb/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/scripts/ld.script rename to boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script index 75cdcb94d47..bd82a15d578 100644 --- a/boards/arm/stm32/nucleo-g431rb/scripts/ld.script +++ b/boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/scripts/ld.script + * boards/arm/stm32g4/nucleo-g431rb/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/.gitignore b/boards/arm/stm32g4/nucleo-g431rb/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g431rb/src/.gitignore rename to boards/arm/stm32g4/nucleo-g431rb/src/.gitignore diff --git a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt rename to boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt index f25dfbffa49..21262028d44 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt +++ b/boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-g431rb/src/CMakeLists.txt +# boards/arm/stm32g4/nucleo-g431rb/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431rb/src/Make.defs b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/Make.defs rename to boards/arm/stm32g4/nucleo-g431rb/src/Make.defs index 14403c22700..17328e8d989 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/Make.defs +++ b/boards/arm/stm32g4/nucleo-g431rb/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-g431rb/src/Make.defs +# boards/arm/stm32g4/nucleo-g431rb/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h similarity index 99% rename from boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h rename to boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h index a00571f7c2e..c1aab3f25c2 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h +++ b/boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/nucleo-g431rb.h + * boards/arm/stm32g4/nucleo-g431rb/src/nucleo-g431rb.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c similarity index 99% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c index c2b993d18fe..23dcbdf7b6e 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_adc.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_adc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c index 4c599539d00..74c7bf61f79 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_autoleds.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c index 9cddcb3b093..8f5ac067df9 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_boot.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c index 5eabcf60798..82b3a8be71f 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_bringup.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c index 462f70b091a..f6bf2f0c90f 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_buttons.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_can.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c index 6f777f22c61..5a91c6e2fe0 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_can.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_can.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_can.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c index 72b03dc2324..c76c3ce5b2a 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cansock.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cansock.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c index aa3a5320176..9318847fd2d 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_cordic.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_cordic.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c index 73316003dd0..bf5f99735eb 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_foc_ihm16m1.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_foc_ihm16m1.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c index ce64c50083b..c91702c323e 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_pwm.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c rename to boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c index 43528165fb3..6d6bc7e72b0 100644 --- a/boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c +++ b/boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g431rb/src/stm32_userleds.c + * boards/arm/stm32g4/nucleo-g431rb/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt new file mode 100644 index 00000000000..4f4bba4b7af --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm/stm32g4/nucleo-g474re/CMakeLists.txt +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/Kconfig b/boards/arm/stm32g4/nucleo-g474re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-g474re/Kconfig rename to boards/arm/stm32g4/nucleo-g474re/Kconfig diff --git a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig rename to boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig index 380f216200a..ee2a8c2db94 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/lpuartnsh/defconfig +++ b/boards/arm/stm32g4/nucleo-g474re/configs/lpuartnsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig similarity index 97% rename from boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig rename to boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig index fbcf8585258..6a8c6317f57 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/nsh/defconfig +++ b/boards/arm/stm32g4/nucleo-g474re/configs/nsh/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig rename to boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig index 3dc81656600..405eabc8cdb 100644 --- a/boards/arm/stm32/nucleo-g474re/configs/usbserial/defconfig +++ b/boards/arm/stm32g4/nucleo-g474re/configs/usbserial/defconfig @@ -11,7 +11,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-g474re" CONFIG_ARCH_BOARD_NUCLEO_G474RE=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32g4" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32G474R=y CONFIG_ARCH_CHIP_STM32G4=y diff --git a/boards/arm/stm32/nucleo-g474re/include/board.h b/boards/arm/stm32g4/nucleo-g474re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-g474re/include/board.h rename to boards/arm/stm32g4/nucleo-g474re/include/board.h index bbc4cf8cf35..8fbf7924c8e 100644 --- a/boards/arm/stm32/nucleo-g474re/include/board.h +++ b/boards/arm/stm32g4/nucleo-g474re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/include/board.h + * boards/arm/stm32g4/nucleo-g474re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs new file mode 100644 index 00000000000..1ab6247f01c --- /dev/null +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# boards/arm/stm32g4/nucleo-g474re/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(CONFIG_STM32_DFU),y) + LDSCRIPT = ld.script.dfu +else + LDSCRIPT = ld.script +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Embed absolute path to source file in debug information so that Eclipse +# source level debugging won't get confused. See: +# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information +CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-g474re/scripts/ld.script rename to boards/arm/stm32g4/nucleo-g474re/scripts/ld.script index 6ed340018bc..4aca8670722 100644 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu similarity index 98% rename from boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu rename to boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu index e35b09cec89..152d9a3852f 100644 --- a/boards/arm/stm32/nucleo-g474re/scripts/ld.script.dfu +++ b/boards/arm/stm32g4/nucleo-g474re/scripts/ld.script.dfu @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/scripts/ld.script + * boards/arm/stm32g4/nucleo-g474re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/.gitignore b/boards/arm/stm32g4/nucleo-g474re/src/.gitignore similarity index 100% rename from boards/arm/stm32/nucleo-g474re/src/.gitignore rename to boards/arm/stm32g4/nucleo-g474re/src/.gitignore diff --git a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt rename to boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt index 53f5643fc8b..494c3bcb577 100644 --- a/boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt +++ b/boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-g474re/src/CMakeLists.txt +# boards/arm/stm32g4/nucleo-g474re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g474re/src/Make.defs b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-g474re/src/Make.defs rename to boards/arm/stm32g4/nucleo-g474re/src/Make.defs index b27f9af3514..7d2f9725ab0 100644 --- a/boards/arm/stm32/nucleo-g474re/src/Make.defs +++ b/boards/arm/stm32g4/nucleo-g474re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-g474re/src/Make.defs +# boards/arm/stm32g4/nucleo-g474re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h rename to boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h index 3609b90e7e5..e50ff639c45 100644 --- a/boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h +++ b/boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/nucleo-g474re.h + * boards/arm/stm32g4/nucleo-g474re/src/nucleo-g474re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c rename to boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c index c06b2fb11b5..28380bf71d7 100644 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_autoleds.c + * boards/arm/stm32g4/nucleo-g474re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/stm32_boot.c rename to boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c index 8f134c1cd9e..9b8eced144d 100644 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_boot.c +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_boot.c + * boards/arm/stm32g4/nucleo-g474re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c rename to boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c index bc3c6aa9007..89d86a499fe 100644 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_bringup.c + * boards/arm/stm32g4/nucleo-g474re/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c similarity index 97% rename from boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c rename to boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c index 898d118a8e7..389fb718f11 100644 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_usbdev.c + * boards/arm/stm32g4/nucleo-g474re/src/stm32_usbdev.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c similarity index 98% rename from boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c rename to boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c index 2b7b61b153a..16dcca37aee 100644 --- a/boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c +++ b/boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-g474re/src/stm32_userleds.c + * boards/arm/stm32g4/nucleo-g474re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * From 07c4bf0048f63bd241ab679d30b9b6b14ae5ed2a Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 25 May 2026 22:44:13 +0200 Subject: [PATCH 160/268] !arch/stm32: move stm32l1 and finalize the directory split Move the stm32l1 sources, headers and boards into arch/arm/src/stm32l1, arch/arm/include/stm32l1 and boards/arm/stm32l1, then finalize the split: source each split family directly in arch/arm/Kconfig and boards/Kconfig and remove the now-empty combined arch/arm/src/stm32 and boards/arm/stm32 trees. BREAKING CHANGE: The legacy STM32 architecture and board paths were split into stm32f1, stm32l1, stm32f2, stm32f3, stm32f4, and stm32g4 directories. Out-of-tree boards must move from stm32 to the matching split family. Signed-off-by: raiden00pl --- .github/CODEOWNERS | 3366 +++++++++-------- .../applications/examples/ft80x/index.rst | 2 +- .../applications/system/usbmsc/index.rst | 2 +- .../drivers/character/leds/userled.rst | 2 +- .../components/drivers/character/serial.rst | 2 +- .../components/drivers/special/lcd.rst | 6 +- .../components/drivers/special/sdio.rst | 2 +- .../components/drivers/special/usbdev.rst | 2 +- .../components/drivers/special/usbhost.rst | 2 +- Documentation/contributing/making-changes.rst | 2 +- .../guides/changing_systemclockconfig.rst | 4 +- Documentation/guides/etcromfs.rst | 2 +- Documentation/guides/ipv6.rst | 4 +- .../guides/nsh_network_link_management.rst | 2 +- Documentation/guides/ofloader.rst | 2 +- Documentation/guides/partially_linked_elf.rst | 2 +- .../guides/port_drivers_to_stm32f7.rst | 2 +- Documentation/guides/protected_build.rst | 22 +- .../guides/smaller_vector_tables.rst | 10 +- Documentation/guides/stm32ccm.rst | 2 +- Documentation/guides/usingkernelthreads.rst | 2 +- .../guides/zerolatencyinterrupts.rst | 4 +- Documentation/implementation/chip_h.rst | 10 +- .../implementation/file_descriptors.rst | 8 +- .../nuttx_initialization_sequence.rst | 26 +- .../arm/stm32f1/boards/fire-stm32v2/index.rst | 4 +- .../arm/stm32f1/boards/shenzhou/index.rst | 2 +- .../stm32f1/boards/stm3210e-eval/index.rst | 12 +- .../boards/stm32f103-minimum/index.rst | 4 +- .../stm32f1/boards/stm32vldiscovery/index.rst | 2 +- .../stm32f4/boards/clicker2-stm32/index.rst | 2 +- .../arm/stm32f4/boards/omnibusf4/index.rst | 2 +- .../stm32f4/boards/stm32f4discovery/index.rst | 14 +- Documentation/platforms/arm/stm32f4/index.rst | 2 +- .../stm32l4/boards/nucleo-l432kc/index.rst | 2 +- .../stm32l4/boards/nucleo-l476rg/index.rst | 2 +- Documentation/quickstart/organization.rst | 2 +- LICENSE | 44 +- arch/arm/Kconfig | 44 +- arch/arm/include/stm32/chip.h | 2756 -------------- arch/arm/include/stm32l1/chip.h | 491 +++ .../stm32l15xxx_irq.h => stm32l1/irq.h} | 86 +- arch/arm/src/common/stm32/CMakeLists.txt | 17 +- .../src/common/stm32/stm32_dma2d_m3m4_v1.c | 2 +- .../common/stm32/stm32_dma_m0_v1_7ch_dmamux.c | 2 +- arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c | 2 +- arch/arm/src/stm32/CMakeLists.txt | 57 - arch/arm/src/stm32/Kconfig | 2675 ------------- .../arm/src/stm32/hardware/stm32f10xxx_uart.h | 206 - .../arm/src/stm32/hardware/stm32f20xxx_uart.h | 218 -- .../arm/src/stm32/hardware/stm32f30xxx_uart.h | 341 -- .../arm/src/stm32/hardware/stm32f40xxx_uart.h | 236 -- .../arm/src/stm32/hardware/stm32g4xxxx_uart.h | 439 --- .../arm/src/stm32/hardware/stm32l15xxx_uart.h | 208 - arch/arm/src/stm32/stm32_pm.h | 127 - arch/arm/src/stm32/stm32_rcc.h | 321 -- arch/arm/src/stm32/stm32_userspace.h | 63 - arch/arm/src/stm32f7/stm32_can_sock.c | 2 +- arch/arm/src/stm32f7/stm32_foc.c | 3 +- .../arm/src/stm32l1}/CMakeLists.txt | 9 +- arch/arm/src/stm32l1/Kconfig | 356 ++ arch/arm/src/{stm32 => stm32l1}/Make.defs | 25 +- .../{stm32/stm32_start.h => stm32l1/chip.h} | 42 +- .../src/stm32l1/hardware/stm32_memorymap.h | 17 + arch/arm/src/stm32l1/hardware/stm32_pinmap.h | 17 + .../hardware/stm32l15xxx_aes.h | 2 +- .../hardware/stm32l15xxx_gpio.h | 2 +- .../hardware/stm32l15xxx_memorymap.h | 2 +- .../hardware/stm32l15xxx_pinmap.h | 2 +- .../hardware/stm32l15xxx_rcc.h | 2 +- .../hardware/stm32l15xxx_syscfg.h | 2 +- .../stm32_lowputc.h => stm32l1/stm32.h} | 73 +- arch/arm/src/stm32l1/stm32_rcc.c | 234 ++ .../{stm32 => stm32l1}/stm32l15xxx_alarm.h | 2 +- .../src/{stm32 => stm32l1}/stm32l15xxx_rcc.c | 2 +- boards/Kconfig | 130 +- boards/arm/stm32/nucleo-f103rb/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f207zg/CMakeLists.txt | 23 - .../arm/stm32/nucleo-f207zg/scripts/Make.defs | 41 - boards/arm/stm32/nucleo-f302r8/CMakeLists.txt | 23 - .../arm/stm32/nucleo-f302r8/scripts/Make.defs | 41 - boards/arm/stm32/nucleo-f303re/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f303ze/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f334r8/CMakeLists.txt | 23 - .../arm/stm32/nucleo-f334r8/scripts/Make.defs | 41 - boards/arm/stm32/nucleo-f401re/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f410rb/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f411re/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f412zg/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f429zi/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-f446re/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-g431kb/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-g431rb/CMakeLists.txt | 23 - boards/arm/stm32/nucleo-g474re/CMakeLists.txt | 23 - .../arm/stm32/nucleo-g474re/scripts/Make.defs | 51 - boards/arm/stm32/nucleo-l152re/CMakeLists.txt | 23 - .../arm/stm32/nucleo-l152re/scripts/Make.defs | 41 - .../stm32/olimex-stm32-e407/CMakeLists.txt | 23 - .../stm32/olimex-stm32-h405/CMakeLists.txt | 23 - .../stm32/olimex-stm32-h407/CMakeLists.txt | 23 - .../stm32/olimex-stm32-h407/scripts/Make.defs | 41 - .../stm32/olimex-stm32-p107/CMakeLists.txt | 23 - .../stm32/olimex-stm32-p207/CMakeLists.txt | 23 - .../stm32/olimex-stm32-p407/CMakeLists.txt | 23 - .../arm/stm32/olimexino-stm32/CMakeLists.txt | 23 - boards/arm/stm32/omnibusf4/CMakeLists.txt | 23 - boards/arm/stm32/shenzhou/CMakeLists.txt | 23 - boards/arm/stm32/stm3210e-eval/CMakeLists.txt | 23 - boards/arm/stm32/stm3220g-eval/CMakeLists.txt | 23 - .../arm/stm32/stm3220g-eval/scripts/Make.defs | 41 - boards/arm/stm32/stm3240g-eval/CMakeLists.txt | 23 - .../arm/stm32/stm3240g-eval/scripts/Make.defs | 41 - boards/arm/stm32/stm32_tiny/CMakeLists.txt | 23 - .../arm/stm32/stm32butterfly2/CMakeLists.txt | 23 - .../stm32/stm32f103-minimum/CMakeLists.txt | 23 - .../arm/stm32/stm32f334-disco/CMakeLists.txt | 23 - .../stm32/stm32f334-disco/scripts/Make.defs | 41 - .../arm/stm32/stm32f3discovery/CMakeLists.txt | 23 - .../stm32/stm32f3discovery/scripts/Make.defs | 41 - .../stm32/stm32f401rc-rs485/CMakeLists.txt | 23 - .../stm32/stm32f411-minimum/CMakeLists.txt | 23 - .../arm/stm32/stm32f411e-disco/CMakeLists.txt | 23 - .../arm/stm32/stm32f429i-disco/CMakeLists.txt | 23 - .../stm32f429i-disco/scripts/kernel-space.ld | 100 - .../stm32/stm32f4discovery/scripts/Make.defs | 41 - .../arm/stm32/stm32ldiscovery/CMakeLists.txt | 23 - .../arm/stm32/stm32vldiscovery/CMakeLists.txt | 23 - .../stm32/viewtool-stm32f107/CMakeLists.txt | 23 - .../common}/CMakeLists.txt | 6 +- boards/arm/stm32l1/common/Kconfig | 6 + .../Make.defs => stm32l1/common/Makefile} | 33 +- .../nucleo-l152re}/CMakeLists.txt | 2 +- .../{stm32 => stm32l1}/nucleo-l152re/Kconfig | 0 .../nucleo-l152re/configs/lcd/defconfig | 2 +- .../nucleo-l152re/configs/nsh/defconfig | 2 +- .../nucleo-l152re/include/board.h | 2 +- .../nucleo-l152re}/scripts/Make.defs | 2 +- .../nucleo-l152re/scripts/ld.script | 2 +- .../nucleo-l152re/src/CMakeLists.txt | 2 +- .../nucleo-l152re/src/Make.defs | 2 +- .../nucleo-l152re/src/nucleo-l152re.h | 2 +- .../nucleo-l152re/src/stm32_autoleds.c | 2 +- .../nucleo-l152re/src/stm32_boot.c | 2 +- .../nucleo-l152re/src/stm32_buttons.c | 2 +- .../nucleo-l152re/src/stm32_ili93418b.c | 2 +- .../nucleo-l152re/src/stm32_spi.c | 2 +- .../nucleo-l152re/src/stm32_spisd.c | 2 +- .../nucleo-l152re/src/stm32_userleds.c | 2 +- .../stm32ldiscovery}/CMakeLists.txt | 2 +- .../stm32ldiscovery/Kconfig | 0 .../stm32ldiscovery/configs/chrono/defconfig | 2 +- .../stm32ldiscovery/configs/nsh/defconfig | 2 +- .../stm32ldiscovery/include/board.h | 2 +- .../stm32ldiscovery/scripts/Make.defs | 2 +- .../stm32ldiscovery/scripts/stm32l152rb.ld | 2 +- .../stm32ldiscovery/scripts/stm32l152rc.ld | 2 +- .../stm32ldiscovery/src/CMakeLists.txt | 2 +- .../stm32ldiscovery/src/Make.defs | 2 +- .../stm32ldiscovery/src/stm32_autoleds.c | 2 +- .../stm32ldiscovery/src/stm32_boot.c | 2 +- .../stm32ldiscovery/src/stm32_bringup.c | 2 +- .../stm32ldiscovery/src/stm32_buttons.c | 2 +- .../stm32ldiscovery/src/stm32_lcd.c | 2 +- .../stm32ldiscovery/src/stm32_pwm.c | 2 +- .../stm32ldiscovery/src/stm32_spi.c | 2 +- .../stm32ldiscovery/src/stm32_userleds.c | 2 +- .../stm32ldiscovery/src/stm32ldiscovery.h | 2 +- tools/ci/testlist/arm-08.dat | 23 +- tools/ci/testlist/arm-09.dat | 16 +- tools/ci/testlist/arm-10.dat | 14 +- tools/ci/testlist/arm-11.dat | 16 +- tools/ci/testlist/arm-12.dat | 8 +- tools/ci/testlist/macos.dat | 2 +- tools/ci/testlist/msys2.dat | 4 +- tools/ci/testlist/windows.dat | 4 +- 175 files changed, 3328 insertions(+), 11152 deletions(-) delete mode 100644 arch/arm/include/stm32/chip.h create mode 100644 arch/arm/include/stm32l1/chip.h rename arch/arm/include/{stm32/stm32l15xxx_irq.h => stm32l1/irq.h} (90%) delete mode 100644 arch/arm/src/stm32/CMakeLists.txt delete mode 100644 arch/arm/src/stm32/Kconfig delete mode 100644 arch/arm/src/stm32/hardware/stm32f10xxx_uart.h delete mode 100644 arch/arm/src/stm32/hardware/stm32f20xxx_uart.h delete mode 100644 arch/arm/src/stm32/hardware/stm32f30xxx_uart.h delete mode 100644 arch/arm/src/stm32/hardware/stm32f40xxx_uart.h delete mode 100644 arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h delete mode 100644 arch/arm/src/stm32/hardware/stm32l15xxx_uart.h delete mode 100644 arch/arm/src/stm32/stm32_pm.h delete mode 100644 arch/arm/src/stm32/stm32_rcc.h delete mode 100644 arch/arm/src/stm32/stm32_userspace.h rename {boards/arm/stm32/mikroe-stm32f4 => arch/arm/src/stm32l1}/CMakeLists.txt (84%) create mode 100644 arch/arm/src/stm32l1/Kconfig rename arch/arm/src/{stm32 => stm32l1}/Make.defs (64%) rename arch/arm/src/{stm32/stm32_start.h => stm32l1/chip.h} (64%) create mode 100644 arch/arm/src/stm32l1/hardware/stm32_memorymap.h create mode 100644 arch/arm/src/stm32l1/hardware/stm32_pinmap.h rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_aes.h (99%) rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_gpio.h (99%) rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_memorymap.h (99%) rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_pinmap.h (99%) rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_rcc.h (99%) rename arch/arm/src/{stm32 => stm32l1}/hardware/stm32l15xxx_syscfg.h (99%) rename arch/arm/src/{stm32/stm32_lowputc.h => stm32l1/stm32.h} (54%) create mode 100644 arch/arm/src/stm32l1/stm32_rcc.c rename arch/arm/src/{stm32 => stm32l1}/stm32l15xxx_alarm.h (99%) rename arch/arm/src/{stm32 => stm32l1}/stm32l15xxx_rcc.c (99%) delete mode 100644 boards/arm/stm32/nucleo-f103rb/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f207zg/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f207zg/scripts/Make.defs delete mode 100644 boards/arm/stm32/nucleo-f302r8/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f302r8/scripts/Make.defs delete mode 100644 boards/arm/stm32/nucleo-f303re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f303ze/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f334r8/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f334r8/scripts/Make.defs delete mode 100644 boards/arm/stm32/nucleo-f401re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f410rb/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f411re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f412zg/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f429zi/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-f446re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-g431kb/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-g431rb/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-g474re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-g474re/scripts/Make.defs delete mode 100644 boards/arm/stm32/nucleo-l152re/CMakeLists.txt delete mode 100644 boards/arm/stm32/nucleo-l152re/scripts/Make.defs delete mode 100644 boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs delete mode 100644 boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt delete mode 100644 boards/arm/stm32/olimexino-stm32/CMakeLists.txt delete mode 100644 boards/arm/stm32/omnibusf4/CMakeLists.txt delete mode 100644 boards/arm/stm32/shenzhou/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm3210e-eval/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm3220g-eval/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm3220g-eval/scripts/Make.defs delete mode 100644 boards/arm/stm32/stm3240g-eval/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm3240g-eval/scripts/Make.defs delete mode 100644 boards/arm/stm32/stm32_tiny/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32butterfly2/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f103-minimum/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f334-disco/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f334-disco/scripts/Make.defs delete mode 100644 boards/arm/stm32/stm32f3discovery/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f3discovery/scripts/Make.defs delete mode 100644 boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f411-minimum/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f411e-disco/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f429i-disco/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld delete mode 100644 boards/arm/stm32/stm32f4discovery/scripts/Make.defs delete mode 100644 boards/arm/stm32/stm32ldiscovery/CMakeLists.txt delete mode 100644 boards/arm/stm32/stm32vldiscovery/CMakeLists.txt delete mode 100644 boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt rename boards/arm/{stm32/et-stm32-stamp => stm32l1/common}/CMakeLists.txt (86%) create mode 100644 boards/arm/stm32l1/common/Kconfig rename boards/arm/{stm32/nucleo-f303re/scripts/Make.defs => stm32l1/common/Makefile} (51%) rename boards/arm/{stm32/hymini-stm32v => stm32l1/nucleo-l152re}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/Kconfig (100%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/configs/lcd/defconfig (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/include/board.h (99%) rename boards/arm/{stm32/nucleo-f303ze => stm32l1/nucleo-l152re}/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/scripts/ld.script (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/Make.defs (96%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/nucleo-l152re.h (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_autoleds.c (97%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_boot.c (99%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_ili93418b.c (99%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_spisd.c (98%) rename boards/arm/{stm32 => stm32l1}/nucleo-l152re/src/stm32_userleds.c (97%) rename boards/arm/{stm32/fire-stm32v2 => stm32l1/stm32ldiscovery}/CMakeLists.txt (95%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/Kconfig (100%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/configs/chrono/defconfig (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/configs/nsh/defconfig (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/include/board.h (99%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/scripts/Make.defs (97%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/scripts/stm32l152rb.ld (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/scripts/stm32l152rc.ld (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/CMakeLists.txt (96%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/Make.defs (96%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_autoleds.c (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_boot.c (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_bringup.c (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_buttons.c (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_lcd.c (99%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_pwm.c (98%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_spi.c (99%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32_userleds.c (97%) rename boards/arm/{stm32 => stm32l1}/stm32ldiscovery/src/stm32ldiscovery.h (99%) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index d6832ccd151..3528e51466d 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -962,20 +962,21 @@ arch/arm/include/samv7/samv71_irq.h alin.jerpelea@sony.com petro.karashchenko@gm arch/arm/include/setjmp.h david.s.alessio@gmail.com alin.jerpelea@sony.com guowei15@xiaomi.com xiaoxiang@xiaomi.com huangqi3@xiaomi.com arch/arm/include/spinlock.h alin.jerpelea@sony.com anchao.archer@bytedance.com xiaoxiang@xiaomi.com hujun5@xiaomi.com arch/arm/include/stdarg.h alin.jerpelea@sony.com guoshichao@xiaomi.com -arch/arm/include/stm32/chip.h raiden00pl@gmail.com 59230071+hartmannathan@users.noreply.github.com paul-a.patience@polymtl.ca -arch/arm/include/stm32/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me -arch/arm/include/stm32/stm32f10xxx_irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net -arch/arm/include/stm32/stm32f20xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f30xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f33xxx_irq.h 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com -arch/arm/include/stm32/stm32f37xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com -arch/arm/include/stm32/stm32f40xxx_irq.h gwenj@trabucayre.com paul-a.patience@polymtl.ca david_s5@usa.net alin.jerpelea@sony.com -arch/arm/include/stm32/stm32g4xxxx_irq.h raiden00@railab.me alin.jerpelea@sony.com devel@sumpfralle.de gustavo.nihei@espressif.com -arch/arm/include/stm32/stm32l15xxx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com xiaoxiang@xiaomi.com arch/arm/include/stm32c0/chip.h raiden00@railab.me arch/arm/include/stm32c0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com arch/arm/include/stm32f0/chip.h raiden00@railab.me juha.niskanen@haltian.com dave@marples.net acassis@gmail.com arch/arm/include/stm32f0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com peter.barada@gmail.com +arch/arm/include/stm32f1/chip.h raiden00@railab.me +arch/arm/include/stm32f1/irq.h raiden00@railab.me alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net peter.barada@gmail.com +arch/arm/include/stm32f2/chip.h raiden00@railab.me +arch/arm/include/stm32f2/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com +arch/arm/include/stm32f3/chip.h raiden00@railab.me +arch/arm/include/stm32f3/irq.h raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com mijung@gmx.net simon@leitwert.ch +arch/arm/include/stm32f3/stm32f30xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f3/stm32f33xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00pl@gmail.com alin.jerpelea@sony.com raiden00@railab.me +arch/arm/include/stm32f3/stm32f37xxx_irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com raiden00@railab.me peter.barada@gmail.com +arch/arm/include/stm32f4/chip.h raiden00@railab.me +arch/arm/include/stm32f4/irq.h david_s5@usa.net gwenj@trabucayre.com paul-a.patience@polymtl.ca alin.jerpelea@sony.com raiden00@railab.me arch/arm/include/stm32f7/chip.h david_s5@usa.net alin.jerpelea@sony.com bob.feretich@rafresearch.com dave@marples.net arch/arm/include/stm32f7/irq.h alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com bob.feretich@rafresearch.com david_s5@usa.net arch/arm/include/stm32f7/stm32f72xx73xx_irq.h bob.feretich@rafresearch.com alin.jerpelea@sony.com 59230071+hartmannathan@users.noreply.github.com gustavo.nihei@espressif.com @@ -983,6 +984,8 @@ arch/arm/include/stm32f7/stm32f74xx75xx_irq.h alin.jerpelea@sony.com 59230071+ha arch/arm/include/stm32f7/stm32f76xx77xx_irq.h 59230071+hartmannathan@users.noreply.github.com david_s5@usa.net alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32g0/chip.h raiden00@railab.me arch/arm/include/stm32g0/irq.h raiden00pl@gmail.com dpo@certi.org.br raiden00@railab.me 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com +arch/arm/include/stm32g4/chip.h raiden00@railab.me +arch/arm/include/stm32g4/irq.h 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com devel@sumpfralle.de arch/arm/include/stm32h5/chip.h kwilson@2g-eng.com tbennett@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/irq.h kwilson@2g-eng.com alin.jerpelea@sony.com arch/arm/include/stm32h5/stm32h5xx_irq.h kwilson@2g-eng.com alin.jerpelea@sony.com @@ -994,6 +997,8 @@ arch/arm/include/stm32h7/stm32h7x5xx_irq.h raiden00@railab.me alin.jerpelea@sony arch/arm/include/stm32h7/stm32h7x7xx_irq.h 59230071+hartmannathan@users.noreply.github.com lwazeh@gmail.com alin.jerpelea@sony.com gustavo.nihei@espressif.com arch/arm/include/stm32l0/chip.h raiden00@railab.me arch/arm/include/stm32l0/irq.h raiden00pl@gmail.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com 59230071+hartmannathan@users.noreply.github.com +arch/arm/include/stm32l1/chip.h raiden00@railab.me +arch/arm/include/stm32l1/irq.h david_s5@usa.net 59230071+hartmannathan@users.noreply.github.com raiden00@railab.me alin.jerpelea@sony.com peter.barada@gmail.com arch/arm/include/stm32l4/chip.h juha.niskanen@haltian.com sebastien@lorquet.fr dave@marples.net alin.jerpelea@sony.com arch/arm/include/stm32l4/irq.h sebastien@lorquet.fr 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com juha.niskanen@haltian.com arch/arm/include/stm32l4/stm32l4x3xx_irq.h juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com alin.jerpelea@sony.com daniel.carvalho@ufu.br @@ -1550,6 +1555,342 @@ arch/arm/src/common/gnu/fork.S guoshichao@xiaomi.com yanghuatao@xiaomi.com liaoa arch/arm/src/common/hwcap.h liaoao@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/arm_fetchadd.S xiaoxiang@xiaomi.com alin.jerpelea@sony.com arch/arm/src/common/iar/fork.S guoshichao@xiaomi.com alin.jerpelea@sony.com +arch/arm/src/common/stm32/Kconfig raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.adc raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.ble raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.cache raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.can raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.comp raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dac raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dfsdm raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dma raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.dts raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.eth raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.fdcan raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.flash raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.foc raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.gpio raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.have raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.hciuart raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.hrtim raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.i2c raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.ipcc raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.lpuart raiden00@railab.me +arch/arm/src/common/stm32/Kconfig.ltdc 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masayuki.ishikawa@gmail.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1289.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_ssd1351.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_st7032.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_st7567.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_st7789.c acassis@gmail.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_sx127x.c acassis@gmail.com alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_timer.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864ambag01.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_ug2864hsweg01.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_usb.c alin.jerpelea@sony.com anchao@xiaomi.com petro.karashchenko@gmail.com xiaoxiang@xiaomi.com devel@sumpfralle.de +boards/arm/stm32f4/stm32f4discovery/src/stm32_usbmsc.c alin.jerpelea@sony.com raiden00@railab.me +boards/arm/stm32f4/stm32f4discovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f4/stm32f4discovery/src/stm32_w5500.c acassis@gmail.com alin.jerpelea@sony.com +boards/arm/stm32f4/stm32f4discovery/src/stm32f4discovery.h alin.jerpelea@sony.com acassis@gmail.com mnitsche@dc.uba.ar masayuki.ishikawa@gmail.com xiaoxiang@xiaomi.com +boards/arm/stm32l1/stm32ldiscovery/Kconfig alin.jerpelea@sony.com juha.niskanen@haltian.com +boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32l1/stm32ldiscovery/include/board.h alin.jerpelea@sony.com juha.niskanen@haltian.com devel@sumpfralle.de xiaoxiang@xiaomi.com anthony@vergeaero.com +boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_appinit.c alin.jerpelea@sony.com juha.niskanen@haltian.com 59230071+hartmannathan@users.noreply.github.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c alin.jerpelea@sony.com juha.niskanen@haltian.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c alin.jerpelea@sony.com juha.niskanen@haltian.com xiaoxiang@xiaomi.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c alin.jerpelea@sony.com juha.niskanen@haltian.com gustavo.nihei@espressif.com xiaoxiang@xiaomi.com mnitsche@dc.uba.ar +boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c alin.jerpelea@sony.com yamamoto@midokura.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com augustofg96@gmail.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h alin.jerpelea@sony.com mnitsche@dc.uba.ar juha.niskanen@haltian.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/Kconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com liguiding1@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/include/board.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu +boards/arm/stm32f1/stm32vldiscovery/scripts/stm32vldiscovery.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_appinit.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32_leds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/Kconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/highpri/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/netnsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com acassis@gmail.com f.panag@amco.gr +boards/arm/stm32f1/viewtool-stm32f107/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/configs/tcpblaster/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com dongjiuzhu1@xiaomi.com acassis@gmail.com f.panag@amco.gr +boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f103vct6.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com devel@sumpfralle.de thomas.narayana-swamy@wandercraft.eu anthony@vergeaero.com +boards/arm/stm32f1/viewtool-stm32f107/include/board-stm32f107vct6.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu hartman.nathan@gmail.com anthony@vergeaero.com +boards/arm/stm32f1/viewtool-stm32f107/include/board.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com thomas.narayana-swamy@wandercraft.eu +boards/arm/stm32f1/viewtool-stm32f107/scripts/dfu.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/scripts/flash.ld alin.jerpelea@sony.com no1wudi@qq.com cuiziwei@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ads7843e.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_appinit.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com 59230071+hartmannathan@users.noreply.github.com hartman.nathan@gmail.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_boot.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_bringup.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com mnitsche@dc.uba.ar raiden00@railab.me +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_buttons.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_can.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ft80x.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c alin.jerpelea@sony.com yamamoto@midokura.com buxiasen@xiaomi.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_leds.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_max3421e.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com anchao@xiaomi.com petro.karashchenko@gmail.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_mmcsd.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_spi.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_ssd1289.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com juha.niskanen@haltian.com gustavo.nihei@espressif.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbdev.c alin.jerpelea@sony.com xiaoxiang@xiaomi.com +boards/arm/stm32f1/viewtool-stm32f107/src/stm32_usbmsc.c alin.jerpelea@sony.com +boards/arm/stm32f1/viewtool-stm32f107/src/viewtool_stm32f107.h alin.jerpelea@sony.com xiaoxiang@xiaomi.com petro.karashchenko@gmail.com thomas.narayana-swamy@wandercraft.eu raiden00@railab.me boards/arm/stm32l0/b-l072z-lrwan1/Kconfig alin.jerpelea@sony.com boards/arm/stm32l0/b-l072z-lrwan1/configs/adc/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com boards/arm/stm32l0/b-l072z-lrwan1/configs/nsh/defconfig alin.jerpelea@sony.com xiaoxiang@xiaomi.com liguiding1@xiaomi.com dongjiuzhu1@xiaomi.com diff --git a/Documentation/applications/examples/ft80x/index.rst b/Documentation/applications/examples/ft80x/index.rst index 9020d67baf0..e093218737a 100644 --- a/Documentation/applications/examples/ft80x/index.rst +++ b/Documentation/applications/examples/ft80x/index.rst @@ -4,4 +4,4 @@ This examples has ports of several FTDI demos for the FTDI/BridgeTek FT80x GUI chip. As an example configuration, see -``nuttx/boards/arm/stm32/viewtool-stm32f107/configs/ft80x/defconfig``. +``nuttx/boards/arm/stm32f1/viewtool-stm32f107/configs/ft80x/defconfig``. diff --git a/Documentation/applications/system/usbmsc/index.rst b/Documentation/applications/system/usbmsc/index.rst index 57da5b30358..f387859f0ca 100644 --- a/Documentation/applications/system/usbmsc/index.rst +++ b/Documentation/applications/system/usbmsc/index.rst @@ -13,7 +13,7 @@ This function will be called by the ``system/usbmsc`` indirectly via the ``board block device drivers. For examples of the implementation of ``board_usbmsc_initialize()`` see ``boards/arm/lpc214x/mcu123-lpc214x/src/up_usbmsc.c`` or -``boards/arm/stm32/stm3210e-eval/src/usbmsc.c``. +``boards/arm/stm32f1/stm3210e-eval/src/usbmsc.c``. Configuration options: diff --git a/Documentation/components/drivers/character/leds/userled.rst b/Documentation/components/drivers/character/leds/userled.rst index dd8ae215ccb..feccbcb4c7d 100644 --- a/Documentation/components/drivers/character/leds/userled.rst +++ b/Documentation/components/drivers/character/leds/userled.rst @@ -59,7 +59,7 @@ Files supporting USERLED can be found in the following locations: Something important to note is that your board initialization code (normally named ``_bringup.c`` should call the function to register the driver. -For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: +For stm32f4discovery board this initialization code is placed at ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` and this is the block responsible to initialize the subsystem: .. code-block:: C diff --git a/Documentation/components/drivers/character/serial.rst b/Documentation/components/drivers/character/serial.rst index 3b80938ba7c..d0349aec3f0 100644 --- a/Documentation/components/drivers/character/serial.rst +++ b/Documentation/components/drivers/character/serial.rst @@ -67,7 +67,7 @@ Serial Device Drivers `character drivers <#chardrivers>`__ and are accessed as other character drivers. -- **Examples**: ``arch/arm/src/stm32/stm32_serial.c``, +- **Examples**: ``arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c``, ``arch/arm/src/lpc214x/lpc214x_serial.c``, ``arch/z16/src/z16f/z16f_serial.c``, etc. diff --git a/Documentation/components/drivers/special/lcd.rst b/Documentation/components/drivers/special/lcd.rst index 3e415e19694..5417a2a1bb9 100644 --- a/Documentation/components/drivers/special/lcd.rst +++ b/Documentation/components/drivers/special/lcd.rst @@ -85,7 +85,7 @@ LCDs Generic LCD driver for LCDs based on the Solomon Systech SSD1289 LCD controller. Think of this as a template for an LCD driver that you will probably have to customize for any particular LCD - hardware. (See also boards/arm/stm32/hymini-stm32v/src/ssd1289.c below). + hardware. (See also boards/arm/stm32f1/hymini-stm32v/src/ssd1289.c below). - ``st7567.c`` @@ -120,7 +120,7 @@ OLEDs OLED Display Module, UUG-2864AMBAG01, Univision Technology Inc. Based on the SH1101A controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/lpc214x/zp214xpa - ``ug-9664hswag01.c`` @@ -140,7 +140,7 @@ OLEDs Densitron Technologies DD-12864WO-4A which is based on SSD1309 LCD controller. Example usage:: - boards/arm/stm32/stm32f4discovery + boards/arm/stm32f4/stm32f4discovery boards/arm/sam34/sam4l-xplained Segment LCDS (SLCDs) diff --git a/Documentation/components/drivers/special/sdio.rst b/Documentation/components/drivers/special/sdio.rst index 6822b82d388..ba62f204957 100644 --- a/Documentation/components/drivers/special/sdio.rst +++ b/Documentation/components/drivers/special/sdio.rst @@ -29,7 +29,7 @@ SDIO Device Drivers #. Provide that instance to the initialization method of the higher level device driver. -- **Examples**: ``arch/arm/src/stm32/stm32_sdio.c`` and +- **Examples**: ``arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c`` and ``drivers/mmcsd/mmcsd_sdio.c`` Implementing an SDIO lower-half diff --git a/Documentation/components/drivers/special/usbdev.rst b/Documentation/components/drivers/special/usbdev.rst index 589a60b7b7f..1b83d9a20d7 100644 --- a/Documentation/components/drivers/special/usbdev.rst +++ b/Documentation/components/drivers/special/usbdev.rst @@ -19,7 +19,7 @@ USB Device-Side Drivers ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbdev.c``, ``arch/arm/src/lpc214x/lpc214x_usbdev.c``, ``arch/arm/src/lpc313x/lpc313x_usbdev.c``, and - ``arch/arm/src/stm32/stm32_usbdev.c``. + ``arch/arm/src/common/stm32/stm32_usbdev_m3m4_v1.c``. - ``struct usbdevclass_driver_s``. Each USB device class driver must implement an instance of diff --git a/Documentation/components/drivers/special/usbhost.rst b/Documentation/components/drivers/special/usbhost.rst index 63077758d10..078677d5e29 100644 --- a/Documentation/components/drivers/special/usbhost.rst +++ b/Documentation/components/drivers/special/usbhost.rst @@ -17,7 +17,7 @@ USB Host-Side Drivers **Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``, - ``arch/arm/src/stm32/stm32_otgfshost.c``, + ``arch/arm/src/common/stm32/stm32_otgfshost_m3m4_v1.c``, ``arch/arm/src/sama5/sam_ohci.c``, and ``arch/arm/src/sama5/sam_ehci.c``. diff --git a/Documentation/contributing/making-changes.rst b/Documentation/contributing/making-changes.rst index a60182210b4..7cbe6cb0add 100644 --- a/Documentation/contributing/making-changes.rst +++ b/Documentation/contributing/making-changes.rst @@ -227,7 +227,7 @@ squash before submitting the Pull Request: .. code-block:: bash - arch/arm/stm32/: Add arch support for stm32 platform + arch/arm/stm32f4/: Add arch support for stm32f4 platform This patch adds initial support for stm32 platform. Please read the documentation included for more details how to wire the display. diff --git a/Documentation/guides/changing_systemclockconfig.rst b/Documentation/guides/changing_systemclockconfig.rst index 872415486eb..0b5039ee2ce 100644 --- a/Documentation/guides/changing_systemclockconfig.rst +++ b/Documentation/guides/changing_systemclockconfig.rst @@ -28,7 +28,7 @@ Custom Clock Configuration The ``configs/vsn/`` configuration does something like you say. It skips the initial clock configuration by defining ``CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=y``. Then the normal clock -configuration logic in ``arch/arm/src/stm32/stm32_rcc.c`` is not executed. +configuration logic in ``arch/arm/src/stm32f4/stm32_rcc.c`` is not executed. Instead, the "custom" clock initialization at ``configs/vsn/src/sysclock.c`` is called: @@ -83,7 +83,7 @@ are hardcoded in the board.h header file. So you have two options: 2. **Variable Peripheral Clocking**. You can make the peripheral clocking variable. I had to do this for the SAMA5Dx family. Look at - ``boards/arm/stm32/sama5d4-ek/include/board_sdram.h`` for example. Notice + ``boards/arm/sama5/sama5d4-ek/include/board_sdram.h`` for example. Notice that the frequencies are not constants, but function calls: .. code-block:: c diff --git a/Documentation/guides/etcromfs.rst b/Documentation/guides/etcromfs.rst index 8bc92ef989e..39ce17bddd2 100644 --- a/Documentation/guides/etcromfs.rst +++ b/Documentation/guides/etcromfs.rst @@ -86,7 +86,7 @@ behave as follows at Nuttx start-up time: ``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might provide useful examples: - - ``boards/arm/stm32/hymini-stm32v/nsh2`` + - ``boards/arm/stm32f1/hymini-stm32v/nsh2`` - ``boards/arm/dm320/ntosd-dm320/nsh`` - ``boards/sim/sim/sim/nsh`` - ``boards/sim/sim/sim/nsh2`` diff --git a/Documentation/guides/ipv6.rst b/Documentation/guides/ipv6.rst index d67c30c5189..bf02bc57f81 100644 --- a/Documentation/guides/ipv6.rst +++ b/Documentation/guides/ipv6.rst @@ -218,7 +218,7 @@ Board Configurations At present, there are three board configuration that are pre-configured to use IPv6: ``nuttx/boards/arm/tiva/dk-tm4c129x/configs/ipv6``, -``nuttx/boards/arm/stm32/stm32f4discovery/ipv6``, and +``nuttx/boards/arm/stm32f4/stm32f4discovery/ipv6``, and ``nuttx/boards/arm/tiva/tm4c1294-launchpad/configs/ipv6``. These default configurations have only IPv6 enabled. But the `README` files at in those board directories describes how to enable `both` IPv4 and IPv6 simultaneously. @@ -345,4 +345,4 @@ the network utils (``netutils``). * Netutils: The network utilities in ``apps/netutils`` have been adapted to work with IPv6: DHCP, FTP, TFTP, Telnet, etc. Support for managing IPv6 address have been included in the ``netlib``, but nothing else has yet been - updated. \ No newline at end of file + updated. diff --git a/Documentation/guides/nsh_network_link_management.rst b/Documentation/guides/nsh_network_link_management.rst index 3100f7ba7d8..05cc4f9d419 100644 --- a/Documentation/guides/nsh_network_link_management.rst +++ b/Documentation/guides/nsh_network_link_management.rst @@ -45,7 +45,7 @@ must be satisfied: are implemented for Atmel SAM4/4, SAMA5 families, and for the STMicro STM32. See ``nuttx/arch/arm/src/sam34/sam_emac.c``, ``nuttx/arch/arm/src/sam34/sam_emaca.c``, ``sam_emacb.c``, and ``sam_gmac.c``, - and ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + and ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. - ``CONFIG_ARCH_PHY_INTERRUPT`` This is not a user-selectable option. Rather, it is set when selecting a board that supports PHY interrupts. In most architectures, the PHY interrupt is not diff --git a/Documentation/guides/ofloader.rst b/Documentation/guides/ofloader.rst index 743fb9d1328..4dfe2375dc9 100644 --- a/Documentation/guides/ofloader.rst +++ b/Documentation/guides/ofloader.rst @@ -52,7 +52,7 @@ Precautions 1.If you need to implement the ofloader on a different board, you will need to read the `wiki ` and refer to the implementation of "ofloader.ld" linker script located -in the "boards/arm/stm32/stm32f429i-disco/scripts" directory. +in the "boards/arm/stm32f4/stm32f429i-disco/scripts" directory. This linker script defines how the different sections of the NuttX image are placed in memory. You should configure the corresponding sections to be located in RAM, where the J-Link can write the image correctly. diff --git a/Documentation/guides/partially_linked_elf.rst b/Documentation/guides/partially_linked_elf.rst index 0fe721e69ed..b2b6ee8f307 100644 --- a/Documentation/guides/partially_linked_elf.rst +++ b/Documentation/guides/partially_linked_elf.rst @@ -40,7 +40,7 @@ compatible with the example provided here: In this example, let's illustrate this using an STM32F4-Discovery configuration. We will assume that you have modified the - ``boards/arm/stm32/stm32fdiscovery/src/stm32_bringup.c`` file, adding the + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_bringup.c`` file, adding the following: .. code-block:: c diff --git a/Documentation/guides/port_drivers_to_stm32f7.rst b/Documentation/guides/port_drivers_to_stm32f7.rst index e7c04a2f3e3..876d184242f 100644 --- a/Documentation/guides/port_drivers_to_stm32f7.rst +++ b/Documentation/guides/port_drivers_to_stm32f7.rst @@ -191,7 +191,7 @@ An Example There is a good example in the STM32 Ethernet driver. The STM32 F7 Ethernet driver (``arch/arm/src/stm32f7/stm32_ethernet.c``) derives directly from the STM32 F4 Ethernet driver -(``arch/arm/src/stm32/stm32_eth.c``). These two Ethernet MAC peripherals +(``arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``). These two Ethernet MAC peripherals are nearly identical. Only changes that are a direct consequence of the STM32 F7 D-Cache were required to make the driver work on the STM32 F7. Those changes are summarized below. diff --git a/Documentation/guides/protected_build.rst b/Documentation/guides/protected_build.rst index e2a60713a3a..a49702df5c7 100644 --- a/Documentation/guides/protected_build.rst +++ b/Documentation/guides/protected_build.rst @@ -177,10 +177,10 @@ Files and Directories Here is a summary of directories and files used by the STM32F4Discovery protected build: -* ``boards/arm/stm32/stm32f4discovery/configs/kostest``. This is the kernel +* ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. This is the kernel mode OS test configuration. The two standard configuration files can be found in this directory: (1) ``defconfig`` and (2) ``Make.defs``. -* ``boards/arm/stm32/stm32f4discovery/kernel``. This is the first past +* ``boards/arm/stm32f4/stm32f4discovery/kernel``. This is the first past build directory. The Makefile in this directory is invoked to produce the pass1 object (``nuttx_user.elf`` in this case). The second pass object is created by ``arch/arm/src/Makefile``. Also @@ -188,7 +188,7 @@ protected build: contains a header that includes information need by the kernel blob in order to interface with the user-code. That header is defined in by this file. -* ``boards/arm/stm32/stm32f4discovery/scripts``. Linker scripts for +* ``boards/arm/stm32f4/stm32f4discovery/scripts``. Linker scripts for the kernel mode build are found in this directory. This includes (1) ``memory.ld`` which hold the common memory map, (2) ``user-space.ld`` that is used for linking the pass1 user-mode blob, and (3) @@ -314,11 +314,11 @@ Comparing the "Flat" Build Configuration with the Protected Build Configuration =============================================================================== Compare, for example the configuration -``boards/arm/stm32/stm32f4discovery/configs/ostest`` and the -configuration ``boards/arm/stm32/stm32f4discovery/configs/kostest``. +``boards/arm/stm32f4/stm32f4discovery/configs/ostest`` and the +configuration ``boards/arm/stm32f4/stm32f4discovery/configs/kostest``. These two configurations are identical except that one builds a "flat" version of OS test and the other builds a kernel version -of the OS test. See the file ``boards/arm/stm32/stm32f4discovery/README.txt`` +of the OS test. See the file ``boards/arm/stm32f4/stm32f4discovery/README.txt`` for more details about those configurations. The configurations can be compared using the ``cmpconfig`` tool: @@ -328,7 +328,7 @@ The configurations can be compared using the ``cmpconfig`` tool: cd tools make -f Makefile.host cmpconfig cd .. - tools/cmpconfig boards/arm/stm32/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32/stm32f4discovery/configs/kostest/defconfig + tools/cmpconfig boards/arm/stm32f4/stm32f4discovery/configs/ostest/defconfig boards/arm/stm32f4/stm32f4discovery/configs/kostest/defconfig Here is a summary of the meaning of all of the important differences in the configurations. This should be enough information for you to convert any @@ -337,7 +337,7 @@ configuration from a "flat" to a protected build: * ``CONFIG_BUILD_2PASS=y``. This enables the two pass build. * ``CONFIG_BUILD_PROTECTED=y``. This option enables the "two pass" protected build. -* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32/stm32f4discovery/kernel"``. +* ``CONFIG_PASS1_BUILDIR="boards/arm/stm32f4/stm32f4discovery/kernel"``. This tells the build system the (relative) location of the pass1 build directory. * ``CONFIG_PASS1_OBJECT=""``. In some "two pass" build configurations, the build system need to know the name of the first pass object. @@ -382,7 +382,7 @@ configuration from a "flat" to a protected build: These includes such things as initializing device drivers. These same initialization steps must be performed in kernel mode for the protected build and ``CONFIG_BOARD_LATE_INITIALIZE``. - See ``boards/arm/stm32/stm32f4discovery/src/up_boot.c`` for an + See ``boards/arm/stm32f4/stm32f4discovery/src/up_boot.c`` for an example of such board initialization code. Architecture-Specific Options: @@ -409,8 +409,8 @@ Size Expansion The protected build will, or course, result in a FLASH image that is larger than that of the corresponding "flat" build. How much larger? I don't have the numbers in hand, but you can build -``boards/arm/stm32/stm32f4discovery/configs/nsh`` and -``boards/arm/stm32/stm32f4discovery/configs/kostest`` and compare +``boards/arm/stm32f4/stm32f4discovery/configs/nsh`` and +``boards/arm/stm32f4/stm32f4discovery/configs/kostest`` and compare the resulting binaries for yourself using the ``size`` command. Increases in size are expected because: diff --git a/Documentation/guides/smaller_vector_tables.rst b/Documentation/guides/smaller_vector_tables.rst index 2cc629fa2a5..ed44b0432d2 100644 --- a/Documentation/guides/smaller_vector_tables.rst +++ b/Documentation/guides/smaller_vector_tables.rst @@ -202,7 +202,7 @@ Most ARMv7-M architectures support two mechanism for handling interrupts: ``CONFIG_ARMV7M_CMNVECTOR=y`` that can be found in ``arch/arm/src/armv7-m/``, and * MCU-specific interrupt handling logic. For the - STM32, this logic can be found at ``arch/arm/src/stm32/gnu/stm32_vectors.S``. + STM32, this logic can be found at ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``. The `common` vector logic is slightly more efficient, the MCU-specific logic is slightly more flexible. @@ -229,7 +229,7 @@ This technical approach requires changes to three files: define ``only`` the small set of 20 ``mapped`` IRQ numbers in the range from 0 through 19. It would also set ``NR_IRQS`` to the value 20. -* A new header file at ``arch/arm/src/stm32/hardware``, say +* A new header file at ``arch/arm/src/stm32f4/hardware``, say ``xyz_vector.h``. It would be similar to the other vector definitions files in that directory: It will consist of a sequence of 100 ``VECTOR`` and ``UNUSED`` macros. It will @@ -248,7 +248,7 @@ This has all been replaced with the common vector handling at Vector Definitions ================== -In ``arch/arm/src/stm32/gnu/stm32_vector.S``, notice that the +In ``arch/arm/src/stm32f4/gnu/stm32_vectors.S``, notice that the ``xyz_vector.h`` file will be included twice. Before each inclusion, the macros ``VECTOR`` and ``UNUSED`` are defined. @@ -290,7 +290,7 @@ file like this: ... Where the value of ``STM32_IRQ_USART1`` was defined to -be 12 in the ``arch/arm/include/stm32/xyz_irq.h`` header +be 12 in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file. When ``xyz_vector.h`` is included by ``stm32_vectors.S`` with the above definitions for ``VECTOR`` and ``UNUSED``, the following would result: @@ -349,7 +349,7 @@ second time the ``xzy_vector.h`` is included by ``stm32_vectors.S``: In the above USART1 example, a single handler would be generated that will provide the IRQ number 12. Remember that 12 is the expansion of the macro ``STM32_IRQ_USART1`` -that is provided in the ``arch/arm/include/stm32/xyz_irq.h`` +that is provided in the ``arch/arm/include/stm32f4/xyz_irq.h`` header file: .. code-block:: asm diff --git a/Documentation/guides/stm32ccm.rst b/Documentation/guides/stm32ccm.rst index 4ec8ba5acb3..14148131805 100644 --- a/Documentation/guides/stm32ccm.rst +++ b/Documentation/guides/stm32ccm.rst @@ -34,7 +34,7 @@ This memory allocator is automatically enabled when the following options are se * ``CONFIG_MM_MULTIHEAP`` Support for multiple heaps is enabled. Under those conditions, the CCM memory allocator is enabled and the allocator -interfaces prototyped in the ``arch/arm/src/stm32/stm32_ccm.h`` are available. +interfaces prototyped in the ``arch/arm/src/common/stm32/stm32_ccm.h`` are available. NOTE: These interfaces are, technically, not prototyped since they are really provided via C pre-processor macros. diff --git a/Documentation/guides/usingkernelthreads.rst b/Documentation/guides/usingkernelthreads.rst index 5818842037a..434dacd62a0 100644 --- a/Documentation/guides/usingkernelthreads.rst +++ b/Documentation/guides/usingkernelthreads.rst @@ -52,7 +52,7 @@ In order to build the task into the OS as a kernel thread, you simply have to: (1) place the kernel thread code in your board source code directory, and (2) start it with ``kthread_create()`` in your board bring-up logic. There a few examples of this in the NuttX source tree. Here is one: -`https://github.com/apache/nuttx/blob/master/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri.c `_ +`https://github.com/apache/nuttx/blob/master/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri.c `_ So that is another trick that you can use to architecture optimal solutions: Create parts of your applications as kernel threads: They need to reside in diff --git a/Documentation/guides/zerolatencyinterrupts.rst b/Documentation/guides/zerolatencyinterrupts.rst index 7acd9352656..2a5f14e70c2 100644 --- a/Documentation/guides/zerolatencyinterrupts.rst +++ b/Documentation/guides/zerolatencyinterrupts.rst @@ -302,8 +302,8 @@ You can find an example that tests the high priority, nested interrupts in the N * :doc:`/platforms/arm/stm32f1/boards/viewtool-stm32f107/index` Description of the configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/highpri`` Test configuration +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/highpri`` Test configuration -* ``nuttx/boards/arm/stm32/viewtool-stm32f107/src/stm32_highpri`` Test +* ``nuttx/boards/arm/stm32f1/viewtool-stm32f107/src/stm32_highpri`` Test driver. diff --git a/Documentation/implementation/chip_h.rst b/Documentation/implementation/chip_h.rst index a2b71584126..2a9d9641986 100644 --- a/Documentation/implementation/chip_h.rst +++ b/Documentation/implementation/chip_h.rst @@ -12,16 +12,16 @@ If you wonder about the purpose of the two ``chip.h`` files in each arm chip. .. code:: sh $ find arch/arm -name chip.h | grep stm32 - arch/arm/include/stm32/chip.h - arch/arm/src/stm32/chip.h + arch/arm/include/stm32f4/chip.h + arch/arm/src/stm32f4/chip.h -The reason behind ``arch/arm/src/stm32/chip.h`` file was a bad idea +The reason behind ``arch/arm/src/stm32f4/chip.h`` file was a bad idea that happened a long time ago. Right now, I believe that its only required when ``CONFIG_ARMV7M_CMNVECTOR`` -is selected in the configuration. In that case, ``arch/arm/src/stm32/chip.h`` +is selected in the configuration. In that case, ``arch/arm/src/stm32f4/chip.h`` is included by ``arch/arm/src/armv7-m/up_vectors.c`` in order provide -the number of interrupt vectors. In stm32, ``arch/arm/src/stm32/chip.h`` +the number of interrupt vectors. In stm32, ``arch/arm/src/stm32f4/chip.h`` provides the number of vectors indirectly by including the correct, chip-specific vectors.h file. This function is a little more obvious in ``arch/arm/srch/lpc43xx/chip.h``. diff --git a/Documentation/implementation/file_descriptors.rst b/Documentation/implementation/file_descriptors.rst index dfad984a347..a54ffae2f04 100644 --- a/Documentation/implementation/file_descriptors.rst +++ b/Documentation/implementation/file_descriptors.rst @@ -135,7 +135,7 @@ Detached File Helpers Once the file structure has been detached from its file descriptor, you can no longer use the standard VFS functions ``read()``, ``write()``, ``ioctl()``, etc. Fortunately, there are a parallel set of interfaces -that can be used with detached files. These are decribed in detail +that can be used with detached files. These are described in detail in ``include/nuttx/fs/fs.h`` and only listed here below: .. code-block:: c @@ -153,8 +153,8 @@ in ``include/nuttx/fs/fs.h`` and only listed here below: int file_vfcntl(FAR struct file *filep, int cmd, va_list ap); -The SYLOG Device: A Case Study -============================== +The SYSLOG Device: A Case Study +=============================== This technique is used for the SYSLOG device. Originally, NuttX used file descriptor ``1`` for SYSLOG output by default. For most task groups, @@ -179,7 +179,7 @@ Other Examples There are some other examples in analog joystick lower half drivers that use the ADC character driver to read joystick positions:: - boards/arm/stm32/nucleo-f4x1re/src/stm32_ajoystick.c: + boards/arm/stm32f4/nucleo-f411re/src/stm32_ajoystick.c: ret = file_detach(fd, &g_adcfile); boards/arm/stm32l4/nucleo-l476rg/src/stm32_ajoystick.c: diff --git a/Documentation/implementation/nuttx_initialization_sequence.rst b/Documentation/implementation/nuttx_initialization_sequence.rst index 2538e7d3a4b..0c68e50e715 100644 --- a/Documentation/implementation/nuttx_initialization_sequence.rst +++ b/Documentation/implementation/nuttx_initialization_sequence.rst @@ -35,7 +35,7 @@ to any supported architecture. Here is the map of initialization function calls:: - __start()-arch/arm/src/stm32/stm32_start.c + __start()-arch/arm/src/common/stm32/stm32_start_m3m4_v1.c | +--*Set stack limit +--stm32_clockconfig() @@ -45,7 +45,7 @@ Here is the map of initialization function calls:: +--showprogress('A') +-- +-- - +--stm32_boardinitialize()-boards/arm/stm32/stm32f4discovery/src/stm32_boot.c + +--stm32_boardinitialize()-boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c | | | +--stm32_spidev_initialize()-stm32_spi.c:ONLY CHIP SELECTS | +--stm32_usbinitialize()- @@ -196,7 +196,7 @@ There are few important things to note about this file. ``.section .vectors, ax``. This pseudo operation will place all of the vectors into a special section call ``.vectors``. On of the STM32 F4 linker scripts is located at -``nuttx/boards/arm/stm32/stm32f4discovery/scripts/ld.script``. +``nuttx/boards/arm/stm32f4/stm32f4discovery/scripts/ld.script``. In that file, you can see that section ``.vectors`` is forced to lie at the very beginning of FLASH memory. The STM32 F4 can be configured to boot in different ways via strapping. @@ -229,7 +229,7 @@ nuttx/arch/arm/src/stm32_start.c ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ The reset vector ``__start`` lies in the file -``nuttx/arch/arm/src/stm32/stm32_start.c`` and does the real, +``nuttx/arch/arm/src/common/stm32/stm32_start_m3m4_v1.c`` and does the real, low-level architecture-specific initialization. This initialization includes: 1. ``stm32_clockconfig()`` - Initialize the PLLs and peripheral clocking @@ -262,7 +262,7 @@ low-level architecture-specific initialization. This initialization includes: 7. ``stm32_boardinitialize()`` - Board-specific logic is initialized by calling this function. For the case of the STM32F4Discovery board, this logic can be found at - ``nuttx/boards/arm/stm32/stm32f4discovery/src/stm32_boot.c`` and does + ``nuttx/boards/arm/stm32f4/stm32f4discovery/src/stm32_boot.c`` and does the following operations: a. ``stm32_spidev_initialize()`` - Initialize SPI chip selects @@ -351,19 +351,19 @@ file and in that case those operations are not performed: ``nx_start()``. However, if the board supports multiple, discontiguous memory regions, any addition memory regions can be added to the heap by this function. For the STM32 F4, ``up_addregion()`` is implemented - in ``nuttx/arch/arm/src/stm32/stm32_allocateheap.c``. + in ``nuttx/arch/arm/src/common/stm32/stm32_allocateheap_m3m4_v1.c``. * ``arm_pminitialize()`` - If ``CONFIG_PM`` is defined, the function must initialize the power management subsystem. This MCU-specific function - must be called very early in the intialization sequence before any other + must be called very early in the initialization sequence before any other device drivers are initialized (since they may attempt to register with the power management subsystem). There is no implementation of ``up_pminitialize()`` for any STM32 platform. * ``arm_dmainitialize()`` - Initialize the DMA subsystem. For the STM32 F4, this DMA initialization can be found in - ``nuttx/arch/arm/src/stm32/stm32_dma.c`` (which includes - ``nuttx/arch/arm/src/stm32f4xxx_dma.c``). + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c`` (which includes + ``nuttx/arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c``). * ``devnull_register()`` - Registers the standard ``/dev/null``. @@ -381,11 +381,11 @@ file and in that case those operations are not performed: (found at ``nuttx/arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c`` STM32 F4). * ``arm_netinitialize()`` - Initialize the network. For the STM32 F4, - this function is in ``nuttx/arch/arm/src/stm32/stm32_eth.c``. + this function is in ``nuttx/arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c``. * ``arm_usbinitialize()`` - Initialize USB (host or device). For the STM32 F4, this function is in - ``nuttx/arch/arm/src/stm32/stm32_otgfsdev.c``. + ``nuttx/arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c``. * ``arm_l2ccinitialize()`` - Initialize the L2 cache if present and selected. @@ -448,7 +448,7 @@ This function performed the following specific operations: for a variety of purposes like misc garbage clean-up. * ``nx_create_initthread()`` - Once the operating system has been initialized, - this funcions either directly calls ``nx_start_application()`` or creates + this functions either directly calls ``nx_start_application()`` or creates a thread for running it * ``nx_start_application()`` - If set in the NuttX configuration, @@ -640,7 +640,7 @@ The resulting ROMFS file system can be found in * ``board_app_initialize()`` - For the STM32F4Discovery, this architecture specific initialization can be found at - ``boards/arm/stm32/stm32f4discovery/src/stm32_appinit.c``. + ``boards/arm/stm32f4/stm32f4discovery/src/stm32_appinit.c``. This it does things like: 1. Initialize SPI devices. diff --git a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst index 19ce66c3fb0..9c15d336c5d 100644 --- a/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/fire-stm32v2/index.rst @@ -228,13 +228,13 @@ OpenOCD ======= I have also used OpenOCD with the M3 Wildfire. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/fire-stm32v2/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/fire-stm32v2/tools/oocd.sh $PWD + boards/arm/stm32f1/fire-stm32v2/tools/oocd.sh $PWD - Load NuttX:: diff --git a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst index d544bea76b2..14f2d03a4cd 100644 --- a/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/shenzhou/index.rst @@ -517,7 +517,7 @@ NOTES: ADC_IN8 (PB0) CON5 CN14 Pin2 ADC_IN9 (PB1) CON5 CN14 Pin1 - The signal selection is hard-coded in boards/arm/stm32/shenzhou/src/up_adc.c: The + The signal selection is hard-coded in boards/arm/stm32f1/shenzhou/src/up_adc.c: The potentiometer input (only) is selected. These selections will enable sampling the potentiometer input at 100Hz using diff --git a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst index fb218ff3c3b..3e499fbfe9b 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm3210e-eval/index.rst @@ -87,13 +87,13 @@ OpenOCD ======= I have also used OpenOCD with the STM3210E-EVAL. In this case, I used -the Olimex USB ARM OCD. See the script in boards/arm/stm32/stm3210e-eval/tools/oocd.sh +the Olimex USB ARM OCD. See the script in boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh for more information. Using the script: - Start the OpenOCD GDB server:: cd - boards/arm/stm32/stm3210e-eval/tools/oocd.sh $PWD + boards/arm/stm32f1/stm3210e-eval/tools/oocd.sh $PWD - Load NuttX:: @@ -171,7 +171,7 @@ More complex temperature sensor operations are also available. See the IOCTL commands enumerated in include/nuttx/sensors/lm75.h. Also read the descriptions of the stm32_lm75initialize() and stm32_lm75attach() interfaces in the arch/board/board.h file (sames as -boards/arm/stm32/stm3210e-eval/include/board.h). +boards/arm/stm32f1/stm3210e-eval/include/board.h). NSH Command Line Application ---------------------------- @@ -812,7 +812,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -824,8 +824,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 4. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst index 68819f0f603..e818cabd221 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32f103-minimum/index.rst @@ -186,7 +186,7 @@ instead of 64KiB as documented in the datasheet and reported by its internal register. In order to enable 128KiB you need modify the linker script to reflect this -new size. Open the boards/arm/stm32/stm32f103-minimum/scripts/ld.script and replace:: +new size. Open the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script and replace:: flash (rx) : ORIGIN = 0x08000000, LENGTH = 64K @@ -358,7 +358,7 @@ enable/disable these options using "make menuconfig" :: Memory Management ---> [*] Small memory model - Also change the boards/arm/stm32/stm32f103-minimum/scripts/ld.script file to use 128KB + Also change the boards/arm/stm32f1/stm32f103-minimum/scripts/ld.script file to use 128KB of Flash instead 64KB (since this board has a hidden 64KB flash) : MEMORY diff --git a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst index 8e76e5abc8c..81c6d7b8289 100644 --- a/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst +++ b/Documentation/platforms/arm/stm32f1/boards/stm32vldiscovery/index.rst @@ -12,7 +12,7 @@ LEDs It is assumed that STMicro STM32F100RB generic board board has one LED on PA0. You should configure the port and pin number in -boards/arm/stm32/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by +boards/arm/stm32f1/stm32vldiscovery/src/stm32vldiscovery.h. This LED is not used by the board port unless CONFIG_ARCH_LEDS is defined. In that case, the usage by the board port is defined in include/board.h and src/up_leds.c. The LED is used to encode OS-related events as follows:: diff --git a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst index 40be36a0576..b2584194578 100644 --- a/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/clicker2-stm32/index.rst @@ -79,7 +79,7 @@ Using JTAG The Clicker2 comes with the mikroBootloader installed. That bootloader has not been used and is possibly incompatible with the Clicker2-STM32 -linker script at boards/arm/stm32/clicker2-stm32/scripts/flash.ld. Often code must +linker script at boards/arm/stm32f4/clicker2-stm32/scripts/flash.ld. Often code must be built to execute at an offset in to FLASH when a bootloader is used. Certainly that is the case for the ST-Micro DFU bootloader but I am not aware of the requirements for use with the mikroBootloader. diff --git a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst index 7021a333f0e..e81cd71ba97 100644 --- a/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/omnibusf4/index.rst @@ -79,6 +79,6 @@ package as flexible as, say, an STM32F4 Discovery board. Build Instructions ================== -The boards/arm/stm32/omnibusf4/nsh/defconfig file creates a basic setup, and +The boards/arm/stm32f4/omnibusf4/nsh/defconfig file creates a basic setup, and includes drivers for all supported onboard chips. The console and command prompt are sent to USART3. diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst index 65a7eaf7831..ea78006fcfd 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f4discovery/index.rst @@ -517,7 +517,7 @@ MAPPING TO STM32 F4:: 4 Also the reset pin for the CS43L22 audio Codec. NOTE: The configuration to test this LCD configuration is available at -boards/arm/stm32/stm32f4discovery/nxlines. As of this writing, I have not seen the +boards/arm/stm32f4/stm32f4discovery/nxlines. As of this writing, I have not seen the LCD working so I probably have some things wrong. I might need to use a bit-banging interface. Below is the pin configuration @@ -613,7 +613,7 @@ that I am using:: Darcy Gong recently added support for the UG-2864HSWEG01 OLED which is also an option with this configuration. I have little technical information about -the UG-2864HSWEG01 interface (see boards/arm/stm32/stm32f4discovery/src/up_ug2864hsweg01.c). +the UG-2864HSWEG01 interface (see boards/arm/stm32f4/stm32f4discovery/src/up_ug2864hsweg01.c). NiceRF LoRa (2AD66-LoRa V2) =========================== @@ -639,7 +639,7 @@ connect the CS to PA4, connect RST to PE1 and finally connect INT to PE4. The next step is to enable the ENC28J60 in the menuconfig ("make menuconfig") and the necessary Network configuration, you can use the -boards/arm/stm32/fire-stm32v2/configs/nsh/defconfig as reference. +boards/arm/stm32f1/fire-stm32v2/configs/nsh/defconfig as reference. HCI UART ======== @@ -1202,7 +1202,7 @@ NOTES: The HCI UART selection can be changed by re-configuring and assigning the different U[S]ART to the HCI. The U[S]ART pin selections can be changed by modifying the disambiguation definitions in -boards/arm/stm32/stm32f4discovery/include/board.h +boards/arm/stm32f4/stm32f4discovery/include/board.h I have been testing with the DVK_BT960_SA board via J10 as follows:: @@ -2021,7 +2021,7 @@ NOTES: CONFIG_ARCH_CUSTOM_PMINIT=y CONFIG_ARCH_CUSTOM_PMINIT moves the PM initialization from - arch/arm/src/stm32/stm32_pminitialiaze.c to boards/arm/stm32/stm3210-eval/src/stm32_pm.c. + arch/arm/src/common/stm32/stm32_pminitialize_m3m4_v1.c to boards/arm/stm32f1/stm3210e-eval/src/stm32_pm.c. This allows us to support board-specific PM initialization.:: CONFIG_ARCH_IDLE_CUSTOM=y @@ -2033,8 +2033,8 @@ NOTES: management. The configuration CONFIG_ARCH_IDLE_CUSTOM allows us to "steal" the - normal STM32 IDLE loop (of arch/arm/src/stm32/stm32_idle.c) and replace - this with our own custom IDLE loop (at boards/arm/stm32/stm3210-eval/src/up_idle.c). + normal STM32 IDLE loop (of arch/arm/src/common/stm32/stm32_idle_m3m4_v1.c) and replace + this with our own custom IDLE loop (at boards/arm/stm32f1/stm3210e-eval/src/up_idle.c). 3. Here are some additional things to note in the configuration:: diff --git a/Documentation/platforms/arm/stm32f4/index.rst b/Documentation/platforms/arm/stm32f4/index.rst index 3684b7dd5a0..474dae92be6 100644 --- a/Documentation/platforms/arm/stm32f4/index.rst +++ b/Documentation/platforms/arm/stm32f4/index.rst @@ -389,7 +389,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst index 578ca414e57..0c691673f2a 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l432kc/index.rst @@ -106,7 +106,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst index 17cb93b0dcc..914494906fa 100644 --- a/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/nucleo-l476rg/index.rst @@ -107,7 +107,7 @@ Here are a few tips before you start that effort: on the command line. Startup files will probably cause you some headaches. The NuttX startup file -is arch/arm/src/stm32/stm32_vectors.S. With RIDE, I have to build NuttX +is arch/arm/src/stm32f4/gnu/stm32_vectors.S. With RIDE, I have to build NuttX one time from the Cygwin command line in order to obtain the pre-built startup object needed by RIDE. diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index 006444feb8e..af0cb591ebe 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -68,7 +68,7 @@ specified by several settings in the NuttX configuration file. sub-directories and are discussed in a paragraph `below <#boards-subdirectory-structure>`__. - The directory ``boards/arm/stm32/stm32f4disovery/``, as an + The directory ``boards/arm/stm32f4/stm32f4discovery/``, as an example, holds board-specific logic for the STM32F4 Discovery board and is selected via the ``CONFIG_ARCH_BOARD="stm32f4discovery"`` configuration setting. diff --git a/LICENSE b/LICENSE index a76c658ae4e..a22fd18f559 100644 --- a/LICENSE +++ b/LICENSE @@ -2918,7 +2918,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/photon/src/stm32_wlan_firmware.c +boards/arm/stm32f2/photon/src/stm32_wlan_firmware.c drivers/wireless/ieee80211/bcm43xxx/bcmf_ioctl.h ================================================ @@ -3249,8 +3249,8 @@ ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. boards/arm/rp2040/common/src/rp2040_ina219.c -boards/arm/stm32/common/src/stm32_ina219.c -boards/arm/stm32/olimex-stm32-e407/src/stm32_dac.c +boards/arm/common/stm32/src/stm32_ina219.c +boards/arm/stm32f4/olimex-stm32-e407/src/stm32_dac.c =============================================== Copyright (C) 2018,2019 Erle Robotics (Juan Flores Muñoz). All rights reserved. @@ -3282,9 +3282,9 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f303re/src/stm32_uid.c -boards/arm/stm32/omnibusf4/src/stm32_uid.c -boards/arm/stm32/stm32f4discovery/src/stm32_uid.c +boards/arm/stm32f3/nucleo-f303re/src/stm32_uid.c +boards/arm/stm32f4/omnibusf4/src/stm32_uid.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_uid.c boards/arm/stm32h7/nucleo-h743zi/src/stm32_uid.c boards/arm/stm32h7/stm32h747i-disco/src/stm32_uid.c =============================================== @@ -3317,8 +3317,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/nucleo-f412zg/src/stm32_usb.c -boards/arm/stm32/stm32f411e-disco/src/stm32_usb.c +boards/arm/stm32f4/nucleo-f412zg/src/stm32_usb.c +boards/arm/stm32f4/stm32f411e-disco/src/stm32_usb.c ================================================= Copyright (C) 2017 Gregory Nutt. All rights reserved. Copyright (C) 2017 Brian Webb. All rights reserved. @@ -3350,10 +3350,10 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -boards/arm/stm32/omnibusf4/src/stm32_romfs.h -boards/arm/stm32/omnibusf4/src/stm32_romfs_initialize.c -boards/arm/stm32/stm32f4discovery/src/stm32_romfs.h -boards/arm/stm32/stm32f4discovery/src/stm32_romfs_initialize.c +boards/arm/stm32f4/omnibusf4/src/stm32_romfs.h +boards/arm/stm32f4/omnibusf4/src/stm32_romfs_initialize.c +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs.h +boards/arm/stm32f4/stm32f4discovery/src/stm32_romfs_initialize.c boards/arm/stm32f7/common/include/stm32_romfs.h boards/arm/stm32f7/common/src/stm32_romfs_initialize.c ============================================================= @@ -3975,7 +3975,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f100_pinmap.h +arch/arm/src/stm32f1/hardware/stm32f100_pinmap.h ================================================= Copyright (C) 2009 Gregory Nutt. All rights reserved. @@ -4009,7 +4009,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/hardware/stm32f37xxx_sdadc.h +arch/arm/src/stm32f3/hardware/stm32f37xxx_sdadc.h ==================================================== Copyright (C) 2009, 2011, 2013 Gregory Nutt. All rights reserved. @@ -4042,7 +4042,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_alt.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v1_alt.c =================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4076,7 +4076,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_i2c_v2.c +arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c =========================================== Copyright (C) 2011 Uros Platise. All rights reserved. @@ -4110,8 +4110,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_sdadc.c -arch/arm/src/stm32/stm32_sdadc.h +arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c +arch/arm/src/common/stm32/stm32_sdadc.h =================================== Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved. @@ -4144,7 +4144,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tickless.c +arch/arm/src/common/stm32/stm32_tickless_m3m4_v1.c ====================================== Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. @@ -4177,7 +4177,7 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_tim_lowerhalf.c +arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3_lowerhalf.c =========================================== Copyright (C) 2015 Wail Khemir. All rights reserved. @@ -4210,8 +4210,8 @@ LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -arch/arm/src/stm32/stm32_uid.c -arch/arm/src/stm32/stm32_uid.h +arch/arm/src/common/stm32/stm32_uid_m3m4_v1v2.c +arch/arm/src/common/stm32/stm32_uid.h =================================== Copyright (C) 2015 Marawan Ragab. All rights reserved. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 603dab1a965..e45eed4a24e 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1317,8 +1317,16 @@ config ARCH_CHIP default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X default "sam34" if ARCH_CHIP_SAM34 default "samv7" if ARCH_CHIP_SAMV7 - default "stm32" if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - default "stm32f0l0g0" if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 + default "stm32f1" if ARCH_CHIP_STM32F1 + default "stm32f2" if ARCH_CHIP_STM32F2 + default "stm32f3" if ARCH_CHIP_STM32F3 + default "stm32f4" if ARCH_CHIP_STM32F4 + default "stm32g4" if ARCH_CHIP_STM32G4 + default "stm32l1" if ARCH_CHIP_STM32L1 + default "stm32f0" if ARCH_CHIP_STM32F0 + default "stm32l0" if ARCH_CHIP_STM32L0 + default "stm32g0" if ARCH_CHIP_STM32G0 + default "stm32c0" if ARCH_CHIP_STM32C0 default "stm32f7" if ARCH_CHIP_STM32F7 default "stm32h7" if ARCH_CHIP_STM32H7 default "stm32l4" if ARCH_CHIP_STM32L4 @@ -1819,11 +1827,35 @@ endif if ARCH_CHIP_SAMV7 source "arch/arm/src/samv7/Kconfig" endif -if ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 -source "arch/arm/src/stm32/Kconfig" +if ARCH_CHIP_STM32F1 +source "arch/arm/src/stm32f1/Kconfig" endif -if ARCH_CHIP_STM32F0 || ARCH_CHIP_STM32L0 || ARCH_CHIP_STM32G0 || ARCH_CHIP_STM32C0 -source "arch/arm/src/stm32f0l0g0/Kconfig" +if ARCH_CHIP_STM32F2 +source "arch/arm/src/stm32f2/Kconfig" +endif +if ARCH_CHIP_STM32F3 +source "arch/arm/src/stm32f3/Kconfig" +endif +if ARCH_CHIP_STM32F4 +source "arch/arm/src/stm32f4/Kconfig" +endif +if ARCH_CHIP_STM32G4 +source "arch/arm/src/stm32g4/Kconfig" +endif +if ARCH_CHIP_STM32L1 +source "arch/arm/src/stm32l1/Kconfig" +endif +if ARCH_CHIP_STM32F0 +source "arch/arm/src/stm32f0/Kconfig" +endif +if ARCH_CHIP_STM32L0 +source "arch/arm/src/stm32l0/Kconfig" +endif +if ARCH_CHIP_STM32G0 +source "arch/arm/src/stm32g0/Kconfig" +endif +if ARCH_CHIP_STM32C0 +source "arch/arm/src/stm32c0/Kconfig" endif if ARCH_CHIP_STM32F7 source "arch/arm/src/stm32f7/Kconfig" diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h deleted file mode 100644 index 1c62bcc3c4b..00000000000 --- a/arch/arm/include/stm32/chip.h +++ /dev/null @@ -1,2756 +0,0 @@ -/**************************************************************************** - * arch/arm/include/stm32/chip.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_INCLUDE_STM32_CHIP_H -#define __ARCH_ARM_INCLUDE_STM32_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Prototypes - ****************************************************************************/ - -/* Check the STM32 family configuration. - * It must be done in arch/arm/src/stm32/Kconfig ! - */ - -#ifdef CONFIG_STM32_STM32F10XX -# define __HAVE_F1 1 -#else -# define __HAVE_F1 0 -#endif -#ifdef CONFIG_STM32_STM32F20XX -# define __HAVE_F2 1 -#else -# define __HAVE_F2 0 -#endif -#ifdef CONFIG_STM32_STM32F30XX -# define __HAVE_F30 1 -#else -# define __HAVE_F30 0 -#endif -#ifdef CONFIG_STM32_STM32F33XX -# define __HAVE_F33 1 -#else -# define __HAVE_F33 0 -#endif -#ifdef CONFIG_STM32_STM32F37XX -# define __HAVE_F37 1 -#else -# define __HAVE_F37 0 -#endif -#ifdef CONFIG_STM32_STM32F4XXX -# define __HAVE_F4 1 -#else -# define __HAVE_F4 0 -#endif -#ifdef CONFIG_STM32_STM32G4XXX -# define __HAVE_G4 1 -#else -# define __HAVE_G4 0 -#endif -#ifdef CONFIG_STM32_STM32L15XX -# define __HAVE_L1 1 -#else -# define __HAVE_L1 0 -#endif - -#if ((__HAVE_F1 + __HAVE_F2 + __HAVE_F30 + __HAVE_F33 + __HAVE_F37 + __HAVE_F4 + \ - __HAVE_G4 + __HAVE_L1) != 1) -# error "Only one STM32 family must be selected !" -#endif - -#ifdef CONFIG_STM32_LOWDENSITY -# define __HAVE_LD 1 -#else -# define __HAVE_LD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMDENSITY -# define __HAVE_MD 1 -#else -# define __HAVE_MD 0 -#endif -#ifdef CONFIG_STM32_MEDIUMPLUSDENSITY -# define __HAVE_MPD 1 -#else -# define __HAVE_MPD 0 -#endif -#ifdef CONFIG_STM32_HIGHDENSITY -# define __HAVE_HD 1 -#else -# define __HAVE_HD 0 -#endif - -#if (__HAVE_LD +__HAVE_MD + __HAVE_MPD + __HAVE_HD) > 1 -# error "Up to one density configuration must be selected" -#endif - -/* Get customizations for each supported chip and provide alternate function - * pin-mapping - * - * NOTE: Each GPIO pin may serve either for general purpose I/O or for a - * special alternate function (such as USART, CAN, USB, SDIO, etc.). That - * particular pin-mapping will depend on the package and STM32 family. If - * you are incorporating a new STM32 chip into NuttX, you will need to add - * the pin-mapping to a header file and to include that header file below. - * The chip-specific pin-mapping is defined in the chip datasheet. - */ - -/* STM32L EnergyLite Line ***************************************************/ - -/* STM32L151XX -- No LCD - * STM32L152XX -- With LCD - * - * STM32L15XCX -- 48-pins - * STM32L15XRX -- 64-pins - * STM32L15XVX -- 100-pins - * STM32L15XZX -- 144-pins - * - * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM - * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM - * - * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) - * - * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) - * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) - */ - -#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC , 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L151VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 20-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ - defined(CONFIG_ARCH_CHIP_STM32L152VB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 1 /* DMA1, 7-channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 24-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x18 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 37 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 14-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 21-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 51 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 109 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-E,H */ -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ -# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 115 /* GPIOA-G,H */ -# define STM32_NADC 1 /* ADC1, 40-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* No advanced timers */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA - * 32-bit general timer TIM5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ -# define STM32_NDMA 2 /* DMA1, 12-channels */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ -# define STM32_NUSART 5 /* USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ -# define STM32_NGPIO 83 /* GPIOA-G,H */ - -# define STM32_NADC 1 /* ADC1, 25-channels */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCMP 2 /* (2) Comparators */ -# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 Value Line ****************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \ - || defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 3 additional timers (15-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F100 High-density value Line ***************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100RE) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 64 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \ - || defined(CONFIG_ARCH_CHIP_STM32F100VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */ - -/* TODO: there are also 6 additional timers (12-17) - * that don't fit any existing category - */ - -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 2 /* DAC 1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F102x8/102xB Medium Density USB Access Family **********************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F102CB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 0 /* No advanced timer TIM1 */ -# define STM32_NGTIM 3 /* 16-bit general timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-D */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC1 */ -# define STM32_NETHERNET 0 /* No ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Low Density Family ********************************************/ - -/* STM32F103C4 & STM32F103C6 */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C4) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 2 /* General timers TIM2,3 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timer */ -# define STM32_NDMA 1 /* DMA1 */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 Medium Density Performance Line *******************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103T8) || defined(CONFIG_ARCH_CHIP_STM32F103TB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 1 /* SPI1 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 26 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103C8) || defined(CONFIG_ARCH_CHIP_STM32F103CB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-C */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103R8) || defined(CONFIG_ARCH_CHIP_STM32F103RB) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 3 /* General timers TIM2-4 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 1 /* DMA1, 7 channels */ -# define STM32_NSPI 2 /* SPI1-2 */ -# define STM32_NI2S 0 /* No I2S */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F103 High Density Family *******************************************/ - -/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103RC) || defined(CONFIG_ARCH_CHIP_STM32F103RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F103RE) || defined(CONFIG_ARCH_CHIP_STM32F103RG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-D */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103VC, STM32F103VD, and STM32F103VE are all provided in 100 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103VC) || defined(CONFIG_ARCH_CHIP_STM32F103VE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* General timers TIM2-5 */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 5 /* USART1-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* bxCAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 3 /* ADC1-3 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F103ZC, STM32F103ZD, and STM32F103ZE are all provided in 144 pin - * packages and differ only in the available FLASH and SRAM. - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F103ZE) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timer TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 0 /* No I2S (?) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 1 /* CAN1 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 112 /* GPIOA-G */ -# define STM32_NADC 1 /* ADC1 */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 0 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F105/F107 Connectivity Line ****************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105VB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F105RB) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* I2C1-2 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2 */ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F107VC) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */ -# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* I2C1 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 80 /* GPIOA-E */ -# define STM32_NADC 2 /* ADC1-2*/ -# define STM32_NDAC 2 /* DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* No random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32 F2 Family **********************************************************/ - -#elif defined(CONFIG_ARCH_CHIP_STM32F205RG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207VC) || defined(CONFIG_ARCH_CHIP_STM32F207VE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207VF) || defined(CONFIG_ARCH_CHIP_STM32F207VG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 82 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207IC) || defined(CONFIG_ARCH_CHIP_STM32F207IE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207IF) || defined(CONFIG_ARCH_CHIP_STM32F207IG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 140 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F207ZC) || defined(CONFIG_ARCH_CHIP_STM32F207ZE) || \ - defined(CONFIG_ARCH_CHIP_STM32F207ZF) || defined(CONFIG_ARCH_CHIP_STM32F207ZG) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -/* STM23 F3 Family **********************************************************/ - -/* Part Numbering: STM32Fssscfxxx - * - * Where - * sss = 302/303, 334 or 372/373 - * c = C (48pins) R (68 pins) V (100 pins) - * c = K (32 pins), C (48 pins), R (68 pins), V (100 pins) - * f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH) - * xxx = Package, temperature range, options (ignored here) - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302K6) || defined(CONFIG_ARCH_CHIP_STM32F302K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 24 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 13 /* (13) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302C6) || defined(CONFIG_ARCH_CHIP_STM32F302C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302R6) || defined(CONFIG_ARCH_CHIP_STM32F302R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 2 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (2) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6*/ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ - -# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 1 /* (1) 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303K6) || defined(CONFIG_ARCH_CHIP_STM32F303K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 2 /* (2) USART1-2, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303C6) || defined(CONFIG_ARCH_CHIP_STM32F303C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 */ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S */ -# define STM32_NUSART 3 /* (3) USART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 52 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (2) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303RD) || defined(CONFIG_ARCH_CHIP_STM32F303RE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303VD) || defined(CONFIG_ARCH_CHIP_STM32F303VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 84 /* GPIOA-F (depends on package) */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F303ZD) || defined(CONFIG_ARCH_CHIP_STM32F303ZE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 3 /* (3) Advanced 16-bit timers with DMA: TIM1, TIM8 and TIM20 */ -# define STM32_NGTIM 6 /* (5) 16-bit general timers - * (1) 32-bit general timers */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 4 /* (4) SPI1-4 */ -# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* (3) I2C1-3 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 115 /* GPIOA-F */ -# define STM32_NADC 4 /* (4) 12-bit ADC1-4 */ -# define STM32_NDAC 2 /* (2) 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 24 /* (24) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 2 /* (2) USART1-2 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 25 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 14 /* (14) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 37 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 17 /* (17) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */ -# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/ -# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3 - * (1) 32-bit general timers with DMA: TIM2 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* All timers have DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */ -# define STM32_NDMA 1 /* (1) DMA1 (7 channels) */ -# define STM32_NSPI 1 /* (1) SPI1 */ -# define STM32_NI2S 0 /* (0) No I2S1 */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 1 /* (1) I2C1 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* (0) No USB */ -# define STM32_NGPIO 51 /* GPIOA-F */ -# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */ -# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */ -# define STM32_NCAPSENSE 18 /* (18) Capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 0 /* (0) Advanced 16-bit timers with DMA: */ -# define STM32_NGTIM 8 /* (3) 16-bit general timers with DMA: TIM3, TIM4 and TIM19 - * (2) 32-bit general timers with DMA: TIM2 and TIM5 - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 3 /* (3) 16-bit general timers count-up timers without DMA: TIM12-14 */ -# define STM32_NBTIM 3 /* (3) Basic timers: TIM6, TIM7 and TIM18 */ -# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */ -# define STM32_NSPI 3 /* (3) SPI1-3 */ -# define STM32_NI2S 3 /* (3) I2S1-2 (multiplexed with SPI1-3) */ -# define STM32_NUSART 3 /* (3) USART1-3 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 2 /* (2) I2C1-2 */ -# define STM32_NCAN 1 /* (1) CAN1 */ -# define STM32_NSDIO 0 /* (0) No SDIO */ -# define STM32_NLCD 0 /* (0) No LCD */ -# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */ -# define STM32_NGPIO 87 /* GPIOA-F */ -# define STM32_NADC 1 /* (1) 12-bit ADC1 */ -# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */ -# define STM32_NDAC 3 /* (3) 12-bit DAC1-2, 3 channels */ -# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */ -# define STM32_NCRC 1 /* (1) CRC calculation unit */ -# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */ -# define STM32_NRNG 0 /* (0) No random number generator (RNG) */ -# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */ - -/* STM23 F4 Family **********************************************************/ - -/* STM32F01xB/C Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CB WLCSP49/UFQFPN48 128Kb No 10 - * STM32F401RB LQFP64 128Kb Yes 16 - * STM32F401VB UFBGA100/LQFP100 128Kb Yes 16 - * STM32F401CC WLCSP49/UFQFPN48 256Kb No 10 - * STM32F401RC LQFP64 256Kb Yes 16 - * STM32F401VC UFBGA100/LQFP100 256Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401RB) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RC) || defined(CONFIG_ARCH_CHIP_STM32F401VC) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -/* STM32F01xD/E Family Differences: - * - * PART PACKAGE FLASH SDIO ADC Channels - * ----------- ---------------- ----- ---- ------------ - * STM32F401CD WLCSP49/UFQFPN48 384Kb No 10 - * STM32F401RD LQFP64 384Kb Yes 16 - * STM32F401VD UFBGA100/LQFP100 384Kb Yes 16 - * STM32F401CE WLCSP49/UFQFPN48 512Kb No 10 - * STM32F401RE LQFP64 512Kb Yes 16 - * STM32F401VE UFBGA100/LQFP100 512Kb Yes 16 - */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401RD) || \ - defined(CONFIG_ARCH_CHIP_STM32F401VD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) || \ - defined(CONFIG_ARCH_CHIP_STM32F401RE) || defined(CONFIG_ARCH_CHIP_STM32F401VE) -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# if defined(CONFIG_ARCH_CHIP_STM32F401CD) || defined(CONFIG_ARCH_CHIP_STM32F401CE) -# define STM32_NSDIO 0 /* No SDIO interface */ -# else -# define STM32_NSDIO 1 /* One SDIO interface */ -# endif -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 10 or 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F410RB) /* LQFP64 package, 512Kb FLASH, 96KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 3 /* SPI1-4 */ -# define STM32_NI2S 0 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 0 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411CE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411RE) /* LQFP64 package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 50 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F411VE) /* 100 pin LQFP/BGA package, 512Kb FLASH, 128KiB SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 1 /* One advanced timers TIM1 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ -# define STM32_NBTIM 0 /* No basic timers */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 0 /* No CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 81 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* No CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 0 /* No Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412CE) /* UFQFPN48 package, 512Kb FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 4 /* 16-bit general timers 9, 12, 13, and 14 without DMA */ -# define STM32_NBTIM 0 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 4 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 34 /* GPIOA-B (sans PB11) and 3 Bits of C */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F412ZG) /* 144 pin LQFP package, 1MB FLASH, 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* 2 basic timers TIM6 and TIM7 */ -# define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ -# define STM32_NSPI 5 /* SPI1-5 */ -# define STM32_NI2S 3 /* I2S1-3 */ -# define STM32_NUSART 6 /* USART1, 2, 3 and 6 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* 2 CAN */ -# define STM32_NSDIO 1 /* One SDIO interface */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS (only) */ -# define STM32_NGPIO 113 /* GPIOA-H */ -# define STM32_NADC 1 /* One 12-bit ADC1, 16 channels */ -# define STM32_NDAC 0 /* No DAC */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 0 /* No FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 1 /* 12-bit DAC1, 1 channel */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 (?) */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F427V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429I) /* BGA176; LQFP176 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429Z) /* LQFP144 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429V) /* LQFP100 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 139 /* GPIOA-I */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446M) /* WLCSP81 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 14 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446R) /* LQFP64 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446V) /* LQFP100 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F446Z) /* LQFP144 UFBGA144 256/512KiB flash 128KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 6 /* USART1-3 and 6, UART 4-5 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 114 /* GPIOA-I */ -# define STM32_NADC 2 /* 12-bit ADC1-3, 16 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 0 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F429N) /* TFBGA216 1024/2048KiB flash 256KiB SRAM */ -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# define STM32_NGPIO 168 /* GPIOA-K */ -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined(CONFIG_ARCH_CHIP_STM32F469A) || \ - defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */ -# define STM32_NGTIM 4 /* 16-bit general timers TIM3 and 4 with DMA - * 32-bit general timers TIM2 and 5 with DMA */ -# define STM32_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 6 /* SPI1-6 */ -# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */ -# define STM32_NUSART 8 /* USART1-3 and 6, UART 4-5 and 7-8 */ -# define STM32_NLPUART 0 /* No LPUART */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 2 /* CAN1-2 */ -# define STM32_NSDIO 1 /* SDIO */ -# define STM32_NLCD 1 /* LCD */ -# define STM32_NUSBOTG 1 /* USB OTG FS/HS */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NGPIO 114 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) -# define STM32_NGPIO 131 /* GPIOA-I */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NGPIO 161 /* GPIOA-K */ -# endif -# define STM32_NADC 3 /* 12-bit ADC1-3, 24 channels */ -# define STM32_NDAC 2 /* 12-bit DAC1, 2 channels */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# if defined(CONFIG_ARCH_CHIP_STM32F469A) -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \ - defined(CONFIG_ARCH_CHIP_STM32F469B) || \ - defined(CONFIG_ARCH_CHIP_STM32F469N) -# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */ -# endif -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431K) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 2 /* USART1-2 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 26 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 66 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G431V) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 2 /* (2) Advanced motor control timers TIM1, 8 with DMA */ -# define STM32_NGTIM 6 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (1) 32-bit general timers TIM2 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 4 /* USART1-3 and UART4*/ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 3 /* I2C1-3 */ -# define STM32_NCAN 1 /* FDCAN1 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 2 /* 12-bit ADC1-2 */ -# define STM32_NDAC 2 /* 12-bit DAC1-2, 4 channels (2 external, 2 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474C) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1-3 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 42 /* GPIOA-C, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474M) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 67 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474R) -# define STM32_NFSMC 0 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 3 /* SPI1-3 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 0 /* No LCD */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 52 /* GPIOA-D, F-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474Q) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 107 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#elif defined (CONFIG_ARCH_CHIP_STM32G474V) -# define STM32_NFSMC 1 /* FSMC */ -# define STM32_NATIM 3 /* (3) Advanced motor control timers TIM1, 8, and 20 with DMA */ -# define STM32_NGTIM 7 /* (2) 16-bit general timers TIM3 and 4 with DMA - * (2) 32-bit general timers TIM2 and 5 with DMA - * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */ -# define STM32_NGTIMNDMA 0 /* (0) 16-bit general timers TIM9-14 without DMA */ -# define STM32_NBTIM 2 /* (2) Basic timers, TIM6-7 */ -# define STM32_NDMA 2 /* DMA1-2 */ -# define STM32_NSPI 4 /* SPI1-4 */ -# define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 5 /* USART1-3 and UART 4-5 */ -# define STM32_NLPUART 1 /* LPUART1 */ -# define STM32_NI2C 4 /* I2C1-4 */ -# define STM32_NCAN 3 /* FDCAN1-3 */ -# define STM32_NSDIO 0 /* No SDIO */ -# define STM32_NLCD 1 /* LCD parallel interface possible via FMC */ -# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (but there is USB 2.0 full-speed - * with LPM and BCD support) */ -# define STM32_NGPIO 86 /* GPIOA-G */ -# define STM32_NADC 5 /* 12-bit ADC1-5 */ -# define STM32_NDAC 4 /* 12-bit DAC1-4, 7 channels (3 external, 4 internal) */ -# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */ -# define STM32_NCRC 1 /* CRC */ -# define STM32_NETHERNET 0 /* No Ethernet MAC */ -# define STM32_NRNG 1 /* Random number generator (RNG) */ -# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ - -#else -# error "Unsupported STM32 chip" -#endif - -/* Peripheral IP versions ***************************************************/ - -/* Peripheral IP versions are invariant and should be decided here, not in - * Kconfig. - * - * REVISIT: Currently only SPI IP version is handled here, with others being - * handled in Kconfig. Those others need to be gradually refactored - * and resolved here. - */ - -#if defined(CONFIG_STM32_STM32F10XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F20XX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32F30XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F33XX) -# define STM32_HAVE_IP_SPI_V1 - -#elif defined(CONFIG_STM32_STM32F37XX) -# define STM32_HAVE_IP_SPI_V3 - -#elif defined(CONFIG_STM32_STM32F4XXX) -# define STM32_HAVE_IP_SPI_V2 - -#elif defined(CONFIG_STM32_STM32G4XXX) -# define STM32_HAVE_IP_SPI_V4 - -#elif defined(CONFIG_STM32_STM32L15XX) -# define STM32_HAVE_IP_SPI_V1 - -#else -# error "Did not resolve peripheral IP versions!" -#endif - -/* NVIC priority levels *****************************************************/ - -#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ -#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ -#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ -#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ - -#endif /* __ARCH_ARM_INCLUDE_STM32_CHIP_H */ diff --git a/arch/arm/include/stm32l1/chip.h b/arch/arm/include/stm32l1/chip.h new file mode 100644 index 00000000000..a8b532d3673 --- /dev/null +++ b/arch/arm/include/stm32l1/chip.h @@ -0,0 +1,491 @@ +/**************************************************************************** + * arch/arm/include/stm32l1/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_STM32L1_CHIP_H +#define __ARCH_ARM_INCLUDE_STM32L1_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Get customizations for each supported chip and provide alternate function + * pin-mapping + * + * NOTE: Each GPIO pin may serve either for general purpose I/O or for a + * special alternate function (such as USART, CAN, USB, SDIO, etc.). That + * particular pin-mapping will depend on the package and STM32 family. If + * you are incorporating a new STM32 chip into NuttX, you will need to add + * the pin-mapping to a header file and to include that header file below. + * The chip-specific pin-mapping is defined in the chip datasheet. + */ + +/* STM32L EnergyLite Line ***************************************************/ + +/* STM32L151XX -- No LCD + * STM32L152XX -- With LCD + * + * STM32L15XCX -- 48-pins + * STM32L15XRX -- 64-pins + * STM32L15XVX -- 100-pins + * STM32L15XZX -- 144-pins + * + * STM32L15XX6 -- 32KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XX8 -- 64KB FLASH, 10KB SRAM, 4KB EEPROM + * STM32L15XXB -- 128KB FLASH, 16KB SRAM, 4KB EEPROM + * + * STM32L15XXC -- 256KB FLASH, 32KB SRAM, 8KB EEPROM (medium+ density) + * + * STM32L16XXD -- 384KB FLASH, 48KB SRAM, 12KB EEPROM (high density) + * STM32L16XXE -- 512KB FLASH, 80KB SRAM, 16KB EEPROM (high density) + */ + +#if defined(CONFIG_ARCH_CHIP_STM32L151C6) || defined(CONFIG_ARCH_CHIP_STM32L151C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151R6) || defined(CONFIG_ARCH_CHIP_STM32L151R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC , 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151V6) || defined(CONFIG_ARCH_CHIP_STM32L151V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L151VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 0 /* No LCD */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152C6) || defined(CONFIG_ARCH_CHIP_STM32L152C8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152CB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 13 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152R6) || defined(CONFIG_ARCH_CHIP_STM32L152R8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152RB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 20-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152V6) || defined(CONFIG_ARCH_CHIP_STM32L152V8) || \ + defined(CONFIG_ARCH_CHIP_STM32L152VB) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 1 /* DMA1, 7-channels */ +# define STM32_NSPI 2 /* SPI1-2 */ +# define STM32_NI2S 0 /* No I2S */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 0 /* No USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 24-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 20 /* Capacitive sensing channels */ +# define STM32_NCRC 0 /* No CRC */ +# define STM32_NETHERNET 0 /* No Ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152CC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x18 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 37 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 14-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 16 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152RC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x32, 8x28 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 21-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L152VC) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 3 /* USART1-3 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151RE) || defined(CONFIG_ARCH_CHIP_STM32L152RE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 51 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151VE) || defined(CONFIG_ARCH_CHIP_STM32L152VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151QE) || defined(CONFIG_ARCH_CHIP_STM32L152QE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 109 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 33 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L151ZE) || defined(CONFIG_ARCH_CHIP_STM32L152ZE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 3 /* 16-bit general up/down timers TIM2-4 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-E,H */ +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162ZD) +# define STM32_NFSMC 1 /* FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 without DMA */ +# define STM32_NDMA 2 /* DMA1, 7-channels, DMA2 (5 channels) */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 1 /* SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40 */ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 115 /* GPIOA-G,H */ +# define STM32_NADC 1 /* ADC1, 40-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 34 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +#elif defined(CONFIG_ARCH_CHIP_STM32L162VE) +# define STM32_NFSMC 0 /* No FSMC */ +# define STM32_NATIM 0 /* No advanced timers */ +# define STM32_NGTIM 4 /* 16-bit general timers TIM2-4 with DMA + * 32-bit general timer TIM5 with DMA */ +# define STM32_NGTIMNDMA 3 /* 16-bit general timers TIM9-11 without DMA */ +# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 with DMA */ +# define STM32_NDMA 2 /* DMA1, 12-channels */ +# define STM32_NSPI 3 /* SPI1-3 */ +# define STM32_NI2S 2 /* I2S1-2, overlapping with SPI2-3 */ +# define STM32_NUSART 5 /* USART1-3, UART4-5 */ +# define STM32_NLPUART 0 /* No LPUART */ +# define STM32_NI2C 2 /* I2C1-2 */ +# define STM32_NCAN 0 /* No CAN */ +# define STM32_NSDIO 0 /* No SDIO */ +# define STM32_NLCD 1 /* LCD 4x44, 8x40*/ +# define STM32_NUSBOTG 1 /* USB OTG FS/HS (only USB 2.0 device) */ +# define STM32_NGPIO 83 /* GPIOA-G,H */ + +# define STM32_NADC 1 /* ADC1, 25-channels */ +# define STM32_NDAC 2 /* DAC 1, 2 channels */ +# define STM32_NCMP 2 /* (2) Comparators */ +# define STM32_NCAPSENSE 23 /* Capacitive sensing channels */ +# define STM32_NCRC 1 /* CRC */ +# define STM32_NETHERNET 0 /* No ethernet */ +# define STM32_NRNG 0 /* No random number generator (RNG) */ +# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */ + +/* STM32 F100 Value Line ****************************************************/ + +#else +# error "Unsupported STM32 chip" +#endif + +/* Peripheral IP versions ***************************************************/ + +/* Peripheral IP versions are invariant and should be decided here, not in + * Kconfig. + * + * REVISIT: Currently only SPI IP version is handled here, with others being + * handled in Kconfig. Those others need to be gradually refactored + * and resolved here. + */ + +#define STM32_HAVE_IP_SPI_V1 + +/* NVIC priority levels *****************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ +#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */ + +#endif /* __ARCH_ARM_INCLUDE_STM32L1_CHIP_H */ diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32l1/irq.h similarity index 90% rename from arch/arm/include/stm32/stm32l15xxx_irq.h rename to arch/arm/include/stm32l1/irq.h index 432d4b013c8..cba5263dd42 100644 --- a/arch/arm/include/stm32/stm32l15xxx_irq.h +++ b/arch/arm/include/stm32l1/irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/include/stm32/stm32l15xxx_irq.h + * arch/arm/include/stm32l1/irq.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ * ****************************************************************************/ -/* This file should never be included directly but, rather, only indirectly - * through nuttx/irq.h +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h */ -#ifndef __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H -#define __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H +#ifndef __ARCH_ARM_INCLUDE_STM32L1_IRQ_H +#define __ARCH_ARM_INCLUDE_STM32L1_IRQ_H /**************************************************************************** * Included Files @@ -33,22 +33,45 @@ #include #include +#include /**************************************************************************** * Pre-processor Prototypes ****************************************************************************/ -/* IRQ numbers. The IRQ number corresponds vector number and hence map - * directly to bits in the NVIC. This does, however, waste several words of - * memory in the IRQ to handle mapping tables. - * - * Processor Exceptions (vectors 0-15). These common definitions can be - * found in nuttx/arch/arm/include/stm32/irq.h - * - * External interrupts (vectors >= 16) for low and medium density devices +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to + * bits in the NVIC. This does, however, waste several words of memory in + * the IRQ to handle mapping tables. */ -#if defined(CONFIG_STM32_LOWDENSITY) || defined(CONFIG_STM32_MEDIUMDENSITY) +/* Processor Exceptions (vectors 0-15) */ + +#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ +#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define STM32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define STM32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define STM32_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +/* External interrupts (vectors >= 16). + * These definitions are chip-specific + */ + +#define STM32_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#if defined(CONFIG_STM32L1_LOWDENSITY) || defined(CONFIG_STM32L1_MEDIUMDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ # define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ @@ -98,8 +121,6 @@ # define STM32_IRQ_NEXTINTS (45) -/* External interrupts (vectors >= 16) medium+ density devices */ - #elif defined(CONFIG_STM32_MEDIUMPLUSDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ @@ -160,9 +181,7 @@ # define STM32_IRQ_NEXTINTS (54) -/* External interrupts (vectors >= 16) high density devices */ - -#elif defined(CONFIG_STM32_HIGHDENSITY) +#elif defined(CONFIG_STM32L1_HIGHDENSITY) # define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */ # define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */ # define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper through EXTI line interrupt, or */ @@ -230,31 +249,4 @@ # define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif - -#endif /* __ARCH_ARM_INCLUDE_STM32_STM32FL15XXX_IRQ_H */ +#endif /* __ARCH_ARM_INCLUDE_STM32L1_IRQ_H */ diff --git a/arch/arm/src/common/stm32/CMakeLists.txt b/arch/arm/src/common/stm32/CMakeLists.txt index c235abddbee..34640d535af 100644 --- a/arch/arm/src/common/stm32/CMakeLists.txt +++ b/arch/arm/src/common/stm32/CMakeLists.txt @@ -227,9 +227,8 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() endif() - if(CONFIG_STM32_ADC - AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) + if(CONFIG_STM32_ADC AND (CONFIG_STM32_HAVE_IP_ADC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_ADC_M3M4_V2)) list(APPEND SRCS stm32_adc_m3m4_v1v2.c) endif() @@ -237,9 +236,8 @@ if(CONFIG_STM32_COMMON_LEGACY) list(APPEND SRCS stm32_sdadc_m3m4_v1.c) endif() - if(CONFIG_STM32_DAC - AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 - OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) + if(CONFIG_STM32_DAC AND (CONFIG_STM32_HAVE_IP_DAC_M3M4_V1 + OR CONFIG_STM32_HAVE_IP_DAC_M3M4_V2)) list(APPEND SRCS stm32_dac_m3m4_v1.c) endif() @@ -358,12 +356,7 @@ if(CONFIG_STM32_COMMON_LEGACY) endif() if(CONFIG_ARCH_CORTEXM0) - list( - APPEND - SRCS - stm32_irq_m0_v1.c - stm32_start_m0_v1.c - stm32_lsi_m0_v1.c) + list(APPEND SRCS stm32_irq_m0_v1.c stm32_start_m0_v1.c stm32_lsi_m0_v1.c) if(CONFIG_STM32_HAVE_IP_GPIO_M0_V1) list(APPEND SRCS stm32_gpio_m0_v1.c) diff --git a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c index e129ee671ce..f1c195a43cd 100644 --- a/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c @@ -1093,7 +1093,7 @@ int stm32_dma2dinitialize(void) stm32_dma2duninitialize(); /* Enable dma2d is done in rcc_enableahb1, see - * arch/arm/src/stm32/stm32f40xxx_rcc.c + * arch/arm/src/stm32f4/stm32_rcc.c */ #ifdef CONFIG_STM32_FB_CMAP diff --git a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c index 6fb57a23624..756c7031663 100644 --- a/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c +++ b/arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c @@ -20,7 +20,7 @@ * ****************************************************************************/ -/* Ported from arch/arm/src/stm32/stm32_dma_v1mux.c */ +/* Ported from arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch_dmamux.c */ /**************************************************************************** * Included Files diff --git a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c index e12f93b77fd..1cb8fb9a9a4 100644 --- a/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c +++ b/arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c @@ -47,7 +47,7 @@ #include "stm32_gpio.h" #include "stm32_rcc.h" -/* Ported from arch/arm/src/stm32/stm32_fdcan.c */ +/* Ported from arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32/CMakeLists.txt b/arch/arm/src/stm32/CMakeLists.txt deleted file mode 100644 index f36e41d25df..00000000000 --- a/arch/arm/src/stm32/CMakeLists.txt +++ /dev/null @@ -1,57 +0,0 @@ -# ############################################################################## -# arch/arm/src/stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -set(SRCS) - -list( - APPEND - SRCS - stm32_allocateheap.c - stm32_start.c - stm32_rcc.c - stm32_lse.c - stm32_lsi.c - stm32_irq.c - stm32_lowputc.c) - -if(CONFIG_STM32_TICKLESS_TIMER) - list(APPEND SRCS stm32_tickless.c) -else() - list(APPEND SRCS stm32_timerisr.c) -endif() - -if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS stm32_userspace.c stm32_mpuinit.c) -endif() - -if(NOT CONFIG_ARCH_IDLE_CUSTOM) - list(APPEND SRCS stm32_idle.c) -endif() - -list(APPEND SRCS stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c) - -if(NOT CONFIG_ARCH_CUSTOM_PMINIT) - list(APPEND SRCS stm32_pminitialize.c) -endif() - -target_sources(arch PRIVATE ${SRCS}) -add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/../common/stm32 stm32_common) diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig deleted file mode 100644 index 82d831fa087..00000000000 --- a/arch/arm/src/stm32/Kconfig +++ /dev/null @@ -1,2675 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -comment "STM32 Configuration Options" - -config STM32_COMMON_PERIPHERALS - bool - default y - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - select STM32_HAVE_COMP if STM32_STM32L15XX || STM32_STM32F33XX || STM32_STM32G4XXX - select STM32_HAVE_DCMI if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_DMA2 if !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY) - select STM32_HAVE_DMA2D if STM32_STM32F429 - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_HASH if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_I2C1 - select STM32_HAVE_LCD if STM32_STM32L15XX - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG if STM32_STM32L15XX || STM32_STM32F30XX - select STM32_HAVE_SYSCFG if STM32_STM32F33XX || STM32_STM32F37XX - select STM32_HAVE_SYSCFG if STM32_STM32F20XX || STM32_STM32F4XXX - select STM32_HAVE_SYSCFG if STM32_STM32G4XXX || STM32_CONNECTIVITYLINE - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - -choice - prompt "STM32 Chip Selection" - default ARCH_CHIP_STM32F103ZE - depends on ARCH_CHIP_STM32F1 || ARCH_CHIP_STM32F2 || ARCH_CHIP_STM32F3 || ARCH_CHIP_STM32F4 || ARCH_CHIP_STM32G4 || ARCH_CHIP_STM32L1 - -config ARCH_CHIP_STM32L151C6 - bool "STM32L151C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151C8 - bool "STM32L151C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151CB - bool "STM32L151CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R6 - bool "STM32L151R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151R8 - bool "STM32L151R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151RB - bool "STM32L151RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V6 - bool "STM32L151V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151V8 - bool "STM32L151V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L151VB - bool "STM32L151VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM - -config ARCH_CHIP_STM32L152C6 - bool "STM32L152C6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152C8 - bool "STM32L152C8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152CB - bool "STM32L152CB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152R6 - bool "STM32L152R6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152R8 - bool "STM32L152R8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152RB - bool "STM32L152RB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152V6 - bool "STM32L152V6" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152V8 - bool "STM32L152V8" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152VB - bool "STM32L152VB" - select STM32_STM32L15XX - select STM32_LOWDENSITY - ---help--- - STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L152CC - bool "STM32L152CC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x18 LCD interface - -config ARCH_CHIP_STM32L152RC - bool "STM32L152RC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x32/8x28 LCD interface - -config ARCH_CHIP_STM32L152VC - bool "STM32L152VC" - select STM32_STM32L15XX - select STM32_MEDIUMPLUSDENSITY - ---help--- - STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L151RE - bool "STM32L151RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152RE - bool "STM32L152RE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151VE - bool "STM32L151VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152VE - bool "STM32L152VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151QE - bool "STM32L151QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152QE - bool "STM32L152QE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L151ZE - bool "STM32L151ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L152ZE - bool "STM32L152ZE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - -config ARCH_CHIP_STM32L162ZD - bool "STM32L162ZD" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32L162VE - bool "STM32L162VE" - select STM32_STM32L15XX - select STM32_HIGHDENSITY - select STM32_HAVE_AES - ---help--- - STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with - 4x44/8x40 LCD interface - -config ARCH_CHIP_STM32F100C8 - bool "STM32F100C8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100CB - bool "STM32F100CB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100R8 - bool "STM32F100R8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RB - bool "STM32F100RB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RC - bool "STM32F100RC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RD - bool "STM32F100RD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100RE - bool "STM32F100RE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100V8 - bool "STM32F100V8" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VB - bool "STM32F100VB" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VC - bool "STM32F100VC" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VD - bool "STM32F100VD" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F100VE - bool "STM32F100VE" - select STM32_STM32F10XX - select STM32_VALUELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F102CB - bool "STM32F102CB" - select STM32_STM32F10XX - select STM32_USBACCESSLINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103T8 - bool "STM32F103T8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103TB - bool "STM32F103TB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103C4 - bool "STM32F103C4" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_LOWDENSITY - -config ARCH_CHIP_STM32F103C8 - bool "STM32F103C8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103CB - bool "STM32F103CB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103R8 - bool "STM32F103R8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RB - bool "STM32F103RB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RC - bool "STM32F103RC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RD - bool "STM32F103RD" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RE - bool "STM32F103RE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103RG - bool "STM32F103RG" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103V8 - bool "STM32F103V8" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VB - bool "STM32F103VB" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_MEDIUMDENSITY - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VC - bool "STM32F103VC" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103VE - bool "STM32F103VE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F103ZE - bool "STM32F103ZE" - select STM32_STM32F10XX - select STM32_PERFORMANCELINE - select STM32_HIGHDENSITY - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105VB - bool "STM32F105VBT7" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F105RB - bool "STM32F105RB" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F107VC - bool "STM32F107VC" - select STM32_STM32F10XX - select STM32_CONNECTIVITYLINE - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM4 - -config ARCH_CHIP_STM32F205RG - bool "STM32F205RG" - select STM32_STM32F20XX - select STM32_STM32F205 - -config ARCH_CHIP_STM32F207VC - bool "STM32F207VC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VE - bool "STM32F207VE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VF - bool "STM32F207VF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207VG - bool "STM32F207VG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IC - bool "STM32F207IC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IE - bool "STM32F207IE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IF - bool "STM32F207IF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207IG - bool "STM32F207IG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZC - bool "STM32F207ZC" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZE - bool "STM32F207ZE" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZF - bool "STM32F207ZF" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F207ZG - bool "STM32F207ZG" - select STM32_STM32F20XX - select STM32_STM32F207 - -config ARCH_CHIP_STM32F302K6 - bool "STM32F302K6" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302K8 - bool "STM32F302K8" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_I2C3 - -config ARCH_CHIP_STM32F302C6 - bool "STM32F302C6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302C8 - bool "STM32F302C8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R6 - bool "STM32F302R6" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302R8 - bool "STM32F302R8" - select STM32_STM32F30XX - select STM32_STM32F302 - -config ARCH_CHIP_STM32F302CB - bool "STM32F302CB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302CC - bool "STM32F302CC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F302RB - bool "STM32F302RB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302RC - bool "STM32F302RC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VB - bool "STM32F302VB" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F302VC - bool "STM32F302VC" - select STM32_STM32F30XX - select STM32_STM32F302 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config ARCH_CHIP_STM32F303K6 - bool "STM32F303K6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303K8 - bool "STM32F303K8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - -config ARCH_CHIP_STM32F303C6 - bool "STM32F303C6" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303C8 - bool "STM32F303C8" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303CB - bool "STM32F303CB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303CC - bool "STM32F303CC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RB - bool "STM32F303RB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RC - bool "STM32F303RC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RD - bool "STM32F303RD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303RE - bool "STM32F303RE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VB - bool "STM32F303VB" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VC - bool "STM32F303VC" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USBDEV - -config ARCH_CHIP_STM32F303VD - bool "STM32F303VD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303VE - bool "STM32F303VE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZD - bool "STM32F303ZD" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F303ZE - bool "STM32F303ZE" - select STM32_STM32F30XX - select STM32_STM32F303 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_USART3 - -config ARCH_CHIP_STM32F334K4 - bool "STM32F334K4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K6 - bool "STM32F334K6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334K8 - bool "STM32F334K8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C4 - bool "STM32F334C4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C6 - bool "STM32F334C6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334C8 - bool "STM32F334C8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R4 - bool "STM32F334R4" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R6 - bool "STM32F334R6" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F334R8 - bool "STM32F334R8" - select STM32_STM32F33XX - -config ARCH_CHIP_STM32F372C8 - bool "STM32F372C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372R8 - bool "STM32F372R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372V8 - bool "STM32F372V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CB - bool "STM32F372CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RB - bool "STM32F372RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VB - bool "STM32F372VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372CC - bool "STM32F372CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372RC - bool "STM32F372RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F372VC - bool "STM32F372VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373C8 - bool "STM32F373C8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373R8 - bool "STM32F373R8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373V8 - bool "STM32F373V8" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CB - bool "STM32F373CB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RB - bool "STM32F373RB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VB - bool "STM32F373VB" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373CC - bool "STM32F373CC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373RC - bool "STM32F373RC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F373VC - bool "STM32F373VC" - select STM32_STM32F37XX - -config ARCH_CHIP_STM32F401CB - bool "STM32F401CB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RB - bool "STM32F401RB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VB - bool "STM32F401VB" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CC - bool "STM32F401CC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401RC - bool "STM32F401RC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401VC - bool "STM32F401VC" - select STM32_STM32F401xBC - -config ARCH_CHIP_STM32F401CD - bool "STM32F401CD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RD - bool "STM32F401RD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VD - bool "STM32F401VD" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401CE - bool "STM32F401CE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401RE - bool "STM32F401RE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F401VE - bool "STM32F401VE" - select STM32_STM32F401xDE - -config ARCH_CHIP_STM32F410RB - bool "STM32F410RB" - select STM32_STM32F4XXX - select STM32_STM32F410 - -config ARCH_CHIP_STM32F411CE - bool "STM32F411CE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411RE - bool "STM32F411RE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F411VE - bool "STM32F411VE" - select STM32_STM32F4XXX - select STM32_STM32F411 - -config ARCH_CHIP_STM32F412CE - bool "STM32F412CE" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F412ZG - bool "STM32F412ZG" - select STM32_STM32F4XXX - select STM32_STM32F412 - -config ARCH_CHIP_STM32F405RG - bool "STM32F405RG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405VG - bool "STM32F405VG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F405ZG - bool "STM32F405ZG" - select STM32_STM32F4XXX - select STM32_STM32F405 - -config ARCH_CHIP_STM32F407VE - bool "STM32F407VE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407VG - bool "STM32F407VG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZE - bool "STM32F407ZE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407ZG - bool "STM32F407ZG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IE - bool "STM32F407IE" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F407IG - bool "STM32F407IG" - select STM32_STM32F4XXX - select STM32_STM32F407 - -config ARCH_CHIP_STM32F427V - bool "STM32F427V" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427Z - bool "STM32F427Z" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F427I - bool "STM32F427I" - select STM32_STM32F4XXX - select STM32_STM32F427 - -config ARCH_CHIP_STM32F429V - bool "STM32F429V" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429Z - bool "STM32F429Z" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429I - bool "STM32F429I" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429B - bool "STM32F429B" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F429N - bool "STM32F429N" - select STM32_STM32F4XXX - select STM32_STM32F429 - -config ARCH_CHIP_STM32F446M - bool "STM32F446M" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446R - bool "STM32F446R" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446V - bool "STM32F446V" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F446Z - bool "STM32F446Z" - select STM32_STM32F4XXX - select STM32_STM32F446 - -config ARCH_CHIP_STM32F469A - bool "STM32F469A" - select STM32_STM32F4XXX - select STM32_STM32F469 - -config ARCH_CHIP_STM32F469I - bool "STM32F469I" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469B - bool "STM32F469B" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32F469N - bool "STM32F469N" - select STM32_STM32F4XXX - select STM32_STM32F469 - select STM32_HAVE_ETHMAC - -config ARCH_CHIP_STM32G431K - bool "STM32G431K" - select STM32_STM32G43XX - select STM32_STM32G4XXK - select STM32_STM32G431K - -config ARCH_CHIP_STM32G431C - bool "STM32G431C" - select STM32_STM32G43XX - select STM32_STM32G4XXC - select STM32_STM32G431C - -config ARCH_CHIP_STM32G431R - bool "STM32G431R" - select STM32_STM32G43XX - select STM32_STM32G4XXR - select STM32_STM32G431R - -config ARCH_CHIP_STM32G431M - bool "STM32G431M" - select STM32_STM32G43XX - select STM32_STM32G4XXM - select STM32_STM32G431M - -config ARCH_CHIP_STM32G431V - bool "STM32G431V" - select STM32_STM32G43XX - select STM32_STM32G4XXV - select STM32_STM32G431V - -config ARCH_CHIP_STM32G474C - bool "STM32G474C" - select STM32_STM32G47XX - select STM32_STM32G4XXC - select STM32_STM32G474C - -config ARCH_CHIP_STM32G474M - bool "STM32G474M" - select STM32_STM32G47XX - select STM32_STM32G4XXM - select STM32_STM32G474M - -config ARCH_CHIP_STM32G474R - bool "STM32G474R" - select STM32_STM32G47XX - select STM32_STM32G4XXR - select STM32_STM32G474R - select STM32_HAVE_USBFS - -config ARCH_CHIP_STM32G474Q - bool "STM32G474Q" - select STM32_STM32G47XX - select STM32_STM32G4XXQ - select STM32_STM32G474Q - -config ARCH_CHIP_STM32G474V - bool "STM32G474V" - select STM32_STM32G47XX - select STM32_STM32G4XXV - select STM32_STM32G474V - -endchoice - -config STM32_FLASH_CONFIG_DEFAULT - bool - -config STM32_FLASH_CONFIG_Z - bool - -config STM32_STM32L15XX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_LCD - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_L1 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V1 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_ENERGYLITE - select STM32_HAVE_USBDEV - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_ADC2 - select STM32_HAVE_USART3 - select STM32_HAVE_RTC_SUBSECONDS if !STM32_LOWDENSITY - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F10XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 if !STM32F1_VALUELINE || STM32F1_HIGHDENSITY - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG if STM32F1_CONNECTIVITYLINE - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKP - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_COUNTER_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_SDIO_M3M4_V1 if !STM32F1_CONNECTIVITYLINE && !STM32F1_VALUELINE - select STM32_HAVE_IP_SPI_V1 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_USART_V1 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY || STM32_MEDIUMDENSITY - select STM32_HAVE_RTC_COUNTER - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_IP_DBGMCU_M3M4_V1 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1_BASIC - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_CONNECTIVITYLINE - bool - default n - select STM32_HAVE_OTGFS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - -config STM32_PERFORMANCELINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - -config STM32_USBACCESSLINE - bool - default n - select STM32_HAVE_USBDEV - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_SPI2 - -config STM32_MEDIUMPLUSDENSITY - bool - default n - -config STM32_HIGHDENSITY - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_MEDIUMDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - -config STM32_LOWDENSITY - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 if !STM32_VALUELINE - -config STM32_STM32F20XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_DCMI - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_HASH - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V2_STREAM - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F2F4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_OTGHS_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKPSRAM - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V2 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM3 - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_OTGFS - select STM32_HAVE_OTGHS - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_DAC1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F205 - bool - default n - -config STM32_STM32F207 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_ETHMAC - -config STM32_STM32F30XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F302 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM4 - select STM32_HAVE_USBDEV - -config STM32_STM32F303 - bool - default n - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM7 - -config STM32_STM32F33XX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_PWR - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_HRTIM1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP6 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_CCM - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_ADC2 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V2 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_COMP_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F37XX - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F1F3 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_IP_SDADC_M3M4_V1 - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_IP_USART_V3 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select STM32_HAVE_PWR - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_USBDEV - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TSC - select STM32_HAVE_SDADC1 - select STM32_HAVE_SDADC2 - select STM32_HAVE_SDADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_I2C2 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_USART3 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1_BASIC - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - -config STM32_STM32F4XXX - select STM32_HAVE_OTGHS - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_DCMI - select STM32_HAVE_HASH - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V2_STREAM - select STM32_HAVE_ETHERNET if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_EXTI_V1 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_F2F4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OTGHS_M3M4_V1 - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_F4 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_BKPSRAM - select STM32_HAVE_IP_SDIO_M3M4_V1 - select STM32_HAVE_IP_SPI_V2 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V2 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_LTDC_M3M4_V1 if STM32_HAVE_LTDC - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select STM32_HAVE_PWR - select ARCH_HAVE_FPU - select STM32_HAVE_FLASH_ICACHE - select STM32_HAVE_FLASH_DCACHE - select STM32_HAVE_CRYP - select STM32_HAVE_SPI2 - select STM32_HAVE_I2C2 - select STM32_HAVE_IOCOMPENSATION - select STM32_HAVE_IP_DBGMCU_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V1 - select STM32_HAVE_IP_ADC_M3M4_V1 - select STM32_HAVE_IP_DAC_M3M4_V1 - select STM32_HAVE_IP_DMA_V2 - select STM32_HAVE_IP_I2C_M3M4_V1 - -config STM32_STM32F401xBC - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401xDE - bool - default n - select STM32_STM32F401 - -config STM32_STM32F401 - bool - default n - select ARCH_CORTEXM4 - select STM32_STM32F4XXX - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F410 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI5 - select STM32_HAVE_DAC1 - -config STM32_STM32F411 - bool - default n - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F412 - bool - default n - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_USART3 - select STM32_HAVE_USART2 - select STM32_HAVE_USART6 - select STM32_HAVE_I2C1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_SPI1 - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_OTGFS - select STM32_HAVE_I2SPLL - -config STM32_STM32F405 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_OTGFS - -config STM32_STM32F407 - bool - default n - select STM32_HAVE_FSMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_OTGFS - -# This is really 427/437, but we treat the two the same. - -config STM32_STM32F427 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SPI6 - select STM32_HAVE_I2SPLL - -# This is really 429/439, but we treat the two the same. - -config STM32_STM32F429 - select STM32_HAVE_DMA2D - select STM32_HAVE_IP_DMA2D_M3M4_V1 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_ETHMAC - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_I2S3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - -config STM32_STM32F446 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - -# This is really 469/479, but we treat the two the same. - -config STM32_STM32F469 - select STM32_HAVE_DMA2D - select STM32_HAVE_IP_DMA2D_M3M4_V1 - bool - default n - select STM32_HAVE_OVERDRIVE - select STM32_HAVE_FMC - select STM32_HAVE_LTDC - select STM32_HAVE_CCM - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_USART6 - select STM32_HAVE_UART7 - select STM32_HAVE_UART8 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM8 - select STM32_HAVE_TIM9 - select STM32_HAVE_TIM10 - select STM32_HAVE_TIM11 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_CAN1 - select STM32_HAVE_CAN2 - select STM32_HAVE_DAC1 - select STM32_HAVE_RNG - select STM32_HAVE_SPI3 - select STM32_HAVE_SPI4 - select STM32_HAVE_SPI5 - select STM32_HAVE_SPI6 - select STM32_HAVE_OTGFS - select STM32_HAVE_SAIPLL - select STM32_HAVE_I2SPLL - select STM32_HAVE_I2S3 - select STM32_HAVE_I2C3 - -config STM32_STM32G4XXX - select STM32_HAVE_DMA1 - select STM32_HAVE_COMP - select STM32_HAVE_DMA2 - select STM32_HAVE_I2C1 - select STM32_HAVE_SPI1 - select STM32_HAVE_SYSCFG - select STM32_HAVE_USART1 - select STM32_HAVE_USART2 - select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES - select STM32_HAVE_IP_BBSRAM_M3M4_V1 - select STM32_HAVE_IP_BKP_M3M4_V1 - select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 - select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM - select STM32_HAVE_IP_CRYPTO_M3M4_V1 - select STM32_FOC_HAVE_ADC_CHAN0_WORKAROUND - select STM32_HAVE_COMMON_FOC - select STM32_HAVE_IP_CORDIC_M3M4_V1 if STM32_HAVE_CORDIC - select STM32_HAVE_IP_DCMI_V1 - select STM32_HAVE_IP_DFUMODE_M3M4_V1 - select STM32_HAVE_IP_DMA_V1_8CH_DMAMUX - select STM32_HAVE_IP_EXTI_V2 - select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC - select STM32_HAVE_IP_FDCAN_MCAN_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_V1 - select STM32_HAVE_IP_FLASH_M3M4_G4 - select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC - select STM32_HAVE_IP_FREERUN_M3M4_V1 - select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC - select STM32_HAVE_IP_GPIO_M3M4_V1 - select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 - select STM32_HAVE_IP_I2S_M3M4_V1 - select STM32_HAVE_IP_ONESHOT_M3M4_V1 - select STM32_HAVE_IP_OPAMP_M3M4_V1 if STM32_HAVE_OPAMP1 || STM32_HAVE_OPAMP2 || STM32_HAVE_OPAMP3 || STM32_HAVE_OPAMP4 || STM32_HAVE_OPAMP5 || STM32_HAVE_OPAMP6 - select STM32_HAVE_IP_PWR_M3M4_V1 - select STM32_HAVE_IP_RNG_M3M4_V1 if STM32_HAVE_RNG - select STM32_HAVE_IP_RTC_M3M4_V1 - select STM32_HAVE_IP_RTCC_M3M4_V1 - select STM32_HAVE_RTC_MAGIC - select STM32_HAVE_RTC - select STM32_HAVE_CRC - select STM32_HAVE_PWR - select STM32_HAVE_IP_SPI_V3 - select STM32_HAVE_IP_SYSCFG_M3M4_V1 - select STM32_HAVE_TIM2_32BITS - select STM32_HAVE_TIM5_32BITS - select STM32_HAVE_IP_USART_V4 - select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV - select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS - select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS - select STM32_HAVE_IP_WDG_M3M4_V1 - bool - default n - select ARCH_CORTEXM4 - select ARCH_HAVE_FPU - select STM32_HAVE_DMAMUX - select STM32_HAVE_IP_DBGMCU_M3M4_V3 - select STM32_HAVE_IP_ADC_M3M4_V2 - select STM32_HAVE_IP_COMP_M3M4_V2 - select STM32_HAVE_IP_DAC_M3M4_V2 - select STM32_HAVE_IP_DMA_V1 - select STM32_HAVE_IP_I2C_M3M4_V2 - select STM32_HAVE_IP_TIMERS_M3M4_V3 - -config STM32_STM32G4_CAT2 - bool - default n - -config STM32_STM32G4_CAT3 - bool - default n - -config STM32_STM32G4_CAT4 - bool - default n - -config STM32_STM32G4XXK - bool - default n - -config STM32_STM32G4XXC - bool - default n - -config STM32_STM32G4XXR - bool - default n - -config STM32_STM32G4XXM - bool - default n - -config STM32_STM32G4XXV - bool - default n - -config STM32_STM32G4XXP - bool - default n - -config STM32_STM32G4XXQ - bool - default n - -config STM32_STM32G43XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT2 - select STM32_HAVE_ADC2 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC3 - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM8 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G431K - bool - default n - -config STM32_STM32G431C - bool - default n - select STM32_HAVE_USART3 - -config STM32_STM32G431R - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431M - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G431V - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - -config STM32_STM32G47XX - bool - default n - select STM32_STM32G4XXX - select STM32_STM32G4_CAT3 - select STM32_HAVE_ADC2 - select STM32_HAVE_ADC3 - select STM32_HAVE_ADC4 - select STM32_HAVE_ADC5 - select STM32_HAVE_CCM - select STM32_HAVE_COMP1 - select STM32_HAVE_COMP2 - select STM32_HAVE_COMP3 - select STM32_HAVE_COMP4 - select STM32_HAVE_COMP5 - select STM32_HAVE_COMP6 - select STM32_HAVE_COMP7 - select STM32_HAVE_CORDIC - select STM32_HAVE_CRS - select STM32_HAVE_DAC1 - select STM32_HAVE_DAC2 - select STM32_HAVE_DAC3 - select STM32_HAVE_DAC4 - select STM32_HAVE_DMA1 - select STM32_HAVE_DMA2 - select STM32_HAVE_FSMC - select STM32_HAVE_FMAC - select STM32_HAVE_FDCAN1 - select STM32_HAVE_FDCAN2 - select STM32_HAVE_HRTIM1 - select STM32_HAVE_I2C2 - select STM32_HAVE_I2C3 - select STM32_HAVE_I2C4 - select STM32_HAVE_I2S3 - select STM32_HAVE_LPTIM1 - select STM32_HAVE_LPUART1 - select STM32_HAVE_OPAMP1 - select STM32_HAVE_OPAMP2 - select STM32_HAVE_OPAMP3 - select STM32_HAVE_OPAMP4 - select STM32_HAVE_OPAMP5 - select STM32_HAVE_OPAMP6 - select STM32_HAVE_QSPI - select STM32_HAVE_RNG - select STM32_HAVE_SPI2 - select STM32_HAVE_SPI3 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_TIM2 - select STM32_HAVE_TIM20 - select STM32_HAVE_TIM3 - select STM32_HAVE_TIM4 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM8 - select STM32_HAVE_USART3 - select STM32_HAVE_UCPD - select STM32_HAVE_USBDEV - -config STM32_STM32G474C - bool - default n - select STM32_HAVE_FDCAN3 - -config STM32_STM32G474M - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474R - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474Q - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -config STM32_STM32G474V - bool - default n - select STM32_HAVE_FDCAN3 - select STM32_HAVE_FMC - select STM32_HAVE_SPI4 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - -# --- restored family-specific symbols over-deleted by move-to-common (split recreates per-family) --- -if ARCH_CHIP_STM32 - -config STM32_VALUELINE - bool - default n - select STM32_HAVE_USART3 - select STM32_HAVE_UART4 - select STM32_HAVE_UART5 - select STM32_HAVE_TIM1 - select STM32_HAVE_TIM5 - select STM32_HAVE_TIM6 - select STM32_HAVE_TIM7 - select STM32_HAVE_TIM12 - select STM32_HAVE_TIM13 - select STM32_HAVE_TIM14 - select STM32_HAVE_TIM15 - select STM32_HAVE_TIM16 - select STM32_HAVE_TIM17 - select STM32_HAVE_SPI2 if STM32_HIGHDENSITY - select STM32_HAVE_SPI3 if STM32_HIGHDENSITY - -choice - prompt "CAN1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_CAN1 - default STM32_CAN1_NO_REMAP - -config STM32_CAN1_NO_REMAP - bool "No pin remapping" - -config STM32_CAN1_REMAP1 - bool "CAN1 alternate pin remapping #1" - -config STM32_CAN1_REMAP2 - bool "CAN1 alternate pin remapping #2" - -endchoice - -config STM32_CAN2_REMAP - bool "CAN2 Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_CAN2 - -config STM32_CEC_REMAP - bool "CEC Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_CEC - -config STM32_ETH_REMAP - bool "Ethernet Alternate Pin Mapping" - default n - depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC - -config STM32_I2C1_REMAP - bool "I2C1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2C1 - -config STM32_SPI1_REMAP - bool "SPI1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI1 - -config STM32_SPI3_REMAP - bool "SPI3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE - -config STM32_I2S3_REMAP - bool "I2S3 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_I2S3 && !STM32_VALUELINE - -choice - prompt "TIM1 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM1 - default STM32_TIM1_NO_REMAP - -config STM32_TIM1_NO_REMAP - bool "No pin remapping" - -config STM32_TIM1_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM1_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -choice - prompt "TIM2 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM2 - default STM32_TIM2_NO_REMAP - -config STM32_TIM2_NO_REMAP - bool "No pin remapping" - -config STM32_TIM2_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM2_PARTIAL_REMAP_1 - bool "Partial pin remapping #1" - -config STM32_TIM2_PARTIAL_REMAP_2 - bool "Partial pin remapping #2" - -endchoice - -choice - prompt "TIM3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_TIM3 - default STM32_TIM3_NO_REMAP - -config STM32_TIM3_NO_REMAP - bool "No pin remapping" - -config STM32_TIM3_FULL_REMAP - bool "Full pin remapping" - -config STM32_TIM3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -config STM32_TIM4_REMAP - bool "TIM4 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM4 - -config STM32_TIM9_REMAP - bool "TIM9 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM9 - -config STM32_TIM10_REMAP - bool "TIM10 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM10 - -config STM32_TIM11_REMAP - bool "TIM11 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM11 - -config STM32_TIM12_REMAP - bool "TIM12 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM12 - -config STM32_TIM13_REMAP - bool "TIM13 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM13 - -config STM32_TIM14_REMAP - bool "TIM14 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM14 - -config STM32_TIM15_REMAP - bool "TIM15 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM15 - -config STM32_TIM16_REMAP - bool "TIM16 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM16 - -config STM32_TIM17_REMAP - bool "TIM17 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_TIM17 - -config STM32_USART1_REMAP - bool "USART1 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART1 - -config STM32_USART2_REMAP - bool "USART2 Alternate Pin Mapping" - default n - depends on STM32_STM32F10XX && STM32_USART2 - -choice - prompt "USART3 Alternate Pin Mappings" - depends on STM32_STM32F10XX && STM32_USART3 - default STM32_USART3_NO_REMAP - -config STM32_USART3_NO_REMAP - bool "No pin remapping" - -config STM32_USART3_FULL_REMAP - bool "Full pin remapping" - -config STM32_USART3_PARTIAL_REMAP - bool "Partial pin remapping" - -endchoice - -endif diff --git a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h deleted file mode 100644 index b499a2cc557..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f10xxx_uart.h +++ /dev/null @@ -1,206 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f10xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F10XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h deleted file mode 100644 index ee01472c30a..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f20xxx_uart.h +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f20xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F20XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h deleted file mode 100644 index 18fc6f1b8b9..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f30xxx_uart.h +++ /dev/null @@ -1,341 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f30xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* Baud Rate Register (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard time and prescaler register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver timeout register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt & status register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt flag clear register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive data register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit data register */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE+STM32_USART_RQR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE+STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE+STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE+STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE+STM32_USART_TDR_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE+STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE+STM32_USART_RQR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE+STM32_USART_GTPR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE+STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE+STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE+STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE+STM32_USART_TDR_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0: USART enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1: USART enable in Stop mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ - -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Receiver wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: Word length */ -#define USART_CR1_MME (1 << 13) /* Bit 13: Mute mode enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14: Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 16-20: Driver Enable deassertion time */ -#define USART_CR1_DEDT_MASK (31 << USART_CR1_DEDT_SHIFT) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 21-25: Driver Enable assertion time */ -#define USART_CR1_DEAT_MASK (31 << USART_CR1_DEAT_SHIFT) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26: Receiver timeout interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27: End of Block interrupt enable */ - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | USART_CR1_TXEIE |\ - USART_CR1_PEIE | USART_CR1_CMIE |USART_CR1_RTOIE | USART_CR1_EOBIE) - -/* Control register 2 */ - -#define USART_CR2_ADDM7 (1 << 4) /* Bit 4: :7-/4-bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ -#define USART_CR2_RXINV (1 << 16) /* Bit 16: RX pin active level inversion */ -#define USART_CR2_TXINV (1 << 17) /* Bit 17: TX pin active level inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Bit 18: Binary data inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* Bit 19: Most significant bit first */ -#define USART_CR2_ABREN (1 << 20) /* Bit 20: Auto baud rate enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Bits 21-22: Auto baud rate mode */ -#define USART_CR2_ABRMOD_MASK (3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_START (0 << USART_CR2_ABRMOD_SHIFT) /* Start bit */ -# define USART_CR2_ABRMOD_FALL (1 << USART_CR2_ABRMOD_SHIFT) /* Falling edge measurement */ -# define USART_CR2_ABRMOD_7F (2 << USART_CR2_ABRMOD_SHIFT) /* 0x7F frame detection */ -# define USART_CR2_ABRMOD_55 (3 << USART_CR2_ABRMOD_SHIFT) /* 0x55 frame detection */ - -#define USART_CR2_RTOEN (1 << 23) /* Bit 23: Receiver timeout enable */ -#define USART_CR2_ADD4L_SHIFT (24) /* Bits 24-17: Address[3:0]:of the USART node */ -#define USART_CR2_ADD4L_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD4H_SHIFT (28) /* Bits 28-31: Address[4:0] of the USART node */ -#define USART_CR2_ADD4H_MASK (15 << USART_CR2_ADD4_SHIFT) -#define USART_CR2_ADD8_SHIFT (24) /* Bits 24-31: Address[7:0] of the USART node */ -#define USART_CR2_ADD8_MASK (255 << USART_CR2_ADD8_SHIFT) - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Bit 12: Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* Bit 13: DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Bit 14: Driver enable mode */ -#define USART_CR3_DEP (1 << 15) /* Bit 15: Driver enable polarity selection */ -#define USART_CR3_SCARCNT_SHIFT (17) /* Bit 17-19: Smartcard auto-retry count */ -#define USART_CR3_SCARCNT_MASK (7 << USART_CR3_SCARCNT_SHIFT) -#define USART_CR3_WUS_SHIFT (20) /* Bit 20-21: Wakeup from Stop mode interrupt */ -#define USART_CR3_WUS_MASK (3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDRMAT (0 << USART_CR3_WUS_SHIFT) /* Active on address match */ -# define USART_CR3_WUS_STARTBIT (2 << USART_CR3_WUS_SHIFT) /* Active on Start bit */ -# define USART_CR3_WUS_RXNE (3 << USART_CR3_WUS_SHIFT) /* Active on RXNE */ - -#define USART_CR3_WUFIE (1 << 22) /* Bit 22: Wakeup from Stop mode interrupt enable */ - -/* Baud Rate Register */ - -#define USART_BRR_SHIFT (0) /* Bits 0-15: USARTDIV[15:0] OVER8=0*/ -#define USART_BRR_MASK (0xffff << USART_BRR_SHIFT) -#define USART_BRR_0_3_SHIFT (0) /* Bits 0-2: USARTDIV[3:0] OVER8=1 */ -#define USART_BRR_0_3_MASK (0x0fff << USART_BRR_0_3_SHIFT) -#define USART_BRR_4_7_SHIFT (0) /* Bits 4-15: USARTDIV[15:4] OVER8=1*/ -#define USART_BRR_4_7_MASK (0xffff << USART_BRR_4_7_SHIFT) - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Receiver timeout register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Bits 0-23: Receiver timeout value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -#define USART_RTOR_BLEN_SHIFT (24) /* Bits 24-31: Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) - -/* Request register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0: Auto baud rate request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1: Send break request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2: Mute mode request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3: Receive data flush request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4: Transmit data flush request */ - -/* Interrupt & status register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0: Parity error */ -#define USART_ISR_FE (1 << 1) /* Bit 1: Framing error */ -#define USART_ISR_NF (1 << 2) /* Bit 2: Noise detected flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3: Overrun error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4: Idle line detected */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5: Read data register not empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ISR_TXE (1 << 7) /* Bit 7: Transmit data register empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8: LIN break detection flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9: CTS interrupt flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10: CTS flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11: Receiver timeout */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12: End of block flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14: Auto baud rate error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15: Auto baud rate flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16: Busy flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17: Character match flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18: Send break flag */ -#define USART_ISR_ISRRWU (1 << 19) /* Bit 19: Receiver wakeup from Mute mode */ -#define USART_ISR_WUF (1 << 20) /* Bit 20: Wakeup from Stop mode flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21: Transmit enable acknowledge flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22: Receive enable acknowledge flag */ - -#define USART_ISR_ALLBITS (0x007fdfff) - -/* Interrupt flag clear register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0: Parity error clear flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1: Framing error clear flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2: Noise detected flag *clear flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3: Overrun error clear flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4: Idle line detected clear flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6: Transmission complete */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8: LIN break detection clear flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9: CTS interrupt clear flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11: Receiver timeout clear flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12: End of block clear flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17: Character match clear flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20: Wakeup from Stop mode clear flag */ - -#define USART_ICR_ALLBITS (0x00121b5f) - -/* Receive data register */ - -#define USART_RDR_SHIFT (0) /* Bits 8:0: Receive data value */ -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) - -/* Transmit data register */ - -#define USART_TDR_SHIFT (0) /* Bits 8:0: Transmit data value */ -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F1/F2/F4 Status register */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NF /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F30XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h b/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h deleted file mode 100644 index edfb2a0cc71..00000000000 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_uart.h +++ /dev/null @@ -1,236 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32f40xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 5 -# define STM32_USART6_SR (STM32_USART6_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART6_DR (STM32_USART6_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART6_BRR (STM32_USART6_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART6_CR1 (STM32_USART6_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART6_CR2 (STM32_USART6_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART6_CR3 (STM32_USART6_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART6_GTPR (STM32_USART6_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 6 -# define STM32_UART7_SR (STM32_UART7_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART7_DR (STM32_UART7_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART7_BRR (STM32_UART7_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART7_CR1 (STM32_UART7_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART7_CR2 (STM32_UART7_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART7_CR3 (STM32_UART7_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 7 -# define STM32_UART8_SR (STM32_UART8_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART8_DR (STM32_UART8_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART8_BRR (STM32_UART8_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART8_CR1 (STM32_UART8_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART8_CR2 (STM32_UART8_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART8_CR3 (STM32_UART8_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0xff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* F3 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32F40XXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h b/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h deleted file mode 100644 index 98990ba21e3..00000000000 --- a/arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h +++ /dev/null @@ -1,439 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32g4xxxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_CR1_OFFSET 0x0000 /* Control Register 1 */ -#define STM32_USART_CR2_OFFSET 0x0004 /* Control Register 2 */ -#define STM32_USART_CR3_OFFSET 0x0008 /* Control Register 3 */ -#define STM32_USART_BRR_OFFSET 0x000c /* BAUD Rate Register */ -#define STM32_USART_GTPR_OFFSET 0x0010 /* Guard Time and Prescaler Register */ -#define STM32_USART_RTOR_OFFSET 0x0014 /* Receiver Timeout Register */ -#define STM32_USART_RQR_OFFSET 0x0018 /* Request Register */ -#define STM32_USART_ISR_OFFSET 0x001c /* Interrupt and Status Register */ -#define STM32_USART_ICR_OFFSET 0x0020 /* Interrupt Flag Clear Register */ -#define STM32_USART_RDR_OFFSET 0x0024 /* Receive Data Register */ -#define STM32_USART_TDR_OFFSET 0x0028 /* Transmit Data Register */ -#define STM32_USART_PRESC_OFFSET 0x002c /* Prescaler Register */ - -/* Register Addresses *******************************************************/ -#if (STM32_NLPUART > 0) -# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_LPUART1_BRR (STM32_LPUART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_LPUART1_RQR (STM32_LPUART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_LPUART1_ISR (STM32_LPUART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_LPUART1_ICR (STM32_LPUART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_LPUART1_RDR (STM32_LPUART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_LPUART1_TDR (STM32_LPUART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 0) -# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART1_RTOR (STM32_USART1_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART1_RQR (STM32_USART1_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART1_ISR (STM32_USART1_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART1_ICR (STM32_USART1_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART1_RDR (STM32_USART1_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART1_TDR (STM32_USART1_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 1) -# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART2_RTOR (STM32_USART2_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART2_RQR (STM32_USART2_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART2_ISR (STM32_USART2_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART2_ICR (STM32_USART2_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART2_RDR (STM32_USART2_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART2_TDR (STM32_USART2_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 2) -# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE + STM32_USART_BRR_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_USART3_RTOR (STM32_USART3_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_USART3_RQR (STM32_USART3_BASE + STM32_USART_RQR_OFFSET) -# define STM32_USART3_ISR (STM32_USART3_BASE + STM32_USART_ISR_OFFSET) -# define STM32_USART3_ICR (STM32_USART3_BASE + STM32_USART_ICR_OFFSET) -# define STM32_USART3_RDR (STM32_USART3_BASE + STM32_USART_RDR_OFFSET) -# define STM32_USART3_TDR (STM32_USART3_BASE + STM32_USART_TDR_OFFSET) -# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 3) -# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART4_GTPR (STM32_UART4_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART4_RTOR (STM32_UART4_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART4_RQR (STM32_UART4_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART4_ISR (STM32_UART4_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART4_ICR (STM32_UART4_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART4_RDR (STM32_UART4_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART4_TDR (STM32_UART4_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET) -#endif - -#if (STM32_NUSART > 4) -# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE + STM32_USART_BRR_OFFSET) -# define STM32_UART5_GTPR (STM32_UART5_BASE + STM32_USART_GTPR_OFFSET) -# define STM32_UART5_RTOR (STM32_UART5_BASE + STM32_USART_RTOR_OFFSET) -# define STM32_UART5_RQR (STM32_UART5_BASE + STM32_USART_RQR_OFFSET) -# define STM32_UART5_ISR (STM32_UART5_BASE + STM32_USART_ISR_OFFSET) -# define STM32_UART5_ICR (STM32_UART5_BASE + STM32_USART_ICR_OFFSET) -# define STM32_UART5_RDR (STM32_UART5_BASE + STM32_USART_RDR_OFFSET) -# define STM32_UART5_TDR (STM32_UART5_BASE + STM32_USART_TDR_OFFSET) -# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Control Register 1 */ - -#define USART_CR1_UE (1 << 0) /* Bit 0 - USART Enable */ -#define USART_CR1_UESM (1 << 1) /* Bit 1 - USART Enable in low power Mode */ -#define USART_CR1_RE (1 << 2) /* Bit 2 - Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3 - Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4 - IDLE Interrupt Enable */ -#define USART_CR1_RXFNEIE (1 << 5) /* Bit 5 in FIFO mode - Rx FIFO Not Empty Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5 in Non-FIFO mode - Rx Data Register Not Empty Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6 - Transmission Complete Interrupt Enable */ -#define USART_CR1_TXFNFIE (1 << 7) /* Bit 7 in FIFO mode - Tx FIFO Not Full Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7 in Non-FIFO mode - Tx Data Register Empty Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8 - PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9 - Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10 - Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11 - Receiver Wakeup method */ -#define USART_CR1_M0 (1 << 12) /* Bit 12 - Word length - Bit 0 */ -#define USART_CR1_MME (1 << 13) /* Bit 13 - Mute Mode Enable */ -#define USART_CR1_CMIE (1 << 14) /* Bit 14 - Character match interrupt enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15 - Oversampling by 8-bit or 16-bit mode */ -#define USART_CR1_DEDT_SHIFT (16) /* Bits 20:16 - Driver Enable Deassertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEDT_MASK (0x1f << USART_CR1_DEDT_SHIFT) -# define USART_CR1_DEDT(n) (((n) << USART_CR1_DEDT_SHIFT) & USART_CR1_DEDT_MASK) -#define USART_CR1_DEAT_SHIFT (21) /* Bits 25:21 - Driver Enable Assertion Time, in 1/16ths or 1/8ths bit time */ -#define USART_CR1_DEAT_MASK (0x1f << USART_CR1_DEAT_SHIFT) -# define USART_CR1_DEAT(n) (((n) << USART_CR1_DEAT_SHIFT) & USART_CR1_DEAT_MASK) -#define USART_CR1_RTOIE (1 << 26) /* Bit 26 - Receive Time Out interrupt enable */ -#define USART_CR1_EOBIE (1 << 27) /* Bit 27 - End of Block interrupt enable */ -#define USART_CR1_M1 (1 << 28) /* Bit 28 - Word length - Bit 1 */ -#define USART_CR1_FIFOEN (1 << 29) /* Bit 29 - FIFO mode enable */ -#define USART_CR1_TXFEIE (1 << 30) /* Bit 30 - TXFIFO empty interrupt enable */ -#define USART_CR1_RXFFIE (1 << 31) /* Bit 31 - RXFIFO Full interrupt enable */ - -#define USART_CR1_M_MASK (USART_CR1_M0 | USART_CR1_M1) - -#define USART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | USART_CR1_RTOIE | \ - USART_CR1_EOBIE | USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -#define LPUART_CR1_ALLINTS \ - (USART_CR1_IDLEIE | USART_CR1_RXNEIE | USART_CR1_TCIE | \ - USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_CMIE | \ - USART_CR1_TXFEIE | USART_CR1_RXFFIE) - -/* Control Register 2 */ - -#define USART_CR2_SLVEN (1 << 0) /* Synchronous Slave Mode Enable */ -#define USART_CR2_DIS_NSS (1 << 3) /* Slave Select (NSS) Pin Ignore For SPI */ -#define USART_CR2_ADDM7 (1 << 4) /* 7-Bit / 4-Bit Address Detection */ -#define USART_CR2_LBDL (1 << 5) /* LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Stop Bit Mode */ -#define USART_CR2_STOP_MASK (0x3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0x0 << USART_CR2_STOP_SHIFT) /* 1 Stop Bit */ -# define USART_CR2_STOP0p5 (0x1 << USART_CR2_STOP_SHIFT) /* 0.5 Stop Bit */ -# define USART_CR2_STOP2 (0x2 << USART_CR2_STOP_SHIFT) /* 2 Stop Bits */ -# define USART_CR2_STOP1p5 (0x3 << USART_CR2_STOP_SHIFT) /* 1.5 Stop Bits */ -#define USART_CR2_LINEN (1 << 14) /* LIN Mode Enable */ -#define USART_CR2_SWAP (1 << 15) /* Swap TX/RX Pins */ -#define USART_CR2_RXINV (1 << 16) /* RX Pin Active Level Inversion */ -#define USART_CR2_TXINV (1 << 17) /* TX Pin Active Level Inversion */ -#define USART_CR2_DATAINV (1 << 18) /* Binary Data Inversion */ -#define USART_CR2_MSBFIRST (1 << 19) /* MSB First */ -#define USART_CR2_ABREN (1 << 20) /* Auto BAUD-Rate Enable */ -#define USART_CR2_ABRMOD_SHIFT (21) /* Auto BAUD-Rate Detection Mode */ -#define USART_CR2_ABRMOD_MASK (0x3 << USART_CR2_ABRMOD_SHIFT) -# define USART_CR2_ABRMOD_STARTBIT (0x0 << USART_CR2_ABRMOD_SHIFT) /* Measurement of Start Bit */ -# define USART_CR2_ABRMOD_FALLEDGE (0x1 << USART_CR2_ABRMOD_SHIFT) /* Falling Edge To Falling Edge */ -# define USART_CR2_ABRMOD_7F_FRAME (0x2 << USART_CR2_ABRMOD_SHIFT) /* 0X7F Frame Detection */ -# define USART_CR2_ABRMOD_55_FRAME (0x3 << USART_CR2_ABRMOD_SHIFT) /* 0X55 Frame Detection */ -#define USART_CR2_RTOEN (1 << 23) /* Receiver Time-Out Enable */ -#define USART_CR2_ADD8_SHIFT (24) /* Address of the USART Node */ -#define USART_CR2_ADD8_MASK (0xff << USART_CR2_ADD8_SHIFT) - -/* Control Register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* IrDA Mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* SmartCard NACK Enable */ -#define USART_CR3_SCEN (1 << 5) /* SmartCard Mode Enable */ -#define USART_CR3_DMAR (1 << 6) /* DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* One Sample Bit Method Enable */ -#define USART_CR3_OVRDIS (1 << 12) /* Overrun Disable */ -#define USART_CR3_DDRE (1 << 13) /* DMA Disable on Reception Error */ -#define USART_CR3_DEM (1 << 14) /* Driver Enable Mode */ -#define USART_CR3_DEP (1 << 15) -#define USART_CR3_SCARCNT_SHIFT (17) /* SmartCard Auto-Retry Count */ -#define USART_CR3_SCARCNT_MASK (0x7 << USART_CR3_SCARCNT_SHIFT) -# define USART_CR3_SCARCNT(n) (((n) << USART_CR3_SCARCNT_SHIFT) & USART_CR3_SCARCNT_MASK) -#define USART_CR3_WUS_SHIFT (20) /* Wake Up From Low Power Mode Interrupt Flag Selection) */ -#define USART_CR3_WUS_MASK (0x3 << USART_CR3_WUS_SHIFT) -# define USART_CR3_WUS_ADDR (0x0 << USART_CR3_WUS_SHIFT) /* On Address Match */ -# define USART_CR3_WUS_STARTBIT (0x2 << USART_CR3_WUS_SHIFT) /* On Start Bit Detection */ -# define USART_CR3_WUS_RXFNE (0x3 << USART_CR3_WUS_SHIFT) /* On RXNE/RXFNE */ -#define USART_CR3_WUFIE (1 << 22) /* Wake Up From Low Power Mode Interrupt Enable */ -#define USART_CR3_TXFTIE (1 << 23) /* Transmit FIFO Threshold Interrupt Enable */ -#define USART_CR3_TCBGTIE (1 << 24) /* Transmit Complete Before Guard Time Interrupt Enable */ -#define USART_CR3_RXFTCFG_SHIFT (25) /* Receive FIFO Threshold Configuration */ -#define USART_CR3_RXFTCFG_MASK (0x7 << USART_CR3_RXFTCFG_SHIFT) -# define USART_CR3_RXFTCFG_1_8 (0x0 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_RXFTCFG_1_4 (0x1 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_RXFTCFG_1_2 (0x2 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 1/2 Depth */ -# define USART_CR3_RXFTCFG_3_4 (0x3 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_RXFTCFG_7_8 (0x4 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_RXFTCFG_FULL (0x5 << USART_CR3_RXFTCFG_SHIFT) /* When Rx FIFO Is Full */ -#define USART_CR3_RXFTIE (1 << 28) /* Receive FIFO Threshold Interrupt Enable */ -#define USART_CR3_TXFTCFG_SHIFT (29) /* Transmit FIFO Threshold Configuration */ -#define USART_CR3_TXFTCFG_MASK (0x7 << USART_CR3_TXFTCFG_SHIFT) -# define USART_CR3_TXFTCFG_1_8 (0x0 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/8Th Depth */ -# define USART_CR3_TXFTCFG_1_4 (0x1 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/4Th Depth */ -# define USART_CR3_TXFTCFG_1_2 (0x2 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 1/2 Depth */ -# define USART_CR3_TXFTCFG_3_4 (0x3 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 3/4Ths Depth */ -# define USART_CR3_TXFTCFG_7_8 (0x4 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Reaches 7/8Ths Depth */ -# define USART_CR3_TXFTCFG_FULL (0x5 << USART_CR3_TXFTCFG_SHIFT) /* When Tx FIFO Is Full */ - -/* BAUD Rate Register */ - -/* Full BRR field */ - -#define USART_BRR_SHIFT (0) -#define USART_BRR_MASK (0xffff << USART_BRR_BRR_SHIFT) -# define USART_BRR(n) (((n) << USART_BRR_BRR_SHIFT) & USART_BRR_BRR_MASK) - -/* Partial BRR field BRR[3:0]: - * - * When OVER8 = 0: BRR[3:0] = USARTDIV[3:0] - * - * When OVER8 = 1: BRR[2:0] = (USARTDIV[3:0] >> 1) and - * BRR[3] must be kept cleared. - */ - -#define USART_BRR_0_3_SHIFT (0) -#define USART_BRR_0_3_MASK (0xf << USART_BRR_0_3_SHIFT) -# define USART_BRR_0_3(n) (((n) << USART_BRR_0_3_SHIFT) & USART_BRR_0_3_MASK) - -/* Partial BRR field BRR[15:4]: - * BRR[15:4] = USARTDIV[15:4] - */ - -#define USART_BRR_4_15_SHIFT (4) -#define USART_BRR_4_15_MASK (0xfff << USART_BRR_4_15_SHIFT) -# define USART_BRR_4_15(n) (((n) << USART_BRR_4_15_SHIFT) & USART_BRR_4_15_MASK) - -/* Guard Time and Prescaler Register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Prescaler Value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -# define USART_GTPR_PSC(n) (((n) << USART_GTPR_PSC_SHIFT) & USART_GTPR_PSC_MASK) -#define USART_GTPR_GT_SHIFT (8) /* Guard Time Value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) -# define USART_GTPR_GT(n) (((n) << USART_GTPR_GT_SHIFT) & USART_GTPR_GT_MASK) - -/* Receiver Timeout Register */ - -#define USART_RTOR_RTO_SHIFT (0) /* Receiver Time Out Value */ -#define USART_RTOR_RTO_MASK (0xffffff << USART_RTOR_RTO_SHIFT) -# define USART_RTOR_RTO(n) (((n) << USART_RTOR_RTO_SHIFT) & USART_RTOR_RTO_MASK) -#define USART_RTOR_BLEN_SHIFT (24) /* Block Length */ -#define USART_RTOR_BLEN_MASK (0xff << USART_RTOR_BLEN_SHIFT) -# define USART_RTOR_BLEN(n) (((n) << USART_RTOR_BLEN_SHIFT) & USART_RTOR_BLEN_MASK) - -/* Request Register */ - -#define USART_RQR_ABRRQ (1 << 0) /* Bit 0 - Auto-Baud Rate Request */ -#define USART_RQR_SBKRQ (1 << 1) /* Bit 1 - Send Break Request */ -#define USART_RQR_MMRQ (1 << 2) /* Bit 2 - Mute Mode Request */ -#define USART_RQR_RXFRQ (1 << 3) /* Bit 3 - Receive Data Flush Request */ -#define USART_RQR_TXFRQ (1 << 4) /* Bit 4 - Transmit Data Flush Request */ - -/* Interrupt and Status Register */ - -#define USART_ISR_PE (1 << 0) /* Bit 0 - Parity Error */ -#define USART_ISR_FE (1 << 1) /* Bit 1 - Framing Error */ -#define USART_ISR_NE (1 << 2) /* Bit 2 - Noise Detected Flag */ -#define USART_ISR_ORE (1 << 3) /* Bit 3 - Overrun Error */ -#define USART_ISR_IDLE (1 << 4) /* Bit 4 - Idle Line Detected */ -#define USART_ISR_RXFNE (1 << 5) /* Bit 5 (When FIFO in use) - Rx FIFO Not Empty */ -#define USART_ISR_RXNE (1 << 5) /* Bit 5 (When FIFO not in use) - Rx Data Register Not Empty */ -#define USART_ISR_TC (1 << 6) /* Bit 6 - Transmission Complete */ -#define USART_ISR_TXFNF (1 << 7) /* Bit 7 (When FIFO in use) - Tx FIFO Not Full */ -#define USART_ISR_TXE (1 << 7) /* Bit 7 (When FIFO not in use) - Tx Data Register Empty */ -#define USART_ISR_LBDF (1 << 8) /* Bit 8 - LIN Break Detection Flag */ -#define USART_ISR_CTSIF (1 << 9) /* Bit 9 - CTS Interrupt Flag */ -#define USART_ISR_CTS (1 << 10) /* Bit 10 - CTS Flag */ -#define USART_ISR_RTOF (1 << 11) /* Bit 11 - Receiver Time Out */ -#define USART_ISR_EOBF (1 << 12) /* Bit 12 - End of Block Flag */ -#define USART_ISR_UDR (1 << 13) /* Bit 13 - SPI Slave Underrun Error Flag */ -#define USART_ISR_ABRE (1 << 14) /* Bit 14 - Auto BAUD Rate Error */ -#define USART_ISR_ABRF (1 << 15) /* Bit 15 - Auto BAUD Rate Flag */ -#define USART_ISR_BUSY (1 << 16) /* Bit 16 - Busy Flag */ -#define USART_ISR_CMF (1 << 17) /* Bit 17 - Character Match Flag */ -#define USART_ISR_SBKF (1 << 18) /* Bit 18 - Send Break Flag */ -#define USART_ISR_RWU (1 << 19) /* Bit 19 - Receive Wake Up From Mute Mode Flag */ -#define USART_ISR_WUF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Flag */ -#define USART_ISR_TEACK (1 << 21) /* Bit 21 - Transmit Enable Acknowledge Flag */ -#define USART_ISR_REACK (1 << 22) /* Bit 22 - Receive Enable Acknowledge Flag */ -#define USART_ISR_TXFE (1 << 23) /* Bit 23 (When FIFO in use) - Tx FIFO Empty */ -#define USART_ISR_RXFF (1 << 24) /* Bit 24 (When FIFO in use) - Rx FIFO Full */ -#define USART_ISR_TCBGT (1 << 25) /* Bit 25 - Transmission Complete Before Guard Time Completion */ -#define USART_ISR_RXFT (1 << 26) /* Bit 26 (When FIFO in use) - Rx FIFO Threshold Flag */ -#define USART_ISR_TXFT (1 << 27) /* Bit 27 (When FIFO in use) - Tx FIFO Threshold Flag */ - -#define USART_ISR_ALLBITS (0x0fffffff) - -/* Interrupt Flag Clear Register */ - -#define USART_ICR_PECF (1 << 0) /* Bit 0 - Parity Error Clear Flag */ -#define USART_ICR_FECF (1 << 1) /* Bit 1 - Framing Error Clear Flag */ -#define USART_ICR_NCF (1 << 2) /* Bit 2 - Noise detected Clear Flag */ -#define USART_ICR_ORECF (1 << 3) /* Bit 3 - OverRun Error Clear Flag */ -#define USART_ICR_IDLECF (1 << 4) /* Bit 4 - Idle Line Detected Clear Flag */ -#define USART_ICR_TXFECF (1 << 5) /* Bit 5 - Tx FIFO Empty Clear Flag */ -#define USART_ICR_TCCF (1 << 6) /* Bit 6 - Transmission Complete Clear Flag */ -#define USART_ICR_TCBGTCF (1 << 7) /* Bit 7 - Transmission Complete Before Guard Time Clear Flag */ -#define USART_ICR_LBDCF (1 << 8) /* Bit 8 - LIN Break Detection Clear Flag */ -#define USART_ICR_CTSCF (1 << 9) /* Bit 9 - CTS Interrupt Clear Flag */ -#define USART_ICR_RTOCF (1 << 11) /* Bit 11 - Receiver Timeout Clear Flag */ -#define USART_ICR_EOBCF (1 << 12) /* Bit 12 - End of Block Clear Flag */ -#define USART_ICR_UDRCF (1 << 13) /* Bit 13 - SPI Slave Underrun Clear Flag */ -#define USART_ICR_CMCF (1 << 17) /* Bit 17 - Character Match Clear Flag */ -#define USART_ICR_WUCF (1 << 20) /* Bit 20 - Wake Up From Stop Mode Clear Flag */ - -/* Receive Data Register */ - -#define USART_RDR_SHIFT (0) -#define USART_RDR_MASK (0x1ff << USART_RDR_SHIFT) -# define USART_RDR(n) (((n) << USART_RDR_SHIFT) & USART_RDR_MASK) - -/* Transmit Data Register */ - -#define USART_TDR_SHIFT (0) -#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT) -# define USART_TDR(n) (((n) << USART_TDR_SHIFT) & USART_TDR_MASK) - -/* Prescaler Register */ - -#define USART_PRESC_PRESCALER_SHIFT (0) -#define USART_PRESC_PRESCALER_MASK (0xf << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_1 (0x0 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_2 (0x1 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_4 (0x2 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_6 (0x3 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_8 (0x4 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_10 (0x5 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_12 (0x6 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_16 (0x7 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_32 (0x8 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_64 (0x9 << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_128 (0xa << USART_PRESC_PRESCALER_SHIFT) -#define USART_PRESC_PRESCALER_256 (0xb << USART_PRESC_PRESCALER_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* Compatibility with F1/F2/F4 Status Register names */ - -#define STM32_USART_SR_OFFSET STM32_USART_ISR_OFFSET - -#define USART_SR_PE USART_ISR_PE /* Parity Error */ -#define USART_SR_FE USART_ISR_FE /* Framing error */ -#define USART_SR_NE USART_ISR_NE /* Noise detected flag */ -#define USART_SR_ORE USART_ISR_ORE /* Overrun error */ -#define USART_SR_IDLE USART_ISR_IDLE /* IDLE line detected */ -#define USART_SR_RXNE USART_ISR_RXNE /* Read Data Register Not Empty */ -#define USART_SR_TC USART_ISR_TC /* Transmission Complete */ -#define USART_SR_TXE USART_ISR_TXE /* Transmit Data Register Empty */ -#define USART_SR_LBD USART_ISR_LBDF /* LIN Break Detection Flag */ -#define USART_SR_CTS USART_ISR_CTS /* CTS Flag */ - -#define USART_SR_ALLBITS USART_ISR_ALLBITS - -#define USART_CR1_M USART_CR1_M0 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32G4XXXX_UART_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h b/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h deleted file mode 100644 index f3cb64060db..00000000000 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_uart.h +++ /dev/null @@ -1,208 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_uart.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H -#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register Offsets *********************************************************/ - -#define STM32_USART_SR_OFFSET 0x0000 /* Status register (32-bits) */ -#define STM32_USART_DR_OFFSET 0x0004 /* Data register (32-bits) */ -#define STM32_USART_BRR_OFFSET 0x0008 /* Baud Rate Register (32-bits) */ -#define STM32_USART_CR1_OFFSET 0x000c /* Control register 1 (32-bits) */ -#define STM32_USART_CR2_OFFSET 0x0010 /* Control register 2 (32-bits) */ -#define STM32_USART_CR3_OFFSET 0x0014 /* Control register 3 (32-bits) */ -#define STM32_USART_GTPR_OFFSET 0x0018 /* Guard time and prescaler register (32-bits) */ - -/* Register Addresses *******************************************************/ - -#if STM32_NUSART > 0 -# define STM32_USART1_SR (STM32_USART1_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART1_DR (STM32_USART1_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART1_BRR (STM32_USART1_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART1_CR1 (STM32_USART1_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART1_CR2 (STM32_USART1_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART1_CR3 (STM32_USART1_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART1_GTPR (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 1 -# define STM32_USART2_SR (STM32_USART2_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART2_DR (STM32_USART2_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART2_BRR (STM32_USART2_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART2_CR1 (STM32_USART2_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART2_CR2 (STM32_USART2_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART2_CR3 (STM32_USART2_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART2_GTPR (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 2 -# define STM32_USART3_SR (STM32_USART3_BASE+STM32_USART_SR_OFFSET) -# define STM32_USART3_DR (STM32_USART3_BASE+STM32_USART_DR_OFFSET) -# define STM32_USART3_BRR (STM32_USART3_BASE+STM32_USART_BRR_OFFSET) -# define STM32_USART3_CR1 (STM32_USART3_BASE+STM32_USART_CR1_OFFSET) -# define STM32_USART3_CR2 (STM32_USART3_BASE+STM32_USART_CR2_OFFSET) -# define STM32_USART3_CR3 (STM32_USART3_BASE+STM32_USART_CR3_OFFSET) -# define STM32_USART3_GTPR (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET) -#endif - -#if STM32_NUSART > 3 -# define STM32_UART4_SR (STM32_UART4_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART4_DR (STM32_UART4_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART4_BRR (STM32_UART4_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART4_CR1 (STM32_UART4_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART4_CR2 (STM32_UART4_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART4_CR3 (STM32_UART4_BASE+STM32_USART_CR3_OFFSET) -#endif - -#if STM32_NUSART > 4 -# define STM32_UART5_SR (STM32_UART5_BASE+STM32_USART_SR_OFFSET) -# define STM32_UART5_DR (STM32_UART5_BASE+STM32_USART_DR_OFFSET) -# define STM32_UART5_BRR (STM32_UART5_BASE+STM32_USART_BRR_OFFSET) -# define STM32_UART5_CR1 (STM32_UART5_BASE+STM32_USART_CR1_OFFSET) -# define STM32_UART5_CR2 (STM32_UART5_BASE+STM32_USART_CR2_OFFSET) -# define STM32_UART5_CR3 (STM32_UART5_BASE+STM32_USART_CR3_OFFSET) -#endif - -/* Register Bitfield Definitions ********************************************/ - -/* Status register */ - -#define USART_SR_PE (1 << 0) /* Bit 0: Parity Error */ -#define USART_SR_FE (1 << 1) /* Bit 1: Framing Error */ -#define USART_SR_NE (1 << 2) /* Bit 2: Noise Error Flag */ -#define USART_SR_ORE (1 << 3) /* Bit 3: OverRun Error */ -#define USART_SR_IDLE (1 << 4) /* Bit 4: IDLE line detected */ -#define USART_SR_RXNE (1 << 5) /* Bit 5: Read Data Register Not Empty */ -#define USART_SR_TC (1 << 6) /* Bit 6: Transmission Complete */ -#define USART_SR_TXE (1 << 7) /* Bit 7: Transmit Data Register Empty */ -#define USART_SR_LBD (1 << 8) /* Bit 8: LIN Break Detection Flag */ -#define USART_SR_CTS (1 << 9) /* Bit 9: CTS Flag */ - -#define USART_SR_ALLBITS (0x03ff) -#define USART_SR_CLRBITS (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */ - -/* Data register */ - -#define USART_DR_SHIFT (0) /* Bits 8:0: Data value */ -#define USART_DR_MASK (0x1ff << USART_DR_SHIFT) - -/* Baud Rate Register */ - -#define USART_BRR_FRAC_SHIFT (0) /* Bits 3-0: fraction of USARTDIV */ -#define USART_BRR_FRAC_MASK (0x0f << USART_BRR_FRAC_SHIFT) -#define USART_BRR_MANT_SHIFT (4) /* Bits 15-4: mantissa of USARTDIV */ -#define USART_BRR_MANT_MASK (0x0fff << USART_BRR_MANT_SHIFT) - -/* Control register 1 */ - -#define USART_CR1_SBK (1 << 0) /* Bit 0: Send Break */ -#define USART_CR1_RWU (1 << 1) /* Bit 1: Receiver wakeup */ -#define USART_CR1_RE (1 << 2) /* Bit 2: Receiver Enable */ -#define USART_CR1_TE (1 << 3) /* Bit 3: Transmitter Enable */ -#define USART_CR1_IDLEIE (1 << 4) /* Bit 4: IDLE Interrupt Enable */ -#define USART_CR1_RXNEIE (1 << 5) /* Bit 5: RXNE Interrupt Enable */ -#define USART_CR1_TCIE (1 << 6) /* Bit 6: Transmission Complete Interrupt Enable */ -#define USART_CR1_TXEIE (1 << 7) /* Bit 7: TXE Interrupt Enable */ -#define USART_CR1_PEIE (1 << 8) /* Bit 8: PE Interrupt Enable */ -#define USART_CR1_PS (1 << 9) /* Bit 9: Parity Selection */ -#define USART_CR1_PCE (1 << 10) /* Bit 10: Parity Control Enable */ -#define USART_CR1_WAKE (1 << 11) /* Bit 11: Wakeup method */ -#define USART_CR1_M (1 << 12) /* Bit 12: word length */ -#define USART_CR1_UE (1 << 13) /* Bit 13: USART Enable */ -#define USART_CR1_OVER8 (1 << 15) /* Bit 15: Oversampling mode */ - -#define USART_CR1_ALLINTS (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE) - -/* Control register 2 */ - -#define USART_CR2_ADD_SHIFT (0) /* Bits 3-0: Address of the USART node */ -#define USART_CR2_ADD_MASK (0x0f << USART_CR2_ADD_SHIFT) -#define USART_CR2_LBDL (1 << 5) /* Bit 5: LIN Break Detection Length */ -#define USART_CR2_LBDIE (1 << 6) /* Bit 6: LIN Break Detection Interrupt Enable */ -#define USART_CR2_LBCL (1 << 8) /* Bit 8: Last Bit Clock pulse */ -#define USART_CR2_CPHA (1 << 9) /* Bit 9: Clock Phase */ -#define USART_CR2_CPOL (1 << 10) /* Bit 10: Clock Polarity */ -#define USART_CR2_CLKEN (1 << 11) /* Bit 11: Clock Enable */ -#define USART_CR2_STOP_SHIFT (12) /* Bits 13-12: STOP bits */ -#define USART_CR2_STOP_MASK (3 << USART_CR2_STOP_SHIFT) -# define USART_CR2_STOP1 (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */ -# define USART_CR2_STOP0p5 (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */ -# define USART_CR2_STOP2 (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */ -# define USART_CR2_STOP1p5 (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */ - -#define USART_CR2_LINEN (1 << 14) /* Bit 14: LIN mode enable */ - -/* Control register 3 */ - -#define USART_CR3_EIE (1 << 0) /* Bit 0: Error Interrupt Enable */ -#define USART_CR3_IREN (1 << 1) /* Bit 1: IrDA mode Enable */ -#define USART_CR3_IRLP (1 << 2) /* Bit 2: IrDA Low-Power */ -#define USART_CR3_HDSEL (1 << 3) /* Bit 3: Half-Duplex Selection */ -#define USART_CR3_NACK (1 << 4) /* Bit 4: Smartcard NACK enable */ -#define USART_CR3_SCEN (1 << 5) /* Bit 5: Smartcard mode enable */ -#define USART_CR3_DMAR (1 << 6) /* Bit 6: DMA Enable Receiver */ -#define USART_CR3_DMAT (1 << 7) /* Bit 7: DMA Enable Transmitter */ -#define USART_CR3_RTSE (1 << 8) /* Bit 8: RTS Enable */ -#define USART_CR3_CTSE (1 << 9) /* Bit 9: CTS Enable */ -#define USART_CR3_CTSIE (1 << 10) /* Bit 10: CTS Interrupt Enable */ -#define USART_CR3_ONEBIT (1 << 11) /* Bit 11: One sample bit method enable */ - -/* Guard time and prescaler register */ - -#define USART_GTPR_PSC_SHIFT (0) /* Bits 0-7: Prescaler value */ -#define USART_GTPR_PSC_MASK (0xff << USART_GTPR_PSC_SHIFT) -#define USART_GTPR_GT_SHIFT (8) /* Bits 8-15: Guard time value */ -#define USART_GTPR_GT_MASK (0xff << USART_GTPR_GT_SHIFT) - -/* Compatibility definitions ************************************************/ - -/* L15 Transmit/Read registers */ - -#define STM32_USART_RDR_OFFSET STM32_USART_DR_OFFSET /* Receive data register */ -#define STM32_USART_TDR_OFFSET STM32_USART_DR_OFFSET /* Transmit data register */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32L15XXX_UART_H */ diff --git a/arch/arm/src/stm32/stm32_pm.h b/arch/arm/src/stm32/stm32_pm.h deleted file mode 100644 index 7d66d3b209f..00000000000 --- a/arch/arm/src/stm32/stm32_pm.h +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_pm.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_PM_H -#define __ARCH_ARM_SRC_STM32_STM32_PM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "chip.h" -#include "arm_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_pmstop - * - * Description: - * Enter STOP mode. - * - * Input Parameters: - * lpds - true: To further reduce power consumption in Stop mode, put the - * internal voltage regulator in low-power mode using the LPDS bit - * of the Power control register (PWR_CR). - * - * Returned Value: - * Zero means that the STOP was successfully entered and the system has - * been re-awakened. The internal voltage regulator is back to its - * original state. Otherwise, STOP mode did not occur and a negated - * errno value is returned to indicate the cause of the failure. - * - ****************************************************************************/ - -int stm32_pmstop(bool lpds); - -/**************************************************************************** - * Name: stm32_pmstandby - * - * Description: - * Enter STANDBY mode. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, this function will not return (STANDBY mode can only be - * terminated with a reset event). Otherwise, STANDBY mode did not occur - * and a negated errno value is returned to indicate the cause of the - * failure. - * - ****************************************************************************/ - -int stm32_pmstandby(void); - -/**************************************************************************** - * Name: stm32_pmsleep - * - * Description: - * Enter SLEEP mode. - * - * Input Parameters: - * sleeponexit - true: SLEEPONEXIT bit is set when the WFI instruction is - * executed, the MCU enters Sleep mode as soon as it - * exits the lowest priority ISR. - * - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep - * mode as soon as WFI or WFE instruction is executed. - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_pmsleep(bool sleeponexit); - -#undef EXTERN -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_ARM_SRC_STM32_STM32_PM_H */ diff --git a/arch/arm/src/stm32/stm32_rcc.h b/arch/arm/src/stm32/stm32_rcc.h deleted file mode 100644 index cfead6ee3e4..00000000000 --- a/arch/arm/src/stm32/stm32_rcc.h +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_rcc.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_RCC_H -#define __ARCH_ARM_SRC_STM32_STM32_RCC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "arm_internal.h" -#include "chip.h" - -#if defined(CONFIG_STM32_STM32L15XX) -# include "hardware/stm32l15xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F10XX) -# include "hardware/stm32f10xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F20XX) -# include "hardware/stm32f20xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F30XX) -# include "hardware/stm32f30xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F33XX) -# include "hardware/stm32f33xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F37XX) -# include "hardware/stm32f37xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32F4XXX) -# include "hardware/stm32f40xxx_rcc.h" -#elif defined(CONFIG_STM32_STM32G4XXX) -# include "hardware/stm32g4xxxx_rcc.h" -#else -# error "Unsupported STM32 chip" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_mco1config - * - * Description: - * Selects the clock source to output on MCO1 pin (PA8). PA8 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO1 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1_HSI, RCC_CFGR_MCO1_LSE, - * RCC_CFGR_MCO1_HSE, RCC_CFGR_MCO1_PLL} - * div - One of the definitions for the RCC_CFGR_MCO1PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO1PRE_NONE, RCC_CFGR_MCO1PRE_DIV2, - * RCC_CFGR_MCO1PRE_DIV3, RCC_CFGR_MCO1PRE_DIV4, RCC_CFGR_MCO1PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco1config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO1_MASK | RCC_CFGR_MCO1PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcoconfig - * - * Description: - * Selects the clock source to output on MC pin (PA8) for stm32f10xxx. - * PA8 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO definitions from - * chip/stm32f10xxx_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK, - * RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK, - * RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_CONNECTIVITYLINE) -static inline void stm32_mcoconfig(uint32_t source) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO_MASK); - regval |= (source & RCC_CFGR_MCO_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mcodivconfig - * - * Description: - * Selects the clock source to output and clock divider on MC pin (PA4) for - * stm32l1xxx. PA4 should be configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCOSEL definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOSEL_DISABLED, RCC_CFGR_MCOSEL_SYSCLK, - * RCC_CFGR_MCOSEL_HSICLK, RCC_CFGR_MCOSEL_MSICLK, - * RCC_CFGR_MCOSEL_HSECLK, RCC_CFGR_MCOSEL_PLLCLK, - * RCC_CFGR_MCOSEL_LSICLK, RCC_CFGR_MCOSEL_LSECLK} - * divider - One of the definitions for the RCC_CFGR_MCOPRE definitions - * from chip/stm32l15xxx_rcc.h - * {RCC_CFGR_MCOPRE_DIV1, RCC_CFGR_MCOPRE_DIV2, - * RCC_CFGR_MCOPRE_DIV4, RCC_CFGR_MCOPRE_DIV8, RCC_CFGR_MCOPRE_DIV16} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32L15XX) -static inline void stm32_mcodivconfig(uint32_t source, uint32_t divider) -{ - uint32_t regval; - - /* Set MCO source */ - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCOSEL_MASK); - regval |= (source & RCC_CFGR_MCOSEL_MASK); - regval &= ~(RCC_CFGR_MCOPRE_MASK); - regval |= (divider & RCC_CFGR_MCOPRE_MASK); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Name: stm32_mco2config - * - * Description: - * Selects the clock source to output on MCO2 pin (PC9). PC9 should be - * configured in alternate function mode. - * - * Input Parameters: - * source - One of the definitions for the RCC_CFGR_MCO2 definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2_SYSCLK, RCC_CFGR_MCO2_PLLI2S, - * RCC_CFGR_MCO2_HSE, RCC_CFGR_MCO2_PLL} - * div - One of the definitions for the RCC_CFGR_MCO2PRE definitions from - * chip/stm32f4xxxx_rcc.h {RCC_CFGR_MCO2PRE_NONE, RCC_CFGR_MCO2PRE_DIV2, - * RCC_CFGR_MCO2PRE_DIV3, RCC_CFGR_MCO2PRE_DIV4, RCC_CFGR_MCO2PRE_DIV5} - * - * Returned Value: - * None - * - ****************************************************************************/ - -#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F4XXX) -static inline void stm32_mco2config(uint32_t source, uint32_t div) -{ - uint32_t regval; - - regval = getreg32(STM32_RCC_CFGR); - regval &= ~(RCC_CFGR_MCO2_MASK | RCC_CFGR_MCO2PRE_MASK); - regval |= (source | div); - putreg32(regval, STM32_RCC_CFGR); -} -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_clockconfig - * - * Description: - * Called to establish the clock settings based on the values in board.h. - * This function (by default) will reset most everything, enable the PLL, - * and enable peripheral clocking for all periperipherals enabled in the - * NuttX configuration file. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_clockconfig(void); - -/**************************************************************************** - * Name: stm32_board_clockconfig - * - * Description: - * Any STM32 board may replace the "standard" board clock configuration - * logic with its own, custom clock configuration logic. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG -void stm32_board_clockconfig(void); -#endif - -/**************************************************************************** - * Name: stm32_clockenable - * - * Description: - * Re-enable the clock and restore the clock settings based on settings in - * board.h. - * This function is only available to support low-power modes of operation: - * When re-awakening from deep-sleep modes, it is necessary to re-enable/ - * re-start the PLL - * - * This functional performs a subset of the operations performed by - * stm32_clockconfig(): It does not reset any devices, and it does not - * reset the currently enabled peripheral clocks. - * - * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking - * will be enabled by an externally provided, board-specific function - * called stm32_board_clockconfig(). - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_PM -void stm32_clockenable(void); -#endif - -/**************************************************************************** - * Name: stm32_rcc_enablelse - * - * Description: - * Enable the External Low-Speed (LSE) Oscillator. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void stm32_rcc_enablelse(void); - -/**************************************************************************** - * Name: stm32_rcc_enablelsi - * - * Description: - * Enable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_enablelsi(void); - -/**************************************************************************** - * Name: stm32_rcc_disablelsi - * - * Description: - * Disable the Internal Low-Speed (LSI) RC Oscillator. - * - ****************************************************************************/ - -void stm32_rcc_disablelsi(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_RCC_H */ diff --git a/arch/arm/src/stm32/stm32_userspace.h b/arch/arm/src/stm32/stm32_userspace.h deleted file mode 100644 index 8cdb47e52ff..00000000000 --- a/arch/arm/src/stm32/stm32_userspace.h +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * arch/arm/src/stm32/stm32_userspace.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H -#define __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_userspace - * - * Description: - * For the case of the separate user-/kernel-space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the user space .data and .bss - * segments. - * - ****************************************************************************/ - -#ifdef CONFIG_BUILD_PROTECTED -void stm32_userspace(void); -#endif - -#endif /* __ARCH_ARM_SRC_STM32_STM32_USERSPACE_H */ diff --git a/arch/arm/src/stm32f7/stm32_can_sock.c b/arch/arm/src/stm32f7/stm32_can_sock.c index 14f9ccda020..327dc5c59a7 100644 --- a/arch/arm/src/stm32f7/stm32_can_sock.c +++ b/arch/arm/src/stm32f7/stm32_can_sock.c @@ -49,7 +49,7 @@ #include "stm32_rcc.h" #include "stm32_can.h" -/* Ported form arch/arm/src/stm32/stm32_can_sock.c */ +/* Ported form arch/arm/src/common/stm32/stm32_can_m3m4_v1_sock.c */ /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index 5932b37c80d..9f51388aaee 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -78,7 +78,8 @@ * * Currently, up to two FOC instances are supported. * - * This implementation is based on arch/arm/src/stm32/stm32_foc.c + * This implementation is based on + * arch/arm/src/common/stm32/stm32_foc_m3m4_v1.c */ /* Verify system configuration **********************************************/ diff --git a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt b/arch/arm/src/stm32l1/CMakeLists.txt similarity index 84% rename from boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt rename to arch/arm/src/stm32l1/CMakeLists.txt index 1f40202c329..1067ff19101 100644 --- a/boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +++ b/arch/arm/src/stm32l1/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/mikroe-stm32f4/CMakeLists.txt +# arch/arm/src/stm32l1/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,9 @@ # # ############################################################################## -add_subdirectory(src) +set(SRCS) + +list(APPEND SRCS stm32_rcc.c) + +target_sources(arch PRIVATE ${SRCS}) +add_subdirectory(${NUTTX_DIR}/arch/arm/src/common/stm32 stm32_common) diff --git a/arch/arm/src/stm32l1/Kconfig b/arch/arm/src/stm32l1/Kconfig new file mode 100644 index 00000000000..129f60d8271 --- /dev/null +++ b/arch/arm/src/stm32l1/Kconfig @@ -0,0 +1,356 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +comment "STM32 L1 configuration" + +if ARCH_CHIP_STM32L1 + +choice + prompt "STM32L1 Chip Selection" + depends on ARCH_CHIP_STM32L1 + +config ARCH_CHIP_STM32L151C6 + bool "STM32L151C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151C8 + bool "STM32L151C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151CB + bool "STM32L151CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R6 + bool "STM32L151R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151R8 + bool "STM32L151R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151RB + bool "STM32L151RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V6 + bool "STM32L151V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151V8 + bool "STM32L151V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L151VB + bool "STM32L151VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM + +config ARCH_CHIP_STM32L152C6 + bool "STM32L152C6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152C8 + bool "STM32L152C8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152CB + bool "STM32L152CB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 48-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152R6 + bool "STM32L152R6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152R8 + bool "STM32L152R8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152RB + bool "STM32L152RB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 64-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152V6 + bool "STM32L152V6" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 32KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152V8 + bool "STM32L152V8" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 64KB FLASH, 10KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152VB + bool "STM32L152VB" + select STM32_STM32L15XX + select STM32L1_LOWDENSITY + ---help--- + STM32L 100-pin EnergyLite, 128KB FLASH, 16KB SRAM, 4KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L152CC + bool "STM32L152CC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 48-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x18 LCD interface + +config ARCH_CHIP_STM32L152RC + bool "STM32L152RC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 64-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x32/8x28 LCD interface + +config ARCH_CHIP_STM32L152VC + bool "STM32L152VC" + select STM32_STM32L15XX + select STM32L1_MEDIUMPLUSDENSITY + ---help--- + STM32L 100-pin EnergyLite, 256KB FLASH, 32KB SRAM, 8KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L151RE + bool "STM32L151RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152RE + bool "STM32L152RE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151VE + bool "STM32L151VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152VE + bool "STM32L152VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151QE + bool "STM32L151QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152QE + bool "STM32L152QE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L151ZE + bool "STM32L151ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L152ZE + bool "STM32L152ZE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + +config ARCH_CHIP_STM32L162ZD + bool "STM32L162ZD" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 144-pin EnergyLite, 384KB FLASH, 48KB SRAM, 12KB EEPROM with + 4x44/8x40 LCD interface + +config ARCH_CHIP_STM32L162VE + bool "STM32L162VE" + select STM32_STM32L15XX + select STM32L1_HIGHDENSITY + select STM32_HAVE_AES + ---help--- + STM32L 100-pin EnergyLite, 512KB FLASH, 80KB SRAM, 16KB EEPROM with + 4x44/8x40 LCD interface + +endchoice + +endif + +config STM32_STM32L15XX + bool + default n + select STM32_HAVE_DMA1 + select STM32_HAVE_COMP + select STM32_HAVE_DMA2 + select ARCH_CORTEXM3 + select STM32_ENERGYLITE + select STM32_HAVE_I2C1 + select STM32_HAVE_LCD + select STM32_HAVE_SPI1 + select STM32_HAVE_SYSCFG + select STM32_HAVE_USART1 + select STM32_HAVE_USART2 + select STM32_HAVE_USBDEV + select STM32_HAVE_DAC1 + select STM32_HAVE_I2C2 + select STM32_HAVE_SPI2 + select STM32_HAVE_SPI3 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM3 + select STM32_HAVE_TIM4 + select STM32_HAVE_TIM9 + select STM32_HAVE_TIM10 + select STM32_HAVE_TIM11 + select STM32_HAVE_ADC2 + select STM32_HAVE_USART3 + select STM32_HAVE_RTC_SUBSECONDS if !STM32L1_LOWDENSITY + select STM32_HAVE_RTC_MAGIC + select STM32_HAVE_RTC + select STM32_HAVE_CRC + select STM32_HAVE_PWR + select STM32_HAVE_IP_AES_M3M4_V1 if STM32_HAVE_AES + select STM32_HAVE_IP_BBSRAM_M3M4_V1 + select STM32_HAVE_IP_BKP_M3M4_V1 + select STM32_HAVE_IP_CAN_BXCAN_M3M4_V1 + select STM32_HAVE_IP_CCM_M3M4_V1 if STM32_HAVE_CCM + select STM32_HAVE_IP_CRYPTO_M3M4_V1 + select STM32_HAVE_IP_DBGMCU_M3M4_V2 + select STM32_HAVE_IP_ADC_M3M4_V1 + select STM32_HAVE_COMMON_FOC + select STM32_HAVE_IP_DCMI_V1 + select STM32_HAVE_IP_DAC_M3M4_V1 + select STM32_HAVE_IP_DFUMODE_M3M4_V1 + select STM32_HAVE_IP_DMA_V1 + select STM32_HAVE_IP_DMA_V1_8CH + select STM32_HAVE_IP_EXTI_V1 + select STM32_HAVE_IP_ETHMAC_M3M4_V1 if STM32_HAVE_ETHMAC + select STM32_HAVE_IP_FLASH_M3M4_V1 + select STM32_HAVE_IP_FLASH_M3M4_L1 + select STM32_HAVE_IP_FMC_M3M4_V1 if STM32_HAVE_FMC + select STM32_HAVE_IP_FREERUN_M3M4_V1 + select STM32_HAVE_IP_FSMC_M3M4_V1 if STM32_HAVE_FSMC + select STM32_HAVE_IP_GPIO_M3M4_V1 + select STM32_HAVE_IP_HRTIM_M3M4_V1 if STM32_HAVE_HRTIM1 + select STM32_HAVE_IP_I2C_M3M4_V1 + select STM32_HAVE_IP_I2S_M3M4_V1 + select STM32_HAVE_IP_ONESHOT_M3M4_V1 + select STM32_HAVE_IP_PWR_M3M4_V1 + select STM32_HAVE_IP_RTC_M3M4_V1 + select STM32_HAVE_IP_RTCC_M3M4_L1 if !STM32_HAVE_RTC_COUNTER + select STM32_HAVE_IP_SDIO_M3M4_V1 + select STM32_HAVE_IP_SPI_V1 + select STM32_HAVE_IP_SYSCFG_M3M4_V1 + select STM32_HAVE_IP_TIMERS_M3M4_V1 + select STM32_HAVE_IP_UID_M3M4_V1 + select STM32_HAVE_IP_USART_V2 + select STM32_HAVE_IP_USBDEV_M3M4_V1 if STM32_HAVE_USBDEV + select STM32_HAVE_IP_USBFS_M3M4_V1 if STM32_HAVE_USBFS + select STM32_HAVE_IP_OTGFS_M3M4_V1 if STM32_HAVE_OTGFS + select STM32_HAVE_IP_WDG_M3M4_V1 + +config STM32L1_MEDIUMPLUSDENSITY + bool + default n + +config STM32L1_HIGHDENSITY + bool + default n + select STM32_HAVE_FSMC + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_MEDIUMDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_ADC3 + select STM32_HAVE_CAN1 + +config STM32L1_LOWDENSITY + bool + default n + select STM32_HAVE_USART3 + select STM32_HAVE_UART4 + select STM32_HAVE_UART5 + select STM32_HAVE_TIM1 + select STM32_HAVE_TIM2 + select STM32_HAVE_TIM5 + select STM32_HAVE_TIM6 + select STM32_HAVE_TIM7 + select STM32_HAVE_TIM8 + select STM32_HAVE_ADC2 + select STM32_HAVE_CAN1 diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32l1/Make.defs similarity index 64% rename from arch/arm/src/stm32/Make.defs rename to arch/arm/src/stm32l1/Make.defs index a7cf6decf4b..f0e835622db 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32l1/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/stm32/Make.defs +# arch/arm/src/stm32l1/Make.defs # # SPDX-License-Identifier: Apache-2.0 # @@ -22,27 +22,6 @@ include armv7-m/Make.defs -CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c -CHIP_CSRCS += stm32_lsi.c stm32_irq.c stm32_lowputc.c - -ifdef CONFIG_STM32_TICKLESS_TIMER -CHIP_CSRCS += stm32_tickless.c -else -CHIP_CSRCS += stm32_timerisr.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += stm32_userspace.c stm32_mpuinit.c -endif - -ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) -CHIP_CSRCS += stm32_idle.c -endif - -CHIP_CSRCS += stm32_pmstop.c stm32_pmstandby.c stm32_pmsleep.c - -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += stm32_pminitialize.c -endif +CHIP_CSRCS = stm32_rcc.c include common/stm32/Make.defs diff --git a/arch/arm/src/stm32/stm32_start.h b/arch/arm/src/stm32l1/chip.h similarity index 64% rename from arch/arm/src/stm32/stm32_start.h rename to arch/arm/src/stm32l1/chip.h index 4d0e326dc49..b0857c70503 100644 --- a/arch/arm/src/stm32/stm32_start.h +++ b/arch/arm/src/stm32l1/chip.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_start.h + * arch/arm/src/stm32l1/chip.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_START_H -#define __ARCH_ARM_SRC_STM32_STM32_START_H +#ifndef __ARCH_ARM_SRC_STM32L1_CHIP_H +#define __ARCH_ARM_SRC_STM32L1_CHIP_H /**************************************************************************** * Included Files @@ -29,21 +29,31 @@ #include -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ +/* Include the chip capabilities file */ + +#include + +/* Include the chip interrupt definition file */ + +#include + +/* Include the chip memory map */ + +#include "hardware/stm32_memorymap.h" + +/* Include the chip pinmap */ + +#include "hardware/stm32_pinmap.h" /**************************************************************************** - * Name: stm32_boardinitialize - * - * Description: - * All STM32 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after - * clocking and memory have been configured but before caches have been - * enabled and before any devices have been initialized. - * + * Pre-processor Definitions ****************************************************************************/ -void stm32_boardinitialize(void); +/* Provide the required number of peripheral interrupt vector + * definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes + * from the chip-specific * IRQ header file included by arch/stm32/irq.h. + */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_START_H */ +#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS + +#endif /* __ARCH_ARM_SRC_STM32L1_CHIP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h new file mode 100644 index 00000000000..bbe24f67a2c --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_memorymap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_memorymap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_memorymap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_MEMORYMAP_H */ diff --git a/arch/arm/src/stm32l1/hardware/stm32_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h new file mode 100644 index 00000000000..9bbf21f2281 --- /dev/null +++ b/arch/arm/src/stm32l1/hardware/stm32_pinmap.h @@ -0,0 +1,17 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/hardware/stm32_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H +#define __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/stm32l15xxx_pinmap.h" + +#endif /* __ARCH_ARM_SRC_STM32L1_HARDWARE_STM32_PINMAP_H */ diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_aes.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h index c68fbc44d66..101ad5e19c4 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_aes.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_aes.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_aes.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h index 49dd7919b22..903605e60af 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_gpio.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_gpio.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h index b1c2ba9ce83..4a59b4c86ca 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_memorymap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_memorymap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h index 9211c8c64be..75294a51a74 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_pinmap.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_pinmap.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h index 0217a9a79d9..c557971f1a3 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_rcc.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_rcc.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h similarity index 99% rename from arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h rename to arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h index 3e6dfa2ddbe..9cba220f8c2 100644 --- a/arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h +++ b/arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/hardware/stm32l15xxx_syscfg.h + * arch/arm/src/stm32l1/hardware/stm32l15xxx_syscfg.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32_lowputc.h b/arch/arm/src/stm32l1/stm32.h similarity index 54% rename from arch/arm/src/stm32/stm32_lowputc.h rename to arch/arm/src/stm32l1/stm32.h index 76629be9c54..2aed55b33ca 100644 --- a/arch/arm/src/stm32/stm32_lowputc.h +++ b/arch/arm/src/stm32l1/stm32.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32_lowputc.h + * arch/arm/src/stm32l1/stm32.h * * SPDX-License-Identifier: Apache-2.0 * @@ -20,47 +20,50 @@ * ****************************************************************************/ -#ifndef __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H -#define __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H +#ifndef __ARCH_ARM_SRC_STM32_STM32_H +#define __ARCH_ARM_SRC_STM32_STM32_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include +#include +#include + +#include "arm_internal.h" + +/* Peripherals **************************************************************/ #include "chip.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern +#include "stm32_adc.h" +#include "stm32_can.h" +#include "stm32_comp.h" +#include "stm32_dbgmcu.h" +#include "stm32_dma.h" +#include "stm32_dac_m3m4_v1.h" +#include "stm32_exti.h" +#include "stm32_flash.h" +#include "stm32_fmc_m3m4_v1.h" +#include "stm32_fsmc_m3m4_v1.h" +#include "stm32_gpio.h" +#include "stm32_i2c.h" +#include "stm32_ltdc_m3m4_v1.h" +#include "stm32_opamp_m3m4_v1.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_sdio_m3m4_v1.h" +#include "stm32_spi.h" +#include "stm32_i2s.h" +#include "stm32_tim.h" +#include "stm32_uart.h" +#if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) +# include "stm32_usbdev.h" #endif +#include "stm32_wdg.h" +#include "stm32_lowputc.h" +#include "stm32_eth_m3m4_v1.h" -/**************************************************************************** - * Name: stm32_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initialization of serial console. - * - ****************************************************************************/ - -void stm32_lowsetup(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_STM32_STM32_LOWPUTC_H */ +#endif /* __ARCH_ARM_SRC_STM32_STM32_H */ diff --git a/arch/arm/src/stm32l1/stm32_rcc.c b/arch/arm/src/stm32l1/stm32_rcc.c new file mode 100644 index 00000000000..044d6aea475 --- /dev/null +++ b/arch/arm/src/stm32l1/stm32_rcc.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/arm/src/stm32l1/stm32_rcc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" +#include "stm32_rtc.h" +#include "stm32_flash.h" +#include "stm32.h" +#include "stm32_waste.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1, + "Configure BOARD_LOOPSPERMSEC to non-default value."); + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Include chip-specific clocking initialization logic */ + +#include "stm32l15xxx_rcc.c" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32_STM32L15XX) +# define STM32_RCC_XXX STM32_RCC_CSR +# define RCC_XXX_YYYRST RCC_CSR_RTCRST +#else +# define STM32_RCC_XXX STM32_RCC_BDCR +# define RCC_XXX_YYYRST RCC_BDCR_BDRST +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_resetbkp + * + * Description: + * The RTC needs to reset the Backup Domain to change RTCSEL and resetting + * the Backup Domain renders to disabling the LSE as consequence. + * In order to avoid resetting the Backup Domain when we already + * configured LSE we will reset the Backup Domain early (here). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_RTC) && defined(CONFIG_STM32_PWR) && !defined(CONFIG_STM32_STM32F10XX) +static inline void rcc_resetbkp(void) +{ + uint32_t regval; + + /* Check if the RTC is already configured */ + + stm32_pwr_initbkp(false); + + regval = getreg32(RTC_MAGIC_REG); + if (regval != RTC_MAGIC && regval != RTC_MAGIC_TIME_SET) + { + stm32_pwr_enablebkp(true); + + /* We might be changing RTCSEL - to ensure such changes work, we must + * reset the backup domain (having backed up the RTC_MAGIC token) + */ + + modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST); + modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0); + + stm32_pwr_enablebkp(false); + } +} +#else +# define rcc_resetbkp() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_clockconfig + * + * Description: + * Called to establish the clock settings based on the values in board.h. + * This function (by default) will reset most everything, enable the PLL, + * and enable peripheral clocking for all peripherals enabled in the NuttX + * configuration file. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void stm32_clockconfig(void) +{ + /* Make sure that we are starting in the reset state */ + + rcc_reset(); + + /* Reset backup domain if appropriate */ + + rcc_resetbkp(); + +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif + + /* Enable peripheral clocking */ + + rcc_enableperipherals(); + +#ifdef CONFIG_STM32_SYSCFG_IOCOMPENSATION + /* Enable I/O Compensation */ + + stm32_iocompensation(); +#endif +} + +/**************************************************************************** + * Name: stm32_clockenable + * + * Description: + * Re-enable the clock and restore the clock settings based on settings + * in board.h. This function is only available to support low-power + * modes of operation: When re-awakening from deep-sleep modes, it is + * necessary to re-enable/re-start the PLL + * + * This functional performs a subset of the operations performed by + * stm32_clockconfig(): It does not reset any devices, and it does not + * reset the currently enabled peripheral clocks. + * + * If CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is defined, then clocking + * will be enabled by an externally provided, board-specific function + * called stm32_board_clockconfig(). + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_PM +void stm32_clockenable(void) +{ +#if defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) + + /* Invoke Board Custom Clock Configuration */ + + stm32_board_clockconfig(); + +#else + + /* Invoke standard, fixed clock configuration based on definitions + * in board.h + */ + + stm32_stdclockconfig(); + +#endif +} +#endif diff --git a/arch/arm/src/stm32/stm32l15xxx_alarm.h b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_alarm.h rename to arch/arm/src/stm32l1/stm32l15xxx_alarm.h index 52267bf83c0..1d5e789cec9 100644 --- a/arch/arm/src/stm32/stm32l15xxx_alarm.h +++ b/arch/arm/src/stm32l1/stm32l15xxx_alarm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_alarm.h + * arch/arm/src/stm32l1/stm32l15xxx_alarm.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/arch/arm/src/stm32/stm32l15xxx_rcc.c b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c similarity index 99% rename from arch/arm/src/stm32/stm32l15xxx_rcc.c rename to arch/arm/src/stm32l1/stm32l15xxx_rcc.c index 043e46beca3..f7f08c0f656 100644 --- a/arch/arm/src/stm32/stm32l15xxx_rcc.c +++ b/arch/arm/src/stm32l1/stm32l15xxx_rcc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/arm/src/stm32/stm32l15xxx_rcc.c + * arch/arm/src/stm32l1/stm32l15xxx_rcc.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/Kconfig b/boards/Kconfig index 354c57d92b0..e39d5b834c6 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -4487,52 +4487,52 @@ if ARCH_BOARD_PIC32CZCA70_CURIOSITY source "boards/arm/samv7/pic32czca70-curiosity/Kconfig" endif if ARCH_BOARD_B_G474E_DPOW1 -source "boards/arm/stm32/b-g474e-dpow1/Kconfig" +source "boards/arm/stm32g4/b-g474e-dpow1/Kconfig" endif if ARCH_BOARD_B_G431B_ESC1 -source "boards/arm/stm32/b-g431b-esc1/Kconfig" +source "boards/arm/stm32g4/b-g431b-esc1/Kconfig" endif if ARCH_BOARD_NUCLEO_G431KB -source "boards/arm/stm32/nucleo-g431kb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431kb/Kconfig" endif if ARCH_BOARD_NUCLEO_G431RB -source "boards/arm/stm32/nucleo-g431rb/Kconfig" +source "boards/arm/stm32g4/nucleo-g431rb/Kconfig" endif if ARCH_BOARD_B_L072Z_LRWAN1 -source "boards/arm/stm32f0l0g0/b-l072z-lrwan1/Kconfig" +source "boards/arm/stm32l0/b-l072z-lrwan1/Kconfig" endif if ARCH_BOARD_NUCLEO_F072RB -source "boards/arm/stm32f0l0g0/nucleo-f072rb/Kconfig" +source "boards/arm/stm32f0/nucleo-f072rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F091RC -source "boards/arm/stm32f0l0g0/nucleo-f091rc/Kconfig" +source "boards/arm/stm32f0/nucleo-f091rc/Kconfig" endif if ARCH_BOARD_NUCLEO_G070RB -source "boards/arm/stm32f0l0g0/nucleo-g070rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g070rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G071RB -source "boards/arm/stm32f0l0g0/nucleo-g071rb/Kconfig" +source "boards/arm/stm32g0/nucleo-g071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_G0B1RE -source "boards/arm/stm32f0l0g0/nucleo-g0b1re/Kconfig" +source "boards/arm/stm32g0/nucleo-g0b1re/Kconfig" endif if ARCH_BOARD_NUCLEO_L073RZ -source "boards/arm/stm32f0l0g0/nucleo-l073rz/Kconfig" +source "boards/arm/stm32l0/nucleo-l073rz/Kconfig" endif if ARCH_BOARD_STM32F051_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f051-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f051-discovery/Kconfig" endif if ARCH_BOARD_STM32L0538_DISCO -source "boards/arm/stm32f0l0g0/stm32l0538-disco/Kconfig" +source "boards/arm/stm32l0/stm32l0538-disco/Kconfig" endif if ARCH_BOARD_STM32F072_DISCOVERY -source "boards/arm/stm32f0l0g0/stm32f072-discovery/Kconfig" +source "boards/arm/stm32f0/stm32f072-discovery/Kconfig" endif if ARCH_BOARD_NUCLEO_C071RB -source "boards/arm/stm32f0l0g0/nucleo-c071rb/Kconfig" +source "boards/arm/stm32c0/nucleo-c071rb/Kconfig" endif if ARCH_BOARD_NUCLEO_C092RC -source "boards/arm/stm32f0l0g0/nucleo-c092rc/Kconfig" +source "boards/arm/stm32c0/nucleo-c092rc/Kconfig" endif if ARCH_BOARD_NUCLEO_F722ZE source "boards/arm/stm32f7/nucleo-f722ze/Kconfig" @@ -4652,151 +4652,151 @@ if ARCH_BOARD_NUCLEO_WB55RG source "boards/arm/stm32wb/nucleo-wb55rg/Kconfig" endif if ARCH_BOARD_AXOLOTI -source "boards/arm/stm32/axoloti/Kconfig" +source "boards/arm/stm32f4/axoloti/Kconfig" endif if ARCH_BOARD_CLICKER2_STM32 -source "boards/arm/stm32/clicker2-stm32/Kconfig" +source "boards/arm/stm32f4/clicker2-stm32/Kconfig" endif if ARCH_BOARD_CLOUDCTRL -source "boards/arm/stm32/cloudctrl/Kconfig" +source "boards/arm/stm32f1/cloudctrl/Kconfig" endif if ARCH_BOARD_EMW3162 -source "boards/arm/stm32/emw3162/Kconfig" +source "boards/arm/stm32f2/emw3162/Kconfig" endif if ARCH_BOARD_FIRE_STM32 -source "boards/arm/stm32/fire-stm32v2/Kconfig" +source "boards/arm/stm32f1/fire-stm32v2/Kconfig" endif if ARCH_BOARD_HYMINI_STM32V -source "boards/arm/stm32/hymini-stm32v/Kconfig" +source "boards/arm/stm32f1/hymini-stm32v/Kconfig" endif if ARCH_BOARD_MAPLE -source "boards/arm/stm32/maple/Kconfig" +source "boards/arm/stm32f1/maple/Kconfig" endif if ARCH_BOARD_ET_STM32_STAMP -source "boards/arm/stm32/et-stm32-stamp/Kconfig" +source "boards/arm/stm32f1/et-stm32-stamp/Kconfig" endif if ARCH_BOARD_MIKROE_STM32F4 -source "boards/arm/stm32/mikroe-stm32f4/Kconfig" +source "boards/arm/stm32f4/mikroe-stm32f4/Kconfig" endif if ARCH_BOARD_NUCLEO_F103RB -source "boards/arm/stm32/nucleo-f103rb/Kconfig" +source "boards/arm/stm32f1/nucleo-f103rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F207ZG -source "boards/arm/stm32/nucleo-f207zg/Kconfig" +source "boards/arm/stm32f2/nucleo-f207zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F302R8 -source "boards/arm/stm32/nucleo-f302r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f302r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F303RE -source "boards/arm/stm32/nucleo-f303re/Kconfig" +source "boards/arm/stm32f3/nucleo-f303re/Kconfig" endif if ARCH_BOARD_NUCLEO_F303ZE -source "boards/arm/stm32/nucleo-f303ze/Kconfig" +source "boards/arm/stm32f3/nucleo-f303ze/Kconfig" endif if ARCH_BOARD_NUCLEO_F334R8 -source "boards/arm/stm32/nucleo-f334r8/Kconfig" +source "boards/arm/stm32f3/nucleo-f334r8/Kconfig" endif if ARCH_BOARD_NUCLEO_F410RB -source "boards/arm/stm32/nucleo-f410rb/Kconfig" +source "boards/arm/stm32f4/nucleo-f410rb/Kconfig" endif if ARCH_BOARD_NUCLEO_F412ZG -source "boards/arm/stm32/nucleo-f412zg/Kconfig" +source "boards/arm/stm32f4/nucleo-f412zg/Kconfig" endif if ARCH_BOARD_NUCLEO_F446RE -source "boards/arm/stm32/nucleo-f446re/Kconfig" +source "boards/arm/stm32f4/nucleo-f446re/Kconfig" endif if ARCH_BOARD_NUCLEO_F401RE -source "boards/arm/stm32/nucleo-f401re/Kconfig" +source "boards/arm/stm32f4/nucleo-f401re/Kconfig" endif if ARCH_BOARD_NUCLEO_F411RE -source "boards/arm/stm32/nucleo-f411re/Kconfig" +source "boards/arm/stm32f4/nucleo-f411re/Kconfig" endif if ARCH_BOARD_STM32F401RC_RS485 -source "boards/arm/stm32/stm32f401rc-rs485/Kconfig" +source "boards/arm/stm32f4/stm32f401rc-rs485/Kconfig" endif if ARCH_BOARD_NUCLEO_F429ZI -source "boards/arm/stm32/nucleo-f429zi/Kconfig" +source "boards/arm/stm32f4/nucleo-f429zi/Kconfig" endif if ARCH_BOARD_NUCLEO_L152RE -source "boards/arm/stm32/nucleo-l152re/Kconfig" +source "boards/arm/stm32l1/nucleo-l152re/Kconfig" endif if ARCH_BOARD_ODRIVE36 -source "boards/arm/stm32/odrive36/Kconfig" +source "boards/arm/stm32f4/odrive36/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32E407 -source "boards/arm/stm32/olimex-stm32-e407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-e407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H405 -source "boards/arm/stm32/olimex-stm32-h405/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h405/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32H407 -source "boards/arm/stm32/olimex-stm32-h407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-h407/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P107 -source "boards/arm/stm32/olimex-stm32-p107/Kconfig" +source "boards/arm/stm32f1/olimex-stm32-p107/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P207 -source "boards/arm/stm32/olimex-stm32-p207/Kconfig" +source "boards/arm/stm32f2/olimex-stm32-p207/Kconfig" endif if ARCH_BOARD_OLIMEX_STM32P407 -source "boards/arm/stm32/olimex-stm32-p407/Kconfig" +source "boards/arm/stm32f4/olimex-stm32-p407/Kconfig" endif if ARCH_BOARD_OLIMEXINO_STM32 -source "boards/arm/stm32/olimexino-stm32/Kconfig" +source "boards/arm/stm32f1/olimexino-stm32/Kconfig" endif if ARCH_BOARD_OMNIBUSF4 -source "boards/arm/stm32/omnibusf4/Kconfig" +source "boards/arm/stm32f4/omnibusf4/Kconfig" endif if ARCH_BOARD_PHOTON -source "boards/arm/stm32/photon/Kconfig" +source "boards/arm/stm32f2/photon/Kconfig" endif if ARCH_BOARD_SHENZHOU -source "boards/arm/stm32/shenzhou/Kconfig" +source "boards/arm/stm32f1/shenzhou/Kconfig" endif if ARCH_BOARD_STM3210E_EVAL -source "boards/arm/stm32/stm3210e-eval/Kconfig" +source "boards/arm/stm32f1/stm3210e-eval/Kconfig" endif if ARCH_BOARD_STM3220G_EVAL -source "boards/arm/stm32/stm3220g-eval/Kconfig" +source "boards/arm/stm32f2/stm3220g-eval/Kconfig" endif if ARCH_BOARD_STM3240G_EVAL -source "boards/arm/stm32/stm3240g-eval/Kconfig" +source "boards/arm/stm32f4/stm3240g-eval/Kconfig" endif if ARCH_BOARD_STM32_TINY -source "boards/arm/stm32/stm32_tiny/Kconfig" +source "boards/arm/stm32f1/stm32_tiny/Kconfig" endif if ARCH_BOARD_STM32_BUTTERFLY2 -source "boards/arm/stm32/stm32butterfly2/Kconfig" +source "boards/arm/stm32f1/stm32butterfly2/Kconfig" endif if ARCH_BOARD_STM32F103_MINIMUM -source "boards/arm/stm32/stm32f103-minimum/Kconfig" +source "boards/arm/stm32f1/stm32f103-minimum/Kconfig" endif if ARCH_BOARD_STM32F411_MINIMUM -source "boards/arm/stm32/stm32f411-minimum/Kconfig" +source "boards/arm/stm32f4/stm32f411-minimum/Kconfig" endif if ARCH_BOARD_STM32F334_DISCO -source "boards/arm/stm32/stm32f334-disco/Kconfig" +source "boards/arm/stm32f3/stm32f334-disco/Kconfig" endif if ARCH_BOARD_STM32F3_DISCOVERY -source "boards/arm/stm32/stm32f3discovery/Kconfig" +source "boards/arm/stm32f3/stm32f3discovery/Kconfig" endif if ARCH_BOARD_STM32F411E_DISCO -source "boards/arm/stm32/stm32f411e-disco/Kconfig" +source "boards/arm/stm32f4/stm32f411e-disco/Kconfig" endif if ARCH_BOARD_STM32F429I_DISCO -source "boards/arm/stm32/stm32f429i-disco/Kconfig" +source "boards/arm/stm32f4/stm32f429i-disco/Kconfig" endif if ARCH_BOARD_STM32F4_DISCOVERY -source "boards/arm/stm32/stm32f4discovery/Kconfig" +source "boards/arm/stm32f4/stm32f4discovery/Kconfig" endif if ARCH_BOARD_STM32L_DISCOVERY -source "boards/arm/stm32/stm32ldiscovery/Kconfig" +source "boards/arm/stm32l1/stm32ldiscovery/Kconfig" endif if ARCH_BOARD_STM32VL_DISCOVERY -source "boards/arm/stm32/stm32vldiscovery/Kconfig" +source "boards/arm/stm32f1/stm32vldiscovery/Kconfig" endif if ARCH_BOARD_VIEWTOOL_STM32F107 -source "boards/arm/stm32/viewtool-stm32f107/Kconfig" +source "boards/arm/stm32f1/viewtool-stm32f107/Kconfig" endif if ARCH_BOARD_OLIMEX_STRP711 source "boards/arm/str71x/olimex-strp711/Kconfig" diff --git a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt deleted file mode 100644 index 3444cc83430..00000000000 --- a/boards/arm/stm32/nucleo-f103rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f103rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt deleted file mode 100644 index 9fe17612d17..00000000000 --- a/boards/arm/stm32/nucleo-f207zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f207zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs b/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs deleted file mode 100644 index a0ae3c3954b..00000000000 --- a/boards/arm/stm32/nucleo-f207zg/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f207zg/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt deleted file mode 100644 index 62e41b7cca4..00000000000 --- a/boards/arm/stm32/nucleo-f302r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f302r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs deleted file mode 100644 index d863be25bf5..00000000000 --- a/boards/arm/stm32/nucleo-f302r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f302r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt b/boards/arm/stm32/nucleo-f303re/CMakeLists.txt deleted file mode 100644 index fb2ec37234e..00000000000 --- a/boards/arm/stm32/nucleo-f303re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt b/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt deleted file mode 100644 index 0892584b294..00000000000 --- a/boards/arm/stm32/nucleo-f303ze/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f303ze/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt b/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt deleted file mode 100644 index ef3be834441..00000000000 --- a/boards/arm/stm32/nucleo-f334r8/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f334r8/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs b/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs deleted file mode 100644 index 24b7d458136..00000000000 --- a/boards/arm/stm32/nucleo-f334r8/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-f334r8/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt b/boards/arm/stm32/nucleo-f401re/CMakeLists.txt deleted file mode 100644 index fc3725e660d..00000000000 --- a/boards/arm/stm32/nucleo-f401re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f401re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt b/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt deleted file mode 100644 index 9c873cd8765..00000000000 --- a/boards/arm/stm32/nucleo-f410rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f410rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt b/boards/arm/stm32/nucleo-f411re/CMakeLists.txt deleted file mode 100644 index 53fe0025e44..00000000000 --- a/boards/arm/stm32/nucleo-f411re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f411re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt b/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt deleted file mode 100644 index df7b29ff230..00000000000 --- a/boards/arm/stm32/nucleo-f412zg/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f412zg/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt b/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt deleted file mode 100644 index 5d868f0710b..00000000000 --- a/boards/arm/stm32/nucleo-f429zi/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f429zi/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt b/boards/arm/stm32/nucleo-f446re/CMakeLists.txt deleted file mode 100644 index 5b0efd703eb..00000000000 --- a/boards/arm/stm32/nucleo-f446re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-f446re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt deleted file mode 100644 index ce86b7005c1..00000000000 --- a/boards/arm/stm32/nucleo-g431kb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431kb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt b/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt deleted file mode 100644 index c8eda596831..00000000000 --- a/boards/arm/stm32/nucleo-g431rb/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g431rb/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt b/boards/arm/stm32/nucleo-g474re/CMakeLists.txt deleted file mode 100644 index 7fcedbbbecb..00000000000 --- a/boards/arm/stm32/nucleo-g474re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-g474re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs b/boards/arm/stm32/nucleo-g474re/scripts/Make.defs deleted file mode 100644 index 977ae0d4707..00000000000 --- a/boards/arm/stm32/nucleo-g474re/scripts/Make.defs +++ /dev/null @@ -1,51 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-g474re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -ifeq ($(CONFIG_STM32_DFU),y) - LDSCRIPT = ld.script.dfu -else - LDSCRIPT = ld.script -endif - -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 - -# Embed absolute path to source file in debug information so that Eclipse -# source level debugging won't get confused. See: -# https://stackoverflow.com/questions/1275476/gcc-gdb-how-to-embed-absolute-path-to-source-file-in-debug-information -CFLAGS += -fdebug-prefix-map=..=$(readlink -f ..) diff --git a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt b/boards/arm/stm32/nucleo-l152re/CMakeLists.txt deleted file mode 100644 index 5a90572fa08..00000000000 --- a/boards/arm/stm32/nucleo-l152re/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/nucleo-l152re/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs b/boards/arm/stm32/nucleo-l152re/scripts/Make.defs deleted file mode 100644 index 2eb2354673a..00000000000 --- a/boards/arm/stm32/nucleo-l152re/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/nucleo-l152re/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt deleted file mode 100644 index 33d4a705181..00000000000 --- a/boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-e407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt deleted file mode 100644 index 58cb6b36828..00000000000 --- a/boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h405/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt deleted file mode 100644 index 37624d8016f..00000000000 --- a/boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-h407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs b/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs deleted file mode 100644 index 6dae53fb984..00000000000 --- a/boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/olimex-stm32-h407/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt deleted file mode 100644 index 714fc64c28c..00000000000 --- a/boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt deleted file mode 100644 index e80a16fed32..00000000000 --- a/boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p207/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt b/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt deleted file mode 100644 index 9932d6545d5..00000000000 --- a/boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimex-stm32-p407/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt b/boards/arm/stm32/olimexino-stm32/CMakeLists.txt deleted file mode 100644 index bf93e02b885..00000000000 --- a/boards/arm/stm32/olimexino-stm32/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/olimexino-stm32/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/omnibusf4/CMakeLists.txt b/boards/arm/stm32/omnibusf4/CMakeLists.txt deleted file mode 100644 index bf326c7306a..00000000000 --- a/boards/arm/stm32/omnibusf4/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/omnibusf4/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/shenzhou/CMakeLists.txt b/boards/arm/stm32/shenzhou/CMakeLists.txt deleted file mode 100644 index afc3a611633..00000000000 --- a/boards/arm/stm32/shenzhou/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/shenzhou/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt b/boards/arm/stm32/stm3210e-eval/CMakeLists.txt deleted file mode 100644 index 7bbea8e4a97..00000000000 --- a/boards/arm/stm32/stm3210e-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3210e-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt b/boards/arm/stm32/stm3220g-eval/CMakeLists.txt deleted file mode 100644 index 70278d3238c..00000000000 --- a/boards/arm/stm32/stm3220g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3220g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs b/boards/arm/stm32/stm3220g-eval/scripts/Make.defs deleted file mode 100644 index f0aa8af0b8e..00000000000 --- a/boards/arm/stm32/stm3220g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3220g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt b/boards/arm/stm32/stm3240g-eval/CMakeLists.txt deleted file mode 100644 index 823f2be9fe8..00000000000 --- a/boards/arm/stm32/stm3240g-eval/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm3240g-eval/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs b/boards/arm/stm32/stm3240g-eval/scripts/Make.defs deleted file mode 100644 index 091ebb2629a..00000000000 --- a/boards/arm/stm32/stm3240g-eval/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm3240g-eval/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32_tiny/CMakeLists.txt b/boards/arm/stm32/stm32_tiny/CMakeLists.txt deleted file mode 100644 index 6b35bfde309..00000000000 --- a/boards/arm/stm32/stm32_tiny/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32_tiny/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt b/boards/arm/stm32/stm32butterfly2/CMakeLists.txt deleted file mode 100644 index 9daf994ef14..00000000000 --- a/boards/arm/stm32/stm32butterfly2/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32butterfly2/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt deleted file mode 100644 index d4b2e558d30..00000000000 --- a/boards/arm/stm32/stm32f103-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f103-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt b/boards/arm/stm32/stm32f334-disco/CMakeLists.txt deleted file mode 100644 index 1d87be10fd0..00000000000 --- a/boards/arm/stm32/stm32f334-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f334-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs b/boards/arm/stm32/stm32f334-disco/scripts/Make.defs deleted file mode 100644 index 3312eb47258..00000000000 --- a/boards/arm/stm32/stm32f334-disco/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f334-disco/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt b/boards/arm/stm32/stm32f3discovery/CMakeLists.txt deleted file mode 100644 index b5910c678d9..00000000000 --- a/boards/arm/stm32/stm32f3discovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f3discovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs b/boards/arm/stm32/stm32f3discovery/scripts/Make.defs deleted file mode 100644 index f4a90c1997c..00000000000 --- a/boards/arm/stm32/stm32f3discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f3discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt deleted file mode 100644 index 0c3a3b0299f..00000000000 --- a/boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f401rc-rs485/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt deleted file mode 100644 index cc4e5162529..00000000000 --- a/boards/arm/stm32/stm32f411-minimum/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411-minimum/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt b/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt deleted file mode 100644 index 884177caaef..00000000000 --- a/boards/arm/stm32/stm32f411e-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f411e-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt deleted file mode 100644 index 7e51cbd70df..00000000000 --- a/boards/arm/stm32/stm32f429i-disco/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32f429i-disco/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld b/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld deleted file mode 100644 index db9d9db676a..00000000000 --- a/boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f429i-disco/scripts/kernel-space.ld - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* NOTE: This depends on the memory.ld script having been included prior to - * this script. - */ - -OUTPUT_ARCH(arm) -EXTERN(_vectors) -ENTRY(_stext) -SECTIONS -{ - .text : { - _stext = ABSOLUTE(.); - *(.vectors) - *(.text .text.*) - *(.fixup) - *(.gnu.warning) - *(.rodata .rodata.*) - *(.gnu.linkonce.t.*) - *(.glue_7) - *(.glue_7t) - *(.got) - *(.gcc_except_table) - *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); - } > kflash - - .init_section : { - _sinit = ABSOLUTE(.); - KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) - KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors)) - _einit = ABSOLUTE(.); - } > kflash - - .ARM.extab : { - *(.ARM.extab*) - } > kflash - - __exidx_start = ABSOLUTE(.); - .ARM.exidx : { - *(.ARM.exidx*) - } > kflash - - __exidx_end = ABSOLUTE(.); - - _eronly = ABSOLUTE(.); - - .data : { - _sdata = ABSOLUTE(.); - *(.data .data.*) - *(.gnu.linkonce.d.*) - CONSTRUCTORS - . = ALIGN(4); - _edata = ABSOLUTE(.); - } > ksram AT > kflash - - .bss : { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs b/boards/arm/stm32/stm32f4discovery/scripts/Make.defs deleted file mode 100644 index 109235fb9cd..00000000000 --- a/boards/arm/stm32/stm32f4discovery/scripts/Make.defs +++ /dev/null @@ -1,41 +0,0 @@ -############################################################################ -# boards/arm/stm32/stm32f4discovery/scripts/Make.defs -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs - -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) - -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt deleted file mode 100644 index bde3559ad0c..00000000000 --- a/boards/arm/stm32/stm32ldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32ldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt b/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt deleted file mode 100644 index 0b290a9db73..00000000000 --- a/boards/arm/stm32/stm32vldiscovery/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/stm32vldiscovery/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt b/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt deleted file mode 100644 index 4fc77f37f5d..00000000000 --- a/boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# ############################################################################## -# boards/arm/stm32/viewtool-stm32f107/CMakeLists.txt -# -# SPDX-License-Identifier: Apache-2.0 -# -# Licensed to the Apache Software Foundation (ASF) under one or more contributor -# license agreements. See the NOTICE file distributed with this work for -# additional information regarding copyright ownership. The ASF licenses this -# file to you under the Apache License, Version 2.0 (the "License"); you may not -# use this file except in compliance with the License. You may obtain a copy of -# the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations under -# the License. -# -# ############################################################################## - -add_subdirectory(src) diff --git a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt b/boards/arm/stm32l1/common/CMakeLists.txt similarity index 86% rename from boards/arm/stm32/et-stm32-stamp/CMakeLists.txt rename to boards/arm/stm32l1/common/CMakeLists.txt index d1c3d364013..901c509ec76 100644 --- a/boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +++ b/boards/arm/stm32l1/common/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/et-stm32-stamp/CMakeLists.txt +# boards/arm/stm32l1/common/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # @@ -20,4 +20,6 @@ # # ############################################################################## -add_subdirectory(src) +if(CONFIG_ARCH_BOARD_COMMON) + add_subdirectory(${NUTTX_DIR}/boards/arm/common/stm32 stm32_common) +endif() diff --git a/boards/arm/stm32l1/common/Kconfig b/boards/arm/stm32l1/common/Kconfig new file mode 100644 index 00000000000..5c48f62a025 --- /dev/null +++ b/boards/arm/stm32l1/common/Kconfig @@ -0,0 +1,6 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +source "boards/arm/common/stm32/Kconfig" diff --git a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs b/boards/arm/stm32l1/common/Makefile similarity index 51% rename from boards/arm/stm32/nucleo-f303re/scripts/Make.defs rename to boards/arm/stm32l1/common/Makefile index eb1b16a4ac2..8b3122d2c70 100644 --- a/boards/arm/stm32/nucleo-f303re/scripts/Make.defs +++ b/boards/arm/stm32l1/common/Makefile @@ -1,5 +1,5 @@ -############################################################################ -# boards/arm/stm32/nucleo-f303re/scripts/Make.defs +############################################################################# +# boards/arm/stm32l1/common/Makefile # # SPDX-License-Identifier: Apache-2.0 # @@ -18,24 +18,21 @@ # License for the specific language governing permissions and limitations # under the License. # -############################################################################ +############################################################################# -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs +include $(TOPDIR)/Make.defs -LDSCRIPT = ld.script -ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) +STM32_BOARD_COMMON_DIR := $(TOPDIR)$(DELIM)boards$(DELIM)arm$(DELIM)common$(DELIM)stm32 +STM32_COMMON_SRCDIR := $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)common$(DELIM)stm32 -ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +include board/Make.defs +include $(STM32_BOARD_COMMON_DIR)$(DELIM)src$(DELIM)Make.defs -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ +DEPPATH += --dep-path board -NXFLATLDFLAGS1 = -r -d -warn-common -NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections -LDNXFLATFLAGS = -e main -s 2048 +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}$(STM32_COMMON_SRCDIR) diff --git a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/hymini-stm32v/CMakeLists.txt rename to boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt index 7cc2354980b..199de2f567a 100644 --- a/boards/arm/stm32/hymini-stm32v/CMakeLists.txt +++ b/boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/hymini-stm32v/CMakeLists.txt +# boards/arm/stm32l1/nucleo-l152re/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/Kconfig b/boards/arm/stm32l1/nucleo-l152re/Kconfig similarity index 100% rename from boards/arm/stm32/nucleo-l152re/Kconfig rename to boards/arm/stm32l1/nucleo-l152re/Kconfig diff --git a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig rename to boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig index bbbb2ac2407..73ee4c8eb4e 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/lcd/defconfig +++ b/boards/arm/stm32l1/nucleo-l152re/configs/lcd/defconfig @@ -10,7 +10,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig rename to boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig index 19e97ac9e09..3b73a53c8df 100644 --- a/boards/arm/stm32/nucleo-l152re/configs/nsh/defconfig +++ b/boards/arm/stm32l1/nucleo-l152re/configs/nsh/defconfig @@ -9,7 +9,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="nucleo-l152re" CONFIG_ARCH_BOARD_NUCLEO_L152RE=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RE=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/nucleo-l152re/include/board.h b/boards/arm/stm32l1/nucleo-l152re/include/board.h similarity index 99% rename from boards/arm/stm32/nucleo-l152re/include/board.h rename to boards/arm/stm32l1/nucleo-l152re/include/board.h index 1c9ff4c06a5..a8e89cabee0 100644 --- a/boards/arm/stm32/nucleo-l152re/include/board.h +++ b/boards/arm/stm32l1/nucleo-l152re/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/include/board.h + * boards/arm/stm32l1/nucleo-l152re/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/nucleo-f303ze/scripts/Make.defs rename to boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs index fba0285e373..656e9afe070 100644 --- a/boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-f303ze/scripts/Make.defs +# boards/arm/stm32l1/nucleo-l152re/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/scripts/ld.script b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script similarity index 98% rename from boards/arm/stm32/nucleo-l152re/scripts/ld.script rename to boards/arm/stm32l1/nucleo-l152re/scripts/ld.script index 51325adba93..747f91401b8 100644 --- a/boards/arm/stm32/nucleo-l152re/scripts/ld.script +++ b/boards/arm/stm32l1/nucleo-l152re/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/scripts/ld.script + * boards/arm/stm32l1/nucleo-l152re/scripts/ld.script * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt rename to boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt index c8bbc27e2fe..9177895b7e4 100644 --- a/boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +++ b/boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/nucleo-l152re/src/CMakeLists.txt +# boards/arm/stm32l1/nucleo-l152re/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/src/Make.defs b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs similarity index 96% rename from boards/arm/stm32/nucleo-l152re/src/Make.defs rename to boards/arm/stm32l1/nucleo-l152re/src/Make.defs index 3eafd51d2e9..b1d374b5b3e 100644 --- a/boards/arm/stm32/nucleo-l152re/src/Make.defs +++ b/boards/arm/stm32l1/nucleo-l152re/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/nucleo-l152re/src/Make.defs +# boards/arm/stm32l1/nucleo-l152re/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h rename to boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h index dbdcb8cbf1a..7533f5860f9 100644 --- a/boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h +++ b/boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/nucleo-l152re.h + * boards/arm/stm32l1/nucleo-l152re/src/nucleo-l152re.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c similarity index 97% rename from boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c index 69c14c5f96f..dcab65cab6d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_autoleds.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_boot.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c index f9b3cd58433..3545cdbafa0 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_boot.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_boot.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c index 47366db118c..645eac093f8 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_buttons.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c index 7b8052671c0..a07de22023d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_ili93418b.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_ili93418b.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spi.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c index 5d59d781d63..66b5dae214d 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spi.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spi.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c similarity index 98% rename from boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c index c08c068b2fb..9683f10cc4c 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_spisd.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_spisd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c rename to boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c index 4ed85198d21..bb9d60e5a2c 100644 --- a/boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c +++ b/boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/nucleo-l152re/src/stm32_userleds.c + * boards/arm/stm32l1/nucleo-l152re/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt similarity index 95% rename from boards/arm/stm32/fire-stm32v2/CMakeLists.txt rename to boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt index a7c4eb1ccad..86a0d6e5493 100644 --- a/boards/arm/stm32/fire-stm32v2/CMakeLists.txt +++ b/boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/fire-stm32v2/CMakeLists.txt +# boards/arm/stm32l1/stm32ldiscovery/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/Kconfig b/boards/arm/stm32l1/stm32ldiscovery/Kconfig similarity index 100% rename from boards/arm/stm32/stm32ldiscovery/Kconfig rename to boards/arm/stm32l1/stm32ldiscovery/Kconfig diff --git a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig rename to boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig index 9022ce804f8..c965f4dc993 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/chrono/defconfig +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/chrono/defconfig @@ -16,7 +16,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig rename to boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig index 0ed417736d6..e07f7bfeadc 100644 --- a/boards/arm/stm32/stm32ldiscovery/configs/nsh/defconfig +++ b/boards/arm/stm32l1/stm32ldiscovery/configs/nsh/defconfig @@ -14,7 +14,7 @@ CONFIG_ARCH="arm" CONFIG_ARCH_BOARD="stm32ldiscovery" CONFIG_ARCH_BOARD_STM32L_DISCOVERY=y -CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP="stm32l1" CONFIG_ARCH_CHIP_STM32=y CONFIG_ARCH_CHIP_STM32L152RB=y CONFIG_ARCH_CHIP_STM32L1=y diff --git a/boards/arm/stm32/stm32ldiscovery/include/board.h b/boards/arm/stm32l1/stm32ldiscovery/include/board.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/include/board.h rename to boards/arm/stm32l1/stm32ldiscovery/include/board.h index a36765cc66e..9e1c58d534c 100644 --- a/boards/arm/stm32/stm32ldiscovery/include/board.h +++ b/boards/arm/stm32l1/stm32ldiscovery/include/board.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/include/board.h + * boards/arm/stm32l1/stm32ldiscovery/include/board.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs similarity index 97% rename from boards/arm/stm32/stm32ldiscovery/scripts/Make.defs rename to boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs index d9b35b396fa..ac42a713715 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32ldiscovery/scripts/Make.defs +# boards/arm/stm32l1/stm32ldiscovery/scripts/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld index bb8c62933c6..184ed288509 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rb.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rb.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld rename to boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld index 81b7157ce80..d295e75c07a 100644 --- a/boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld +++ b/boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/scripts/stm32l152rc.ld + * boards/arm/stm32l1/stm32ldiscovery/scripts/stm32l152rc.ld * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt similarity index 96% rename from boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt rename to boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt index feae2b53ca1..a496f64f86b 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +++ b/boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/stm32ldiscovery/src/CMakeLists.txt +# boards/arm/stm32l1/stm32ldiscovery/src/CMakeLists.txt # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/src/Make.defs b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs similarity index 96% rename from boards/arm/stm32/stm32ldiscovery/src/Make.defs rename to boards/arm/stm32l1/stm32ldiscovery/src/Make.defs index 0a07db0a932..f483afc2b24 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/Make.defs +++ b/boards/arm/stm32l1/stm32ldiscovery/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/stm32ldiscovery/src/Make.defs +# boards/arm/stm32l1/stm32ldiscovery/src/Make.defs # # SPDX-License-Identifier: Apache-2.0 # diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c index e251d0f2ead..e62f9ed1484 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_autoleds.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_autoleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c index 701fdbd303c..751e937f799 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_boot.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_boot.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c index be3ff1616ed..ee512f314b3 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_bringup.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_bringup.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c index 15071e1fe40..3f0e1ffb331 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_buttons.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_buttons.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c index ff4119682da..379abcfa7bd 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_lcd.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_lcd.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c similarity index 98% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c index 3857da41ec4..d18d9278bdd 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_pwm.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_pwm.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c index 7263febe7ea..3066e34f1d6 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_spi.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_spi.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c similarity index 97% rename from boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c index 362209fa599..5c6555da521 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32_userleds.c + * boards/arm/stm32l1/stm32ldiscovery/src/stm32_userleds.c * * SPDX-License-Identifier: Apache-2.0 * diff --git a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h similarity index 99% rename from boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h rename to boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h index a3ef72b7265..7f1afcb12f9 100644 --- a/boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h +++ b/boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/arm/stm32/stm32ldiscovery/src/stm32ldiscovery.h + * boards/arm/stm32l1/stm32ldiscovery/src/stm32ldiscovery.h * * SPDX-License-Identifier: Apache-2.0 * diff --git a/tools/ci/testlist/arm-08.dat b/tools/ci/testlist/arm-08.dat index dda347b33d8..b6354c5200c 100644 --- a/tools/ci/testlist/arm-08.dat +++ b/tools/ci/testlist/arm-08.dat @@ -1,10 +1,25 @@ -/arm/stm32/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32c0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32h7/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l0/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l4/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32u5/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32wb/[a-m]*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/nucleo-f1*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f2/nucleo-f2*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f3/nucleo-f30*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-09.dat b/tools/ci/testlist/arm-09.dat index cd9c27d5fdb..82448d0a9ab 100644 --- a/tools/ci/testlist/arm-09.dat +++ b/tools/ci/testlist/arm-09.dat @@ -1,12 +1,18 @@ -/arm/stm32/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/nucleo-f33*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f4*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g0/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32g4/nucleo-g*,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l0/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l4/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l5/nucleo-l*,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/olimex-*,CONFIG_ARM_TOOLCHAIN_GNU_EABI # Boards build by CMake diff --git a/tools/ci/testlist/arm-10.dat b/tools/ci/testlist/arm-10.dat index 1e45e9365cd..30d56951ccd 100644 --- a/tools/ci/testlist/arm-10.dat +++ b/tools/ci/testlist/arm-10.dat @@ -1,15 +1,15 @@ -/arm/stm32/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/olimexino-stm32,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/omnibusf4,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/photon,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/shenzhou,CONFIG_ARM_TOOLCHAIN_CLANG -shenzhou:thttpd -/arm/stm32/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm3210e-eval,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f2/stm3220g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm3240g-eval,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm3240g-eval:knxwm diff --git a/tools/ci/testlist/arm-11.dat b/tools/ci/testlist/arm-11.dat index 6af3cdbfa51..2564b8be8e0 100644 --- a/tools/ci/testlist/arm-11.dat +++ b/tools/ci/testlist/arm-11.dat @@ -1,18 +1,18 @@ -/arm/stm32/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32_tiny,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32butterfly2,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f1/stm32f103-minimum,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f334-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f3/stm32f3discovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411-minimum,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f411e-disco,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/stm32f429i-disco,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake diff --git a/tools/ci/testlist/arm-12.dat b/tools/ci/testlist/arm-12.dat index caf77554375..e9e1aa7a42b 100644 --- a/tools/ci/testlist/arm-12.dat +++ b/tools/ci/testlist/arm-12.dat @@ -1,11 +1,11 @@ -/arm/stm32/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery,CONFIG_ARM_TOOLCHAIN_GNU_EABI -stm32f4discovery:winbuild -/arm/stm32/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32l1/stm32ldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/stm32vldiscovery,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f1/viewtool-stm32f107,CONFIG_ARM_TOOLCHAIN_CLANG # cURL error 60 SSL certificate expired -stm32f4discovery:cxxtest diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 70c05ee29db..6c442b5026a 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -3,7 +3,7 @@ # ARM -/arm/stm32/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/stm32f4discovery/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/msys2.dat b/tools/ci/testlist/msys2.dat index 542b59af419..1996dff9c3c 100644 --- a/tools/ci/testlist/msys2.dat +++ b/tools/ci/testlist/msys2.dat @@ -3,9 +3,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI # ARM64 diff --git a/tools/ci/testlist/windows.dat b/tools/ci/testlist/windows.dat index ec54d4f82bb..15d7c21b1ae 100644 --- a/tools/ci/testlist/windows.dat +++ b/tools/ci/testlist/windows.dat @@ -2,9 +2,9 @@ # ARM -/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI +/arm/stm32l1/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI -/arm/stm32/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f4/nucleo-f411re/configs/nsh,CONFIG_ARM_TOOLCHAIN_CLANG /arm/rp2040/raspberrypi-pico/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI From e8ac5be43e41b822b0f9a3fda0504dfec33c8482 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 09:51:49 +0200 Subject: [PATCH 161/268] boards: fix various stm32 boards errors fix various stm32 boards errors found by CI Signed-off-by: raiden00pl --- boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c | 2 ++ boards/arm/stm32f2/emw3162/src/stm32_wlan.c | 2 +- boards/arm/stm32f2/photon/src/stm32_wlan.c | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c index b392a99ddf8..3150b338e92 100644 --- a/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c +++ b/boards/arm/stm32f1/stm32_tiny/src/stm32_boot.c @@ -106,6 +106,8 @@ void board_late_initialize(void) { int ret = OK; + UNUSED(ret); + #ifdef CONFIG_PWM /* Initialize PWM and register the PWM device. */ diff --git a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c index ff0e8ccaf1d..4396b94401a 100644 --- a/boards/arm/stm32f2/emw3162/src/stm32_wlan.c +++ b/boards/arm/stm32f2/emw3162/src/stm32_wlan.c @@ -142,7 +142,7 @@ bool bcmf_board_etheraddr(struct ether_addr *ethaddr) * Name: emw3162_wlan_initialize ****************************************************************************/ -int emw3162_wlan_initialize() +int emw3162_wlan_initialize(void) { int ret; diff --git a/boards/arm/stm32f2/photon/src/stm32_wlan.c b/boards/arm/stm32f2/photon/src/stm32_wlan.c index 88bfa4561e9..f1548ca8a85 100644 --- a/boards/arm/stm32f2/photon/src/stm32_wlan.c +++ b/boards/arm/stm32f2/photon/src/stm32_wlan.c @@ -123,7 +123,7 @@ bool bcmf_board_etheraddr(struct ether_addr *ethaddr) * Name: photon_wlan_initialize ****************************************************************************/ -int photon_wlan_initialize() +int photon_wlan_initialize(void) { int ret; From e5a9e5e1aae17eebab8c22e6ba4f0009fd50f5f4 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Mon, 1 Jun 2026 09:52:32 +0200 Subject: [PATCH 162/268] ci/arm-13.dat: update targets update arm-13.dat build targets so they match state before stm32 split Signed-off-by: raiden00pl --- tools/ci/testlist/arm-13.dat | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/tools/ci/testlist/arm-13.dat b/tools/ci/testlist/arm-13.dat index ed3b7bb9401..411f2ed1ea2 100644 --- a/tools/ci/testlist/arm-13.dat +++ b/tools/ci/testlist/arm-13.dat @@ -1,6 +1,7 @@ -/arm/stm32f*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32f7,CONFIG_ARM_TOOLCHAIN_CLANG -/arm/stm32h*,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h5,CONFIG_ARM_TOOLCHAIN_CLANG +/arm/stm32h7,CONFIG_ARM_TOOLCHAIN_CLANG # Boards build by CMake From 8b7639d5a3568867eef2e3151cb0c7eaeca5d7c8 Mon Sep 17 00:00:00 2001 From: raiden00pl Date: Tue, 26 May 2026 13:34:34 +0200 Subject: [PATCH 163/268] Documentation: add STM32 porting guide add STM32 porting guide Signed-off-by: raiden00pl --- Documentation/guides/index.rst | 1 + Documentation/guides/stm32_ports.rst | 957 +++++++++++++++++++++++++++ 2 files changed, 958 insertions(+) create mode 100644 Documentation/guides/stm32_ports.rst diff --git a/Documentation/guides/index.rst b/Documentation/guides/index.rst index f1e11bc9a45..acbb2a118b5 100644 --- a/Documentation/guides/index.rst +++ b/Documentation/guides/index.rst @@ -61,4 +61,5 @@ Guides optee.rst qemu_tips.rst lwl.rst + stm32_ports.rst diff --git a/Documentation/guides/stm32_ports.rst b/Documentation/guides/stm32_ports.rst new file mode 100644 index 00000000000..cafe2f317eb --- /dev/null +++ b/Documentation/guides/stm32_ports.rst @@ -0,0 +1,957 @@ +=========== +STM32 ports +=========== + +This page records the STM32 families supported by the NuttX ARM port and the +peripheral IP-core selections used by the common STM32 implementation. The +goal of this inventory is to keep shared STM32 code selected by peripheral IP +version, not by family name. + +Family status +============= + +============ ================ =========== =========================== +Family CPU core Status NuttX source directory +============ ================ =========== =========================== +STM32C0 Cortex-M0+ supported ``arch/arm/src/stm32c0`` +STM32C5 Cortex-M33 unsupported none +STM32F0 Cortex-M0 supported ``arch/arm/src/stm32f0`` +STM32F1 Cortex-M3 supported ``arch/arm/src/stm32f1`` +STM32F2 Cortex-M3 supported ``arch/arm/src/stm32f2`` +STM32F3 Cortex-M4 supported ``arch/arm/src/stm32f3`` +STM32F4 Cortex-M4 supported ``arch/arm/src/stm32f4`` +STM32F7 Cortex-M7 supported ``arch/arm/src/stm32f7`` +STM32G0 Cortex-M0+ supported ``arch/arm/src/stm32g0`` +STM32G4 Cortex-M4 supported ``arch/arm/src/stm32g4`` +STM32H5 Cortex-M33 supported ``arch/arm/src/stm32h5`` +STM32H7 Cortex-M7 supported ``arch/arm/src/stm32h7`` +STM32L0 Cortex-M0+ supported ``arch/arm/src/stm32l0`` +STM32L1 Cortex-M3 supported ``arch/arm/src/stm32l1`` +STM32L4 Cortex-M4 supported ``arch/arm/src/stm32l4`` +STM32L5 Cortex-M33 supported ``arch/arm/src/stm32l5`` +STM32MP1 Cortex-A7 unsupported none +STM32MP1 Cortex-M4 unsupported none +STM32MP2 Cortex-A35 unsupported none +STM32MP2 Cortex-M33 unsupported none +STM32N6 Cortex-M55 supported ``arch/arm/src/stm32n6`` +STM32U0 Cortex-M0+ unsupported none +STM32U3 Cortex-M33 unsupported none +STM32U5 Cortex-M33 supported ``arch/arm/src/stm32u5`` +STM32WB Cortex-M4 supported ``arch/arm/src/stm32wb`` +STM32WB Cortex-M0+ unsupported none +STM32WB0 Cortex-M0+ unsupported none +STM32WBA Cortex-M33 unsupported none +STM32WL3 Cortex-M0+ unsupported none +STM32WL5 Cortex-M4 supported ``arch/arm/src/stm32wl5`` +STM32WL5 Cortex-M0+ unsupported none +STM32WLE Cortex-M4 unsupported none +============ ================ =========== =========================== + + +Migration to NuttX 13.0 +======================= + +Release 13.0 normalizes every STM32 port onto a single, consistent Kconfig +namespace, public API and source tree. All of the changes below are breaking. +Each entry states what changed and the exact migration step; almost every +migration is a mechanical search-and-replace that can be scripted (``sed``, +IDE refactor, etc.). + +Apply the steps in this order so that each replacement stays unambiguous: + +#. Chip family selectors (``CONFIG_ARCH_CHIP_*``). +#. Kconfig options (``CONFIG_STM32xx_*`` to ``CONFIG_STM32_*``). +#. Hardware definition macros (``STM32xx_*`` to ``STM32_*``). +#. Public API names (``stm32xx_*`` to ``stm32_*``) and family includes. +#. Out-of-tree source / include / board paths. + +Chip family selectors split +--------------------------- + +PR `#19067 `__. + +The combined ``CONFIG_ARCH_CHIP_STM32`` selector was replaced by one concrete +selector per legacy sub-family. Update out-of-tree defconfigs:: + + CONFIG_ARCH_CHIP_STM32 -> one of: + CONFIG_ARCH_CHIP_STM32F1 + CONFIG_ARCH_CHIP_STM32F2 + CONFIG_ARCH_CHIP_STM32F3 + CONFIG_ARCH_CHIP_STM32F4 + CONFIG_ARCH_CHIP_STM32G4 + CONFIG_ARCH_CHIP_STM32L1 + +Kconfig options unified to ``CONFIG_STM32_*`` +--------------------------------------------- + +PR `#19136 `__. + +All family-prefixed Kconfig options were renamed to the common +``CONFIG_STM32_*`` namespace (common options now live in +``arch/arm/src/common/stm32``). Replace the family prefix with +``CONFIG_STM32_`` for every affected family:: + + CONFIG_STM32F0L0G0_ -> CONFIG_STM32_ + CONFIG_STM32F7_ -> CONFIG_STM32_ + CONFIG_STM32L4_ -> CONFIG_STM32_ + CONFIG_STM32L5_ -> CONFIG_STM32_ + CONFIG_STM32U5_ -> CONFIG_STM32_ + CONFIG_STM32H5_ -> CONFIG_STM32_ + CONFIG_STM32H7_ -> CONFIG_STM32_ + CONFIG_STM32WB_ -> CONFIG_STM32_ + CONFIG_STM32WL5_ -> CONFIG_STM32_ + CONFIG_STM32N6_ -> CONFIG_STM32_ + +Board clock-config options are normalized too:: + + CONFIG_ARCH_BOARD_STM32F0L0G0_CUSTOM_CLOCKCONFIG -> CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG -> CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + CONFIG_ARCH_BOARD_STM32L4_CUSTOM_CLOCKCONFIG -> CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG + +QUADSPI was also renamed to QSPI on F7/H7 (the IP block is the same; +PR `#19069 `__). The QUADSPI +register/pin/DMA hardware macros are unchanged:: + + CONFIG_STM32F7_QUADSPI -> CONFIG_STM32_QSPI + CONFIG_STM32H7_QUADSPI -> CONFIG_STM32_QSPI + +Hardware definition macros unified to ``STM32_*`` +------------------------------------------------- + +PR `#19114 `__. + +Non-standard hardware definition macros (IRQ numbers, peripheral counts, SRAM +and related) were renamed to the common ``STM32_*`` prefix. Replace the family +prefix in out-of-tree code (do this *after* the Kconfig migration so a plain +prefix replace is safe):: + + STM32L4_ -> STM32_ + STM32L5_ -> STM32_ + STM32F7_ -> STM32_ + STM32H5_ -> STM32_ + STM32H7_ -> STM32_ + STM32U5_ -> STM32_ + STM32WB_ -> STM32_ + STM32WL5_ -> STM32_ + STM32N6_ -> STM32_ + +Public API names unified to ``stm32_*`` +--------------------------------------- + +PR `#19125 `__. + +Public STM32 interfaces (functions and API-facing types, including the +timer / lptimer / dma / freerun APIs) were renamed from ``stm32_*`` to +canonical ``stm32_*`` for F7, H5, H7, L4, L5, WB and WL5. The per-family root +header ``stm32.h`` was renamed to ``stm32.h``. Migrate out-of-tree +code (the same rule applies to ``stm32f7_``, ``stm32h5_``, ``stm32h7_``, +``stm32l5_``, ``stm32wb_`` and ``stm32wl5_``):: + + stm32l4_ -> stm32_ + #include "stm32l4.h" -> #include "stm32.h" + +Common sources moved to ``common/stm32`` +---------------------------------------- + +PR `#19143 `__. + +Shared STM32 code was relocated so that all families build from one tree. +Out-of-tree code that references family-local common source/include paths must +point at the new common locations:: + + arch source and private headers -> arch/arm/src/common/stm32 + board common sources -> boards/arm/common/stm32 + +Per-family directory split +-------------------------- + +PR `#19143 `__. + +The two combined super-directories were split into one directory per chip +family. Out-of-tree boards, include paths, source paths and defconfigs must +move to the matching family directory:: + + arch/arm/src/stm32f0l0g0 -> stm32f0, stm32l0, stm32g0, stm32c0 + boards/arm/stm32f0l0g0 -> boards/arm/stm32{f0,l0,g0,c0} + arch/arm/src/stm32 -> stm32f1, stm32f2, stm32f3, stm32f4, stm32g4, stm32l1 + boards/arm/stm32 -> boards/arm/stm32{f1,f2,f3,f4,g4,l1} + +Family peripheral inventory +=========================== + +Each family table records every peripheral group currently tracked by this +inventory. ``unsupported`` means the peripheral is not available in that +family or is intentionally not implemented by the NuttX family port. +``to be done`` means the peripheral exists or needs confirmation, but the +exact IP core version has not been documented yet. + +STM32C0 +------- + +============ ============ ================================================= +Peripheral Core version Driver +============ ============ ================================================= +ADC v1 arch/arm/src/common/stm32/stm32_adc_m0_v1.c +AES/CRYP v1 not supported +CAN/FDCAN FDCAN arch/arm/src/common/stm32/stm32_fdcan_m0_v1.c +CRC to be done not supported +DAC v1 not supported +DBGMCU v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +DMAMUX v1 7ch arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +EXTI v2 arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c +FLASH G0/C0 arch/arm/src/common/stm32/stm32_flash_m0_g0c0.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c +PWR G0 arch/arm/src/common/stm32/stm32_pwr_m0_g0.c +RCC to be done arch/arm/src/stm32c0/stm32_rcc.c +RTC RTCC M0 not supported +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c +SYSCFG to be done not supported +TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c +USB device not supported +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c +============ ============ ================================================= + +STM32F0 +------- + +============ ============ ================================================= +Peripheral Core version Driver +============ ============ ================================================= +ADC v1 arch/arm/src/common/stm32/stm32_adc_m0_v1.c +CAN/FDCAN bxCAN not supported +CRC to be done not supported +DAC v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c +FLASH M0 v1 not supported +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c +HDMI-CEC to be done not supported +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c +PWR v1 arch/arm/src/common/stm32/stm32_pwr_m0_v1.c +RCC to be done arch/arm/src/stm32f0/stm32_rcc.c +RTC RTCC M0 not supported +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c +SYSCFG to be done not supported +TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c +USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c +============ ============ ================================================= + +STM32F1 +------- + +============ ============= ======================================================= +Peripheral Core version Driver +============ ============= ======================================================= +ADC v1 basic arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +CAN/FDCAN bxCAN arch/arm/src/common/stm32/stm32_can_m3m4_v1.c +CRC to be done not supported +DAC v1 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DBGMCU v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c +ETH to be done arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH F1/F3 arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c +FSMC v1 arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +PWR v1 arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c +RCC to be done arch/arm/src/stm32f1/stm32_rcc.c +RTC counter arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c +SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +SPI/I2S v1 arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v1 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB device/OTG FS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============= ======================================================= + +STM32F2 +------- + +============ ============ ======================================================= +Peripheral Core version Driver +============ ============ ======================================================= +ADC v1 arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +CAN/FDCAN bxCAN arch/arm/src/common/stm32/stm32_can_m3m4_v1.c +CRYP v1 arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c +DAC v1 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DMA v2 arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c +ETH to be done arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH F2/F4 arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c +FSMC v1 arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +HASH to be done not supported +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +RCC to be done arch/arm/src/stm32f2/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c +RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c +SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c +TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB OTG FS/HS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============ ======================================================= + +STM32F3 +------- + +============ ============== ======================================================= +Peripheral Core version Driver +============ ============== ======================================================= +ADC v1 basic or v2 arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +CAN/FDCAN bxCAN arch/arm/src/common/stm32/stm32_can_m3m4_v1.c +COMP v1 arch/arm/src/common/stm32/stm32_comp_m3m4_v1.c +DAC v1 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DBGMCU v2 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH F1/F3 arch/arm/src/common/stm32/stm32_flash_m3m4_f1f3.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +HRTIM v1 arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c +I2C v2 arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +OPAMP v1 arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c +RCC to be done arch/arm/src/stm32f3/stm32_rcc.c +RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c +SDADC v1 arch/arm/src/common/stm32/stm32_sdadc_m3m4_v1.c +SPI/I2S v3 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c +SYSCFG v1 not supported +TIM v1 or v2 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============== ======================================================= + +STM32F4 +------- + +============ ============ ====================================================== +Peripheral Core version Driver +============ ============ ====================================================== +ADC v1 arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +CAN/FDCAN bxCAN arch/arm/src/common/stm32/stm32_can_m3m4_v1.c +CRYP v1 arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c +DAC v1 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DMA v2 arch/arm/src/common/stm32/stm32_dma_m3m4_v2_stream.c +DMA2D v1 arch/arm/src/common/stm32/stm32_dma2d_m3m4_v1.c +ETH to be done arch/arm/src/common/stm32/stm32_eth_m3m4_v1.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH F2/F4 arch/arm/src/common/stm32/stm32_flash_m3m4_f2f4.c +FMC/FSMC v1 arch/arm/src/common/stm32/stm32_fmc_m3m4_v1.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +HASH to be done not supported +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +LTDC v1 arch/arm/src/common/stm32/stm32_ltdc_m3m4_v1.c +QUADSPI to be done not supported +RCC to be done arch/arm/src/stm32f4/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c +RTC RTCC F4 arch/arm/src/common/stm32/stm32_rtcc_m3m4_f4.c +SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c +TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB OTG FS/HS arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============ ====================================================== + +STM32G4 +------- + +============ ============ ======================================================= +Peripheral Core version Driver +============ ============ ======================================================= +ADC v2 arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +AES v1 arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c +CAN/FDCAN FDCAN arch/arm/src/common/stm32/stm32_can_m3m4_v1.c +COMP v2 arch/arm/src/common/stm32/stm32_comp_m3m4_v2.c +CORDIC v1 arch/arm/src/common/stm32/stm32_cordic_m3m4_v1.c +DAC v2 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DMA v1 arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c +DMAMUX v1 8ch arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c +EXTI v2 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH G4 arch/arm/src/common/stm32/stm32_flash_m3m4_g4.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +HRTIM v1 arch/arm/src/common/stm32/stm32_hrtim_m3m4_v1.c +I2C v2 arch/arm/src/common/stm32/stm32_i2c_m3m4_v2.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +OPAMP v1 arch/arm/src/common/stm32/stm32_opamp_m3m4_v1.c +RCC to be done arch/arm/src/stm32g4/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m3m4_v1.c +RTC RTCC v1 arch/arm/src/common/stm32/stm32_rtc_m3m4_v1_lowerhalf.c +SPI/I2S v3 arch/arm/src/common/stm32/stm32_spi_m3m4_v2v3v4.c +TIM v3 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============ ======================================================= + +STM32L4 +------- + +============ ============ ========================================= +Peripheral Core version Driver +============ ============ ========================================= +ADC to be done arch/arm/src/stm32l4/stm32l4_adc.c +CAN/FDCAN bxCAN arch/arm/src/stm32l4/stm32l4_can.c +COMP to be done arch/arm/src/stm32l4/stm32l4_comp.c +DAC to be done arch/arm/src/stm32l4/stm32l4_dac.c +DFSDM to be done arch/arm/src/stm32l4/stm32l4_dfsdm.c +DMA v1+DMAMUX arch/arm/src/stm32l4/stm32l4_dma.c +EXTI to be done arch/arm/src/stm32l4/stm32l4_exti_gpio.c +FLASH to be done arch/arm/src/stm32l4/stm32l4_flash.c +GPIO to be done arch/arm/src/stm32l4/stm32l4_gpio.c +I2C to be done arch/arm/src/stm32l4/stm32l4_i2c.c +IWDG v1 arch/arm/src/stm32l4/stm32l4_iwdg.c +LPTIM to be done arch/arm/src/stm32l4/stm32l4_lptim.c +PWR to be done arch/arm/src/stm32l4/stm32l4_pwr.c +QSPI to be done arch/arm/src/stm32l4/stm32l4_qspi.c +RCC to be done arch/arm/src/stm32l4/stm32l4_rcc.c +RNG to be done arch/arm/src/stm32l4/stm32l4_rng.c +RTC to be done arch/arm/src/stm32l4/stm32l4_rtc.c +SAI to be done arch/arm/src/stm32l4/stm32l4_sai.c +SDMMC to be done arch/arm/src/stm32l4/stm32l4_sdmmc.c +SPI/I2S to be done arch/arm/src/stm32l4/stm32l4_spi.c +TIM to be done arch/arm/src/stm32l4/stm32l4_tim.c +USART/LPUART v3 arch/arm/src/stm32l4/stm32l4_serial.c +USB OTG FS arch/arm/src/stm32l4/stm32l4_otgfsdev.c +PULSECOUNT n/a arch/arm/src/stm32l4/stm32l4_pulsecount.c +PWM n/a arch/arm/src/stm32l4/stm32l4_pwm.c +QENCODER n/a arch/arm/src/stm32l4/stm32l4_qencoder.c +USB host n/a arch/arm/src/stm32l4/stm32l4_otgfshost.c +============ ============ ========================================= + +STM32F7 +------- + +============ ============ ======================================= +Peripheral Core version Driver +============ ============ ======================================= +ADC to be done arch/arm/src/stm32f7/stm32_adc.c +CAN/FDCAN bxCAN arch/arm/src/stm32f7/stm32_can.c +DAC to be done not supported +DMA v2 style arch/arm/src/stm32f7/stm32_dma.c +DMA2D v1 arch/arm/src/stm32f7/stm32_dma2d.c +ETH to be done arch/arm/src/stm32f7/stm32_ethernet.c +EXTI to be done arch/arm/src/stm32f7/stm32_exti_gpio.c +FLASH to be done arch/arm/src/stm32f7/stm32_flash.c +FMC/FSMC to be done arch/arm/src/stm32f7/stm32_fmc.c +GPIO to be done arch/arm/src/stm32f7/stm32_gpio.c +I2C to be done arch/arm/src/stm32f7/stm32_i2c.c +IWDG v1 not supported +LTDC to be done arch/arm/src/stm32f7/stm32_ltdc.c +PWR to be done arch/arm/src/stm32f7/stm32_pwr.c +QUADSPI to be done arch/arm/src/stm32f7/stm32_qspi.c +RCC to be done arch/arm/src/stm32f7/stm32_rcc.c +RNG to be done arch/arm/src/stm32f7/stm32_rng.c +RTC to be done arch/arm/src/stm32f7/stm32_rtc.c +SDMMC to be done arch/arm/src/stm32f7/stm32_sdmmc.c +SPI/I2S to be done arch/arm/src/stm32f7/stm32_i2s.c +TIM to be done arch/arm/src/stm32f7/stm32_tim.c +USART/LPUART v3 arch/arm/src/stm32f7/stm32_serial.c +USB OTG FS/HS arch/arm/src/stm32f7/stm32_otgdev.c +WWDG v1 not supported +BBSRAM n/a arch/arm/src/stm32f7/stm32_bbsram.c +CAPTURE n/a arch/arm/src/stm32f7/stm32_capture.c +FOC n/a arch/arm/src/stm32f7/stm32_foc.c +PULSECOUNT n/a arch/arm/src/stm32f7/stm32_pulsecount.c +PWM n/a arch/arm/src/stm32f7/stm32_pwm.c +QENCODER n/a arch/arm/src/stm32f7/stm32_qencoder.c +SAI n/a arch/arm/src/stm32f7/stm32_sai.c +USB host n/a arch/arm/src/stm32f7/stm32_otghost.c +============ ============ ======================================= + +STM32G0 +------- + +============ ============ ================================================= +Peripheral Core version Driver +============ ============ ================================================= +ADC v1 arch/arm/src/common/stm32/stm32_adc_m0_v1.c +AES v1 arch/arm/src/common/stm32/stm32_aes_m0_v1.c +CAN/FDCAN FDCAN not supported +DAC v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +DMAMUX v1 7ch arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +EXTI v2 arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c +FLASH G0/C0 not supported +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c +PWR G0 not supported +RCC to be done arch/arm/src/stm32g0/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c +RTC RTCC M0 not supported +SPI/I2S v2 arch/arm/src/common/stm32/stm32_spi_m0_v1.c +SYSCFG to be done not supported +TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +USART/LPUART v4 arch/arm/src/common/stm32/stm32_serial_m0_v4.c +USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c +============ ============ ================================================= + +STM32H5 +------- + +============ ============ ======================================= +Peripheral Core version Driver +============ ============ ======================================= +ADC to be done arch/arm/src/stm32h5/stm32_adc.c +AES/CRYP to be done not supported +CAN/FDCAN FDCAN arch/arm/src/stm32h5/stm32_fdcan.c +DAC to be done not supported +DTS to be done arch/arm/src/stm32h5/stm32_dts.c +ETH to be done arch/arm/src/stm32h5/stm32_ethernet.c +EXTI to be done not supported +FLASH to be done arch/arm/src/stm32h5/stm32_flash.c +GPIO to be done arch/arm/src/stm32h5/stm32_gpio.c +GPDMA to be done arch/arm/src/stm32h5/stm32_dma.c +I2C to be done arch/arm/src/stm32h5/stm32_i2c.c +ICACHE to be done arch/arm/src/stm32h5/stm32_icache.c +OCTOSPI to be done arch/arm/src/stm32h5/stm32_qspi.c +PWR to be done arch/arm/src/stm32h5/stm32_pwr.c +RCC to be done arch/arm/src/stm32h5/stm32_rcc.c +SPI/I2S to be done arch/arm/src/stm32h5/stm32_spi.c +TIM to be done arch/arm/src/stm32h5/stm32_tim.c +USART/LPUART v3 arch/arm/src/stm32h5/stm32_serial.c +USB FS arch/arm/src/stm32h5/stm32_usbfs.c +PULSECOUNT n/a arch/arm/src/stm32h5/stm32_pulsecount.c +PWM n/a arch/arm/src/stm32h5/stm32_pwm.c +RNG n/a arch/arm/src/stm32h5/stm32_rng.c +USB host n/a arch/arm/src/stm32h5/stm32_usbdrdhost.c +============ ============ ======================================= + +STM32H7 +------- + +============ ============ ======================================= +Peripheral Core version Driver +============ ============ ======================================= +ADC to be done arch/arm/src/stm32h7/stm32_adc.c +BDMA to be done arch/arm/src/stm32h7/stm32_dma.c +CAN/FDCAN FDCAN arch/arm/src/stm32h7/stm32_fdcan_sock.c +DAC to be done not supported +DMA v2 style arch/arm/src/stm32h7/stm32_dma.c +DMA2D to be done not supported +ETH to be done arch/arm/src/stm32h7/stm32_ethernet.c +EXTI to be done arch/arm/src/stm32h7/stm32_exti_gpio.c +FLASH to be done arch/arm/src/stm32h7/stm32_flash.c +FMC/FSMC to be done arch/arm/src/stm32h7/stm32_fmc.c +GPIO to be done arch/arm/src/stm32h7/stm32_gpio.c +HSEM to be done not supported +I2C to be done arch/arm/src/stm32h7/stm32_i2c.c +IWDG v1 arch/arm/src/stm32h7/stm32_iwdg.c +LTDC to be done arch/arm/src/stm32h7/stm32_ltdc.c +MDMA to be done arch/arm/src/stm32h7/stm32_dma.c +PWR to be done arch/arm/src/stm32h7/stm32_pwr.c +QUADSPI to be done arch/arm/src/stm32h7/stm32_qspi.c +RCC to be done arch/arm/src/stm32h7/stm32_rcc.c +RNG to be done arch/arm/src/stm32h7/stm32_rng.c +RTC to be done arch/arm/src/stm32h7/stm32_rtc.c +SDMMC to be done arch/arm/src/stm32h7/stm32_sdmmc.c +SPI/I2S to be done arch/arm/src/stm32h7/stm32_spi.c +TIM to be done arch/arm/src/stm32h7/stm32_tim.c +USART/LPUART v4 arch/arm/src/stm32h7/stm32_serial.c +USB OTG FS/HS arch/arm/src/stm32h7/stm32_otgdev.c +WWDG v1 arch/arm/src/stm32h7/stm32_wwdg.c +AES/CRYP n/a arch/arm/src/stm32h7/stm32_aes.c +BBSRAM n/a arch/arm/src/stm32h7/stm32_bbsram.c +CAPTURE n/a arch/arm/src/stm32h7/stm32_capture.c +LPTIM n/a arch/arm/src/stm32h7/stm32_lptim.c +PULSECOUNT n/a arch/arm/src/stm32h7/stm32_pulsecount.c +PWM n/a arch/arm/src/stm32h7/stm32_pwm.c +QENCODER n/a arch/arm/src/stm32h7/stm32_qencoder.c +USB host n/a arch/arm/src/stm32h7/stm32_otghost.c +============ ============ ======================================= + +STM32L0 +------- + +============ ============ ================================================= +Peripheral Core version Driver +============ ============ ================================================= +ADC v1 arch/arm/src/common/stm32/stm32_adc_m0_v1.c +AES v1 arch/arm/src/common/stm32/stm32_aes_m0_v1.c +DAC v1 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m0_v1_7ch.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m0_v1.c +FLASH M0 v1 not supported +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m0_v1.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m0_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m0_v1.c +PWR v1 arch/arm/src/common/stm32/stm32_pwr_m0_v1.c +RCC to be done arch/arm/src/stm32l0/stm32_rcc.c +RNG v1 arch/arm/src/common/stm32/stm32_rng_m0_v1.c +RTC RTCC M0 not supported +SPI/I2S v1 arch/arm/src/common/stm32/stm32_spi_m0_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim_m0_v1.c +USART/LPUART v3 arch/arm/src/common/stm32/stm32_serial_m0_v3.c +USB device arch/arm/src/common/stm32/stm32_usbdev_m0_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m0_v1.c +============ ============ ================================================= + +STM32L1 +------- + +============ ============ ====================================================== +Peripheral Core version Driver +============ ============ ====================================================== +ADC v1 arch/arm/src/common/stm32/stm32_adc_m3m4_v1v2.c +AES v1 arch/arm/src/common/stm32/stm32_aes_m3m4_v1.c +DAC v1 arch/arm/src/common/stm32/stm32_dac_m3m4_v1.c +DBGMCU v2 not supported +DMA v1 arch/arm/src/common/stm32/stm32_dma_m3m4_v1_8ch.c +EXTI v1 arch/arm/src/common/stm32/stm32_exti_gpio_m3m4_v1v2.c +FLASH L1 arch/arm/src/common/stm32/stm32_flash_m3m4_l1.c +FSMC v1 arch/arm/src/common/stm32/stm32_fsmc_m3m4_v1.c +GPIO v1 arch/arm/src/common/stm32/stm32_gpio_m3m4_v1v2.c +I2C v1 arch/arm/src/common/stm32/stm32_i2c_m3m4_v1.c +IWDG v1 arch/arm/src/common/stm32/stm32_iwdg_m3m4_v1.c +LCD to be done not supported +PWR v1 arch/arm/src/common/stm32/stm32_pwr_m3m4_v1.c +RCC to be done arch/arm/src/stm32l1/stm32_rcc.c +RTC RTCC L1 arch/arm/src/common/stm32/stm32_rtcc_m3m4_l1.c +SDIO v1 arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +SPI/I2S v1 arch/arm/src/common/stm32/stm32_i2s_m3m4_v1.c +TIM v1 arch/arm/src/common/stm32/stm32_tim_m3m4_v1v2v3.c +USART/LPUART v2 arch/arm/src/common/stm32/stm32_serial_m3m4_v1v2v3v4.c +USB device arch/arm/src/common/stm32/stm32_otgfsdev_m3m4_v1.c +WWDG v1 arch/arm/src/common/stm32/stm32_wwdg_m3m4_v1.c +============ ============ ====================================================== + +STM32L5 +------- + +============ ============ ======================================== +Peripheral Core version Driver +============ ============ ======================================== +ADC to be done not supported +DAC to be done not supported +DMA/DMAMUX to be done not supported +EXTI to be done arch/arm/src/stm32l5/stm32l5_exti_gpio.c +FLASH to be done arch/arm/src/stm32l5/stm32l5_flash.c +GPIO to be done arch/arm/src/stm32l5/stm32l5_gpio.c +GTZC to be done not supported +HASH to be done not supported +I2C to be done not supported +OCTOSPI to be done not supported +PWR to be done arch/arm/src/stm32l5/stm32l5_pwr.c +RCC to be done arch/arm/src/stm32l5/stm32l5_rcc.c +RNG to be done not supported +RTC to be done not supported +SDMMC to be done not supported +SPI/I2S to be done arch/arm/src/stm32l5/stm32l5_spi.c +TIM/LPTIM to be done arch/arm/src/stm32l5/stm32l5_tim.c +USART/LPUART v3 arch/arm/src/stm32l5/stm32l5_serial.c +USB device not supported +============ ============ ======================================== + +STM32N6 +------- + +============ ============ =================================== +Peripheral Core version Driver +============ ============ =================================== +ADC to be done not supported +CAN/FDCAN to be done not supported +DAC to be done not supported +ETH to be done not supported +EXTI to be done not supported +GPIO to be done arch/arm/src/stm32n6/stm32_gpio.c +GPDMA to be done not supported +I2C to be done not supported +PWR to be done arch/arm/src/stm32n6/stm32_pwr.c +RCC to be done arch/arm/src/stm32n6/stm32_rcc.c +SPI/I2S to be done not supported +TIM to be done not supported +USART/LPUART v4 arch/arm/src/stm32n6/stm32_serial.c +USB device not supported +XSPI to be done not supported +============ ============ =================================== + +STM32U5 +------- + +============ ============ ====================================== +Peripheral Core version Driver +============ ============ ====================================== +ADC to be done not supported +DAC to be done not supported +DCACHE to be done not supported +EXTI to be done arch/arm/src/stm32u5/stm32_exti_gpio.c +FLASH to be done arch/arm/src/stm32u5/stm32_flash.c +GPIO to be done arch/arm/src/stm32u5/stm32_gpio.c +GPDMA to be done not supported +HASH to be done not supported +I2C to be done arch/arm/src/stm32u5/stm32_i2c.c +ICACHE to be done not supported +OCTOSPI to be done not supported +PWR to be done arch/arm/src/stm32u5/stm32_pwr.c +RCC to be done arch/arm/src/stm32u5/stm32_rcc.c +RNG to be done not supported +RTC to be done not supported +SAES/AES to be done not supported +SDMMC to be done not supported +SPI/I2S to be done arch/arm/src/stm32u5/stm32_spi.c +TAMP to be done not supported +TIM/LPTIM to be done arch/arm/src/stm32u5/stm32_tim.c +USART/LPUART v3 arch/arm/src/stm32u5/stm32_serial.c +USB device not supported +============ ============ ====================================== + +STM32WB +------- + +============ ============ ======================================== +Peripheral Core version Driver +============ ============ ======================================== +ADC to be done not supported +AES to be done not supported +DAC to be done not supported +DMA to be done arch/arm/src/stm32wb/stm32wb_dma.c +EXTI to be done arch/arm/src/stm32wb/stm32wb_exti_gpio.c +FLASH to be done arch/arm/src/stm32wb/stm32wb_flash.c +GPIO to be done arch/arm/src/stm32wb/stm32wb_gpio.c +I2C to be done arch/arm/src/stm32wb/stm32wb_i2c.c +IPCC to be done arch/arm/src/stm32wb/stm32wb_ipcc.c +PWR to be done arch/arm/src/stm32wb/stm32wb_pwr.c +Radio to be done not supported +RCC to be done arch/arm/src/stm32wb/stm32wb_rcc.c +RNG to be done not supported +RTC to be done arch/arm/src/stm32wb/stm32wb_rtc.c +SPI/I2S to be done arch/arm/src/stm32wb/stm32wb_spi.c +TIM/LPTIM to be done arch/arm/src/stm32wb/stm32wb_tim.c +USART/LPUART v4 arch/arm/src/stm32wb/stm32wb_serial.c +USB device not supported +============ ============ ======================================== + +STM32WL5 +-------- + +============ ============ ========================================== +Peripheral Core version Driver +============ ============ ========================================== +ADC to be done not supported +AES to be done not supported +DAC to be done not supported +DMA to be done not supported +EXTI to be done arch/arm/src/stm32wl5/stm32wl5_exti_gpio.c +FLASH to be done arch/arm/src/stm32wl5/stm32wl5_flash.c +GPIO to be done arch/arm/src/stm32wl5/stm32wl5_gpio.c +I2C to be done not supported +IPCC to be done arch/arm/src/stm32wl5/stm32wl5_ipcc.c +PWR to be done arch/arm/src/stm32wl5/stm32wl5_pwr.c +Radio to be done not supported +RCC to be done arch/arm/src/stm32wl5/stm32wl5_rcc.c +RNG to be done not supported +RTC to be done not supported +SPI/I2S to be done arch/arm/src/stm32wl5/stm32wl5_spi.c +TIM/LPTIM to be done arch/arm/src/stm32wl5/stm32wl5_tim.c +USART/LPUART v3 arch/arm/src/stm32wl5/stm32wl5_serial.c +USB to be done not supported +============ ============ ========================================== + +Kconfig option organization +=========================== + +STM32 common Kconfig symbols are split into three layers, each with a fixed +home so contributors always know where a given option belongs: + +================================= ============================ ==================== +Layer Symbol form File +================================= ============================ ==================== +Capability flags (hidden) ``STM32_HAVE_*`` ``Kconfig.have`` +Instance feature flags (hidden) ``STM32__HAVE_*`` ``Kconfig.`` +Peripheral selection ``STM32_`` ``Kconfig.periph`` +Peripheral options ``STM32__*`` ``Kconfig.`` +================================= ============================ ==================== + +All ``STM32_HAVE_*`` and ``STM32_HAVE_IP_*`` symbols are defined in the single +file ``arch/arm/src/common/stm32/Kconfig.have`` — the authoritative description +of what hardware exists. The ``STM32_HAVE_IP_*`` selectors listed above are a +subset of it. The rules for these capability flags are: + +* They are prompt-less ``bool`` symbols, defined exactly once. Never give a + capability flag a prompt. +* Family Kconfig files (``arch/arm/src/stm32/Kconfig``) ``select`` these + symbols to describe the silicon of each chip. +* Presence and feature flags may use ``default y if `` so + the right instances and features light up automatically once a family selects + its IP-core version. +* User-visible options in ``Kconfig.periph`` and ``Kconfig.`` should + ``depends on`` the capability flags rather than on family names. + +The ``STM32_HAVE_`` prefix is reserved for **chip capabilities** — things the +silicon *has*, independent of any single peripheral instance. Those live in +``Kconfig.have``. A flag that instead describes a feature of one **specific +peripheral instance** ("ADC3 *has* a DMA path", "USART1 *supports* RX DMA") is +not a chip capability: it must be named ``STM32__HAVE_`` +(``HAVE`` *after* the instance) and defined in that peripheral's +``Kconfig.`` file, never in ``Kconfig.have``. It is still a prompt-less +``bool`` ``select``-ed by the family Kconfig files, just homed with the rest of +its peripheral's options. For example: + +============================ ============================ ==================== +Wrong (chip-capability form) Correct (instance-feature) Home +============================ ============================ ==================== +``STM32_HAVE_ADC3_DMA`` ``STM32_ADC3_HAVE_DMA`` ``Kconfig.adc`` +``STM32_HAVE_SDADC1_DMA`` ``STM32_SDADC1_HAVE_DMA`` ``Kconfig.sdadc`` +``STM32_HAVE_USART1_RXDMA`` ``STM32_USART1_HAVE_RXDMA`` ``Kconfig.uart`` +``STM32_HAVE_PHY_POLLED`` ``STM32_PHY_HAVE_POLLED`` ``Kconfig.eth`` +============================ ============================ ==================== + +Capability-flag naming: + +* IP-core version selectors: ``STM32_HAVE_IP___V`` (see + `IP-core naming convention`_; the version number resets per core). +* Per-instance presence: ``STM32_HAVE_`` (for example + ``STM32_HAVE_ADC2`` or ``STM32_HAVE_USART3``). +* Feature capability (chip-wide, **no** instance number): ``STM32_HAVE_`` + (for example ``STM32_HAVE_ADC_OVERSAMPLE``). A feature tied to a specific + instance is **not** written this way — see ``STM32__HAVE_`` + above. +* Per-instance feature: ``STM32__HAVE_`` (for example + ``STM32_ADC3_HAVE_DMA``), defined in ``Kconfig.``. + +Source naming rules +=================== + +IP-core naming convention +------------------------- + +STM32 common files use a ``_`` naming convention that +encodes the CPU core family and peripheral IP version in filenames and +Kconfig symbols. Version numbers are reset per core: the first version +of a peripheral on a given core is ``V1``. + +**Header file naming** (under ``arch/arm/src/common/stm32/``): + +- Facade headers: ``stm32_.h`` — dispatch on Kconfig IP symbols +- M0-core variants: ``stm32__m0_v1.h`` +- M3/M4-core variants: ``stm32__m3m4_v1.h``, ``stm32__m3m4_v2.h`` +- Combined variants: ``stm32__m3m4_v1v2.h``, ``stm32__m3m4_v1v2v3.h`` + +**Source file naming** (``.c`` files): + +- Follow the same convention as headers: ``stm32_gpio_m3m4_v1v2.c``, + ``stm32_adc_m0_v1.c``, ``stm32_tim_m0_v1.c``, ``stm32_pwm_m3m4_v1v2v3.c`` + +**Kconfig symbol naming** (``CONFIG_STM32_HAVE_IP___``): + +- M0: ``CONFIG_STM32_HAVE_IP_GPIO_M0_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M0_V1`` +- M3/M4: ``CONFIG_STM32_HAVE_IP_GPIO_M3M4_V1``, + ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_ADC_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V1``, ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V2``, + ``CONFIG_STM32_HAVE_IP_TIMERS_M3M4_V3`` + +Note that in the future the core prefix may be dropped and a single +version number space used across all cores. For now the core prefix is +kept to make migration of families into common code simpler. + +Common STM32 files should follow these rules: + +* Files shared by more than one family are placed under + ``arch/arm/src/common/stm32``. +* Board-facing public headers use stable peripheral names such as + ``stm32_adc.h``, ``stm32_gpio.h``, and ``stm32_uart.h``. Boards and + drivers should not include IP-versioned public headers directly. +* Public STM32 symbols must use canonical ``stm32_*`` names, not + family-prefixed names (for example, use ``stm32_tim_init``, + ``stm32_dmachannel``, and ``stm32_caninitialize`` rather than + ``stm32l4_*``/``stm32h7_*`` forms). +* Public API-facing type names must also use canonical ``stm32_*`` forms + (for example, ``struct stm32_tim_dev_s``, ``struct stm32_dmaregs_s``, + and ``struct stm32_freerun_s``). +* When an equivalent STM32 API already exists, new family code must reuse + the exact public function name and compatible prototype/type signature. +* Family root aggregation headers should use ``stm32.h`` and family code + should include ```` for that root header include path. +* Hardware register selectors keep the ``hardware/stm32_.h`` + public name and may include hardware-version headers when those headers + describe real register layouts. +* Private common implementation selectors may be split only when the API, + register map, or reusable hardware shape really differs. Prefer capability + names over family names for these splits. +* Common STM32 source and hardware header names must not encode composite + family groups. If a reusable distinction is still named after a family, the + next cleanup step is to map that distinction to an IP-core version or a + hardware feature. +* Public compatibility selectors such as ``stm32_adc.h`` and + ``hardware/stm32_adc.h`` keep their public include names while selecting the + proper common implementation internally. + +Hardware definition naming convention +-------------------------------------- + +All STM32 hardware definitions (IRQ vectors, peripheral counts, SRAM sizes) +must use the standard ``STM32_`` prefix rather than family-specific prefixes. +Family-specific prefixes prevent common code from referencing hardware +definitions across families and create unnecessary differences between ports. + +**IRQ vectors** must use ``STM32_IRQ_`` (not ``STM32L4_IRQ_``, +``STM32WB_IRQ_``, etc.). + +**Peripheral count macros** (``NATIM``, ``NADC``, ``NSPI``, etc.) and SRAM +size macros must use ``STM32_`` prefix (not ``STM32F7_``, ``STM32H5_``, etc.). + +**Per-family hardware register definitions** (in ``arch/arm/src//hardware/``) +must use ``STM32_XXX_`` (not ``STM32L4_XXX_``, ``STM32WB4_XXX_``, etc.). + +Next steps +========== + +The goal is for all STM32 families to follow the rules above, so that shared +code is selected by peripheral IP version instead of family name and code +duplication is limited. The remaining work is: + +Architecture +------------ + +* Migrate the remaining families to use the common ``arch/arm/src/common/stm32`` + code. +* Review every family's selectors so they use the correct IP cores and select + only the peripherals each family actually supports. +* Remove all family-specific options that were left for later, and simplify the + complex Kconfig conditions. +* Unify the remaining peripheral-driver public headers so the API is the same + for all families. +* Better organize the CMake and Make build files for common STM32. Now it's a mess. +* Unify all supported features across families. + +Boards +------ + +* Move all families to shared ``boards/common/stm32`` board code, including + boards that do not yet use the recently added common code. +* Unify all supported features across boards of the same class (such as the + Nucleo boards) so they follow the same patterns. + +Kconfig simplification +---------------------- + +Many Kconfig conditions are still long, mix normalized ``STM32_HAVE_IP_*`` +flags with family names, and rely on composite family-group symbols +(``STM32_COMMON_LEGACY``, ``STM32_COMMON_F7_H7``, ``STM32_COMMON_L4_L5_U5``, +``STM32_COMMON_L4_H5_L5_U5``, …) that the naming rules forbid. These are the +most likely to need rework and should be reduced to depend on capability flags +only: + +* ``Kconfig.tim`` and ``Kconfig.uart`` hold the bulk of the family-name + conditions (hundreds of lines each) and are the biggest cleanup. +* ``Kconfig.adc``, ``Kconfig.periph`` and ``Kconfig.have`` carry many mixed + family/IP ``||`` chains (for example ``(STM32_HAVE_IP_ADC_M3M4_V1 || + STM32_HAVE_IP_ADC_M3M4_V2) || ARCH_CHIP_STM32F7``), where F7/H5/L4 are patched + in by family name only because they have no IP flag yet. +* Replace the composite ``STM32_COMMON_*`` family-group symbols with per-IP-core + or per-feature flags. From 9704481224a199506bfb74702c2b3638081d8474 Mon Sep 17 00:00:00 2001 From: Xiang Xiao Date: Sun, 21 Jun 2026 01:48:17 +0800 Subject: [PATCH 164/268] libc/unistd: add getgroups() Add getgroups() to the C library. NuttX has no supplementary group IDs, so it reports a single group, the effective group ID, and follows POSIX for the gidsetsize == 0 and short-buffer (EINVAL) cases. Signed-off-by: Xiang Xiao --- Documentation/standards/posix.rst | 2 +- include/unistd.h | 2 + libs/libc/unistd/CMakeLists.txt | 1 + libs/libc/unistd/Make.defs | 2 +- libs/libc/unistd/lib_getgroups.c | 85 +++++++++++++++++++++++++++++++ 5 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 libs/libc/unistd/lib_getgroups.c diff --git a/Documentation/standards/posix.rst b/Documentation/standards/posix.rst index 577abf16ce5..cdca6eb748e 100644 --- a/Documentation/standards/posix.rst +++ b/Documentation/standards/posix.rst @@ -1972,7 +1972,7 @@ User and Group: +--------------------------------+---------+ | :c:func:`getgid` | Yes | +--------------------------------+---------+ -| getgroups() | No | +| :c:func:`getgroups` | Yes | +--------------------------------+---------+ | getlogin() | No | +--------------------------------+---------+ diff --git a/include/unistd.h b/include/unistd.h index 6c7f7d1bcf3..63ded5444ac 100644 --- a/include/unistd.h +++ b/include/unistd.h @@ -494,6 +494,8 @@ gid_t getegid(void); int setreuid(uid_t ruid, uid_t euid); int setregid(gid_t rgid, gid_t egid); +int getgroups(int, gid_t[]); + int getentropy(FAR void *buffer, size_t length); void sync(void); diff --git a/libs/libc/unistd/CMakeLists.txt b/libs/libc/unistd/CMakeLists.txt index 797ff8aba9e..eb4ca8e5e93 100644 --- a/libs/libc/unistd/CMakeLists.txt +++ b/libs/libc/unistd/CMakeLists.txt @@ -65,6 +65,7 @@ set(SRCS lib_getpgrp.c lib_getpgid.c lib_getsid.c + lib_getgroups.c lib_setpgid.c lib_setsid.c lib_lockf.c diff --git a/libs/libc/unistd/Make.defs b/libs/libc/unistd/Make.defs index e7852230ad7..e3e5ed3a214 100644 --- a/libs/libc/unistd/Make.defs +++ b/libs/libc/unistd/Make.defs @@ -32,7 +32,7 @@ CSRCS += lib_setrlimit.c lib_getrlimit.c lib_setpriority.c lib_getpriority.c CSRCS += lib_futimes.c lib_lutimes.c lib_gethostname.c lib_sethostname.c CSRCS += lib_fchownat.c lib_linkat.c lib_readlinkat.c lib_symlinkat.c CSRCS += lib_unlinkat.c lib_usleep.c lib_getpgrp.c lib_getpgid.c -CSRCS += lib_getsid.c lib_setpgid.c lib_setsid.c +CSRCS += lib_getsid.c lib_getgroups.c lib_setpgid.c lib_setsid.c CSRCS += lib_lockf.c lib_flock.c lib_getpass.c CSRCS += lib_chdir.c lib_fchdir.c lib_confstr.c lib_ulimit.c diff --git a/libs/libc/unistd/lib_getgroups.c b/libs/libc/unistd/lib_getgroups.c new file mode 100644 index 00000000000..53cbc11ba82 --- /dev/null +++ b/libs/libc/unistd/lib_getgroups.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * libs/libc/unistd/lib_getgroups.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: getgroups + * + * Description: + * The getgroups() function returns the supplementary group IDs of the + * calling process in the array grouplist. NuttX does not support + * supplementary group IDs, so the calling process is treated as belonging + * to a single group: its effective group ID. + * + * Input Parameters: + * gidsetsize - The number of elements available in grouplist. + * grouplist - The buffer used to return the group IDs. + * + * Returned Value: + * On success, the number of group IDs is returned. If gidsetsize is zero, + * the total number of group IDs is returned without modifying grouplist. + * On failure, -1 is returned and errno is set appropriately. + * + ****************************************************************************/ + +int getgroups(int gidsetsize, gid_t grouplist[]) +{ + if (gidsetsize < 0) + { + set_errno(EINVAL); + return -1; + } + + /* If gidsetsize is zero, return the number of group IDs without touching + * grouplist. + */ + + if (gidsetsize == 0) + { + return 1; + } + + if (grouplist == NULL) + { + set_errno(EFAULT); + return -1; + } + + /* NuttX has no notion of supplementary group IDs. Report the single + * effective group ID of the calling process. + */ + + grouplist[0] = getegid(); + return 1; +} From d79beefa549b88bccc2cfe8375a511214682d5ae Mon Sep 17 00:00:00 2001 From: Andrew Au Date: Mon, 15 Jun 2026 18:22:31 +0000 Subject: [PATCH 165/268] armv7-m/armv8-m: honor SP modifications on signal return On ARMv7-M/ARMv8-M, the hardware exception return determines the final SP from the physical location of the HW exception frame, ignoring any software modification to REG_R13 in the saved register context. This means signal handlers that adjust SP have their change silently discarded. Fix this by relocating the saved context in arm_sigdeliver before calling arm_fullcontextrestore. If the desired SP (regs[REG_R13]) differs from the implied SP, memmove the entire context frame so that the hardware exception return produces the correct final SP. The fix runs only in the signal return path, adding zero overhead to the normal exception return hot path. Signed-off-by: Andrew Au --- arch/arm/src/armv7-m/arm_sigdeliver.c | 25 +++++++++++++++++++++++++ arch/arm/src/armv8-m/arm_sigdeliver.c | 25 +++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/arch/arm/src/armv7-m/arm_sigdeliver.c b/arch/arm/src/armv7-m/arm_sigdeliver.c index ad01879ff9e..02b17525288 100644 --- a/arch/arm/src/armv7-m/arm_sigdeliver.c +++ b/arch/arm/src/armv7-m/arm_sigdeliver.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -57,6 +58,9 @@ void arm_sigdeliver(void) { struct tcb_s *rtcb = this_task(); uint32_t *regs = rtcb->xcp.saved_regs; + uint32_t *new_regs; + uint32_t desired_sp; + uint32_t implied_sp; #ifdef CONFIG_SMP /* In the SMP case, we must terminate the critical section while the signal @@ -163,6 +167,27 @@ retry: leave_critical_section(up_irq_save()); #endif + /* If the signal handler modified SP (REG_R13), relocate the saved + * context so that the hardware exception return produces the correct SP. + * + * On ARMv7-M, the exception return path sets PSP to the HW frame address + * and hardware computes final SP = PSP + frame_size. The implied SP is + * determined by the physical location of the context, not by REG_R13. + * To honor a modified SP, we memmove the entire context frame to the + * address where the end of the frame equals the desired SP. + */ + + desired_sp = regs[REG_R13]; + implied_sp = (uint32_t)regs + XCPTCONTEXT_SIZE; + + if (desired_sp != implied_sp) + { + new_regs = (uint32_t *)(desired_sp - XCPTCONTEXT_SIZE); + memmove(new_regs, regs, XCPTCONTEXT_SIZE); + regs = new_regs; + rtcb->xcp.saved_regs = new_regs; + } + rtcb->xcp.regs = rtcb->xcp.saved_regs; arm_fullcontextrestore(); UNUSED(regs); diff --git a/arch/arm/src/armv8-m/arm_sigdeliver.c b/arch/arm/src/armv8-m/arm_sigdeliver.c index 538350a77ab..39e1b0d3be9 100644 --- a/arch/arm/src/armv8-m/arm_sigdeliver.c +++ b/arch/arm/src/armv8-m/arm_sigdeliver.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -57,6 +58,9 @@ void arm_sigdeliver(void) { struct tcb_s *rtcb = this_task(); uint32_t *regs = rtcb->xcp.saved_regs; + uint32_t *new_regs; + uint32_t desired_sp; + uint32_t implied_sp; #ifdef CONFIG_SMP /* In the SMP case, we must terminate the critical section while the signal @@ -163,6 +167,27 @@ retry: leave_critical_section(up_irq_save()); #endif + /* If the signal handler modified SP (REG_R13), relocate the saved + * context so that the hardware exception return produces the correct SP. + * + * On ARMv8-M, the exception return path sets PSP to the HW frame address + * and hardware computes final SP = PSP + frame_size. The implied SP is + * determined by the physical location of the context, not by REG_R13. + * To honor a modified SP, we memmove the entire context frame to the + * address where the end of the frame equals the desired SP. + */ + + desired_sp = regs[REG_R13]; + implied_sp = (uint32_t)regs + XCPTCONTEXT_SIZE; + + if (desired_sp != implied_sp) + { + new_regs = (uint32_t *)(desired_sp - XCPTCONTEXT_SIZE); + memmove(new_regs, regs, XCPTCONTEXT_SIZE); + regs = new_regs; + rtcb->xcp.saved_regs = new_regs; + } + rtcb->xcp.regs = rtcb->xcp.saved_regs; arm_fullcontextrestore(); UNUSED(regs); From 2b17b0c9924fb287180725679abba30a29ddf5d9 Mon Sep 17 00:00:00 2001 From: Joao Mario Lago Date: Wed, 24 Jun 2026 14:39:11 -0300 Subject: [PATCH 166/268] arch/arm/stm32h5/adc: disable CONT for timer-triggered circular DMA Clear ADC_CFGR_CONT when using timer-triggered circular DMA so each timer event starts a single conversion sequence. This prevents the ADC from free-running after the first trigger and losing syncronization with the timer. Signed-off-by: Joao Mario Lago --- arch/arm/src/stm32h5/stm32_adc.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/src/stm32h5/stm32_adc.c b/arch/arm/src/stm32h5/stm32_adc.c index 7fe90ea6464..e38f34e8a70 100644 --- a/arch/arm/src/stm32h5/stm32_adc.c +++ b/arch/arm/src/stm32h5/stm32_adc.c @@ -1445,7 +1445,18 @@ static int adc_setup(struct adc_dev_s *dev) { setbits |= ADC_CFGR_OVRMOD; /* overwrite on overrun */ setbits |= ADC_CFGR_DMACFG; +# ifdef ADC_HAVE_TIMER + if (priv->tbase != 0) + { + clrbits |= ADC_CFGR_CONT; + } + else + { + setbits |= ADC_CFGR_CONT; + } +# else setbits |= ADC_CFGR_CONT; +# endif } else { From 3aa3c215049d6fd69746c752b39436de7fca7bb1 Mon Sep 17 00:00:00 2001 From: Felipe Moura Date: Wed, 24 Jun 2026 16:50:15 -0300 Subject: [PATCH 167/268] fs/vfs: provide link fallback without softlinks Build fs_link.c unconditionally so link() remains available even when CONFIG_PSEUDOFS_SOFTLINKS is disabled. Return ENOSYS in that configuration instead of leaving applications with an undefined symbol. Signed-off-by: Felipe Moura --- fs/vfs/CMakeLists.txt | 5 +++-- fs/vfs/Make.defs | 4 ++-- fs/vfs/fs_link.c | 23 +++++++++++------------ 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/fs/vfs/CMakeLists.txt b/fs/vfs/CMakeLists.txt index f1b6b45f743..3880b2a3727 100644 --- a/fs/vfs/CMakeLists.txt +++ b/fs/vfs/CMakeLists.txt @@ -51,7 +51,8 @@ set(SRCS fs_dir.c fs_fsync.c fs_syncfs.c - fs_truncate.c) + fs_truncate.c + fs_link.c) # File notify support @@ -66,7 +67,7 @@ if(NOT "${CONFIG_FS_LOCK_BUCKET_SIZE}" STREQUAL "0") endif() if(NOT "${CONFIG_PSEUDOFS_SOFTLINKS}" STREQUAL "0") - list(APPEND SRCS fs_link.c fs_symlink.c fs_readlink.c) + list(APPEND SRCS fs_symlink.c fs_readlink.c) endif() # Pseudofile support diff --git a/fs/vfs/Make.defs b/fs/vfs/Make.defs index 75b7ad168c4..ce2a7a5f5af 100644 --- a/fs/vfs/Make.defs +++ b/fs/vfs/Make.defs @@ -27,7 +27,7 @@ CSRCS += fs_epoll.c fs_fchstat.c fs_fstat.c fs_fstatfs.c fs_ioctl.c fs_lseek.c CSRCS += fs_mkdir.c fs_open.c fs_poll.c fs_pread.c fs_pwrite.c fs_read.c CSRCS += fs_rename.c fs_rmdir.c fs_select.c fs_sendfile.c fs_stat.c CSRCS += fs_statfs.c fs_uio.c fs_unlink.c fs_write.c fs_dir.c fs_fsync.c -CSRCS += fs_syncfs.c fs_truncate.c +CSRCS += fs_syncfs.c fs_truncate.c fs_link.c ifeq ($(CONFIG_FS_NOTIFY),y) CSRCS += fs_inotify.c @@ -38,7 +38,7 @@ CSRCS += fs_lock.c endif ifneq ($(CONFIG_PSEUDOFS_SOFTLINKS),0) -CSRCS += fs_link.c fs_symlink.c fs_readlink.c +CSRCS += fs_symlink.c fs_readlink.c endif # Pseudofile support diff --git a/fs/vfs/fs_link.c b/fs/vfs/fs_link.c index ffdb193706f..e47ac41fffe 100644 --- a/fs/vfs/fs_link.c +++ b/fs/vfs/fs_link.c @@ -26,14 +26,9 @@ #include +#include #include -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_PSEUDOFS_SOFTLINKS - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -42,10 +37,8 @@ * Name: link * * Description: - * The link function provides a wrapper to symlink. Solely to provide - * compatibility to posix compatibility layer. - * - * See symlink for details on limitations. + * The link function provides a wrapper to symlink when pseudo filesystem + * softlinks are enabled. Otherwise, hard links are unsupported. * * Input Parameters: * path1 - Points to a pathname naming an existing file. @@ -60,7 +53,13 @@ int link(FAR const char *path1, FAR const char *path2) { +#ifdef CONFIG_PSEUDOFS_SOFTLINKS return symlink(path1, path2); -} +#else + (void)path1; + (void)path2; -#endif /* CONFIG_PSEUDOFS_SOFTLINKS */ + set_errno(ENOSYS); + return ERROR; +#endif +} From 0d4ad87fe4e220ec691235b903e21210f1569ca4 Mon Sep 17 00:00:00 2001 From: Alin Jerpelea Date: Thu, 25 Jun 2026 11:33:37 +0200 Subject: [PATCH 168/268] Documentation: add NuttX 13.0.0 release notes add release notes for NuttX 13.0.0 release Signed-off-by: Alin Jerpelea --- Documentation/ReleaseNotes/NuttX-13.0.0 | 394 ++++++++++++++++++++++++ 1 file changed, 394 insertions(+) create mode 100644 Documentation/ReleaseNotes/NuttX-13.0.0 diff --git a/Documentation/ReleaseNotes/NuttX-13.0.0 b/Documentation/ReleaseNotes/NuttX-13.0.0 new file mode 100644 index 00000000000..e4dd19106f0 --- /dev/null +++ b/Documentation/ReleaseNotes/NuttX-13.0.0 @@ -0,0 +1,394 @@ +NuttX-13.0.0 +------------ + +What's New In This Release +Major Changes to Core OS +Sched +* [#18485](https://github.com/apache/nuttx/pull/18485) sched/critmon: Fix CPU load stats incorrect when using SCHED_CPULOAD_CRITMONITOR +* [#18486](https://github.com/apache/nuttx/pull/18486) sched/tickless: Fix CLOCK_MONOTONIC always 0 by updating sched ticks +* [#18592](https://github.com/apache/nuttx/pull/18592) sched/group_foreachchild.c: fix warning +* [#18672](https://github.com/apache/nuttx/pull/18672) sched/semaphore: check unmasked pending signals before blocking. +* [#18715](https://github.com/apache/nuttx/pull/18715) sched/nsh: Remove Hard-coded Default Password +* [#18731](https://github.com/apache/nuttx/pull/18731) sched/misc: Optimize thread saving order in coredump for easier gdb d… +* [#18826](https://github.com/apache/nuttx/pull/18826) sched/group: skip group_release for kernel thread group + +Crypto +* [#18679](https://github.com/apache/nuttx/pull/18679) crypto: decouple curve25519 and idgen from random pool +* [#18608](https://github.com/apache/nuttx/pull/18608) crypto/cryptosoft: Add support for PBKDF2 + +libc +* [#18347](https://github.com/apache/nuttx/pull/18347) libc: Add C23 stdbit.h with optional Kconfig and generic implementation +* [#18572](https://github.com/apache/nuttx/pull/18572) libs/libbuiltin: Fix spacing style in gcov.c +* [#18844](https://github.com/apache/nuttx/pull/18844) libs/netdb: Fix dns_recv_response() to dns_answer_s size +various +* [#18643](https://github.com/apache/nuttx/pull/18643) guard include/cxx by LIBMINIABI, fix div_t conflicts with downloaded toolchains +* [#18660](https://github.com/apache/nuttx/pull/18660) include/debug.h: Move to include/nuttx/debug.h +* [#18839](https://github.com/apache/nuttx/pull/18839) include/errno.h: skip set_errno in interrupt context + +Major Changes to the Build System +tools +* [#18856](https://github.com/apache/nuttx/pull/18856) tools: mksyscall fix compilation warning +* [#18538](https://github.com/apache/nuttx/pull/18538) tools: replace showstack.sh with stackusage.py +* [#18863](https://github.com/apache/nuttx/pull/18863) tools: Update note about first line of a block +* [#18426](https://github.com/apache/nuttx/pull/18426) tools/checkpatch: enforce blank line after subject and add breaking-change checks +* [#18868](https://github.com/apache/nuttx/pull/18868) tools/Config.mk: speed up builds by caching the prefix-detection shells +* [#18973](https://github.com/apache/nuttx/pull/18973) tools/espressif: Add UF2 output support +* [#18360](https://github.com/apache/nuttx/pull/18360) tools/mksyscall: fix union illegal type for cast +* [#19006](https://github.com/apache/nuttx/pull/19006) tools/nxstyle: Whitelist Micro XRCE-DDS uxrCustomTransport prefix +* [#19001](https://github.com/apache/nuttx/pull/19001) tools/nxstyle: Whitelist ROS 2 message type identifiers. +* [#18992](https://github.com/apache/nuttx/pull/18992) tools/rust: Fix aarch64 NuttX Rust target specs +* [#19003](https://github.com/apache/nuttx/pull/19003) tools/rust: Move NuttX Rust target specs into nuttx +* [#18547](https://github.com/apache/nuttx/pull/18547) tools/testbuild.sh: Added a break to the dotest Blacklist and CMake loop +* [#18735](https://github.com/apache/nuttx/pull/18735) tools/Unix.mk: fix Untracked files defconfig.tmp-e on macOS + +cmake +* [#18768](https://github.com/apache/nuttx/pull/18768) arch/risc-v/cmake: fix linker option case in Toolchain.cmake. +* [#18702](https://github.com/apache/nuttx/pull/18702) arch/risc-v/espressif: Aligned Cmake with Make +* [#18940](https://github.com/apache/nuttx/pull/18940) arch/risc-v/espressif: Fix CMake build issues for new peripheral support +* [#18901](https://github.com/apache/nuttx/pull/18901) arch/risc-v/espressif: Fix CMake irq.h header ordering race +* [#18698](https://github.com/apache/nuttx/pull/18698) CMake: add -D__NuttX__ to preprocessor +* [#18661](https://github.com/apache/nuttx/pull/18661) CMake: add build support on RISC-V +* [#18706](https://github.com/apache/nuttx/pull/18706) CMake: added esp32c6-xiao and esp32p4-pico-wifi-wareshare boards +* [#18669](https://github.com/apache/nuttx/pull/18669) CMake: added Seeed Studio XIAO ESP32C3 board +* [#18523](https://github.com/apache/nuttx/pull/18523) CMake: added ViewTool stm32f107 board +* [#18665](https://github.com/apache/nuttx/pull/18665) CMake: added Waveshare ESP32-C3-Zero board +* [#18594](https://github.com/apache/nuttx/pull/18594) CMake: build implemented for Allwinner A64 +* [#18565](https://github.com/apache/nuttx/pull/18565) CMake: build implemented for GigaDevice GD32F4xx Series +* [#18524](https://github.com/apache/nuttx/pull/18524) CMake: build implemented for MAX326xx Series +* [#18605](https://github.com/apache/nuttx/pull/18605) CMake: build implemented for HPMicro HPM6750 +* [#18528](https://github.com/apache/nuttx/pull/18528) CMake: build implemented for NXP LPC54000 Series +* [#18537](https://github.com/apache/nuttx/pull/18537) CMake: build implemented for NXP i.MX 8M Plus family +* [#18539](https://github.com/apache/nuttx/pull/18539) CMake: build implemented for NXP LPC17xx/40xx family +* [#18545](https://github.com/apache/nuttx/pull/18545) CMake: build implemented for NuMicro NUC100 Series +* [#18546](https://github.com/apache/nuttx/pull/18546) CMake: build implemented for NXP LPC43xx +* [#18595](https://github.com/apache/nuttx/pull/18595) CMake: build implemented for NXP i.MX 8 +* [#18597](https://github.com/apache/nuttx/pull/18597) CMake: build implemented for Rockchip RK3399 +* [#18604](https://github.com/apache/nuttx/pull/18604) CMake: build implemented for SiFive FE310 +* [#18957](https://github.com/apache/nuttx/pull/18957) CMake: Fix SIM_TOOLCHAIN using CMake on macOS. +* [#18743](https://github.com/apache/nuttx/pull/18743) CMake: Improvements to CMakeLists.txt file +* [#18964](https://github.com/apache/nuttx/pull/18964) CMake: nuttx_create_symlink: Remove warning for CMP0205 +* [#18871](https://github.com/apache/nuttx/pull/18871) fix macOS sim cmake build and compiler-rt +* [#18858](https://github.com/apache/nuttx/pull/18858) openamp: fix CMake dcache option +* [#18773](https://github.com/apache/nuttx/pull/18773) sensors/Make.defs: Aligned Make with Cmake file + +Architectural Support +New Architecture Support +* [#18739](https://github.com/apache/nuttx/pull/18739) arch/arm: add STM32H755XI chip + +Architecture improvements +* [#18704](https://github.com/apache/nuttx/pull/18704) arch/*/Makefile: Avoid uncessary relinking of the nuttx binary. +ARM +* [#18734](https://github.com/apache/nuttx/pull/18734) arch/arm: Fix the compilation error +* [#18898](https://github.com/apache/nuttx/pull/18898) arch/arm: fix infinite loop in test and clean cache operations +* [#18824](https://github.com/apache/nuttx/pull/18824) arch/arm/include/arm*/irq.h: fix FPU context layout guard macro +* [#19194](https://github.com/apache/nuttx/pull/19194) arch/arm/armv7-a: Fix L1 page table entry double-offset in addrenv create region +* [#18600](https://github.com/apache/nuttx/pull/18600) arch/arm/cxd56xx: Fix DMA transfer for large memory size +* [#18930](https://github.com/apache/nuttx/pull/18930) arch/arm/imx9: Add SAR ADC support +* [#18727](https://github.com/apache/nuttx/pull/18727) arch/arm/imx9: eDMA5 don't enable all interrupts +* [#18713](https://github.com/apache/nuttx/pull/18713) arch/arm/nrf52|nrf53: add qencoder support +* [#18865](https://github.com/apache/nuttx/pull/18865) arch/arm/rp23xx: correct NVIC and PendSV priority initialisation +* [#18947](https://github.com/apache/nuttx/pull/18947) arch/arm/rp23xx: Fix PWM frequency, duty cycle and API migration. +* [#18621](https://github.com/apache/nuttx/pull/18621) arch/arm/samX/sam_gpioirq.c: fix pin base address calculation +* [#18494](https://github.com/apache/nuttx/pull/18494) arch/arm/samvX/sam_gpioirq.c: fix pin base address calculation +* [#18717](https://github.com/apache/nuttx/pull/18717) arch/arm/sarm/tm32f0l0g0: add qencoder support +* [#18878](https://github.com/apache/nuttx/pull/18878) arch/arm/stm32: chunk DMA exchanges to honor 16-bit NDTR for SPI +* [#18975](https://github.com/apache/nuttx/pull/18975) arch/arm/stm32: Support optional TX/RX UART GPIOs. +* [#18606](https://github.com/apache/nuttx/pull/18606) arch/arm/stm32*: Cleanup stm32 irq reporting +* [#18657](https://github.com/apache/nuttx/pull/18657) arch/arm/stm32*: Use PRIx32 format specifier where appropriate +* [#18753](https://github.com/apache/nuttx/pull/18753) arch/arm/stm32f0l0g0/stm32_serial_v2.c: fix compilation error +* [#18917](https://github.com/apache/nuttx/pull/18917) arch/arm/stm32f0l0g0: restore PWM mapping for single channel +* [#18922](https://github.com/apache/nuttx/pull/18922) arch/arm/stm32h5: Add ethernet hardware checksum +* [#18944](https://github.com/apache/nuttx/pull/18944) arch/arm/stm32h5: Add missing netdev_carrier calls +* [#18549](https://github.com/apache/nuttx/pull/18549) arch/arm/stm32h5: Add support for HW RNG. +* [#18748](https://github.com/apache/nuttx/pull/18748) arch/arm/stm32h5: Add support for USB host +* [#18935](https://github.com/apache/nuttx/pull/18935) arch/arm/stm32h5: Fix warning message about used but not initialized variables +* [#18761](https://github.com/apache/nuttx/pull/18761) arch/arm/stm32h5: Fixed Hub support +* [#18960](https://github.com/apache/nuttx/pull/18960) arch/arm/stm32h7: Add support for CRYP peripheral +* [#18787](https://github.com/apache/nuttx/pull/18787) arch/arm/stm32h7: Fix SPI RX DMA returning stale DCACHE data +* [#18691](https://github.com/apache/nuttx/pull/18691) arch/arm/stm32h7: fix stm32_mdio private structure use +* [#18526](https://github.com/apache/nuttx/pull/18526) arch/arm/stm32l5: enable LPUART1 console on ST-Link VCP. on nucleo-l552ze board +* [#18892](https://github.com/apache/nuttx/pull/18892) arch/arm/stm32n6: Add STM32N6 chip and Nucleo-N657X0-Q board support +ARM64 +* [#18490](https://github.com/apache/nuttx/pull/18490) arch/arm64: handle fatal user exception +* [#18870](https://github.com/apache/nuttx/pull/18870) arch/arm64/imx9: Add SAR ADC support +* [#18501](https://github.com/apache/nuttx/pull/18501) arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing +RISC-V +* [#18516](https://github.com/apache/nuttx/pull/18516) arch/risc-v/espressif/esp32p4: Support ESP32-P4 on NuttX +* [#18536](https://github.com/apache/nuttx/pull/18536) arch/risc-v/espressif: Add SHA accelerator features +* [#18540](https://github.com/apache/nuttx/pull/18540) arch/risc-v/k210: Add sysctl driver for clock and reset control. +* [#18544](https://github.com/apache/nuttx/pull/18544) arch/risc-v/espressif: Add AES accelerator support +* [#18550](https://github.com/apache/nuttx/pull/18550) arch/risc-v/k210: Add Watchdog Timer (WDT) driver support. +* [#18553](https://github.com/apache/nuttx/pull/18553) arch/risc-v/hpm6000: Use WDOGx naming for watchdog peripherals +* [#18577](https://github.com/apache/nuttx/pull/18577) arch/risc-v/k210: Remove QEMU support +* [#18611](https://github.com/apache/nuttx/pull/18611) arch/risc-v/espressif: select EFUSE when ESPRESSIF_EFUSE is enabled +* [#18694](https://github.com/apache/nuttx/pull/18694) arch/risc-v/esp32[-c3|-c6|-h2]: Add auto light sleep +* [#18640](https://github.com/apache/nuttx/pull/18640) arch/risc-v/espressif: Fix wrong C3 naming +* [#18644](https://github.com/apache/nuttx/pull/18644) arch/risc-v/qemu-rv: Configure PMP before booting secondary harts. +* [#18651](https://github.com/apache/nuttx/pull/18651) arch/risc-v/espressif: Add lpcore support for esp32p4 +* [#18656](https://github.com/apache/nuttx/pull/18656) arch/risc-v/espressif: Add LPI2C support for esp32p4 +* [#18686](https://github.com/apache/nuttx/pull/18686) arch/risc-v: migrate hr timer backend to HAL esp_timer adapter +* [#18707](https://github.com/apache/nuttx/pull/18707) arch/risc-v: Enable low power mode for ESP32-P4 +* [#18733](https://github.com/apache/nuttx/pull/18733) arch/risc-v: fix linking process of Espressif devices +* [#18740](https://github.com/apache/nuttx/pull/18740) arch/risc-v/espressif: Fix Kconfig option for TWAI +* [#18741](https://github.com/apache/nuttx/pull/18741) arch/risc-v/espressif: Add DFS feature +* [#18827](https://github.com/apache/nuttx/pull/18827) arch/risc-v: Support the ethernet driver on ESP32-P4 +* [#18757](https://github.com/apache/nuttx/pull/18757) arch/risc-v: update MCUboot slot sizes on Espressif devices +* [#18765](https://github.com/apache/nuttx/pull/18765) arch/risc-v/espressif: Fix auto light sleep enable flag +* [#18776](https://github.com/apache/nuttx/pull/18776) arch/[risc-v|xtensa]: Re-add `RMT_LOOP_TEST_MODE` Kconfig entry +* [#18791](https://github.com/apache/nuttx/pull/18791) arch/risc-v/espressif: Add LP_ADC support +* [#18792](https://github.com/apache/nuttx/pull/18792) arch/risc-v/espressif: Add ULP wakeup modes +* [#18814](https://github.com/apache/nuttx/pull/18814) arch/risc-v/espressif: Fix PM wakeup sources +* [#18854](https://github.com/apache/nuttx/pull/18854) arch/risc-v/espressif: Add BLE sleep +* [#18652](https://github.com/apache/nuttx/pull/18652) arch/risc-v/espressif: serialize Wi-Fi RX queue access. +* [#18926](https://github.com/apache/nuttx/pull/18926) arch/risc-v/espressif: Add Analog Comparator for esp32[-h2|-p4] +* [#18874](https://github.com/apache/nuttx/pull/18874) arch/risc-v: Allow BSS segments on PSRAM for ESP32-P4 +* [#18893](https://github.com/apache/nuttx/pull/18893) arch/risc-v/espressif: Add LPSPI and SPI3 support +* [#18896](https://github.com/apache/nuttx/pull/18896) arch/risc-v/espressif: Add touch sensor support for esp32[-p4] +* [#18931](https://github.com/apache/nuttx/pull/18931) arch/risc-v: Enable setting cache line size for ESP32-P4 +* [#18941](https://github.com/apache/nuttx/pull/18941) arch/risc-v: Clear BSS section for RISC-V-based Espressif SoCs +* [#18942](https://github.com/apache/nuttx/pull/18942) arch/risc-v: Fix Espressif timer registering ID +* [#18959](https://github.com/apache/nuttx/pull/18959) arch/risc-v/espressif: Add LP Mailbox support for esp32p4 +* [#19204](https://github.com/apache/nuttx/pull/19204) arch/risc-v/rp23xx-rv: Fix PWM frequency and duty cycle calculation. +SIM +* [#18801](https://github.com/apache/nuttx/pull/18801) arch/sim: add simulated time ratio support +* [#18809](https://github.com/apache/nuttx/pull/18809) arch/sim: add host_set_timeratio stub for Windows +* [#18966](https://github.com/apache/nuttx/pull/18966) arch/sim: Add MM_FILL_ALLOCATIONS support to sim customized heap. +* [#18886](https://github.com/apache/nuttx/pull/18886) arch/sim: replace macOS C++ constructor runtime hack with post-link patch +* [#18887](https://github.com/apache/nuttx/pull/18887) arch/sim: rename nuttx libc memchr to avoid host glibc collision +* [#18956](https://github.com/apache/nuttx/pull/18956) arch/sim: Stop publishing stale X11 display during teardown. +TRICORE +* [#18391](https://github.com/apache/nuttx/pull/18391) arch/tricore: add support for tc4xx series chips and boards +* [#18525](https://github.com/apache/nuttx/pull/18525) arch/tricore: Fix `--help--` in Kconfig +* [#18899](https://github.com/apache/nuttx/pull/18899) arch/tricore: add TriCore up_backtrace() support +* [#18909](https://github.com/apache/nuttx/pull/18909) arch/tricore: Add up_perf function for tricore. +* [#18910](https://github.com/apache/nuttx/pull/18910) arch/tricore: Improve up_backtrace implementation +* [#18911](https://github.com/apache/nuttx/pull/18911) arch/tricore: Suspend stm when CPU stops. +* [#18927](https://github.com/apache/nuttx/pull/18927) arch/tricore: Support setjmp and longjmp. +* [#18936](https://github.com/apache/nuttx/pull/18936) arch/tricore: Add hardware debug breakpoint and watchpoint support. +X86_64 +* [#18829](https://github.com/apache/nuttx/pull/18829) arch/x86: Add support to 256 color for qemu i486 VGA driver +* [#18602](https://github.com/apache/nuttx/pull/18602) arch/intel64: add CPU affinity support for irq +* [#18772](https://github.com/apache/nuttx/pull/18772) arch/intel64: fix broken ostest +XTENSA +* [#18610](https://github.com/apache/nuttx/pull/18610) arch/xtensa: Fix Kconfig style +* [#18688](https://github.com/apache/nuttx/pull/18688) arch/xtensa/esp32: Add support for hardware accelerated PBKDF2 +* [#18695](https://github.com/apache/nuttx/pull/18695) arch/xtensa/esp32: Fix IRAM heap boot issue +* [#18728](https://github.com/apache/nuttx/pull/18728) arch/xtensa/esp32[|s3]: Fix ROM strdup heap issue in USER_HEAP mode +* [#18769](https://github.com/apache/nuttx/pull/18769) arch/xtensa: remove _info from startup of ESP32 +* [#18770](https://github.com/apache/nuttx/pull/18770) arch/xtensa: Scope Wi-Fi disconnect case declarations. +* [#18778](https://github.com/apache/nuttx/pull/18778) arch/xtensa: properly set carrier on/off on espnow driver + +Driver Support +New Driver Support +* [#18780](https://github.com/apache/nuttx/pull/18780) drivers/input: Add support to MPR121 Capacitive Keypad +* [#18904](https://github.com/apache/nuttx/pull/18904) drivers/mtd/mx25rxx.c: add support for MX25L12873G +* [#18807](https://github.com/apache/nuttx/pull/18807) drivers/sensors: Add support to mt6816 magnetic encoder +* [#18609](https://github.com/apache/nuttx/pull/18609) drivers/usbdev: add UVC gadget class driver +* [#17408](https://github.com/apache/nuttx/pull/17408) initial support for fixed-point data for sensors +Drivers With Improvements +* [#18985](https://github.com/apache/nuttx/pull/18985) drivers: Fix comment typos — 'register' → 'registered' across drivers. +* [#18980](https://github.com/apache/nuttx/pull/18980) drivers/analog: fix dead free and memory leak in mcp48xx and mcp47x6. +* [#18986](https://github.com/apache/nuttx/pull/18986) drivers/analog: Fix memory leak and dead code in mcp3008_initialize. +* [#18987](https://github.com/apache/nuttx/pull/18987) drivers/analog: Fix memory leak in ads1115_initialize. +* [#18996](https://github.com/apache/nuttx/pull/18996) drivers/analog/dac7554: Add NULL checks after kmm_malloc in dac7554_initialize +* [#18759](https://github.com/apache/nuttx/pull/18759) drivers/can: Fix close drain, write-only reader lifecycle, and STM32 RX header +* [#19192](https://github.com/apache/nuttx/pull/19192) drivers/clk: use uintptr_t for register addresses to fix GCC15 warnings +* [#19193](https://github.com/apache/nuttx/pull/19193) drivers/eeprom/i2c_xx24xx: Integer Overflow in I2C EEPROM ee24xx_seek() +* [#18505](https://github.com/apache/nuttx/pull/18505) drivers/lcd: Refactor ST7796 to use Kconfig and add Power Management +* [#18835](https://github.com/apache/nuttx/pull/18835) drivers/fb: Fix a symbol missing CONFIG_ +* [#18552](https://github.com/apache/nuttx/pull/18552) drivers/mtd/ftl: honor O_DIRECT flag, remove bootloader write buffering +* [#18685](https://github.com/apache/nuttx/pull/18685) drivers/mtd/mx25rxx.c: use 4 byte address for large flash memories. +* [#18564](https://github.com/apache/nuttx/pull/18564) drivers/mtd/w25.c: ensure the device is not in power down mode +* [#18771](https://github.com/apache/nuttx/pull/18771) drivers/mtd/w25n: implement bad block management +* [#18984](https://github.com/apache/nuttx/pull/18984) drivers/net: Fix typo in lan9250_set_txavailable function name. +* [#18633](https://github.com/apache/nuttx/pull/18633) drivers/net/telnet: Ignore unsupported subnegotiation data. +* [#18638](https://github.com/apache/nuttx/pull/18638) drivers/net/telnet: Fix typo. +* [#18599](https://github.com/apache/nuttx/pull/18599) drivers/net/telnet: fix typo in telnet.c +* [#18933](https://github.com/apache/nuttx/pull/18933) drivers/usbhost_hidmouse: fix button detection in touchscreen example +* [#18997](https://github.com/apache/nuttx/pull/18997) drivers/rpmsg: Fix typo rpmsg_device_destory -> rpmsg_device_destroy +* [#18903](https://github.com/apache/nuttx/pull/18903) drivers/rpmsg and rptun: some compile error fix +* [#18491](https://github.com/apache/nuttx/pull/18491) drivers/rpmsg_virtio: add VIRTIO_RPMSG_F_BUFADDR to support specifying buffer address +* [#18742](https://github.com/apache/nuttx/pull/18742) drivers/sensors: fix misplaced endif in bmi160_base.c +* [#18848](https://github.com/apache/nuttx/pull/18848) drivers/timers: avoid 32-bit overflow in arch_timer current_usec +* [#18938](https://github.com/apache/nuttx/pull/18938) drivers/video: use spinlock to replace critical section for goldfish_… +* [#18897](https://github.com/apache/nuttx/pull/18897) drivers/video/vnc: fix typo in Kconfig +* [#18527](https://github.com/apache/nuttx/pull/18527) drivers/wireless/cc1101: Add MSK/4-FSK, dynamic PATABLE ramping, and fix IOCTL safety + +Board Support +New Board Support +* [#17229](https://github.com/apache/nuttx/pull/17229) boards/arm/am67: Add support for T3 Gemstone O1 board +* [#18573](https://github.com/apache/nuttx/pull/18573) boards/arm/ht32f491x3: Add support for the HT32F49163 Starter Kit board +* [#18921](https://github.com/apache/nuttx/pull/18921) boards/arm/stm32h7: Add support for nucleo-h753zi board +* [#18475](https://github.com/apache/nuttx/pull/18475) boards/arm/stm32h7: Add support for the NUCLEO-H723ZG board +* [#18907](https://github.com/apache/nuttx/pull/18907) boards/arm64/am62x: add initial BeaglePlay and PocketBeagle2 bring-up +* [#18570](https://github.com/apache/nuttx/pull/18570) boards/risc-v/esp32: Added support for wareshare ESP32-P4-Pico-wifi. +* [#18730](https://github.com/apache/nuttx/pull/18730) boards/xtensa/esp32s3: New board WaveShare ESP32-S3-(Touch)-LCD-1.28. +Boards With Improvements +* [#18551](https://github.com/apache/nuttx/pull/18551) boards: add option to disable SPI Flash MTD automatic bringup on Espressif devices +* [#18744](https://github.com/apache/nuttx/pull/18744) boards: Fix modbus configs after moving it to apps/industry +* [#18750](https://github.com/apache/nuttx/pull/18750) boards: Increase `esp32h2-devkit:efuse` IDLETHREAD stack to 3072 +* [#18918](https://github.com/apache/nuttx/pull/18918) boards: PWM support for nucleo-c091 and nucleo-c071 +* [#18833](https://github.com/apache/nuttx/pull/18833) boards/config: Remove final mentions of `NSH_ARCHINIT` +ARM +* [#18838](https://github.com/apache/nuttx/pull/18838) boards/arm: Remove app-specific initialization +* [#18756](https://github.com/apache/nuttx/pull/18756) boards/arm/cxd56xx/spresense: Add ostest, coremark and getprime configs. +* [#18649](https://github.com/apache/nuttx/pull/18649) boards/arm/ht32f491x3: Add PWM support for the HT32F49163 Starter Kit board +* [#18714](https://github.com/apache/nuttx/pull/18714) boards/arm/nrf52/nrf52840-dk|nrf5340-dk: remove nrf52_timer.c +* [#18681](https://github.com/apache/nuttx/pull/18681) boards/arm/rp23xx: add hardware SHA-256 cryptodev support +* [#18823](https://github.com/apache/nuttx/pull/18823) boards/arm/stm32: add nucleo-f412zg ostest and coremark configs. +* [#18766](https://github.com/apache/nuttx/pull/18766) boards/arm/stm32: route nucleo-f412zg console through ST-LINK VCP. +* [#18634](https://github.com/apache/nuttx/pull/18634) boards/arm/stm32/nucleo-c0{71rb|92rc}: fix USART 1 pins +* [#18716](https://github.com/apache/nuttx/pull/18716) boards/arm/stm32/nucleo-c0XX: fix invalid ADC buff size +* [#18569](https://github.com/apache/nuttx/pull/18569) boards/arm/stm32*/: Align ARM STM32 idle stack +* [#18797](https://github.com/apache/nuttx/pull/18797) boards/arm/stm32f1: migrate to new pinmap +* [#18760](https://github.com/apache/nuttx/pull/18760) boards/arm/stm32f103-minimum: Add CAN bring-up, char/socket drivers, and … +* [#18796](https://github.com/apache/nuttx/pull/18796) boards/arm/stm32f2: migrate to new pinmap +* [#18799](https://github.com/apache/nuttx/pull/18799) boards/arm/stm32f3: migrate to new pinmap +* [#18798](https://github.com/apache/nuttx/pull/18798) boards/arm/stm32f4: migrate to new pinmap +* [#18534](https://github.com/apache/nuttx/pull/18534) boards/arm/stm32f4/stm32f4discovery: Add board config to LCD ST7567 and documentation +* [#18846](https://github.com/apache/nuttx/pull/18846) boards/arm/stm32f4/stm32f4discovery: Normalize mt6816 defconfig +* [#18795](https://github.com/apache/nuttx/pull/18795) boards/arm/stm32g4: migrate to new pinmap +* [#18509](https://github.com/apache/nuttx/pull/18509) boards/arm/stm32h7/nucleo-h743zi: Add nxboot bootloader support +* [#18503](https://github.com/apache/nuttx/pull/18503) boards/arm/stm32h7/nucleo-h723zg: Add support for 10BASE-T1S SPI Ethernet, remove untested/unsupported code, improve stability +* [#18850](https://github.com/apache/nuttx/pull/18850) boards/arm/stm32h7/weact-stm32h750: Don't disable compilation optimization +* [#18794](https://github.com/apache/nuttx/pull/18794) boards/arm/stm32l1: migrate to new pinmap +* [#18786](https://github.com/apache/nuttx/pull/18786) boards/arm/stm32l4: migrate to new pinmap +* [#18783](https://github.com/apache/nuttx/pull/18783) boards/arm/stm32l5: migrate to new pinmap +* [#18945](https://github.com/apache/nuttx/pull/18945) boards/arm/stm32n6/nucleo-n657x0-q: Add autoleds and userleds support +* [#18784](https://github.com/apache/nuttx/pull/18784) boards/arm/stm32wb: migrate to new pinmap +ARM64 +* [#19002](https://github.com/apache/nuttx/pull/19002) boards/arm64/bcm2711/raspberrypi-4b: Add NXInit configuration +* [#18499](https://github.com/apache/nuttx/pull/18499) boards/arm64/bcm2711/raspberrypi-4b: Fix GPIO +* [#18861](https://github.com/apache/nuttx/pull/18861) boards/arm64/bcm2711/raspberrypi-4b: Implement SMP support +RISC-V +* [#18625](https://github.com/apache/nuttx/pull/18625) boards/risc-v: increase init stacksize for efuse defconfig on ESP32-C6 +* [#18626](https://github.com/apache/nuttx/pull/18626) boards/risc-v: increase init stack size on esp32h2-devkit:efuse +* [#18596](https://github.com/apache/nuttx/pull/18596) boards/risc-v/k210/maix-bit: Add userled support +* [#18806](https://github.com/apache/nuttx/pull/18806) boards/risc-v/esp32c3-xiao: Add SMARTFS configuration +* [#18533](https://github.com/apache/nuttx/pull/18533) boards/risc-v/esp32c6: remove debug options from defconfig +* [#18943](https://github.com/apache/nuttx/pull/18943) boards/risc-v/esp32p4: Add defconfig for Python on ESP32-P4 +* [#18889](https://github.com/apache/nuttx/pull/18889) boards/risc-v/esp32p4: Remove unnecessary `CONFIG_ESPRESSIF_MERGE_BINS` +* [#18860](https://github.com/apache/nuttx/pull/18860) boards/risc-v/esp32p4-function-ev-board: Normalize configuration +SIM +* [#18732](https://github.com/apache/nuttx/pull/18732) Fix NuttX simulator on macOS +* [#18736](https://github.com/apache/nuttx/pull/18736) boards/sim: Replaced message of the day (MOTD) +* [#18888](https://github.com/apache/nuttx/pull/18888) boards/sim: skip -no-pie on HOST_ARM64 to fix sim:nsh link on aarch64… +* [#18781](https://github.com/apache/nuttx/pull/18781) Prefer tmpfs for /tmp mount in SIM and update documentation +* [#18331](https://github.com/apache/nuttx/pull/18331) sim: Fix linker support and macOS host build issues +* [#18923](https://github.com/apache/nuttx/pull/18923) sim: pass no-pie through gcc driver +* [#18924](https://github.com/apache/nuttx/pull/18924) sim: resolve host symbols eagerly on Linux +* [#18745](https://github.com/apache/nuttx/pull/18745) sim/camera: add AVFoundation backend and multi-cam support +* [#18949](https://github.com/apache/nuttx/pull/18949) sim/keyboard: Translate X11 key codes to NuttX codec +TIVA +* [#18690](https://github.com/apache/nuttx/pull/18690) boards/tiva: change default toolchain for tm4c123g to GNU EABI +X86 +* [#18822](https://github.com/apache/nuttx/pull/18822) boards/x86/qemu-i486: Add support to VGA framebuffer +* [#18834](https://github.com/apache/nuttx/pull/18834) boards/x86/qemu-i486: Fix the removal of qemu_appinit.c +XTENSA +* [#18559](https://github.com/apache/nuttx/pull/18559) boards/xtensa: fix optional item on spiflash config +* [#18852](https://github.com/apache/nuttx/pull/18852) boards/xtensa: Normalize configurations +* [#18925](https://github.com/apache/nuttx/pull/18925) boards/xtensa/esp32: increase MM_REGIONS for psram defconfig +* [#18502](https://github.com/apache/nuttx/pull/18502) boards/xtensa/esp32/Kconfig: Fix bug on ESP32, ESP32-S2 and ESP32-S3 GPIO IRQ +* [#18624](https://github.com/apache/nuttx/pull/18624) boards/xtensa/esp32s3: Fix MAC address byte order in LAN9250 driver +* [#18628](https://github.com/apache/nuttx/pull/18628) boards/xtensa/esp32s3: fix WiFi init by using CONFIG_ESPRESSIF_WIFI +* [#18535](https://github.com/apache/nuttx/pull/18535) boards/xtensa/esp32s3/lckfb-szpi-esp32s3: add sdmmc defconfig +* [#18813](https://github.com/apache/nuttx/pull/18813) boards/xtensa/esp32s3/lckfb-szpi-esp32s3: add vncviewer defconfig and documentation +* [#18650](https://github.com/apache/nuttx/pull/18650) boards/xtensa/esp32s3/lckfb-szpi-esp32s3: enable required IRQ vector table configs for uvc + +File System +File System improvements +* [#18607](https://github.com/apache/nuttx/pull/18607) fs: Add Kernel-level VFS Performance Profiler +* [#18671](https://github.com/apache/nuttx/pull/18671) fs: rpmsgfs_client: process host message as ns_announcement +* [#18697](https://github.com/apache/nuttx/pull/18697) fs/fat: fix incorrect representation of SFN files created on Linux +* [#18782](https://github.com/apache/nuttx/pull/18782) fs/inode: add optional manual FD backtrace control via task group flag +* [#18872](https://github.com/apache/nuttx/pull/18872) fs/Kconfig: Add CONFIG_FS_PERMISSION option +* [#18884](https://github.com/apache/nuttx/pull/18884) fs/mnemofs: Add mnemofs version 1 support. +* [#18506](https://github.com/apache/nuttx/pull/18506) fs/mnemofs: Add portable bit primitives and cleanup hash functions +* [#18830](https://github.com/apache/nuttx/pull/18830) fs/vfs: allow NULL iov_base in KERNEL build with zero-based text +* [#18891](https://github.com/apache/nuttx/pull/18891) fs/vfs: enforce pseudoFS permissions on open() +* [#18876](https://github.com/apache/nuttx/pull/18876) fs/vfs: fix pseudoFS mode reporting +* [#18914](https://github.com/apache/nuttx/pull/18914) fs/vfs: validate chmod and chown callers in inode_chstat() +* [#18746](https://github.com/apache/nuttx/pull/18746) fs/vfs/fs_fstat.c: fix write capability check in proxy_fstat() +* [#18811](https://github.com/apache/nuttx/pull/18811) fs/vfs/fs_lock.c: Close stale locks unconditionally + +Networking +Improvements +* [#18723](https://github.com/apache/nuttx/pull/18723) net: fix multiple bugs across network subsystem +* [#18847](https://github.com/apache/nuttx/pull/18847) net/bluetooth: fix BTPROTO_HCI socket device lookup +* [#18664](https://github.com/apache/nuttx/pull/18664) net/can,udp: fix conn unlock position in callback +* [#18764](https://github.com/apache/nuttx/pull/18764) net/devif: Reorder ipv4_input packet classification. +* [#18843](https://github.com/apache/nuttx/pull/18843) net/icmpv6: Discard Neighbor Discovery packet if optlen is 0 +* [#18866](https://github.com/apache/nuttx/pull/18866) net/icmpv6/icmpv6_input.c: Dont increase d_pktsize from router advertise +* [#18738](https://github.com/apache/nuttx/pull/18738) net/ipforward: Forbid non-forwardable multicast scopes. +* [#18629](https://github.com/apache/nuttx/pull/18629) net/nat: g_nat_lock can be used recursively and nat_lock/unlock should be paired +* [#18812](https://github.com/apache/nuttx/pull/18812) net/nat: Let ICMP echo id zero be a valid NAT id. +* [#18674](https://github.com/apache/nuttx/pull/18674) net/nat: Unlock on outbound NAT entry creation failure. +* [#18670](https://github.com/apache/nuttx/pull/18670) net/netdb/dns: validate nameserver input in dns_add_nameserver +* [#18619](https://github.com/apache/nuttx/pull/18619) net/netdev/netdev_ioctl: log in hex mode for ioctl cmd +* [#18851](https://github.com/apache/nuttx/pull/18851) net/netdev/netdev_txnotify.c: add debug log with interface name +* [#18845](https://github.com/apache/nuttx/pull/18845) net/sixlowpan: Fix sixlowpan_uncompresshdr_hc06() +* [#18751](https://github.com/apache/nuttx/pull/18751) net/tcp: improve tcp_send_txnotify +* [#18689](https://github.com/apache/nuttx/pull/18689) net/udp: fix conn_unlock not called outside conditional block + +Unsorted +* [#18417](https://github.com/apache/nuttx/pull/18417) kinetis/serial: Enable RTS as GPIO for RS485CONTROL +* [#18472](https://github.com/apache/nuttx/pull/18472) wireless/cc1101: Add standard RF IOCTL support +* [#18487](https://github.com/apache/nuttx/pull/18487) serial/uart_rpmsg: Remove redundant CONFIG_RPMSG_UART_CONSOLE macro check +* [#18510](https://github.com/apache/nuttx/pull/18510) wireless/cc1101: migrate to wlioc_rx_hdr_s and add operation modes +* [#18532](https://github.com/apache/nuttx/pull/18532) wireless/cc1101: Make SPI burst and single frequencies configurable +* [#18542](https://github.com/apache/nuttx/pull/18542) video/esp32s3: add GC0308 DVP camera support for lckfb-szpi-esp32s3 +* [#18554](https://github.com/apache/nuttx/pull/18554) ioexpander/iso1i813t: add option to check errors during read +* [#18579](https://github.com/apache/nuttx/pull/18579) nucleo-l476rg: register userleds device driver if CONFIG_USERLED is set +* [#18588](https://github.com/apache/nuttx/pull/18588) add nxscope examples and doc +* [#18593](https://github.com/apache/nuttx/pull/18593) add adcscope example for nucleo-c071rb +* [#18598](https://github.com/apache/nuttx/pull/18598) stm32h5/adc: fix TROVS bit and watchdog threshold register writes +* [#18614](https://github.com/apache/nuttx/pull/18614) xtensa/espressif: Update common-source integration for Xtensa devices +* [#18618](https://github.com/apache/nuttx/pull/18618) serial/uart_rpmsg: Remove redundant CONFIG_RPMSG_UART_CONSOLE macro c… +* [#18622](https://github.com/apache/nuttx/pull/18622) esp_i2s: fix ESP32-S3 I2S RX DMA and add ES7210 4-ch ADC codec driver +* [#18631](https://github.com/apache/nuttx/pull/18631) nucleo-l476rg: register userleds device driver if CONFIG_USERLED is set +* [#18636](https://github.com/apache/nuttx/pull/18636) stm32h5/adc: fix TROVS bit and watchdog threshold register writes +* [#18637](https://github.com/apache/nuttx/pull/18637) nucleo-l476rg: fix ADC driver compilation +* [#18642](https://github.com/apache/nuttx/pull/18642) nucleo-l476rg/stm32_gpio.c: fix compilation error +* [#18654](https://github.com/apache/nuttx/pull/18654) espressif/rmt: replace rmtchar with arch-specific lirc adapter +* [#18667](https://github.com/apache/nuttx/pull/18667) graphics/nxglib: use putarea for lcd copyrectangle when available +* [#18683](https://github.com/apache/nuttx/pull/18683) Fix ARMv6-M/ARMv7-M SVCall register corruption in protected builds, fix `lm3s6965-ek:qemu-protected` boot, and add board documentation. +* [#18684](https://github.com/apache/nuttx/pull/18684) kinetis/dac: Implement basics DAC +* [#18692](https://github.com/apache/nuttx/pull/18692) xtensa/esp32s3: cam driver fixes and GC0308 DVP enhancements +* [#18699](https://github.com/apache/nuttx/pull/18699) arm/imx6: Fix IMX_IRQ definitions +* [#18703](https://github.com/apache/nuttx/pull/18703) xtensa/esp32s3: refactor cam driver to use cam_ll HAL layer +* [#18709](https://github.com/apache/nuttx/pull/18709) espressif: fix Wi-Fi IRQ issue during SPI Flash operations +* [#18718](https://github.com/apache/nuttx/pull/18718) Remove useless references to CONFIG_STM32_TIMx_QECLKOUT +* [#18724](https://github.com/apache/nuttx/pull/18724) video/fb: fix compilation errors +* [#18726](https://github.com/apache/nuttx/pull/18726) nuttx/nx: compilation error occurs +* [#18737](https://github.com/apache/nuttx/pull/18737) video/fb: guarantee fb read-write integrity to prevent display tearing +* [#18754](https://github.com/apache/nuttx/pull/18754) esp32p4: Implements PSRAM support for ESP32-P4 +* [#18755](https://github.com/apache/nuttx/pull/18755) add nxmodbus doc and examples +* [#18779](https://github.com/apache/nuttx/pull/18779) remove legacy pinmap support for stm32h7, stm32f7 and stm32f0l0g0 +* [#18785](https://github.com/apache/nuttx/pull/18785) Introduce dshot ESC protocol upperhalf and imx9 lowerhalf +* [#18788](https://github.com/apache/nuttx/pull/18788) Espressif: Update RMT peripheral testing application to `irtest` +* [#18789](https://github.com/apache/nuttx/pull/18789) cleanup after pinmap migration for stm32l5, stm32wb, stm32l4 +* [#18810](https://github.com/apache/nuttx/pull/18810) syscall: fcntl param3 type to uintptr_t +* [#18815](https://github.com/apache/nuttx/pull/18815) Add USB CDC-ECM Host support +* [#18816](https://github.com/apache/nuttx/pull/18816) clock_settime: don't block when up_rtc_settime is called +* [#18817](https://github.com/apache/nuttx/pull/18817) i.MX95: ARM/CM7: LPI2C/Flexio backport and eDMA SG fix +* [#18853](https://github.com/apache/nuttx/pull/18853) kinetis/pit: Update Kconfig, implement oneshot PIT +* [#18855](https://github.com/apache/nuttx/pull/18855) arm: memcpy: add NEON paths for aligned copies +* [#18908](https://github.com/apache/nuttx/pull/18908) tricore: Add fpu init and fpucmp support. +* [#18937](https://github.com/apache/nuttx/pull/18937) golfish_gpu_fb: clear fb when initialization +* [#18968](https://github.com/apache/nuttx/pull/18968) Fix issues about watchdog timers on ESP32, ESP32-S2 and ESP32-S3 +* [#18988](https://github.com/apache/nuttx/pull/18988) rtc/ptc85263A: Add handling of stop_enable flag. +* [#18999](https://github.com/apache/nuttx/pull/18999) bcm2711/fb: Use physical device resolution OR force resolution +* [#19203](https://github.com/apache/nuttx/pull/19203) syslog: avoid an infinite loop if one channel fails + +Compatibility Concerns +* [#19191](https://github.com/apache/nuttx/pull/19191) !arch: unify all STM32 ports public API +* [#19202](https://github.com/apache/nuttx/pull/19202) !arch/arm/stm32: rename STM32F7/H7 QUADSPI Kconfig symbol to QSPI +* [#18800](https://github.com/apache/nuttx/pull/18800) !arch/arm/stm32: remove STM32_USE_LEGACY_PINMAP +* [#19136](https://github.com/apache/nuttx/pull/19136) !arch/arm/stm32: unify all Kconfig options for STM32 ports. +* [#18492](https://github.com/apache/nuttx/pull/18492) !arch/risc-v/espressif: Update common-source integration for RISC-V devices +* [#18408](https://github.com/apache/nuttx/pull/18408) !boards: Simplify NuttX initialization +* [#18832](https://github.com/apache/nuttx/pull/18832) !boards/boardctl: Remove BOARDIOC_INIT +* [#18864](https://github.com/apache/nuttx/pull/18864) !drivers/pwm: remove PWM_MULTICHAN option +* [#18916](https://github.com/apache/nuttx/pull/18916) !drivers: separate pulse count from PWM driver +* [#18840](https://github.com/apache/nuttx/pull/18840) !sched/clock: drop CONFIG_SYSTEM_TIME64 / CONFIG_HAVE_LONG_LONG / CONFIG_LIBC_LONG_LONG and sclock_t + From 5c8fa78c4e9cadd886e3038084653e5e18982913 Mon Sep 17 00:00:00 2001 From: Michael Rogov Papernov Date: Thu, 25 Jun 2026 10:06:38 +0100 Subject: [PATCH 169/268] ci/testing: Update MemBrowse targets and concurrency condition Update the linker script path in membrowse-targets.json and the cuncurrency condition, to prevent breaking the commit chain Signed-off-by: Michael Rogov Papernov --- .github/membrowse-targets.json | 2 +- .github/workflows/membrowse-report.yml | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/.github/membrowse-targets.json b/.github/membrowse-targets.json index f0a227f4dbb..c105a921969 100644 --- a/.github/membrowse-targets.json +++ b/.github/membrowse-targets.json @@ -3,7 +3,7 @@ "target_name": "stm32-nucleo-f103rb", "board_config": "nucleo-f103rb:nsh", "elf": "nuttx", - "ld": "boards/arm/stm32/nucleo-f103rb/scripts/ld.script", + "ld": "boards/arm/stm32f1/nucleo-f103rb/scripts/ld.script", "map_file": "nuttx.map", "linker_vars": "", "config_overrides": "" diff --git a/.github/workflows/membrowse-report.yml b/.github/workflows/membrowse-report.yml index c18c050a148..de24d212708 100644 --- a/.github/workflows/membrowse-report.yml +++ b/.github/workflows/membrowse-report.yml @@ -10,8 +10,13 @@ on: permissions: contents: read +# Per-PR group so superseded PR pushes cancel; per-SHA on push so master +# commits never share a group. A shared refs/heads/master group lets a burst +# of pushes evict each other while pending (GitHub keeps only one pending run +# per group), leaving a commit with no report and breaking the MemBrowse +# parent chain for every commit that bases on it. concurrency: - group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }} + group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.sha }} cancel-in-progress: ${{ github.event_name == 'pull_request' }} jobs: From b840bf6552bb01ccecb8cc972c176e3faad543a2 Mon Sep 17 00:00:00 2001 From: Catalin Visinescu Date: Wed, 17 Jun 2026 09:50:11 -0400 Subject: [PATCH 170/268] drivers/can/ctucanfd_pci: Fix Malformed CAN Data Msg (address off-by-one) PR https://github.com/apache/nuttx/pull/19139 addresses the issue, but there is one minor problem. In the for loop the element `i+1` is written which means there can still be an overflow by one element (uint32_t or 4 bytes). Addressing here with this PR. Tested locally, builds fine. Signed-off-by: Catalin Visinescu --- drivers/can/ctucanfd_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/can/ctucanfd_pci.c b/drivers/can/ctucanfd_pci.c index 62382c3cbbb..d8287b8fbd8 100644 --- a/drivers/can/ctucanfd_pci.c +++ b/drivers/can/ctucanfd_pci.c @@ -762,7 +762,7 @@ static void ctucanfd_chardev_receive(FAR struct ctucanfd_can_s *priv) /* buff[0] populated the frame->fmt.rwcnt. Check before use. */ - if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0])) + if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0]) - 1) { canerr("ERROR: CAN read/write count is too large. Dropped\n"); return; @@ -1259,7 +1259,7 @@ static FAR netpkt_t *ctucanfd_sock_recv(FAR struct netdev_lowerhalf_s *dev) /* buff[0] populated the frame->fmt.rwcnt. Check before use. */ - if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0])) + if (frame->fmt.rwcnt > sizeof(buff) / sizeof(buff[0]) - 1) { canerr("ERROR: CAN read/write count is too large. Dropped\n"); return NULL; From 21def97623a4f45bfef0c976bf769be3581c5ed0 Mon Sep 17 00:00:00 2001 From: shichunma Date: Fri, 12 Jun 2026 10:57:53 +0800 Subject: [PATCH 171/268] net/devif: harden devif_conn_event() against list mutation devif_conn_event() saves list->nxtconn before invoking the current callback. If the callback mutates its callback list, the saved local successor may no longer match the post-callback list topology. Align devif_conn_event() with devif_dev_event(): protect the current callback with DEVIF_CB_DONT_FREE, refresh next after the callback returns, and defer freeing the current node until iteration is safe. Signed-off-by: shichunma --- net/devif/devif_callback.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/net/devif/devif_callback.c b/net/devif/devif_callback.c index 2f58ea6d32c..d59ff7b9b89 100644 --- a/net/devif/devif_callback.c +++ b/net/devif/devif_callback.c @@ -455,12 +455,26 @@ uint32_t devif_conn_event(FAR struct net_driver_s *dev, uint32_t flags, if (list->event != NULL && devif_event_trigger(flags, list->flags)) { + list->free_flags |= DEVIF_CB_DONT_FREE; + /* Yes.. perform the callback. Actions perform by the callback * may delete the current list entry or add a new list entry to * beginning of the list (which will be ignored on this pass) */ flags = list->event(dev, list->priv, flags); + list->free_flags &= ~DEVIF_CB_DONT_FREE; + + /* update the next callback to prevent previously recorded the + * next callback from being deleted + */ + + next = list->nxtconn; + if ((list->free_flags & DEVIF_CB_PEND_FREE) != 0) + { + list->free_flags &= ~DEVIF_CB_PEND_FREE; + devif_callback_free(dev, list, NULL, NULL); + } } /* Set up for the next time through the loop */ From 5feb1c4b8b3fda0bfeccbf49a2be8865169cdfd4 Mon Sep 17 00:00:00 2001 From: Carlos Sanchez Date: Wed, 24 Jun 2026 10:46:43 +0200 Subject: [PATCH 172/268] arch/arm: fix DMA transfers with sizes smaller than 4 bytes. When the buffer to send has a size not multiple of 4 bytes, 4-byte words are sent correctly, but when the code reaches the section to send the remaining bytes (1, 2 or 3) it was taking the remaining byte count as origin of the copy, instead of the buffer (as it should). This commit fixes it to correctly copy from the buffer pointer. Signed-off-by: Carlos Sanchez --- arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c | 2 +- arch/arm/src/stm32f7/stm32_sdmmc.c | 2 +- arch/arm/src/stm32h7/stm32_sdmmc.c | 2 +- arch/arm/src/stm32l4/stm32l4_sdmmc.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c index 3387e111c4e..460ce937c48 100644 --- a/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c +++ b/arch/arm/src/common/stm32/stm32_sdio_m3m4_v1.c @@ -1087,7 +1087,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * padding with zero as necessary to extend to a full word. */ - uint8_t *ptr = (uint8_t *)priv->remaining; + uint8_t *ptr = (uint8_t *)priv->buffer; int i; data.w = 0; diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index d82877095a1..772e62572bf 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -1313,7 +1313,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * padding with zero as necessary to extend to a full word. */ - uint8_t *ptr = (uint8_t *)priv->remaining; + uint8_t *ptr = (uint8_t *)priv->buffer; int i; data.w = 0; diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index 2aca3035cd2..0e713eadb07 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -1232,7 +1232,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * padding with zero as necessary to extend to a full word. */ - uint8_t *ptr = (uint8_t *)priv->remaining; + uint8_t *ptr = (uint8_t *)priv->buffer; int i; data.w = 0; diff --git a/arch/arm/src/stm32l4/stm32l4_sdmmc.c b/arch/arm/src/stm32l4/stm32l4_sdmmc.c index bea2a35c088..3f1aaef30c8 100644 --- a/arch/arm/src/stm32l4/stm32l4_sdmmc.c +++ b/arch/arm/src/stm32l4/stm32l4_sdmmc.c @@ -1177,7 +1177,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * padding with zero as necessary to extend to a full word. */ - uint8_t *ptr = (uint8_t *)priv->remaining; + uint8_t *ptr = (uint8_t *)priv->buffer; int i; data.w = 0; From f5e3bb24595b78c5e329d13b1ad559a294ed3ef9 Mon Sep 17 00:00:00 2001 From: Jorge Guzman Date: Thu, 25 Jun 2026 22:34:09 -0300 Subject: [PATCH 173/268] boards/esp32p4: add support to M5Stack Tab5 board This initial port supports NSH and the I2C0 bus; all board pins are documented for future drivers. Signed-off-by: Jorge Guzman --- .../esp32p4-tab5/esp32p4-tab5-m5stack-1.png | Bin 0 -> 223094 bytes .../esp32p4-tab5/esp32p4-tab5-m5stack-2.png | Bin 0 -> 235880 bytes .../esp32p4/boards/esp32p4-tab5/index.rst | 165 ++++++++++++++++++ boards/Kconfig | 11 ++ .../esp32p4/esp32p4-tab5/CMakeLists.txt | 23 +++ boards/risc-v/esp32p4/esp32p4-tab5/Kconfig | 8 + .../esp32p4-tab5/configs/nsh/defconfig | 57 ++++++ .../esp32p4/esp32p4-tab5/include/board.h | 116 ++++++++++++ .../esp32p4/esp32p4-tab5/scripts/Make.defs | 64 +++++++ .../esp32p4/esp32p4-tab5/src/CMakeLists.txt | 54 ++++++ .../risc-v/esp32p4/esp32p4-tab5/src/Make.defs | 35 ++++ .../esp32p4/esp32p4-tab5/src/esp32p4-tab5.h | 60 +++++++ .../esp32p4/esp32p4-tab5/src/esp32p4_boot.c | 91 ++++++++++ .../esp32p4-tab5/src/esp32p4_bringup.c | 92 ++++++++++ .../esp32p4/esp32p4-tab5/src/esp32p4_reset.c | 83 +++++++++ 15 files changed, 859 insertions(+) create mode 100644 Documentation/platforms/risc-v/esp32p4/boards/esp32p4-tab5/esp32p4-tab5-m5stack-1.png create mode 100644 Documentation/platforms/risc-v/esp32p4/boards/esp32p4-tab5/esp32p4-tab5-m5stack-2.png create mode 100644 Documentation/platforms/risc-v/esp32p4/boards/esp32p4-tab5/index.rst create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/CMakeLists.txt create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/Kconfig create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/configs/nsh/defconfig create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/include/board.h create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/scripts/Make.defs create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/CMakeLists.txt create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/Make.defs create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/esp32p4-tab5.h create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/esp32p4_boot.c create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/esp32p4_bringup.c create mode 100644 boards/risc-v/esp32p4/esp32p4-tab5/src/esp32p4_reset.c diff --git a/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-tab5/esp32p4-tab5-m5stack-1.png b/Documentation/platforms/risc-v/esp32p4/boards/esp32p4-tab5/esp32p4-tab5-m5stack-1.png new file mode 100644 index 0000000000000000000000000000000000000000..afd92daa17d97d851e65c5ed2832c217730ca59d GIT binary patch literal 223094 zcmXt91yodBwDw2Dp%m$q8UbNQkp^k$?yjL3x=WOhE*Tm`1f&^akQlm$6mV#yK}tYM z>RsMjkF{p0$hzEn&pCU4wWBrE-V)+b<2`urfKX9ER_noo|JH!d4-gLUon_5J9^emb zPiaLR5bzZQviS)7o61Yhz)RcJ*2~w@1Ny)Y=IR3F^tASXLSdfvu3m=^+a-V>;=KPM z84swXmxC*eLC3)b`as9tn}P2&gOWFlfscnzfPt4+T!@8BsCoFNmaqqzMW#8Tq~mPJsRu#xy-@nfh7?_*^LKF#%s;!b_JMn% zndJtxrZ!*X9Qd_}ii*AxJUlGHN7p(B{omJ;;MeoO$N%?tiGvHPy|t6)mh%G0ebGGN zn@iLiH%tG~=O?mDe`PKxZpqPo$24A z^I$C31BF>qR`zqEyO1tmMQKnN1l>L~vx3}kac1q#k;C$@0+HQXG4uT%2-HWYF9P1}Fj|&c3`cL{Jyw}NC zfDk3clDd+nZ?-b=mVRR(nfVhMN*#~$phydMl0RC$kbscTeHNO2)Y5*{qN1w$ELzrR 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